// hps_sdram_mm_interconnect_1.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 15.1 193

`timescale 1 ps / 1 ps
module hps_sdram_mm_interconnect_1 (
		input  wire        p0_avl_clk_clk,                               //                             p0_avl_clk.clk
		input  wire        cpu_inst_reset_n_reset_bridge_in_reset_reset, // cpu_inst_reset_n_reset_bridge_in_reset.reset
		input  wire [19:0] cpu_inst_data_master_address,                 //                   cpu_inst_data_master.address
		output wire        cpu_inst_data_master_waitrequest,             //                                       .waitrequest
		input  wire [3:0]  cpu_inst_data_master_byteenable,              //                                       .byteenable
		input  wire        cpu_inst_data_master_read,                    //                                       .read
		output wire [31:0] cpu_inst_data_master_readdata,                //                                       .readdata
		input  wire        cpu_inst_data_master_write,                   //                                       .write
		input  wire [31:0] cpu_inst_data_master_writedata,               //                                       .writedata
		input  wire [16:0] cpu_inst_instruction_master_address,          //            cpu_inst_instruction_master.address
		output wire        cpu_inst_instruction_master_waitrequest,      //                                       .waitrequest
		input  wire        cpu_inst_instruction_master_read,             //                                       .read
		output wire [31:0] cpu_inst_instruction_master_readdata,         //                                       .readdata
		output wire [15:0] avl2apb_avalon_slave_address,                 //                   avl2apb_avalon_slave.address
		output wire        avl2apb_avalon_slave_write,                   //                                       .write
		output wire        avl2apb_avalon_slave_read,                    //                                       .read
		input  wire [31:0] avl2apb_avalon_slave_readdata,                //                                       .readdata
		output wire [31:0] avl2apb_avalon_slave_writedata,               //                                       .writedata
		output wire [3:0]  avl2apb_avalon_slave_byteenable,              //                                       .byteenable
		input  wire        avl2apb_avalon_slave_waitrequest,             //                                       .waitrequest
		output wire [12:0] sequencer_mem_s1_address,                     //                       sequencer_mem_s1.address
		output wire        sequencer_mem_s1_write,                       //                                       .write
		input  wire [31:0] sequencer_mem_s1_readdata,                    //                                       .readdata
		output wire [31:0] sequencer_mem_s1_writedata,                   //                                       .writedata
		output wire [3:0]  sequencer_mem_s1_byteenable,                  //                                       .byteenable
		output wire        sequencer_mem_s1_chipselect                   //                                       .chipselect
	);

	wire         cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest;          // cpu_inst_data_master_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest
	wire  [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_readdata;             // cpu_inst_data_master_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess;          // cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_agent:av_debugaccess
	wire  [19:0] cpu_inst_data_master_translator_avalon_universal_master_0_address;              // cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_agent:av_address
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_read;                 // cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_agent:av_read
	wire   [3:0] cpu_inst_data_master_translator_avalon_universal_master_0_byteenable;           // cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_agent:av_byteenable
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid;        // cpu_inst_data_master_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_lock;                 // cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_agent:av_lock
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_write;                // cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_agent:av_write
	wire  [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_writedata;            // cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_agent:av_writedata
	wire   [2:0] cpu_inst_data_master_translator_avalon_universal_master_0_burstcount;           // cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_agent:av_burstcount
	wire         rsp_mux_src_valid;                                                              // rsp_mux:src_valid -> cpu_inst_data_master_agent:rp_valid
	wire  [91:0] rsp_mux_src_data;                                                               // rsp_mux:src_data -> cpu_inst_data_master_agent:rp_data
	wire         rsp_mux_src_ready;                                                              // cpu_inst_data_master_agent:rp_ready -> rsp_mux:src_ready
	wire   [1:0] rsp_mux_src_channel;                                                            // rsp_mux:src_channel -> cpu_inst_data_master_agent:rp_channel
	wire         rsp_mux_src_startofpacket;                                                      // rsp_mux:src_startofpacket -> cpu_inst_data_master_agent:rp_startofpacket
	wire         rsp_mux_src_endofpacket;                                                        // rsp_mux:src_endofpacket -> cpu_inst_data_master_agent:rp_endofpacket
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest;   // cpu_inst_instruction_master_agent:av_waitrequest -> cpu_inst_instruction_master_translator:uav_waitrequest
	wire  [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata;      // cpu_inst_instruction_master_agent:av_readdata -> cpu_inst_instruction_master_translator:uav_readdata
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess;   // cpu_inst_instruction_master_translator:uav_debugaccess -> cpu_inst_instruction_master_agent:av_debugaccess
	wire  [19:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_address;       // cpu_inst_instruction_master_translator:uav_address -> cpu_inst_instruction_master_agent:av_address
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_read;          // cpu_inst_instruction_master_translator:uav_read -> cpu_inst_instruction_master_agent:av_read
	wire   [3:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable;    // cpu_inst_instruction_master_translator:uav_byteenable -> cpu_inst_instruction_master_agent:av_byteenable
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_instruction_master_agent:av_readdatavalid -> cpu_inst_instruction_master_translator:uav_readdatavalid
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_lock;          // cpu_inst_instruction_master_translator:uav_lock -> cpu_inst_instruction_master_agent:av_lock
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_write;         // cpu_inst_instruction_master_translator:uav_write -> cpu_inst_instruction_master_agent:av_write
	wire  [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata;     // cpu_inst_instruction_master_translator:uav_writedata -> cpu_inst_instruction_master_agent:av_writedata
	wire   [2:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount;    // cpu_inst_instruction_master_translator:uav_burstcount -> cpu_inst_instruction_master_agent:av_burstcount
	wire         rsp_mux_001_src_valid;                                                          // rsp_mux_001:src_valid -> cpu_inst_instruction_master_agent:rp_valid
	wire  [91:0] rsp_mux_001_src_data;                                                           // rsp_mux_001:src_data -> cpu_inst_instruction_master_agent:rp_data
	wire         rsp_mux_001_src_ready;                                                          // cpu_inst_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
	wire   [1:0] rsp_mux_001_src_channel;                                                        // rsp_mux_001:src_channel -> cpu_inst_instruction_master_agent:rp_channel
	wire         rsp_mux_001_src_startofpacket;                                                  // rsp_mux_001:src_startofpacket -> cpu_inst_instruction_master_agent:rp_startofpacket
	wire         rsp_mux_001_src_endofpacket;                                                    // rsp_mux_001:src_endofpacket -> cpu_inst_instruction_master_agent:rp_endofpacket
	wire  [31:0] sequencer_mem_s1_agent_m0_readdata;                                             // sequencer_mem_s1_translator:uav_readdata -> sequencer_mem_s1_agent:m0_readdata
	wire         sequencer_mem_s1_agent_m0_waitrequest;                                          // sequencer_mem_s1_translator:uav_waitrequest -> sequencer_mem_s1_agent:m0_waitrequest
	wire         sequencer_mem_s1_agent_m0_debugaccess;                                          // sequencer_mem_s1_agent:m0_debugaccess -> sequencer_mem_s1_translator:uav_debugaccess
	wire  [19:0] sequencer_mem_s1_agent_m0_address;                                              // sequencer_mem_s1_agent:m0_address -> sequencer_mem_s1_translator:uav_address
	wire   [3:0] sequencer_mem_s1_agent_m0_byteenable;                                           // sequencer_mem_s1_agent:m0_byteenable -> sequencer_mem_s1_translator:uav_byteenable
	wire         sequencer_mem_s1_agent_m0_read;                                                 // sequencer_mem_s1_agent:m0_read -> sequencer_mem_s1_translator:uav_read
	wire         sequencer_mem_s1_agent_m0_readdatavalid;                                        // sequencer_mem_s1_translator:uav_readdatavalid -> sequencer_mem_s1_agent:m0_readdatavalid
	wire         sequencer_mem_s1_agent_m0_lock;                                                 // sequencer_mem_s1_agent:m0_lock -> sequencer_mem_s1_translator:uav_lock
	wire  [31:0] sequencer_mem_s1_agent_m0_writedata;                                            // sequencer_mem_s1_agent:m0_writedata -> sequencer_mem_s1_translator:uav_writedata
	wire         sequencer_mem_s1_agent_m0_write;                                                // sequencer_mem_s1_agent:m0_write -> sequencer_mem_s1_translator:uav_write
	wire   [2:0] sequencer_mem_s1_agent_m0_burstcount;                                           // sequencer_mem_s1_agent:m0_burstcount -> sequencer_mem_s1_translator:uav_burstcount
	wire         sequencer_mem_s1_agent_rf_source_valid;                                         // sequencer_mem_s1_agent:rf_source_valid -> sequencer_mem_s1_agent_rsp_fifo:in_valid
	wire  [92:0] sequencer_mem_s1_agent_rf_source_data;                                          // sequencer_mem_s1_agent:rf_source_data -> sequencer_mem_s1_agent_rsp_fifo:in_data
	wire         sequencer_mem_s1_agent_rf_source_ready;                                         // sequencer_mem_s1_agent_rsp_fifo:in_ready -> sequencer_mem_s1_agent:rf_source_ready
	wire         sequencer_mem_s1_agent_rf_source_startofpacket;                                 // sequencer_mem_s1_agent:rf_source_startofpacket -> sequencer_mem_s1_agent_rsp_fifo:in_startofpacket
	wire         sequencer_mem_s1_agent_rf_source_endofpacket;                                   // sequencer_mem_s1_agent:rf_source_endofpacket -> sequencer_mem_s1_agent_rsp_fifo:in_endofpacket
	wire         sequencer_mem_s1_agent_rsp_fifo_out_valid;                                      // sequencer_mem_s1_agent_rsp_fifo:out_valid -> sequencer_mem_s1_agent:rf_sink_valid
	wire  [92:0] sequencer_mem_s1_agent_rsp_fifo_out_data;                                       // sequencer_mem_s1_agent_rsp_fifo:out_data -> sequencer_mem_s1_agent:rf_sink_data
	wire         sequencer_mem_s1_agent_rsp_fifo_out_ready;                                      // sequencer_mem_s1_agent:rf_sink_ready -> sequencer_mem_s1_agent_rsp_fifo:out_ready
	wire         sequencer_mem_s1_agent_rsp_fifo_out_startofpacket;                              // sequencer_mem_s1_agent_rsp_fifo:out_startofpacket -> sequencer_mem_s1_agent:rf_sink_startofpacket
	wire         sequencer_mem_s1_agent_rsp_fifo_out_endofpacket;                                // sequencer_mem_s1_agent_rsp_fifo:out_endofpacket -> sequencer_mem_s1_agent:rf_sink_endofpacket
	wire         cmd_mux_src_valid;                                                              // cmd_mux:src_valid -> sequencer_mem_s1_agent:cp_valid
	wire  [91:0] cmd_mux_src_data;                                                               // cmd_mux:src_data -> sequencer_mem_s1_agent:cp_data
	wire         cmd_mux_src_ready;                                                              // sequencer_mem_s1_agent:cp_ready -> cmd_mux:src_ready
	wire   [1:0] cmd_mux_src_channel;                                                            // cmd_mux:src_channel -> sequencer_mem_s1_agent:cp_channel
	wire         cmd_mux_src_startofpacket;                                                      // cmd_mux:src_startofpacket -> sequencer_mem_s1_agent:cp_startofpacket
	wire         cmd_mux_src_endofpacket;                                                        // cmd_mux:src_endofpacket -> sequencer_mem_s1_agent:cp_endofpacket
	wire  [31:0] avl2apb_avalon_slave_agent_m0_readdata;                                         // avl2apb_avalon_slave_translator:uav_readdata -> avl2apb_avalon_slave_agent:m0_readdata
	wire         avl2apb_avalon_slave_agent_m0_waitrequest;                                      // avl2apb_avalon_slave_translator:uav_waitrequest -> avl2apb_avalon_slave_agent:m0_waitrequest
	wire         avl2apb_avalon_slave_agent_m0_debugaccess;                                      // avl2apb_avalon_slave_agent:m0_debugaccess -> avl2apb_avalon_slave_translator:uav_debugaccess
	wire  [19:0] avl2apb_avalon_slave_agent_m0_address;                                          // avl2apb_avalon_slave_agent:m0_address -> avl2apb_avalon_slave_translator:uav_address
	wire   [3:0] avl2apb_avalon_slave_agent_m0_byteenable;                                       // avl2apb_avalon_slave_agent:m0_byteenable -> avl2apb_avalon_slave_translator:uav_byteenable
	wire         avl2apb_avalon_slave_agent_m0_read;                                             // avl2apb_avalon_slave_agent:m0_read -> avl2apb_avalon_slave_translator:uav_read
	wire         avl2apb_avalon_slave_agent_m0_readdatavalid;                                    // avl2apb_avalon_slave_translator:uav_readdatavalid -> avl2apb_avalon_slave_agent:m0_readdatavalid
	wire         avl2apb_avalon_slave_agent_m0_lock;                                             // avl2apb_avalon_slave_agent:m0_lock -> avl2apb_avalon_slave_translator:uav_lock
	wire  [31:0] avl2apb_avalon_slave_agent_m0_writedata;                                        // avl2apb_avalon_slave_agent:m0_writedata -> avl2apb_avalon_slave_translator:uav_writedata
	wire         avl2apb_avalon_slave_agent_m0_write;                                            // avl2apb_avalon_slave_agent:m0_write -> avl2apb_avalon_slave_translator:uav_write
	wire   [2:0] avl2apb_avalon_slave_agent_m0_burstcount;                                       // avl2apb_avalon_slave_agent:m0_burstcount -> avl2apb_avalon_slave_translator:uav_burstcount
	wire         avl2apb_avalon_slave_agent_rf_source_valid;                                     // avl2apb_avalon_slave_agent:rf_source_valid -> avl2apb_avalon_slave_agent_rsp_fifo:in_valid
	wire  [92:0] avl2apb_avalon_slave_agent_rf_source_data;                                      // avl2apb_avalon_slave_agent:rf_source_data -> avl2apb_avalon_slave_agent_rsp_fifo:in_data
	wire         avl2apb_avalon_slave_agent_rf_source_ready;                                     // avl2apb_avalon_slave_agent_rsp_fifo:in_ready -> avl2apb_avalon_slave_agent:rf_source_ready
	wire         avl2apb_avalon_slave_agent_rf_source_startofpacket;                             // avl2apb_avalon_slave_agent:rf_source_startofpacket -> avl2apb_avalon_slave_agent_rsp_fifo:in_startofpacket
	wire         avl2apb_avalon_slave_agent_rf_source_endofpacket;                               // avl2apb_avalon_slave_agent:rf_source_endofpacket -> avl2apb_avalon_slave_agent_rsp_fifo:in_endofpacket
	wire         avl2apb_avalon_slave_agent_rsp_fifo_out_valid;                                  // avl2apb_avalon_slave_agent_rsp_fifo:out_valid -> avl2apb_avalon_slave_agent:rf_sink_valid
	wire  [92:0] avl2apb_avalon_slave_agent_rsp_fifo_out_data;                                   // avl2apb_avalon_slave_agent_rsp_fifo:out_data -> avl2apb_avalon_slave_agent:rf_sink_data
	wire         avl2apb_avalon_slave_agent_rsp_fifo_out_ready;                                  // avl2apb_avalon_slave_agent:rf_sink_ready -> avl2apb_avalon_slave_agent_rsp_fifo:out_ready
	wire         avl2apb_avalon_slave_agent_rsp_fifo_out_startofpacket;                          // avl2apb_avalon_slave_agent_rsp_fifo:out_startofpacket -> avl2apb_avalon_slave_agent:rf_sink_startofpacket
	wire         avl2apb_avalon_slave_agent_rsp_fifo_out_endofpacket;                            // avl2apb_avalon_slave_agent_rsp_fifo:out_endofpacket -> avl2apb_avalon_slave_agent:rf_sink_endofpacket
	wire         cpu_inst_data_master_agent_cp_valid;                                            // cpu_inst_data_master_agent:cp_valid -> router:sink_valid
	wire  [91:0] cpu_inst_data_master_agent_cp_data;                                             // cpu_inst_data_master_agent:cp_data -> router:sink_data
	wire         cpu_inst_data_master_agent_cp_ready;                                            // router:sink_ready -> cpu_inst_data_master_agent:cp_ready
	wire         cpu_inst_data_master_agent_cp_startofpacket;                                    // cpu_inst_data_master_agent:cp_startofpacket -> router:sink_startofpacket
	wire         cpu_inst_data_master_agent_cp_endofpacket;                                      // cpu_inst_data_master_agent:cp_endofpacket -> router:sink_endofpacket
	wire         router_src_valid;                                                               // router:src_valid -> cmd_demux:sink_valid
	wire  [91:0] router_src_data;                                                                // router:src_data -> cmd_demux:sink_data
	wire         router_src_ready;                                                               // cmd_demux:sink_ready -> router:src_ready
	wire   [1:0] router_src_channel;                                                             // router:src_channel -> cmd_demux:sink_channel
	wire         router_src_startofpacket;                                                       // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire         router_src_endofpacket;                                                         // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire         cpu_inst_instruction_master_agent_cp_valid;                                     // cpu_inst_instruction_master_agent:cp_valid -> router_001:sink_valid
	wire  [91:0] cpu_inst_instruction_master_agent_cp_data;                                      // cpu_inst_instruction_master_agent:cp_data -> router_001:sink_data
	wire         cpu_inst_instruction_master_agent_cp_ready;                                     // router_001:sink_ready -> cpu_inst_instruction_master_agent:cp_ready
	wire         cpu_inst_instruction_master_agent_cp_startofpacket;                             // cpu_inst_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
	wire         cpu_inst_instruction_master_agent_cp_endofpacket;                               // cpu_inst_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
	wire         router_001_src_valid;                                                           // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [91:0] router_001_src_data;                                                            // router_001:src_data -> cmd_demux_001:sink_data
	wire         router_001_src_ready;                                                           // cmd_demux_001:sink_ready -> router_001:src_ready
	wire   [1:0] router_001_src_channel;                                                         // router_001:src_channel -> cmd_demux_001:sink_channel
	wire         router_001_src_startofpacket;                                                   // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire         router_001_src_endofpacket;                                                     // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire         sequencer_mem_s1_agent_rp_valid;                                                // sequencer_mem_s1_agent:rp_valid -> router_002:sink_valid
	wire  [91:0] sequencer_mem_s1_agent_rp_data;                                                 // sequencer_mem_s1_agent:rp_data -> router_002:sink_data
	wire         sequencer_mem_s1_agent_rp_ready;                                                // router_002:sink_ready -> sequencer_mem_s1_agent:rp_ready
	wire         sequencer_mem_s1_agent_rp_startofpacket;                                        // sequencer_mem_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
	wire         sequencer_mem_s1_agent_rp_endofpacket;                                          // sequencer_mem_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
	wire         router_002_src_valid;                                                           // router_002:src_valid -> rsp_demux:sink_valid
	wire  [91:0] router_002_src_data;                                                            // router_002:src_data -> rsp_demux:sink_data
	wire         router_002_src_ready;                                                           // rsp_demux:sink_ready -> router_002:src_ready
	wire   [1:0] router_002_src_channel;                                                         // router_002:src_channel -> rsp_demux:sink_channel
	wire         router_002_src_startofpacket;                                                   // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
	wire         router_002_src_endofpacket;                                                     // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
	wire         avl2apb_avalon_slave_agent_rp_valid;                                            // avl2apb_avalon_slave_agent:rp_valid -> router_003:sink_valid
	wire  [91:0] avl2apb_avalon_slave_agent_rp_data;                                             // avl2apb_avalon_slave_agent:rp_data -> router_003:sink_data
	wire         avl2apb_avalon_slave_agent_rp_ready;                                            // router_003:sink_ready -> avl2apb_avalon_slave_agent:rp_ready
	wire         avl2apb_avalon_slave_agent_rp_startofpacket;                                    // avl2apb_avalon_slave_agent:rp_startofpacket -> router_003:sink_startofpacket
	wire         avl2apb_avalon_slave_agent_rp_endofpacket;                                      // avl2apb_avalon_slave_agent:rp_endofpacket -> router_003:sink_endofpacket
	wire         router_003_src_valid;                                                           // router_003:src_valid -> rsp_demux_001:sink_valid
	wire  [91:0] router_003_src_data;                                                            // router_003:src_data -> rsp_demux_001:sink_data
	wire         router_003_src_ready;                                                           // rsp_demux_001:sink_ready -> router_003:src_ready
	wire   [1:0] router_003_src_channel;                                                         // router_003:src_channel -> rsp_demux_001:sink_channel
	wire         router_003_src_startofpacket;                                                   // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire         router_003_src_endofpacket;                                                     // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire         cmd_mux_001_src_valid;                                                          // cmd_mux_001:src_valid -> avl2apb_avalon_slave_burst_adapter:sink0_valid
	wire  [91:0] cmd_mux_001_src_data;                                                           // cmd_mux_001:src_data -> avl2apb_avalon_slave_burst_adapter:sink0_data
	wire         cmd_mux_001_src_ready;                                                          // avl2apb_avalon_slave_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
	wire   [1:0] cmd_mux_001_src_channel;                                                        // cmd_mux_001:src_channel -> avl2apb_avalon_slave_burst_adapter:sink0_channel
	wire         cmd_mux_001_src_startofpacket;                                                  // cmd_mux_001:src_startofpacket -> avl2apb_avalon_slave_burst_adapter:sink0_startofpacket
	wire         cmd_mux_001_src_endofpacket;                                                    // cmd_mux_001:src_endofpacket -> avl2apb_avalon_slave_burst_adapter:sink0_endofpacket
	wire         avl2apb_avalon_slave_burst_adapter_source0_valid;                               // avl2apb_avalon_slave_burst_adapter:source0_valid -> avl2apb_avalon_slave_agent:cp_valid
	wire  [91:0] avl2apb_avalon_slave_burst_adapter_source0_data;                                // avl2apb_avalon_slave_burst_adapter:source0_data -> avl2apb_avalon_slave_agent:cp_data
	wire         avl2apb_avalon_slave_burst_adapter_source0_ready;                               // avl2apb_avalon_slave_agent:cp_ready -> avl2apb_avalon_slave_burst_adapter:source0_ready
	wire   [1:0] avl2apb_avalon_slave_burst_adapter_source0_channel;                             // avl2apb_avalon_slave_burst_adapter:source0_channel -> avl2apb_avalon_slave_agent:cp_channel
	wire         avl2apb_avalon_slave_burst_adapter_source0_startofpacket;                       // avl2apb_avalon_slave_burst_adapter:source0_startofpacket -> avl2apb_avalon_slave_agent:cp_startofpacket
	wire         avl2apb_avalon_slave_burst_adapter_source0_endofpacket;                         // avl2apb_avalon_slave_burst_adapter:source0_endofpacket -> avl2apb_avalon_slave_agent:cp_endofpacket
	wire         cmd_demux_src0_valid;                                                           // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [91:0] cmd_demux_src0_data;                                                            // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire         cmd_demux_src0_ready;                                                           // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire   [1:0] cmd_demux_src0_channel;                                                         // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire         cmd_demux_src0_startofpacket;                                                   // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire         cmd_demux_src0_endofpacket;                                                     // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire         cmd_demux_src1_valid;                                                           // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	wire  [91:0] cmd_demux_src1_data;                                                            // cmd_demux:src1_data -> cmd_mux_001:sink0_data
	wire         cmd_demux_src1_ready;                                                           // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	wire   [1:0] cmd_demux_src1_channel;                                                         // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	wire         cmd_demux_src1_startofpacket;                                                   // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire         cmd_demux_src1_endofpacket;                                                     // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire         cmd_demux_001_src0_valid;                                                       // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
	wire  [91:0] cmd_demux_001_src0_data;                                                        // cmd_demux_001:src0_data -> cmd_mux:sink1_data
	wire         cmd_demux_001_src0_ready;                                                       // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
	wire   [1:0] cmd_demux_001_src0_channel;                                                     // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
	wire         cmd_demux_001_src0_startofpacket;                                               // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
	wire         cmd_demux_001_src0_endofpacket;                                                 // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
	wire         rsp_demux_src0_valid;                                                           // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [91:0] rsp_demux_src0_data;                                                            // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire         rsp_demux_src0_ready;                                                           // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire   [1:0] rsp_demux_src0_channel;                                                         // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire         rsp_demux_src0_startofpacket;                                                   // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire         rsp_demux_src0_endofpacket;                                                     // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire         rsp_demux_src1_valid;                                                           // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
	wire  [91:0] rsp_demux_src1_data;                                                            // rsp_demux:src1_data -> rsp_mux_001:sink0_data
	wire         rsp_demux_src1_ready;                                                           // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
	wire   [1:0] rsp_demux_src1_channel;                                                         // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
	wire         rsp_demux_src1_startofpacket;                                                   // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire         rsp_demux_src1_endofpacket;                                                     // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire         rsp_demux_001_src0_valid;                                                       // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	wire  [91:0] rsp_demux_001_src0_data;                                                        // rsp_demux_001:src0_data -> rsp_mux:sink1_data
	wire         rsp_demux_001_src0_ready;                                                       // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	wire   [1:0] rsp_demux_001_src0_channel;                                                     // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	wire         rsp_demux_001_src0_startofpacket;                                               // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	wire         rsp_demux_001_src0_endofpacket;                                                 // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	wire         sequencer_mem_s1_agent_rdata_fifo_src_valid;                                    // sequencer_mem_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
	wire  [33:0] sequencer_mem_s1_agent_rdata_fifo_src_data;                                     // sequencer_mem_s1_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
	wire         sequencer_mem_s1_agent_rdata_fifo_src_ready;                                    // avalon_st_adapter:in_0_ready -> sequencer_mem_s1_agent:rdata_fifo_src_ready
	wire         avalon_st_adapter_out_0_valid;                                                  // avalon_st_adapter:out_0_valid -> sequencer_mem_s1_agent:rdata_fifo_sink_valid
	wire  [33:0] avalon_st_adapter_out_0_data;                                                   // avalon_st_adapter:out_0_data -> sequencer_mem_s1_agent:rdata_fifo_sink_data
	wire         avalon_st_adapter_out_0_ready;                                                  // sequencer_mem_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire   [0:0] avalon_st_adapter_out_0_error;                                                  // avalon_st_adapter:out_0_error -> sequencer_mem_s1_agent:rdata_fifo_sink_error
	wire         avl2apb_avalon_slave_agent_rdata_fifo_src_valid;                                // avl2apb_avalon_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
	wire  [33:0] avl2apb_avalon_slave_agent_rdata_fifo_src_data;                                 // avl2apb_avalon_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
	wire         avl2apb_avalon_slave_agent_rdata_fifo_src_ready;                                // avalon_st_adapter_001:in_0_ready -> avl2apb_avalon_slave_agent:rdata_fifo_src_ready
	wire         avalon_st_adapter_001_out_0_valid;                                              // avalon_st_adapter_001:out_0_valid -> avl2apb_avalon_slave_agent:rdata_fifo_sink_valid
	wire  [33:0] avalon_st_adapter_001_out_0_data;                                               // avalon_st_adapter_001:out_0_data -> avl2apb_avalon_slave_agent:rdata_fifo_sink_data
	wire         avalon_st_adapter_001_out_0_ready;                                              // avl2apb_avalon_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
	wire   [0:0] avalon_st_adapter_001_out_0_error;                                              // avalon_st_adapter_001:out_0_error -> avl2apb_avalon_slave_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (20),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (20),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (1)
	) cpu_inst_data_master_translator (
		.clk                    (p0_avl_clk_clk),                                                          //                       clk.clk
		.reset                  (cpu_inst_reset_n_reset_bridge_in_reset_reset),                            //                     reset.reset
		.uav_address            (cpu_inst_data_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (cpu_inst_data_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (cpu_inst_data_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (cpu_inst_data_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (cpu_inst_data_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (cpu_inst_data_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (cpu_inst_data_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (cpu_inst_data_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable          (cpu_inst_data_master_byteenable),                                         //                          .byteenable
		.av_read                (cpu_inst_data_master_read),                                               //                          .read
		.av_readdata            (cpu_inst_data_master_readdata),                                           //                          .readdata
		.av_write               (cpu_inst_data_master_write),                                              //                          .write
		.av_writedata           (cpu_inst_data_master_writedata),                                          //                          .writedata
		.av_burstcount          (1'b1),                                                                    //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                    //               (terminated)
		.av_begintransfer       (1'b0),                                                                    //               (terminated)
		.av_chipselect          (1'b0),                                                                    //               (terminated)
		.av_readdatavalid       (),                                                                        //               (terminated)
		.av_lock                (1'b0),                                                                    //               (terminated)
		.av_debugaccess         (1'b0),                                                                    //               (terminated)
		.uav_clken              (),                                                                        //               (terminated)
		.av_clken               (1'b1),                                                                    //               (terminated)
		.uav_response           (2'b00),                                                                   //               (terminated)
		.av_response            (),                                                                        //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                    //               (terminated)
		.av_writeresponsevalid  ()                                                                         //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (17),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (20),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (1),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) cpu_inst_instruction_master_translator (
		.clk                    (p0_avl_clk_clk),                                                                 //                       clk.clk
		.reset                  (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                   //                     reset.reset
		.uav_address            (cpu_inst_instruction_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (cpu_inst_instruction_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (cpu_inst_instruction_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (cpu_inst_instruction_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (cpu_inst_instruction_master_waitrequest),                                        //                          .waitrequest
		.av_read                (cpu_inst_instruction_master_read),                                               //                          .read
		.av_readdata            (cpu_inst_instruction_master_readdata),                                           //                          .readdata
		.av_burstcount          (1'b1),                                                                           //               (terminated)
		.av_byteenable          (4'b1111),                                                                        //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                           //               (terminated)
		.av_begintransfer       (1'b0),                                                                           //               (terminated)
		.av_chipselect          (1'b0),                                                                           //               (terminated)
		.av_readdatavalid       (),                                                                               //               (terminated)
		.av_write               (1'b0),                                                                           //               (terminated)
		.av_writedata           (32'b00000000000000000000000000000000),                                           //               (terminated)
		.av_lock                (1'b0),                                                                           //               (terminated)
		.av_debugaccess         (1'b0),                                                                           //               (terminated)
		.uav_clken              (),                                                                               //               (terminated)
		.av_clken               (1'b1),                                                                           //               (terminated)
		.uav_response           (2'b00),                                                                          //               (terminated)
		.av_response            (),                                                                               //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                           //               (terminated)
		.av_writeresponsevalid  ()                                                                                //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (13),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (20),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sequencer_mem_s1_translator (
		.clk                    (p0_avl_clk_clk),                               //                      clk.clk
		.reset                  (cpu_inst_reset_n_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (sequencer_mem_s1_agent_m0_address),            // avalon_universal_slave_0.address
		.uav_burstcount         (sequencer_mem_s1_agent_m0_burstcount),         //                         .burstcount
		.uav_read               (sequencer_mem_s1_agent_m0_read),               //                         .read
		.uav_write              (sequencer_mem_s1_agent_m0_write),              //                         .write
		.uav_waitrequest        (sequencer_mem_s1_agent_m0_waitrequest),        //                         .waitrequest
		.uav_readdatavalid      (sequencer_mem_s1_agent_m0_readdatavalid),      //                         .readdatavalid
		.uav_byteenable         (sequencer_mem_s1_agent_m0_byteenable),         //                         .byteenable
		.uav_readdata           (sequencer_mem_s1_agent_m0_readdata),           //                         .readdata
		.uav_writedata          (sequencer_mem_s1_agent_m0_writedata),          //                         .writedata
		.uav_lock               (sequencer_mem_s1_agent_m0_lock),               //                         .lock
		.uav_debugaccess        (sequencer_mem_s1_agent_m0_debugaccess),        //                         .debugaccess
		.av_address             (sequencer_mem_s1_address),                     //      avalon_anti_slave_0.address
		.av_write               (sequencer_mem_s1_write),                       //                         .write
		.av_readdata            (sequencer_mem_s1_readdata),                    //                         .readdata
		.av_writedata           (sequencer_mem_s1_writedata),                   //                         .writedata
		.av_byteenable          (sequencer_mem_s1_byteenable),                  //                         .byteenable
		.av_chipselect          (sequencer_mem_s1_chipselect),                  //                         .chipselect
		.av_read                (),                                             //              (terminated)
		.av_begintransfer       (),                                             //              (terminated)
		.av_beginbursttransfer  (),                                             //              (terminated)
		.av_burstcount          (),                                             //              (terminated)
		.av_readdatavalid       (1'b0),                                         //              (terminated)
		.av_waitrequest         (1'b0),                                         //              (terminated)
		.av_writebyteenable     (),                                             //              (terminated)
		.av_lock                (),                                             //              (terminated)
		.av_clken               (),                                             //              (terminated)
		.uav_clken              (1'b0),                                         //              (terminated)
		.av_debugaccess         (),                                             //              (terminated)
		.av_outputenable        (),                                             //              (terminated)
		.uav_response           (),                                             //              (terminated)
		.av_response            (2'b00),                                        //              (terminated)
		.uav_writeresponsevalid (),                                             //              (terminated)
		.av_writeresponsevalid  (1'b0)                                          //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (16),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (20),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (1),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) avl2apb_avalon_slave_translator (
		.clk                    (p0_avl_clk_clk),                               //                      clk.clk
		.reset                  (cpu_inst_reset_n_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (avl2apb_avalon_slave_agent_m0_address),        // avalon_universal_slave_0.address
		.uav_burstcount         (avl2apb_avalon_slave_agent_m0_burstcount),     //                         .burstcount
		.uav_read               (avl2apb_avalon_slave_agent_m0_read),           //                         .read
		.uav_write              (avl2apb_avalon_slave_agent_m0_write),          //                         .write
		.uav_waitrequest        (avl2apb_avalon_slave_agent_m0_waitrequest),    //                         .waitrequest
		.uav_readdatavalid      (avl2apb_avalon_slave_agent_m0_readdatavalid),  //                         .readdatavalid
		.uav_byteenable         (avl2apb_avalon_slave_agent_m0_byteenable),     //                         .byteenable
		.uav_readdata           (avl2apb_avalon_slave_agent_m0_readdata),       //                         .readdata
		.uav_writedata          (avl2apb_avalon_slave_agent_m0_writedata),      //                         .writedata
		.uav_lock               (avl2apb_avalon_slave_agent_m0_lock),           //                         .lock
		.uav_debugaccess        (avl2apb_avalon_slave_agent_m0_debugaccess),    //                         .debugaccess
		.av_address             (avl2apb_avalon_slave_address),                 //      avalon_anti_slave_0.address
		.av_write               (avl2apb_avalon_slave_write),                   //                         .write
		.av_read                (avl2apb_avalon_slave_read),                    //                         .read
		.av_readdata            (avl2apb_avalon_slave_readdata),                //                         .readdata
		.av_writedata           (avl2apb_avalon_slave_writedata),               //                         .writedata
		.av_byteenable          (avl2apb_avalon_slave_byteenable),              //                         .byteenable
		.av_waitrequest         (avl2apb_avalon_slave_waitrequest),             //                         .waitrequest
		.av_begintransfer       (),                                             //              (terminated)
		.av_beginbursttransfer  (),                                             //              (terminated)
		.av_burstcount          (),                                             //              (terminated)
		.av_readdatavalid       (1'b0),                                         //              (terminated)
		.av_writebyteenable     (),                                             //              (terminated)
		.av_lock                (),                                             //              (terminated)
		.av_chipselect          (),                                             //              (terminated)
		.av_clken               (),                                             //              (terminated)
		.uav_clken              (1'b0),                                         //              (terminated)
		.av_debugaccess         (),                                             //              (terminated)
		.av_outputenable        (),                                             //              (terminated)
		.uav_response           (),                                             //              (terminated)
		.av_response            (2'b00),                                        //              (terminated)
		.uav_writeresponsevalid (),                                             //              (terminated)
		.av_writeresponsevalid  (1'b0)                                          //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (91),
		.PKT_ORI_BURST_SIZE_L      (89),
		.PKT_RESPONSE_STATUS_H     (88),
		.PKT_RESPONSE_STATUS_L     (87),
		.PKT_QOS_H                 (76),
		.PKT_QOS_L                 (76),
		.PKT_DATA_SIDEBAND_H       (74),
		.PKT_DATA_SIDEBAND_L       (74),
		.PKT_ADDR_SIDEBAND_H       (73),
		.PKT_ADDR_SIDEBAND_L       (73),
		.PKT_BURST_TYPE_H          (72),
		.PKT_BURST_TYPE_L          (71),
		.PKT_CACHE_H               (86),
		.PKT_CACHE_L               (83),
		.PKT_THREAD_ID_H           (79),
		.PKT_THREAD_ID_L           (79),
		.PKT_BURST_SIZE_H          (70),
		.PKT_BURST_SIZE_L          (68),
		.PKT_TRANS_EXCLUSIVE       (61),
		.PKT_TRANS_LOCK            (60),
		.PKT_BEGIN_BURST           (75),
		.PKT_PROTECTION_H          (82),
		.PKT_PROTECTION_L          (80),
		.PKT_BURSTWRAP_H           (67),
		.PKT_BURSTWRAP_L           (65),
		.PKT_BYTE_CNT_H            (64),
		.PKT_BYTE_CNT_L            (62),
		.PKT_ADDR_H                (55),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (56),
		.PKT_TRANS_POSTED          (57),
		.PKT_TRANS_WRITE           (58),
		.PKT_TRANS_READ            (59),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (77),
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (78),
		.ST_DATA_W                 (92),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (7),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) cpu_inst_data_master_agent (
		.clk                   (p0_avl_clk_clk),                                                          //       clk.clk
		.reset                 (cpu_inst_reset_n_reset_bridge_in_reset_reset),                            // clk_reset.reset
		.av_address            (cpu_inst_data_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (cpu_inst_data_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (cpu_inst_data_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (cpu_inst_data_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (cpu_inst_data_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (cpu_inst_data_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (cpu_inst_data_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (cpu_inst_data_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (cpu_inst_data_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (cpu_inst_data_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (cpu_inst_data_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_src_valid),                                                       //        rp.valid
		.rp_data               (rsp_mux_src_data),                                                        //          .data
		.rp_channel            (rsp_mux_src_channel),                                                     //          .channel
		.rp_startofpacket      (rsp_mux_src_startofpacket),                                               //          .startofpacket
		.rp_endofpacket        (rsp_mux_src_endofpacket),                                                 //          .endofpacket
		.rp_ready              (rsp_mux_src_ready),                                                       //          .ready
		.av_response           (),                                                                        // (terminated)
		.av_writeresponsevalid ()                                                                         // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (91),
		.PKT_ORI_BURST_SIZE_L      (89),
		.PKT_RESPONSE_STATUS_H     (88),
		.PKT_RESPONSE_STATUS_L     (87),
		.PKT_QOS_H                 (76),
		.PKT_QOS_L                 (76),
		.PKT_DATA_SIDEBAND_H       (74),
		.PKT_DATA_SIDEBAND_L       (74),
		.PKT_ADDR_SIDEBAND_H       (73),
		.PKT_ADDR_SIDEBAND_L       (73),
		.PKT_BURST_TYPE_H          (72),
		.PKT_BURST_TYPE_L          (71),
		.PKT_CACHE_H               (86),
		.PKT_CACHE_L               (83),
		.PKT_THREAD_ID_H           (79),
		.PKT_THREAD_ID_L           (79),
		.PKT_BURST_SIZE_H          (70),
		.PKT_BURST_SIZE_L          (68),
		.PKT_TRANS_EXCLUSIVE       (61),
		.PKT_TRANS_LOCK            (60),
		.PKT_BEGIN_BURST           (75),
		.PKT_PROTECTION_H          (82),
		.PKT_PROTECTION_L          (80),
		.PKT_BURSTWRAP_H           (67),
		.PKT_BURSTWRAP_L           (65),
		.PKT_BYTE_CNT_H            (64),
		.PKT_BYTE_CNT_L            (62),
		.PKT_ADDR_H                (55),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (56),
		.PKT_TRANS_POSTED          (57),
		.PKT_TRANS_WRITE           (58),
		.PKT_TRANS_READ            (59),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (77),
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (78),
		.ST_DATA_W                 (92),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (3),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) cpu_inst_instruction_master_agent (
		.clk                   (p0_avl_clk_clk),                                                                 //       clk.clk
		.reset                 (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                   // clk_reset.reset
		.av_address            (cpu_inst_instruction_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (cpu_inst_instruction_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (cpu_inst_instruction_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (cpu_inst_instruction_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (cpu_inst_instruction_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (cpu_inst_instruction_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (cpu_inst_instruction_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (cpu_inst_instruction_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_001_src_valid),                                                          //        rp.valid
		.rp_data               (rsp_mux_001_src_data),                                                           //          .data
		.rp_channel            (rsp_mux_001_src_channel),                                                        //          .channel
		.rp_startofpacket      (rsp_mux_001_src_startofpacket),                                                  //          .startofpacket
		.rp_endofpacket        (rsp_mux_001_src_endofpacket),                                                    //          .endofpacket
		.rp_ready              (rsp_mux_001_src_ready),                                                          //          .ready
		.av_response           (),                                                                               // (terminated)
		.av_writeresponsevalid ()                                                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (91),
		.PKT_ORI_BURST_SIZE_L      (89),
		.PKT_RESPONSE_STATUS_H     (88),
		.PKT_RESPONSE_STATUS_L     (87),
		.PKT_BURST_SIZE_H          (70),
		.PKT_BURST_SIZE_L          (68),
		.PKT_TRANS_LOCK            (60),
		.PKT_BEGIN_BURST           (75),
		.PKT_PROTECTION_H          (82),
		.PKT_PROTECTION_L          (80),
		.PKT_BURSTWRAP_H           (67),
		.PKT_BURSTWRAP_L           (65),
		.PKT_BYTE_CNT_H            (64),
		.PKT_BYTE_CNT_L            (62),
		.PKT_ADDR_H                (55),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (56),
		.PKT_TRANS_POSTED          (57),
		.PKT_TRANS_WRITE           (58),
		.PKT_TRANS_READ            (59),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (77),
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (78),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (92),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) sequencer_mem_s1_agent (
		.clk                     (p0_avl_clk_clk),                                    //             clk.clk
		.reset                   (cpu_inst_reset_n_reset_bridge_in_reset_reset),      //       clk_reset.reset
		.m0_address              (sequencer_mem_s1_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sequencer_mem_s1_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sequencer_mem_s1_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sequencer_mem_s1_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sequencer_mem_s1_agent_m0_lock),                    //                .lock
		.m0_readdata             (sequencer_mem_s1_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sequencer_mem_s1_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sequencer_mem_s1_agent_m0_read),                    //                .read
		.m0_waitrequest          (sequencer_mem_s1_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sequencer_mem_s1_agent_m0_writedata),               //                .writedata
		.m0_write                (sequencer_mem_s1_agent_m0_write),                   //                .write
		.rp_endofpacket          (sequencer_mem_s1_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sequencer_mem_s1_agent_rp_ready),                   //                .ready
		.rp_valid                (sequencer_mem_s1_agent_rp_valid),                   //                .valid
		.rp_data                 (sequencer_mem_s1_agent_rp_data),                    //                .data
		.rp_startofpacket        (sequencer_mem_s1_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_src_ready),                                 //              cp.ready
		.cp_valid                (cmd_mux_src_valid),                                 //                .valid
		.cp_data                 (cmd_mux_src_data),                                  //                .data
		.cp_startofpacket        (cmd_mux_src_startofpacket),                         //                .startofpacket
		.cp_endofpacket          (cmd_mux_src_endofpacket),                           //                .endofpacket
		.cp_channel              (cmd_mux_src_channel),                               //                .channel
		.rf_sink_ready           (sequencer_mem_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sequencer_mem_s1_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sequencer_mem_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sequencer_mem_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sequencer_mem_s1_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sequencer_mem_s1_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sequencer_mem_s1_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sequencer_mem_s1_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sequencer_mem_s1_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sequencer_mem_s1_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                     // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                     //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                      //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                     //                .error
		.rdata_fifo_src_ready    (sequencer_mem_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sequencer_mem_s1_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sequencer_mem_s1_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                             //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                               //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (93),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sequencer_mem_s1_agent_rsp_fifo (
		.clk               (p0_avl_clk_clk),                                    //       clk.clk
		.reset             (cpu_inst_reset_n_reset_bridge_in_reset_reset),      // clk_reset.reset
		.in_data           (sequencer_mem_s1_agent_rf_source_data),             //        in.data
		.in_valid          (sequencer_mem_s1_agent_rf_source_valid),            //          .valid
		.in_ready          (sequencer_mem_s1_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sequencer_mem_s1_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sequencer_mem_s1_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sequencer_mem_s1_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sequencer_mem_s1_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sequencer_mem_s1_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sequencer_mem_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sequencer_mem_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                             // (terminated)
		.csr_read          (1'b0),                                              // (terminated)
		.csr_write         (1'b0),                                              // (terminated)
		.csr_readdata      (),                                                  // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),              // (terminated)
		.almost_full_data  (),                                                  // (terminated)
		.almost_empty_data (),                                                  // (terminated)
		.in_empty          (1'b0),                                              // (terminated)
		.out_empty         (),                                                  // (terminated)
		.in_error          (1'b0),                                              // (terminated)
		.out_error         (),                                                  // (terminated)
		.in_channel        (1'b0),                                              // (terminated)
		.out_channel       ()                                                   // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (91),
		.PKT_ORI_BURST_SIZE_L      (89),
		.PKT_RESPONSE_STATUS_H     (88),
		.PKT_RESPONSE_STATUS_L     (87),
		.PKT_BURST_SIZE_H          (70),
		.PKT_BURST_SIZE_L          (68),
		.PKT_TRANS_LOCK            (60),
		.PKT_BEGIN_BURST           (75),
		.PKT_PROTECTION_H          (82),
		.PKT_PROTECTION_L          (80),
		.PKT_BURSTWRAP_H           (67),
		.PKT_BURSTWRAP_L           (65),
		.PKT_BYTE_CNT_H            (64),
		.PKT_BYTE_CNT_L            (62),
		.PKT_ADDR_H                (55),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (56),
		.PKT_TRANS_POSTED          (57),
		.PKT_TRANS_WRITE           (58),
		.PKT_TRANS_READ            (59),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (77),
		.PKT_SRC_ID_L              (77),
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (78),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (92),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) avl2apb_avalon_slave_agent (
		.clk                     (p0_avl_clk_clk),                                           //             clk.clk
		.reset                   (cpu_inst_reset_n_reset_bridge_in_reset_reset),             //       clk_reset.reset
		.m0_address              (avl2apb_avalon_slave_agent_m0_address),                    //              m0.address
		.m0_burstcount           (avl2apb_avalon_slave_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (avl2apb_avalon_slave_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (avl2apb_avalon_slave_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (avl2apb_avalon_slave_agent_m0_lock),                       //                .lock
		.m0_readdata             (avl2apb_avalon_slave_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (avl2apb_avalon_slave_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (avl2apb_avalon_slave_agent_m0_read),                       //                .read
		.m0_waitrequest          (avl2apb_avalon_slave_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (avl2apb_avalon_slave_agent_m0_writedata),                  //                .writedata
		.m0_write                (avl2apb_avalon_slave_agent_m0_write),                      //                .write
		.rp_endofpacket          (avl2apb_avalon_slave_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (avl2apb_avalon_slave_agent_rp_ready),                      //                .ready
		.rp_valid                (avl2apb_avalon_slave_agent_rp_valid),                      //                .valid
		.rp_data                 (avl2apb_avalon_slave_agent_rp_data),                       //                .data
		.rp_startofpacket        (avl2apb_avalon_slave_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (avl2apb_avalon_slave_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (avl2apb_avalon_slave_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (avl2apb_avalon_slave_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (avl2apb_avalon_slave_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (avl2apb_avalon_slave_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (avl2apb_avalon_slave_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (avl2apb_avalon_slave_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (avl2apb_avalon_slave_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (avl2apb_avalon_slave_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (avl2apb_avalon_slave_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (avl2apb_avalon_slave_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (avl2apb_avalon_slave_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (avl2apb_avalon_slave_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (avl2apb_avalon_slave_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (avl2apb_avalon_slave_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (avl2apb_avalon_slave_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),                        // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),                        //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),                         //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),                        //                .error
		.rdata_fifo_src_ready    (avl2apb_avalon_slave_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (avl2apb_avalon_slave_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (avl2apb_avalon_slave_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                    //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                      //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (93),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) avl2apb_avalon_slave_agent_rsp_fifo (
		.clk               (p0_avl_clk_clk),                                        //       clk.clk
		.reset             (cpu_inst_reset_n_reset_bridge_in_reset_reset),          // clk_reset.reset
		.in_data           (avl2apb_avalon_slave_agent_rf_source_data),             //        in.data
		.in_valid          (avl2apb_avalon_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (avl2apb_avalon_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (avl2apb_avalon_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (avl2apb_avalon_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (avl2apb_avalon_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (avl2apb_avalon_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (avl2apb_avalon_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (avl2apb_avalon_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (avl2apb_avalon_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                 // (terminated)
		.csr_read          (1'b0),                                                  // (terminated)
		.csr_write         (1'b0),                                                  // (terminated)
		.csr_readdata      (),                                                      // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                  // (terminated)
		.almost_full_data  (),                                                      // (terminated)
		.almost_empty_data (),                                                      // (terminated)
		.in_empty          (1'b0),                                                  // (terminated)
		.out_empty         (),                                                      // (terminated)
		.in_error          (1'b0),                                                  // (terminated)
		.out_error         (),                                                      // (terminated)
		.in_channel        (1'b0),                                                  // (terminated)
		.out_channel       ()                                                       // (terminated)
	);

	hps_sdram_mm_interconnect_1_router router (
		.sink_ready         (cpu_inst_data_master_agent_cp_ready),          //      sink.ready
		.sink_valid         (cpu_inst_data_master_agent_cp_valid),          //          .valid
		.sink_data          (cpu_inst_data_master_agent_cp_data),           //          .data
		.sink_startofpacket (cpu_inst_data_master_agent_cp_startofpacket),  //          .startofpacket
		.sink_endofpacket   (cpu_inst_data_master_agent_cp_endofpacket),    //          .endofpacket
		.clk                (p0_avl_clk_clk),                               //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                             //       src.ready
		.src_valid          (router_src_valid),                             //          .valid
		.src_data           (router_src_data),                              //          .data
		.src_channel        (router_src_channel),                           //          .channel
		.src_startofpacket  (router_src_startofpacket),                     //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                        //          .endofpacket
	);

	hps_sdram_mm_interconnect_1_router_001 router_001 (
		.sink_ready         (cpu_inst_instruction_master_agent_cp_ready),         //      sink.ready
		.sink_valid         (cpu_inst_instruction_master_agent_cp_valid),         //          .valid
		.sink_data          (cpu_inst_instruction_master_agent_cp_data),          //          .data
		.sink_startofpacket (cpu_inst_instruction_master_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (cpu_inst_instruction_master_agent_cp_endofpacket),   //          .endofpacket
		.clk                (p0_avl_clk_clk),                                     //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset),       // clk_reset.reset
		.src_ready          (router_001_src_ready),                               //       src.ready
		.src_valid          (router_001_src_valid),                               //          .valid
		.src_data           (router_001_src_data),                                //          .data
		.src_channel        (router_001_src_channel),                             //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                       //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                          //          .endofpacket
	);

	hps_sdram_mm_interconnect_1_router_002 router_002 (
		.sink_ready         (sequencer_mem_s1_agent_rp_ready),              //      sink.ready
		.sink_valid         (sequencer_mem_s1_agent_rp_valid),              //          .valid
		.sink_data          (sequencer_mem_s1_agent_rp_data),               //          .data
		.sink_startofpacket (sequencer_mem_s1_agent_rp_startofpacket),      //          .startofpacket
		.sink_endofpacket   (sequencer_mem_s1_agent_rp_endofpacket),        //          .endofpacket
		.clk                (p0_avl_clk_clk),                               //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_002_src_ready),                         //       src.ready
		.src_valid          (router_002_src_valid),                         //          .valid
		.src_data           (router_002_src_data),                          //          .data
		.src_channel        (router_002_src_channel),                       //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                 //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                    //          .endofpacket
	);

	hps_sdram_mm_interconnect_1_router_003 router_003 (
		.sink_ready         (avl2apb_avalon_slave_agent_rp_ready),          //      sink.ready
		.sink_valid         (avl2apb_avalon_slave_agent_rp_valid),          //          .valid
		.sink_data          (avl2apb_avalon_slave_agent_rp_data),           //          .data
		.sink_startofpacket (avl2apb_avalon_slave_agent_rp_startofpacket),  //          .startofpacket
		.sink_endofpacket   (avl2apb_avalon_slave_agent_rp_endofpacket),    //          .endofpacket
		.clk                (p0_avl_clk_clk),                               //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_003_src_ready),                         //       src.ready
		.src_valid          (router_003_src_valid),                         //          .valid
		.src_data           (router_003_src_data),                          //          .data
		.src_channel        (router_003_src_channel),                       //          .channel
		.src_startofpacket  (router_003_src_startofpacket),                 //          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                    //          .endofpacket
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (55),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (75),
		.PKT_BYTE_CNT_H            (64),
		.PKT_BYTE_CNT_L            (62),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (70),
		.PKT_BURST_SIZE_L          (68),
		.PKT_BURST_TYPE_H          (72),
		.PKT_BURST_TYPE_L          (71),
		.PKT_BURSTWRAP_H           (67),
		.PKT_BURSTWRAP_L           (65),
		.PKT_TRANS_COMPRESSED_READ (56),
		.PKT_TRANS_WRITE           (58),
		.PKT_TRANS_READ            (59),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (92),
		.ST_CHANNEL_W              (2),
		.OUT_BYTE_CNT_H            (62),
		.OUT_BURSTWRAP_H           (67),
		.COMPRESSED_READ_SUPPORT   (0),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (7),
		.BURSTWRAP_CONST_VALUE     (7),
		.ADAPTER_VERSION           ("13.1")
	) avl2apb_avalon_slave_burst_adapter (
		.clk                   (p0_avl_clk_clk),                                           //       cr0.clk
		.reset                 (cpu_inst_reset_n_reset_bridge_in_reset_reset),             // cr0_reset.reset
		.sink0_valid           (cmd_mux_001_src_valid),                                    //     sink0.valid
		.sink0_data            (cmd_mux_001_src_data),                                     //          .data
		.sink0_channel         (cmd_mux_001_src_channel),                                  //          .channel
		.sink0_startofpacket   (cmd_mux_001_src_startofpacket),                            //          .startofpacket
		.sink0_endofpacket     (cmd_mux_001_src_endofpacket),                              //          .endofpacket
		.sink0_ready           (cmd_mux_001_src_ready),                                    //          .ready
		.source0_valid         (avl2apb_avalon_slave_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (avl2apb_avalon_slave_burst_adapter_source0_data),          //          .data
		.source0_channel       (avl2apb_avalon_slave_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (avl2apb_avalon_slave_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (avl2apb_avalon_slave_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (avl2apb_avalon_slave_burst_adapter_source0_ready)          //          .ready
	);

	hps_sdram_mm_interconnect_1_cmd_demux cmd_demux (
		.clk                (p0_avl_clk_clk),                               //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                             //      sink.ready
		.sink_channel       (router_src_channel),                           //          .channel
		.sink_data          (router_src_data),                              //          .data
		.sink_startofpacket (router_src_startofpacket),                     //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                       //          .endofpacket
		.sink_valid         (router_src_valid),                             //          .valid
		.src0_ready         (cmd_demux_src0_ready),                         //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                         //          .valid
		.src0_data          (cmd_demux_src0_data),                          //          .data
		.src0_channel       (cmd_demux_src0_channel),                       //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                 //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                   //          .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                         //      src1.ready
		.src1_valid         (cmd_demux_src1_valid),                         //          .valid
		.src1_data          (cmd_demux_src1_data),                          //          .data
		.src1_channel       (cmd_demux_src1_channel),                       //          .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                 //          .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket)                    //          .endofpacket
	);

	hps_sdram_mm_interconnect_1_cmd_demux_001 cmd_demux_001 (
		.clk                (p0_avl_clk_clk),                               //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                         //      sink.ready
		.sink_channel       (router_001_src_channel),                       //          .channel
		.sink_data          (router_001_src_data),                          //          .data
		.sink_startofpacket (router_001_src_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                   //          .endofpacket
		.sink_valid         (router_001_src_valid),                         //          .valid
		.src0_ready         (cmd_demux_001_src0_ready),                     //      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                     //          .valid
		.src0_data          (cmd_demux_001_src0_data),                      //          .data
		.src0_channel       (cmd_demux_001_src0_channel),                   //          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),             //          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket)                //          .endofpacket
	);

	hps_sdram_mm_interconnect_1_cmd_mux cmd_mux (
		.clk                 (p0_avl_clk_clk),                               //       clk.clk
		.reset               (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                            //       src.ready
		.src_valid           (cmd_mux_src_valid),                            //          .valid
		.src_data            (cmd_mux_src_data),                             //          .data
		.src_channel         (cmd_mux_src_channel),                          //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                    //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                      //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                         //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                         //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                       //          .channel
		.sink0_data          (cmd_demux_src0_data),                          //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                 //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket),                   //          .endofpacket
		.sink1_ready         (cmd_demux_001_src0_ready),                     //     sink1.ready
		.sink1_valid         (cmd_demux_001_src0_valid),                     //          .valid
		.sink1_channel       (cmd_demux_001_src0_channel),                   //          .channel
		.sink1_data          (cmd_demux_001_src0_data),                      //          .data
		.sink1_startofpacket (cmd_demux_001_src0_startofpacket),             //          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src0_endofpacket)                //          .endofpacket
	);

	hps_sdram_mm_interconnect_1_cmd_mux_001 cmd_mux_001 (
		.clk                 (p0_avl_clk_clk),                               //       clk.clk
		.reset               (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                        //       src.ready
		.src_valid           (cmd_mux_001_src_valid),                        //          .valid
		.src_data            (cmd_mux_001_src_data),                         //          .data
		.src_channel         (cmd_mux_001_src_channel),                      //          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                //          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                  //          .endofpacket
		.sink0_ready         (cmd_demux_src1_ready),                         //     sink0.ready
		.sink0_valid         (cmd_demux_src1_valid),                         //          .valid
		.sink0_channel       (cmd_demux_src1_channel),                       //          .channel
		.sink0_data          (cmd_demux_src1_data),                          //          .data
		.sink0_startofpacket (cmd_demux_src1_startofpacket),                 //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src1_endofpacket)                    //          .endofpacket
	);

	hps_sdram_mm_interconnect_1_cmd_demux rsp_demux (
		.clk                (p0_avl_clk_clk),                               //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_002_src_ready),                         //      sink.ready
		.sink_channel       (router_002_src_channel),                       //          .channel
		.sink_data          (router_002_src_data),                          //          .data
		.sink_startofpacket (router_002_src_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                   //          .endofpacket
		.sink_valid         (router_002_src_valid),                         //          .valid
		.src0_ready         (rsp_demux_src0_ready),                         //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                         //          .valid
		.src0_data          (rsp_demux_src0_data),                          //          .data
		.src0_channel       (rsp_demux_src0_channel),                       //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                 //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket),                   //          .endofpacket
		.src1_ready         (rsp_demux_src1_ready),                         //      src1.ready
		.src1_valid         (rsp_demux_src1_valid),                         //          .valid
		.src1_data          (rsp_demux_src1_data),                          //          .data
		.src1_channel       (rsp_demux_src1_channel),                       //          .channel
		.src1_startofpacket (rsp_demux_src1_startofpacket),                 //          .startofpacket
		.src1_endofpacket   (rsp_demux_src1_endofpacket)                    //          .endofpacket
	);

	hps_sdram_mm_interconnect_1_cmd_demux_001 rsp_demux_001 (
		.clk                (p0_avl_clk_clk),                               //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_003_src_ready),                         //      sink.ready
		.sink_channel       (router_003_src_channel),                       //          .channel
		.sink_data          (router_003_src_data),                          //          .data
		.sink_startofpacket (router_003_src_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (router_003_src_endofpacket),                   //          .endofpacket
		.sink_valid         (router_003_src_valid),                         //          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                     //      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                     //          .valid
		.src0_data          (rsp_demux_001_src0_data),                      //          .data
		.src0_channel       (rsp_demux_001_src0_channel),                   //          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),             //          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)                //          .endofpacket
	);

	hps_sdram_mm_interconnect_1_rsp_mux rsp_mux (
		.clk                 (p0_avl_clk_clk),                               //       clk.clk
		.reset               (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                            //       src.ready
		.src_valid           (rsp_mux_src_valid),                            //          .valid
		.src_data            (rsp_mux_src_data),                             //          .data
		.src_channel         (rsp_mux_src_channel),                          //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                    //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                      //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                         //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                         //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                       //          .channel
		.sink0_data          (rsp_demux_src0_data),                          //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                 //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket),                   //          .endofpacket
		.sink1_ready         (rsp_demux_001_src0_ready),                     //     sink1.ready
		.sink1_valid         (rsp_demux_001_src0_valid),                     //          .valid
		.sink1_channel       (rsp_demux_001_src0_channel),                   //          .channel
		.sink1_data          (rsp_demux_001_src0_data),                      //          .data
		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),             //          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket)                //          .endofpacket
	);

	hps_sdram_mm_interconnect_1_rsp_mux_001 rsp_mux_001 (
		.clk                 (p0_avl_clk_clk),                               //       clk.clk
		.reset               (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                        //       src.ready
		.src_valid           (rsp_mux_001_src_valid),                        //          .valid
		.src_data            (rsp_mux_001_src_data),                         //          .data
		.src_channel         (rsp_mux_001_src_channel),                      //          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),                //          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),                  //          .endofpacket
		.sink0_ready         (rsp_demux_src1_ready),                         //     sink0.ready
		.sink0_valid         (rsp_demux_src1_valid),                         //          .valid
		.sink0_channel       (rsp_demux_src1_channel),                       //          .channel
		.sink0_data          (rsp_demux_src1_data),                          //          .data
		.sink0_startofpacket (rsp_demux_src1_startofpacket),                 //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src1_endofpacket)                    //          .endofpacket
	);

	hps_sdram_mm_interconnect_1_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (p0_avl_clk_clk),                               // in_clk_0.clk
		.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (sequencer_mem_s1_agent_rdata_fifo_src_data),   //     in_0.data
		.in_0_valid     (sequencer_mem_s1_agent_rdata_fifo_src_valid),  //         .valid
		.in_0_ready     (sequencer_mem_s1_agent_rdata_fifo_src_ready),  //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                 //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                 //         .error
	);

	hps_sdram_mm_interconnect_1_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_001 (
		.in_clk_0_clk   (p0_avl_clk_clk),                                  // in_clk_0.clk
		.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset),    // in_rst_0.reset
		.in_0_data      (avl2apb_avalon_slave_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (avl2apb_avalon_slave_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (avl2apb_avalon_slave_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_001_out_0_data),                //    out_0.data
		.out_0_valid    (avalon_st_adapter_001_out_0_valid),               //         .valid
		.out_0_ready    (avalon_st_adapter_001_out_0_ready),               //         .ready
		.out_0_error    (avalon_st_adapter_001_out_0_error)                //         .error
	);

endmodule
