// system_acl_iface_mm_interconnect_5.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 15.1 193

`timescale 1 ps / 1 ps
module system_acl_iface_mm_interconnect_5 (
		input  wire         pll_outclk0_clk,                                               //                                             pll_outclk0.clk
		input  wire         clock_cross_axi_fpga_m0_reset_reset_bridge_in_reset_reset,     //     clock_cross_axi_fpga_m0_reset_reset_bridge_in_reset.reset
		input  wire         fpga_sdram_avl_0_translator_reset_reset_bridge_in_reset_reset, // fpga_sdram_avl_0_translator_reset_reset_bridge_in_reset.reset
		input  wire         fpga_sdram_mp_cmd_reset_n_0_reset_bridge_in_reset_reset,       //       fpga_sdram_mp_cmd_reset_n_0_reset_bridge_in_reset.reset
		input  wire [29:0]  clock_cross_axi_fpga_m0_address,                               //                                 clock_cross_axi_fpga_m0.address
		output wire         clock_cross_axi_fpga_m0_waitrequest,                           //                                                        .waitrequest
		input  wire [4:0]   clock_cross_axi_fpga_m0_burstcount,                            //                                                        .burstcount
		input  wire [31:0]  clock_cross_axi_fpga_m0_byteenable,                            //                                                        .byteenable
		input  wire         clock_cross_axi_fpga_m0_read,                                  //                                                        .read
		output wire [255:0] clock_cross_axi_fpga_m0_readdata,                              //                                                        .readdata
		output wire         clock_cross_axi_fpga_m0_readdatavalid,                         //                                                        .readdatavalid
		input  wire         clock_cross_axi_fpga_m0_write,                                 //                                                        .write
		input  wire [255:0] clock_cross_axi_fpga_m0_writedata,                             //                                                        .writedata
		input  wire         clock_cross_axi_fpga_m0_debugaccess,                           //                                                        .debugaccess
		input  wire [24:0]  clock_cross_kernel_mem0_m0_address,                            //                              clock_cross_kernel_mem0_m0.address
		output wire         clock_cross_kernel_mem0_m0_waitrequest,                        //                                                        .waitrequest
		input  wire [4:0]   clock_cross_kernel_mem0_m0_burstcount,                         //                                                        .burstcount
		input  wire [31:0]  clock_cross_kernel_mem0_m0_byteenable,                         //                                                        .byteenable
		input  wire         clock_cross_kernel_mem0_m0_read,                               //                                                        .read
		output wire [255:0] clock_cross_kernel_mem0_m0_readdata,                           //                                                        .readdata
		output wire         clock_cross_kernel_mem0_m0_readdatavalid,                      //                                                        .readdatavalid
		input  wire         clock_cross_kernel_mem0_m0_write,                              //                                                        .write
		input  wire [255:0] clock_cross_kernel_mem0_m0_writedata,                          //                                                        .writedata
		input  wire         clock_cross_kernel_mem0_m0_debugaccess,                        //                                                        .debugaccess
		output wire [24:0]  fpga_sdram_avl_0_address,                                      //                                        fpga_sdram_avl_0.address
		output wire         fpga_sdram_avl_0_write,                                        //                                                        .write
		output wire         fpga_sdram_avl_0_read,                                         //                                                        .read
		input  wire [255:0] fpga_sdram_avl_0_readdata,                                     //                                                        .readdata
		output wire [255:0] fpga_sdram_avl_0_writedata,                                    //                                                        .writedata
		output wire         fpga_sdram_avl_0_beginbursttransfer,                           //                                                        .beginbursttransfer
		output wire [4:0]   fpga_sdram_avl_0_burstcount,                                   //                                                        .burstcount
		output wire [31:0]  fpga_sdram_avl_0_byteenable,                                   //                                                        .byteenable
		input  wire         fpga_sdram_avl_0_readdatavalid,                                //                                                        .readdatavalid
		input  wire         fpga_sdram_avl_0_waitrequest                                   //                                                        .waitrequest
	);

	wire          clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_waitrequest;      // clock_cross_axi_fpga_m0_agent:av_waitrequest -> clock_cross_axi_fpga_m0_translator:uav_waitrequest
	wire  [255:0] clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_readdata;         // clock_cross_axi_fpga_m0_agent:av_readdata -> clock_cross_axi_fpga_m0_translator:uav_readdata
	wire          clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_debugaccess;      // clock_cross_axi_fpga_m0_translator:uav_debugaccess -> clock_cross_axi_fpga_m0_agent:av_debugaccess
	wire   [29:0] clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_address;          // clock_cross_axi_fpga_m0_translator:uav_address -> clock_cross_axi_fpga_m0_agent:av_address
	wire          clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_read;             // clock_cross_axi_fpga_m0_translator:uav_read -> clock_cross_axi_fpga_m0_agent:av_read
	wire   [31:0] clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_byteenable;       // clock_cross_axi_fpga_m0_translator:uav_byteenable -> clock_cross_axi_fpga_m0_agent:av_byteenable
	wire          clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_readdatavalid;    // clock_cross_axi_fpga_m0_agent:av_readdatavalid -> clock_cross_axi_fpga_m0_translator:uav_readdatavalid
	wire          clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_lock;             // clock_cross_axi_fpga_m0_translator:uav_lock -> clock_cross_axi_fpga_m0_agent:av_lock
	wire          clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_write;            // clock_cross_axi_fpga_m0_translator:uav_write -> clock_cross_axi_fpga_m0_agent:av_write
	wire  [255:0] clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_writedata;        // clock_cross_axi_fpga_m0_translator:uav_writedata -> clock_cross_axi_fpga_m0_agent:av_writedata
	wire    [9:0] clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_burstcount;       // clock_cross_axi_fpga_m0_translator:uav_burstcount -> clock_cross_axi_fpga_m0_agent:av_burstcount
	wire          rsp_mux_src_valid;                                                             // rsp_mux:src_valid -> clock_cross_axi_fpga_m0_agent:rp_valid
	wire  [358:0] rsp_mux_src_data;                                                              // rsp_mux:src_data -> clock_cross_axi_fpga_m0_agent:rp_data
	wire          rsp_mux_src_ready;                                                             // clock_cross_axi_fpga_m0_agent:rp_ready -> rsp_mux:src_ready
	wire    [1:0] rsp_mux_src_channel;                                                           // rsp_mux:src_channel -> clock_cross_axi_fpga_m0_agent:rp_channel
	wire          rsp_mux_src_startofpacket;                                                     // rsp_mux:src_startofpacket -> clock_cross_axi_fpga_m0_agent:rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                                       // rsp_mux:src_endofpacket -> clock_cross_axi_fpga_m0_agent:rp_endofpacket
	wire          clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_waitrequest;   // clock_cross_kernel_mem0_m0_agent:av_waitrequest -> clock_cross_kernel_mem0_m0_translator:uav_waitrequest
	wire  [255:0] clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_readdata;      // clock_cross_kernel_mem0_m0_agent:av_readdata -> clock_cross_kernel_mem0_m0_translator:uav_readdata
	wire          clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_debugaccess;   // clock_cross_kernel_mem0_m0_translator:uav_debugaccess -> clock_cross_kernel_mem0_m0_agent:av_debugaccess
	wire   [29:0] clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_address;       // clock_cross_kernel_mem0_m0_translator:uav_address -> clock_cross_kernel_mem0_m0_agent:av_address
	wire          clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_read;          // clock_cross_kernel_mem0_m0_translator:uav_read -> clock_cross_kernel_mem0_m0_agent:av_read
	wire   [31:0] clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_byteenable;    // clock_cross_kernel_mem0_m0_translator:uav_byteenable -> clock_cross_kernel_mem0_m0_agent:av_byteenable
	wire          clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_readdatavalid; // clock_cross_kernel_mem0_m0_agent:av_readdatavalid -> clock_cross_kernel_mem0_m0_translator:uav_readdatavalid
	wire          clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_lock;          // clock_cross_kernel_mem0_m0_translator:uav_lock -> clock_cross_kernel_mem0_m0_agent:av_lock
	wire          clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_write;         // clock_cross_kernel_mem0_m0_translator:uav_write -> clock_cross_kernel_mem0_m0_agent:av_write
	wire  [255:0] clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_writedata;     // clock_cross_kernel_mem0_m0_translator:uav_writedata -> clock_cross_kernel_mem0_m0_agent:av_writedata
	wire    [9:0] clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_burstcount;    // clock_cross_kernel_mem0_m0_translator:uav_burstcount -> clock_cross_kernel_mem0_m0_agent:av_burstcount
	wire          rsp_mux_001_src_valid;                                                         // rsp_mux_001:src_valid -> clock_cross_kernel_mem0_m0_agent:rp_valid
	wire  [358:0] rsp_mux_001_src_data;                                                          // rsp_mux_001:src_data -> clock_cross_kernel_mem0_m0_agent:rp_data
	wire          rsp_mux_001_src_ready;                                                         // clock_cross_kernel_mem0_m0_agent:rp_ready -> rsp_mux_001:src_ready
	wire    [1:0] rsp_mux_001_src_channel;                                                       // rsp_mux_001:src_channel -> clock_cross_kernel_mem0_m0_agent:rp_channel
	wire          rsp_mux_001_src_startofpacket;                                                 // rsp_mux_001:src_startofpacket -> clock_cross_kernel_mem0_m0_agent:rp_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                                   // rsp_mux_001:src_endofpacket -> clock_cross_kernel_mem0_m0_agent:rp_endofpacket
	wire  [255:0] fpga_sdram_avl_0_agent_m0_readdata;                                            // fpga_sdram_avl_0_translator:uav_readdata -> fpga_sdram_avl_0_agent:m0_readdata
	wire          fpga_sdram_avl_0_agent_m0_waitrequest;                                         // fpga_sdram_avl_0_translator:uav_waitrequest -> fpga_sdram_avl_0_agent:m0_waitrequest
	wire          fpga_sdram_avl_0_agent_m0_debugaccess;                                         // fpga_sdram_avl_0_agent:m0_debugaccess -> fpga_sdram_avl_0_translator:uav_debugaccess
	wire   [29:0] fpga_sdram_avl_0_agent_m0_address;                                             // fpga_sdram_avl_0_agent:m0_address -> fpga_sdram_avl_0_translator:uav_address
	wire   [31:0] fpga_sdram_avl_0_agent_m0_byteenable;                                          // fpga_sdram_avl_0_agent:m0_byteenable -> fpga_sdram_avl_0_translator:uav_byteenable
	wire          fpga_sdram_avl_0_agent_m0_read;                                                // fpga_sdram_avl_0_agent:m0_read -> fpga_sdram_avl_0_translator:uav_read
	wire          fpga_sdram_avl_0_agent_m0_readdatavalid;                                       // fpga_sdram_avl_0_translator:uav_readdatavalid -> fpga_sdram_avl_0_agent:m0_readdatavalid
	wire          fpga_sdram_avl_0_agent_m0_lock;                                                // fpga_sdram_avl_0_agent:m0_lock -> fpga_sdram_avl_0_translator:uav_lock
	wire  [255:0] fpga_sdram_avl_0_agent_m0_writedata;                                           // fpga_sdram_avl_0_agent:m0_writedata -> fpga_sdram_avl_0_translator:uav_writedata
	wire          fpga_sdram_avl_0_agent_m0_write;                                               // fpga_sdram_avl_0_agent:m0_write -> fpga_sdram_avl_0_translator:uav_write
	wire    [9:0] fpga_sdram_avl_0_agent_m0_burstcount;                                          // fpga_sdram_avl_0_agent:m0_burstcount -> fpga_sdram_avl_0_translator:uav_burstcount
	wire          fpga_sdram_avl_0_agent_rf_source_valid;                                        // fpga_sdram_avl_0_agent:rf_source_valid -> fpga_sdram_avl_0_agent_rsp_fifo:in_valid
	wire  [359:0] fpga_sdram_avl_0_agent_rf_source_data;                                         // fpga_sdram_avl_0_agent:rf_source_data -> fpga_sdram_avl_0_agent_rsp_fifo:in_data
	wire          fpga_sdram_avl_0_agent_rf_source_ready;                                        // fpga_sdram_avl_0_agent_rsp_fifo:in_ready -> fpga_sdram_avl_0_agent:rf_source_ready
	wire          fpga_sdram_avl_0_agent_rf_source_startofpacket;                                // fpga_sdram_avl_0_agent:rf_source_startofpacket -> fpga_sdram_avl_0_agent_rsp_fifo:in_startofpacket
	wire          fpga_sdram_avl_0_agent_rf_source_endofpacket;                                  // fpga_sdram_avl_0_agent:rf_source_endofpacket -> fpga_sdram_avl_0_agent_rsp_fifo:in_endofpacket
	wire          fpga_sdram_avl_0_agent_rsp_fifo_out_valid;                                     // fpga_sdram_avl_0_agent_rsp_fifo:out_valid -> fpga_sdram_avl_0_agent:rf_sink_valid
	wire  [359:0] fpga_sdram_avl_0_agent_rsp_fifo_out_data;                                      // fpga_sdram_avl_0_agent_rsp_fifo:out_data -> fpga_sdram_avl_0_agent:rf_sink_data
	wire          fpga_sdram_avl_0_agent_rsp_fifo_out_ready;                                     // fpga_sdram_avl_0_agent:rf_sink_ready -> fpga_sdram_avl_0_agent_rsp_fifo:out_ready
	wire          fpga_sdram_avl_0_agent_rsp_fifo_out_startofpacket;                             // fpga_sdram_avl_0_agent_rsp_fifo:out_startofpacket -> fpga_sdram_avl_0_agent:rf_sink_startofpacket
	wire          fpga_sdram_avl_0_agent_rsp_fifo_out_endofpacket;                               // fpga_sdram_avl_0_agent_rsp_fifo:out_endofpacket -> fpga_sdram_avl_0_agent:rf_sink_endofpacket
	wire          cmd_mux_src_valid;                                                             // cmd_mux:src_valid -> fpga_sdram_avl_0_agent:cp_valid
	wire  [358:0] cmd_mux_src_data;                                                              // cmd_mux:src_data -> fpga_sdram_avl_0_agent:cp_data
	wire          cmd_mux_src_ready;                                                             // fpga_sdram_avl_0_agent:cp_ready -> cmd_mux:src_ready
	wire    [1:0] cmd_mux_src_channel;                                                           // cmd_mux:src_channel -> fpga_sdram_avl_0_agent:cp_channel
	wire          cmd_mux_src_startofpacket;                                                     // cmd_mux:src_startofpacket -> fpga_sdram_avl_0_agent:cp_startofpacket
	wire          cmd_mux_src_endofpacket;                                                       // cmd_mux:src_endofpacket -> fpga_sdram_avl_0_agent:cp_endofpacket
	wire          clock_cross_axi_fpga_m0_agent_cp_valid;                                        // clock_cross_axi_fpga_m0_agent:cp_valid -> router:sink_valid
	wire  [358:0] clock_cross_axi_fpga_m0_agent_cp_data;                                         // clock_cross_axi_fpga_m0_agent:cp_data -> router:sink_data
	wire          clock_cross_axi_fpga_m0_agent_cp_ready;                                        // router:sink_ready -> clock_cross_axi_fpga_m0_agent:cp_ready
	wire          clock_cross_axi_fpga_m0_agent_cp_startofpacket;                                // clock_cross_axi_fpga_m0_agent:cp_startofpacket -> router:sink_startofpacket
	wire          clock_cross_axi_fpga_m0_agent_cp_endofpacket;                                  // clock_cross_axi_fpga_m0_agent:cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                              // router:src_valid -> cmd_demux:sink_valid
	wire  [358:0] router_src_data;                                                               // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                                              // cmd_demux:sink_ready -> router:src_ready
	wire    [1:0] router_src_channel;                                                            // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                                      // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                                        // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          clock_cross_kernel_mem0_m0_agent_cp_valid;                                     // clock_cross_kernel_mem0_m0_agent:cp_valid -> router_001:sink_valid
	wire  [358:0] clock_cross_kernel_mem0_m0_agent_cp_data;                                      // clock_cross_kernel_mem0_m0_agent:cp_data -> router_001:sink_data
	wire          clock_cross_kernel_mem0_m0_agent_cp_ready;                                     // router_001:sink_ready -> clock_cross_kernel_mem0_m0_agent:cp_ready
	wire          clock_cross_kernel_mem0_m0_agent_cp_startofpacket;                             // clock_cross_kernel_mem0_m0_agent:cp_startofpacket -> router_001:sink_startofpacket
	wire          clock_cross_kernel_mem0_m0_agent_cp_endofpacket;                               // clock_cross_kernel_mem0_m0_agent:cp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                          // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [358:0] router_001_src_data;                                                           // router_001:src_data -> cmd_demux_001:sink_data
	wire          router_001_src_ready;                                                          // cmd_demux_001:sink_ready -> router_001:src_ready
	wire    [1:0] router_001_src_channel;                                                        // router_001:src_channel -> cmd_demux_001:sink_channel
	wire          router_001_src_startofpacket;                                                  // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          router_001_src_endofpacket;                                                    // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          fpga_sdram_avl_0_agent_rp_valid;                                               // fpga_sdram_avl_0_agent:rp_valid -> router_002:sink_valid
	wire  [358:0] fpga_sdram_avl_0_agent_rp_data;                                                // fpga_sdram_avl_0_agent:rp_data -> router_002:sink_data
	wire          fpga_sdram_avl_0_agent_rp_ready;                                               // router_002:sink_ready -> fpga_sdram_avl_0_agent:rp_ready
	wire          fpga_sdram_avl_0_agent_rp_startofpacket;                                       // fpga_sdram_avl_0_agent:rp_startofpacket -> router_002:sink_startofpacket
	wire          fpga_sdram_avl_0_agent_rp_endofpacket;                                         // fpga_sdram_avl_0_agent:rp_endofpacket -> router_002:sink_endofpacket
	wire          router_002_src_valid;                                                          // router_002:src_valid -> rsp_demux:sink_valid
	wire  [358:0] router_002_src_data;                                                           // router_002:src_data -> rsp_demux:sink_data
	wire          router_002_src_ready;                                                          // rsp_demux:sink_ready -> router_002:src_ready
	wire    [1:0] router_002_src_channel;                                                        // router_002:src_channel -> rsp_demux:sink_channel
	wire          router_002_src_startofpacket;                                                  // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_002_src_endofpacket;                                                    // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          cmd_demux_src0_valid;                                                          // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [358:0] cmd_demux_src0_data;                                                           // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                          // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [1:0] cmd_demux_src0_channel;                                                        // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                                  // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                    // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                                      // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
	wire  [358:0] cmd_demux_001_src0_data;                                                       // cmd_demux_001:src0_data -> cmd_mux:sink1_data
	wire          cmd_demux_001_src0_ready;                                                      // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
	wire    [1:0] cmd_demux_001_src0_channel;                                                    // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
	wire          cmd_demux_001_src0_startofpacket;                                              // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                                // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
	wire          rsp_demux_src0_valid;                                                          // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [358:0] rsp_demux_src0_data;                                                           // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                          // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [1:0] rsp_demux_src0_channel;                                                        // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                                  // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                    // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_src1_valid;                                                          // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
	wire  [358:0] rsp_demux_src1_data;                                                           // rsp_demux:src1_data -> rsp_mux_001:sink0_data
	wire          rsp_demux_src1_ready;                                                          // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
	wire    [1:0] rsp_demux_src1_channel;                                                        // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
	wire          rsp_demux_src1_startofpacket;                                                  // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          rsp_demux_src1_endofpacket;                                                    // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          fpga_sdram_avl_0_agent_rdata_fifo_src_valid;                                   // fpga_sdram_avl_0_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
	wire  [257:0] fpga_sdram_avl_0_agent_rdata_fifo_src_data;                                    // fpga_sdram_avl_0_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
	wire          fpga_sdram_avl_0_agent_rdata_fifo_src_ready;                                   // avalon_st_adapter:in_0_ready -> fpga_sdram_avl_0_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_out_0_valid;                                                 // avalon_st_adapter:out_0_valid -> fpga_sdram_avl_0_agent:rdata_fifo_sink_valid
	wire  [257:0] avalon_st_adapter_out_0_data;                                                  // avalon_st_adapter:out_0_data -> fpga_sdram_avl_0_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                                 // fpga_sdram_avl_0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                                 // avalon_st_adapter:out_0_error -> fpga_sdram_avl_0_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (30),
		.AV_DATA_W                   (256),
		.AV_BURSTCOUNT_W             (5),
		.AV_BYTEENABLE_W             (32),
		.UAV_ADDRESS_W               (30),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (32),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) clock_cross_axi_fpga_m0_translator (
		.clk                    (pll_outclk0_clk),                                                            //                       clk.clk
		.reset                  (clock_cross_axi_fpga_m0_reset_reset_bridge_in_reset_reset),                  //                     reset.reset
		.uav_address            (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (clock_cross_axi_fpga_m0_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (clock_cross_axi_fpga_m0_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (clock_cross_axi_fpga_m0_burstcount),                                         //                          .burstcount
		.av_byteenable          (clock_cross_axi_fpga_m0_byteenable),                                         //                          .byteenable
		.av_read                (clock_cross_axi_fpga_m0_read),                                               //                          .read
		.av_readdata            (clock_cross_axi_fpga_m0_readdata),                                           //                          .readdata
		.av_readdatavalid       (clock_cross_axi_fpga_m0_readdatavalid),                                      //                          .readdatavalid
		.av_write               (clock_cross_axi_fpga_m0_write),                                              //                          .write
		.av_writedata           (clock_cross_axi_fpga_m0_writedata),                                          //                          .writedata
		.av_debugaccess         (clock_cross_axi_fpga_m0_debugaccess),                                        //                          .debugaccess
		.av_beginbursttransfer  (1'b0),                                                                       //               (terminated)
		.av_begintransfer       (1'b0),                                                                       //               (terminated)
		.av_chipselect          (1'b0),                                                                       //               (terminated)
		.av_lock                (1'b0),                                                                       //               (terminated)
		.uav_clken              (),                                                                           //               (terminated)
		.av_clken               (1'b1),                                                                       //               (terminated)
		.uav_response           (2'b00),                                                                      //               (terminated)
		.av_response            (),                                                                           //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                       //               (terminated)
		.av_writeresponsevalid  ()                                                                            //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (25),
		.AV_DATA_W                   (256),
		.AV_BURSTCOUNT_W             (5),
		.AV_BYTEENABLE_W             (32),
		.UAV_ADDRESS_W               (30),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (32),
		.AV_ADDRESS_SYMBOLS          (0),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) clock_cross_kernel_mem0_m0_translator (
		.clk                    (pll_outclk0_clk),                                                               //                       clk.clk
		.reset                  (clock_cross_axi_fpga_m0_reset_reset_bridge_in_reset_reset),                     //                     reset.reset
		.uav_address            (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (clock_cross_kernel_mem0_m0_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (clock_cross_kernel_mem0_m0_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (clock_cross_kernel_mem0_m0_burstcount),                                         //                          .burstcount
		.av_byteenable          (clock_cross_kernel_mem0_m0_byteenable),                                         //                          .byteenable
		.av_read                (clock_cross_kernel_mem0_m0_read),                                               //                          .read
		.av_readdata            (clock_cross_kernel_mem0_m0_readdata),                                           //                          .readdata
		.av_readdatavalid       (clock_cross_kernel_mem0_m0_readdatavalid),                                      //                          .readdatavalid
		.av_write               (clock_cross_kernel_mem0_m0_write),                                              //                          .write
		.av_writedata           (clock_cross_kernel_mem0_m0_writedata),                                          //                          .writedata
		.av_debugaccess         (clock_cross_kernel_mem0_m0_debugaccess),                                        //                          .debugaccess
		.av_beginbursttransfer  (1'b0),                                                                          //               (terminated)
		.av_begintransfer       (1'b0),                                                                          //               (terminated)
		.av_chipselect          (1'b0),                                                                          //               (terminated)
		.av_lock                (1'b0),                                                                          //               (terminated)
		.uav_clken              (),                                                                              //               (terminated)
		.av_clken               (1'b1),                                                                          //               (terminated)
		.uav_response           (2'b00),                                                                         //               (terminated)
		.av_response            (),                                                                              //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                          //               (terminated)
		.av_writeresponsevalid  ()                                                                               //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (25),
		.AV_DATA_W                      (256),
		.UAV_DATA_W                     (256),
		.AV_BURSTCOUNT_W                (5),
		.AV_BYTEENABLE_W                (32),
		.UAV_BYTEENABLE_W               (32),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (10),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (32),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) fpga_sdram_avl_0_translator (
		.clk                    (pll_outclk0_clk),                                               //                      clk.clk
		.reset                  (fpga_sdram_avl_0_translator_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (fpga_sdram_avl_0_agent_m0_address),                             // avalon_universal_slave_0.address
		.uav_burstcount         (fpga_sdram_avl_0_agent_m0_burstcount),                          //                         .burstcount
		.uav_read               (fpga_sdram_avl_0_agent_m0_read),                                //                         .read
		.uav_write              (fpga_sdram_avl_0_agent_m0_write),                               //                         .write
		.uav_waitrequest        (fpga_sdram_avl_0_agent_m0_waitrequest),                         //                         .waitrequest
		.uav_readdatavalid      (fpga_sdram_avl_0_agent_m0_readdatavalid),                       //                         .readdatavalid
		.uav_byteenable         (fpga_sdram_avl_0_agent_m0_byteenable),                          //                         .byteenable
		.uav_readdata           (fpga_sdram_avl_0_agent_m0_readdata),                            //                         .readdata
		.uav_writedata          (fpga_sdram_avl_0_agent_m0_writedata),                           //                         .writedata
		.uav_lock               (fpga_sdram_avl_0_agent_m0_lock),                                //                         .lock
		.uav_debugaccess        (fpga_sdram_avl_0_agent_m0_debugaccess),                         //                         .debugaccess
		.av_address             (fpga_sdram_avl_0_address),                                      //      avalon_anti_slave_0.address
		.av_write               (fpga_sdram_avl_0_write),                                        //                         .write
		.av_read                (fpga_sdram_avl_0_read),                                         //                         .read
		.av_readdata            (fpga_sdram_avl_0_readdata),                                     //                         .readdata
		.av_writedata           (fpga_sdram_avl_0_writedata),                                    //                         .writedata
		.av_beginbursttransfer  (fpga_sdram_avl_0_beginbursttransfer),                           //                         .beginbursttransfer
		.av_burstcount          (fpga_sdram_avl_0_burstcount),                                   //                         .burstcount
		.av_byteenable          (fpga_sdram_avl_0_byteenable),                                   //                         .byteenable
		.av_readdatavalid       (fpga_sdram_avl_0_readdatavalid),                                //                         .readdatavalid
		.av_waitrequest         (fpga_sdram_avl_0_waitrequest),                                  //                         .waitrequest
		.av_begintransfer       (),                                                              //              (terminated)
		.av_writebyteenable     (),                                                              //              (terminated)
		.av_lock                (),                                                              //              (terminated)
		.av_chipselect          (),                                                              //              (terminated)
		.av_clken               (),                                                              //              (terminated)
		.uav_clken              (1'b0),                                                          //              (terminated)
		.av_debugaccess         (),                                                              //              (terminated)
		.av_outputenable        (),                                                              //              (terminated)
		.uav_response           (),                                                              //              (terminated)
		.av_response            (2'b00),                                                         //              (terminated)
		.uav_writeresponsevalid (),                                                              //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                           //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (358),
		.PKT_ORI_BURST_SIZE_L      (356),
		.PKT_RESPONSE_STATUS_H     (355),
		.PKT_RESPONSE_STATUS_L     (354),
		.PKT_QOS_H                 (343),
		.PKT_QOS_L                 (343),
		.PKT_DATA_SIDEBAND_H       (341),
		.PKT_DATA_SIDEBAND_L       (341),
		.PKT_ADDR_SIDEBAND_H       (340),
		.PKT_ADDR_SIDEBAND_L       (340),
		.PKT_BURST_TYPE_H          (339),
		.PKT_BURST_TYPE_L          (338),
		.PKT_CACHE_H               (353),
		.PKT_CACHE_L               (350),
		.PKT_THREAD_ID_H           (346),
		.PKT_THREAD_ID_L           (346),
		.PKT_BURST_SIZE_H          (337),
		.PKT_BURST_SIZE_L          (335),
		.PKT_TRANS_EXCLUSIVE       (323),
		.PKT_TRANS_LOCK            (322),
		.PKT_BEGIN_BURST           (342),
		.PKT_PROTECTION_H          (349),
		.PKT_PROTECTION_L          (347),
		.PKT_BURSTWRAP_H           (334),
		.PKT_BURSTWRAP_L           (334),
		.PKT_BYTE_CNT_H            (333),
		.PKT_BYTE_CNT_L            (324),
		.PKT_ADDR_H                (317),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (318),
		.PKT_TRANS_POSTED          (319),
		.PKT_TRANS_WRITE           (320),
		.PKT_TRANS_READ            (321),
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_SRC_ID_H              (344),
		.PKT_SRC_ID_L              (344),
		.PKT_DEST_ID_H             (345),
		.PKT_DEST_ID_L             (345),
		.ST_DATA_W                 (359),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) clock_cross_axi_fpga_m0_agent (
		.clk                   (pll_outclk0_clk),                                                            //       clk.clk
		.reset                 (clock_cross_axi_fpga_m0_reset_reset_bridge_in_reset_reset),                  // clk_reset.reset
		.av_address            (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (clock_cross_axi_fpga_m0_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (clock_cross_axi_fpga_m0_agent_cp_valid),                                     //        cp.valid
		.cp_data               (clock_cross_axi_fpga_m0_agent_cp_data),                                      //          .data
		.cp_startofpacket      (clock_cross_axi_fpga_m0_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (clock_cross_axi_fpga_m0_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (clock_cross_axi_fpga_m0_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_src_valid),                                                          //        rp.valid
		.rp_data               (rsp_mux_src_data),                                                           //          .data
		.rp_channel            (rsp_mux_src_channel),                                                        //          .channel
		.rp_startofpacket      (rsp_mux_src_startofpacket),                                                  //          .startofpacket
		.rp_endofpacket        (rsp_mux_src_endofpacket),                                                    //          .endofpacket
		.rp_ready              (rsp_mux_src_ready),                                                          //          .ready
		.av_response           (),                                                                           // (terminated)
		.av_writeresponsevalid ()                                                                            // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (358),
		.PKT_ORI_BURST_SIZE_L      (356),
		.PKT_RESPONSE_STATUS_H     (355),
		.PKT_RESPONSE_STATUS_L     (354),
		.PKT_QOS_H                 (343),
		.PKT_QOS_L                 (343),
		.PKT_DATA_SIDEBAND_H       (341),
		.PKT_DATA_SIDEBAND_L       (341),
		.PKT_ADDR_SIDEBAND_H       (340),
		.PKT_ADDR_SIDEBAND_L       (340),
		.PKT_BURST_TYPE_H          (339),
		.PKT_BURST_TYPE_L          (338),
		.PKT_CACHE_H               (353),
		.PKT_CACHE_L               (350),
		.PKT_THREAD_ID_H           (346),
		.PKT_THREAD_ID_L           (346),
		.PKT_BURST_SIZE_H          (337),
		.PKT_BURST_SIZE_L          (335),
		.PKT_TRANS_EXCLUSIVE       (323),
		.PKT_TRANS_LOCK            (322),
		.PKT_BEGIN_BURST           (342),
		.PKT_PROTECTION_H          (349),
		.PKT_PROTECTION_L          (347),
		.PKT_BURSTWRAP_H           (334),
		.PKT_BURSTWRAP_L           (334),
		.PKT_BYTE_CNT_H            (333),
		.PKT_BYTE_CNT_L            (324),
		.PKT_ADDR_H                (317),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (318),
		.PKT_TRANS_POSTED          (319),
		.PKT_TRANS_WRITE           (320),
		.PKT_TRANS_READ            (321),
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_SRC_ID_H              (344),
		.PKT_SRC_ID_L              (344),
		.PKT_DEST_ID_H             (345),
		.PKT_DEST_ID_L             (345),
		.ST_DATA_W                 (359),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) clock_cross_kernel_mem0_m0_agent (
		.clk                   (pll_outclk0_clk),                                                               //       clk.clk
		.reset                 (clock_cross_axi_fpga_m0_reset_reset_bridge_in_reset_reset),                     // clk_reset.reset
		.av_address            (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (clock_cross_kernel_mem0_m0_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (clock_cross_kernel_mem0_m0_agent_cp_valid),                                     //        cp.valid
		.cp_data               (clock_cross_kernel_mem0_m0_agent_cp_data),                                      //          .data
		.cp_startofpacket      (clock_cross_kernel_mem0_m0_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (clock_cross_kernel_mem0_m0_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (clock_cross_kernel_mem0_m0_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_001_src_valid),                                                         //        rp.valid
		.rp_data               (rsp_mux_001_src_data),                                                          //          .data
		.rp_channel            (rsp_mux_001_src_channel),                                                       //          .channel
		.rp_startofpacket      (rsp_mux_001_src_startofpacket),                                                 //          .startofpacket
		.rp_endofpacket        (rsp_mux_001_src_endofpacket),                                                   //          .endofpacket
		.rp_ready              (rsp_mux_001_src_ready),                                                         //          .ready
		.av_response           (),                                                                              // (terminated)
		.av_writeresponsevalid ()                                                                               // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (358),
		.PKT_ORI_BURST_SIZE_L      (356),
		.PKT_RESPONSE_STATUS_H     (355),
		.PKT_RESPONSE_STATUS_L     (354),
		.PKT_BURST_SIZE_H          (337),
		.PKT_BURST_SIZE_L          (335),
		.PKT_TRANS_LOCK            (322),
		.PKT_BEGIN_BURST           (342),
		.PKT_PROTECTION_H          (349),
		.PKT_PROTECTION_L          (347),
		.PKT_BURSTWRAP_H           (334),
		.PKT_BURSTWRAP_L           (334),
		.PKT_BYTE_CNT_H            (333),
		.PKT_BYTE_CNT_L            (324),
		.PKT_ADDR_H                (317),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (318),
		.PKT_TRANS_POSTED          (319),
		.PKT_TRANS_WRITE           (320),
		.PKT_TRANS_READ            (321),
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_SRC_ID_H              (344),
		.PKT_SRC_ID_L              (344),
		.PKT_DEST_ID_H             (345),
		.PKT_DEST_ID_L             (345),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (359),
		.AVS_BURSTCOUNT_W          (10),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) fpga_sdram_avl_0_agent (
		.clk                     (pll_outclk0_clk),                                               //             clk.clk
		.reset                   (fpga_sdram_avl_0_translator_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (fpga_sdram_avl_0_agent_m0_address),                             //              m0.address
		.m0_burstcount           (fpga_sdram_avl_0_agent_m0_burstcount),                          //                .burstcount
		.m0_byteenable           (fpga_sdram_avl_0_agent_m0_byteenable),                          //                .byteenable
		.m0_debugaccess          (fpga_sdram_avl_0_agent_m0_debugaccess),                         //                .debugaccess
		.m0_lock                 (fpga_sdram_avl_0_agent_m0_lock),                                //                .lock
		.m0_readdata             (fpga_sdram_avl_0_agent_m0_readdata),                            //                .readdata
		.m0_readdatavalid        (fpga_sdram_avl_0_agent_m0_readdatavalid),                       //                .readdatavalid
		.m0_read                 (fpga_sdram_avl_0_agent_m0_read),                                //                .read
		.m0_waitrequest          (fpga_sdram_avl_0_agent_m0_waitrequest),                         //                .waitrequest
		.m0_writedata            (fpga_sdram_avl_0_agent_m0_writedata),                           //                .writedata
		.m0_write                (fpga_sdram_avl_0_agent_m0_write),                               //                .write
		.rp_endofpacket          (fpga_sdram_avl_0_agent_rp_endofpacket),                         //              rp.endofpacket
		.rp_ready                (fpga_sdram_avl_0_agent_rp_ready),                               //                .ready
		.rp_valid                (fpga_sdram_avl_0_agent_rp_valid),                               //                .valid
		.rp_data                 (fpga_sdram_avl_0_agent_rp_data),                                //                .data
		.rp_startofpacket        (fpga_sdram_avl_0_agent_rp_startofpacket),                       //                .startofpacket
		.cp_ready                (cmd_mux_src_ready),                                             //              cp.ready
		.cp_valid                (cmd_mux_src_valid),                                             //                .valid
		.cp_data                 (cmd_mux_src_data),                                              //                .data
		.cp_startofpacket        (cmd_mux_src_startofpacket),                                     //                .startofpacket
		.cp_endofpacket          (cmd_mux_src_endofpacket),                                       //                .endofpacket
		.cp_channel              (cmd_mux_src_channel),                                           //                .channel
		.rf_sink_ready           (fpga_sdram_avl_0_agent_rsp_fifo_out_ready),                     //         rf_sink.ready
		.rf_sink_valid           (fpga_sdram_avl_0_agent_rsp_fifo_out_valid),                     //                .valid
		.rf_sink_startofpacket   (fpga_sdram_avl_0_agent_rsp_fifo_out_startofpacket),             //                .startofpacket
		.rf_sink_endofpacket     (fpga_sdram_avl_0_agent_rsp_fifo_out_endofpacket),               //                .endofpacket
		.rf_sink_data            (fpga_sdram_avl_0_agent_rsp_fifo_out_data),                      //                .data
		.rf_source_ready         (fpga_sdram_avl_0_agent_rf_source_ready),                        //       rf_source.ready
		.rf_source_valid         (fpga_sdram_avl_0_agent_rf_source_valid),                        //                .valid
		.rf_source_startofpacket (fpga_sdram_avl_0_agent_rf_source_startofpacket),                //                .startofpacket
		.rf_source_endofpacket   (fpga_sdram_avl_0_agent_rf_source_endofpacket),                  //                .endofpacket
		.rf_source_data          (fpga_sdram_avl_0_agent_rf_source_data),                         //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                 // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                 //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                  //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                 //                .error
		.rdata_fifo_src_ready    (fpga_sdram_avl_0_agent_rdata_fifo_src_ready),                   //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (fpga_sdram_avl_0_agent_rdata_fifo_src_valid),                   //                .valid
		.rdata_fifo_src_data     (fpga_sdram_avl_0_agent_rdata_fifo_src_data),                    //                .data
		.m0_response             (2'b00),                                                         //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                           //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (360),
		.FIFO_DEPTH          (49),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) fpga_sdram_avl_0_agent_rsp_fifo (
		.clk               (pll_outclk0_clk),                                               //       clk.clk
		.reset             (fpga_sdram_avl_0_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (fpga_sdram_avl_0_agent_rf_source_data),                         //        in.data
		.in_valid          (fpga_sdram_avl_0_agent_rf_source_valid),                        //          .valid
		.in_ready          (fpga_sdram_avl_0_agent_rf_source_ready),                        //          .ready
		.in_startofpacket  (fpga_sdram_avl_0_agent_rf_source_startofpacket),                //          .startofpacket
		.in_endofpacket    (fpga_sdram_avl_0_agent_rf_source_endofpacket),                  //          .endofpacket
		.out_data          (fpga_sdram_avl_0_agent_rsp_fifo_out_data),                      //       out.data
		.out_valid         (fpga_sdram_avl_0_agent_rsp_fifo_out_valid),                     //          .valid
		.out_ready         (fpga_sdram_avl_0_agent_rsp_fifo_out_ready),                     //          .ready
		.out_startofpacket (fpga_sdram_avl_0_agent_rsp_fifo_out_startofpacket),             //          .startofpacket
		.out_endofpacket   (fpga_sdram_avl_0_agent_rsp_fifo_out_endofpacket),               //          .endofpacket
		.csr_address       (2'b00),                                                         // (terminated)
		.csr_read          (1'b0),                                                          // (terminated)
		.csr_write         (1'b0),                                                          // (terminated)
		.csr_readdata      (),                                                              // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                          // (terminated)
		.almost_full_data  (),                                                              // (terminated)
		.almost_empty_data (),                                                              // (terminated)
		.in_empty          (1'b0),                                                          // (terminated)
		.out_empty         (),                                                              // (terminated)
		.in_error          (1'b0),                                                          // (terminated)
		.out_error         (),                                                              // (terminated)
		.in_channel        (1'b0),                                                          // (terminated)
		.out_channel       ()                                                               // (terminated)
	);

	system_acl_iface_mm_interconnect_5_router router (
		.sink_ready         (clock_cross_axi_fpga_m0_agent_cp_ready),                    //      sink.ready
		.sink_valid         (clock_cross_axi_fpga_m0_agent_cp_valid),                    //          .valid
		.sink_data          (clock_cross_axi_fpga_m0_agent_cp_data),                     //          .data
		.sink_startofpacket (clock_cross_axi_fpga_m0_agent_cp_startofpacket),            //          .startofpacket
		.sink_endofpacket   (clock_cross_axi_fpga_m0_agent_cp_endofpacket),              //          .endofpacket
		.clk                (pll_outclk0_clk),                                           //       clk.clk
		.reset              (clock_cross_axi_fpga_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                                          //       src.ready
		.src_valid          (router_src_valid),                                          //          .valid
		.src_data           (router_src_data),                                           //          .data
		.src_channel        (router_src_channel),                                        //          .channel
		.src_startofpacket  (router_src_startofpacket),                                  //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                     //          .endofpacket
	);

	system_acl_iface_mm_interconnect_5_router router_001 (
		.sink_ready         (clock_cross_kernel_mem0_m0_agent_cp_ready),                 //      sink.ready
		.sink_valid         (clock_cross_kernel_mem0_m0_agent_cp_valid),                 //          .valid
		.sink_data          (clock_cross_kernel_mem0_m0_agent_cp_data),                  //          .data
		.sink_startofpacket (clock_cross_kernel_mem0_m0_agent_cp_startofpacket),         //          .startofpacket
		.sink_endofpacket   (clock_cross_kernel_mem0_m0_agent_cp_endofpacket),           //          .endofpacket
		.clk                (pll_outclk0_clk),                                           //       clk.clk
		.reset              (clock_cross_axi_fpga_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                                      //       src.ready
		.src_valid          (router_001_src_valid),                                      //          .valid
		.src_data           (router_001_src_data),                                       //          .data
		.src_channel        (router_001_src_channel),                                    //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                              //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                 //          .endofpacket
	);

	system_acl_iface_mm_interconnect_5_router_002 router_002 (
		.sink_ready         (fpga_sdram_avl_0_agent_rp_ready),                               //      sink.ready
		.sink_valid         (fpga_sdram_avl_0_agent_rp_valid),                               //          .valid
		.sink_data          (fpga_sdram_avl_0_agent_rp_data),                                //          .data
		.sink_startofpacket (fpga_sdram_avl_0_agent_rp_startofpacket),                       //          .startofpacket
		.sink_endofpacket   (fpga_sdram_avl_0_agent_rp_endofpacket),                         //          .endofpacket
		.clk                (pll_outclk0_clk),                                               //       clk.clk
		.reset              (fpga_sdram_avl_0_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_002_src_ready),                                          //       src.ready
		.src_valid          (router_002_src_valid),                                          //          .valid
		.src_data           (router_002_src_data),                                           //          .data
		.src_channel        (router_002_src_channel),                                        //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                                  //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                                     //          .endofpacket
	);

	system_acl_iface_mm_interconnect_5_cmd_demux cmd_demux (
		.clk                (pll_outclk0_clk),                                           //       clk.clk
		.reset              (clock_cross_axi_fpga_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                                          //      sink.ready
		.sink_channel       (router_src_channel),                                        //          .channel
		.sink_data          (router_src_data),                                           //          .data
		.sink_startofpacket (router_src_startofpacket),                                  //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                                    //          .endofpacket
		.sink_valid         (router_src_valid),                                          //          .valid
		.src0_ready         (cmd_demux_src0_ready),                                      //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                      //          .valid
		.src0_data          (cmd_demux_src0_data),                                       //          .data
		.src0_channel       (cmd_demux_src0_channel),                                    //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                              //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket)                                 //          .endofpacket
	);

	system_acl_iface_mm_interconnect_5_cmd_demux cmd_demux_001 (
		.clk                (pll_outclk0_clk),                                           //       clk.clk
		.reset              (clock_cross_axi_fpga_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                                      //      sink.ready
		.sink_channel       (router_001_src_channel),                                    //          .channel
		.sink_data          (router_001_src_data),                                       //          .data
		.sink_startofpacket (router_001_src_startofpacket),                              //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                                //          .endofpacket
		.sink_valid         (router_001_src_valid),                                      //          .valid
		.src0_ready         (cmd_demux_001_src0_ready),                                  //      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                                  //          .valid
		.src0_data          (cmd_demux_001_src0_data),                                   //          .data
		.src0_channel       (cmd_demux_001_src0_channel),                                //          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),                          //          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket)                             //          .endofpacket
	);

	system_acl_iface_mm_interconnect_5_cmd_mux cmd_mux (
		.clk                 (pll_outclk0_clk),                                               //       clk.clk
		.reset               (fpga_sdram_avl_0_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                             //       src.ready
		.src_valid           (cmd_mux_src_valid),                                             //          .valid
		.src_data            (cmd_mux_src_data),                                              //          .data
		.src_channel         (cmd_mux_src_channel),                                           //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                     //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                       //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                                          //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                                          //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                                        //          .channel
		.sink0_data          (cmd_demux_src0_data),                                           //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                                  //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket),                                    //          .endofpacket
		.sink1_ready         (cmd_demux_001_src0_ready),                                      //     sink1.ready
		.sink1_valid         (cmd_demux_001_src0_valid),                                      //          .valid
		.sink1_channel       (cmd_demux_001_src0_channel),                                    //          .channel
		.sink1_data          (cmd_demux_001_src0_data),                                       //          .data
		.sink1_startofpacket (cmd_demux_001_src0_startofpacket),                              //          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src0_endofpacket)                                 //          .endofpacket
	);

	system_acl_iface_mm_interconnect_5_rsp_demux rsp_demux (
		.clk                (pll_outclk0_clk),                                               //       clk.clk
		.reset              (fpga_sdram_avl_0_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_002_src_ready),                                          //      sink.ready
		.sink_channel       (router_002_src_channel),                                        //          .channel
		.sink_data          (router_002_src_data),                                           //          .data
		.sink_startofpacket (router_002_src_startofpacket),                                  //          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                                    //          .endofpacket
		.sink_valid         (router_002_src_valid),                                          //          .valid
		.src0_ready         (rsp_demux_src0_ready),                                          //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                          //          .valid
		.src0_data          (rsp_demux_src0_data),                                           //          .data
		.src0_channel       (rsp_demux_src0_channel),                                        //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                  //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket),                                    //          .endofpacket
		.src1_ready         (rsp_demux_src1_ready),                                          //      src1.ready
		.src1_valid         (rsp_demux_src1_valid),                                          //          .valid
		.src1_data          (rsp_demux_src1_data),                                           //          .data
		.src1_channel       (rsp_demux_src1_channel),                                        //          .channel
		.src1_startofpacket (rsp_demux_src1_startofpacket),                                  //          .startofpacket
		.src1_endofpacket   (rsp_demux_src1_endofpacket)                                     //          .endofpacket
	);

	system_acl_iface_mm_interconnect_5_rsp_mux rsp_mux (
		.clk                 (pll_outclk0_clk),                                           //       clk.clk
		.reset               (clock_cross_axi_fpga_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                         //       src.ready
		.src_valid           (rsp_mux_src_valid),                                         //          .valid
		.src_data            (rsp_mux_src_data),                                          //          .data
		.src_channel         (rsp_mux_src_channel),                                       //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                 //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                   //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                                      //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                                      //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                                    //          .channel
		.sink0_data          (rsp_demux_src0_data),                                       //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                              //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket)                                 //          .endofpacket
	);

	system_acl_iface_mm_interconnect_5_rsp_mux rsp_mux_001 (
		.clk                 (pll_outclk0_clk),                                           //       clk.clk
		.reset               (clock_cross_axi_fpga_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                                     //       src.ready
		.src_valid           (rsp_mux_001_src_valid),                                     //          .valid
		.src_data            (rsp_mux_001_src_data),                                      //          .data
		.src_channel         (rsp_mux_001_src_channel),                                   //          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),                             //          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),                               //          .endofpacket
		.sink0_ready         (rsp_demux_src1_ready),                                      //     sink0.ready
		.sink0_valid         (rsp_demux_src1_valid),                                      //          .valid
		.sink0_channel       (rsp_demux_src1_channel),                                    //          .channel
		.sink0_data          (rsp_demux_src1_data),                                       //          .data
		.sink0_startofpacket (rsp_demux_src1_startofpacket),                              //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src1_endofpacket)                                 //          .endofpacket
	);

	system_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (258),
		.inUsePackets    (0),
		.inDataWidth     (258),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (258),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (pll_outclk0_clk),                                               // in_clk_0.clk
		.in_rst_0_reset (fpga_sdram_avl_0_translator_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (fpga_sdram_avl_0_agent_rdata_fifo_src_data),                    //     in_0.data
		.in_0_valid     (fpga_sdram_avl_0_agent_rdata_fifo_src_valid),                   //         .valid
		.in_0_ready     (fpga_sdram_avl_0_agent_rdata_fifo_src_ready),                   //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                                  //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                                 //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                                 //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                                  //         .error
	);

endmodule
