// system_acl_iface_mm_interconnect_0.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 15.1 193

`timescale 1 ps / 1 ps
module system_acl_iface_mm_interconnect_0 (
		input  wire         config_clk_out_clk_clk,                                    //                                  config_clk_out_clk.clk
		input  wire         acl_memory_bank_divider_reset_reset_bridge_in_reset_reset, // acl_memory_bank_divider_reset_reset_bridge_in_reset.reset
		input  wire         clock_cross_axi_fpga_s0_reset_reset_bridge_in_reset_reset, // clock_cross_axi_fpga_s0_reset_reset_bridge_in_reset.reset
		input  wire [29:0]  acl_memory_bank_divider_bank1_address,                     //                       acl_memory_bank_divider_bank1.address
		output wire         acl_memory_bank_divider_bank1_waitrequest,                 //                                                    .waitrequest
		input  wire [4:0]   acl_memory_bank_divider_bank1_burstcount,                  //                                                    .burstcount
		input  wire [31:0]  acl_memory_bank_divider_bank1_byteenable,                  //                                                    .byteenable
		input  wire         acl_memory_bank_divider_bank1_read,                        //                                                    .read
		output wire [255:0] acl_memory_bank_divider_bank1_readdata,                    //                                                    .readdata
		output wire         acl_memory_bank_divider_bank1_readdatavalid,               //                                                    .readdatavalid
		input  wire         acl_memory_bank_divider_bank1_write,                       //                                                    .write
		input  wire [255:0] acl_memory_bank_divider_bank1_writedata,                   //                                                    .writedata
		output wire [29:0]  clock_cross_axi_fpga_s0_address,                           //                             clock_cross_axi_fpga_s0.address
		output wire         clock_cross_axi_fpga_s0_write,                             //                                                    .write
		output wire         clock_cross_axi_fpga_s0_read,                              //                                                    .read
		input  wire [255:0] clock_cross_axi_fpga_s0_readdata,                          //                                                    .readdata
		output wire [255:0] clock_cross_axi_fpga_s0_writedata,                         //                                                    .writedata
		output wire [4:0]   clock_cross_axi_fpga_s0_burstcount,                        //                                                    .burstcount
		output wire [31:0]  clock_cross_axi_fpga_s0_byteenable,                        //                                                    .byteenable
		input  wire         clock_cross_axi_fpga_s0_readdatavalid,                     //                                                    .readdatavalid
		input  wire         clock_cross_axi_fpga_s0_waitrequest,                       //                                                    .waitrequest
		output wire         clock_cross_axi_fpga_s0_debugaccess                        //                                                    .debugaccess
	);

	wire          acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_waitrequest;   // clock_cross_axi_fpga_s0_translator:uav_waitrequest -> acl_memory_bank_divider_bank1_translator:uav_waitrequest
	wire  [255:0] acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_readdata;      // clock_cross_axi_fpga_s0_translator:uav_readdata -> acl_memory_bank_divider_bank1_translator:uav_readdata
	wire          acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_debugaccess;   // acl_memory_bank_divider_bank1_translator:uav_debugaccess -> clock_cross_axi_fpga_s0_translator:uav_debugaccess
	wire   [29:0] acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_address;       // acl_memory_bank_divider_bank1_translator:uav_address -> clock_cross_axi_fpga_s0_translator:uav_address
	wire          acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_read;          // acl_memory_bank_divider_bank1_translator:uav_read -> clock_cross_axi_fpga_s0_translator:uav_read
	wire   [31:0] acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_byteenable;    // acl_memory_bank_divider_bank1_translator:uav_byteenable -> clock_cross_axi_fpga_s0_translator:uav_byteenable
	wire          acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_readdatavalid; // clock_cross_axi_fpga_s0_translator:uav_readdatavalid -> acl_memory_bank_divider_bank1_translator:uav_readdatavalid
	wire          acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_lock;          // acl_memory_bank_divider_bank1_translator:uav_lock -> clock_cross_axi_fpga_s0_translator:uav_lock
	wire          acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_write;         // acl_memory_bank_divider_bank1_translator:uav_write -> clock_cross_axi_fpga_s0_translator:uav_write
	wire  [255:0] acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_writedata;     // acl_memory_bank_divider_bank1_translator:uav_writedata -> clock_cross_axi_fpga_s0_translator:uav_writedata
	wire    [9:0] acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_burstcount;    // acl_memory_bank_divider_bank1_translator:uav_burstcount -> clock_cross_axi_fpga_s0_translator:uav_burstcount

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (30),
		.AV_DATA_W                   (256),
		.AV_BURSTCOUNT_W             (5),
		.AV_BYTEENABLE_W             (32),
		.UAV_ADDRESS_W               (30),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (32),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (1),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) acl_memory_bank_divider_bank1_translator (
		.clk                    (config_clk_out_clk_clk),                                                           //                       clk.clk
		.reset                  (acl_memory_bank_divider_reset_reset_bridge_in_reset_reset),                        //                     reset.reset
		.uav_address            (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (acl_memory_bank_divider_bank1_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (acl_memory_bank_divider_bank1_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (acl_memory_bank_divider_bank1_burstcount),                                         //                          .burstcount
		.av_byteenable          (acl_memory_bank_divider_bank1_byteenable),                                         //                          .byteenable
		.av_read                (acl_memory_bank_divider_bank1_read),                                               //                          .read
		.av_readdata            (acl_memory_bank_divider_bank1_readdata),                                           //                          .readdata
		.av_readdatavalid       (acl_memory_bank_divider_bank1_readdatavalid),                                      //                          .readdatavalid
		.av_write               (acl_memory_bank_divider_bank1_write),                                              //                          .write
		.av_writedata           (acl_memory_bank_divider_bank1_writedata),                                          //                          .writedata
		.av_beginbursttransfer  (1'b0),                                                                             //               (terminated)
		.av_begintransfer       (1'b0),                                                                             //               (terminated)
		.av_chipselect          (1'b0),                                                                             //               (terminated)
		.av_lock                (1'b0),                                                                             //               (terminated)
		.av_debugaccess         (1'b0),                                                                             //               (terminated)
		.uav_clken              (),                                                                                 //               (terminated)
		.av_clken               (1'b1),                                                                             //               (terminated)
		.uav_response           (2'b00),                                                                            //               (terminated)
		.av_response            (),                                                                                 //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                             //               (terminated)
		.av_writeresponsevalid  ()                                                                                  //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (30),
		.AV_DATA_W                      (256),
		.UAV_DATA_W                     (256),
		.AV_BURSTCOUNT_W                (5),
		.AV_BYTEENABLE_W                (32),
		.UAV_BYTEENABLE_W               (32),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (10),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (32),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) clock_cross_axi_fpga_s0_translator (
		.clk                    (config_clk_out_clk_clk),                                                           //                      clk.clk
		.reset                  (clock_cross_axi_fpga_s0_reset_reset_bridge_in_reset_reset),                        //                    reset.reset
		.uav_address            (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_burstcount),    //                         .burstcount
		.uav_read               (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_read),          //                         .read
		.uav_write              (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_write),         //                         .write
		.uav_waitrequest        (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_byteenable),    //                         .byteenable
		.uav_readdata           (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_readdata),      //                         .readdata
		.uav_writedata          (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_writedata),     //                         .writedata
		.uav_lock               (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_lock),          //                         .lock
		.uav_debugaccess        (acl_memory_bank_divider_bank1_translator_avalon_universal_master_0_debugaccess),   //                         .debugaccess
		.av_address             (clock_cross_axi_fpga_s0_address),                                                  //      avalon_anti_slave_0.address
		.av_write               (clock_cross_axi_fpga_s0_write),                                                    //                         .write
		.av_read                (clock_cross_axi_fpga_s0_read),                                                     //                         .read
		.av_readdata            (clock_cross_axi_fpga_s0_readdata),                                                 //                         .readdata
		.av_writedata           (clock_cross_axi_fpga_s0_writedata),                                                //                         .writedata
		.av_burstcount          (clock_cross_axi_fpga_s0_burstcount),                                               //                         .burstcount
		.av_byteenable          (clock_cross_axi_fpga_s0_byteenable),                                               //                         .byteenable
		.av_readdatavalid       (clock_cross_axi_fpga_s0_readdatavalid),                                            //                         .readdatavalid
		.av_waitrequest         (clock_cross_axi_fpga_s0_waitrequest),                                              //                         .waitrequest
		.av_debugaccess         (clock_cross_axi_fpga_s0_debugaccess),                                              //                         .debugaccess
		.av_begintransfer       (),                                                                                 //              (terminated)
		.av_beginbursttransfer  (),                                                                                 //              (terminated)
		.av_writebyteenable     (),                                                                                 //              (terminated)
		.av_lock                (),                                                                                 //              (terminated)
		.av_chipselect          (),                                                                                 //              (terminated)
		.av_clken               (),                                                                                 //              (terminated)
		.uav_clken              (1'b0),                                                                             //              (terminated)
		.av_outputenable        (),                                                                                 //              (terminated)
		.uav_response           (),                                                                                 //              (terminated)
		.av_response            (2'b00),                                                                            //              (terminated)
		.uav_writeresponsevalid (),                                                                                 //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                                              //              (terminated)
	);

endmodule
