// hps_sdram.v

// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 15.1 193

`timescale 1 ps / 1 ps
module hps_sdram (
		input  wire [5:0]  cfg_axi_mm_select,   // hps_f2sdram.cfg_axi_mm_select
		input  wire [17:0] cfg_cport_rfifo_map, //            .cfg_cport_rfifo_map
		input  wire [11:0] cfg_cport_type,      //            .cfg_cport_type
		input  wire [17:0] cfg_cport_wfifo_map, //            .cfg_cport_wfifo_map
		input  wire [11:0] cfg_port_width,      //            .cfg_port_width
		input  wire [15:0] cfg_rfifo_cport_map, //            .cfg_rfifo_cport_map
		input  wire [15:0] cfg_wfifo_cport_map, //            .cfg_wfifo_cport_map
		input  wire [59:0] cmd_data_0,          //            .cmd_data_0
		input  wire [59:0] cmd_data_1,          //            .cmd_data_1
		input  wire [59:0] cmd_data_2,          //            .cmd_data_2
		input  wire [59:0] cmd_data_3,          //            .cmd_data_3
		input  wire [59:0] cmd_data_4,          //            .cmd_data_4
		input  wire [59:0] cmd_data_5,          //            .cmd_data_5
		input  wire        cmd_port_clk_0,      //            .cmd_port_clk_0
		input  wire        cmd_port_clk_1,      //            .cmd_port_clk_1
		input  wire        cmd_port_clk_2,      //            .cmd_port_clk_2
		input  wire        cmd_port_clk_3,      //            .cmd_port_clk_3
		input  wire        cmd_port_clk_4,      //            .cmd_port_clk_4
		input  wire        cmd_port_clk_5,      //            .cmd_port_clk_5
		input  wire        cmd_valid_0,         //            .cmd_valid_0
		input  wire        cmd_valid_1,         //            .cmd_valid_1
		input  wire        cmd_valid_2,         //            .cmd_valid_2
		input  wire        cmd_valid_3,         //            .cmd_valid_3
		input  wire        cmd_valid_4,         //            .cmd_valid_4
		input  wire        cmd_valid_5,         //            .cmd_valid_5
		input  wire        rd_clk_0,            //            .rd_clk_0
		input  wire        rd_clk_1,            //            .rd_clk_1
		input  wire        rd_clk_2,            //            .rd_clk_2
		input  wire        rd_clk_3,            //            .rd_clk_3
		input  wire        rd_ready_0,          //            .rd_ready_0
		input  wire        rd_ready_1,          //            .rd_ready_1
		input  wire        rd_ready_2,          //            .rd_ready_2
		input  wire        rd_ready_3,          //            .rd_ready_3
		input  wire        wr_clk_0,            //            .wr_clk_0
		input  wire        wr_clk_1,            //            .wr_clk_1
		input  wire        wr_clk_2,            //            .wr_clk_2
		input  wire        wr_clk_3,            //            .wr_clk_3
		input  wire [89:0] wr_data_0,           //            .wr_data_0
		input  wire [89:0] wr_data_1,           //            .wr_data_1
		input  wire [89:0] wr_data_2,           //            .wr_data_2
		input  wire [89:0] wr_data_3,           //            .wr_data_3
		input  wire        wr_valid_0,          //            .wr_valid_0
		input  wire        wr_valid_1,          //            .wr_valid_1
		input  wire        wr_valid_2,          //            .wr_valid_2
		input  wire        wr_valid_3,          //            .wr_valid_3
		input  wire        wrack_ready_0,       //            .wrack_ready_0
		input  wire        wrack_ready_1,       //            .wrack_ready_1
		input  wire        wrack_ready_2,       //            .wrack_ready_2
		input  wire        wrack_ready_3,       //            .wrack_ready_3
		input  wire        wrack_ready_4,       //            .wrack_ready_4
		input  wire        wrack_ready_5,       //            .wrack_ready_5
		output wire [3:0]  bonding_out_1,       //            .bonding_out_1
		output wire [3:0]  bonding_out_2,       //            .bonding_out_2
		output wire        cmd_ready_0,         //            .cmd_ready_0
		output wire        cmd_ready_1,         //            .cmd_ready_1
		output wire        cmd_ready_2,         //            .cmd_ready_2
		output wire        cmd_ready_3,         //            .cmd_ready_3
		output wire        cmd_ready_4,         //            .cmd_ready_4
		output wire        cmd_ready_5,         //            .cmd_ready_5
		output wire [79:0] rd_data_0,           //            .rd_data_0
		output wire [79:0] rd_data_1,           //            .rd_data_1
		output wire [79:0] rd_data_2,           //            .rd_data_2
		output wire [79:0] rd_data_3,           //            .rd_data_3
		output wire        rd_valid_0,          //            .rd_valid_0
		output wire        rd_valid_1,          //            .rd_valid_1
		output wire        rd_valid_2,          //            .rd_valid_2
		output wire        rd_valid_3,          //            .rd_valid_3
		output wire        wr_ready_0,          //            .wr_ready_0
		output wire        wr_ready_1,          //            .wr_ready_1
		output wire        wr_ready_2,          //            .wr_ready_2
		output wire        wr_ready_3,          //            .wr_ready_3
		output wire [9:0]  wrack_data_0,        //            .wrack_data_0
		output wire [9:0]  wrack_data_1,        //            .wrack_data_1
		output wire [9:0]  wrack_data_2,        //            .wrack_data_2
		output wire [9:0]  wrack_data_3,        //            .wrack_data_3
		output wire [9:0]  wrack_data_4,        //            .wrack_data_4
		output wire [9:0]  wrack_data_5,        //            .wrack_data_5
		output wire        wrack_valid_0,       //            .wrack_valid_0
		output wire        wrack_valid_1,       //            .wrack_valid_1
		output wire        wrack_valid_2,       //            .wrack_valid_2
		output wire        wrack_valid_3,       //            .wrack_valid_3
		output wire        wrack_valid_4,       //            .wrack_valid_4
		output wire        wrack_valid_5        //            .wrack_valid_5
	);

	wire         pll_ref_clk_clk_clk;                                // pll_ref_clk:clk -> [global_reset:clk, pll:pll_ref_clk]
	wire         global_reset_reset_reset;                           // global_reset:reset -> [p0:global_reset_n, p0:soft_reset_n, pll:global_reset_n]
	wire         pll_afi_clk_clk;                                    // pll:afi_clk -> p0:afi_clk
	wire         pll_afi_half_clk_clk;                               // pll:afi_half_clk -> p0:afi_half_clk
	wire   [4:0] p0_afi_afi_rlat;                                    // p0:afi_rlat -> c0:afi_rlat
	wire         p0_afi_afi_cal_success;                             // p0:afi_cal_success -> c0:afi_cal_success
	wire  [79:0] p0_afi_afi_rdata;                                   // p0:afi_rdata -> c0:afi_rdata
	wire   [3:0] p0_afi_afi_wlat;                                    // p0:afi_wlat -> c0:afi_wlat
	wire         p0_afi_afi_cal_fail;                                // p0:afi_cal_fail -> c0:afi_cal_fail
	wire   [0:0] p0_afi_afi_rdata_valid;                             // p0:afi_rdata_valid -> c0:afi_rdata_valid
	wire         p0_avl_clk_clk;                                     // p0:avl_clk -> [avl2apb:pclk, c0:csr_clk, cpu_inst:clk, irq_mapper:clk, mm_interconnect_1:p0_avl_clk_clk, mm_interconnect_2:p0_avl_clk_clk, s0:apb_clk, s0:avl_clk, sequencer_mem:clk1]
	wire         p0_avl_reset_reset;                                 // p0:avl_reset_n -> [avl2apb:sp_reset_n, c0:csr_reset_n, cpu_inst:reset_n, irq_mapper:reset, mm_interconnect_1:cpu_inst_reset_n_reset_bridge_in_reset_reset, mm_interconnect_2:c0_csr_reset_n_reset_bridge_in_reset_reset, mm_interconnect_2:s0_avl_reset_reset_bridge_in_reset_reset, s0:apb_reset_n, s0:avl_reset_n, sequencer_mem:reset1]
	wire         p0_scc_clk_clk;                                     // p0:scc_clk -> s0:scc_clk
	wire         p0_scc_reset_reset;                                 // p0:scc_reset_n -> s0:reset_n_scc_clk
	wire  [31:0] s0_avl_readdata;                                    // p0:avl_readdata -> s0:avl_readdata
	wire         s0_avl_waitrequest;                                 // p0:avl_waitrequest -> s0:avl_waitrequest
	wire  [15:0] s0_avl_address;                                     // s0:avl_address -> p0:avl_address
	wire         s0_avl_read;                                        // s0:avl_read -> p0:avl_read
	wire         s0_avl_write;                                       // s0:avl_write -> p0:avl_write
	wire  [31:0] s0_avl_writedata;                                   // s0:avl_writedata -> p0:avl_writedata
	wire  [39:0] s0_scc_scc_dq_ena;                                  // s0:scc_dq_ena -> p0:scc_dq_ena
	wire   [0:0] s0_scc_scc_upd;                                     // s0:scc_upd -> p0:scc_upd
	wire   [4:0] s0_scc_scc_dqs_io_ena;                              // s0:scc_dqs_io_ena -> p0:scc_dqs_io_ena
	wire   [4:0] s0_scc_scc_dm_ena;                                  // s0:scc_dm_ena -> p0:scc_dm_ena
	wire   [4:0] p0_scc_capture_strobe_tracking;                     // p0:capture_strobe_tracking -> s0:capture_strobe_tracking
	wire   [4:0] s0_scc_scc_dqs_ena;                                 // s0:scc_dqs_ena -> p0:scc_dqs_ena
	wire   [0:0] s0_scc_scc_data;                                    // s0:scc_data -> p0:scc_data
	wire   [0:0] s0_tracking_afi_seq_busy;                           // s0:afi_seq_busy -> c0:afi_seq_busy
	wire  [31:0] avl2apb_apb_master_paddr;                           // avl2apb:paddr -> s0:paddr
	wire         s0_apb_slave_pready;                                // s0:pready -> avl2apb:pready
	wire  [31:0] s0_apb_slave_prdata;                                // s0:prdata -> avl2apb:prdata
	wire         s0_apb_slave_pslverr;                               // s0:pslverr -> avl2apb:pslverr
	wire  [31:0] avl2apb_apb_master_pwdata;                          // avl2apb:pwdata -> s0:pwdata
	wire         avl2apb_apb_master_penable;                         // avl2apb:penable -> s0:penable
	wire         avl2apb_apb_master_pwrite;                          // avl2apb:pwrite -> s0:pwrite
	wire         avl2apb_apb_master_psel;                            // avl2apb:psel -> s0:psel
	wire   [4:0] c0_afi_afi_rdata_en_full;                           // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
	wire   [0:0] c0_afi_afi_rst_n;                                   // c0:afi_rst_n -> p0:afi_rst_n
	wire   [4:0] c0_afi_afi_dqs_burst;                               // c0:afi_dqs_burst -> p0:afi_dqs_burst
	wire  [19:0] c0_afi_afi_addr;                                    // c0:afi_addr -> p0:afi_addr
	wire   [9:0] c0_afi_afi_dm;                                      // c0:afi_dm -> p0:afi_dm
	wire   [0:0] c0_afi_afi_mem_clk_disable;                         // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
	wire         c0_afi_afi_init_req;                                // c0:afi_init_req -> s0:afi_init_req
	wire   [0:0] c0_afi_afi_we_n;                                    // c0:afi_we_n -> p0:afi_we_n
	wire   [0:0] c0_afi_afi_ctl_refresh_done;                        // c0:afi_ctl_refresh_done -> s0:afi_ctl_refresh_done
	wire   [4:0] c0_afi_afi_rdata_en;                                // c0:afi_rdata_en -> p0:afi_rdata_en
	wire   [1:0] c0_afi_afi_odt;                                     // c0:afi_odt -> p0:afi_odt
	wire   [0:0] c0_afi_afi_ras_n;                                   // c0:afi_ras_n -> p0:afi_ras_n
	wire   [1:0] c0_afi_afi_cke;                                     // c0:afi_cke -> p0:afi_cke
	wire   [4:0] c0_afi_afi_wdata_valid;                             // c0:afi_wdata_valid -> p0:afi_wdata_valid
	wire  [79:0] c0_afi_afi_wdata;                                   // c0:afi_wdata -> p0:afi_wdata
	wire         c0_afi_afi_cal_req;                                 // c0:afi_cal_req -> s0:afi_cal_req
	wire   [2:0] c0_afi_afi_ba;                                      // c0:afi_ba -> p0:afi_ba
	wire   [0:0] c0_afi_afi_ctl_long_idle;                           // c0:afi_ctl_long_idle -> s0:afi_ctl_long_idle
	wire   [0:0] c0_afi_afi_cas_n;                                   // c0:afi_cas_n -> p0:afi_cas_n
	wire   [1:0] c0_afi_afi_cs_n;                                    // c0:afi_cs_n -> p0:afi_cs_n
	wire   [7:0] c0_hard_phy_cfg_cfg_tmrd;                           // c0:cfg_tmrd -> p0:cfg_tmrd
	wire  [23:0] c0_hard_phy_cfg_cfg_dramconfig;                     // c0:cfg_dramconfig -> p0:cfg_dramconfig
	wire   [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth;                   // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
	wire   [7:0] c0_hard_phy_cfg_cfg_devicewidth;                    // c0:cfg_devicewidth -> p0:cfg_devicewidth
	wire  [15:0] c0_hard_phy_cfg_cfg_trefi;                          // c0:cfg_trefi -> p0:cfg_trefi
	wire   [7:0] c0_hard_phy_cfg_cfg_tcl;                            // c0:cfg_tcl -> p0:cfg_tcl
	wire   [7:0] c0_hard_phy_cfg_cfg_csaddrwidth;                    // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
	wire   [7:0] c0_hard_phy_cfg_cfg_coladdrwidth;                   // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
	wire   [7:0] c0_hard_phy_cfg_cfg_trfc;                           // c0:cfg_trfc -> p0:cfg_trfc
	wire   [7:0] c0_hard_phy_cfg_cfg_addlat;                         // c0:cfg_addlat -> p0:cfg_addlat
	wire   [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth;                  // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
	wire   [7:0] c0_hard_phy_cfg_cfg_interfacewidth;                 // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
	wire   [7:0] c0_hard_phy_cfg_cfg_twr;                            // c0:cfg_twr -> p0:cfg_twr
	wire   [7:0] c0_hard_phy_cfg_cfg_caswrlat;                       // c0:cfg_caswrlat -> p0:cfg_caswrlat
	wire         p0_ctl_clk_clk;                                     // p0:ctl_clk -> c0:ctl_clk
	wire         p0_ctl_reset_reset;                                 // p0:ctl_reset_n -> c0:ctl_reset_n
	wire   [0:0] p0_memory_mem_cas_n;                                // p0:mem_cas_n -> mem:mem_cas_n
	wire         p0_memory_mem_reset_n;                              // p0:mem_reset_n -> mem:mem_reset_n
	wire   [2:0] p0_memory_mem_ba;                                   // p0:mem_ba -> mem:mem_ba
	wire   [0:0] p0_memory_mem_we_n;                                 // p0:mem_we_n -> mem:mem_we_n
	wire   [0:0] p0_memory_mem_ck;                                   // p0:mem_ck -> mem:mem_ck
	wire   [4:0] p0_memory_mem_dm;                                   // p0:mem_dm -> mem:mem_dm
	wire   [4:0] mem_memory_mem_dqs;                                 // [] -> [mem:mem_dqs, p0:mem_dqs]
	wire  [39:0] mem_memory_mem_dq;                                  // [] -> [mem:mem_dq, p0:mem_dq]
	wire   [0:0] p0_memory_mem_cs_n;                                 // p0:mem_cs_n -> mem:mem_cs_n
	wire  [14:0] p0_memory_mem_a;                                    // p0:mem_a -> mem:mem_a
	wire   [0:0] p0_memory_mem_ras_n;                                // p0:mem_ras_n -> mem:mem_ras_n
	wire   [4:0] mem_memory_mem_dqs_n;                               // [] -> [mem:mem_dqs_n, p0:mem_dqs_n]
	wire   [0:0] p0_memory_mem_odt;                                  // p0:mem_odt -> mem:mem_odt
	wire   [0:0] p0_memory_mem_ck_n;                                 // p0:mem_ck_n -> mem:mem_ck_n
	wire   [0:0] p0_memory_mem_cke;                                  // p0:mem_cke -> mem:mem_cke
	wire         pll_pll_sharing_pll_write_clk;                      // pll:pll_write_clk -> p0:pll_write_clk
	wire         pll_pll_sharing_pll_avl_clk;                        // pll:pll_avl_clk -> p0:pll_avl_clk
	wire         pll_pll_sharing_pll_write_clk_pre_phy_clk;          // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
	wire         pll_pll_sharing_pll_addr_cmd_clk;                   // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
	wire         pll_pll_sharing_pll_config_clk;                     // pll:pll_config_clk -> p0:pll_config_clk
	wire         pll_pll_sharing_pll_avl_phy_clk;                    // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
	wire         pll_pll_sharing_afi_phy_clk;                        // pll:afi_phy_clk -> p0:afi_phy_clk
	wire         pll_pll_sharing_pll_mem_clk;                        // pll:pll_mem_clk -> p0:pll_mem_clk
	wire         pll_pll_sharing_pll_locked;                         // pll:pll_locked -> p0:pll_locked
	wire         pll_pll_sharing_pll_mem_phy_clk;                    // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
	wire         p0_dll_clk_clk;                                     // p0:dll_clk -> dll:clk
	wire         p0_dll_sharing_dll_pll_locked;                      // p0:dll_pll_locked -> dll:dll_pll_locked
	wire   [6:0] dll_dll_sharing_dll_delayctrl;                      // dll:dll_delayctrl -> p0:dll_delayctrl
	wire  [31:0] cpu_inst_data_master_readdata;                      // mm_interconnect_1:cpu_inst_data_master_readdata -> cpu_inst:d_readdata
	wire         cpu_inst_data_master_waitrequest;                   // mm_interconnect_1:cpu_inst_data_master_waitrequest -> cpu_inst:d_waitrequest
	wire  [19:0] cpu_inst_data_master_address;                       // cpu_inst:d_address -> mm_interconnect_1:cpu_inst_data_master_address
	wire   [3:0] cpu_inst_data_master_byteenable;                    // cpu_inst:d_byteenable -> mm_interconnect_1:cpu_inst_data_master_byteenable
	wire         cpu_inst_data_master_read;                          // cpu_inst:d_read -> mm_interconnect_1:cpu_inst_data_master_read
	wire         cpu_inst_data_master_write;                         // cpu_inst:d_write -> mm_interconnect_1:cpu_inst_data_master_write
	wire  [31:0] cpu_inst_data_master_writedata;                     // cpu_inst:d_writedata -> mm_interconnect_1:cpu_inst_data_master_writedata
	wire  [31:0] cpu_inst_instruction_master_readdata;               // mm_interconnect_1:cpu_inst_instruction_master_readdata -> cpu_inst:i_readdata
	wire         cpu_inst_instruction_master_waitrequest;            // mm_interconnect_1:cpu_inst_instruction_master_waitrequest -> cpu_inst:i_waitrequest
	wire  [16:0] cpu_inst_instruction_master_address;                // cpu_inst:i_address -> mm_interconnect_1:cpu_inst_instruction_master_address
	wire         cpu_inst_instruction_master_read;                   // cpu_inst:i_read -> mm_interconnect_1:cpu_inst_instruction_master_read
	wire         mm_interconnect_1_sequencer_mem_s1_chipselect;      // mm_interconnect_1:sequencer_mem_s1_chipselect -> sequencer_mem:s1_chipselect
	wire  [31:0] mm_interconnect_1_sequencer_mem_s1_readdata;        // sequencer_mem:s1_readdata -> mm_interconnect_1:sequencer_mem_s1_readdata
	wire  [12:0] mm_interconnect_1_sequencer_mem_s1_address;         // mm_interconnect_1:sequencer_mem_s1_address -> sequencer_mem:s1_address
	wire   [3:0] mm_interconnect_1_sequencer_mem_s1_byteenable;      // mm_interconnect_1:sequencer_mem_s1_byteenable -> sequencer_mem:s1_be
	wire         mm_interconnect_1_sequencer_mem_s1_write;           // mm_interconnect_1:sequencer_mem_s1_write -> sequencer_mem:s1_write
	wire  [31:0] mm_interconnect_1_sequencer_mem_s1_writedata;       // mm_interconnect_1:sequencer_mem_s1_writedata -> sequencer_mem:s1_writedata
	wire  [31:0] mm_interconnect_1_avl2apb_avalon_slave_readdata;    // avl2apb:av_readdata -> mm_interconnect_1:avl2apb_avalon_slave_readdata
	wire         mm_interconnect_1_avl2apb_avalon_slave_waitrequest; // avl2apb:av_waitrequest -> mm_interconnect_1:avl2apb_avalon_slave_waitrequest
	wire  [15:0] mm_interconnect_1_avl2apb_avalon_slave_address;     // mm_interconnect_1:avl2apb_avalon_slave_address -> avl2apb:av_addr
	wire         mm_interconnect_1_avl2apb_avalon_slave_read;        // mm_interconnect_1:avl2apb_avalon_slave_read -> avl2apb:av_read
	wire   [3:0] mm_interconnect_1_avl2apb_avalon_slave_byteenable;  // mm_interconnect_1:avl2apb_avalon_slave_byteenable -> avl2apb:av_byteenable
	wire         mm_interconnect_1_avl2apb_avalon_slave_write;       // mm_interconnect_1:avl2apb_avalon_slave_write -> avl2apb:av_write
	wire  [31:0] mm_interconnect_1_avl2apb_avalon_slave_writedata;   // mm_interconnect_1:avl2apb_avalon_slave_writedata -> avl2apb:av_writedata
	wire  [31:0] s0_mmr_avl_readdata;                                // mm_interconnect_2:s0_mmr_avl_readdata -> s0:mmr_avl_readdata
	wire         s0_mmr_avl_waitrequest;                             // mm_interconnect_2:s0_mmr_avl_waitrequest -> s0:mmr_avl_waitrequest
	wire   [7:0] s0_mmr_avl_address;                                 // s0:mmr_avl_address -> mm_interconnect_2:s0_mmr_avl_address
	wire         s0_mmr_avl_read;                                    // s0:mmr_avl_read -> mm_interconnect_2:s0_mmr_avl_read
	wire         s0_mmr_avl_readdatavalid;                           // mm_interconnect_2:s0_mmr_avl_readdatavalid -> s0:mmr_avl_readdatavalid
	wire         s0_mmr_avl_write;                                   // s0:mmr_avl_write -> mm_interconnect_2:s0_mmr_avl_write
	wire  [31:0] s0_mmr_avl_writedata;                               // s0:mmr_avl_writedata -> mm_interconnect_2:s0_mmr_avl_writedata
	wire         s0_mmr_avl_burstcount;                              // s0:mmr_avl_burstcount -> mm_interconnect_2:s0_mmr_avl_burstcount
	wire  [31:0] mm_interconnect_2_c0_csr_readdata;                  // c0:csr_rdata -> mm_interconnect_2:c0_csr_readdata
	wire         mm_interconnect_2_c0_csr_waitrequest;               // c0:csr_waitrequest -> mm_interconnect_2:c0_csr_waitrequest
	wire   [7:0] mm_interconnect_2_c0_csr_address;                   // mm_interconnect_2:c0_csr_address -> c0:csr_addr
	wire         mm_interconnect_2_c0_csr_read;                      // mm_interconnect_2:c0_csr_read -> c0:csr_read_req
	wire   [3:0] mm_interconnect_2_c0_csr_byteenable;                // mm_interconnect_2:c0_csr_byteenable -> c0:csr_be
	wire         mm_interconnect_2_c0_csr_readdatavalid;             // c0:csr_rdata_valid -> mm_interconnect_2:c0_csr_readdatavalid
	wire         mm_interconnect_2_c0_csr_write;                     // mm_interconnect_2:c0_csr_write -> c0:csr_write_req
	wire  [31:0] mm_interconnect_2_c0_csr_writedata;                 // mm_interconnect_2:c0_csr_writedata -> c0:csr_wdata
	wire  [31:0] cpu_inst_d_irq_irq;                                 // irq_mapper:sender_irq -> cpu_inst:d_irq

	altera_avalon_clock_source #(
		.CLOCK_RATE (25),
		.CLOCK_UNIT (1000000)
	) pll_ref_clk (
		.clk (pll_ref_clk_clk_clk)  // clk.clk
	);

	altera_avalon_reset_source #(
		.ASSERT_HIGH_RESET    (0),
		.INITIAL_RESET_CYCLES (5)
	) global_reset (
		.reset (global_reset_reset_reset), // reset.reset_n
		.clk   (pll_ref_clk_clk_clk)       //   clk.clk
	);

	hps_sdram_pll pll (
		.global_reset_n            (global_reset_reset_reset),                  // global_reset.reset_n
		.pll_ref_clk               (pll_ref_clk_clk_clk),                       //  pll_ref_clk.clk
		.afi_clk                   (pll_afi_clk_clk),                           //      afi_clk.clk
		.afi_half_clk              (pll_afi_half_clk_clk),                      // afi_half_clk.clk
		.pll_mem_clk               (pll_pll_sharing_pll_mem_clk),               //  pll_sharing.pll_mem_clk
		.pll_write_clk             (pll_pll_sharing_pll_write_clk),             //             .pll_write_clk
		.pll_locked                (pll_pll_sharing_pll_locked),                //             .pll_locked
		.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), //             .pll_write_clk_pre_phy_clk
		.pll_addr_cmd_clk          (pll_pll_sharing_pll_addr_cmd_clk),          //             .pll_addr_cmd_clk
		.pll_avl_clk               (pll_pll_sharing_pll_avl_clk),               //             .pll_avl_clk
		.pll_config_clk            (pll_pll_sharing_pll_config_clk),            //             .pll_config_clk
		.pll_mem_phy_clk           (pll_pll_sharing_pll_mem_phy_clk),           //             .pll_mem_phy_clk
		.afi_phy_clk               (pll_pll_sharing_afi_phy_clk),               //             .afi_phy_clk
		.pll_avl_phy_clk           (pll_pll_sharing_pll_avl_phy_clk)            //             .pll_avl_phy_clk
	);

	hps_sdram_p0 p0 (
		.global_reset_n             (global_reset_reset_reset),                                                                                                                                                                  //        global_reset.reset_n
		.soft_reset_n               (global_reset_reset_reset),                                                                                                                                                                  //          soft_reset.reset_n
		.afi_reset_n                (),                                                                                                                                                                                          //           afi_reset.reset_n
		.afi_reset_export_n         (),                                                                                                                                                                                          //    afi_reset_export.reset_n
		.ctl_reset_n                (p0_ctl_reset_reset),                                                                                                                                                                        //           ctl_reset.reset_n
		.afi_clk                    (pll_afi_clk_clk),                                                                                                                                                                           //             afi_clk.clk
		.afi_half_clk               (pll_afi_half_clk_clk),                                                                                                                                                                      //        afi_half_clk.clk
		.ctl_clk                    (p0_ctl_clk_clk),                                                                                                                                                                            //             ctl_clk.clk
		.avl_clk                    (p0_avl_clk_clk),                                                                                                                                                                            //             avl_clk.clk
		.avl_reset_n                (p0_avl_reset_reset),                                                                                                                                                                        //           avl_reset.reset_n
		.scc_clk                    (p0_scc_clk_clk),                                                                                                                                                                            //             scc_clk.clk
		.scc_reset_n                (p0_scc_reset_reset),                                                                                                                                                                        //           scc_reset.reset_n
		.avl_address                (s0_avl_address),                                                                                                                                                                            //                 avl.address
		.avl_write                  (s0_avl_write),                                                                                                                                                                              //                    .write
		.avl_writedata              (s0_avl_writedata),                                                                                                                                                                          //                    .writedata
		.avl_read                   (s0_avl_read),                                                                                                                                                                               //                    .read
		.avl_readdata               (s0_avl_readdata),                                                                                                                                                                           //                    .readdata
		.avl_waitrequest            (s0_avl_waitrequest),                                                                                                                                                                        //                    .waitrequest
		.dll_clk                    (p0_dll_clk_clk),                                                                                                                                                                            //             dll_clk.clk
		.afi_addr                   (c0_afi_afi_addr),                                                                                                                                                                           //                 afi.afi_addr
		.afi_ba                     (c0_afi_afi_ba),                                                                                                                                                                             //                    .afi_ba
		.afi_cke                    (c0_afi_afi_cke),                                                                                                                                                                            //                    .afi_cke
		.afi_cs_n                   (c0_afi_afi_cs_n),                                                                                                                                                                           //                    .afi_cs_n
		.afi_ras_n                  (c0_afi_afi_ras_n),                                                                                                                                                                          //                    .afi_ras_n
		.afi_we_n                   (c0_afi_afi_we_n),                                                                                                                                                                           //                    .afi_we_n
		.afi_cas_n                  (c0_afi_afi_cas_n),                                                                                                                                                                          //                    .afi_cas_n
		.afi_rst_n                  (c0_afi_afi_rst_n),                                                                                                                                                                          //                    .afi_rst_n
		.afi_odt                    (c0_afi_afi_odt),                                                                                                                                                                            //                    .afi_odt
		.afi_dqs_burst              (c0_afi_afi_dqs_burst),                                                                                                                                                                      //                    .afi_dqs_burst
		.afi_wdata_valid            (c0_afi_afi_wdata_valid),                                                                                                                                                                    //                    .afi_wdata_valid
		.afi_wdata                  (c0_afi_afi_wdata),                                                                                                                                                                          //                    .afi_wdata
		.afi_dm                     (c0_afi_afi_dm),                                                                                                                                                                             //                    .afi_dm
		.afi_rdata                  (p0_afi_afi_rdata),                                                                                                                                                                          //                    .afi_rdata
		.afi_rdata_en               (c0_afi_afi_rdata_en),                                                                                                                                                                       //                    .afi_rdata_en
		.afi_rdata_en_full          (c0_afi_afi_rdata_en_full),                                                                                                                                                                  //                    .afi_rdata_en_full
		.afi_rdata_valid            (p0_afi_afi_rdata_valid),                                                                                                                                                                    //                    .afi_rdata_valid
		.afi_wlat                   (p0_afi_afi_wlat),                                                                                                                                                                           //                    .afi_wlat
		.afi_rlat                   (p0_afi_afi_rlat),                                                                                                                                                                           //                    .afi_rlat
		.afi_cal_success            (p0_afi_afi_cal_success),                                                                                                                                                                    //                    .afi_cal_success
		.afi_cal_fail               (p0_afi_afi_cal_fail),                                                                                                                                                                       //                    .afi_cal_fail
		.scc_data                   (s0_scc_scc_data),                                                                                                                                                                           //                 scc.scc_data
		.scc_dqs_ena                (s0_scc_scc_dqs_ena),                                                                                                                                                                        //                    .scc_dqs_ena
		.scc_dqs_io_ena             (s0_scc_scc_dqs_io_ena),                                                                                                                                                                     //                    .scc_dqs_io_ena
		.scc_dq_ena                 (s0_scc_scc_dq_ena),                                                                                                                                                                         //                    .scc_dq_ena
		.scc_dm_ena                 (s0_scc_scc_dm_ena),                                                                                                                                                                         //                    .scc_dm_ena
		.capture_strobe_tracking    (p0_scc_capture_strobe_tracking),                                                                                                                                                            //                    .capture_strobe_tracking
		.scc_upd                    (s0_scc_scc_upd),                                                                                                                                                                            //                    .scc_upd
		.cfg_addlat                 (c0_hard_phy_cfg_cfg_addlat),                                                                                                                                                                //        hard_phy_cfg.cfg_addlat
		.cfg_bankaddrwidth          (c0_hard_phy_cfg_cfg_bankaddrwidth),                                                                                                                                                         //                    .cfg_bankaddrwidth
		.cfg_caswrlat               (c0_hard_phy_cfg_cfg_caswrlat),                                                                                                                                                              //                    .cfg_caswrlat
		.cfg_coladdrwidth           (c0_hard_phy_cfg_cfg_coladdrwidth),                                                                                                                                                          //                    .cfg_coladdrwidth
		.cfg_csaddrwidth            (c0_hard_phy_cfg_cfg_csaddrwidth),                                                                                                                                                           //                    .cfg_csaddrwidth
		.cfg_devicewidth            (c0_hard_phy_cfg_cfg_devicewidth),                                                                                                                                                           //                    .cfg_devicewidth
		.cfg_dramconfig             (c0_hard_phy_cfg_cfg_dramconfig),                                                                                                                                                            //                    .cfg_dramconfig
		.cfg_interfacewidth         (c0_hard_phy_cfg_cfg_interfacewidth),                                                                                                                                                        //                    .cfg_interfacewidth
		.cfg_rowaddrwidth           (c0_hard_phy_cfg_cfg_rowaddrwidth),                                                                                                                                                          //                    .cfg_rowaddrwidth
		.cfg_tcl                    (c0_hard_phy_cfg_cfg_tcl),                                                                                                                                                                   //                    .cfg_tcl
		.cfg_tmrd                   (c0_hard_phy_cfg_cfg_tmrd),                                                                                                                                                                  //                    .cfg_tmrd
		.cfg_trefi                  (c0_hard_phy_cfg_cfg_trefi),                                                                                                                                                                 //                    .cfg_trefi
		.cfg_trfc                   (c0_hard_phy_cfg_cfg_trfc),                                                                                                                                                                  //                    .cfg_trfc
		.cfg_twr                    (c0_hard_phy_cfg_cfg_twr),                                                                                                                                                                   //                    .cfg_twr
		.afi_mem_clk_disable        (c0_afi_afi_mem_clk_disable),                                                                                                                                                                // afi_mem_clk_disable.afi_mem_clk_disable
		.pll_mem_clk                (pll_pll_sharing_pll_mem_clk),                                                                                                                                                               //         pll_sharing.pll_mem_clk
		.pll_write_clk              (pll_pll_sharing_pll_write_clk),                                                                                                                                                             //                    .pll_write_clk
		.pll_locked                 (pll_pll_sharing_pll_locked),                                                                                                                                                                //                    .pll_locked
		.pll_write_clk_pre_phy_clk  (pll_pll_sharing_pll_write_clk_pre_phy_clk),                                                                                                                                                 //                    .pll_write_clk_pre_phy_clk
		.pll_addr_cmd_clk           (pll_pll_sharing_pll_addr_cmd_clk),                                                                                                                                                          //                    .pll_addr_cmd_clk
		.pll_avl_clk                (pll_pll_sharing_pll_avl_clk),                                                                                                                                                               //                    .pll_avl_clk
		.pll_config_clk             (pll_pll_sharing_pll_config_clk),                                                                                                                                                            //                    .pll_config_clk
		.pll_mem_phy_clk            (pll_pll_sharing_pll_mem_phy_clk),                                                                                                                                                           //                    .pll_mem_phy_clk
		.afi_phy_clk                (pll_pll_sharing_afi_phy_clk),                                                                                                                                                               //                    .afi_phy_clk
		.pll_avl_phy_clk            (pll_pll_sharing_pll_avl_phy_clk),                                                                                                                                                           //                    .pll_avl_phy_clk
		.dll_pll_locked             (p0_dll_sharing_dll_pll_locked),                                                                                                                                                             //         dll_sharing.dll_pll_locked
		.dll_delayctrl              (dll_dll_sharing_dll_delayctrl),                                                                                                                                                             //                    .dll_delayctrl
		.seriesterminationcontrol   (),                                                                                                                                                                                          //         oct_sharing.seriesterminationcontrol
		.parallelterminationcontrol (),                                                                                                                                                                                          //                    .parallelterminationcontrol
		.mem_a                      (p0_memory_mem_a),                                                                                                                                                                           //              memory.mem_a
		.mem_ba                     (p0_memory_mem_ba),                                                                                                                                                                          //                    .mem_ba
		.mem_ck                     (p0_memory_mem_ck),                                                                                                                                                                          //                    .mem_ck
		.mem_ck_n                   (p0_memory_mem_ck_n),                                                                                                                                                                        //                    .mem_ck_n
		.mem_cke                    (p0_memory_mem_cke),                                                                                                                                                                         //                    .mem_cke
		.mem_cs_n                   (p0_memory_mem_cs_n),                                                                                                                                                                        //                    .mem_cs_n
		.mem_dm                     (p0_memory_mem_dm),                                                                                                                                                                          //                    .mem_dm
		.mem_ras_n                  (p0_memory_mem_ras_n),                                                                                                                                                                       //                    .mem_ras_n
		.mem_cas_n                  (p0_memory_mem_cas_n),                                                                                                                                                                       //                    .mem_cas_n
		.mem_we_n                   (p0_memory_mem_we_n),                                                                                                                                                                        //                    .mem_we_n
		.mem_reset_n                (p0_memory_mem_reset_n),                                                                                                                                                                     //                    .mem_reset_n
		.mem_dq                     (mem_memory_mem_dq),                                                                                                                                                                         //                    .mem_dq
		.mem_dqs                    (mem_memory_mem_dqs),                                                                                                                                                                        //                    .mem_dqs
		.mem_dqs_n                  (mem_memory_mem_dqs_n),                                                                                                                                                                      //                    .mem_dqs_n
		.mem_odt                    (p0_memory_mem_odt),                                                                                                                                                                         //                    .mem_odt
		.io_intaficalfail           (),                                                                                                                                                                                          //              io_int.io_intaficalfail
		.io_intaficalsuccess        (),                                                                                                                                                                                          //                    .io_intaficalsuccess
		.csr_soft_reset_req         (1'b0),                                                                                                                                                                                      //         (terminated)
		.io_intaddrdout             (64'b0000000000000000000000000000000000000000000000000000000000000000),                                                                                                                      //         (terminated)
		.io_intbadout               (12'b000000000000),                                                                                                                                                                          //         (terminated)
		.io_intcasndout             (4'b0000),                                                                                                                                                                                   //         (terminated)
		.io_intckdout               (4'b0000),                                                                                                                                                                                   //         (terminated)
		.io_intckedout              (8'b00000000),                                                                                                                                                                               //         (terminated)
		.io_intckndout              (4'b0000),                                                                                                                                                                                   //         (terminated)
		.io_intcsndout              (8'b00000000),                                                                                                                                                                               //         (terminated)
		.io_intdmdout               (20'b00000000000000000000),                                                                                                                                                                  //         (terminated)
		.io_intdqdin                (),                                                                                                                                                                                          //         (terminated)
		.io_intdqdout               (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), //         (terminated)
		.io_intdqoe                 (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),                                                                                            //         (terminated)
		.io_intdqsbdout             (20'b00000000000000000000),                                                                                                                                                                  //         (terminated)
		.io_intdqsboe               (10'b0000000000),                                                                                                                                                                            //         (terminated)
		.io_intdqsdout              (20'b00000000000000000000),                                                                                                                                                                  //         (terminated)
		.io_intdqslogicdqsena       (10'b0000000000),                                                                                                                                                                            //         (terminated)
		.io_intdqslogicfiforeset    (5'b00000),                                                                                                                                                                                  //         (terminated)
		.io_intdqslogicincrdataen   (10'b0000000000),                                                                                                                                                                            //         (terminated)
		.io_intdqslogicincwrptr     (10'b0000000000),                                                                                                                                                                            //         (terminated)
		.io_intdqslogicoct          (10'b0000000000),                                                                                                                                                                            //         (terminated)
		.io_intdqslogicrdatavalid   (),                                                                                                                                                                                          //         (terminated)
		.io_intdqslogicreadlatency  (25'b0000000000000000000000000),                                                                                                                                                             //         (terminated)
		.io_intdqsoe                (10'b0000000000),                                                                                                                                                                            //         (terminated)
		.io_intodtdout              (8'b00000000),                                                                                                                                                                               //         (terminated)
		.io_intrasndout             (4'b0000),                                                                                                                                                                                   //         (terminated)
		.io_intresetndout           (4'b0000),                                                                                                                                                                                   //         (terminated)
		.io_intwendout              (4'b0000),                                                                                                                                                                                   //         (terminated)
		.io_intafirlat              (),                                                                                                                                                                                          //         (terminated)
		.io_intafiwlat              ()                                                                                                                                                                                           //         (terminated)
	);

	altera_mem_if_hhp_qseq_top #(
		.MEM_IF_DM_WIDTH  (5),
		.MEM_IF_DQS_WIDTH (5),
		.MEM_IF_CS_WIDTH  (1),
		.MEM_IF_DQ_WIDTH  (40)
	) s0 (
		.avl_clk                 (p0_avl_clk_clk),                 //          avl_clk.clk
		.avl_reset_n             (p0_avl_reset_reset),             //        avl_reset.reset_n
		.scc_clk                 (p0_scc_clk_clk),                 //          scc_clk.clk
		.reset_n_scc_clk         (p0_scc_reset_reset),             //        scc_reset.reset_n
		.scc_data                (s0_scc_scc_data),                //              scc.scc_data
		.scc_dqs_ena             (s0_scc_scc_dqs_ena),             //                 .scc_dqs_ena
		.scc_dqs_io_ena          (s0_scc_scc_dqs_io_ena),          //                 .scc_dqs_io_ena
		.scc_dq_ena              (s0_scc_scc_dq_ena),              //                 .scc_dq_ena
		.scc_dm_ena              (s0_scc_scc_dm_ena),              //                 .scc_dm_ena
		.capture_strobe_tracking (p0_scc_capture_strobe_tracking), //                 .capture_strobe_tracking
		.scc_upd                 (s0_scc_scc_upd),                 //                 .scc_upd
		.afi_init_req            (c0_afi_afi_init_req),            // afi_init_cal_req.afi_init_req
		.afi_cal_req             (c0_afi_afi_cal_req),             //                 .afi_cal_req
		.avl_address             (s0_avl_address),                 //              avl.address
		.avl_write               (s0_avl_write),                   //                 .write
		.avl_writedata           (s0_avl_writedata),               //                 .writedata
		.avl_read                (s0_avl_read),                    //                 .read
		.avl_readdata            (s0_avl_readdata),                //                 .readdata
		.avl_waitrequest         (s0_avl_waitrequest),             //                 .waitrequest
		.apb_clk                 (p0_avl_clk_clk),                 //          apb_clk.clk
		.apb_reset_n             (p0_avl_reset_reset),             //        apb_reset.reset_n
		.prdata                  (s0_apb_slave_prdata),            //        apb_slave.prdata
		.pready                  (s0_apb_slave_pready),            //                 .pready
		.pslverr                 (s0_apb_slave_pslverr),           //                 .pslverr
		.pwdata                  (avl2apb_apb_master_pwdata),      //                 .pwdata
		.pwrite                  (avl2apb_apb_master_pwrite),      //                 .pwrite
		.penable                 (avl2apb_apb_master_penable),     //                 .penable
		.psel                    (avl2apb_apb_master_psel),        //                 .psel
		.paddr                   (avl2apb_apb_master_paddr),       //                 .paddr
		.mmr_avl_address         (s0_mmr_avl_address),             //          mmr_avl.address
		.mmr_avl_write           (s0_mmr_avl_write),               //                 .write
		.mmr_avl_writedata       (s0_mmr_avl_writedata),           //                 .writedata
		.mmr_avl_read            (s0_mmr_avl_read),                //                 .read
		.mmr_avl_readdata        (s0_mmr_avl_readdata),            //                 .readdata
		.mmr_avl_waitrequest     (s0_mmr_avl_waitrequest),         //                 .waitrequest
		.mmr_avl_burstcount      (s0_mmr_avl_burstcount),          //                 .burstcount
		.mmr_avl_readdatavalid   (s0_mmr_avl_readdatavalid),       //                 .readdatavalid
		.afi_seq_busy            (s0_tracking_afi_seq_busy),       //         tracking.afi_seq_busy
		.afi_ctl_refresh_done    (c0_afi_afi_ctl_refresh_done),    //                 .afi_ctl_refresh_done
		.afi_ctl_long_idle       (c0_afi_afi_ctl_long_idle)        //                 .afi_ctl_long_idle
	);

	altera_mem_if_avalon2apb_bridge #(
		.DWIDTH           (32),
		.AWIDTH           (16),
		.BYTEENABLE_WIDTH (4)
	) avl2apb (
		.av_addr        (mm_interconnect_1_avl2apb_avalon_slave_address),     // avalon_slave.address
		.av_write       (mm_interconnect_1_avl2apb_avalon_slave_write),       //             .write
		.av_read        (mm_interconnect_1_avl2apb_avalon_slave_read),        //             .read
		.av_writedata   (mm_interconnect_1_avl2apb_avalon_slave_writedata),   //             .writedata
		.av_readdata    (mm_interconnect_1_avl2apb_avalon_slave_readdata),    //             .readdata
		.av_byteenable  (mm_interconnect_1_avl2apb_avalon_slave_byteenable),  //             .byteenable
		.av_waitrequest (mm_interconnect_1_avl2apb_avalon_slave_waitrequest), //             .waitrequest
		.prdata         (s0_apb_slave_prdata),                                //   apb_master.prdata
		.pready         (s0_apb_slave_pready),                                //             .pready
		.pslverr        (s0_apb_slave_pslverr),                               //             .pslverr
		.pwdata         (avl2apb_apb_master_pwdata),                          //             .pwdata
		.pwrite         (avl2apb_apb_master_pwrite),                          //             .pwrite
		.penable        (avl2apb_apb_master_penable),                         //             .penable
		.psel           (avl2apb_apb_master_psel),                            //             .psel
		.paddr          (avl2apb_apb_master_paddr),                           //             .paddr
		.pclk           (p0_avl_clk_clk),                                     //         pclk.clk
		.sp_reset_n     (p0_avl_reset_reset)                                  //   sp_reset_n.reset_n
	);

	altera_mem_if_sequencer_mem_no_ifdef_params #(
		.AVL_DATA_WIDTH   (32),
		.AVL_ADDR_WIDTH   (13),
		.AVL_NUM_SYMBOLS  (4),
		.AVL_SYMBOL_WIDTH (8),
		.MEM_SIZE         (32768),
		.INIT_FILE        ("hps_sequencer_mem.hex"),
		.RAM_BLOCK_TYPE   ("AUTO")
	) sequencer_mem (
		.clk1          (p0_avl_clk_clk),                                //   clk1.clk
		.reset1        (~p0_avl_reset_reset),                           // reset1.reset
		.clken1        (),                                              // clken1.clken
		.s1_address    (mm_interconnect_1_sequencer_mem_s1_address),    //     s1.address
		.s1_write      (mm_interconnect_1_sequencer_mem_s1_write),      //       .write
		.s1_writedata  (mm_interconnect_1_sequencer_mem_s1_writedata),  //       .writedata
		.s1_readdata   (mm_interconnect_1_sequencer_mem_s1_readdata),   //       .readdata
		.s1_be         (mm_interconnect_1_sequencer_mem_s1_byteenable), //       .byteenable
		.s1_chipselect (mm_interconnect_1_sequencer_mem_s1_chipselect)  //       .chipselect
	);

	altera_mem_if_sequencer_cpu_cv_sim_cpu_inst #(
		.DEVICE_FAMILY ("CYCLONEV")
	) cpu_inst (
		.clk           (p0_avl_clk_clk),                          //                       clk.clk
		.reset_n       (p0_avl_reset_reset),                      //                   reset_n.reset_n
		.d_address     (cpu_inst_data_master_address),            //               data_master.address
		.d_byteenable  (cpu_inst_data_master_byteenable),         //                          .byteenable
		.d_read        (cpu_inst_data_master_read),               //                          .read
		.d_readdata    (cpu_inst_data_master_readdata),           //                          .readdata
		.d_waitrequest (cpu_inst_data_master_waitrequest),        //                          .waitrequest
		.d_write       (cpu_inst_data_master_write),              //                          .write
		.d_writedata   (cpu_inst_data_master_writedata),          //                          .writedata
		.i_address     (cpu_inst_instruction_master_address),     //        instruction_master.address
		.i_read        (cpu_inst_instruction_master_read),        //                          .read
		.i_readdata    (cpu_inst_instruction_master_readdata),    //                          .readdata
		.i_waitrequest (cpu_inst_instruction_master_waitrequest), //                          .waitrequest
		.d_irq         (cpu_inst_d_irq_irq),                      //                     d_irq.irq
		.no_ci_readra  ()                                         // custom_instruction_master.readra
	);

	altera_mem_if_hps_memory_controller_top c0 (
		.ctl_reset_n          (p0_ctl_reset_reset),                     //    ctl_reset.reset_n
		.ctl_clk              (p0_ctl_clk_clk),                         //      ctl_clk.clk
		.csr_clk              (p0_avl_clk_clk),                         //      csr_clk.clk
		.csr_reset_n          (p0_avl_reset_reset),                     //  csr_reset_n.reset_n
		.cfg_axi_mm_select    (cfg_axi_mm_select),                      //  hps_f2sdram.cfg_axi_mm_select
		.cfg_cport_rfifo_map  (cfg_cport_rfifo_map),                    //             .cfg_cport_rfifo_map
		.cfg_cport_type       (cfg_cport_type),                         //             .cfg_cport_type
		.cfg_cport_wfifo_map  (cfg_cport_wfifo_map),                    //             .cfg_cport_wfifo_map
		.cfg_port_width       (cfg_port_width),                         //             .cfg_port_width
		.cfg_rfifo_cport_map  (cfg_rfifo_cport_map),                    //             .cfg_rfifo_cport_map
		.cfg_wfifo_cport_map  (cfg_wfifo_cport_map),                    //             .cfg_wfifo_cport_map
		.cmd_data_0           (cmd_data_0),                             //             .cmd_data_0
		.cmd_data_1           (cmd_data_1),                             //             .cmd_data_1
		.cmd_data_2           (cmd_data_2),                             //             .cmd_data_2
		.cmd_data_3           (cmd_data_3),                             //             .cmd_data_3
		.cmd_data_4           (cmd_data_4),                             //             .cmd_data_4
		.cmd_data_5           (cmd_data_5),                             //             .cmd_data_5
		.cmd_port_clk_0       (cmd_port_clk_0),                         //             .cmd_port_clk_0
		.cmd_port_clk_1       (cmd_port_clk_1),                         //             .cmd_port_clk_1
		.cmd_port_clk_2       (cmd_port_clk_2),                         //             .cmd_port_clk_2
		.cmd_port_clk_3       (cmd_port_clk_3),                         //             .cmd_port_clk_3
		.cmd_port_clk_4       (cmd_port_clk_4),                         //             .cmd_port_clk_4
		.cmd_port_clk_5       (cmd_port_clk_5),                         //             .cmd_port_clk_5
		.cmd_valid_0          (cmd_valid_0),                            //             .cmd_valid_0
		.cmd_valid_1          (cmd_valid_1),                            //             .cmd_valid_1
		.cmd_valid_2          (cmd_valid_2),                            //             .cmd_valid_2
		.cmd_valid_3          (cmd_valid_3),                            //             .cmd_valid_3
		.cmd_valid_4          (cmd_valid_4),                            //             .cmd_valid_4
		.cmd_valid_5          (cmd_valid_5),                            //             .cmd_valid_5
		.rd_clk_0             (rd_clk_0),                               //             .rd_clk_0
		.rd_clk_1             (rd_clk_1),                               //             .rd_clk_1
		.rd_clk_2             (rd_clk_2),                               //             .rd_clk_2
		.rd_clk_3             (rd_clk_3),                               //             .rd_clk_3
		.rd_ready_0           (rd_ready_0),                             //             .rd_ready_0
		.rd_ready_1           (rd_ready_1),                             //             .rd_ready_1
		.rd_ready_2           (rd_ready_2),                             //             .rd_ready_2
		.rd_ready_3           (rd_ready_3),                             //             .rd_ready_3
		.wr_clk_0             (wr_clk_0),                               //             .wr_clk_0
		.wr_clk_1             (wr_clk_1),                               //             .wr_clk_1
		.wr_clk_2             (wr_clk_2),                               //             .wr_clk_2
		.wr_clk_3             (wr_clk_3),                               //             .wr_clk_3
		.wr_data_0            (wr_data_0),                              //             .wr_data_0
		.wr_data_1            (wr_data_1),                              //             .wr_data_1
		.wr_data_2            (wr_data_2),                              //             .wr_data_2
		.wr_data_3            (wr_data_3),                              //             .wr_data_3
		.wr_valid_0           (wr_valid_0),                             //             .wr_valid_0
		.wr_valid_1           (wr_valid_1),                             //             .wr_valid_1
		.wr_valid_2           (wr_valid_2),                             //             .wr_valid_2
		.wr_valid_3           (wr_valid_3),                             //             .wr_valid_3
		.wrack_ready_0        (wrack_ready_0),                          //             .wrack_ready_0
		.wrack_ready_1        (wrack_ready_1),                          //             .wrack_ready_1
		.wrack_ready_2        (wrack_ready_2),                          //             .wrack_ready_2
		.wrack_ready_3        (wrack_ready_3),                          //             .wrack_ready_3
		.wrack_ready_4        (wrack_ready_4),                          //             .wrack_ready_4
		.wrack_ready_5        (wrack_ready_5),                          //             .wrack_ready_5
		.bonding_out_1        (bonding_out_1),                          //             .bonding_out_1
		.bonding_out_2        (bonding_out_2),                          //             .bonding_out_2
		.cmd_ready_0          (cmd_ready_0),                            //             .cmd_ready_0
		.cmd_ready_1          (cmd_ready_1),                            //             .cmd_ready_1
		.cmd_ready_2          (cmd_ready_2),                            //             .cmd_ready_2
		.cmd_ready_3          (cmd_ready_3),                            //             .cmd_ready_3
		.cmd_ready_4          (cmd_ready_4),                            //             .cmd_ready_4
		.cmd_ready_5          (cmd_ready_5),                            //             .cmd_ready_5
		.rd_data_0            (rd_data_0),                              //             .rd_data_0
		.rd_data_1            (rd_data_1),                              //             .rd_data_1
		.rd_data_2            (rd_data_2),                              //             .rd_data_2
		.rd_data_3            (rd_data_3),                              //             .rd_data_3
		.rd_valid_0           (rd_valid_0),                             //             .rd_valid_0
		.rd_valid_1           (rd_valid_1),                             //             .rd_valid_1
		.rd_valid_2           (rd_valid_2),                             //             .rd_valid_2
		.rd_valid_3           (rd_valid_3),                             //             .rd_valid_3
		.wr_ready_0           (wr_ready_0),                             //             .wr_ready_0
		.wr_ready_1           (wr_ready_1),                             //             .wr_ready_1
		.wr_ready_2           (wr_ready_2),                             //             .wr_ready_2
		.wr_ready_3           (wr_ready_3),                             //             .wr_ready_3
		.wrack_data_0         (wrack_data_0),                           //             .wrack_data_0
		.wrack_data_1         (wrack_data_1),                           //             .wrack_data_1
		.wrack_data_2         (wrack_data_2),                           //             .wrack_data_2
		.wrack_data_3         (wrack_data_3),                           //             .wrack_data_3
		.wrack_data_4         (wrack_data_4),                           //             .wrack_data_4
		.wrack_data_5         (wrack_data_5),                           //             .wrack_data_5
		.wrack_valid_0        (wrack_valid_0),                          //             .wrack_valid_0
		.wrack_valid_1        (wrack_valid_1),                          //             .wrack_valid_1
		.wrack_valid_2        (wrack_valid_2),                          //             .wrack_valid_2
		.wrack_valid_3        (wrack_valid_3),                          //             .wrack_valid_3
		.wrack_valid_4        (wrack_valid_4),                          //             .wrack_valid_4
		.wrack_valid_5        (wrack_valid_5),                          //             .wrack_valid_5
		.csr_write_req        (mm_interconnect_2_c0_csr_write),         //          csr.write
		.csr_read_req         (mm_interconnect_2_c0_csr_read),          //             .read
		.csr_waitrequest      (mm_interconnect_2_c0_csr_waitrequest),   //             .waitrequest
		.csr_addr             (mm_interconnect_2_c0_csr_address),       //             .address
		.csr_be               (mm_interconnect_2_c0_csr_byteenable),    //             .byteenable
		.csr_wdata            (mm_interconnect_2_c0_csr_writedata),     //             .writedata
		.csr_rdata            (mm_interconnect_2_c0_csr_readdata),      //             .readdata
		.csr_rdata_valid      (mm_interconnect_2_c0_csr_readdatavalid), //             .readdatavalid
		.afi_addr             (c0_afi_afi_addr),                        //          afi.afi_addr
		.afi_ba               (c0_afi_afi_ba),                          //             .afi_ba
		.afi_cke              (c0_afi_afi_cke),                         //             .afi_cke
		.afi_cs_n             (c0_afi_afi_cs_n),                        //             .afi_cs_n
		.afi_ras_n            (c0_afi_afi_ras_n),                       //             .afi_ras_n
		.afi_we_n             (c0_afi_afi_we_n),                        //             .afi_we_n
		.afi_cas_n            (c0_afi_afi_cas_n),                       //             .afi_cas_n
		.afi_rst_n            (c0_afi_afi_rst_n),                       //             .afi_rst_n
		.afi_odt              (c0_afi_afi_odt),                         //             .afi_odt
		.afi_mem_clk_disable  (c0_afi_afi_mem_clk_disable),             //             .afi_mem_clk_disable
		.afi_init_req         (c0_afi_afi_init_req),                    //             .afi_init_req
		.afi_cal_req          (c0_afi_afi_cal_req),                     //             .afi_cal_req
		.afi_seq_busy         (s0_tracking_afi_seq_busy),               //             .afi_seq_busy
		.afi_ctl_refresh_done (c0_afi_afi_ctl_refresh_done),            //             .afi_ctl_refresh_done
		.afi_ctl_long_idle    (c0_afi_afi_ctl_long_idle),               //             .afi_ctl_long_idle
		.afi_dqs_burst        (c0_afi_afi_dqs_burst),                   //             .afi_dqs_burst
		.afi_wdata_valid      (c0_afi_afi_wdata_valid),                 //             .afi_wdata_valid
		.afi_wdata            (c0_afi_afi_wdata),                       //             .afi_wdata
		.afi_dm               (c0_afi_afi_dm),                          //             .afi_dm
		.afi_rdata            (p0_afi_afi_rdata),                       //             .afi_rdata
		.afi_rdata_en         (c0_afi_afi_rdata_en),                    //             .afi_rdata_en
		.afi_rdata_en_full    (c0_afi_afi_rdata_en_full),               //             .afi_rdata_en_full
		.afi_rdata_valid      (p0_afi_afi_rdata_valid),                 //             .afi_rdata_valid
		.afi_wlat             (p0_afi_afi_wlat),                        //             .afi_wlat
		.afi_rlat             (p0_afi_afi_rlat),                        //             .afi_rlat
		.afi_cal_success      (p0_afi_afi_cal_success),                 //             .afi_cal_success
		.afi_cal_fail         (p0_afi_afi_cal_fail),                    //             .afi_cal_fail
		.cfg_addlat           (c0_hard_phy_cfg_cfg_addlat),             // hard_phy_cfg.cfg_addlat
		.cfg_bankaddrwidth    (c0_hard_phy_cfg_cfg_bankaddrwidth),      //             .cfg_bankaddrwidth
		.cfg_caswrlat         (c0_hard_phy_cfg_cfg_caswrlat),           //             .cfg_caswrlat
		.cfg_coladdrwidth     (c0_hard_phy_cfg_cfg_coladdrwidth),       //             .cfg_coladdrwidth
		.cfg_csaddrwidth      (c0_hard_phy_cfg_cfg_csaddrwidth),        //             .cfg_csaddrwidth
		.cfg_devicewidth      (c0_hard_phy_cfg_cfg_devicewidth),        //             .cfg_devicewidth
		.cfg_dramconfig       (c0_hard_phy_cfg_cfg_dramconfig),         //             .cfg_dramconfig
		.cfg_interfacewidth   (c0_hard_phy_cfg_cfg_interfacewidth),     //             .cfg_interfacewidth
		.cfg_rowaddrwidth     (c0_hard_phy_cfg_cfg_rowaddrwidth),       //             .cfg_rowaddrwidth
		.cfg_tcl              (c0_hard_phy_cfg_cfg_tcl),                //             .cfg_tcl
		.cfg_tmrd             (c0_hard_phy_cfg_cfg_tmrd),               //             .cfg_tmrd
		.cfg_trefi            (c0_hard_phy_cfg_cfg_trefi),              //             .cfg_trefi
		.cfg_trfc             (c0_hard_phy_cfg_cfg_trfc),               //             .cfg_trfc
		.cfg_twr              (c0_hard_phy_cfg_cfg_twr)                 //             .cfg_twr
	);

	alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en #(
		.MEM_IF_ADDR_WIDTH            (15),
		.MEM_IF_ROW_ADDR_WIDTH        (15),
		.MEM_IF_COL_ADDR_WIDTH        (10),
		.MEM_IF_CONTROL_WIDTH         (1),
		.MEM_IF_DQS_WIDTH             (5),
		.MEM_IF_CS_WIDTH              (1),
		.MEM_IF_BANKADDR_WIDTH        (3),
		.MEM_IF_DQ_WIDTH              (40),
		.MEM_IF_CK_WIDTH              (1),
		.MEM_IF_CLK_EN_WIDTH          (1),
		.MEM_TRCD                     (6),
		.MEM_TRTP                     (4),
		.MEM_DQS_TO_CLK_CAPTURE_DELAY (450),
		.MEM_CLK_TO_DQS_CAPTURE_DELAY (100000),
		.MEM_IF_ODT_WIDTH             (1),
		.MEM_IF_LRDIMM_RM             (0),
		.MEM_MIRROR_ADDRESSING_DEC    (0),
		.MEM_REGDIMM_ENABLED          (0),
		.MEM_LRDIMM_ENABLED           (0),
		.DEVICE_DEPTH                 (1),
		.MEM_NUMBER_OF_DIMMS          (1),
		.MEM_NUMBER_OF_RANKS_PER_DIMM (1),
		.MEM_GUARANTEED_WRITE_INIT    (0),
		.MEM_VERBOSE                  (1),
		.REFRESH_BURST_VALIDATION     (0),
		.AP_MODE_EN                   (2'b00),
		.MEM_INIT_EN                  (0),
		.MEM_INIT_FILE                (""),
		.DAT_DATA_WIDTH               (32)
	) mem (
		.mem_a       (p0_memory_mem_a),       // memory.mem_a
		.mem_ba      (p0_memory_mem_ba),      //       .mem_ba
		.mem_ck      (p0_memory_mem_ck),      //       .mem_ck
		.mem_ck_n    (p0_memory_mem_ck_n),    //       .mem_ck_n
		.mem_cke     (p0_memory_mem_cke),     //       .mem_cke
		.mem_cs_n    (p0_memory_mem_cs_n),    //       .mem_cs_n
		.mem_dm      (p0_memory_mem_dm),      //       .mem_dm
		.mem_ras_n   (p0_memory_mem_ras_n),   //       .mem_ras_n
		.mem_cas_n   (p0_memory_mem_cas_n),   //       .mem_cas_n
		.mem_we_n    (p0_memory_mem_we_n),    //       .mem_we_n
		.mem_reset_n (p0_memory_mem_reset_n), //       .mem_reset_n
		.mem_dq      (mem_memory_mem_dq),     //       .mem_dq
		.mem_dqs     (mem_memory_mem_dqs),    //       .mem_dqs
		.mem_dqs_n   (mem_memory_mem_dqs_n),  //       .mem_dqs_n
		.mem_odt     (p0_memory_mem_odt)      //       .mem_odt
	);

	altera_mem_if_oct_cyclonev #(
		.OCT_TERM_CONTROL_WIDTH (16)
	) oct (
		.oct_rzqin                  (), //         oct.rzqin
		.seriesterminationcontrol   (), // oct_sharing.seriesterminationcontrol
		.parallelterminationcontrol ()  //            .parallelterminationcontrol
	);

	altera_mem_if_dll_cyclonev #(
		.DLL_DELAY_CTRL_WIDTH       (7),
		.DLL_OFFSET_CTRL_WIDTH      (6),
		.DELAY_BUFFER_MODE          ("HIGH"),
		.DELAY_CHAIN_LENGTH         (8),
		.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
	) dll (
		.clk            (p0_dll_clk_clk),                //         clk.clk
		.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
		.dll_delayctrl  (dll_dll_sharing_dll_delayctrl)  //            .dll_delayctrl
	);

	hps_sdram_mm_interconnect_1 mm_interconnect_1 (
		.p0_avl_clk_clk                               (p0_avl_clk_clk),                                     //                             p0_avl_clk.clk
		.cpu_inst_reset_n_reset_bridge_in_reset_reset (~p0_avl_reset_reset),                                // cpu_inst_reset_n_reset_bridge_in_reset.reset
		.cpu_inst_data_master_address                 (cpu_inst_data_master_address),                       //                   cpu_inst_data_master.address
		.cpu_inst_data_master_waitrequest             (cpu_inst_data_master_waitrequest),                   //                                       .waitrequest
		.cpu_inst_data_master_byteenable              (cpu_inst_data_master_byteenable),                    //                                       .byteenable
		.cpu_inst_data_master_read                    (cpu_inst_data_master_read),                          //                                       .read
		.cpu_inst_data_master_readdata                (cpu_inst_data_master_readdata),                      //                                       .readdata
		.cpu_inst_data_master_write                   (cpu_inst_data_master_write),                         //                                       .write
		.cpu_inst_data_master_writedata               (cpu_inst_data_master_writedata),                     //                                       .writedata
		.cpu_inst_instruction_master_address          (cpu_inst_instruction_master_address),                //            cpu_inst_instruction_master.address
		.cpu_inst_instruction_master_waitrequest      (cpu_inst_instruction_master_waitrequest),            //                                       .waitrequest
		.cpu_inst_instruction_master_read             (cpu_inst_instruction_master_read),                   //                                       .read
		.cpu_inst_instruction_master_readdata         (cpu_inst_instruction_master_readdata),               //                                       .readdata
		.avl2apb_avalon_slave_address                 (mm_interconnect_1_avl2apb_avalon_slave_address),     //                   avl2apb_avalon_slave.address
		.avl2apb_avalon_slave_write                   (mm_interconnect_1_avl2apb_avalon_slave_write),       //                                       .write
		.avl2apb_avalon_slave_read                    (mm_interconnect_1_avl2apb_avalon_slave_read),        //                                       .read
		.avl2apb_avalon_slave_readdata                (mm_interconnect_1_avl2apb_avalon_slave_readdata),    //                                       .readdata
		.avl2apb_avalon_slave_writedata               (mm_interconnect_1_avl2apb_avalon_slave_writedata),   //                                       .writedata
		.avl2apb_avalon_slave_byteenable              (mm_interconnect_1_avl2apb_avalon_slave_byteenable),  //                                       .byteenable
		.avl2apb_avalon_slave_waitrequest             (mm_interconnect_1_avl2apb_avalon_slave_waitrequest), //                                       .waitrequest
		.sequencer_mem_s1_address                     (mm_interconnect_1_sequencer_mem_s1_address),         //                       sequencer_mem_s1.address
		.sequencer_mem_s1_write                       (mm_interconnect_1_sequencer_mem_s1_write),           //                                       .write
		.sequencer_mem_s1_readdata                    (mm_interconnect_1_sequencer_mem_s1_readdata),        //                                       .readdata
		.sequencer_mem_s1_writedata                   (mm_interconnect_1_sequencer_mem_s1_writedata),       //                                       .writedata
		.sequencer_mem_s1_byteenable                  (mm_interconnect_1_sequencer_mem_s1_byteenable),      //                                       .byteenable
		.sequencer_mem_s1_chipselect                  (mm_interconnect_1_sequencer_mem_s1_chipselect)       //                                       .chipselect
	);

	hps_sdram_mm_interconnect_2 mm_interconnect_2 (
		.p0_avl_clk_clk                             (p0_avl_clk_clk),                         //                           p0_avl_clk.clk
		.c0_csr_reset_n_reset_bridge_in_reset_reset (~p0_avl_reset_reset),                    // c0_csr_reset_n_reset_bridge_in_reset.reset
		.s0_avl_reset_reset_bridge_in_reset_reset   (~p0_avl_reset_reset),                    //   s0_avl_reset_reset_bridge_in_reset.reset
		.s0_mmr_avl_address                         (s0_mmr_avl_address),                     //                           s0_mmr_avl.address
		.s0_mmr_avl_waitrequest                     (s0_mmr_avl_waitrequest),                 //                                     .waitrequest
		.s0_mmr_avl_burstcount                      (s0_mmr_avl_burstcount),                  //                                     .burstcount
		.s0_mmr_avl_read                            (s0_mmr_avl_read),                        //                                     .read
		.s0_mmr_avl_readdata                        (s0_mmr_avl_readdata),                    //                                     .readdata
		.s0_mmr_avl_readdatavalid                   (s0_mmr_avl_readdatavalid),               //                                     .readdatavalid
		.s0_mmr_avl_write                           (s0_mmr_avl_write),                       //                                     .write
		.s0_mmr_avl_writedata                       (s0_mmr_avl_writedata),                   //                                     .writedata
		.c0_csr_address                             (mm_interconnect_2_c0_csr_address),       //                               c0_csr.address
		.c0_csr_write                               (mm_interconnect_2_c0_csr_write),         //                                     .write
		.c0_csr_read                                (mm_interconnect_2_c0_csr_read),          //                                     .read
		.c0_csr_readdata                            (mm_interconnect_2_c0_csr_readdata),      //                                     .readdata
		.c0_csr_writedata                           (mm_interconnect_2_c0_csr_writedata),     //                                     .writedata
		.c0_csr_byteenable                          (mm_interconnect_2_c0_csr_byteenable),    //                                     .byteenable
		.c0_csr_readdatavalid                       (mm_interconnect_2_c0_csr_readdatavalid), //                                     .readdatavalid
		.c0_csr_waitrequest                         (mm_interconnect_2_c0_csr_waitrequest)    //                                     .waitrequest
	);

	hps_sdram_irq_mapper irq_mapper (
		.clk        (p0_avl_clk_clk),      //       clk.clk
		.reset      (~p0_avl_reset_reset), // clk_reset.reset
		.sender_irq (cpu_inst_d_irq_irq)   //    sender.irq
	);

endmodule
