// system_acl_iface_mm_interconnect_2.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 15.1 193

`timescale 1 ps / 1 ps
module system_acl_iface_mm_interconnect_2 (
		input  wire         pll_outclk0_clk,                                                  //                                                pll_outclk0.clk
		input  wire         address_span_extender_kernel_reset_reset_bridge_in_reset_reset,   //   address_span_extender_kernel_reset_reset_bridge_in_reset.reset
		input  wire         hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset, // hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset.reset
		input  wire [31:0]  address_span_extender_kernel_expanded_master_address,             //               address_span_extender_kernel_expanded_master.address
		output wire         address_span_extender_kernel_expanded_master_waitrequest,         //                                                           .waitrequest
		input  wire [4:0]   address_span_extender_kernel_expanded_master_burstcount,          //                                                           .burstcount
		input  wire [31:0]  address_span_extender_kernel_expanded_master_byteenable,          //                                                           .byteenable
		input  wire         address_span_extender_kernel_expanded_master_read,                //                                                           .read
		output wire [255:0] address_span_extender_kernel_expanded_master_readdata,            //                                                           .readdata
		output wire         address_span_extender_kernel_expanded_master_readdatavalid,       //                                                           .readdatavalid
		input  wire         address_span_extender_kernel_expanded_master_write,               //                                                           .write
		input  wire [255:0] address_span_extender_kernel_expanded_master_writedata,           //                                                           .writedata
		output wire [26:0]  hps_f2h_sdram0_data_address,                                      //                                        hps_f2h_sdram0_data.address
		output wire         hps_f2h_sdram0_data_write,                                        //                                                           .write
		output wire         hps_f2h_sdram0_data_read,                                         //                                                           .read
		input  wire [255:0] hps_f2h_sdram0_data_readdata,                                     //                                                           .readdata
		output wire [255:0] hps_f2h_sdram0_data_writedata,                                    //                                                           .writedata
		output wire [7:0]   hps_f2h_sdram0_data_burstcount,                                   //                                                           .burstcount
		output wire [31:0]  hps_f2h_sdram0_data_byteenable,                                   //                                                           .byteenable
		input  wire         hps_f2h_sdram0_data_readdatavalid,                                //                                                           .readdatavalid
		input  wire         hps_f2h_sdram0_data_waitrequest                                   //                                                           .waitrequest
	);

	wire          address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_waitrequest;   // address_span_extender_kernel_expanded_master_agent:av_waitrequest -> address_span_extender_kernel_expanded_master_translator:uav_waitrequest
	wire  [255:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdata;      // address_span_extender_kernel_expanded_master_agent:av_readdata -> address_span_extender_kernel_expanded_master_translator:uav_readdata
	wire          address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_debugaccess;   // address_span_extender_kernel_expanded_master_translator:uav_debugaccess -> address_span_extender_kernel_expanded_master_agent:av_debugaccess
	wire   [31:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_address;       // address_span_extender_kernel_expanded_master_translator:uav_address -> address_span_extender_kernel_expanded_master_agent:av_address
	wire          address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_read;          // address_span_extender_kernel_expanded_master_translator:uav_read -> address_span_extender_kernel_expanded_master_agent:av_read
	wire   [31:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_byteenable;    // address_span_extender_kernel_expanded_master_translator:uav_byteenable -> address_span_extender_kernel_expanded_master_agent:av_byteenable
	wire          address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_kernel_expanded_master_agent:av_readdatavalid -> address_span_extender_kernel_expanded_master_translator:uav_readdatavalid
	wire          address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_lock;          // address_span_extender_kernel_expanded_master_translator:uav_lock -> address_span_extender_kernel_expanded_master_agent:av_lock
	wire          address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_write;         // address_span_extender_kernel_expanded_master_translator:uav_write -> address_span_extender_kernel_expanded_master_agent:av_write
	wire  [255:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_writedata;     // address_span_extender_kernel_expanded_master_translator:uav_writedata -> address_span_extender_kernel_expanded_master_agent:av_writedata
	wire    [9:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_burstcount;    // address_span_extender_kernel_expanded_master_translator:uav_burstcount -> address_span_extender_kernel_expanded_master_agent:av_burstcount
	wire          rsp_mux_src_valid;                                                                               // rsp_mux:src_valid -> address_span_extender_kernel_expanded_master_agent:rp_valid
	wire  [363:0] rsp_mux_src_data;                                                                                // rsp_mux:src_data -> address_span_extender_kernel_expanded_master_agent:rp_data
	wire          rsp_mux_src_ready;                                                                               // address_span_extender_kernel_expanded_master_agent:rp_ready -> rsp_mux:src_ready
	wire    [0:0] rsp_mux_src_channel;                                                                             // rsp_mux:src_channel -> address_span_extender_kernel_expanded_master_agent:rp_channel
	wire          rsp_mux_src_startofpacket;                                                                       // rsp_mux:src_startofpacket -> address_span_extender_kernel_expanded_master_agent:rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                                                         // rsp_mux:src_endofpacket -> address_span_extender_kernel_expanded_master_agent:rp_endofpacket
	wire  [255:0] hps_f2h_sdram0_data_agent_m0_readdata;                                                           // hps_f2h_sdram0_data_translator:uav_readdata -> hps_f2h_sdram0_data_agent:m0_readdata
	wire          hps_f2h_sdram0_data_agent_m0_waitrequest;                                                        // hps_f2h_sdram0_data_translator:uav_waitrequest -> hps_f2h_sdram0_data_agent:m0_waitrequest
	wire          hps_f2h_sdram0_data_agent_m0_debugaccess;                                                        // hps_f2h_sdram0_data_agent:m0_debugaccess -> hps_f2h_sdram0_data_translator:uav_debugaccess
	wire   [31:0] hps_f2h_sdram0_data_agent_m0_address;                                                            // hps_f2h_sdram0_data_agent:m0_address -> hps_f2h_sdram0_data_translator:uav_address
	wire   [31:0] hps_f2h_sdram0_data_agent_m0_byteenable;                                                         // hps_f2h_sdram0_data_agent:m0_byteenable -> hps_f2h_sdram0_data_translator:uav_byteenable
	wire          hps_f2h_sdram0_data_agent_m0_read;                                                               // hps_f2h_sdram0_data_agent:m0_read -> hps_f2h_sdram0_data_translator:uav_read
	wire          hps_f2h_sdram0_data_agent_m0_readdatavalid;                                                      // hps_f2h_sdram0_data_translator:uav_readdatavalid -> hps_f2h_sdram0_data_agent:m0_readdatavalid
	wire          hps_f2h_sdram0_data_agent_m0_lock;                                                               // hps_f2h_sdram0_data_agent:m0_lock -> hps_f2h_sdram0_data_translator:uav_lock
	wire  [255:0] hps_f2h_sdram0_data_agent_m0_writedata;                                                          // hps_f2h_sdram0_data_agent:m0_writedata -> hps_f2h_sdram0_data_translator:uav_writedata
	wire          hps_f2h_sdram0_data_agent_m0_write;                                                              // hps_f2h_sdram0_data_agent:m0_write -> hps_f2h_sdram0_data_translator:uav_write
	wire   [12:0] hps_f2h_sdram0_data_agent_m0_burstcount;                                                         // hps_f2h_sdram0_data_agent:m0_burstcount -> hps_f2h_sdram0_data_translator:uav_burstcount
	wire          hps_f2h_sdram0_data_agent_rf_source_valid;                                                       // hps_f2h_sdram0_data_agent:rf_source_valid -> hps_f2h_sdram0_data_agent_rsp_fifo:in_valid
	wire  [364:0] hps_f2h_sdram0_data_agent_rf_source_data;                                                        // hps_f2h_sdram0_data_agent:rf_source_data -> hps_f2h_sdram0_data_agent_rsp_fifo:in_data
	wire          hps_f2h_sdram0_data_agent_rf_source_ready;                                                       // hps_f2h_sdram0_data_agent_rsp_fifo:in_ready -> hps_f2h_sdram0_data_agent:rf_source_ready
	wire          hps_f2h_sdram0_data_agent_rf_source_startofpacket;                                               // hps_f2h_sdram0_data_agent:rf_source_startofpacket -> hps_f2h_sdram0_data_agent_rsp_fifo:in_startofpacket
	wire          hps_f2h_sdram0_data_agent_rf_source_endofpacket;                                                 // hps_f2h_sdram0_data_agent:rf_source_endofpacket -> hps_f2h_sdram0_data_agent_rsp_fifo:in_endofpacket
	wire          hps_f2h_sdram0_data_agent_rsp_fifo_out_valid;                                                    // hps_f2h_sdram0_data_agent_rsp_fifo:out_valid -> hps_f2h_sdram0_data_agent:rf_sink_valid
	wire  [364:0] hps_f2h_sdram0_data_agent_rsp_fifo_out_data;                                                     // hps_f2h_sdram0_data_agent_rsp_fifo:out_data -> hps_f2h_sdram0_data_agent:rf_sink_data
	wire          hps_f2h_sdram0_data_agent_rsp_fifo_out_ready;                                                    // hps_f2h_sdram0_data_agent:rf_sink_ready -> hps_f2h_sdram0_data_agent_rsp_fifo:out_ready
	wire          hps_f2h_sdram0_data_agent_rsp_fifo_out_startofpacket;                                            // hps_f2h_sdram0_data_agent_rsp_fifo:out_startofpacket -> hps_f2h_sdram0_data_agent:rf_sink_startofpacket
	wire          hps_f2h_sdram0_data_agent_rsp_fifo_out_endofpacket;                                              // hps_f2h_sdram0_data_agent_rsp_fifo:out_endofpacket -> hps_f2h_sdram0_data_agent:rf_sink_endofpacket
	wire          cmd_mux_src_valid;                                                                               // cmd_mux:src_valid -> hps_f2h_sdram0_data_agent:cp_valid
	wire  [363:0] cmd_mux_src_data;                                                                                // cmd_mux:src_data -> hps_f2h_sdram0_data_agent:cp_data
	wire          cmd_mux_src_ready;                                                                               // hps_f2h_sdram0_data_agent:cp_ready -> cmd_mux:src_ready
	wire    [0:0] cmd_mux_src_channel;                                                                             // cmd_mux:src_channel -> hps_f2h_sdram0_data_agent:cp_channel
	wire          cmd_mux_src_startofpacket;                                                                       // cmd_mux:src_startofpacket -> hps_f2h_sdram0_data_agent:cp_startofpacket
	wire          cmd_mux_src_endofpacket;                                                                         // cmd_mux:src_endofpacket -> hps_f2h_sdram0_data_agent:cp_endofpacket
	wire          address_span_extender_kernel_expanded_master_agent_cp_valid;                                     // address_span_extender_kernel_expanded_master_agent:cp_valid -> router:sink_valid
	wire  [363:0] address_span_extender_kernel_expanded_master_agent_cp_data;                                      // address_span_extender_kernel_expanded_master_agent:cp_data -> router:sink_data
	wire          address_span_extender_kernel_expanded_master_agent_cp_ready;                                     // router:sink_ready -> address_span_extender_kernel_expanded_master_agent:cp_ready
	wire          address_span_extender_kernel_expanded_master_agent_cp_startofpacket;                             // address_span_extender_kernel_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
	wire          address_span_extender_kernel_expanded_master_agent_cp_endofpacket;                               // address_span_extender_kernel_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                                                // router:src_valid -> cmd_demux:sink_valid
	wire  [363:0] router_src_data;                                                                                 // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                                                                // cmd_demux:sink_ready -> router:src_ready
	wire    [0:0] router_src_channel;                                                                              // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                                                        // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                                                          // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          hps_f2h_sdram0_data_agent_rp_valid;                                                              // hps_f2h_sdram0_data_agent:rp_valid -> router_001:sink_valid
	wire  [363:0] hps_f2h_sdram0_data_agent_rp_data;                                                               // hps_f2h_sdram0_data_agent:rp_data -> router_001:sink_data
	wire          hps_f2h_sdram0_data_agent_rp_ready;                                                              // router_001:sink_ready -> hps_f2h_sdram0_data_agent:rp_ready
	wire          hps_f2h_sdram0_data_agent_rp_startofpacket;                                                      // hps_f2h_sdram0_data_agent:rp_startofpacket -> router_001:sink_startofpacket
	wire          hps_f2h_sdram0_data_agent_rp_endofpacket;                                                        // hps_f2h_sdram0_data_agent:rp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                                            // router_001:src_valid -> rsp_demux:sink_valid
	wire  [363:0] router_001_src_data;                                                                             // router_001:src_data -> rsp_demux:sink_data
	wire          router_001_src_ready;                                                                            // rsp_demux:sink_ready -> router_001:src_ready
	wire    [0:0] router_001_src_channel;                                                                          // router_001:src_channel -> rsp_demux:sink_channel
	wire          router_001_src_startofpacket;                                                                    // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_001_src_endofpacket;                                                                      // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          cmd_demux_src0_valid;                                                                            // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [363:0] cmd_demux_src0_data;                                                                             // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                                            // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [0:0] cmd_demux_src0_channel;                                                                          // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                                                    // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                                      // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                                                            // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [363:0] rsp_demux_src0_data;                                                                             // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                                            // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [0:0] rsp_demux_src0_channel;                                                                          // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                                                    // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                                      // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          hps_f2h_sdram0_data_agent_rdata_fifo_src_valid;                                                  // hps_f2h_sdram0_data_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
	wire  [257:0] hps_f2h_sdram0_data_agent_rdata_fifo_src_data;                                                   // hps_f2h_sdram0_data_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
	wire          hps_f2h_sdram0_data_agent_rdata_fifo_src_ready;                                                  // avalon_st_adapter:in_0_ready -> hps_f2h_sdram0_data_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_out_0_valid;                                                                   // avalon_st_adapter:out_0_valid -> hps_f2h_sdram0_data_agent:rdata_fifo_sink_valid
	wire  [257:0] avalon_st_adapter_out_0_data;                                                                    // avalon_st_adapter:out_0_data -> hps_f2h_sdram0_data_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                                                   // hps_f2h_sdram0_data_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                                                   // avalon_st_adapter:out_0_error -> hps_f2h_sdram0_data_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (256),
		.AV_BURSTCOUNT_W             (5),
		.AV_BYTEENABLE_W             (32),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (32),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) address_span_extender_kernel_expanded_master_translator (
		.clk                    (pll_outclk0_clk),                                                                                 //                       clk.clk
		.reset                  (address_span_extender_kernel_reset_reset_bridge_in_reset_reset),                                  //                     reset.reset
		.uav_address            (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (address_span_extender_kernel_expanded_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (address_span_extender_kernel_expanded_master_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (address_span_extender_kernel_expanded_master_burstcount),                                         //                          .burstcount
		.av_byteenable          (address_span_extender_kernel_expanded_master_byteenable),                                         //                          .byteenable
		.av_read                (address_span_extender_kernel_expanded_master_read),                                               //                          .read
		.av_readdata            (address_span_extender_kernel_expanded_master_readdata),                                           //                          .readdata
		.av_readdatavalid       (address_span_extender_kernel_expanded_master_readdatavalid),                                      //                          .readdatavalid
		.av_write               (address_span_extender_kernel_expanded_master_write),                                              //                          .write
		.av_writedata           (address_span_extender_kernel_expanded_master_writedata),                                          //                          .writedata
		.av_beginbursttransfer  (1'b0),                                                                                            //               (terminated)
		.av_begintransfer       (1'b0),                                                                                            //               (terminated)
		.av_chipselect          (1'b0),                                                                                            //               (terminated)
		.av_lock                (1'b0),                                                                                            //               (terminated)
		.av_debugaccess         (1'b0),                                                                                            //               (terminated)
		.uav_clken              (),                                                                                                //               (terminated)
		.av_clken               (1'b1),                                                                                            //               (terminated)
		.uav_response           (2'b00),                                                                                           //               (terminated)
		.av_response            (),                                                                                                //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                                            //               (terminated)
		.av_writeresponsevalid  ()                                                                                                 //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (27),
		.AV_DATA_W                      (256),
		.UAV_DATA_W                     (256),
		.AV_BURSTCOUNT_W                (8),
		.AV_BYTEENABLE_W                (32),
		.UAV_BYTEENABLE_W               (32),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (13),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (32),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hps_f2h_sdram0_data_translator (
		.clk                    (pll_outclk0_clk),                                                  //                      clk.clk
		.reset                  (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (hps_f2h_sdram0_data_agent_m0_address),                             // avalon_universal_slave_0.address
		.uav_burstcount         (hps_f2h_sdram0_data_agent_m0_burstcount),                          //                         .burstcount
		.uav_read               (hps_f2h_sdram0_data_agent_m0_read),                                //                         .read
		.uav_write              (hps_f2h_sdram0_data_agent_m0_write),                               //                         .write
		.uav_waitrequest        (hps_f2h_sdram0_data_agent_m0_waitrequest),                         //                         .waitrequest
		.uav_readdatavalid      (hps_f2h_sdram0_data_agent_m0_readdatavalid),                       //                         .readdatavalid
		.uav_byteenable         (hps_f2h_sdram0_data_agent_m0_byteenable),                          //                         .byteenable
		.uav_readdata           (hps_f2h_sdram0_data_agent_m0_readdata),                            //                         .readdata
		.uav_writedata          (hps_f2h_sdram0_data_agent_m0_writedata),                           //                         .writedata
		.uav_lock               (hps_f2h_sdram0_data_agent_m0_lock),                                //                         .lock
		.uav_debugaccess        (hps_f2h_sdram0_data_agent_m0_debugaccess),                         //                         .debugaccess
		.av_address             (hps_f2h_sdram0_data_address),                                      //      avalon_anti_slave_0.address
		.av_write               (hps_f2h_sdram0_data_write),                                        //                         .write
		.av_read                (hps_f2h_sdram0_data_read),                                         //                         .read
		.av_readdata            (hps_f2h_sdram0_data_readdata),                                     //                         .readdata
		.av_writedata           (hps_f2h_sdram0_data_writedata),                                    //                         .writedata
		.av_burstcount          (hps_f2h_sdram0_data_burstcount),                                   //                         .burstcount
		.av_byteenable          (hps_f2h_sdram0_data_byteenable),                                   //                         .byteenable
		.av_readdatavalid       (hps_f2h_sdram0_data_readdatavalid),                                //                         .readdatavalid
		.av_waitrequest         (hps_f2h_sdram0_data_waitrequest),                                  //                         .waitrequest
		.av_begintransfer       (),                                                                 //              (terminated)
		.av_beginbursttransfer  (),                                                                 //              (terminated)
		.av_writebyteenable     (),                                                                 //              (terminated)
		.av_lock                (),                                                                 //              (terminated)
		.av_chipselect          (),                                                                 //              (terminated)
		.av_clken               (),                                                                 //              (terminated)
		.uav_clken              (1'b0),                                                             //              (terminated)
		.av_debugaccess         (),                                                                 //              (terminated)
		.av_outputenable        (),                                                                 //              (terminated)
		.uav_response           (),                                                                 //              (terminated)
		.av_response            (2'b00),                                                            //              (terminated)
		.uav_writeresponsevalid (),                                                                 //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                              //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (363),
		.PKT_ORI_BURST_SIZE_L      (361),
		.PKT_RESPONSE_STATUS_H     (360),
		.PKT_RESPONSE_STATUS_L     (359),
		.PKT_QOS_H                 (348),
		.PKT_QOS_L                 (348),
		.PKT_DATA_SIDEBAND_H       (346),
		.PKT_DATA_SIDEBAND_L       (346),
		.PKT_ADDR_SIDEBAND_H       (345),
		.PKT_ADDR_SIDEBAND_L       (345),
		.PKT_BURST_TYPE_H          (344),
		.PKT_BURST_TYPE_L          (343),
		.PKT_CACHE_H               (358),
		.PKT_CACHE_L               (355),
		.PKT_THREAD_ID_H           (351),
		.PKT_THREAD_ID_L           (351),
		.PKT_BURST_SIZE_H          (342),
		.PKT_BURST_SIZE_L          (340),
		.PKT_TRANS_EXCLUSIVE       (325),
		.PKT_TRANS_LOCK            (324),
		.PKT_BEGIN_BURST           (347),
		.PKT_PROTECTION_H          (354),
		.PKT_PROTECTION_L          (352),
		.PKT_BURSTWRAP_H           (339),
		.PKT_BURSTWRAP_L           (339),
		.PKT_BYTE_CNT_H            (338),
		.PKT_BYTE_CNT_L            (326),
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_POSTED          (321),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_SRC_ID_H              (349),
		.PKT_SRC_ID_L              (349),
		.PKT_DEST_ID_H             (350),
		.PKT_DEST_ID_L             (350),
		.ST_DATA_W                 (364),
		.ST_CHANNEL_W              (1),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) address_span_extender_kernel_expanded_master_agent (
		.clk                   (pll_outclk0_clk),                                                                                 //       clk.clk
		.reset                 (address_span_extender_kernel_reset_reset_bridge_in_reset_reset),                                  // clk_reset.reset
		.av_address            (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (address_span_extender_kernel_expanded_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (address_span_extender_kernel_expanded_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (address_span_extender_kernel_expanded_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (address_span_extender_kernel_expanded_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (address_span_extender_kernel_expanded_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_src_valid),                                                                               //        rp.valid
		.rp_data               (rsp_mux_src_data),                                                                                //          .data
		.rp_channel            (rsp_mux_src_channel),                                                                             //          .channel
		.rp_startofpacket      (rsp_mux_src_startofpacket),                                                                       //          .startofpacket
		.rp_endofpacket        (rsp_mux_src_endofpacket),                                                                         //          .endofpacket
		.rp_ready              (rsp_mux_src_ready),                                                                               //          .ready
		.av_response           (),                                                                                                // (terminated)
		.av_writeresponsevalid ()                                                                                                 // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (363),
		.PKT_ORI_BURST_SIZE_L      (361),
		.PKT_RESPONSE_STATUS_H     (360),
		.PKT_RESPONSE_STATUS_L     (359),
		.PKT_BURST_SIZE_H          (342),
		.PKT_BURST_SIZE_L          (340),
		.PKT_TRANS_LOCK            (324),
		.PKT_BEGIN_BURST           (347),
		.PKT_PROTECTION_H          (354),
		.PKT_PROTECTION_L          (352),
		.PKT_BURSTWRAP_H           (339),
		.PKT_BURSTWRAP_L           (339),
		.PKT_BYTE_CNT_H            (338),
		.PKT_BYTE_CNT_L            (326),
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_POSTED          (321),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_SRC_ID_H              (349),
		.PKT_SRC_ID_L              (349),
		.PKT_DEST_ID_H             (350),
		.PKT_DEST_ID_L             (350),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (1),
		.ST_DATA_W                 (364),
		.AVS_BURSTCOUNT_W          (13),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) hps_f2h_sdram0_data_agent (
		.clk                     (pll_outclk0_clk),                                                  //             clk.clk
		.reset                   (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (hps_f2h_sdram0_data_agent_m0_address),                             //              m0.address
		.m0_burstcount           (hps_f2h_sdram0_data_agent_m0_burstcount),                          //                .burstcount
		.m0_byteenable           (hps_f2h_sdram0_data_agent_m0_byteenable),                          //                .byteenable
		.m0_debugaccess          (hps_f2h_sdram0_data_agent_m0_debugaccess),                         //                .debugaccess
		.m0_lock                 (hps_f2h_sdram0_data_agent_m0_lock),                                //                .lock
		.m0_readdata             (hps_f2h_sdram0_data_agent_m0_readdata),                            //                .readdata
		.m0_readdatavalid        (hps_f2h_sdram0_data_agent_m0_readdatavalid),                       //                .readdatavalid
		.m0_read                 (hps_f2h_sdram0_data_agent_m0_read),                                //                .read
		.m0_waitrequest          (hps_f2h_sdram0_data_agent_m0_waitrequest),                         //                .waitrequest
		.m0_writedata            (hps_f2h_sdram0_data_agent_m0_writedata),                           //                .writedata
		.m0_write                (hps_f2h_sdram0_data_agent_m0_write),                               //                .write
		.rp_endofpacket          (hps_f2h_sdram0_data_agent_rp_endofpacket),                         //              rp.endofpacket
		.rp_ready                (hps_f2h_sdram0_data_agent_rp_ready),                               //                .ready
		.rp_valid                (hps_f2h_sdram0_data_agent_rp_valid),                               //                .valid
		.rp_data                 (hps_f2h_sdram0_data_agent_rp_data),                                //                .data
		.rp_startofpacket        (hps_f2h_sdram0_data_agent_rp_startofpacket),                       //                .startofpacket
		.cp_ready                (cmd_mux_src_ready),                                                //              cp.ready
		.cp_valid                (cmd_mux_src_valid),                                                //                .valid
		.cp_data                 (cmd_mux_src_data),                                                 //                .data
		.cp_startofpacket        (cmd_mux_src_startofpacket),                                        //                .startofpacket
		.cp_endofpacket          (cmd_mux_src_endofpacket),                                          //                .endofpacket
		.cp_channel              (cmd_mux_src_channel),                                              //                .channel
		.rf_sink_ready           (hps_f2h_sdram0_data_agent_rsp_fifo_out_ready),                     //         rf_sink.ready
		.rf_sink_valid           (hps_f2h_sdram0_data_agent_rsp_fifo_out_valid),                     //                .valid
		.rf_sink_startofpacket   (hps_f2h_sdram0_data_agent_rsp_fifo_out_startofpacket),             //                .startofpacket
		.rf_sink_endofpacket     (hps_f2h_sdram0_data_agent_rsp_fifo_out_endofpacket),               //                .endofpacket
		.rf_sink_data            (hps_f2h_sdram0_data_agent_rsp_fifo_out_data),                      //                .data
		.rf_source_ready         (hps_f2h_sdram0_data_agent_rf_source_ready),                        //       rf_source.ready
		.rf_source_valid         (hps_f2h_sdram0_data_agent_rf_source_valid),                        //                .valid
		.rf_source_startofpacket (hps_f2h_sdram0_data_agent_rf_source_startofpacket),                //                .startofpacket
		.rf_source_endofpacket   (hps_f2h_sdram0_data_agent_rf_source_endofpacket),                  //                .endofpacket
		.rf_source_data          (hps_f2h_sdram0_data_agent_rf_source_data),                         //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                    // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                    //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                     //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                    //                .error
		.rdata_fifo_src_ready    (hps_f2h_sdram0_data_agent_rdata_fifo_src_ready),                   //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hps_f2h_sdram0_data_agent_rdata_fifo_src_valid),                   //                .valid
		.rdata_fifo_src_data     (hps_f2h_sdram0_data_agent_rdata_fifo_src_data),                    //                .data
		.m0_response             (2'b00),                                                            //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                              //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (365),
		.FIFO_DEPTH          (15),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hps_f2h_sdram0_data_agent_rsp_fifo (
		.clk               (pll_outclk0_clk),                                                  //       clk.clk
		.reset             (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (hps_f2h_sdram0_data_agent_rf_source_data),                         //        in.data
		.in_valid          (hps_f2h_sdram0_data_agent_rf_source_valid),                        //          .valid
		.in_ready          (hps_f2h_sdram0_data_agent_rf_source_ready),                        //          .ready
		.in_startofpacket  (hps_f2h_sdram0_data_agent_rf_source_startofpacket),                //          .startofpacket
		.in_endofpacket    (hps_f2h_sdram0_data_agent_rf_source_endofpacket),                  //          .endofpacket
		.out_data          (hps_f2h_sdram0_data_agent_rsp_fifo_out_data),                      //       out.data
		.out_valid         (hps_f2h_sdram0_data_agent_rsp_fifo_out_valid),                     //          .valid
		.out_ready         (hps_f2h_sdram0_data_agent_rsp_fifo_out_ready),                     //          .ready
		.out_startofpacket (hps_f2h_sdram0_data_agent_rsp_fifo_out_startofpacket),             //          .startofpacket
		.out_endofpacket   (hps_f2h_sdram0_data_agent_rsp_fifo_out_endofpacket),               //          .endofpacket
		.csr_address       (2'b00),                                                            // (terminated)
		.csr_read          (1'b0),                                                             // (terminated)
		.csr_write         (1'b0),                                                             // (terminated)
		.csr_readdata      (),                                                                 // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                             // (terminated)
		.almost_full_data  (),                                                                 // (terminated)
		.almost_empty_data (),                                                                 // (terminated)
		.in_empty          (1'b0),                                                             // (terminated)
		.out_empty         (),                                                                 // (terminated)
		.in_error          (1'b0),                                                             // (terminated)
		.out_error         (),                                                                 // (terminated)
		.in_channel        (1'b0),                                                             // (terminated)
		.out_channel       ()                                                                  // (terminated)
	);

	system_acl_iface_mm_interconnect_2_router router (
		.sink_ready         (address_span_extender_kernel_expanded_master_agent_cp_ready),         //      sink.ready
		.sink_valid         (address_span_extender_kernel_expanded_master_agent_cp_valid),         //          .valid
		.sink_data          (address_span_extender_kernel_expanded_master_agent_cp_data),          //          .data
		.sink_startofpacket (address_span_extender_kernel_expanded_master_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (address_span_extender_kernel_expanded_master_agent_cp_endofpacket),   //          .endofpacket
		.clk                (pll_outclk0_clk),                                                     //       clk.clk
		.reset              (address_span_extender_kernel_reset_reset_bridge_in_reset_reset),      // clk_reset.reset
		.src_ready          (router_src_ready),                                                    //       src.ready
		.src_valid          (router_src_valid),                                                    //          .valid
		.src_data           (router_src_data),                                                     //          .data
		.src_channel        (router_src_channel),                                                  //          .channel
		.src_startofpacket  (router_src_startofpacket),                                            //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                               //          .endofpacket
	);

	system_acl_iface_mm_interconnect_2_router_001 router_001 (
		.sink_ready         (hps_f2h_sdram0_data_agent_rp_ready),                               //      sink.ready
		.sink_valid         (hps_f2h_sdram0_data_agent_rp_valid),                               //          .valid
		.sink_data          (hps_f2h_sdram0_data_agent_rp_data),                                //          .data
		.sink_startofpacket (hps_f2h_sdram0_data_agent_rp_startofpacket),                       //          .startofpacket
		.sink_endofpacket   (hps_f2h_sdram0_data_agent_rp_endofpacket),                         //          .endofpacket
		.clk                (pll_outclk0_clk),                                                  //       clk.clk
		.reset              (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                                             //       src.ready
		.src_valid          (router_001_src_valid),                                             //          .valid
		.src_data           (router_001_src_data),                                              //          .data
		.src_channel        (router_001_src_channel),                                           //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                                     //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                        //          .endofpacket
	);

	system_acl_iface_mm_interconnect_2_cmd_demux cmd_demux (
		.clk                (pll_outclk0_clk),                                                //       clk.clk
		.reset              (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                                               //      sink.ready
		.sink_channel       (router_src_channel),                                             //          .channel
		.sink_data          (router_src_data),                                                //          .data
		.sink_startofpacket (router_src_startofpacket),                                       //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                                         //          .endofpacket
		.sink_valid         (router_src_valid),                                               //          .valid
		.src0_ready         (cmd_demux_src0_ready),                                           //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                           //          .valid
		.src0_data          (cmd_demux_src0_data),                                            //          .data
		.src0_channel       (cmd_demux_src0_channel),                                         //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                   //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket)                                      //          .endofpacket
	);

	system_acl_iface_mm_interconnect_2_cmd_mux cmd_mux (
		.clk                 (pll_outclk0_clk),                                                  //       clk.clk
		.reset               (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                                //       src.ready
		.src_valid           (cmd_mux_src_valid),                                                //          .valid
		.src_data            (cmd_mux_src_data),                                                 //          .data
		.src_channel         (cmd_mux_src_channel),                                              //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                        //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                          //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                                             //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                                             //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                                           //          .channel
		.sink0_data          (cmd_demux_src0_data),                                              //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                                     //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket)                                        //          .endofpacket
	);

	system_acl_iface_mm_interconnect_2_cmd_demux rsp_demux (
		.clk                (pll_outclk0_clk),                                                  //       clk.clk
		.reset              (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                                             //      sink.ready
		.sink_channel       (router_001_src_channel),                                           //          .channel
		.sink_data          (router_001_src_data),                                              //          .data
		.sink_startofpacket (router_001_src_startofpacket),                                     //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                                       //          .endofpacket
		.sink_valid         (router_001_src_valid),                                             //          .valid
		.src0_ready         (rsp_demux_src0_ready),                                             //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                             //          .valid
		.src0_data          (rsp_demux_src0_data),                                              //          .data
		.src0_channel       (rsp_demux_src0_channel),                                           //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                     //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                                        //          .endofpacket
	);

	system_acl_iface_mm_interconnect_2_rsp_mux rsp_mux (
		.clk                 (pll_outclk0_clk),                                                //       clk.clk
		.reset               (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                              //       src.ready
		.src_valid           (rsp_mux_src_valid),                                              //          .valid
		.src_data            (rsp_mux_src_data),                                               //          .data
		.src_channel         (rsp_mux_src_channel),                                            //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                      //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                        //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                                           //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                                           //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                                         //          .channel
		.sink0_data          (rsp_demux_src0_data),                                            //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                                   //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket)                                      //          .endofpacket
	);

	system_acl_iface_mm_interconnect_2_avalon_st_adapter #(
		.inBitsPerSymbol (258),
		.inUsePackets    (0),
		.inDataWidth     (258),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (258),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (pll_outclk0_clk),                                                  // in_clk_0.clk
		.in_rst_0_reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (hps_f2h_sdram0_data_agent_rdata_fifo_src_data),                    //     in_0.data
		.in_0_valid     (hps_f2h_sdram0_data_agent_rdata_fifo_src_valid),                   //         .valid
		.in_0_ready     (hps_f2h_sdram0_data_agent_rdata_fifo_src_ready),                   //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                                     //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                                    //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                                    //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                                     //         .error
	);

endmodule
