// (C) 1992-2016 Altera Corporation. All rights reserved.                         
// Your use of Altera Corporation's design tools, logic functions and other       
// software and tools, and its AMPP partner logic functions, and any output       
// files any of the foregoing (including device programming or simulation         
// files), and any associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License Subscription         
// Agreement, Altera MegaCore Function License Agreement, or other applicable     
// license agreement, including, without limitation, that your use is for the     
// sole purpose of programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the applicable         
// agreement for further details.                                                 
    

//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////

// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module float_mult_basic_block_0
	(
		input 		clock,
		input 		resetn,
		input 		valid_in,
		output 		stall_out,
		input [31:0] 		input_global_id_0,
		output 		valid_out,
		input 		stall_in,
		output [31:0] 		lvb_input_global_id_0,
		input [31:0] 		workgroup_size,
		input 		start
	);


// Values used for debugging.  These are swept away by synthesis.
wire _entry;
wire _exit;
 reg [31:0] _num_entry_NO_SHIFT_REG;
 reg [31:0] _num_exit_NO_SHIFT_REG;
wire [31:0] _num_live;

assign _entry = ((&valid_in) & ~((|stall_out)));
assign _exit = ((&valid_out) & ~((|stall_in)));
assign _num_live = (_num_entry_NO_SHIFT_REG - _num_exit_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		_num_entry_NO_SHIFT_REG <= 32'h0;
		_num_exit_NO_SHIFT_REG <= 32'h0;
	end
	else
	begin
		if (_entry)
		begin
			_num_entry_NO_SHIFT_REG <= (_num_entry_NO_SHIFT_REG + 2'h1);
		end
		if (_exit)
		begin
			_num_exit_NO_SHIFT_REG <= (_num_exit_NO_SHIFT_REG + 2'h1);
		end
	end
end



// This section defines the behaviour of the MERGE node
wire merge_node_stall_in;
 reg merge_node_valid_out_NO_SHIFT_REG;
wire merge_stalled_by_successors;
 reg merge_block_selector_NO_SHIFT_REG;
 reg merge_node_valid_in_staging_reg_NO_SHIFT_REG;
 reg [31:0] input_global_id_0_staging_reg_NO_SHIFT_REG;
 reg [31:0] local_lvm_input_global_id_0_NO_SHIFT_REG;
 reg is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
 reg invariant_valid_NO_SHIFT_REG;

assign merge_stalled_by_successors = (|(merge_node_stall_in & merge_node_valid_out_NO_SHIFT_REG));
assign stall_out = merge_node_valid_in_staging_reg_NO_SHIFT_REG;

always @(*)
begin
	if ((merge_node_valid_in_staging_reg_NO_SHIFT_REG | valid_in))
	begin
		merge_block_selector_NO_SHIFT_REG = 1'b0;
		is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b1;
	end
	else
	begin
		merge_block_selector_NO_SHIFT_REG = 1'b0;
		is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b0;
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		input_global_id_0_staging_reg_NO_SHIFT_REG <= 'x;
		merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (((merge_block_selector_NO_SHIFT_REG != 1'b0) | merge_stalled_by_successors))
		begin
			if (~(merge_node_valid_in_staging_reg_NO_SHIFT_REG))
			begin
				input_global_id_0_staging_reg_NO_SHIFT_REG <= input_global_id_0;
				merge_node_valid_in_staging_reg_NO_SHIFT_REG <= valid_in;
			end
		end
		else
		begin
			merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
		end
	end
end

always @(posedge clock)
begin
	if (~(merge_stalled_by_successors))
	begin
		case (merge_block_selector_NO_SHIFT_REG)
			1'b0:
			begin
				if (merge_node_valid_in_staging_reg_NO_SHIFT_REG)
				begin
					local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0_staging_reg_NO_SHIFT_REG;
				end
				else
				begin
					local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0;
				end
			end

			default:
			begin
			end

		endcase
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		merge_node_valid_out_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (~(merge_stalled_by_successors))
		begin
			merge_node_valid_out_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
		end
		else
		begin
			if (~(merge_node_stall_in))
			begin
				merge_node_valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		invariant_valid_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		invariant_valid_NO_SHIFT_REG <= (~(start) & (invariant_valid_NO_SHIFT_REG | is_merge_data_to_local_regs_valid_NO_SHIFT_REG));
	end
end


// This section describes the behaviour of the BRANCH node.
wire branch_var__inputs_ready;
 reg branch_node_valid_out_NO_SHIFT_REG;
wire branch_var__output_regs_ready;
wire combined_branch_stall_in_signal;
 reg [31:0] lvb_input_global_id_0_reg_NO_SHIFT_REG;

assign branch_var__inputs_ready = merge_node_valid_out_NO_SHIFT_REG;
assign branch_var__output_regs_ready = (~(stall_in) | ~(branch_node_valid_out_NO_SHIFT_REG));
assign merge_node_stall_in = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign lvb_input_global_id_0 = lvb_input_global_id_0_reg_NO_SHIFT_REG;
assign combined_branch_stall_in_signal = stall_in;
assign valid_out = branch_node_valid_out_NO_SHIFT_REG;

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		branch_node_valid_out_NO_SHIFT_REG <= 1'b0;
		lvb_input_global_id_0_reg_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (branch_var__output_regs_ready)
		begin
			branch_node_valid_out_NO_SHIFT_REG <= branch_var__inputs_ready;
			lvb_input_global_id_0_reg_NO_SHIFT_REG <= local_lvm_input_global_id_0_NO_SHIFT_REG;
		end
		else
		begin
			if (~(combined_branch_stall_in_signal))
			begin
				branch_node_valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end


endmodule

//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////

// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module float_mult_basic_block_1
	(
		input 		clock,
		input 		resetn,
		input [63:0] 		input_x,
		input [63:0] 		input_y,
		input [63:0] 		input_z,
		input 		valid_in_0,
		output 		stall_out_0,
		input [31:0] 		input_t_01_0,
		input [31:0] 		input_global_id_0_0,
		input 		valid_in_1,
		output 		stall_out_1,
		input [31:0] 		input_t_01_1,
		input [31:0] 		input_global_id_0_1,
		output 		valid_out_0,
		input 		stall_in_0,
		output [31:0] 		lvb_bb1_inc_0,
		output [31:0] 		lvb_input_global_id_0_0,
		output 		valid_out_1,
		input 		stall_in_1,
		output [31:0] 		lvb_bb1_inc_1,
		output [31:0] 		lvb_input_global_id_0_1,
		input [31:0] 		workgroup_size,
		input 		start,
		output 		avm_local_bb1_ld__enable,
		input [255:0] 		avm_local_bb1_ld__readdata,
		input 		avm_local_bb1_ld__readdatavalid,
		input 		avm_local_bb1_ld__waitrequest,
		output [30:0] 		avm_local_bb1_ld__address,
		output 		avm_local_bb1_ld__read,
		output 		avm_local_bb1_ld__write,
		input 		avm_local_bb1_ld__writeack,
		output [255:0] 		avm_local_bb1_ld__writedata,
		output [31:0] 		avm_local_bb1_ld__byteenable,
		output [4:0] 		avm_local_bb1_ld__burstcount,
		output 		local_bb1_ld__active,
		input 		clock2x,
		output 		avm_local_bb1_ld__u0_enable,
		input [255:0] 		avm_local_bb1_ld__u0_readdata,
		input 		avm_local_bb1_ld__u0_readdatavalid,
		input 		avm_local_bb1_ld__u0_waitrequest,
		output [30:0] 		avm_local_bb1_ld__u0_address,
		output 		avm_local_bb1_ld__u0_read,
		output 		avm_local_bb1_ld__u0_write,
		input 		avm_local_bb1_ld__u0_writeack,
		output [255:0] 		avm_local_bb1_ld__u0_writedata,
		output [31:0] 		avm_local_bb1_ld__u0_byteenable,
		output [4:0] 		avm_local_bb1_ld__u0_burstcount,
		output 		local_bb1_ld__u0_active,
		output 		avm_local_bb1_st__enable,
		input [255:0] 		avm_local_bb1_st__readdata,
		input 		avm_local_bb1_st__readdatavalid,
		input 		avm_local_bb1_st__waitrequest,
		output [30:0] 		avm_local_bb1_st__address,
		output 		avm_local_bb1_st__read,
		output 		avm_local_bb1_st__write,
		input 		avm_local_bb1_st__writeack,
		output [255:0] 		avm_local_bb1_st__writedata,
		output [31:0] 		avm_local_bb1_st__byteenable,
		output [4:0] 		avm_local_bb1_st__burstcount,
		output 		local_bb1_st__active
	);


// Values used for debugging.  These are swept away by synthesis.
wire _entry;
wire _exit;
 reg [31:0] _num_entry_NO_SHIFT_REG;
 reg [31:0] _num_exit_NO_SHIFT_REG;
wire [31:0] _num_live;

assign _entry = ((valid_in_0 & valid_in_1) & ~((stall_out_0 | stall_out_1)));
assign _exit = ((valid_out_0 & valid_out_1) & ~((stall_in_0 | stall_in_1)));
assign _num_live = (_num_entry_NO_SHIFT_REG - _num_exit_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		_num_entry_NO_SHIFT_REG <= 32'h0;
		_num_exit_NO_SHIFT_REG <= 32'h0;
	end
	else
	begin
		if (_entry)
		begin
			_num_entry_NO_SHIFT_REG <= (_num_entry_NO_SHIFT_REG + 2'h1);
		end
		if (_exit)
		begin
			_num_exit_NO_SHIFT_REG <= (_num_exit_NO_SHIFT_REG + 2'h1);
		end
	end
end



// This section defines the behaviour of the MERGE node
wire merge_node_stall_in_0;
 reg merge_node_valid_out_0_NO_SHIFT_REG;
wire merge_node_stall_in_1;
 reg merge_node_valid_out_1_NO_SHIFT_REG;
wire merge_node_stall_in_2;
 reg merge_node_valid_out_2_NO_SHIFT_REG;
wire merge_stalled_by_successors;
 reg merge_block_selector_NO_SHIFT_REG;
 reg merge_node_valid_in_0_staging_reg_NO_SHIFT_REG;
 reg [31:0] input_t_01_0_staging_reg_NO_SHIFT_REG;
 reg [31:0] input_global_id_0_0_staging_reg_NO_SHIFT_REG;
 reg [31:0] local_lvm_t_01_NO_SHIFT_REG;
 reg [31:0] local_lvm_input_global_id_0_NO_SHIFT_REG;
 reg merge_node_valid_in_1_staging_reg_NO_SHIFT_REG;
 reg [31:0] input_t_01_1_staging_reg_NO_SHIFT_REG;
 reg [31:0] input_global_id_0_1_staging_reg_NO_SHIFT_REG;
 reg is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
 reg invariant_valid_NO_SHIFT_REG;

assign merge_stalled_by_successors = ((merge_node_stall_in_0 & merge_node_valid_out_0_NO_SHIFT_REG) | (merge_node_stall_in_1 & merge_node_valid_out_1_NO_SHIFT_REG) | (merge_node_stall_in_2 & merge_node_valid_out_2_NO_SHIFT_REG));
assign stall_out_0 = merge_node_valid_in_0_staging_reg_NO_SHIFT_REG;
assign stall_out_1 = merge_node_valid_in_1_staging_reg_NO_SHIFT_REG;

always @(*)
begin
	if ((merge_node_valid_in_0_staging_reg_NO_SHIFT_REG | valid_in_0))
	begin
		merge_block_selector_NO_SHIFT_REG = 1'b0;
		is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b1;
	end
	else
	begin
		if ((merge_node_valid_in_1_staging_reg_NO_SHIFT_REG | valid_in_1))
		begin
			merge_block_selector_NO_SHIFT_REG = 1'b1;
			is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b1;
		end
		else
		begin
			merge_block_selector_NO_SHIFT_REG = 1'b0;
			is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b0;
		end
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		input_t_01_0_staging_reg_NO_SHIFT_REG <= 'x;
		input_global_id_0_0_staging_reg_NO_SHIFT_REG <= 'x;
		merge_node_valid_in_0_staging_reg_NO_SHIFT_REG <= 1'b0;
		input_t_01_1_staging_reg_NO_SHIFT_REG <= 'x;
		input_global_id_0_1_staging_reg_NO_SHIFT_REG <= 'x;
		merge_node_valid_in_1_staging_reg_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (((merge_block_selector_NO_SHIFT_REG != 1'b0) | merge_stalled_by_successors))
		begin
			if (~(merge_node_valid_in_0_staging_reg_NO_SHIFT_REG))
			begin
				input_t_01_0_staging_reg_NO_SHIFT_REG <= input_t_01_0;
				input_global_id_0_0_staging_reg_NO_SHIFT_REG <= input_global_id_0_0;
				merge_node_valid_in_0_staging_reg_NO_SHIFT_REG <= valid_in_0;
			end
		end
		else
		begin
			merge_node_valid_in_0_staging_reg_NO_SHIFT_REG <= 1'b0;
		end
		if (((merge_block_selector_NO_SHIFT_REG != 1'b1) | merge_stalled_by_successors))
		begin
			if (~(merge_node_valid_in_1_staging_reg_NO_SHIFT_REG))
			begin
				input_t_01_1_staging_reg_NO_SHIFT_REG <= input_t_01_1;
				input_global_id_0_1_staging_reg_NO_SHIFT_REG <= input_global_id_0_1;
				merge_node_valid_in_1_staging_reg_NO_SHIFT_REG <= valid_in_1;
			end
		end
		else
		begin
			merge_node_valid_in_1_staging_reg_NO_SHIFT_REG <= 1'b0;
		end
	end
end

always @(posedge clock)
begin
	if (~(merge_stalled_by_successors))
	begin
		case (merge_block_selector_NO_SHIFT_REG)
			1'b0:
			begin
				if (merge_node_valid_in_0_staging_reg_NO_SHIFT_REG)
				begin
					local_lvm_t_01_NO_SHIFT_REG <= input_t_01_0_staging_reg_NO_SHIFT_REG;
					local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0_0_staging_reg_NO_SHIFT_REG;
				end
				else
				begin
					local_lvm_t_01_NO_SHIFT_REG <= input_t_01_0;
					local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0_0;
				end
			end

			1'b1:
			begin
				if (merge_node_valid_in_1_staging_reg_NO_SHIFT_REG)
				begin
					local_lvm_t_01_NO_SHIFT_REG <= input_t_01_1_staging_reg_NO_SHIFT_REG;
					local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0_1_staging_reg_NO_SHIFT_REG;
				end
				else
				begin
					local_lvm_t_01_NO_SHIFT_REG <= input_t_01_1;
					local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0_1;
				end
			end

			default:
			begin
			end

		endcase
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		merge_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
		merge_node_valid_out_1_NO_SHIFT_REG <= 1'b0;
		merge_node_valid_out_2_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (~(merge_stalled_by_successors))
		begin
			merge_node_valid_out_0_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
			merge_node_valid_out_1_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
			merge_node_valid_out_2_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
		end
		else
		begin
			if (~(merge_node_stall_in_0))
			begin
				merge_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
			end
			if (~(merge_node_stall_in_1))
			begin
				merge_node_valid_out_1_NO_SHIFT_REG <= 1'b0;
			end
			if (~(merge_node_stall_in_2))
			begin
				merge_node_valid_out_2_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		invariant_valid_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		invariant_valid_NO_SHIFT_REG <= (~(start) & (invariant_valid_NO_SHIFT_REG | is_merge_data_to_local_regs_valid_NO_SHIFT_REG));
	end
end


// This section implements an unregistered operation.
// 
wire local_bb1_idxprom_RM_stall_local;
wire [63:0] local_bb1_idxprom_RM;

assign local_bb1_idxprom_RM[32] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[33] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[34] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[35] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[36] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[37] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[38] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[39] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[40] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[41] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[42] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[43] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[44] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[45] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[46] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[47] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[48] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[49] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[50] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[51] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[52] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[53] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[54] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[55] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[56] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[57] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[58] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[59] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[60] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[61] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[62] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[63] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[31:0] = local_lvm_input_global_id_0_NO_SHIFT_REG;

// Register node:
//  * latency = 322
//  * capacity = 322
 logic rnode_1to323_t_01_0_valid_out_NO_SHIFT_REG;
 logic rnode_1to323_t_01_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_1to323_t_01_0_NO_SHIFT_REG;
 logic rnode_1to323_t_01_0_reg_323_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_1to323_t_01_0_reg_323_NO_SHIFT_REG;
 logic rnode_1to323_t_01_0_valid_out_reg_323_NO_SHIFT_REG;
 logic rnode_1to323_t_01_0_stall_in_reg_323_NO_SHIFT_REG;
 logic rnode_1to323_t_01_0_stall_out_reg_323_NO_SHIFT_REG;

acl_data_fifo rnode_1to323_t_01_0_reg_323_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_1to323_t_01_0_reg_323_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_1to323_t_01_0_stall_in_reg_323_NO_SHIFT_REG),
	.valid_out(rnode_1to323_t_01_0_valid_out_reg_323_NO_SHIFT_REG),
	.stall_out(rnode_1to323_t_01_0_stall_out_reg_323_NO_SHIFT_REG),
	.data_in((local_lvm_t_01_NO_SHIFT_REG & 32'h3FF)),
	.data_out(rnode_1to323_t_01_0_reg_323_NO_SHIFT_REG)
);

defparam rnode_1to323_t_01_0_reg_323_fifo.DEPTH = 323;
defparam rnode_1to323_t_01_0_reg_323_fifo.DATA_WIDTH = 32;
defparam rnode_1to323_t_01_0_reg_323_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_1to323_t_01_0_reg_323_fifo.IMPL = "ram";

assign rnode_1to323_t_01_0_reg_323_inputs_ready_NO_SHIFT_REG = merge_node_valid_out_1_NO_SHIFT_REG;
assign merge_node_stall_in_1 = rnode_1to323_t_01_0_stall_out_reg_323_NO_SHIFT_REG;
assign rnode_1to323_t_01_0_NO_SHIFT_REG = rnode_1to323_t_01_0_reg_323_NO_SHIFT_REG;
assign rnode_1to323_t_01_0_stall_in_reg_323_NO_SHIFT_REG = rnode_1to323_t_01_0_stall_in_NO_SHIFT_REG;
assign rnode_1to323_t_01_0_valid_out_NO_SHIFT_REG = rnode_1to323_t_01_0_valid_out_reg_323_NO_SHIFT_REG;

// Register node:
//  * latency = 323
//  * capacity = 323
 logic rnode_1to324_input_global_id_0_0_valid_out_NO_SHIFT_REG;
 logic rnode_1to324_input_global_id_0_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_1to324_input_global_id_0_0_NO_SHIFT_REG;
 logic rnode_1to324_input_global_id_0_0_reg_324_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_1to324_input_global_id_0_0_reg_324_NO_SHIFT_REG;
 logic rnode_1to324_input_global_id_0_0_valid_out_reg_324_NO_SHIFT_REG;
 logic rnode_1to324_input_global_id_0_0_stall_in_reg_324_NO_SHIFT_REG;
 logic rnode_1to324_input_global_id_0_0_stall_out_reg_324_NO_SHIFT_REG;

acl_data_fifo rnode_1to324_input_global_id_0_0_reg_324_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_1to324_input_global_id_0_0_reg_324_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_1to324_input_global_id_0_0_stall_in_reg_324_NO_SHIFT_REG),
	.valid_out(rnode_1to324_input_global_id_0_0_valid_out_reg_324_NO_SHIFT_REG),
	.stall_out(rnode_1to324_input_global_id_0_0_stall_out_reg_324_NO_SHIFT_REG),
	.data_in(local_lvm_input_global_id_0_NO_SHIFT_REG),
	.data_out(rnode_1to324_input_global_id_0_0_reg_324_NO_SHIFT_REG)
);

defparam rnode_1to324_input_global_id_0_0_reg_324_fifo.DEPTH = 324;
defparam rnode_1to324_input_global_id_0_0_reg_324_fifo.DATA_WIDTH = 32;
defparam rnode_1to324_input_global_id_0_0_reg_324_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_1to324_input_global_id_0_0_reg_324_fifo.IMPL = "ram";

assign rnode_1to324_input_global_id_0_0_reg_324_inputs_ready_NO_SHIFT_REG = merge_node_valid_out_2_NO_SHIFT_REG;
assign merge_node_stall_in_2 = rnode_1to324_input_global_id_0_0_stall_out_reg_324_NO_SHIFT_REG;
assign rnode_1to324_input_global_id_0_0_NO_SHIFT_REG = rnode_1to324_input_global_id_0_0_reg_324_NO_SHIFT_REG;
assign rnode_1to324_input_global_id_0_0_stall_in_reg_324_NO_SHIFT_REG = rnode_1to324_input_global_id_0_0_stall_in_NO_SHIFT_REG;
assign rnode_1to324_input_global_id_0_0_valid_out_NO_SHIFT_REG = rnode_1to324_input_global_id_0_0_valid_out_reg_324_NO_SHIFT_REG;

// This section implements an unregistered operation.
// 
wire local_bb1_arrayidx_RM_stall_local;
wire [63:0] local_bb1_arrayidx_RM;

assign local_bb1_arrayidx_RM = ((input_x & 64'hFFFFFFFFFFFFFC00) + (local_bb1_idxprom_RM << 6'h2));

// This section implements an unregistered operation.
// 
wire local_bb1_arrayidx3_RM_stall_local;
wire [63:0] local_bb1_arrayidx3_RM;

assign local_bb1_arrayidx3_RM = ((input_y & 64'hFFFFFFFFFFFFFC00) + (local_bb1_idxprom_RM << 6'h2));

// This section implements an unregistered operation.
// 
wire local_bb1_arrayidx_RM_valid_out;
wire local_bb1_arrayidx_RM_stall_in;
wire local_bb1_arrayidx3_RM_valid_out;
wire local_bb1_arrayidx3_RM_stall_in;
wire local_bb1_arrayidx5_RM_valid_out;
wire local_bb1_arrayidx5_RM_stall_in;
wire local_bb1_arrayidx5_RM_inputs_ready;
wire local_bb1_arrayidx5_RM_stall_local;
wire [63:0] local_bb1_arrayidx5_RM;
 reg local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG;
 reg local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG;
 reg local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG;

assign local_bb1_arrayidx5_RM_inputs_ready = merge_node_valid_out_0_NO_SHIFT_REG;
assign local_bb1_arrayidx5_RM = ((input_z & 64'hFFFFFFFFFFFFFC00) + (local_bb1_idxprom_RM << 6'h2));
assign local_bb1_arrayidx5_RM_stall_local = ((local_bb1_arrayidx_RM_stall_in & ~(local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG)) | (local_bb1_arrayidx3_RM_stall_in & ~(local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG)) | (local_bb1_arrayidx5_RM_stall_in & ~(local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG)));
assign local_bb1_arrayidx_RM_valid_out = (local_bb1_arrayidx5_RM_inputs_ready & ~(local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG));
assign local_bb1_arrayidx3_RM_valid_out = (local_bb1_arrayidx5_RM_inputs_ready & ~(local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG));
assign local_bb1_arrayidx5_RM_valid_out = (local_bb1_arrayidx5_RM_inputs_ready & ~(local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG));
assign merge_node_stall_in_0 = (|local_bb1_arrayidx5_RM_stall_local);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG <= 1'b0;
		local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG <= 1'b0;
		local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG <= (local_bb1_arrayidx5_RM_inputs_ready & (local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG | ~(local_bb1_arrayidx_RM_stall_in)) & local_bb1_arrayidx5_RM_stall_local);
		local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG <= (local_bb1_arrayidx5_RM_inputs_ready & (local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG | ~(local_bb1_arrayidx3_RM_stall_in)) & local_bb1_arrayidx5_RM_stall_local);
		local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG <= (local_bb1_arrayidx5_RM_inputs_ready & (local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG | ~(local_bb1_arrayidx5_RM_stall_in)) & local_bb1_arrayidx5_RM_stall_local);
	end
end


// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_323to324_t_01_0_valid_out_NO_SHIFT_REG;
 logic rnode_323to324_t_01_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_323to324_t_01_0_NO_SHIFT_REG;
 logic rnode_323to324_t_01_0_reg_324_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_323to324_t_01_0_reg_324_NO_SHIFT_REG;
 logic rnode_323to324_t_01_0_valid_out_reg_324_NO_SHIFT_REG;
 logic rnode_323to324_t_01_0_stall_in_reg_324_NO_SHIFT_REG;
 logic rnode_323to324_t_01_0_stall_out_reg_324_NO_SHIFT_REG;

acl_data_fifo rnode_323to324_t_01_0_reg_324_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_323to324_t_01_0_reg_324_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_323to324_t_01_0_stall_in_reg_324_NO_SHIFT_REG),
	.valid_out(rnode_323to324_t_01_0_valid_out_reg_324_NO_SHIFT_REG),
	.stall_out(rnode_323to324_t_01_0_stall_out_reg_324_NO_SHIFT_REG),
	.data_in((rnode_1to323_t_01_0_NO_SHIFT_REG & 32'h3FF)),
	.data_out(rnode_323to324_t_01_0_reg_324_NO_SHIFT_REG)
);

defparam rnode_323to324_t_01_0_reg_324_fifo.DEPTH = 1;
defparam rnode_323to324_t_01_0_reg_324_fifo.DATA_WIDTH = 32;
defparam rnode_323to324_t_01_0_reg_324_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_323to324_t_01_0_reg_324_fifo.IMPL = "ll_reg";

assign rnode_323to324_t_01_0_reg_324_inputs_ready_NO_SHIFT_REG = rnode_1to323_t_01_0_valid_out_NO_SHIFT_REG;
assign rnode_1to323_t_01_0_stall_in_NO_SHIFT_REG = rnode_323to324_t_01_0_stall_out_reg_324_NO_SHIFT_REG;
assign rnode_323to324_t_01_0_NO_SHIFT_REG = rnode_323to324_t_01_0_reg_324_NO_SHIFT_REG;
assign rnode_323to324_t_01_0_stall_in_reg_324_NO_SHIFT_REG = rnode_323to324_t_01_0_stall_in_NO_SHIFT_REG;
assign rnode_323to324_t_01_0_valid_out_NO_SHIFT_REG = rnode_323to324_t_01_0_valid_out_reg_324_NO_SHIFT_REG;

// This section implements a staging register.
// 
wire rstag_1to1_bb1_arrayidx_RM_valid_out;
wire rstag_1to1_bb1_arrayidx_RM_stall_in;
wire rstag_1to1_bb1_arrayidx_RM_inputs_ready;
wire rstag_1to1_bb1_arrayidx_RM_stall_local;
 reg rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG;
wire rstag_1to1_bb1_arrayidx_RM_combined_valid;
 reg [63:0] rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG;
wire [63:0] rstag_1to1_bb1_arrayidx_RM;

assign rstag_1to1_bb1_arrayidx_RM_inputs_ready = local_bb1_arrayidx_RM_valid_out;
assign rstag_1to1_bb1_arrayidx_RM = (rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ? rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG : (local_bb1_arrayidx_RM & 64'hFFFFFFFFFFFFFFFC));
assign rstag_1to1_bb1_arrayidx_RM_combined_valid = (rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG | rstag_1to1_bb1_arrayidx_RM_inputs_ready);
assign rstag_1to1_bb1_arrayidx_RM_valid_out = rstag_1to1_bb1_arrayidx_RM_combined_valid;
assign rstag_1to1_bb1_arrayidx_RM_stall_local = rstag_1to1_bb1_arrayidx_RM_stall_in;
assign local_bb1_arrayidx_RM_stall_in = (|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG <= 1'b0;
		rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (rstag_1to1_bb1_arrayidx_RM_stall_local)
		begin
			if (~(rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG))
			begin
				rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG <= rstag_1to1_bb1_arrayidx_RM_inputs_ready;
			end
		end
		else
		begin
			rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG <= 1'b0;
		end
		if (~(rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG))
		begin
			rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG <= (local_bb1_arrayidx_RM & 64'hFFFFFFFFFFFFFFFC);
		end
	end
end


// This section implements a staging register.
// 
wire rstag_1to1_bb1_arrayidx3_RM_valid_out;
wire rstag_1to1_bb1_arrayidx3_RM_stall_in;
wire rstag_1to1_bb1_arrayidx3_RM_inputs_ready;
wire rstag_1to1_bb1_arrayidx3_RM_stall_local;
 reg rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG;
wire rstag_1to1_bb1_arrayidx3_RM_combined_valid;
 reg [63:0] rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG;
wire [63:0] rstag_1to1_bb1_arrayidx3_RM;

assign rstag_1to1_bb1_arrayidx3_RM_inputs_ready = local_bb1_arrayidx3_RM_valid_out;
assign rstag_1to1_bb1_arrayidx3_RM = (rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ? rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG : (local_bb1_arrayidx3_RM & 64'hFFFFFFFFFFFFFFFC));
assign rstag_1to1_bb1_arrayidx3_RM_combined_valid = (rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG | rstag_1to1_bb1_arrayidx3_RM_inputs_ready);
assign rstag_1to1_bb1_arrayidx3_RM_valid_out = rstag_1to1_bb1_arrayidx3_RM_combined_valid;
assign rstag_1to1_bb1_arrayidx3_RM_stall_local = rstag_1to1_bb1_arrayidx3_RM_stall_in;
assign local_bb1_arrayidx3_RM_stall_in = (|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG <= 1'b0;
		rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (rstag_1to1_bb1_arrayidx3_RM_stall_local)
		begin
			if (~(rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG))
			begin
				rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG <= rstag_1to1_bb1_arrayidx3_RM_inputs_ready;
			end
		end
		else
		begin
			rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG <= 1'b0;
		end
		if (~(rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG))
		begin
			rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG <= (local_bb1_arrayidx3_RM & 64'hFFFFFFFFFFFFFFFC);
		end
	end
end


// Register node:
//  * latency = 163
//  * capacity = 163
 logic rnode_1to164_bb1_arrayidx5_RM_0_valid_out_NO_SHIFT_REG;
 logic rnode_1to164_bb1_arrayidx5_RM_0_stall_in_NO_SHIFT_REG;
 logic [63:0] rnode_1to164_bb1_arrayidx5_RM_0_NO_SHIFT_REG;
 logic rnode_1to164_bb1_arrayidx5_RM_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic [63:0] rnode_1to164_bb1_arrayidx5_RM_0_reg_164_NO_SHIFT_REG;
 logic rnode_1to164_bb1_arrayidx5_RM_0_valid_out_reg_164_NO_SHIFT_REG;
 logic rnode_1to164_bb1_arrayidx5_RM_0_stall_in_reg_164_NO_SHIFT_REG;
 logic rnode_1to164_bb1_arrayidx5_RM_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_1to164_bb1_arrayidx5_RM_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_1to164_bb1_arrayidx5_RM_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_1to164_bb1_arrayidx5_RM_0_stall_in_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_1to164_bb1_arrayidx5_RM_0_valid_out_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_1to164_bb1_arrayidx5_RM_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in((local_bb1_arrayidx5_RM & 64'hFFFFFFFFFFFFFFFC)),
	.data_out(rnode_1to164_bb1_arrayidx5_RM_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_1to164_bb1_arrayidx5_RM_0_reg_164_fifo.DEPTH = 164;
defparam rnode_1to164_bb1_arrayidx5_RM_0_reg_164_fifo.DATA_WIDTH = 64;
defparam rnode_1to164_bb1_arrayidx5_RM_0_reg_164_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_1to164_bb1_arrayidx5_RM_0_reg_164_fifo.IMPL = "ram";

assign rnode_1to164_bb1_arrayidx5_RM_0_reg_164_inputs_ready_NO_SHIFT_REG = local_bb1_arrayidx5_RM_valid_out;
assign local_bb1_arrayidx5_RM_stall_in = rnode_1to164_bb1_arrayidx5_RM_0_stall_out_reg_164_NO_SHIFT_REG;
assign rnode_1to164_bb1_arrayidx5_RM_0_NO_SHIFT_REG = rnode_1to164_bb1_arrayidx5_RM_0_reg_164_NO_SHIFT_REG;
assign rnode_1to164_bb1_arrayidx5_RM_0_stall_in_reg_164_NO_SHIFT_REG = rnode_1to164_bb1_arrayidx5_RM_0_stall_in_NO_SHIFT_REG;
assign rnode_1to164_bb1_arrayidx5_RM_0_valid_out_NO_SHIFT_REG = rnode_1to164_bb1_arrayidx5_RM_0_valid_out_reg_164_NO_SHIFT_REG;

// This section implements an unregistered operation.
// 
wire local_bb1_inc_valid_out;
wire local_bb1_inc_stall_in;
wire local_bb1_inc_inputs_ready;
wire local_bb1_inc_stall_local;
wire [31:0] local_bb1_inc;

assign local_bb1_inc_inputs_ready = rnode_323to324_t_01_0_valid_out_NO_SHIFT_REG;
assign local_bb1_inc = ((rnode_323to324_t_01_0_NO_SHIFT_REG & 32'h3FF) + 32'h1);
assign local_bb1_inc_valid_out = local_bb1_inc_inputs_ready;
assign local_bb1_inc_stall_local = local_bb1_inc_stall_in;
assign rnode_323to324_t_01_0_stall_in_NO_SHIFT_REG = (|local_bb1_inc_stall_local);

// This section implements a registered operation.
// 
wire local_bb1_ld__inputs_ready;
 reg local_bb1_ld__valid_out_NO_SHIFT_REG;
wire local_bb1_ld__stall_in;
wire local_bb1_ld__output_regs_ready;
wire local_bb1_ld__fu_stall_out;
wire local_bb1_ld__fu_valid_out;
wire [31:0] local_bb1_ld__lsu_dataout;
 reg [31:0] local_bb1_ld__NO_SHIFT_REG;
wire local_bb1_ld__causedstall;

lsu_top lsu_local_bb1_ld_ (
	.clock(clock),
	.clock2x(clock2x),
	.resetn(resetn),
	.flush(start),
	.stream_base_addr(),
	.stream_size(),
	.stream_reset(),
	.o_stall(local_bb1_ld__fu_stall_out),
	.i_valid(local_bb1_ld__inputs_ready),
	.i_address((rstag_1to1_bb1_arrayidx_RM & 64'hFFFFFFFFFFFFFFFC)),
	.i_writedata(),
	.i_cmpdata(),
	.i_predicate(1'b0),
	.i_bitwiseor(64'h0),
	.i_byteenable(),
	.i_stall(~(local_bb1_ld__output_regs_ready)),
	.o_valid(local_bb1_ld__fu_valid_out),
	.o_readdata(local_bb1_ld__lsu_dataout),
	.o_input_fifo_depth(),
	.o_writeack(),
	.i_atomic_op(3'h0),
	.o_active(local_bb1_ld__active),
	.avm_address(avm_local_bb1_ld__address),
	.avm_read(avm_local_bb1_ld__read),
	.avm_enable(avm_local_bb1_ld__enable),
	.avm_readdata(avm_local_bb1_ld__readdata),
	.avm_write(avm_local_bb1_ld__write),
	.avm_writeack(avm_local_bb1_ld__writeack),
	.avm_burstcount(avm_local_bb1_ld__burstcount),
	.avm_writedata(avm_local_bb1_ld__writedata),
	.avm_byteenable(avm_local_bb1_ld__byteenable),
	.avm_waitrequest(avm_local_bb1_ld__waitrequest),
	.avm_readdatavalid(avm_local_bb1_ld__readdatavalid),
	.profile_bw(),
	.profile_bw_incr(),
	.profile_total_ivalid(),
	.profile_total_req(),
	.profile_i_stall_count(),
	.profile_o_stall_count(),
	.profile_avm_readwrite_count(),
	.profile_avm_burstcount_total(),
	.profile_avm_burstcount_total_incr(),
	.profile_req_cache_hit_count(),
	.profile_extra_unaligned_reqs(),
	.profile_avm_stall()
);

defparam lsu_local_bb1_ld_.AWIDTH = 31;
defparam lsu_local_bb1_ld_.WIDTH_BYTES = 4;
defparam lsu_local_bb1_ld_.MWIDTH_BYTES = 32;
defparam lsu_local_bb1_ld_.WRITEDATAWIDTH_BYTES = 32;
defparam lsu_local_bb1_ld_.ALIGNMENT_BYTES = 4;
defparam lsu_local_bb1_ld_.READ = 1;
defparam lsu_local_bb1_ld_.ATOMIC = 0;
defparam lsu_local_bb1_ld_.WIDTH = 32;
defparam lsu_local_bb1_ld_.MWIDTH = 256;
defparam lsu_local_bb1_ld_.ATOMIC_WIDTH = 3;
defparam lsu_local_bb1_ld_.BURSTCOUNT_WIDTH = 5;
defparam lsu_local_bb1_ld_.KERNEL_SIDE_MEM_LATENCY = 160;
defparam lsu_local_bb1_ld_.MEMORY_SIDE_MEM_LATENCY = 89;
defparam lsu_local_bb1_ld_.USE_WRITE_ACK = 0;
defparam lsu_local_bb1_ld_.ENABLE_BANKED_MEMORY = 0;
defparam lsu_local_bb1_ld_.ABITS_PER_LMEM_BANK = 0;
defparam lsu_local_bb1_ld_.NUMBER_BANKS = 1;
defparam lsu_local_bb1_ld_.LMEM_ADDR_PERMUTATION_STYLE = 0;
defparam lsu_local_bb1_ld_.INTENDED_DEVICE_FAMILY = "Cyclone V";
defparam lsu_local_bb1_ld_.USEINPUTFIFO = 0;
defparam lsu_local_bb1_ld_.USECACHING = 0;
defparam lsu_local_bb1_ld_.USEOUTPUTFIFO = 1;
defparam lsu_local_bb1_ld_.FORCE_NOP_SUPPORT = 0;
defparam lsu_local_bb1_ld_.ADDRSPACE = 1;
defparam lsu_local_bb1_ld_.STYLE = "BURST-COALESCED";

assign local_bb1_ld__inputs_ready = rstag_1to1_bb1_arrayidx_RM_valid_out;
assign local_bb1_ld__output_regs_ready = (&(~(local_bb1_ld__valid_out_NO_SHIFT_REG) | ~(local_bb1_ld__stall_in)));
assign rstag_1to1_bb1_arrayidx_RM_stall_in = (local_bb1_ld__fu_stall_out | ~(local_bb1_ld__inputs_ready));
assign local_bb1_ld__causedstall = (local_bb1_ld__inputs_ready && (local_bb1_ld__fu_stall_out && !(~(local_bb1_ld__output_regs_ready))));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_ld__NO_SHIFT_REG <= 'x;
		local_bb1_ld__valid_out_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (local_bb1_ld__output_regs_ready)
		begin
			local_bb1_ld__NO_SHIFT_REG <= local_bb1_ld__lsu_dataout;
			local_bb1_ld__valid_out_NO_SHIFT_REG <= local_bb1_ld__fu_valid_out;
		end
		else
		begin
			if (~(local_bb1_ld__stall_in))
			begin
				local_bb1_ld__valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end


// This section implements a registered operation.
// 
wire local_bb1_ld__u0_inputs_ready;
 reg local_bb1_ld__u0_valid_out_NO_SHIFT_REG;
wire local_bb1_ld__u0_stall_in;
wire local_bb1_ld__u0_output_regs_ready;
wire local_bb1_ld__u0_fu_stall_out;
wire local_bb1_ld__u0_fu_valid_out;
wire [31:0] local_bb1_ld__u0_lsu_dataout;
 reg [31:0] local_bb1_ld__u0_NO_SHIFT_REG;
wire local_bb1_ld__u0_causedstall;

lsu_top lsu_local_bb1_ld__u0 (
	.clock(clock),
	.clock2x(clock2x),
	.resetn(resetn),
	.flush(start),
	.stream_base_addr(),
	.stream_size(),
	.stream_reset(),
	.o_stall(local_bb1_ld__u0_fu_stall_out),
	.i_valid(local_bb1_ld__u0_inputs_ready),
	.i_address((rstag_1to1_bb1_arrayidx3_RM & 64'hFFFFFFFFFFFFFFFC)),
	.i_writedata(),
	.i_cmpdata(),
	.i_predicate(1'b0),
	.i_bitwiseor(64'h0),
	.i_byteenable(),
	.i_stall(~(local_bb1_ld__u0_output_regs_ready)),
	.o_valid(local_bb1_ld__u0_fu_valid_out),
	.o_readdata(local_bb1_ld__u0_lsu_dataout),
	.o_input_fifo_depth(),
	.o_writeack(),
	.i_atomic_op(3'h0),
	.o_active(local_bb1_ld__u0_active),
	.avm_address(avm_local_bb1_ld__u0_address),
	.avm_read(avm_local_bb1_ld__u0_read),
	.avm_enable(avm_local_bb1_ld__u0_enable),
	.avm_readdata(avm_local_bb1_ld__u0_readdata),
	.avm_write(avm_local_bb1_ld__u0_write),
	.avm_writeack(avm_local_bb1_ld__u0_writeack),
	.avm_burstcount(avm_local_bb1_ld__u0_burstcount),
	.avm_writedata(avm_local_bb1_ld__u0_writedata),
	.avm_byteenable(avm_local_bb1_ld__u0_byteenable),
	.avm_waitrequest(avm_local_bb1_ld__u0_waitrequest),
	.avm_readdatavalid(avm_local_bb1_ld__u0_readdatavalid),
	.profile_bw(),
	.profile_bw_incr(),
	.profile_total_ivalid(),
	.profile_total_req(),
	.profile_i_stall_count(),
	.profile_o_stall_count(),
	.profile_avm_readwrite_count(),
	.profile_avm_burstcount_total(),
	.profile_avm_burstcount_total_incr(),
	.profile_req_cache_hit_count(),
	.profile_extra_unaligned_reqs(),
	.profile_avm_stall()
);

defparam lsu_local_bb1_ld__u0.AWIDTH = 31;
defparam lsu_local_bb1_ld__u0.WIDTH_BYTES = 4;
defparam lsu_local_bb1_ld__u0.MWIDTH_BYTES = 32;
defparam lsu_local_bb1_ld__u0.WRITEDATAWIDTH_BYTES = 32;
defparam lsu_local_bb1_ld__u0.ALIGNMENT_BYTES = 4;
defparam lsu_local_bb1_ld__u0.READ = 1;
defparam lsu_local_bb1_ld__u0.ATOMIC = 0;
defparam lsu_local_bb1_ld__u0.WIDTH = 32;
defparam lsu_local_bb1_ld__u0.MWIDTH = 256;
defparam lsu_local_bb1_ld__u0.ATOMIC_WIDTH = 3;
defparam lsu_local_bb1_ld__u0.BURSTCOUNT_WIDTH = 5;
defparam lsu_local_bb1_ld__u0.KERNEL_SIDE_MEM_LATENCY = 160;
defparam lsu_local_bb1_ld__u0.MEMORY_SIDE_MEM_LATENCY = 89;
defparam lsu_local_bb1_ld__u0.USE_WRITE_ACK = 0;
defparam lsu_local_bb1_ld__u0.ENABLE_BANKED_MEMORY = 0;
defparam lsu_local_bb1_ld__u0.ABITS_PER_LMEM_BANK = 0;
defparam lsu_local_bb1_ld__u0.NUMBER_BANKS = 1;
defparam lsu_local_bb1_ld__u0.LMEM_ADDR_PERMUTATION_STYLE = 0;
defparam lsu_local_bb1_ld__u0.INTENDED_DEVICE_FAMILY = "Cyclone V";
defparam lsu_local_bb1_ld__u0.USEINPUTFIFO = 0;
defparam lsu_local_bb1_ld__u0.USECACHING = 0;
defparam lsu_local_bb1_ld__u0.USEOUTPUTFIFO = 1;
defparam lsu_local_bb1_ld__u0.FORCE_NOP_SUPPORT = 0;
defparam lsu_local_bb1_ld__u0.ADDRSPACE = 1;
defparam lsu_local_bb1_ld__u0.STYLE = "BURST-COALESCED";

assign local_bb1_ld__u0_inputs_ready = rstag_1to1_bb1_arrayidx3_RM_valid_out;
assign local_bb1_ld__u0_output_regs_ready = (&(~(local_bb1_ld__u0_valid_out_NO_SHIFT_REG) | ~(local_bb1_ld__u0_stall_in)));
assign rstag_1to1_bb1_arrayidx3_RM_stall_in = (local_bb1_ld__u0_fu_stall_out | ~(local_bb1_ld__u0_inputs_ready));
assign local_bb1_ld__u0_causedstall = (local_bb1_ld__u0_inputs_ready && (local_bb1_ld__u0_fu_stall_out && !(~(local_bb1_ld__u0_output_regs_ready))));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_ld__u0_NO_SHIFT_REG <= 'x;
		local_bb1_ld__u0_valid_out_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (local_bb1_ld__u0_output_regs_ready)
		begin
			local_bb1_ld__u0_NO_SHIFT_REG <= local_bb1_ld__u0_lsu_dataout;
			local_bb1_ld__u0_valid_out_NO_SHIFT_REG <= local_bb1_ld__u0_fu_valid_out;
		end
		else
		begin
			if (~(local_bb1_ld__u0_stall_in))
			begin
				local_bb1_ld__u0_valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end


// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_164to165_bb1_arrayidx5_RM_0_valid_out_NO_SHIFT_REG;
 logic rnode_164to165_bb1_arrayidx5_RM_0_stall_in_NO_SHIFT_REG;
 logic [63:0] rnode_164to165_bb1_arrayidx5_RM_0_NO_SHIFT_REG;
 logic rnode_164to165_bb1_arrayidx5_RM_0_reg_165_inputs_ready_NO_SHIFT_REG;
 logic [63:0] rnode_164to165_bb1_arrayidx5_RM_0_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1_arrayidx5_RM_0_valid_out_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1_arrayidx5_RM_0_stall_in_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1_arrayidx5_RM_0_stall_out_reg_165_NO_SHIFT_REG;
wire [63:0] rci_rcnode_324to325_rc0_bb1_inc_0_reg_324;

acl_data_fifo rnode_164to165_bb1_arrayidx5_RM_0_reg_165_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_164to165_bb1_arrayidx5_RM_0_reg_165_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_164to165_bb1_arrayidx5_RM_0_stall_in_reg_165_NO_SHIFT_REG),
	.valid_out(rnode_164to165_bb1_arrayidx5_RM_0_valid_out_reg_165_NO_SHIFT_REG),
	.stall_out(rnode_164to165_bb1_arrayidx5_RM_0_stall_out_reg_165_NO_SHIFT_REG),
	.data_in((rnode_1to164_bb1_arrayidx5_RM_0_NO_SHIFT_REG & 64'hFFFFFFFFFFFFFFFC)),
	.data_out(rnode_164to165_bb1_arrayidx5_RM_0_reg_165_NO_SHIFT_REG)
);

defparam rnode_164to165_bb1_arrayidx5_RM_0_reg_165_fifo.DEPTH = 2;
defparam rnode_164to165_bb1_arrayidx5_RM_0_reg_165_fifo.DATA_WIDTH = 64;
defparam rnode_164to165_bb1_arrayidx5_RM_0_reg_165_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_164to165_bb1_arrayidx5_RM_0_reg_165_fifo.IMPL = "ll_reg";

assign rnode_164to165_bb1_arrayidx5_RM_0_reg_165_inputs_ready_NO_SHIFT_REG = rnode_1to164_bb1_arrayidx5_RM_0_valid_out_NO_SHIFT_REG;
assign rnode_1to164_bb1_arrayidx5_RM_0_stall_in_NO_SHIFT_REG = rnode_164to165_bb1_arrayidx5_RM_0_stall_out_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_arrayidx5_RM_0_NO_SHIFT_REG = rnode_164to165_bb1_arrayidx5_RM_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_arrayidx5_RM_0_stall_in_reg_165_NO_SHIFT_REG = rnode_164to165_bb1_arrayidx5_RM_0_stall_in_NO_SHIFT_REG;
assign rnode_164to165_bb1_arrayidx5_RM_0_valid_out_NO_SHIFT_REG = rnode_164to165_bb1_arrayidx5_RM_0_valid_out_reg_165_NO_SHIFT_REG;
assign rci_rcnode_324to325_rc0_bb1_inc_0_reg_324[31:0] = (local_bb1_inc & 32'h7FF);
assign rci_rcnode_324to325_rc0_bb1_inc_0_reg_324[63:32] = rnode_1to324_input_global_id_0_0_NO_SHIFT_REG;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rcnode_324to325_rc0_bb1_inc_0_valid_out_0_NO_SHIFT_REG;
 logic rcnode_324to325_rc0_bb1_inc_0_stall_in_0_NO_SHIFT_REG;
 logic [63:0] rcnode_324to325_rc0_bb1_inc_0_NO_SHIFT_REG;
 logic rcnode_324to325_rc0_bb1_inc_0_valid_out_1_NO_SHIFT_REG;
 logic rcnode_324to325_rc0_bb1_inc_0_stall_in_1_NO_SHIFT_REG;
 logic [63:0] rcnode_324to325_rc0_bb1_inc_1_NO_SHIFT_REG;
 logic rcnode_324to325_rc0_bb1_inc_0_reg_325_inputs_ready_NO_SHIFT_REG;
 logic [63:0] rcnode_324to325_rc0_bb1_inc_0_reg_325_NO_SHIFT_REG;
 logic rcnode_324to325_rc0_bb1_inc_0_valid_out_0_reg_325_NO_SHIFT_REG;
 logic rcnode_324to325_rc0_bb1_inc_0_stall_in_0_reg_325_NO_SHIFT_REG;
 logic rcnode_324to325_rc0_bb1_inc_0_stall_out_0_reg_325_IP_NO_SHIFT_REG;
 logic rcnode_324to325_rc0_bb1_inc_0_stall_out_0_reg_325_NO_SHIFT_REG;

acl_data_fifo rcnode_324to325_rc0_bb1_inc_0_reg_325_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rcnode_324to325_rc0_bb1_inc_0_reg_325_inputs_ready_NO_SHIFT_REG),
	.stall_in(rcnode_324to325_rc0_bb1_inc_0_stall_in_0_reg_325_NO_SHIFT_REG),
	.valid_out(rcnode_324to325_rc0_bb1_inc_0_valid_out_0_reg_325_NO_SHIFT_REG),
	.stall_out(rcnode_324to325_rc0_bb1_inc_0_stall_out_0_reg_325_IP_NO_SHIFT_REG),
	.data_in(rci_rcnode_324to325_rc0_bb1_inc_0_reg_324),
	.data_out(rcnode_324to325_rc0_bb1_inc_0_reg_325_NO_SHIFT_REG)
);

defparam rcnode_324to325_rc0_bb1_inc_0_reg_325_fifo.DEPTH = 1;
defparam rcnode_324to325_rc0_bb1_inc_0_reg_325_fifo.DATA_WIDTH = 64;
defparam rcnode_324to325_rc0_bb1_inc_0_reg_325_fifo.ALLOW_FULL_WRITE = 1;
defparam rcnode_324to325_rc0_bb1_inc_0_reg_325_fifo.IMPL = "ll_reg";

assign rcnode_324to325_rc0_bb1_inc_0_reg_325_inputs_ready_NO_SHIFT_REG = (local_bb1_inc_valid_out & rnode_1to324_input_global_id_0_0_valid_out_NO_SHIFT_REG);
assign rcnode_324to325_rc0_bb1_inc_0_stall_out_0_reg_325_NO_SHIFT_REG = (~(rcnode_324to325_rc0_bb1_inc_0_reg_325_inputs_ready_NO_SHIFT_REG) | rcnode_324to325_rc0_bb1_inc_0_stall_out_0_reg_325_IP_NO_SHIFT_REG);
assign local_bb1_inc_stall_in = rcnode_324to325_rc0_bb1_inc_0_stall_out_0_reg_325_NO_SHIFT_REG;
assign rnode_1to324_input_global_id_0_0_stall_in_NO_SHIFT_REG = rcnode_324to325_rc0_bb1_inc_0_stall_out_0_reg_325_NO_SHIFT_REG;
assign rcnode_324to325_rc0_bb1_inc_0_stall_in_0_reg_325_NO_SHIFT_REG = (rcnode_324to325_rc0_bb1_inc_0_stall_in_0_NO_SHIFT_REG | rcnode_324to325_rc0_bb1_inc_0_stall_in_1_NO_SHIFT_REG);
assign rcnode_324to325_rc0_bb1_inc_0_valid_out_0_NO_SHIFT_REG = rcnode_324to325_rc0_bb1_inc_0_valid_out_0_reg_325_NO_SHIFT_REG;
assign rcnode_324to325_rc0_bb1_inc_0_valid_out_1_NO_SHIFT_REG = rcnode_324to325_rc0_bb1_inc_0_valid_out_0_reg_325_NO_SHIFT_REG;
assign rcnode_324to325_rc0_bb1_inc_0_NO_SHIFT_REG = rcnode_324to325_rc0_bb1_inc_0_reg_325_NO_SHIFT_REG;
assign rcnode_324to325_rc0_bb1_inc_1_NO_SHIFT_REG = rcnode_324to325_rc0_bb1_inc_0_reg_325_NO_SHIFT_REG;

// This section implements a staging register.
// 
wire rstag_161to161_bb1_ld__valid_out;
wire rstag_161to161_bb1_ld__stall_in;
wire rstag_161to161_bb1_ld__inputs_ready;
wire rstag_161to161_bb1_ld__stall_local;
 reg rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG;
wire rstag_161to161_bb1_ld__combined_valid;
 reg [31:0] rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG;
wire [31:0] rstag_161to161_bb1_ld_;

assign rstag_161to161_bb1_ld__inputs_ready = local_bb1_ld__valid_out_NO_SHIFT_REG;
assign rstag_161to161_bb1_ld_ = (rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ? rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG : local_bb1_ld__NO_SHIFT_REG);
assign rstag_161to161_bb1_ld__combined_valid = (rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG | rstag_161to161_bb1_ld__inputs_ready);
assign rstag_161to161_bb1_ld__valid_out = rstag_161to161_bb1_ld__combined_valid;
assign rstag_161to161_bb1_ld__stall_local = rstag_161to161_bb1_ld__stall_in;
assign local_bb1_ld__stall_in = (|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG <= 1'b0;
		rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (rstag_161to161_bb1_ld__stall_local)
		begin
			if (~(rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG))
			begin
				rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG <= rstag_161to161_bb1_ld__inputs_ready;
			end
		end
		else
		begin
			rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG <= 1'b0;
		end
		if (~(rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG))
		begin
			rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG <= local_bb1_ld__NO_SHIFT_REG;
		end
	end
end


// This section implements a staging register.
// 
wire rstag_161to161_bb1_ld__u0_valid_out;
wire rstag_161to161_bb1_ld__u0_stall_in;
wire rstag_161to161_bb1_ld__u0_inputs_ready;
wire rstag_161to161_bb1_ld__u0_stall_local;
 reg rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG;
wire rstag_161to161_bb1_ld__u0_combined_valid;
 reg [31:0] rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG;
wire [31:0] rstag_161to161_bb1_ld__u0;

assign rstag_161to161_bb1_ld__u0_inputs_ready = local_bb1_ld__u0_valid_out_NO_SHIFT_REG;
assign rstag_161to161_bb1_ld__u0 = (rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ? rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG : local_bb1_ld__u0_NO_SHIFT_REG);
assign rstag_161to161_bb1_ld__u0_combined_valid = (rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG | rstag_161to161_bb1_ld__u0_inputs_ready);
assign rstag_161to161_bb1_ld__u0_valid_out = rstag_161to161_bb1_ld__u0_combined_valid;
assign rstag_161to161_bb1_ld__u0_stall_local = rstag_161to161_bb1_ld__u0_stall_in;
assign local_bb1_ld__u0_stall_in = (|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG <= 1'b0;
		rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (rstag_161to161_bb1_ld__u0_stall_local)
		begin
			if (~(rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG))
			begin
				rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG <= rstag_161to161_bb1_ld__u0_inputs_ready;
			end
		end
		else
		begin
			rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG <= 1'b0;
		end
		if (~(rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG))
		begin
			rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG <= local_bb1_ld__u0_NO_SHIFT_REG;
		end
	end
end


// This section implements an unregistered operation.
// 
wire local_bb1_exitcond_valid_out;
wire local_bb1_exitcond_stall_in;
wire local_bb1_exitcond_inputs_ready;
wire local_bb1_exitcond_stall_local;
wire local_bb1_exitcond;

assign local_bb1_exitcond_inputs_ready = rcnode_324to325_rc0_bb1_inc_0_valid_out_0_NO_SHIFT_REG;
assign local_bb1_exitcond = ((rcnode_324to325_rc0_bb1_inc_0_NO_SHIFT_REG[31:0] & 32'h7FF) == 32'h3E8);
assign local_bb1_exitcond_valid_out = local_bb1_exitcond_inputs_ready;
assign local_bb1_exitcond_stall_local = local_bb1_exitcond_stall_in;
assign rcnode_324to325_rc0_bb1_inc_0_stall_in_0_NO_SHIFT_REG = (|local_bb1_exitcond_stall_local);

// This section implements an unregistered operation.
// 
wire local_bb1_var__stall_local;
wire [31:0] local_bb1_var_;

assign local_bb1_var_ = rstag_161to161_bb1_ld_;

// This section implements an unregistered operation.
// 
wire local_bb1_var__u1_stall_local;
wire [31:0] local_bb1_var__u1;

assign local_bb1_var__u1 = rstag_161to161_bb1_ld__u0;

// This section implements an unregistered operation.
// 
wire local_bb1_shr_i_stall_local;
wire [31:0] local_bb1_shr_i;

assign local_bb1_shr_i = (local_bb1_var_ >> 32'h17);

// This section implements an unregistered operation.
// 
wire local_bb1_and5_i_stall_local;
wire [31:0] local_bb1_and5_i;

assign local_bb1_and5_i = (local_bb1_var_ & 32'h7FFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1_shr2_i_stall_local;
wire [31:0] local_bb1_shr2_i;

assign local_bb1_shr2_i = (local_bb1_var__u1 >> 32'h17);

// This section implements an unregistered operation.
// 
wire local_bb1_xor_i_stall_local;
wire [31:0] local_bb1_xor_i;

assign local_bb1_xor_i = (local_bb1_var__u1 ^ local_bb1_var_);

// This section implements an unregistered operation.
// 
wire local_bb1_and6_i_stall_local;
wire [31:0] local_bb1_and6_i;

assign local_bb1_and6_i = (local_bb1_var__u1 & 32'h7FFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u2_stall_local;
wire [31:0] local_bb1_var__u2;

assign local_bb1_var__u2 = (local_bb1_var_ | local_bb1_var__u1);

// This section implements an unregistered operation.
// 
wire local_bb1_and_i_stall_local;
wire [31:0] local_bb1_and_i;

assign local_bb1_and_i = ((local_bb1_shr_i & 32'h1FF) & 32'hFF);

// This section implements an unregistered operation.
// 
wire local_bb1_lnot14_not_i_stall_local;
wire local_bb1_lnot14_not_i;

assign local_bb1_lnot14_not_i = ((local_bb1_and5_i & 32'h7FFFFF) != 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_or_i_stall_local;
wire [31:0] local_bb1_or_i;

assign local_bb1_or_i = ((local_bb1_and5_i & 32'h7FFFFF) | 32'h800000);

// This section implements an unregistered operation.
// 
wire local_bb1_and3_i_stall_local;
wire [31:0] local_bb1_and3_i;

assign local_bb1_and3_i = ((local_bb1_shr2_i & 32'h1FF) & 32'hFF);

// This section implements an unregistered operation.
// 
wire local_bb1_lnot17_i_stall_local;
wire local_bb1_lnot17_i;

assign local_bb1_lnot17_i = ((local_bb1_and6_i & 32'h7FFFFF) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_or47_i_stall_local;
wire [31:0] local_bb1_or47_i;

assign local_bb1_or47_i = ((local_bb1_and6_i & 32'h7FFFFF) | 32'h800000);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u3_stall_local;
wire [31:0] local_bb1_var__u3;

assign local_bb1_var__u3 = (local_bb1_var__u2 & 32'h7FFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1_lnot_i_stall_local;
wire local_bb1_lnot_i;

assign local_bb1_lnot_i = ((local_bb1_and_i & 32'hFF) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp_i_stall_local;
wire local_bb1_cmp_i;

assign local_bb1_cmp_i = ((local_bb1_and_i & 32'hFF) == 32'hFF);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u4_stall_local;
wire [31:0] local_bb1_var__u4;

assign local_bb1_var__u4 = ((local_bb1_and_i & 32'hFF) | (local_bb1_and5_i & 32'h7FFFFF));

// This section implements an unregistered operation.
// 
wire local_bb1_conv_i_i_stall_local;
wire [63:0] local_bb1_conv_i_i;

assign local_bb1_conv_i_i[63:32] = 32'h0;
assign local_bb1_conv_i_i[31:0] = ((local_bb1_or_i & 32'hFFFFFF) | 32'h800000);

// This section implements an unregistered operation.
// 
wire local_bb1_lnot8_i_stall_local;
wire local_bb1_lnot8_i;

assign local_bb1_lnot8_i = ((local_bb1_and3_i & 32'hFF) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp11_i_stall_local;
wire local_bb1_cmp11_i;

assign local_bb1_cmp11_i = ((local_bb1_and3_i & 32'hFF) == 32'hFF);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u5_stall_local;
wire [31:0] local_bb1_var__u5;

assign local_bb1_var__u5 = ((local_bb1_and3_i & 32'hFF) | (local_bb1_and6_i & 32'h7FFFFF));

// This section implements an unregistered operation.
// 
wire local_bb1_add_i_stall_local;
wire [31:0] local_bb1_add_i;

assign local_bb1_add_i = ((local_bb1_and3_i & 32'hFF) + (local_bb1_and_i & 32'hFF));

// This section implements an unregistered operation.
// 
wire local_bb1_conv1_i_i_stall_local;
wire [63:0] local_bb1_conv1_i_i;

assign local_bb1_conv1_i_i[63:32] = 32'h0;
assign local_bb1_conv1_i_i[31:0] = ((local_bb1_or47_i & 32'hFFFFFF) | 32'h800000);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u6_stall_local;
wire local_bb1_var__u6;

assign local_bb1_var__u6 = ((local_bb1_var__u3 & 32'h7FFFFF) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1__22_i_stall_local;
wire local_bb1__22_i;

assign local_bb1__22_i = (local_bb1_cmp_i & local_bb1_lnot14_not_i);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u7_stall_local;
wire local_bb1_var__u7;

assign local_bb1_var__u7 = ((local_bb1_var__u4 & 32'h7FFFFF) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_3_i_stall_local;
wire local_bb1_reduction_3_i;

assign local_bb1_reduction_3_i = (local_bb1_lnot_i | local_bb1_lnot8_i);

// This section implements an unregistered operation.
// 
wire local_bb1_brmerge13_demorgan_i_stall_local;
wire local_bb1_brmerge13_demorgan_i;

assign local_bb1_brmerge13_demorgan_i = (local_bb1_cmp11_i & local_bb1_lnot17_i);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u8_stall_local;
wire local_bb1_var__u8;

assign local_bb1_var__u8 = (local_bb1_cmp_i | local_bb1_cmp11_i);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u9_stall_local;
wire local_bb1_var__u9;

assign local_bb1_var__u9 = ((local_bb1_var__u5 & 32'h7FFFFF) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1__20_demorgan_i_stall_local;
wire local_bb1__20_demorgan_i;

assign local_bb1__20_demorgan_i = (local_bb1_cmp_i | local_bb1_brmerge13_demorgan_i);

// This section implements an unregistered operation.
// 
wire local_bb1__not_i_stall_local;
wire local_bb1__not_i;

assign local_bb1__not_i = (local_bb1_var__u9 ^ 1'b1);

// This section implements an unregistered operation.
// 
wire local_bb1__mux_mux_i_stall_local;
wire local_bb1__mux_mux_i;

assign local_bb1__mux_mux_i = (local_bb1_var__u9 | local_bb1_cmp11_i);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_1_i_stall_local;
wire local_bb1_reduction_1_i;

assign local_bb1_reduction_1_i = (local_bb1_cmp11_i & local_bb1__not_i);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_2_i_stall_local;
wire local_bb1_reduction_2_i;

assign local_bb1_reduction_2_i = (local_bb1_var__u6 & local_bb1_reduction_1_i);

// This section implements an unregistered operation.
// 
wire local_bb1__18_i_stall_local;
wire local_bb1__18_i;

assign local_bb1__18_i = (local_bb1_cmp_i ? local_bb1_reduction_2_i : local_bb1_brmerge13_demorgan_i);

// This section implements an unregistered operation.
// 
wire local_bb1__19_i_stall_local;
wire local_bb1__19_i;

assign local_bb1__19_i = (local_bb1__18_i ? local_bb1_var__u7 : local_bb1__mux_mux_i);

// This section implements an unregistered operation.
// 
wire local_bb1__21_i_stall_local;
wire local_bb1__21_i;

assign local_bb1__21_i = (local_bb1__20_demorgan_i ? local_bb1__19_i : local_bb1_cmp11_i);

// This section implements an unregistered operation.
// 
wire local_bb1_xor_i_valid_out;
wire local_bb1_xor_i_stall_in;
wire local_bb1_add_i_valid_out;
wire local_bb1_add_i_stall_in;
wire local_bb1_conv_i_i_valid_out;
wire local_bb1_conv_i_i_stall_in;
wire local_bb1_conv1_i_i_valid_out;
wire local_bb1_conv1_i_i_stall_in;
wire local_bb1_reduction_3_i_valid_out;
wire local_bb1_reduction_3_i_stall_in;
wire local_bb1_var__u8_valid_out;
wire local_bb1_var__u8_stall_in;
wire local_bb1__23_i_valid_out;
wire local_bb1__23_i_stall_in;
wire local_bb1__23_i_inputs_ready;
wire local_bb1__23_i_stall_local;
wire local_bb1__23_i;
 reg local_bb1_xor_i_consumed_0_NO_SHIFT_REG;
 reg local_bb1_add_i_consumed_0_NO_SHIFT_REG;
 reg local_bb1_conv_i_i_consumed_0_NO_SHIFT_REG;
 reg local_bb1_conv1_i_i_consumed_0_NO_SHIFT_REG;
 reg local_bb1_reduction_3_i_consumed_0_NO_SHIFT_REG;
 reg local_bb1_var__u8_consumed_0_NO_SHIFT_REG;
 reg local_bb1__23_i_consumed_0_NO_SHIFT_REG;

assign local_bb1__23_i_inputs_ready = (rstag_161to161_bb1_ld__valid_out & rstag_161to161_bb1_ld__u0_valid_out);
assign local_bb1__23_i = (local_bb1__22_i | local_bb1__21_i);
assign local_bb1__23_i_stall_local = ((local_bb1_xor_i_stall_in & ~(local_bb1_xor_i_consumed_0_NO_SHIFT_REG)) | (local_bb1_add_i_stall_in & ~(local_bb1_add_i_consumed_0_NO_SHIFT_REG)) | (local_bb1_conv_i_i_stall_in & ~(local_bb1_conv_i_i_consumed_0_NO_SHIFT_REG)) | (local_bb1_conv1_i_i_stall_in & ~(local_bb1_conv1_i_i_consumed_0_NO_SHIFT_REG)) | (local_bb1_reduction_3_i_stall_in & ~(local_bb1_reduction_3_i_consumed_0_NO_SHIFT_REG)) | (local_bb1_var__u8_stall_in & ~(local_bb1_var__u8_consumed_0_NO_SHIFT_REG)) | (local_bb1__23_i_stall_in & ~(local_bb1__23_i_consumed_0_NO_SHIFT_REG)));
assign local_bb1_xor_i_valid_out = (local_bb1__23_i_inputs_ready & ~(local_bb1_xor_i_consumed_0_NO_SHIFT_REG));
assign local_bb1_add_i_valid_out = (local_bb1__23_i_inputs_ready & ~(local_bb1_add_i_consumed_0_NO_SHIFT_REG));
assign local_bb1_conv_i_i_valid_out = (local_bb1__23_i_inputs_ready & ~(local_bb1_conv_i_i_consumed_0_NO_SHIFT_REG));
assign local_bb1_conv1_i_i_valid_out = (local_bb1__23_i_inputs_ready & ~(local_bb1_conv1_i_i_consumed_0_NO_SHIFT_REG));
assign local_bb1_reduction_3_i_valid_out = (local_bb1__23_i_inputs_ready & ~(local_bb1_reduction_3_i_consumed_0_NO_SHIFT_REG));
assign local_bb1_var__u8_valid_out = (local_bb1__23_i_inputs_ready & ~(local_bb1_var__u8_consumed_0_NO_SHIFT_REG));
assign local_bb1__23_i_valid_out = (local_bb1__23_i_inputs_ready & ~(local_bb1__23_i_consumed_0_NO_SHIFT_REG));
assign rstag_161to161_bb1_ld__stall_in = (local_bb1__23_i_stall_local | ~(local_bb1__23_i_inputs_ready));
assign rstag_161to161_bb1_ld__u0_stall_in = (local_bb1__23_i_stall_local | ~(local_bb1__23_i_inputs_ready));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_xor_i_consumed_0_NO_SHIFT_REG <= 1'b0;
		local_bb1_add_i_consumed_0_NO_SHIFT_REG <= 1'b0;
		local_bb1_conv_i_i_consumed_0_NO_SHIFT_REG <= 1'b0;
		local_bb1_conv1_i_i_consumed_0_NO_SHIFT_REG <= 1'b0;
		local_bb1_reduction_3_i_consumed_0_NO_SHIFT_REG <= 1'b0;
		local_bb1_var__u8_consumed_0_NO_SHIFT_REG <= 1'b0;
		local_bb1__23_i_consumed_0_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		local_bb1_xor_i_consumed_0_NO_SHIFT_REG <= (local_bb1__23_i_inputs_ready & (local_bb1_xor_i_consumed_0_NO_SHIFT_REG | ~(local_bb1_xor_i_stall_in)) & local_bb1__23_i_stall_local);
		local_bb1_add_i_consumed_0_NO_SHIFT_REG <= (local_bb1__23_i_inputs_ready & (local_bb1_add_i_consumed_0_NO_SHIFT_REG | ~(local_bb1_add_i_stall_in)) & local_bb1__23_i_stall_local);
		local_bb1_conv_i_i_consumed_0_NO_SHIFT_REG <= (local_bb1__23_i_inputs_ready & (local_bb1_conv_i_i_consumed_0_NO_SHIFT_REG | ~(local_bb1_conv_i_i_stall_in)) & local_bb1__23_i_stall_local);
		local_bb1_conv1_i_i_consumed_0_NO_SHIFT_REG <= (local_bb1__23_i_inputs_ready & (local_bb1_conv1_i_i_consumed_0_NO_SHIFT_REG | ~(local_bb1_conv1_i_i_stall_in)) & local_bb1__23_i_stall_local);
		local_bb1_reduction_3_i_consumed_0_NO_SHIFT_REG <= (local_bb1__23_i_inputs_ready & (local_bb1_reduction_3_i_consumed_0_NO_SHIFT_REG | ~(local_bb1_reduction_3_i_stall_in)) & local_bb1__23_i_stall_local);
		local_bb1_var__u8_consumed_0_NO_SHIFT_REG <= (local_bb1__23_i_inputs_ready & (local_bb1_var__u8_consumed_0_NO_SHIFT_REG | ~(local_bb1_var__u8_stall_in)) & local_bb1__23_i_stall_local);
		local_bb1__23_i_consumed_0_NO_SHIFT_REG <= (local_bb1__23_i_inputs_ready & (local_bb1__23_i_consumed_0_NO_SHIFT_REG | ~(local_bb1__23_i_stall_in)) & local_bb1__23_i_stall_local);
	end
end


// Register node:
//  * latency = 4
//  * capacity = 4
 logic rnode_161to165_bb1_xor_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_161to165_bb1_xor_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_161to165_bb1_xor_i_0_NO_SHIFT_REG;
 logic rnode_161to165_bb1_xor_i_0_reg_165_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_161to165_bb1_xor_i_0_reg_165_NO_SHIFT_REG;
 logic rnode_161to165_bb1_xor_i_0_valid_out_reg_165_NO_SHIFT_REG;
 logic rnode_161to165_bb1_xor_i_0_stall_in_reg_165_NO_SHIFT_REG;
 logic rnode_161to165_bb1_xor_i_0_stall_out_reg_165_NO_SHIFT_REG;

acl_data_fifo rnode_161to165_bb1_xor_i_0_reg_165_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_161to165_bb1_xor_i_0_reg_165_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_161to165_bb1_xor_i_0_stall_in_reg_165_NO_SHIFT_REG),
	.valid_out(rnode_161to165_bb1_xor_i_0_valid_out_reg_165_NO_SHIFT_REG),
	.stall_out(rnode_161to165_bb1_xor_i_0_stall_out_reg_165_NO_SHIFT_REG),
	.data_in(local_bb1_xor_i),
	.data_out(rnode_161to165_bb1_xor_i_0_reg_165_NO_SHIFT_REG)
);

defparam rnode_161to165_bb1_xor_i_0_reg_165_fifo.DEPTH = 5;
defparam rnode_161to165_bb1_xor_i_0_reg_165_fifo.DATA_WIDTH = 32;
defparam rnode_161to165_bb1_xor_i_0_reg_165_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_161to165_bb1_xor_i_0_reg_165_fifo.IMPL = "ll_reg";

assign rnode_161to165_bb1_xor_i_0_reg_165_inputs_ready_NO_SHIFT_REG = local_bb1_xor_i_valid_out;
assign local_bb1_xor_i_stall_in = rnode_161to165_bb1_xor_i_0_stall_out_reg_165_NO_SHIFT_REG;
assign rnode_161to165_bb1_xor_i_0_NO_SHIFT_REG = rnode_161to165_bb1_xor_i_0_reg_165_NO_SHIFT_REG;
assign rnode_161to165_bb1_xor_i_0_stall_in_reg_165_NO_SHIFT_REG = rnode_161to165_bb1_xor_i_0_stall_in_NO_SHIFT_REG;
assign rnode_161to165_bb1_xor_i_0_valid_out_NO_SHIFT_REG = rnode_161to165_bb1_xor_i_0_valid_out_reg_165_NO_SHIFT_REG;

// Register node:
//  * latency = 3
//  * capacity = 3
 logic rnode_161to164_bb1_add_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_161to164_bb1_add_i_0_stall_in_0_NO_SHIFT_REG;
 logic [31:0] rnode_161to164_bb1_add_i_0_NO_SHIFT_REG;
 logic rnode_161to164_bb1_add_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_161to164_bb1_add_i_0_stall_in_1_NO_SHIFT_REG;
 logic [31:0] rnode_161to164_bb1_add_i_1_NO_SHIFT_REG;
 logic rnode_161to164_bb1_add_i_0_valid_out_2_NO_SHIFT_REG;
 logic rnode_161to164_bb1_add_i_0_stall_in_2_NO_SHIFT_REG;
 logic [31:0] rnode_161to164_bb1_add_i_2_NO_SHIFT_REG;
 logic rnode_161to164_bb1_add_i_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_161to164_bb1_add_i_0_reg_164_NO_SHIFT_REG;
 logic rnode_161to164_bb1_add_i_0_valid_out_0_reg_164_NO_SHIFT_REG;
 logic rnode_161to164_bb1_add_i_0_stall_in_0_reg_164_NO_SHIFT_REG;
 logic rnode_161to164_bb1_add_i_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_161to164_bb1_add_i_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_161to164_bb1_add_i_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_161to164_bb1_add_i_0_stall_in_0_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_161to164_bb1_add_i_0_valid_out_0_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_161to164_bb1_add_i_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in((local_bb1_add_i & 32'h1FF)),
	.data_out(rnode_161to164_bb1_add_i_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_161to164_bb1_add_i_0_reg_164_fifo.DEPTH = 4;
defparam rnode_161to164_bb1_add_i_0_reg_164_fifo.DATA_WIDTH = 32;
defparam rnode_161to164_bb1_add_i_0_reg_164_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_161to164_bb1_add_i_0_reg_164_fifo.IMPL = "ll_reg";

assign rnode_161to164_bb1_add_i_0_reg_164_inputs_ready_NO_SHIFT_REG = local_bb1_add_i_valid_out;
assign local_bb1_add_i_stall_in = rnode_161to164_bb1_add_i_0_stall_out_reg_164_NO_SHIFT_REG;
assign rnode_161to164_bb1_add_i_0_stall_in_0_reg_164_NO_SHIFT_REG = (rnode_161to164_bb1_add_i_0_stall_in_0_NO_SHIFT_REG | rnode_161to164_bb1_add_i_0_stall_in_1_NO_SHIFT_REG | rnode_161to164_bb1_add_i_0_stall_in_2_NO_SHIFT_REG);
assign rnode_161to164_bb1_add_i_0_valid_out_0_NO_SHIFT_REG = rnode_161to164_bb1_add_i_0_valid_out_0_reg_164_NO_SHIFT_REG;
assign rnode_161to164_bb1_add_i_0_valid_out_1_NO_SHIFT_REG = rnode_161to164_bb1_add_i_0_valid_out_0_reg_164_NO_SHIFT_REG;
assign rnode_161to164_bb1_add_i_0_valid_out_2_NO_SHIFT_REG = rnode_161to164_bb1_add_i_0_valid_out_0_reg_164_NO_SHIFT_REG;
assign rnode_161to164_bb1_add_i_0_NO_SHIFT_REG = rnode_161to164_bb1_add_i_0_reg_164_NO_SHIFT_REG;
assign rnode_161to164_bb1_add_i_1_NO_SHIFT_REG = rnode_161to164_bb1_add_i_0_reg_164_NO_SHIFT_REG;
assign rnode_161to164_bb1_add_i_2_NO_SHIFT_REG = rnode_161to164_bb1_add_i_0_reg_164_NO_SHIFT_REG;

// This section implements a staging register.
// 
wire rstag_161to161_bb1_conv_i_i_valid_out;
wire rstag_161to161_bb1_conv_i_i_stall_in;
wire rstag_161to161_bb1_conv_i_i_inputs_ready;
wire rstag_161to161_bb1_conv_i_i_stall_local;
 reg rstag_161to161_bb1_conv_i_i_staging_valid_NO_SHIFT_REG;
wire rstag_161to161_bb1_conv_i_i_combined_valid;
 reg [63:0] rstag_161to161_bb1_conv_i_i_staging_reg_NO_SHIFT_REG;
wire [63:0] rstag_161to161_bb1_conv_i_i;

assign rstag_161to161_bb1_conv_i_i_inputs_ready = local_bb1_conv_i_i_valid_out;
assign rstag_161to161_bb1_conv_i_i = (rstag_161to161_bb1_conv_i_i_staging_valid_NO_SHIFT_REG ? rstag_161to161_bb1_conv_i_i_staging_reg_NO_SHIFT_REG : ((local_bb1_conv_i_i & 64'hFFFFFF) | 64'h800000));
assign rstag_161to161_bb1_conv_i_i_combined_valid = (rstag_161to161_bb1_conv_i_i_staging_valid_NO_SHIFT_REG | rstag_161to161_bb1_conv_i_i_inputs_ready);
assign rstag_161to161_bb1_conv_i_i_valid_out = rstag_161to161_bb1_conv_i_i_combined_valid;
assign rstag_161to161_bb1_conv_i_i_stall_local = rstag_161to161_bb1_conv_i_i_stall_in;
assign local_bb1_conv_i_i_stall_in = (|rstag_161to161_bb1_conv_i_i_staging_valid_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		rstag_161to161_bb1_conv_i_i_staging_valid_NO_SHIFT_REG <= 1'b0;
		rstag_161to161_bb1_conv_i_i_staging_reg_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (rstag_161to161_bb1_conv_i_i_stall_local)
		begin
			if (~(rstag_161to161_bb1_conv_i_i_staging_valid_NO_SHIFT_REG))
			begin
				rstag_161to161_bb1_conv_i_i_staging_valid_NO_SHIFT_REG <= rstag_161to161_bb1_conv_i_i_inputs_ready;
			end
		end
		else
		begin
			rstag_161to161_bb1_conv_i_i_staging_valid_NO_SHIFT_REG <= 1'b0;
		end
		if (~(rstag_161to161_bb1_conv_i_i_staging_valid_NO_SHIFT_REG))
		begin
			rstag_161to161_bb1_conv_i_i_staging_reg_NO_SHIFT_REG <= ((local_bb1_conv_i_i & 64'hFFFFFF) | 64'h800000);
		end
	end
end


// This section implements a staging register.
// 
wire rstag_161to161_bb1_conv1_i_i_valid_out;
wire rstag_161to161_bb1_conv1_i_i_stall_in;
wire rstag_161to161_bb1_conv1_i_i_inputs_ready;
wire rstag_161to161_bb1_conv1_i_i_stall_local;
 reg rstag_161to161_bb1_conv1_i_i_staging_valid_NO_SHIFT_REG;
wire rstag_161to161_bb1_conv1_i_i_combined_valid;
 reg [63:0] rstag_161to161_bb1_conv1_i_i_staging_reg_NO_SHIFT_REG;
wire [63:0] rstag_161to161_bb1_conv1_i_i;

assign rstag_161to161_bb1_conv1_i_i_inputs_ready = local_bb1_conv1_i_i_valid_out;
assign rstag_161to161_bb1_conv1_i_i = (rstag_161to161_bb1_conv1_i_i_staging_valid_NO_SHIFT_REG ? rstag_161to161_bb1_conv1_i_i_staging_reg_NO_SHIFT_REG : ((local_bb1_conv1_i_i & 64'hFFFFFF) | 64'h800000));
assign rstag_161to161_bb1_conv1_i_i_combined_valid = (rstag_161to161_bb1_conv1_i_i_staging_valid_NO_SHIFT_REG | rstag_161to161_bb1_conv1_i_i_inputs_ready);
assign rstag_161to161_bb1_conv1_i_i_valid_out = rstag_161to161_bb1_conv1_i_i_combined_valid;
assign rstag_161to161_bb1_conv1_i_i_stall_local = rstag_161to161_bb1_conv1_i_i_stall_in;
assign local_bb1_conv1_i_i_stall_in = (|rstag_161to161_bb1_conv1_i_i_staging_valid_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		rstag_161to161_bb1_conv1_i_i_staging_valid_NO_SHIFT_REG <= 1'b0;
		rstag_161to161_bb1_conv1_i_i_staging_reg_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (rstag_161to161_bb1_conv1_i_i_stall_local)
		begin
			if (~(rstag_161to161_bb1_conv1_i_i_staging_valid_NO_SHIFT_REG))
			begin
				rstag_161to161_bb1_conv1_i_i_staging_valid_NO_SHIFT_REG <= rstag_161to161_bb1_conv1_i_i_inputs_ready;
			end
		end
		else
		begin
			rstag_161to161_bb1_conv1_i_i_staging_valid_NO_SHIFT_REG <= 1'b0;
		end
		if (~(rstag_161to161_bb1_conv1_i_i_staging_valid_NO_SHIFT_REG))
		begin
			rstag_161to161_bb1_conv1_i_i_staging_reg_NO_SHIFT_REG <= ((local_bb1_conv1_i_i & 64'hFFFFFF) | 64'h800000);
		end
	end
end


// Register node:
//  * latency = 4
//  * capacity = 4
 logic rnode_161to165_bb1_reduction_3_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_161to165_bb1_reduction_3_i_0_stall_in_NO_SHIFT_REG;
 logic rnode_161to165_bb1_reduction_3_i_0_NO_SHIFT_REG;
 logic rnode_161to165_bb1_reduction_3_i_0_reg_165_inputs_ready_NO_SHIFT_REG;
 logic rnode_161to165_bb1_reduction_3_i_0_reg_165_NO_SHIFT_REG;
 logic rnode_161to165_bb1_reduction_3_i_0_valid_out_reg_165_NO_SHIFT_REG;
 logic rnode_161to165_bb1_reduction_3_i_0_stall_in_reg_165_NO_SHIFT_REG;
 logic rnode_161to165_bb1_reduction_3_i_0_stall_out_reg_165_NO_SHIFT_REG;

acl_data_fifo rnode_161to165_bb1_reduction_3_i_0_reg_165_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_161to165_bb1_reduction_3_i_0_reg_165_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_161to165_bb1_reduction_3_i_0_stall_in_reg_165_NO_SHIFT_REG),
	.valid_out(rnode_161to165_bb1_reduction_3_i_0_valid_out_reg_165_NO_SHIFT_REG),
	.stall_out(rnode_161to165_bb1_reduction_3_i_0_stall_out_reg_165_NO_SHIFT_REG),
	.data_in(local_bb1_reduction_3_i),
	.data_out(rnode_161to165_bb1_reduction_3_i_0_reg_165_NO_SHIFT_REG)
);

defparam rnode_161to165_bb1_reduction_3_i_0_reg_165_fifo.DEPTH = 5;
defparam rnode_161to165_bb1_reduction_3_i_0_reg_165_fifo.DATA_WIDTH = 1;
defparam rnode_161to165_bb1_reduction_3_i_0_reg_165_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_161to165_bb1_reduction_3_i_0_reg_165_fifo.IMPL = "ll_reg";

assign rnode_161to165_bb1_reduction_3_i_0_reg_165_inputs_ready_NO_SHIFT_REG = local_bb1_reduction_3_i_valid_out;
assign local_bb1_reduction_3_i_stall_in = rnode_161to165_bb1_reduction_3_i_0_stall_out_reg_165_NO_SHIFT_REG;
assign rnode_161to165_bb1_reduction_3_i_0_NO_SHIFT_REG = rnode_161to165_bb1_reduction_3_i_0_reg_165_NO_SHIFT_REG;
assign rnode_161to165_bb1_reduction_3_i_0_stall_in_reg_165_NO_SHIFT_REG = rnode_161to165_bb1_reduction_3_i_0_stall_in_NO_SHIFT_REG;
assign rnode_161to165_bb1_reduction_3_i_0_valid_out_NO_SHIFT_REG = rnode_161to165_bb1_reduction_3_i_0_valid_out_reg_165_NO_SHIFT_REG;

// Register node:
//  * latency = 3
//  * capacity = 3
 logic rnode_161to164_bb1_var__u8_0_valid_out_NO_SHIFT_REG;
 logic rnode_161to164_bb1_var__u8_0_stall_in_NO_SHIFT_REG;
 logic rnode_161to164_bb1_var__u8_0_NO_SHIFT_REG;
 logic rnode_161to164_bb1_var__u8_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic rnode_161to164_bb1_var__u8_0_reg_164_NO_SHIFT_REG;
 logic rnode_161to164_bb1_var__u8_0_valid_out_reg_164_NO_SHIFT_REG;
 logic rnode_161to164_bb1_var__u8_0_stall_in_reg_164_NO_SHIFT_REG;
 logic rnode_161to164_bb1_var__u8_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_161to164_bb1_var__u8_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_161to164_bb1_var__u8_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_161to164_bb1_var__u8_0_stall_in_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_161to164_bb1_var__u8_0_valid_out_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_161to164_bb1_var__u8_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in(local_bb1_var__u8),
	.data_out(rnode_161to164_bb1_var__u8_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_161to164_bb1_var__u8_0_reg_164_fifo.DEPTH = 4;
defparam rnode_161to164_bb1_var__u8_0_reg_164_fifo.DATA_WIDTH = 1;
defparam rnode_161to164_bb1_var__u8_0_reg_164_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_161to164_bb1_var__u8_0_reg_164_fifo.IMPL = "ll_reg";

assign rnode_161to164_bb1_var__u8_0_reg_164_inputs_ready_NO_SHIFT_REG = local_bb1_var__u8_valid_out;
assign local_bb1_var__u8_stall_in = rnode_161to164_bb1_var__u8_0_stall_out_reg_164_NO_SHIFT_REG;
assign rnode_161to164_bb1_var__u8_0_NO_SHIFT_REG = rnode_161to164_bb1_var__u8_0_reg_164_NO_SHIFT_REG;
assign rnode_161to164_bb1_var__u8_0_stall_in_reg_164_NO_SHIFT_REG = rnode_161to164_bb1_var__u8_0_stall_in_NO_SHIFT_REG;
assign rnode_161to164_bb1_var__u8_0_valid_out_NO_SHIFT_REG = rnode_161to164_bb1_var__u8_0_valid_out_reg_164_NO_SHIFT_REG;

// Register node:
//  * latency = 4
//  * capacity = 4
 logic rnode_161to165_bb1__23_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_161to165_bb1__23_i_0_stall_in_NO_SHIFT_REG;
 logic rnode_161to165_bb1__23_i_0_NO_SHIFT_REG;
 logic rnode_161to165_bb1__23_i_0_reg_165_inputs_ready_NO_SHIFT_REG;
 logic rnode_161to165_bb1__23_i_0_reg_165_NO_SHIFT_REG;
 logic rnode_161to165_bb1__23_i_0_valid_out_reg_165_NO_SHIFT_REG;
 logic rnode_161to165_bb1__23_i_0_stall_in_reg_165_NO_SHIFT_REG;
 logic rnode_161to165_bb1__23_i_0_stall_out_reg_165_NO_SHIFT_REG;

acl_data_fifo rnode_161to165_bb1__23_i_0_reg_165_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_161to165_bb1__23_i_0_reg_165_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_161to165_bb1__23_i_0_stall_in_reg_165_NO_SHIFT_REG),
	.valid_out(rnode_161to165_bb1__23_i_0_valid_out_reg_165_NO_SHIFT_REG),
	.stall_out(rnode_161to165_bb1__23_i_0_stall_out_reg_165_NO_SHIFT_REG),
	.data_in(local_bb1__23_i),
	.data_out(rnode_161to165_bb1__23_i_0_reg_165_NO_SHIFT_REG)
);

defparam rnode_161to165_bb1__23_i_0_reg_165_fifo.DEPTH = 5;
defparam rnode_161to165_bb1__23_i_0_reg_165_fifo.DATA_WIDTH = 1;
defparam rnode_161to165_bb1__23_i_0_reg_165_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_161to165_bb1__23_i_0_reg_165_fifo.IMPL = "ll_reg";

assign rnode_161to165_bb1__23_i_0_reg_165_inputs_ready_NO_SHIFT_REG = local_bb1__23_i_valid_out;
assign local_bb1__23_i_stall_in = rnode_161to165_bb1__23_i_0_stall_out_reg_165_NO_SHIFT_REG;
assign rnode_161to165_bb1__23_i_0_NO_SHIFT_REG = rnode_161to165_bb1__23_i_0_reg_165_NO_SHIFT_REG;
assign rnode_161to165_bb1__23_i_0_stall_in_reg_165_NO_SHIFT_REG = rnode_161to165_bb1__23_i_0_stall_in_NO_SHIFT_REG;
assign rnode_161to165_bb1__23_i_0_valid_out_NO_SHIFT_REG = rnode_161to165_bb1__23_i_0_valid_out_reg_165_NO_SHIFT_REG;

// This section implements an unregistered operation.
// 
wire local_bb1_and4_i_stall_local;
wire [31:0] local_bb1_and4_i;

assign local_bb1_and4_i = (rnode_161to165_bb1_xor_i_0_NO_SHIFT_REG & 32'h80000000);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp50_not_i_stall_local;
wire local_bb1_cmp50_not_i;

assign local_bb1_cmp50_not_i = ((rnode_161to164_bb1_add_i_0_NO_SHIFT_REG & 32'h1FF) != 32'h7F);

// This section implements an unregistered operation.
// 
wire local_bb1_inc_i_stall_local;
wire [31:0] local_bb1_inc_i;

assign local_bb1_inc_i = ((rnode_161to164_bb1_add_i_1_NO_SHIFT_REG & 32'h1FF) + 32'h1);

// This section implements a registered operation.
// 
wire local_bb1_mul_i_i_inputs_ready;
 reg local_bb1_mul_i_i_valid_out_NO_SHIFT_REG;
wire local_bb1_mul_i_i_stall_in;
wire local_bb1_mul_i_i_output_regs_ready;
wire [63:0] local_bb1_mul_i_i;
 reg local_bb1_mul_i_i_valid_pipe_0_NO_SHIFT_REG;
 reg local_bb1_mul_i_i_valid_pipe_1_NO_SHIFT_REG;
wire local_bb1_mul_i_i_causedstall;

acl_int_mult int_module_local_bb1_mul_i_i (
	.clock(clock),
	.dataa(((rstag_161to161_bb1_conv1_i_i & 64'hFFFFFF) | 64'h800000)),
	.datab(((rstag_161to161_bb1_conv_i_i & 64'hFFFFFF) | 64'h800000)),
	.enable(local_bb1_mul_i_i_output_regs_ready),
	.result(local_bb1_mul_i_i)
);

defparam int_module_local_bb1_mul_i_i.INPUT1_WIDTH = 24;
defparam int_module_local_bb1_mul_i_i.INPUT2_WIDTH = 24;
defparam int_module_local_bb1_mul_i_i.OUTPUT_WIDTH = 64;
defparam int_module_local_bb1_mul_i_i.LATENCY = 3;
defparam int_module_local_bb1_mul_i_i.SIGNED = 0;

assign local_bb1_mul_i_i_inputs_ready = (rstag_161to161_bb1_conv1_i_i_valid_out & rstag_161to161_bb1_conv_i_i_valid_out);
assign local_bb1_mul_i_i_output_regs_ready = (&(~(local_bb1_mul_i_i_valid_out_NO_SHIFT_REG) | ~(local_bb1_mul_i_i_stall_in)));
assign rstag_161to161_bb1_conv1_i_i_stall_in = (~(local_bb1_mul_i_i_output_regs_ready) | ~(local_bb1_mul_i_i_inputs_ready));
assign rstag_161to161_bb1_conv_i_i_stall_in = (~(local_bb1_mul_i_i_output_regs_ready) | ~(local_bb1_mul_i_i_inputs_ready));
assign local_bb1_mul_i_i_causedstall = (local_bb1_mul_i_i_inputs_ready && (~(local_bb1_mul_i_i_output_regs_ready) && !(~(local_bb1_mul_i_i_output_regs_ready))));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_mul_i_i_valid_pipe_0_NO_SHIFT_REG <= 1'b0;
		local_bb1_mul_i_i_valid_pipe_1_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (local_bb1_mul_i_i_output_regs_ready)
		begin
			local_bb1_mul_i_i_valid_pipe_0_NO_SHIFT_REG <= local_bb1_mul_i_i_inputs_ready;
			local_bb1_mul_i_i_valid_pipe_1_NO_SHIFT_REG <= local_bb1_mul_i_i_valid_pipe_0_NO_SHIFT_REG;
		end
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_mul_i_i_valid_out_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (local_bb1_mul_i_i_output_regs_ready)
		begin
			local_bb1_mul_i_i_valid_out_NO_SHIFT_REG <= local_bb1_mul_i_i_valid_pipe_1_NO_SHIFT_REG;
		end
		else
		begin
			if (~(local_bb1_mul_i_i_stall_in))
			begin
				local_bb1_mul_i_i_valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end


// Register node:
//  * latency = 0
//  * capacity = 2
 logic rnode_164to164_bb1_mul_i_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_164to164_bb1_mul_i_i_0_stall_in_0_NO_SHIFT_REG;
 logic [63:0] rnode_164to164_bb1_mul_i_i_0_NO_SHIFT_REG;
 logic rnode_164to164_bb1_mul_i_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_164to164_bb1_mul_i_i_0_stall_in_1_NO_SHIFT_REG;
 logic [63:0] rnode_164to164_bb1_mul_i_i_1_NO_SHIFT_REG;
 logic rnode_164to164_bb1_mul_i_i_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic [63:0] rnode_164to164_bb1_mul_i_i_0_reg_164_NO_SHIFT_REG;
 logic rnode_164to164_bb1_mul_i_i_0_valid_out_0_reg_164_NO_SHIFT_REG;
 logic rnode_164to164_bb1_mul_i_i_0_stall_in_0_reg_164_NO_SHIFT_REG;
 logic rnode_164to164_bb1_mul_i_i_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_164to164_bb1_mul_i_i_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_164to164_bb1_mul_i_i_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_164to164_bb1_mul_i_i_0_stall_in_0_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_164to164_bb1_mul_i_i_0_valid_out_0_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_164to164_bb1_mul_i_i_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in((local_bb1_mul_i_i & 64'hFFFFFFFFFFFF)),
	.data_out(rnode_164to164_bb1_mul_i_i_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_164to164_bb1_mul_i_i_0_reg_164_fifo.DEPTH = 3;
defparam rnode_164to164_bb1_mul_i_i_0_reg_164_fifo.DATA_WIDTH = 64;
defparam rnode_164to164_bb1_mul_i_i_0_reg_164_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_164to164_bb1_mul_i_i_0_reg_164_fifo.IMPL = "zl_reg";

assign rnode_164to164_bb1_mul_i_i_0_reg_164_inputs_ready_NO_SHIFT_REG = local_bb1_mul_i_i_valid_out_NO_SHIFT_REG;
assign local_bb1_mul_i_i_stall_in = rnode_164to164_bb1_mul_i_i_0_stall_out_reg_164_NO_SHIFT_REG;
assign rnode_164to164_bb1_mul_i_i_0_stall_in_0_reg_164_NO_SHIFT_REG = (rnode_164to164_bb1_mul_i_i_0_stall_in_0_NO_SHIFT_REG | rnode_164to164_bb1_mul_i_i_0_stall_in_1_NO_SHIFT_REG);
assign rnode_164to164_bb1_mul_i_i_0_valid_out_0_NO_SHIFT_REG = rnode_164to164_bb1_mul_i_i_0_valid_out_0_reg_164_NO_SHIFT_REG;
assign rnode_164to164_bb1_mul_i_i_0_valid_out_1_NO_SHIFT_REG = rnode_164to164_bb1_mul_i_i_0_valid_out_0_reg_164_NO_SHIFT_REG;
assign rnode_164to164_bb1_mul_i_i_0_NO_SHIFT_REG = rnode_164to164_bb1_mul_i_i_0_reg_164_NO_SHIFT_REG;
assign rnode_164to164_bb1_mul_i_i_1_NO_SHIFT_REG = rnode_164to164_bb1_mul_i_i_0_reg_164_NO_SHIFT_REG;

// This section implements an unregistered operation.
// 
wire local_bb1_var__u10_stall_local;
wire [63:0] local_bb1_var__u10;

assign local_bb1_var__u10 = ((rnode_164to164_bb1_mul_i_i_0_NO_SHIFT_REG & 64'hFFFFFFFFFFFF) >> 64'h18);

// This section implements an unregistered operation.
// 
wire local_bb1_conv3_i_i_stall_local;
wire [31:0] local_bb1_conv3_i_i;
wire [63:0] local_bb1_conv3_i_i$ps;

assign local_bb1_conv3_i_i$ps = (rnode_164to164_bb1_mul_i_i_1_NO_SHIFT_REG & 64'hFFFFFFFFFFFF);
assign local_bb1_conv3_i_i = local_bb1_conv3_i_i$ps[31:0];

// This section implements an unregistered operation.
// 
wire local_bb1__tr_i_stall_local;
wire [31:0] local_bb1__tr_i;
wire [63:0] local_bb1__tr_i$ps;

assign local_bb1__tr_i$ps = (local_bb1_var__u10 & 64'hFFFFFF);
assign local_bb1__tr_i = local_bb1__tr_i$ps[31:0];

// This section implements an unregistered operation.
// 
wire local_bb1_shr_i2_i_stall_local;
wire [31:0] local_bb1_shr_i2_i;

assign local_bb1_shr_i2_i = (local_bb1_conv3_i_i >> 32'h18);

// This section implements an unregistered operation.
// 
wire local_bb1_shl1_i4_i_stall_local;
wire [31:0] local_bb1_shl1_i4_i;

assign local_bb1_shl1_i4_i = (local_bb1_conv3_i_i << 32'h8);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u11_stall_local;
wire [31:0] local_bb1_var__u11;

assign local_bb1_var__u11 = (local_bb1_conv3_i_i >> 32'h17);

// This section implements an unregistered operation.
// 
wire local_bb1_shl1_i_i_stall_local;
wire [31:0] local_bb1_shl1_i_i;

assign local_bb1_shl1_i_i = (local_bb1_conv3_i_i << 32'h9);

// This section implements an unregistered operation.
// 
wire local_bb1_shl_i1_i_stall_local;
wire [31:0] local_bb1_shl_i1_i;

assign local_bb1_shl_i1_i = ((local_bb1__tr_i & 32'hFFFFFF) & 32'hFFFF00);

// This section implements an unregistered operation.
// 
wire local_bb1_and48_i_stall_local;
wire [31:0] local_bb1_and48_i;

assign local_bb1_and48_i = ((local_bb1__tr_i & 32'hFFFFFF) & 32'h800000);

// This section implements an unregistered operation.
// 
wire local_bb1_shr_i_i_stall_local;
wire [31:0] local_bb1_shr_i_i;

assign local_bb1_shr_i_i = ((local_bb1_var__u11 & 32'h1FF) & 32'h1);

// This section implements an unregistered operation.
// 
wire local_bb1_or_i3_i_stall_local;
wire [31:0] local_bb1_or_i3_i;

assign local_bb1_or_i3_i = ((local_bb1_shl_i1_i & 32'hFFFF00) | (local_bb1_shr_i2_i & 32'hFF));

// This section implements an unregistered operation.
// 
wire local_bb1_tobool49_i_stall_local;
wire local_bb1_tobool49_i;

assign local_bb1_tobool49_i = ((local_bb1_and48_i & 32'h800000) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_shl_i_i_stall_local;
wire [31:0] local_bb1_shl_i_i;

assign local_bb1_shl_i_i = ((local_bb1_or_i3_i & 32'hFFFFFF) << 32'h1);

// This section implements an unregistered operation.
// 
wire local_bb1__25_i_stall_local;
wire local_bb1__25_i;

assign local_bb1__25_i = (local_bb1_tobool49_i & local_bb1_cmp50_not_i);

// This section implements an unregistered operation.
// 
wire local_bb1_or_i_i_stall_local;
wire [31:0] local_bb1_or_i_i;

assign local_bb1_or_i_i = ((local_bb1_shl_i_i & 32'h1FFFFFE) | (local_bb1_shr_i_i & 32'h1));

// This section implements an unregistered operation.
// 
wire local_bb1__28_i_stall_local;
wire [31:0] local_bb1__28_i;

assign local_bb1__28_i = (local_bb1__25_i ? (local_bb1_shl1_i_i & 32'hFFFFFE00) : (local_bb1_shl1_i4_i & 32'hFFFFFF00));

// This section implements an unregistered operation.
// 
wire local_bb1__30_i_stall_local;
wire [31:0] local_bb1__30_i;

assign local_bb1__30_i = (local_bb1__25_i ? (rnode_161to164_bb1_add_i_2_NO_SHIFT_REG & 32'h1FF) : 32'h7F);

// This section implements an unregistered operation.
// 
wire local_bb1__26_i_stall_local;
wire [31:0] local_bb1__26_i;

assign local_bb1__26_i = (local_bb1__25_i ? (local_bb1_or_i_i & 32'h1FFFFFF) : (local_bb1_or_i3_i & 32'hFFFFFF));

// This section implements an unregistered operation.
// 
wire local_bb1__29_i_stall_local;
wire [31:0] local_bb1__29_i;

assign local_bb1__29_i = (local_bb1_tobool49_i ? (local_bb1__28_i & 32'hFFFFFF00) : (local_bb1_shl1_i4_i & 32'hFFFFFF00));

// This section implements an unregistered operation.
// 
wire local_bb1__31_i_stall_local;
wire [31:0] local_bb1__31_i;

assign local_bb1__31_i = (local_bb1_tobool49_i ? (local_bb1__30_i & 32'h1FF) : (local_bb1_inc_i & 32'h3FF));

// This section implements an unregistered operation.
// 
wire local_bb1__27_i_stall_local;
wire [31:0] local_bb1__27_i;

assign local_bb1__27_i = (local_bb1_tobool49_i ? (local_bb1__26_i & 32'h1FFFFFF) : (local_bb1_or_i3_i & 32'hFFFFFF));

// This section implements an unregistered operation.
// 
wire local_bb1_cmp70_i_stall_local;
wire local_bb1_cmp70_i;

assign local_bb1_cmp70_i = ((local_bb1__29_i & 32'hFFFFFF00) > 32'h80000000);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u12_stall_local;
wire local_bb1_var__u12;

assign local_bb1_var__u12 = ($signed((local_bb1__29_i & 32'hFFFFFF00)) < $signed(32'h0));

// This section implements an unregistered operation.
// 
wire local_bb1_cmp53_i_stall_local;
wire local_bb1_cmp53_i;

assign local_bb1_cmp53_i = ((local_bb1__31_i & 32'h3FF) > 32'h17D);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp63_i_stall_local;
wire local_bb1_cmp63_i;

assign local_bb1_cmp63_i = ((local_bb1__31_i & 32'h3FF) < 32'h80);

// This section implements an unregistered operation.
// 
wire local_bb1_sub_i_stall_local;
wire [31:0] local_bb1_sub_i;

assign local_bb1_sub_i = ((local_bb1__31_i & 32'h3FF) << 32'h17);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp65_not_i_stall_local;
wire local_bb1_cmp65_not_i;

assign local_bb1_cmp65_not_i = ((local_bb1__31_i & 32'h3FF) != 32'h7F);

// This section implements an unregistered operation.
// 
wire local_bb1_and68_i_stall_local;
wire [31:0] local_bb1_and68_i;

assign local_bb1_and68_i = ((local_bb1__27_i & 32'h1FFFFFF) & 32'h7FFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1_and74_i_stall_local;
wire [31:0] local_bb1_and74_i;

assign local_bb1_and74_i = ((local_bb1__27_i & 32'h1FFFFFF) & 32'h1);

// This section implements an unregistered operation.
// 
wire local_bb1_or57_i_stall_local;
wire local_bb1_or57_i;

assign local_bb1_or57_i = (rnode_161to164_bb1_var__u8_0_NO_SHIFT_REG | local_bb1_cmp53_i);

// This section implements an unregistered operation.
// 
wire local_bb1_and67_i_stall_local;
wire [31:0] local_bb1_and67_i;

assign local_bb1_and67_i = ((local_bb1_sub_i & 32'hFF800000) + 32'h40800000);

// This section implements an unregistered operation.
// 
wire local_bb1_tobool75_i_stall_local;
wire local_bb1_tobool75_i;

assign local_bb1_tobool75_i = ((local_bb1_and74_i & 32'h1) != 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_shl_i_stall_local;
wire [31:0] local_bb1_shl_i;

assign local_bb1_shl_i = ((local_bb1_and67_i & 32'hFF800000) & 32'h7F800000);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp63_i_valid_out;
wire local_bb1_cmp63_i_stall_in;
wire local_bb1_cmp65_not_i_valid_out;
wire local_bb1_cmp65_not_i_stall_in;
wire local_bb1_or57_i_valid_out;
wire local_bb1_or57_i_stall_in;
wire local_bb1_and68_i_valid_out;
wire local_bb1_and68_i_stall_in;
wire local_bb1_cmp70_i_valid_out;
wire local_bb1_cmp70_i_stall_in;
wire local_bb1_shl_i_valid_out;
wire local_bb1_shl_i_stall_in;
wire local_bb1__33_i_valid_out;
wire local_bb1__33_i_stall_in;
wire local_bb1__33_i_inputs_ready;
wire local_bb1__33_i_stall_local;
wire local_bb1__33_i;
wire [68:0] rci_rcnode_164to165_rc0_bb1_or57_i_0_reg_164;

assign local_bb1__33_i_inputs_ready = (rnode_161to164_bb1_add_i_0_valid_out_0_NO_SHIFT_REG & rnode_161to164_bb1_add_i_0_valid_out_1_NO_SHIFT_REG & rnode_161to164_bb1_add_i_0_valid_out_2_NO_SHIFT_REG & rnode_161to164_bb1_var__u8_0_valid_out_NO_SHIFT_REG & rnode_164to164_bb1_mul_i_i_0_valid_out_1_NO_SHIFT_REG & rnode_164to164_bb1_mul_i_i_0_valid_out_0_NO_SHIFT_REG);
assign local_bb1__33_i = (local_bb1_tobool75_i & local_bb1_var__u12);
assign local_bb1__33_i_stall_local = (local_bb1_cmp63_i_stall_in | local_bb1_cmp65_not_i_stall_in | local_bb1_or57_i_stall_in | local_bb1_and68_i_stall_in | local_bb1_cmp70_i_stall_in | local_bb1_shl_i_stall_in | local_bb1__33_i_stall_in);
assign local_bb1_cmp63_i_valid_out = local_bb1__33_i_inputs_ready;
assign local_bb1_cmp65_not_i_valid_out = local_bb1__33_i_inputs_ready;
assign local_bb1_or57_i_valid_out = local_bb1__33_i_inputs_ready;
assign local_bb1_and68_i_valid_out = local_bb1__33_i_inputs_ready;
assign local_bb1_cmp70_i_valid_out = local_bb1__33_i_inputs_ready;
assign local_bb1_shl_i_valid_out = local_bb1__33_i_inputs_ready;
assign local_bb1__33_i_valid_out = local_bb1__33_i_inputs_ready;
assign rnode_161to164_bb1_add_i_0_stall_in_0_NO_SHIFT_REG = (local_bb1__33_i_stall_local | ~(local_bb1__33_i_inputs_ready));
assign rnode_161to164_bb1_add_i_0_stall_in_1_NO_SHIFT_REG = (local_bb1__33_i_stall_local | ~(local_bb1__33_i_inputs_ready));
assign rnode_161to164_bb1_add_i_0_stall_in_2_NO_SHIFT_REG = (local_bb1__33_i_stall_local | ~(local_bb1__33_i_inputs_ready));
assign rnode_161to164_bb1_var__u8_0_stall_in_NO_SHIFT_REG = (local_bb1__33_i_stall_local | ~(local_bb1__33_i_inputs_ready));
assign rnode_164to164_bb1_mul_i_i_0_stall_in_1_NO_SHIFT_REG = (local_bb1__33_i_stall_local | ~(local_bb1__33_i_inputs_ready));
assign rnode_164to164_bb1_mul_i_i_0_stall_in_0_NO_SHIFT_REG = (local_bb1__33_i_stall_local | ~(local_bb1__33_i_inputs_ready));
assign rci_rcnode_164to165_rc0_bb1_or57_i_0_reg_164[0] = local_bb1_or57_i;
assign rci_rcnode_164to165_rc0_bb1_or57_i_0_reg_164[1] = local_bb1_cmp63_i;
assign rci_rcnode_164to165_rc0_bb1_or57_i_0_reg_164[2] = local_bb1_cmp65_not_i;
assign rci_rcnode_164to165_rc0_bb1_or57_i_0_reg_164[34:3] = (local_bb1_shl_i & 32'h7F800000);
assign rci_rcnode_164to165_rc0_bb1_or57_i_0_reg_164[66:35] = (local_bb1_and68_i & 32'h7FFFFF);
assign rci_rcnode_164to165_rc0_bb1_or57_i_0_reg_164[67] = local_bb1_cmp70_i;
assign rci_rcnode_164to165_rc0_bb1_or57_i_0_reg_164[68] = local_bb1__33_i;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rcnode_164to165_rc0_bb1_or57_i_0_valid_out_0_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_stall_in_0_NO_SHIFT_REG;
 logic [68:0] rcnode_164to165_rc0_bb1_or57_i_0_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_valid_out_1_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_stall_in_1_NO_SHIFT_REG;
 logic [68:0] rcnode_164to165_rc0_bb1_or57_i_1_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_valid_out_2_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_stall_in_2_NO_SHIFT_REG;
 logic [68:0] rcnode_164to165_rc0_bb1_or57_i_2_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_valid_out_3_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_stall_in_3_NO_SHIFT_REG;
 logic [68:0] rcnode_164to165_rc0_bb1_or57_i_3_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_valid_out_4_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_stall_in_4_NO_SHIFT_REG;
 logic [68:0] rcnode_164to165_rc0_bb1_or57_i_4_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_valid_out_5_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_stall_in_5_NO_SHIFT_REG;
 logic [68:0] rcnode_164to165_rc0_bb1_or57_i_5_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_reg_165_inputs_ready_NO_SHIFT_REG;
 logic [68:0] rcnode_164to165_rc0_bb1_or57_i_0_reg_165_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_valid_out_0_reg_165_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_stall_in_0_reg_165_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_stall_out_0_reg_165_IP_NO_SHIFT_REG;
 logic rcnode_164to165_rc0_bb1_or57_i_0_stall_out_0_reg_165_NO_SHIFT_REG;

acl_data_fifo rcnode_164to165_rc0_bb1_or57_i_0_reg_165_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rcnode_164to165_rc0_bb1_or57_i_0_reg_165_inputs_ready_NO_SHIFT_REG),
	.stall_in(rcnode_164to165_rc0_bb1_or57_i_0_stall_in_0_reg_165_NO_SHIFT_REG),
	.valid_out(rcnode_164to165_rc0_bb1_or57_i_0_valid_out_0_reg_165_NO_SHIFT_REG),
	.stall_out(rcnode_164to165_rc0_bb1_or57_i_0_stall_out_0_reg_165_IP_NO_SHIFT_REG),
	.data_in(rci_rcnode_164to165_rc0_bb1_or57_i_0_reg_164),
	.data_out(rcnode_164to165_rc0_bb1_or57_i_0_reg_165_NO_SHIFT_REG)
);

defparam rcnode_164to165_rc0_bb1_or57_i_0_reg_165_fifo.DEPTH = 1;
defparam rcnode_164to165_rc0_bb1_or57_i_0_reg_165_fifo.DATA_WIDTH = 69;
defparam rcnode_164to165_rc0_bb1_or57_i_0_reg_165_fifo.ALLOW_FULL_WRITE = 1;
defparam rcnode_164to165_rc0_bb1_or57_i_0_reg_165_fifo.IMPL = "ll_reg";

assign rcnode_164to165_rc0_bb1_or57_i_0_reg_165_inputs_ready_NO_SHIFT_REG = (local_bb1_or57_i_valid_out & local_bb1_cmp63_i_valid_out & local_bb1_cmp65_not_i_valid_out & local_bb1_shl_i_valid_out & local_bb1_and68_i_valid_out & local_bb1_cmp70_i_valid_out & local_bb1__33_i_valid_out);
assign rcnode_164to165_rc0_bb1_or57_i_0_stall_out_0_reg_165_NO_SHIFT_REG = (~(rcnode_164to165_rc0_bb1_or57_i_0_reg_165_inputs_ready_NO_SHIFT_REG) | rcnode_164to165_rc0_bb1_or57_i_0_stall_out_0_reg_165_IP_NO_SHIFT_REG);
assign local_bb1_or57_i_stall_in = rcnode_164to165_rc0_bb1_or57_i_0_stall_out_0_reg_165_NO_SHIFT_REG;
assign local_bb1_cmp63_i_stall_in = rcnode_164to165_rc0_bb1_or57_i_0_stall_out_0_reg_165_NO_SHIFT_REG;
assign local_bb1_cmp65_not_i_stall_in = rcnode_164to165_rc0_bb1_or57_i_0_stall_out_0_reg_165_NO_SHIFT_REG;
assign local_bb1_shl_i_stall_in = rcnode_164to165_rc0_bb1_or57_i_0_stall_out_0_reg_165_NO_SHIFT_REG;
assign local_bb1_and68_i_stall_in = rcnode_164to165_rc0_bb1_or57_i_0_stall_out_0_reg_165_NO_SHIFT_REG;
assign local_bb1_cmp70_i_stall_in = rcnode_164to165_rc0_bb1_or57_i_0_stall_out_0_reg_165_NO_SHIFT_REG;
assign local_bb1__33_i_stall_in = rcnode_164to165_rc0_bb1_or57_i_0_stall_out_0_reg_165_NO_SHIFT_REG;
assign rcnode_164to165_rc0_bb1_or57_i_0_stall_in_0_reg_165_NO_SHIFT_REG = (rcnode_164to165_rc0_bb1_or57_i_0_stall_in_0_NO_SHIFT_REG | rcnode_164to165_rc0_bb1_or57_i_0_stall_in_1_NO_SHIFT_REG | rcnode_164to165_rc0_bb1_or57_i_0_stall_in_2_NO_SHIFT_REG | rcnode_164to165_rc0_bb1_or57_i_0_stall_in_3_NO_SHIFT_REG | rcnode_164to165_rc0_bb1_or57_i_0_stall_in_4_NO_SHIFT_REG | rcnode_164to165_rc0_bb1_or57_i_0_stall_in_5_NO_SHIFT_REG);
assign rcnode_164to165_rc0_bb1_or57_i_0_valid_out_0_NO_SHIFT_REG = rcnode_164to165_rc0_bb1_or57_i_0_valid_out_0_reg_165_NO_SHIFT_REG;
assign rcnode_164to165_rc0_bb1_or57_i_0_valid_out_1_NO_SHIFT_REG = rcnode_164to165_rc0_bb1_or57_i_0_valid_out_0_reg_165_NO_SHIFT_REG;
assign rcnode_164to165_rc0_bb1_or57_i_0_valid_out_2_NO_SHIFT_REG = rcnode_164to165_rc0_bb1_or57_i_0_valid_out_0_reg_165_NO_SHIFT_REG;
assign rcnode_164to165_rc0_bb1_or57_i_0_valid_out_3_NO_SHIFT_REG = rcnode_164to165_rc0_bb1_or57_i_0_valid_out_0_reg_165_NO_SHIFT_REG;
assign rcnode_164to165_rc0_bb1_or57_i_0_valid_out_4_NO_SHIFT_REG = rcnode_164to165_rc0_bb1_or57_i_0_valid_out_0_reg_165_NO_SHIFT_REG;
assign rcnode_164to165_rc0_bb1_or57_i_0_valid_out_5_NO_SHIFT_REG = rcnode_164to165_rc0_bb1_or57_i_0_valid_out_0_reg_165_NO_SHIFT_REG;
assign rcnode_164to165_rc0_bb1_or57_i_0_NO_SHIFT_REG = rcnode_164to165_rc0_bb1_or57_i_0_reg_165_NO_SHIFT_REG;
assign rcnode_164to165_rc0_bb1_or57_i_1_NO_SHIFT_REG = rcnode_164to165_rc0_bb1_or57_i_0_reg_165_NO_SHIFT_REG;
assign rcnode_164to165_rc0_bb1_or57_i_2_NO_SHIFT_REG = rcnode_164to165_rc0_bb1_or57_i_0_reg_165_NO_SHIFT_REG;
assign rcnode_164to165_rc0_bb1_or57_i_3_NO_SHIFT_REG = rcnode_164to165_rc0_bb1_or57_i_0_reg_165_NO_SHIFT_REG;
assign rcnode_164to165_rc0_bb1_or57_i_4_NO_SHIFT_REG = rcnode_164to165_rc0_bb1_or57_i_0_reg_165_NO_SHIFT_REG;
assign rcnode_164to165_rc0_bb1_or57_i_5_NO_SHIFT_REG = rcnode_164to165_rc0_bb1_or57_i_0_reg_165_NO_SHIFT_REG;

// This section implements an unregistered operation.
// 
wire local_bb1_cond95_i_stall_local;
wire [31:0] local_bb1_cond95_i;

assign local_bb1_cond95_i = (rcnode_164to165_rc0_bb1_or57_i_0_NO_SHIFT_REG[0] ? 32'h7F800000 : 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_or69_i_stall_local;
wire [31:0] local_bb1_or69_i;

assign local_bb1_or69_i = ((rcnode_164to165_rc0_bb1_or57_i_0_NO_SHIFT_REG[34:3] & 32'h7F800000) | (rcnode_164to165_rc0_bb1_or57_i_0_NO_SHIFT_REG[66:35] & 32'h7FFFFF));

// This section implements an unregistered operation.
// 
wire local_bb1__34_i_stall_local;
wire local_bb1__34_i;

assign local_bb1__34_i = (rcnode_164to165_rc0_bb1_or57_i_0_NO_SHIFT_REG[67] | rcnode_164to165_rc0_bb1_or57_i_0_NO_SHIFT_REG[68]);

// This section implements an unregistered operation.
// 
wire local_bb1_cond_i_stall_local;
wire [31:0] local_bb1_cond_i;

assign local_bb1_cond_i[31:1] = 31'h0;
assign local_bb1_cond_i[0] = local_bb1__34_i;

// This section implements an unregistered operation.
// 
wire local_bb1_add78_i_stall_local;
wire [31:0] local_bb1_add78_i;

assign local_bb1_add78_i = ((local_bb1_cond_i & 32'h1) + (local_bb1_or69_i & 32'h7FFFFFFF));

// This section implements an unregistered operation.
// 
wire local_bb1_and79_i_stall_local;
wire [31:0] local_bb1_and79_i;

assign local_bb1_and79_i = (local_bb1_add78_i & 32'h7FFFFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1_and81_i_stall_local;
wire [31:0] local_bb1_and81_i;

assign local_bb1_and81_i = (local_bb1_add78_i & 32'h800000);

// This section implements an unregistered operation.
// 
wire local_bb1_or80_i_stall_local;
wire [31:0] local_bb1_or80_i;

assign local_bb1_or80_i = ((local_bb1_and79_i & 32'h7FFFFFFF) | (local_bb1_and4_i & 32'h80000000));

// This section implements an unregistered operation.
// 
wire local_bb1_cmp82_i_stall_local;
wire local_bb1_cmp82_i;

assign local_bb1_cmp82_i = ((local_bb1_and81_i & 32'h800000) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_brmerge16_i_stall_local;
wire local_bb1_brmerge16_i;

assign local_bb1_brmerge16_i = (local_bb1_cmp82_i | rcnode_164to165_rc0_bb1_or57_i_0_NO_SHIFT_REG[2]);

// This section implements an unregistered operation.
// 
wire local_bb1_tobool87_i_stall_local;
wire local_bb1_tobool87_i;

assign local_bb1_tobool87_i = (local_bb1_brmerge16_i & rcnode_164to165_rc0_bb1_or57_i_0_NO_SHIFT_REG[1]);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_5_i_stall_local;
wire local_bb1_reduction_5_i;

assign local_bb1_reduction_5_i = (local_bb1_tobool87_i | rnode_161to165_bb1_reduction_3_i_0_NO_SHIFT_REG);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_6_i_stall_local;
wire local_bb1_reduction_6_i;

assign local_bb1_reduction_6_i = (rcnode_164to165_rc0_bb1_or57_i_0_NO_SHIFT_REG[0] | local_bb1_reduction_5_i);

// This section implements an unregistered operation.
// 
wire local_bb1_and4__i_stall_local;
wire [31:0] local_bb1_and4__i;

assign local_bb1_and4__i = (local_bb1_reduction_6_i ? (local_bb1_and4_i & 32'h80000000) : 32'hFFFFFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1_and93_i_stall_local;
wire [31:0] local_bb1_and93_i;

assign local_bb1_and93_i = (local_bb1_and4__i & local_bb1_or80_i);

// This section implements an unregistered operation.
// 
wire local_bb1_or96_i_stall_local;
wire [31:0] local_bb1_or96_i;

assign local_bb1_or96_i = (local_bb1_and93_i | (local_bb1_cond95_i & 32'h7F800000));

// This section implements an unregistered operation.
// 
wire local_bb1_var__u13_stall_local;
wire [31:0] local_bb1_var__u13;

assign local_bb1_var__u13 = local_bb1_or96_i;

// This section implements an unregistered operation.
// 
wire local_bb1_var__u14_valid_out;
wire local_bb1_var__u14_stall_in;
wire local_bb1_var__u14_inputs_ready;
wire local_bb1_var__u14_stall_local;
wire [31:0] local_bb1_var__u14;

assign local_bb1_var__u14_inputs_ready = (rnode_161to165_bb1_xor_i_0_valid_out_NO_SHIFT_REG & rnode_161to165_bb1_reduction_3_i_0_valid_out_NO_SHIFT_REG & rcnode_164to165_rc0_bb1_or57_i_0_valid_out_0_NO_SHIFT_REG & rnode_161to165_bb1__23_i_0_valid_out_NO_SHIFT_REG & rcnode_164to165_rc0_bb1_or57_i_0_valid_out_1_NO_SHIFT_REG & rcnode_164to165_rc0_bb1_or57_i_0_valid_out_2_NO_SHIFT_REG & rcnode_164to165_rc0_bb1_or57_i_0_valid_out_3_NO_SHIFT_REG & rcnode_164to165_rc0_bb1_or57_i_0_valid_out_4_NO_SHIFT_REG & rcnode_164to165_rc0_bb1_or57_i_0_valid_out_5_NO_SHIFT_REG);
assign local_bb1_var__u14 = (rnode_161to165_bb1__23_i_0_NO_SHIFT_REG ? 32'h7FC00000 : local_bb1_var__u13);
assign local_bb1_var__u14_valid_out = local_bb1_var__u14_inputs_ready;
assign local_bb1_var__u14_stall_local = local_bb1_var__u14_stall_in;
assign rnode_161to165_bb1_xor_i_0_stall_in_NO_SHIFT_REG = (local_bb1_var__u14_stall_local | ~(local_bb1_var__u14_inputs_ready));
assign rnode_161to165_bb1_reduction_3_i_0_stall_in_NO_SHIFT_REG = (local_bb1_var__u14_stall_local | ~(local_bb1_var__u14_inputs_ready));
assign rcnode_164to165_rc0_bb1_or57_i_0_stall_in_0_NO_SHIFT_REG = (local_bb1_var__u14_stall_local | ~(local_bb1_var__u14_inputs_ready));
assign rnode_161to165_bb1__23_i_0_stall_in_NO_SHIFT_REG = (local_bb1_var__u14_stall_local | ~(local_bb1_var__u14_inputs_ready));
assign rcnode_164to165_rc0_bb1_or57_i_0_stall_in_1_NO_SHIFT_REG = (local_bb1_var__u14_stall_local | ~(local_bb1_var__u14_inputs_ready));
assign rcnode_164to165_rc0_bb1_or57_i_0_stall_in_2_NO_SHIFT_REG = (local_bb1_var__u14_stall_local | ~(local_bb1_var__u14_inputs_ready));
assign rcnode_164to165_rc0_bb1_or57_i_0_stall_in_3_NO_SHIFT_REG = (local_bb1_var__u14_stall_local | ~(local_bb1_var__u14_inputs_ready));
assign rcnode_164to165_rc0_bb1_or57_i_0_stall_in_4_NO_SHIFT_REG = (local_bb1_var__u14_stall_local | ~(local_bb1_var__u14_inputs_ready));
assign rcnode_164to165_rc0_bb1_or57_i_0_stall_in_5_NO_SHIFT_REG = (local_bb1_var__u14_stall_local | ~(local_bb1_var__u14_inputs_ready));

// This section implements a staging register.
// 
wire rstag_165to165_bb1_var__u14_valid_out;
wire rstag_165to165_bb1_var__u14_stall_in;
wire rstag_165to165_bb1_var__u14_inputs_ready;
wire rstag_165to165_bb1_var__u14_stall_local;
 reg rstag_165to165_bb1_var__u14_staging_valid_NO_SHIFT_REG;
wire rstag_165to165_bb1_var__u14_combined_valid;
 reg [31:0] rstag_165to165_bb1_var__u14_staging_reg_NO_SHIFT_REG;
wire [31:0] rstag_165to165_bb1_var__u14;

assign rstag_165to165_bb1_var__u14_inputs_ready = local_bb1_var__u14_valid_out;
assign rstag_165to165_bb1_var__u14 = (rstag_165to165_bb1_var__u14_staging_valid_NO_SHIFT_REG ? rstag_165to165_bb1_var__u14_staging_reg_NO_SHIFT_REG : local_bb1_var__u14);
assign rstag_165to165_bb1_var__u14_combined_valid = (rstag_165to165_bb1_var__u14_staging_valid_NO_SHIFT_REG | rstag_165to165_bb1_var__u14_inputs_ready);
assign rstag_165to165_bb1_var__u14_valid_out = rstag_165to165_bb1_var__u14_combined_valid;
assign rstag_165to165_bb1_var__u14_stall_local = rstag_165to165_bb1_var__u14_stall_in;
assign local_bb1_var__u14_stall_in = (|rstag_165to165_bb1_var__u14_staging_valid_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		rstag_165to165_bb1_var__u14_staging_valid_NO_SHIFT_REG <= 1'b0;
		rstag_165to165_bb1_var__u14_staging_reg_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (rstag_165to165_bb1_var__u14_stall_local)
		begin
			if (~(rstag_165to165_bb1_var__u14_staging_valid_NO_SHIFT_REG))
			begin
				rstag_165to165_bb1_var__u14_staging_valid_NO_SHIFT_REG <= rstag_165to165_bb1_var__u14_inputs_ready;
			end
		end
		else
		begin
			rstag_165to165_bb1_var__u14_staging_valid_NO_SHIFT_REG <= 1'b0;
		end
		if (~(rstag_165to165_bb1_var__u14_staging_valid_NO_SHIFT_REG))
		begin
			rstag_165to165_bb1_var__u14_staging_reg_NO_SHIFT_REG <= local_bb1_var__u14;
		end
	end
end


// This section implements a registered operation.
// 
wire local_bb1_st__inputs_ready;
 reg local_bb1_st__valid_out_NO_SHIFT_REG;
wire local_bb1_st__stall_in;
wire local_bb1_st__output_regs_ready;
wire local_bb1_st__fu_stall_out;
wire local_bb1_st__fu_valid_out;
wire local_bb1_st__causedstall;

lsu_top lsu_local_bb1_st_ (
	.clock(clock),
	.clock2x(clock2x),
	.resetn(resetn),
	.flush(start),
	.stream_base_addr(),
	.stream_size(),
	.stream_reset(),
	.o_stall(local_bb1_st__fu_stall_out),
	.i_valid(local_bb1_st__inputs_ready),
	.i_address((rnode_164to165_bb1_arrayidx5_RM_0_NO_SHIFT_REG & 64'hFFFFFFFFFFFFFFFC)),
	.i_writedata(rstag_165to165_bb1_var__u14),
	.i_cmpdata(),
	.i_predicate(1'b0),
	.i_bitwiseor(64'h0),
	.i_byteenable(),
	.i_stall(~(local_bb1_st__output_regs_ready)),
	.o_valid(local_bb1_st__fu_valid_out),
	.o_readdata(),
	.o_input_fifo_depth(),
	.o_writeack(),
	.i_atomic_op(3'h0),
	.o_active(local_bb1_st__active),
	.avm_address(avm_local_bb1_st__address),
	.avm_read(avm_local_bb1_st__read),
	.avm_enable(avm_local_bb1_st__enable),
	.avm_readdata(avm_local_bb1_st__readdata),
	.avm_write(avm_local_bb1_st__write),
	.avm_writeack(avm_local_bb1_st__writeack),
	.avm_burstcount(avm_local_bb1_st__burstcount),
	.avm_writedata(avm_local_bb1_st__writedata),
	.avm_byteenable(avm_local_bb1_st__byteenable),
	.avm_waitrequest(avm_local_bb1_st__waitrequest),
	.avm_readdatavalid(avm_local_bb1_st__readdatavalid),
	.profile_bw(),
	.profile_bw_incr(),
	.profile_total_ivalid(),
	.profile_total_req(),
	.profile_i_stall_count(),
	.profile_o_stall_count(),
	.profile_avm_readwrite_count(),
	.profile_avm_burstcount_total(),
	.profile_avm_burstcount_total_incr(),
	.profile_req_cache_hit_count(),
	.profile_extra_unaligned_reqs(),
	.profile_avm_stall()
);

defparam lsu_local_bb1_st_.AWIDTH = 31;
defparam lsu_local_bb1_st_.WIDTH_BYTES = 4;
defparam lsu_local_bb1_st_.MWIDTH_BYTES = 32;
defparam lsu_local_bb1_st_.WRITEDATAWIDTH_BYTES = 32;
defparam lsu_local_bb1_st_.ALIGNMENT_BYTES = 4;
defparam lsu_local_bb1_st_.READ = 0;
defparam lsu_local_bb1_st_.ATOMIC = 0;
defparam lsu_local_bb1_st_.WIDTH = 32;
defparam lsu_local_bb1_st_.MWIDTH = 256;
defparam lsu_local_bb1_st_.ATOMIC_WIDTH = 3;
defparam lsu_local_bb1_st_.BURSTCOUNT_WIDTH = 5;
defparam lsu_local_bb1_st_.KERNEL_SIDE_MEM_LATENCY = 160;
defparam lsu_local_bb1_st_.MEMORY_SIDE_MEM_LATENCY = 10;
defparam lsu_local_bb1_st_.USE_WRITE_ACK = 1;
defparam lsu_local_bb1_st_.ENABLE_BANKED_MEMORY = 0;
defparam lsu_local_bb1_st_.ABITS_PER_LMEM_BANK = 0;
defparam lsu_local_bb1_st_.NUMBER_BANKS = 1;
defparam lsu_local_bb1_st_.LMEM_ADDR_PERMUTATION_STYLE = 0;
defparam lsu_local_bb1_st_.INTENDED_DEVICE_FAMILY = "Cyclone V";
defparam lsu_local_bb1_st_.USEINPUTFIFO = 0;
defparam lsu_local_bb1_st_.USECACHING = 0;
defparam lsu_local_bb1_st_.USEOUTPUTFIFO = 1;
defparam lsu_local_bb1_st_.FORCE_NOP_SUPPORT = 0;
defparam lsu_local_bb1_st_.ADDRSPACE = 1;
defparam lsu_local_bb1_st_.STYLE = "BURST-COALESCED";
defparam lsu_local_bb1_st_.USE_BYTE_EN = 0;

assign local_bb1_st__inputs_ready = (rnode_164to165_bb1_arrayidx5_RM_0_valid_out_NO_SHIFT_REG & rstag_165to165_bb1_var__u14_valid_out);
assign local_bb1_st__output_regs_ready = (&(~(local_bb1_st__valid_out_NO_SHIFT_REG) | ~(local_bb1_st__stall_in)));
assign rnode_164to165_bb1_arrayidx5_RM_0_stall_in_NO_SHIFT_REG = (local_bb1_st__fu_stall_out | ~(local_bb1_st__inputs_ready));
assign rstag_165to165_bb1_var__u14_stall_in = (local_bb1_st__fu_stall_out | ~(local_bb1_st__inputs_ready));
assign local_bb1_st__causedstall = (local_bb1_st__inputs_ready && (local_bb1_st__fu_stall_out && !(~(local_bb1_st__output_regs_ready))));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_st__valid_out_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (local_bb1_st__output_regs_ready)
		begin
			local_bb1_st__valid_out_NO_SHIFT_REG <= local_bb1_st__fu_valid_out;
		end
		else
		begin
			if (~(local_bb1_st__stall_in))
			begin
				local_bb1_st__valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end


// This section implements a staging register.
// 
wire rstag_325to325_bb1_st__valid_out;
wire rstag_325to325_bb1_st__stall_in;
wire rstag_325to325_bb1_st__inputs_ready;
wire rstag_325to325_bb1_st__stall_local;
 reg rstag_325to325_bb1_st__staging_valid_NO_SHIFT_REG;
wire rstag_325to325_bb1_st__combined_valid;

assign rstag_325to325_bb1_st__inputs_ready = local_bb1_st__valid_out_NO_SHIFT_REG;
assign rstag_325to325_bb1_st__combined_valid = (rstag_325to325_bb1_st__staging_valid_NO_SHIFT_REG | rstag_325to325_bb1_st__inputs_ready);
assign rstag_325to325_bb1_st__valid_out = rstag_325to325_bb1_st__combined_valid;
assign rstag_325to325_bb1_st__stall_local = rstag_325to325_bb1_st__stall_in;
assign local_bb1_st__stall_in = (|rstag_325to325_bb1_st__staging_valid_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		rstag_325to325_bb1_st__staging_valid_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (rstag_325to325_bb1_st__stall_local)
		begin
			if (~(rstag_325to325_bb1_st__staging_valid_NO_SHIFT_REG))
			begin
				rstag_325to325_bb1_st__staging_valid_NO_SHIFT_REG <= rstag_325to325_bb1_st__inputs_ready;
			end
		end
		else
		begin
			rstag_325to325_bb1_st__staging_valid_NO_SHIFT_REG <= 1'b0;
		end
	end
end


// This section describes the behaviour of the BRANCH node.
wire branch_var__inputs_ready;
 reg branch_node_valid_out_0_NO_SHIFT_REG;
 reg branch_compare_result_NO_SHIFT_REG;
wire branch_var__output_regs_ready;
wire combined_branch_stall_in_signal;
 reg [31:0] lvb_bb1_inc_0_reg_NO_SHIFT_REG;
 reg [31:0] lvb_input_global_id_0_0_reg_NO_SHIFT_REG;

assign branch_var__inputs_ready = (local_bb1_exitcond_valid_out & rcnode_324to325_rc0_bb1_inc_0_valid_out_1_NO_SHIFT_REG & rstag_325to325_bb1_st__valid_out);
assign branch_var__output_regs_ready = (~(branch_node_valid_out_0_NO_SHIFT_REG) | (((branch_compare_result_NO_SHIFT_REG != 1'b1) & ~(stall_in_1)) | (~((branch_compare_result_NO_SHIFT_REG != 1'b1)) & ~(stall_in_0))));
assign local_bb1_exitcond_stall_in = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign rcnode_324to325_rc0_bb1_inc_0_stall_in_1_NO_SHIFT_REG = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign rstag_325to325_bb1_st__stall_in = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign lvb_bb1_inc_0 = lvb_bb1_inc_0_reg_NO_SHIFT_REG;
assign lvb_bb1_inc_1 = lvb_bb1_inc_0_reg_NO_SHIFT_REG;
assign lvb_input_global_id_0_0 = lvb_input_global_id_0_0_reg_NO_SHIFT_REG;
assign lvb_input_global_id_0_1 = lvb_input_global_id_0_0_reg_NO_SHIFT_REG;
assign valid_out_0 = (~((branch_compare_result_NO_SHIFT_REG != 1'b1)) & branch_node_valid_out_0_NO_SHIFT_REG);
assign valid_out_1 = ((branch_compare_result_NO_SHIFT_REG != 1'b1) & branch_node_valid_out_0_NO_SHIFT_REG);
assign combined_branch_stall_in_signal = ((((branch_compare_result_NO_SHIFT_REG != 1'b1) & branch_node_valid_out_0_NO_SHIFT_REG) & stall_in_1) | ((~((branch_compare_result_NO_SHIFT_REG != 1'b1)) & branch_node_valid_out_0_NO_SHIFT_REG) & stall_in_0));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		branch_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
		lvb_bb1_inc_0_reg_NO_SHIFT_REG <= 'x;
		lvb_input_global_id_0_0_reg_NO_SHIFT_REG <= 'x;
		branch_compare_result_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (branch_var__output_regs_ready)
		begin
			branch_node_valid_out_0_NO_SHIFT_REG <= branch_var__inputs_ready;
			lvb_bb1_inc_0_reg_NO_SHIFT_REG <= (rcnode_324to325_rc0_bb1_inc_0_NO_SHIFT_REG[31:0] & 32'h7FF);
			lvb_input_global_id_0_0_reg_NO_SHIFT_REG <= rcnode_324to325_rc0_bb1_inc_0_NO_SHIFT_REG[63:32];
			branch_compare_result_NO_SHIFT_REG <= local_bb1_exitcond;
		end
		else
		begin
			if (~(combined_branch_stall_in_signal))
			begin
				branch_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end


endmodule

//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////

// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module float_mult_basic_block_2
	(
		input 		clock,
		input 		resetn,
		input 		valid_in,
		output 		stall_out,
		output 		valid_out,
		input 		stall_in,
		input [31:0] 		workgroup_size,
		input 		start
	);


// Values used for debugging.  These are swept away by synthesis.
wire _entry;
wire _exit;
 reg [31:0] _num_entry_NO_SHIFT_REG;
 reg [31:0] _num_exit_NO_SHIFT_REG;
wire [31:0] _num_live;

assign _entry = ((&valid_in) & ~((|stall_out)));
assign _exit = ((&valid_out) & ~((|stall_in)));
assign _num_live = (_num_entry_NO_SHIFT_REG - _num_exit_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		_num_entry_NO_SHIFT_REG <= 32'h0;
		_num_exit_NO_SHIFT_REG <= 32'h0;
	end
	else
	begin
		if (_entry)
		begin
			_num_entry_NO_SHIFT_REG <= (_num_entry_NO_SHIFT_REG + 2'h1);
		end
		if (_exit)
		begin
			_num_exit_NO_SHIFT_REG <= (_num_exit_NO_SHIFT_REG + 2'h1);
		end
	end
end



// This section defines the behaviour of the MERGE node
wire merge_node_stall_in;
 reg merge_node_valid_out_NO_SHIFT_REG;
wire merge_stalled_by_successors;
 reg merge_block_selector_NO_SHIFT_REG;
 reg merge_node_valid_in_staging_reg_NO_SHIFT_REG;
 reg is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
 reg invariant_valid_NO_SHIFT_REG;

assign merge_stalled_by_successors = (|(merge_node_stall_in & merge_node_valid_out_NO_SHIFT_REG));
assign stall_out = merge_node_valid_in_staging_reg_NO_SHIFT_REG;

always @(*)
begin
	if ((merge_node_valid_in_staging_reg_NO_SHIFT_REG | valid_in))
	begin
		merge_block_selector_NO_SHIFT_REG = 1'b0;
		is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b1;
	end
	else
	begin
		merge_block_selector_NO_SHIFT_REG = 1'b0;
		is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b0;
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (((merge_block_selector_NO_SHIFT_REG != 1'b0) | merge_stalled_by_successors))
		begin
			if (~(merge_node_valid_in_staging_reg_NO_SHIFT_REG))
			begin
				merge_node_valid_in_staging_reg_NO_SHIFT_REG <= valid_in;
			end
		end
		else
		begin
			merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
		end
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		merge_node_valid_out_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (~(merge_stalled_by_successors))
		begin
			merge_node_valid_out_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
		end
		else
		begin
			if (~(merge_node_stall_in))
			begin
				merge_node_valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		invariant_valid_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		invariant_valid_NO_SHIFT_REG <= (~(start) & (invariant_valid_NO_SHIFT_REG | is_merge_data_to_local_regs_valid_NO_SHIFT_REG));
	end
end


// This section describes the behaviour of the BRANCH node.
wire branch_var__inputs_ready;
wire branch_var__output_regs_ready;

assign branch_var__inputs_ready = merge_node_valid_out_NO_SHIFT_REG;
assign branch_var__output_regs_ready = ~(stall_in);
assign merge_node_stall_in = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign valid_out = branch_var__inputs_ready;

endmodule

//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////

// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module float_mult_function
	(
		input 		clock,
		input 		resetn,
		input [31:0] 		input_global_id_0,
		output 		stall_out,
		input 		valid_in,
		output 		valid_out,
		input 		stall_in,
		input [31:0] 		workgroup_size,
		output 		avm_local_bb1_ld__enable,
		input [255:0] 		avm_local_bb1_ld__readdata,
		input 		avm_local_bb1_ld__readdatavalid,
		input 		avm_local_bb1_ld__waitrequest,
		output [30:0] 		avm_local_bb1_ld__address,
		output 		avm_local_bb1_ld__read,
		output 		avm_local_bb1_ld__write,
		input 		avm_local_bb1_ld__writeack,
		output [255:0] 		avm_local_bb1_ld__writedata,
		output [31:0] 		avm_local_bb1_ld__byteenable,
		output [4:0] 		avm_local_bb1_ld__burstcount,
		output 		avm_local_bb1_ld__u0_enable,
		input [255:0] 		avm_local_bb1_ld__u0_readdata,
		input 		avm_local_bb1_ld__u0_readdatavalid,
		input 		avm_local_bb1_ld__u0_waitrequest,
		output [30:0] 		avm_local_bb1_ld__u0_address,
		output 		avm_local_bb1_ld__u0_read,
		output 		avm_local_bb1_ld__u0_write,
		input 		avm_local_bb1_ld__u0_writeack,
		output [255:0] 		avm_local_bb1_ld__u0_writedata,
		output [31:0] 		avm_local_bb1_ld__u0_byteenable,
		output [4:0] 		avm_local_bb1_ld__u0_burstcount,
		output 		avm_local_bb1_st__enable,
		input [255:0] 		avm_local_bb1_st__readdata,
		input 		avm_local_bb1_st__readdatavalid,
		input 		avm_local_bb1_st__waitrequest,
		output [30:0] 		avm_local_bb1_st__address,
		output 		avm_local_bb1_st__read,
		output 		avm_local_bb1_st__write,
		input 		avm_local_bb1_st__writeack,
		output [255:0] 		avm_local_bb1_st__writedata,
		output [31:0] 		avm_local_bb1_st__byteenable,
		output [4:0] 		avm_local_bb1_st__burstcount,
		input 		start,
		input 		clock2x,
		input [63:0] 		input_x,
		input [63:0] 		input_y,
		input [63:0] 		input_z,
		output reg 		has_a_write_pending,
		output reg 		has_a_lsu_active
	);


wire [31:0] cur_cycle;
wire bb_0_stall_out;
wire bb_0_valid_out;
wire [31:0] bb_0_lvb_input_global_id_0;
wire bb_1_stall_out_0;
wire bb_1_stall_out_1;
wire bb_1_valid_out_0;
wire [31:0] bb_1_lvb_bb1_inc_0;
wire [31:0] bb_1_lvb_input_global_id_0_0;
wire bb_1_valid_out_1;
wire [31:0] bb_1_lvb_bb1_inc_1;
wire [31:0] bb_1_lvb_input_global_id_0_1;
wire bb_1_local_bb1_ld__active;
wire bb_1_local_bb1_ld__u0_active;
wire bb_1_local_bb1_st__active;
wire bb_2_stall_out;
wire bb_2_valid_out;
wire loop_limiter_0_stall_out;
wire loop_limiter_0_valid_out;
wire writes_pending;
wire [2:0] lsus_active;

float_mult_basic_block_0 float_mult_basic_block_0 (
	.clock(clock),
	.resetn(resetn),
	.valid_in(valid_in),
	.stall_out(bb_0_stall_out),
	.input_global_id_0(input_global_id_0),
	.valid_out(bb_0_valid_out),
	.stall_in(loop_limiter_0_stall_out),
	.lvb_input_global_id_0(bb_0_lvb_input_global_id_0),
	.workgroup_size(workgroup_size),
	.start(start)
);


float_mult_basic_block_1 float_mult_basic_block_1 (
	.clock(clock),
	.resetn(resetn),
	.input_x(input_x),
	.input_y(input_y),
	.input_z(input_z),
	.valid_in_0(bb_1_valid_out_1),
	.stall_out_0(bb_1_stall_out_0),
	.input_t_01_0(bb_1_lvb_bb1_inc_1),
	.input_global_id_0_0(bb_1_lvb_input_global_id_0_1),
	.valid_in_1(loop_limiter_0_valid_out),
	.stall_out_1(bb_1_stall_out_1),
	.input_t_01_1(32'h0),
	.input_global_id_0_1(bb_0_lvb_input_global_id_0),
	.valid_out_0(bb_1_valid_out_0),
	.stall_in_0(bb_2_stall_out),
	.lvb_bb1_inc_0(bb_1_lvb_bb1_inc_0),
	.lvb_input_global_id_0_0(bb_1_lvb_input_global_id_0_0),
	.valid_out_1(bb_1_valid_out_1),
	.stall_in_1(bb_1_stall_out_0),
	.lvb_bb1_inc_1(bb_1_lvb_bb1_inc_1),
	.lvb_input_global_id_0_1(bb_1_lvb_input_global_id_0_1),
	.workgroup_size(workgroup_size),
	.start(start),
	.avm_local_bb1_ld__enable(avm_local_bb1_ld__enable),
	.avm_local_bb1_ld__readdata(avm_local_bb1_ld__readdata),
	.avm_local_bb1_ld__readdatavalid(avm_local_bb1_ld__readdatavalid),
	.avm_local_bb1_ld__waitrequest(avm_local_bb1_ld__waitrequest),
	.avm_local_bb1_ld__address(avm_local_bb1_ld__address),
	.avm_local_bb1_ld__read(avm_local_bb1_ld__read),
	.avm_local_bb1_ld__write(avm_local_bb1_ld__write),
	.avm_local_bb1_ld__writeack(avm_local_bb1_ld__writeack),
	.avm_local_bb1_ld__writedata(avm_local_bb1_ld__writedata),
	.avm_local_bb1_ld__byteenable(avm_local_bb1_ld__byteenable),
	.avm_local_bb1_ld__burstcount(avm_local_bb1_ld__burstcount),
	.local_bb1_ld__active(bb_1_local_bb1_ld__active),
	.clock2x(clock2x),
	.avm_local_bb1_ld__u0_enable(avm_local_bb1_ld__u0_enable),
	.avm_local_bb1_ld__u0_readdata(avm_local_bb1_ld__u0_readdata),
	.avm_local_bb1_ld__u0_readdatavalid(avm_local_bb1_ld__u0_readdatavalid),
	.avm_local_bb1_ld__u0_waitrequest(avm_local_bb1_ld__u0_waitrequest),
	.avm_local_bb1_ld__u0_address(avm_local_bb1_ld__u0_address),
	.avm_local_bb1_ld__u0_read(avm_local_bb1_ld__u0_read),
	.avm_local_bb1_ld__u0_write(avm_local_bb1_ld__u0_write),
	.avm_local_bb1_ld__u0_writeack(avm_local_bb1_ld__u0_writeack),
	.avm_local_bb1_ld__u0_writedata(avm_local_bb1_ld__u0_writedata),
	.avm_local_bb1_ld__u0_byteenable(avm_local_bb1_ld__u0_byteenable),
	.avm_local_bb1_ld__u0_burstcount(avm_local_bb1_ld__u0_burstcount),
	.local_bb1_ld__u0_active(bb_1_local_bb1_ld__u0_active),
	.avm_local_bb1_st__enable(avm_local_bb1_st__enable),
	.avm_local_bb1_st__readdata(avm_local_bb1_st__readdata),
	.avm_local_bb1_st__readdatavalid(avm_local_bb1_st__readdatavalid),
	.avm_local_bb1_st__waitrequest(avm_local_bb1_st__waitrequest),
	.avm_local_bb1_st__address(avm_local_bb1_st__address),
	.avm_local_bb1_st__read(avm_local_bb1_st__read),
	.avm_local_bb1_st__write(avm_local_bb1_st__write),
	.avm_local_bb1_st__writeack(avm_local_bb1_st__writeack),
	.avm_local_bb1_st__writedata(avm_local_bb1_st__writedata),
	.avm_local_bb1_st__byteenable(avm_local_bb1_st__byteenable),
	.avm_local_bb1_st__burstcount(avm_local_bb1_st__burstcount),
	.local_bb1_st__active(bb_1_local_bb1_st__active)
);


float_mult_basic_block_2 float_mult_basic_block_2 (
	.clock(clock),
	.resetn(resetn),
	.valid_in(bb_1_valid_out_0),
	.stall_out(bb_2_stall_out),
	.valid_out(bb_2_valid_out),
	.stall_in(stall_in),
	.workgroup_size(workgroup_size),
	.start(start)
);


acl_loop_limiter loop_limiter_0 (
	.clock(clock),
	.resetn(resetn),
	.i_valid(bb_0_valid_out),
	.i_stall(bb_1_stall_out_1),
	.i_valid_exit(bb_1_valid_out_0),
	.i_stall_exit(bb_2_stall_out),
	.o_valid(loop_limiter_0_valid_out),
	.o_stall(loop_limiter_0_stall_out)
);

defparam loop_limiter_0.ENTRY_WIDTH = 1;
defparam loop_limiter_0.EXIT_WIDTH = 1;
defparam loop_limiter_0.THRESHOLD = 326;

float_mult_sys_cycle_time system_cycle_time_module (
	.clock(clock),
	.resetn(resetn),
	.cur_cycle(cur_cycle)
);


assign valid_out = bb_2_valid_out;
assign stall_out = bb_0_stall_out;
assign writes_pending = bb_1_local_bb1_st__active;
assign lsus_active[0] = bb_1_local_bb1_ld__active;
assign lsus_active[1] = bb_1_local_bb1_ld__u0_active;
assign lsus_active[2] = bb_1_local_bb1_st__active;

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		has_a_write_pending <= 1'b0;
		has_a_lsu_active <= 1'b0;
	end
	else
	begin
		has_a_write_pending <= (|writes_pending);
		has_a_lsu_active <= (|lsus_active);
	end
end

endmodule

//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////

// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module float_mult_function_wrapper
	(
		input 		clock,
		input 		resetn,
		input 		clock2x,
		input 		local_router_hang,
		input 		avs_cra_enable,
		input 		avs_cra_read,
		input 		avs_cra_write,
		input [3:0] 		avs_cra_address,
		input [63:0] 		avs_cra_writedata,
		input [7:0] 		avs_cra_byteenable,
		output reg [63:0] 		avs_cra_readdata,
		output reg 		avs_cra_readdatavalid,
		output 		cra_irq,
		output 		avm_local_bb1_ld__inst0_enable,
		input [255:0] 		avm_local_bb1_ld__inst0_readdata,
		input 		avm_local_bb1_ld__inst0_readdatavalid,
		input 		avm_local_bb1_ld__inst0_waitrequest,
		output [30:0] 		avm_local_bb1_ld__inst0_address,
		output 		avm_local_bb1_ld__inst0_read,
		output 		avm_local_bb1_ld__inst0_write,
		input 		avm_local_bb1_ld__inst0_writeack,
		output [255:0] 		avm_local_bb1_ld__inst0_writedata,
		output [31:0] 		avm_local_bb1_ld__inst0_byteenable,
		output [4:0] 		avm_local_bb1_ld__inst0_burstcount,
		output 		avm_local_bb1_ld__u0_inst0_enable,
		input [255:0] 		avm_local_bb1_ld__u0_inst0_readdata,
		input 		avm_local_bb1_ld__u0_inst0_readdatavalid,
		input 		avm_local_bb1_ld__u0_inst0_waitrequest,
		output [30:0] 		avm_local_bb1_ld__u0_inst0_address,
		output 		avm_local_bb1_ld__u0_inst0_read,
		output 		avm_local_bb1_ld__u0_inst0_write,
		input 		avm_local_bb1_ld__u0_inst0_writeack,
		output [255:0] 		avm_local_bb1_ld__u0_inst0_writedata,
		output [31:0] 		avm_local_bb1_ld__u0_inst0_byteenable,
		output [4:0] 		avm_local_bb1_ld__u0_inst0_burstcount,
		output 		avm_local_bb1_st__inst0_enable,
		input [255:0] 		avm_local_bb1_st__inst0_readdata,
		input 		avm_local_bb1_st__inst0_readdatavalid,
		input 		avm_local_bb1_st__inst0_waitrequest,
		output [30:0] 		avm_local_bb1_st__inst0_address,
		output 		avm_local_bb1_st__inst0_read,
		output 		avm_local_bb1_st__inst0_write,
		input 		avm_local_bb1_st__inst0_writeack,
		output [255:0] 		avm_local_bb1_st__inst0_writedata,
		output [31:0] 		avm_local_bb1_st__inst0_byteenable,
		output [4:0] 		avm_local_bb1_st__inst0_burstcount
	);

// Responsible for interfacing a kernel with the outside world. It comprises a
// slave interface to specify the kernel arguments and retain kernel status. 

// This section of the wrapper implements the slave interface.
// twoXclock_consumer uses clock2x, even if nobody inside the kernel does. Keeps interface to acl_iface consistent for all kernels.
 reg start_NO_SHIFT_REG;
 reg started_NO_SHIFT_REG;
wire finish;
 reg [31:0] status_NO_SHIFT_REG;
wire has_a_write_pending;
wire has_a_lsu_active;
 reg [191:0] kernel_arguments_NO_SHIFT_REG;
 reg twoXclock_consumer_NO_SHIFT_REG /* synthesis  preserve  noprune  */;
 reg [31:0] workgroup_size_NO_SHIFT_REG;
 reg [31:0] global_size_NO_SHIFT_REG[2:0];
 reg [31:0] num_groups_NO_SHIFT_REG[2:0];
 reg [31:0] local_size_NO_SHIFT_REG[2:0];
 reg [31:0] work_dim_NO_SHIFT_REG;
 reg [31:0] global_offset_NO_SHIFT_REG[2:0];
 reg [63:0] profile_data_NO_SHIFT_REG;
 reg [31:0] profile_ctrl_NO_SHIFT_REG;
 reg [63:0] profile_start_cycle_NO_SHIFT_REG;
 reg [63:0] profile_stop_cycle_NO_SHIFT_REG;
wire dispatched_all_groups;
wire [31:0] group_id_tmp[2:0];
wire [31:0] global_id_base_out[2:0];
wire start_out;
wire [31:0] local_id[0:0][2:0];
wire [31:0] global_id[0:0][2:0];
wire [31:0] group_id[0:0][2:0];
wire iter_valid_in;
wire iter_stall_out;
wire stall_in;
wire stall_out;
wire valid_in;
wire valid_out;

always @(posedge clock2x or negedge resetn)
begin
	if (~(resetn))
	begin
		twoXclock_consumer_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		twoXclock_consumer_NO_SHIFT_REG <= 1'b1;
	end
end



// Work group dispatcher is responsible for issuing work-groups to id iterator(s)
acl_work_group_dispatcher group_dispatcher (
	.clock(clock),
	.resetn(resetn),
	.start(start_NO_SHIFT_REG),
	.num_groups(num_groups_NO_SHIFT_REG),
	.local_size(local_size_NO_SHIFT_REG),
	.stall_in(iter_stall_out),
	.valid_out(iter_valid_in),
	.group_id_out(group_id_tmp),
	.global_id_base_out(global_id_base_out),
	.start_out(start_out),
	.dispatched_all_groups(dispatched_all_groups)
);

defparam group_dispatcher.NUM_COPIES = 1;
defparam group_dispatcher.RUN_FOREVER = 0;


// This section of the wrapper implements an Avalon Slave Interface used to configure a kernel invocation.
// The few words words contain the status and the workgroup size registers.
// The remaining addressable space is reserved for kernel arguments.
 reg [63:0] cra_readdata_st1_NO_SHIFT_REG;
 reg [3:0] cra_addr_st1_NO_SHIFT_REG;
 reg cra_read_st1_NO_SHIFT_REG;
wire [63:0] bitenable;

assign bitenable[7:0] = (avs_cra_byteenable[0] ? 8'hFF : 8'h0);
assign bitenable[15:8] = (avs_cra_byteenable[1] ? 8'hFF : 8'h0);
assign bitenable[23:16] = (avs_cra_byteenable[2] ? 8'hFF : 8'h0);
assign bitenable[31:24] = (avs_cra_byteenable[3] ? 8'hFF : 8'h0);
assign bitenable[39:32] = (avs_cra_byteenable[4] ? 8'hFF : 8'h0);
assign bitenable[47:40] = (avs_cra_byteenable[5] ? 8'hFF : 8'h0);
assign bitenable[55:48] = (avs_cra_byteenable[6] ? 8'hFF : 8'h0);
assign bitenable[63:56] = (avs_cra_byteenable[7] ? 8'hFF : 8'h0);
assign cra_irq = (status_NO_SHIFT_REG[1] | status_NO_SHIFT_REG[3]);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		start_NO_SHIFT_REG <= 1'b0;
		started_NO_SHIFT_REG <= 1'b0;
		kernel_arguments_NO_SHIFT_REG <= 192'h0;
		status_NO_SHIFT_REG <= 32'h30000;
		profile_ctrl_NO_SHIFT_REG <= 32'h4;
		profile_start_cycle_NO_SHIFT_REG <= 64'h0;
		profile_stop_cycle_NO_SHIFT_REG <= 64'hFFFFFFFFFFFFFFFF;
		work_dim_NO_SHIFT_REG <= 32'h0;
		workgroup_size_NO_SHIFT_REG <= 32'h0;
		global_size_NO_SHIFT_REG[0] <= 32'h0;
		global_size_NO_SHIFT_REG[1] <= 32'h0;
		global_size_NO_SHIFT_REG[2] <= 32'h0;
		num_groups_NO_SHIFT_REG[0] <= 32'h0;
		num_groups_NO_SHIFT_REG[1] <= 32'h0;
		num_groups_NO_SHIFT_REG[2] <= 32'h0;
		local_size_NO_SHIFT_REG[0] <= 32'h0;
		local_size_NO_SHIFT_REG[1] <= 32'h0;
		local_size_NO_SHIFT_REG[2] <= 32'h0;
		global_offset_NO_SHIFT_REG[0] <= 32'h0;
		global_offset_NO_SHIFT_REG[1] <= 32'h0;
		global_offset_NO_SHIFT_REG[2] <= 32'h0;
	end
	else
	begin
		if (avs_cra_write)
		begin
			case (avs_cra_address)
				4'h0:
				begin
					status_NO_SHIFT_REG[31:16] <= 16'h3;
					status_NO_SHIFT_REG[15:0] <= ((status_NO_SHIFT_REG[15:0] & ~(bitenable[15:0])) | (avs_cra_writedata[15:0] & bitenable[15:0]));
				end

				4'h1:
				begin
					profile_ctrl_NO_SHIFT_REG <= ((profile_ctrl_NO_SHIFT_REG & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h3:
				begin
					profile_start_cycle_NO_SHIFT_REG[31:0] <= ((profile_start_cycle_NO_SHIFT_REG[31:0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					profile_start_cycle_NO_SHIFT_REG[63:32] <= ((profile_start_cycle_NO_SHIFT_REG[63:32] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h4:
				begin
					profile_stop_cycle_NO_SHIFT_REG[31:0] <= ((profile_stop_cycle_NO_SHIFT_REG[31:0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					profile_stop_cycle_NO_SHIFT_REG[63:32] <= ((profile_stop_cycle_NO_SHIFT_REG[63:32] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h5:
				begin
					work_dim_NO_SHIFT_REG <= ((work_dim_NO_SHIFT_REG & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					workgroup_size_NO_SHIFT_REG <= ((workgroup_size_NO_SHIFT_REG & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h6:
				begin
					global_size_NO_SHIFT_REG[0] <= ((global_size_NO_SHIFT_REG[0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					global_size_NO_SHIFT_REG[1] <= ((global_size_NO_SHIFT_REG[1] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h7:
				begin
					global_size_NO_SHIFT_REG[2] <= ((global_size_NO_SHIFT_REG[2] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					num_groups_NO_SHIFT_REG[0] <= ((num_groups_NO_SHIFT_REG[0] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h8:
				begin
					num_groups_NO_SHIFT_REG[1] <= ((num_groups_NO_SHIFT_REG[1] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					num_groups_NO_SHIFT_REG[2] <= ((num_groups_NO_SHIFT_REG[2] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h9:
				begin
					local_size_NO_SHIFT_REG[0] <= ((local_size_NO_SHIFT_REG[0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					local_size_NO_SHIFT_REG[1] <= ((local_size_NO_SHIFT_REG[1] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'hA:
				begin
					local_size_NO_SHIFT_REG[2] <= ((local_size_NO_SHIFT_REG[2] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					global_offset_NO_SHIFT_REG[0] <= ((global_offset_NO_SHIFT_REG[0] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'hB:
				begin
					global_offset_NO_SHIFT_REG[1] <= ((global_offset_NO_SHIFT_REG[1] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					global_offset_NO_SHIFT_REG[2] <= ((global_offset_NO_SHIFT_REG[2] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'hC:
				begin
					kernel_arguments_NO_SHIFT_REG[31:0] <= ((kernel_arguments_NO_SHIFT_REG[31:0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					kernel_arguments_NO_SHIFT_REG[63:32] <= ((kernel_arguments_NO_SHIFT_REG[63:32] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'hD:
				begin
					kernel_arguments_NO_SHIFT_REG[95:64] <= ((kernel_arguments_NO_SHIFT_REG[95:64] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					kernel_arguments_NO_SHIFT_REG[127:96] <= ((kernel_arguments_NO_SHIFT_REG[127:96] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'hE:
				begin
					kernel_arguments_NO_SHIFT_REG[159:128] <= ((kernel_arguments_NO_SHIFT_REG[159:128] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					kernel_arguments_NO_SHIFT_REG[191:160] <= ((kernel_arguments_NO_SHIFT_REG[191:160] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				default:
				begin
				end

			endcase
		end
		else
		begin
			if (status_NO_SHIFT_REG[0])
			begin
				start_NO_SHIFT_REG <= 1'b1;
			end
			if (start_NO_SHIFT_REG)
			begin
				status_NO_SHIFT_REG[0] <= 1'b0;
				started_NO_SHIFT_REG <= 1'b1;
			end
			if (started_NO_SHIFT_REG)
			begin
				start_NO_SHIFT_REG <= 1'b0;
			end
			if (finish)
			begin
				status_NO_SHIFT_REG[1] <= 1'b1;
				started_NO_SHIFT_REG <= 1'b0;
			end
		end
		status_NO_SHIFT_REG[11] <= 1'b0;
		status_NO_SHIFT_REG[12] <= (|has_a_lsu_active);
		status_NO_SHIFT_REG[13] <= (|has_a_write_pending);
		status_NO_SHIFT_REG[14] <= (|valid_in);
		status_NO_SHIFT_REG[15] <= started_NO_SHIFT_REG;
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		cra_read_st1_NO_SHIFT_REG <= 1'b0;
		cra_addr_st1_NO_SHIFT_REG <= 4'h0;
		cra_readdata_st1_NO_SHIFT_REG <= 64'h0;
	end
	else
	begin
		cra_read_st1_NO_SHIFT_REG <= avs_cra_read;
		cra_addr_st1_NO_SHIFT_REG <= avs_cra_address;
		case (avs_cra_address)
			4'h0:
			begin
				cra_readdata_st1_NO_SHIFT_REG[31:0] <= status_NO_SHIFT_REG;
				cra_readdata_st1_NO_SHIFT_REG[63:32] <= 32'h0;
			end

			4'h1:
			begin
				cra_readdata_st1_NO_SHIFT_REG[31:0] <= 'x;
				cra_readdata_st1_NO_SHIFT_REG[63:32] <= 32'h0;
			end

			4'h2:
			begin
				cra_readdata_st1_NO_SHIFT_REG[63:0] <= 64'h0;
			end

			4'h3:
			begin
				cra_readdata_st1_NO_SHIFT_REG[63:0] <= 64'h0;
			end

			4'h4:
			begin
				cra_readdata_st1_NO_SHIFT_REG[63:0] <= 64'h0;
			end

			default:
			begin
				cra_readdata_st1_NO_SHIFT_REG <= status_NO_SHIFT_REG;
			end

		endcase
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		avs_cra_readdatavalid <= 1'b0;
		avs_cra_readdata <= 64'h0;
	end
	else
	begin
		avs_cra_readdatavalid <= cra_read_st1_NO_SHIFT_REG;
		case (cra_addr_st1_NO_SHIFT_REG)
			4'h2:
			begin
				avs_cra_readdata[63:0] <= profile_data_NO_SHIFT_REG;
			end

			default:
			begin
				avs_cra_readdata <= cra_readdata_st1_NO_SHIFT_REG;
			end

		endcase
	end
end


// Handshaking signals used to control data through the pipeline

// Determine when the kernel is finished.
acl_kernel_finish_detector kernel_finish_detector (
	.clock(clock),
	.resetn(resetn),
	.start(start_NO_SHIFT_REG),
	.wg_size(workgroup_size_NO_SHIFT_REG),
	.wg_dispatch_valid_out(iter_valid_in),
	.wg_dispatch_stall_in(iter_stall_out),
	.dispatched_all_groups(dispatched_all_groups),
	.kernel_copy_valid_out(valid_out),
	.kernel_copy_stall_in(stall_in),
	.pending_writes(has_a_write_pending),
	.finish(finish)
);

defparam kernel_finish_detector.TESSELLATION_SIZE = 0;
defparam kernel_finish_detector.NUM_COPIES = 1;
defparam kernel_finish_detector.WG_SIZE_W = 32;

assign stall_in = 1'b0;

// Creating ID iterator and kernel instance for every requested kernel copy

// ID iterator is responsible for iterating over all local ids for given work-groups
acl_id_iterator id_iter_inst0 (
	.clock(clock),
	.resetn(resetn),
	.start(start_out),
	.valid_in(iter_valid_in),
	.stall_out(iter_stall_out),
	.stall_in(stall_out),
	.valid_out(valid_in),
	.group_id_in(group_id_tmp),
	.global_id_base_in(global_id_base_out),
	.local_size(local_size_NO_SHIFT_REG),
	.global_size(global_size_NO_SHIFT_REG),
	.local_id(local_id[0]),
	.global_id(global_id[0]),
	.group_id(group_id[0])
);

defparam id_iter_inst0.LOCAL_WIDTH_X = 32;
defparam id_iter_inst0.LOCAL_WIDTH_Y = 32;
defparam id_iter_inst0.LOCAL_WIDTH_Z = 32;


// This section instantiates a kernel function block
float_mult_function float_mult_function_inst0 (
	.clock(clock),
	.resetn(resetn),
	.input_global_id_0(global_id[0][0]),
	.stall_out(stall_out),
	.valid_in(valid_in),
	.valid_out(valid_out),
	.stall_in(stall_in),
	.workgroup_size(workgroup_size_NO_SHIFT_REG),
	.avm_local_bb1_ld__enable(avm_local_bb1_ld__inst0_enable),
	.avm_local_bb1_ld__readdata(avm_local_bb1_ld__inst0_readdata),
	.avm_local_bb1_ld__readdatavalid(avm_local_bb1_ld__inst0_readdatavalid),
	.avm_local_bb1_ld__waitrequest(avm_local_bb1_ld__inst0_waitrequest),
	.avm_local_bb1_ld__address(avm_local_bb1_ld__inst0_address),
	.avm_local_bb1_ld__read(avm_local_bb1_ld__inst0_read),
	.avm_local_bb1_ld__write(avm_local_bb1_ld__inst0_write),
	.avm_local_bb1_ld__writeack(avm_local_bb1_ld__inst0_writeack),
	.avm_local_bb1_ld__writedata(avm_local_bb1_ld__inst0_writedata),
	.avm_local_bb1_ld__byteenable(avm_local_bb1_ld__inst0_byteenable),
	.avm_local_bb1_ld__burstcount(avm_local_bb1_ld__inst0_burstcount),
	.avm_local_bb1_ld__u0_enable(avm_local_bb1_ld__u0_inst0_enable),
	.avm_local_bb1_ld__u0_readdata(avm_local_bb1_ld__u0_inst0_readdata),
	.avm_local_bb1_ld__u0_readdatavalid(avm_local_bb1_ld__u0_inst0_readdatavalid),
	.avm_local_bb1_ld__u0_waitrequest(avm_local_bb1_ld__u0_inst0_waitrequest),
	.avm_local_bb1_ld__u0_address(avm_local_bb1_ld__u0_inst0_address),
	.avm_local_bb1_ld__u0_read(avm_local_bb1_ld__u0_inst0_read),
	.avm_local_bb1_ld__u0_write(avm_local_bb1_ld__u0_inst0_write),
	.avm_local_bb1_ld__u0_writeack(avm_local_bb1_ld__u0_inst0_writeack),
	.avm_local_bb1_ld__u0_writedata(avm_local_bb1_ld__u0_inst0_writedata),
	.avm_local_bb1_ld__u0_byteenable(avm_local_bb1_ld__u0_inst0_byteenable),
	.avm_local_bb1_ld__u0_burstcount(avm_local_bb1_ld__u0_inst0_burstcount),
	.avm_local_bb1_st__enable(avm_local_bb1_st__inst0_enable),
	.avm_local_bb1_st__readdata(avm_local_bb1_st__inst0_readdata),
	.avm_local_bb1_st__readdatavalid(avm_local_bb1_st__inst0_readdatavalid),
	.avm_local_bb1_st__waitrequest(avm_local_bb1_st__inst0_waitrequest),
	.avm_local_bb1_st__address(avm_local_bb1_st__inst0_address),
	.avm_local_bb1_st__read(avm_local_bb1_st__inst0_read),
	.avm_local_bb1_st__write(avm_local_bb1_st__inst0_write),
	.avm_local_bb1_st__writeack(avm_local_bb1_st__inst0_writeack),
	.avm_local_bb1_st__writedata(avm_local_bb1_st__inst0_writedata),
	.avm_local_bb1_st__byteenable(avm_local_bb1_st__inst0_byteenable),
	.avm_local_bb1_st__burstcount(avm_local_bb1_st__inst0_burstcount),
	.start(start_out),
	.clock2x(clock2x),
	.input_x(kernel_arguments_NO_SHIFT_REG[63:0]),
	.input_y(kernel_arguments_NO_SHIFT_REG[127:64]),
	.input_z(kernel_arguments_NO_SHIFT_REG[191:128]),
	.has_a_write_pending(has_a_write_pending),
	.has_a_lsu_active(has_a_lsu_active)
);



endmodule

//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////

// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module float_mult_sys_cycle_time
	(
		input 		clock,
		input 		resetn,
		output [31:0] 		cur_cycle
	);


 reg [31:0] cur_count_NO_SHIFT_REG;

assign cur_cycle = cur_count_NO_SHIFT_REG;

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		cur_count_NO_SHIFT_REG <= 32'h0;
	end
	else
	begin
		cur_count_NO_SHIFT_REG <= (cur_count_NO_SHIFT_REG + 32'h1);
	end
end

endmodule

// (C) 1992-2016 Altera Corporation. All rights reserved.                         
// Your use of Altera Corporation's design tools, logic functions and other       
// software and tools, and its AMPP partner logic functions, and any output       
// files any of the foregoing (including device programming or simulation         
// files), and any associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License Subscription         
// Agreement, Altera MegaCore Function License Agreement, or other applicable     
// license agreement, including, without limitation, that your use is for the     
// sole purpose of programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the applicable         
// agreement for further details.                                                 
    

//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////

// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module float_add_basic_block_0
	(
		input 		clock,
		input 		resetn,
		input 		valid_in,
		output 		stall_out,
		input [31:0] 		input_global_id_0,
		output 		valid_out,
		input 		stall_in,
		output [31:0] 		lvb_input_global_id_0,
		input [31:0] 		workgroup_size,
		input 		start
	);


// Values used for debugging.  These are swept away by synthesis.
wire _entry;
wire _exit;
 reg [31:0] _num_entry_NO_SHIFT_REG;
 reg [31:0] _num_exit_NO_SHIFT_REG;
wire [31:0] _num_live;

assign _entry = ((&valid_in) & ~((|stall_out)));
assign _exit = ((&valid_out) & ~((|stall_in)));
assign _num_live = (_num_entry_NO_SHIFT_REG - _num_exit_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		_num_entry_NO_SHIFT_REG <= 32'h0;
		_num_exit_NO_SHIFT_REG <= 32'h0;
	end
	else
	begin
		if (_entry)
		begin
			_num_entry_NO_SHIFT_REG <= (_num_entry_NO_SHIFT_REG + 2'h1);
		end
		if (_exit)
		begin
			_num_exit_NO_SHIFT_REG <= (_num_exit_NO_SHIFT_REG + 2'h1);
		end
	end
end



// This section defines the behaviour of the MERGE node
wire merge_node_stall_in;
 reg merge_node_valid_out_NO_SHIFT_REG;
wire merge_stalled_by_successors;
 reg merge_block_selector_NO_SHIFT_REG;
 reg merge_node_valid_in_staging_reg_NO_SHIFT_REG;
 reg [31:0] input_global_id_0_staging_reg_NO_SHIFT_REG;
 reg [31:0] local_lvm_input_global_id_0_NO_SHIFT_REG;
 reg is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
 reg invariant_valid_NO_SHIFT_REG;

assign merge_stalled_by_successors = (|(merge_node_stall_in & merge_node_valid_out_NO_SHIFT_REG));
assign stall_out = merge_node_valid_in_staging_reg_NO_SHIFT_REG;

always @(*)
begin
	if ((merge_node_valid_in_staging_reg_NO_SHIFT_REG | valid_in))
	begin
		merge_block_selector_NO_SHIFT_REG = 1'b0;
		is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b1;
	end
	else
	begin
		merge_block_selector_NO_SHIFT_REG = 1'b0;
		is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b0;
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		input_global_id_0_staging_reg_NO_SHIFT_REG <= 'x;
		merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (((merge_block_selector_NO_SHIFT_REG != 1'b0) | merge_stalled_by_successors))
		begin
			if (~(merge_node_valid_in_staging_reg_NO_SHIFT_REG))
			begin
				input_global_id_0_staging_reg_NO_SHIFT_REG <= input_global_id_0;
				merge_node_valid_in_staging_reg_NO_SHIFT_REG <= valid_in;
			end
		end
		else
		begin
			merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
		end
	end
end

always @(posedge clock)
begin
	if (~(merge_stalled_by_successors))
	begin
		case (merge_block_selector_NO_SHIFT_REG)
			1'b0:
			begin
				if (merge_node_valid_in_staging_reg_NO_SHIFT_REG)
				begin
					local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0_staging_reg_NO_SHIFT_REG;
				end
				else
				begin
					local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0;
				end
			end

			default:
			begin
			end

		endcase
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		merge_node_valid_out_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (~(merge_stalled_by_successors))
		begin
			merge_node_valid_out_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
		end
		else
		begin
			if (~(merge_node_stall_in))
			begin
				merge_node_valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		invariant_valid_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		invariant_valid_NO_SHIFT_REG <= (~(start) & (invariant_valid_NO_SHIFT_REG | is_merge_data_to_local_regs_valid_NO_SHIFT_REG));
	end
end


// This section describes the behaviour of the BRANCH node.
wire branch_var__inputs_ready;
 reg branch_node_valid_out_NO_SHIFT_REG;
wire branch_var__output_regs_ready;
wire combined_branch_stall_in_signal;
 reg [31:0] lvb_input_global_id_0_reg_NO_SHIFT_REG;

assign branch_var__inputs_ready = merge_node_valid_out_NO_SHIFT_REG;
assign branch_var__output_regs_ready = (~(stall_in) | ~(branch_node_valid_out_NO_SHIFT_REG));
assign merge_node_stall_in = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign lvb_input_global_id_0 = lvb_input_global_id_0_reg_NO_SHIFT_REG;
assign combined_branch_stall_in_signal = stall_in;
assign valid_out = branch_node_valid_out_NO_SHIFT_REG;

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		branch_node_valid_out_NO_SHIFT_REG <= 1'b0;
		lvb_input_global_id_0_reg_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (branch_var__output_regs_ready)
		begin
			branch_node_valid_out_NO_SHIFT_REG <= branch_var__inputs_ready;
			lvb_input_global_id_0_reg_NO_SHIFT_REG <= local_lvm_input_global_id_0_NO_SHIFT_REG;
		end
		else
		begin
			if (~(combined_branch_stall_in_signal))
			begin
				branch_node_valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end


endmodule

//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////

// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module float_add_basic_block_1
	(
		input 		clock,
		input 		resetn,
		input [63:0] 		input_x,
		input [63:0] 		input_y,
		input [63:0] 		input_z,
		input 		valid_in_0,
		output 		stall_out_0,
		input [31:0] 		input_t_01_0,
		input [31:0] 		input_global_id_0_0,
		input 		valid_in_1,
		output 		stall_out_1,
		input [31:0] 		input_t_01_1,
		input [31:0] 		input_global_id_0_1,
		output 		valid_out_0,
		input 		stall_in_0,
		output [31:0] 		lvb_bb1_inc_0,
		output [31:0] 		lvb_input_global_id_0_0,
		output 		valid_out_1,
		input 		stall_in_1,
		output [31:0] 		lvb_bb1_inc_1,
		output [31:0] 		lvb_input_global_id_0_1,
		input [31:0] 		workgroup_size,
		input 		start,
		output 		avm_local_bb1_ld__enable,
		input [255:0] 		avm_local_bb1_ld__readdata,
		input 		avm_local_bb1_ld__readdatavalid,
		input 		avm_local_bb1_ld__waitrequest,
		output [30:0] 		avm_local_bb1_ld__address,
		output 		avm_local_bb1_ld__read,
		output 		avm_local_bb1_ld__write,
		input 		avm_local_bb1_ld__writeack,
		output [255:0] 		avm_local_bb1_ld__writedata,
		output [31:0] 		avm_local_bb1_ld__byteenable,
		output [4:0] 		avm_local_bb1_ld__burstcount,
		output 		local_bb1_ld__active,
		input 		clock2x,
		output 		avm_local_bb1_ld__u0_enable,
		input [255:0] 		avm_local_bb1_ld__u0_readdata,
		input 		avm_local_bb1_ld__u0_readdatavalid,
		input 		avm_local_bb1_ld__u0_waitrequest,
		output [30:0] 		avm_local_bb1_ld__u0_address,
		output 		avm_local_bb1_ld__u0_read,
		output 		avm_local_bb1_ld__u0_write,
		input 		avm_local_bb1_ld__u0_writeack,
		output [255:0] 		avm_local_bb1_ld__u0_writedata,
		output [31:0] 		avm_local_bb1_ld__u0_byteenable,
		output [4:0] 		avm_local_bb1_ld__u0_burstcount,
		output 		local_bb1_ld__u0_active,
		output 		avm_local_bb1_st_c0_exe1_enable,
		input [255:0] 		avm_local_bb1_st_c0_exe1_readdata,
		input 		avm_local_bb1_st_c0_exe1_readdatavalid,
		input 		avm_local_bb1_st_c0_exe1_waitrequest,
		output [30:0] 		avm_local_bb1_st_c0_exe1_address,
		output 		avm_local_bb1_st_c0_exe1_read,
		output 		avm_local_bb1_st_c0_exe1_write,
		input 		avm_local_bb1_st_c0_exe1_writeack,
		output [255:0] 		avm_local_bb1_st_c0_exe1_writedata,
		output [31:0] 		avm_local_bb1_st_c0_exe1_byteenable,
		output [4:0] 		avm_local_bb1_st_c0_exe1_burstcount,
		output 		local_bb1_st_c0_exe1_active
	);


// Values used for debugging.  These are swept away by synthesis.
wire _entry;
wire _exit;
 reg [31:0] _num_entry_NO_SHIFT_REG;
 reg [31:0] _num_exit_NO_SHIFT_REG;
wire [31:0] _num_live;

assign _entry = ((valid_in_0 & valid_in_1) & ~((stall_out_0 | stall_out_1)));
assign _exit = ((valid_out_0 & valid_out_1) & ~((stall_in_0 | stall_in_1)));
assign _num_live = (_num_entry_NO_SHIFT_REG - _num_exit_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		_num_entry_NO_SHIFT_REG <= 32'h0;
		_num_exit_NO_SHIFT_REG <= 32'h0;
	end
	else
	begin
		if (_entry)
		begin
			_num_entry_NO_SHIFT_REG <= (_num_entry_NO_SHIFT_REG + 2'h1);
		end
		if (_exit)
		begin
			_num_exit_NO_SHIFT_REG <= (_num_exit_NO_SHIFT_REG + 2'h1);
		end
	end
end



// This section defines the behaviour of the MERGE node
wire merge_node_stall_in_0;
 reg merge_node_valid_out_0_NO_SHIFT_REG;
wire merge_node_stall_in_1;
 reg merge_node_valid_out_1_NO_SHIFT_REG;
wire merge_node_stall_in_2;
 reg merge_node_valid_out_2_NO_SHIFT_REG;
wire merge_stalled_by_successors;
 reg merge_block_selector_NO_SHIFT_REG;
 reg merge_node_valid_in_0_staging_reg_NO_SHIFT_REG;
 reg [31:0] input_t_01_0_staging_reg_NO_SHIFT_REG;
 reg [31:0] input_global_id_0_0_staging_reg_NO_SHIFT_REG;
 reg [31:0] local_lvm_t_01_NO_SHIFT_REG;
 reg [31:0] local_lvm_input_global_id_0_NO_SHIFT_REG;
 reg merge_node_valid_in_1_staging_reg_NO_SHIFT_REG;
 reg [31:0] input_t_01_1_staging_reg_NO_SHIFT_REG;
 reg [31:0] input_global_id_0_1_staging_reg_NO_SHIFT_REG;
 reg is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
 reg invariant_valid_NO_SHIFT_REG;

assign merge_stalled_by_successors = ((merge_node_stall_in_0 & merge_node_valid_out_0_NO_SHIFT_REG) | (merge_node_stall_in_1 & merge_node_valid_out_1_NO_SHIFT_REG) | (merge_node_stall_in_2 & merge_node_valid_out_2_NO_SHIFT_REG));
assign stall_out_0 = merge_node_valid_in_0_staging_reg_NO_SHIFT_REG;
assign stall_out_1 = merge_node_valid_in_1_staging_reg_NO_SHIFT_REG;

always @(*)
begin
	if ((merge_node_valid_in_0_staging_reg_NO_SHIFT_REG | valid_in_0))
	begin
		merge_block_selector_NO_SHIFT_REG = 1'b0;
		is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b1;
	end
	else
	begin
		if ((merge_node_valid_in_1_staging_reg_NO_SHIFT_REG | valid_in_1))
		begin
			merge_block_selector_NO_SHIFT_REG = 1'b1;
			is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b1;
		end
		else
		begin
			merge_block_selector_NO_SHIFT_REG = 1'b0;
			is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b0;
		end
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		input_t_01_0_staging_reg_NO_SHIFT_REG <= 'x;
		input_global_id_0_0_staging_reg_NO_SHIFT_REG <= 'x;
		merge_node_valid_in_0_staging_reg_NO_SHIFT_REG <= 1'b0;
		input_t_01_1_staging_reg_NO_SHIFT_REG <= 'x;
		input_global_id_0_1_staging_reg_NO_SHIFT_REG <= 'x;
		merge_node_valid_in_1_staging_reg_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (((merge_block_selector_NO_SHIFT_REG != 1'b0) | merge_stalled_by_successors))
		begin
			if (~(merge_node_valid_in_0_staging_reg_NO_SHIFT_REG))
			begin
				input_t_01_0_staging_reg_NO_SHIFT_REG <= input_t_01_0;
				input_global_id_0_0_staging_reg_NO_SHIFT_REG <= input_global_id_0_0;
				merge_node_valid_in_0_staging_reg_NO_SHIFT_REG <= valid_in_0;
			end
		end
		else
		begin
			merge_node_valid_in_0_staging_reg_NO_SHIFT_REG <= 1'b0;
		end
		if (((merge_block_selector_NO_SHIFT_REG != 1'b1) | merge_stalled_by_successors))
		begin
			if (~(merge_node_valid_in_1_staging_reg_NO_SHIFT_REG))
			begin
				input_t_01_1_staging_reg_NO_SHIFT_REG <= input_t_01_1;
				input_global_id_0_1_staging_reg_NO_SHIFT_REG <= input_global_id_0_1;
				merge_node_valid_in_1_staging_reg_NO_SHIFT_REG <= valid_in_1;
			end
		end
		else
		begin
			merge_node_valid_in_1_staging_reg_NO_SHIFT_REG <= 1'b0;
		end
	end
end

always @(posedge clock)
begin
	if (~(merge_stalled_by_successors))
	begin
		case (merge_block_selector_NO_SHIFT_REG)
			1'b0:
			begin
				if (merge_node_valid_in_0_staging_reg_NO_SHIFT_REG)
				begin
					local_lvm_t_01_NO_SHIFT_REG <= input_t_01_0_staging_reg_NO_SHIFT_REG;
					local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0_0_staging_reg_NO_SHIFT_REG;
				end
				else
				begin
					local_lvm_t_01_NO_SHIFT_REG <= input_t_01_0;
					local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0_0;
				end
			end

			1'b1:
			begin
				if (merge_node_valid_in_1_staging_reg_NO_SHIFT_REG)
				begin
					local_lvm_t_01_NO_SHIFT_REG <= input_t_01_1_staging_reg_NO_SHIFT_REG;
					local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0_1_staging_reg_NO_SHIFT_REG;
				end
				else
				begin
					local_lvm_t_01_NO_SHIFT_REG <= input_t_01_1;
					local_lvm_input_global_id_0_NO_SHIFT_REG <= input_global_id_0_1;
				end
			end

			default:
			begin
			end

		endcase
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		merge_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
		merge_node_valid_out_1_NO_SHIFT_REG <= 1'b0;
		merge_node_valid_out_2_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (~(merge_stalled_by_successors))
		begin
			merge_node_valid_out_0_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
			merge_node_valid_out_1_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
			merge_node_valid_out_2_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
		end
		else
		begin
			if (~(merge_node_stall_in_0))
			begin
				merge_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
			end
			if (~(merge_node_stall_in_1))
			begin
				merge_node_valid_out_1_NO_SHIFT_REG <= 1'b0;
			end
			if (~(merge_node_stall_in_2))
			begin
				merge_node_valid_out_2_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		invariant_valid_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		invariant_valid_NO_SHIFT_REG <= (~(start) & (invariant_valid_NO_SHIFT_REG | is_merge_data_to_local_regs_valid_NO_SHIFT_REG));
	end
end


// This section implements an unregistered operation.
// 
wire local_bb1_idxprom_RM_stall_local;
wire [63:0] local_bb1_idxprom_RM;

assign local_bb1_idxprom_RM[32] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[33] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[34] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[35] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[36] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[37] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[38] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[39] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[40] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[41] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[42] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[43] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[44] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[45] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[46] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[47] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[48] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[49] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[50] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[51] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[52] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[53] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[54] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[55] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[56] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[57] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[58] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[59] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[60] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[61] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[62] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[63] = local_lvm_input_global_id_0_NO_SHIFT_REG[31];
assign local_bb1_idxprom_RM[31:0] = local_lvm_input_global_id_0_NO_SHIFT_REG;

// Register node:
//  * latency = 330
//  * capacity = 330
 logic rnode_1to331_t_01_0_valid_out_NO_SHIFT_REG;
 logic rnode_1to331_t_01_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_1to331_t_01_0_NO_SHIFT_REG;
 logic rnode_1to331_t_01_0_reg_331_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_1to331_t_01_0_reg_331_NO_SHIFT_REG;
 logic rnode_1to331_t_01_0_valid_out_reg_331_NO_SHIFT_REG;
 logic rnode_1to331_t_01_0_stall_in_reg_331_NO_SHIFT_REG;
 logic rnode_1to331_t_01_0_stall_out_reg_331_NO_SHIFT_REG;

acl_data_fifo rnode_1to331_t_01_0_reg_331_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_1to331_t_01_0_reg_331_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_1to331_t_01_0_stall_in_reg_331_NO_SHIFT_REG),
	.valid_out(rnode_1to331_t_01_0_valid_out_reg_331_NO_SHIFT_REG),
	.stall_out(rnode_1to331_t_01_0_stall_out_reg_331_NO_SHIFT_REG),
	.data_in((local_lvm_t_01_NO_SHIFT_REG & 32'h3FF)),
	.data_out(rnode_1to331_t_01_0_reg_331_NO_SHIFT_REG)
);

defparam rnode_1to331_t_01_0_reg_331_fifo.DEPTH = 331;
defparam rnode_1to331_t_01_0_reg_331_fifo.DATA_WIDTH = 32;
defparam rnode_1to331_t_01_0_reg_331_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_1to331_t_01_0_reg_331_fifo.IMPL = "ram";

assign rnode_1to331_t_01_0_reg_331_inputs_ready_NO_SHIFT_REG = merge_node_valid_out_1_NO_SHIFT_REG;
assign merge_node_stall_in_1 = rnode_1to331_t_01_0_stall_out_reg_331_NO_SHIFT_REG;
assign rnode_1to331_t_01_0_NO_SHIFT_REG = rnode_1to331_t_01_0_reg_331_NO_SHIFT_REG;
assign rnode_1to331_t_01_0_stall_in_reg_331_NO_SHIFT_REG = rnode_1to331_t_01_0_stall_in_NO_SHIFT_REG;
assign rnode_1to331_t_01_0_valid_out_NO_SHIFT_REG = rnode_1to331_t_01_0_valid_out_reg_331_NO_SHIFT_REG;

// Register node:
//  * latency = 331
//  * capacity = 331
 logic rnode_1to332_input_global_id_0_0_valid_out_NO_SHIFT_REG;
 logic rnode_1to332_input_global_id_0_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_1to332_input_global_id_0_0_NO_SHIFT_REG;
 logic rnode_1to332_input_global_id_0_0_reg_332_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_1to332_input_global_id_0_0_reg_332_NO_SHIFT_REG;
 logic rnode_1to332_input_global_id_0_0_valid_out_reg_332_NO_SHIFT_REG;
 logic rnode_1to332_input_global_id_0_0_stall_in_reg_332_NO_SHIFT_REG;
 logic rnode_1to332_input_global_id_0_0_stall_out_reg_332_NO_SHIFT_REG;

acl_data_fifo rnode_1to332_input_global_id_0_0_reg_332_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_1to332_input_global_id_0_0_reg_332_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_1to332_input_global_id_0_0_stall_in_reg_332_NO_SHIFT_REG),
	.valid_out(rnode_1to332_input_global_id_0_0_valid_out_reg_332_NO_SHIFT_REG),
	.stall_out(rnode_1to332_input_global_id_0_0_stall_out_reg_332_NO_SHIFT_REG),
	.data_in(local_lvm_input_global_id_0_NO_SHIFT_REG),
	.data_out(rnode_1to332_input_global_id_0_0_reg_332_NO_SHIFT_REG)
);

defparam rnode_1to332_input_global_id_0_0_reg_332_fifo.DEPTH = 332;
defparam rnode_1to332_input_global_id_0_0_reg_332_fifo.DATA_WIDTH = 32;
defparam rnode_1to332_input_global_id_0_0_reg_332_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_1to332_input_global_id_0_0_reg_332_fifo.IMPL = "ram";

assign rnode_1to332_input_global_id_0_0_reg_332_inputs_ready_NO_SHIFT_REG = merge_node_valid_out_2_NO_SHIFT_REG;
assign merge_node_stall_in_2 = rnode_1to332_input_global_id_0_0_stall_out_reg_332_NO_SHIFT_REG;
assign rnode_1to332_input_global_id_0_0_NO_SHIFT_REG = rnode_1to332_input_global_id_0_0_reg_332_NO_SHIFT_REG;
assign rnode_1to332_input_global_id_0_0_stall_in_reg_332_NO_SHIFT_REG = rnode_1to332_input_global_id_0_0_stall_in_NO_SHIFT_REG;
assign rnode_1to332_input_global_id_0_0_valid_out_NO_SHIFT_REG = rnode_1to332_input_global_id_0_0_valid_out_reg_332_NO_SHIFT_REG;

// This section implements an unregistered operation.
// 
wire local_bb1_arrayidx_RM_stall_local;
wire [63:0] local_bb1_arrayidx_RM;

assign local_bb1_arrayidx_RM = ((input_x & 64'hFFFFFFFFFFFFFC00) + (local_bb1_idxprom_RM << 6'h2));

// This section implements an unregistered operation.
// 
wire local_bb1_arrayidx3_RM_stall_local;
wire [63:0] local_bb1_arrayidx3_RM;

assign local_bb1_arrayidx3_RM = ((input_y & 64'hFFFFFFFFFFFFFC00) + (local_bb1_idxprom_RM << 6'h2));

// This section implements an unregistered operation.
// 
wire local_bb1_arrayidx_RM_valid_out;
wire local_bb1_arrayidx_RM_stall_in;
wire local_bb1_arrayidx3_RM_valid_out;
wire local_bb1_arrayidx3_RM_stall_in;
wire local_bb1_arrayidx5_RM_valid_out;
wire local_bb1_arrayidx5_RM_stall_in;
wire local_bb1_arrayidx5_RM_inputs_ready;
wire local_bb1_arrayidx5_RM_stall_local;
wire [63:0] local_bb1_arrayidx5_RM;
 reg local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG;
 reg local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG;
 reg local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG;

assign local_bb1_arrayidx5_RM_inputs_ready = merge_node_valid_out_0_NO_SHIFT_REG;
assign local_bb1_arrayidx5_RM = ((input_z & 64'hFFFFFFFFFFFFFC00) + (local_bb1_idxprom_RM << 6'h2));
assign local_bb1_arrayidx5_RM_stall_local = ((local_bb1_arrayidx_RM_stall_in & ~(local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG)) | (local_bb1_arrayidx3_RM_stall_in & ~(local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG)) | (local_bb1_arrayidx5_RM_stall_in & ~(local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG)));
assign local_bb1_arrayidx_RM_valid_out = (local_bb1_arrayidx5_RM_inputs_ready & ~(local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG));
assign local_bb1_arrayidx3_RM_valid_out = (local_bb1_arrayidx5_RM_inputs_ready & ~(local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG));
assign local_bb1_arrayidx5_RM_valid_out = (local_bb1_arrayidx5_RM_inputs_ready & ~(local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG));
assign merge_node_stall_in_0 = (|local_bb1_arrayidx5_RM_stall_local);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG <= 1'b0;
		local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG <= 1'b0;
		local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG <= (local_bb1_arrayidx5_RM_inputs_ready & (local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG | ~(local_bb1_arrayidx_RM_stall_in)) & local_bb1_arrayidx5_RM_stall_local);
		local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG <= (local_bb1_arrayidx5_RM_inputs_ready & (local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG | ~(local_bb1_arrayidx3_RM_stall_in)) & local_bb1_arrayidx5_RM_stall_local);
		local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG <= (local_bb1_arrayidx5_RM_inputs_ready & (local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG | ~(local_bb1_arrayidx5_RM_stall_in)) & local_bb1_arrayidx5_RM_stall_local);
	end
end


// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_331to332_t_01_0_valid_out_NO_SHIFT_REG;
 logic rnode_331to332_t_01_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_331to332_t_01_0_NO_SHIFT_REG;
 logic rnode_331to332_t_01_0_reg_332_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_331to332_t_01_0_reg_332_NO_SHIFT_REG;
 logic rnode_331to332_t_01_0_valid_out_reg_332_NO_SHIFT_REG;
 logic rnode_331to332_t_01_0_stall_in_reg_332_NO_SHIFT_REG;
 logic rnode_331to332_t_01_0_stall_out_reg_332_NO_SHIFT_REG;

acl_data_fifo rnode_331to332_t_01_0_reg_332_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_331to332_t_01_0_reg_332_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_331to332_t_01_0_stall_in_reg_332_NO_SHIFT_REG),
	.valid_out(rnode_331to332_t_01_0_valid_out_reg_332_NO_SHIFT_REG),
	.stall_out(rnode_331to332_t_01_0_stall_out_reg_332_NO_SHIFT_REG),
	.data_in((rnode_1to331_t_01_0_NO_SHIFT_REG & 32'h3FF)),
	.data_out(rnode_331to332_t_01_0_reg_332_NO_SHIFT_REG)
);

defparam rnode_331to332_t_01_0_reg_332_fifo.DEPTH = 1;
defparam rnode_331to332_t_01_0_reg_332_fifo.DATA_WIDTH = 32;
defparam rnode_331to332_t_01_0_reg_332_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_331to332_t_01_0_reg_332_fifo.IMPL = "ll_reg";

assign rnode_331to332_t_01_0_reg_332_inputs_ready_NO_SHIFT_REG = rnode_1to331_t_01_0_valid_out_NO_SHIFT_REG;
assign rnode_1to331_t_01_0_stall_in_NO_SHIFT_REG = rnode_331to332_t_01_0_stall_out_reg_332_NO_SHIFT_REG;
assign rnode_331to332_t_01_0_NO_SHIFT_REG = rnode_331to332_t_01_0_reg_332_NO_SHIFT_REG;
assign rnode_331to332_t_01_0_stall_in_reg_332_NO_SHIFT_REG = rnode_331to332_t_01_0_stall_in_NO_SHIFT_REG;
assign rnode_331to332_t_01_0_valid_out_NO_SHIFT_REG = rnode_331to332_t_01_0_valid_out_reg_332_NO_SHIFT_REG;

// This section implements a staging register.
// 
wire rstag_1to1_bb1_arrayidx_RM_valid_out;
wire rstag_1to1_bb1_arrayidx_RM_stall_in;
wire rstag_1to1_bb1_arrayidx_RM_inputs_ready;
wire rstag_1to1_bb1_arrayidx_RM_stall_local;
 reg rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG;
wire rstag_1to1_bb1_arrayidx_RM_combined_valid;
 reg [63:0] rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG;
wire [63:0] rstag_1to1_bb1_arrayidx_RM;

assign rstag_1to1_bb1_arrayidx_RM_inputs_ready = local_bb1_arrayidx_RM_valid_out;
assign rstag_1to1_bb1_arrayidx_RM = (rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ? rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG : (local_bb1_arrayidx_RM & 64'hFFFFFFFFFFFFFFFC));
assign rstag_1to1_bb1_arrayidx_RM_combined_valid = (rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG | rstag_1to1_bb1_arrayidx_RM_inputs_ready);
assign rstag_1to1_bb1_arrayidx_RM_valid_out = rstag_1to1_bb1_arrayidx_RM_combined_valid;
assign rstag_1to1_bb1_arrayidx_RM_stall_local = rstag_1to1_bb1_arrayidx_RM_stall_in;
assign local_bb1_arrayidx_RM_stall_in = (|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG <= 1'b0;
		rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (rstag_1to1_bb1_arrayidx_RM_stall_local)
		begin
			if (~(rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG))
			begin
				rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG <= rstag_1to1_bb1_arrayidx_RM_inputs_ready;
			end
		end
		else
		begin
			rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG <= 1'b0;
		end
		if (~(rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG))
		begin
			rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG <= (local_bb1_arrayidx_RM & 64'hFFFFFFFFFFFFFFFC);
		end
	end
end


// This section implements a staging register.
// 
wire rstag_1to1_bb1_arrayidx3_RM_valid_out;
wire rstag_1to1_bb1_arrayidx3_RM_stall_in;
wire rstag_1to1_bb1_arrayidx3_RM_inputs_ready;
wire rstag_1to1_bb1_arrayidx3_RM_stall_local;
 reg rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG;
wire rstag_1to1_bb1_arrayidx3_RM_combined_valid;
 reg [63:0] rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG;
wire [63:0] rstag_1to1_bb1_arrayidx3_RM;

assign rstag_1to1_bb1_arrayidx3_RM_inputs_ready = local_bb1_arrayidx3_RM_valid_out;
assign rstag_1to1_bb1_arrayidx3_RM = (rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ? rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG : (local_bb1_arrayidx3_RM & 64'hFFFFFFFFFFFFFFFC));
assign rstag_1to1_bb1_arrayidx3_RM_combined_valid = (rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG | rstag_1to1_bb1_arrayidx3_RM_inputs_ready);
assign rstag_1to1_bb1_arrayidx3_RM_valid_out = rstag_1to1_bb1_arrayidx3_RM_combined_valid;
assign rstag_1to1_bb1_arrayidx3_RM_stall_local = rstag_1to1_bb1_arrayidx3_RM_stall_in;
assign local_bb1_arrayidx3_RM_stall_in = (|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG <= 1'b0;
		rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (rstag_1to1_bb1_arrayidx3_RM_stall_local)
		begin
			if (~(rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG))
			begin
				rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG <= rstag_1to1_bb1_arrayidx3_RM_inputs_ready;
			end
		end
		else
		begin
			rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG <= 1'b0;
		end
		if (~(rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG))
		begin
			rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG <= (local_bb1_arrayidx3_RM & 64'hFFFFFFFFFFFFFFFC);
		end
	end
end


// Register node:
//  * latency = 171
//  * capacity = 171
 logic rnode_1to172_bb1_arrayidx5_RM_0_valid_out_NO_SHIFT_REG;
 logic rnode_1to172_bb1_arrayidx5_RM_0_stall_in_NO_SHIFT_REG;
 logic [63:0] rnode_1to172_bb1_arrayidx5_RM_0_NO_SHIFT_REG;
 logic rnode_1to172_bb1_arrayidx5_RM_0_reg_172_inputs_ready_NO_SHIFT_REG;
 logic [63:0] rnode_1to172_bb1_arrayidx5_RM_0_reg_172_NO_SHIFT_REG;
 logic rnode_1to172_bb1_arrayidx5_RM_0_valid_out_reg_172_NO_SHIFT_REG;
 logic rnode_1to172_bb1_arrayidx5_RM_0_stall_in_reg_172_NO_SHIFT_REG;
 logic rnode_1to172_bb1_arrayidx5_RM_0_stall_out_reg_172_NO_SHIFT_REG;

acl_data_fifo rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_1to172_bb1_arrayidx5_RM_0_reg_172_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_1to172_bb1_arrayidx5_RM_0_stall_in_reg_172_NO_SHIFT_REG),
	.valid_out(rnode_1to172_bb1_arrayidx5_RM_0_valid_out_reg_172_NO_SHIFT_REG),
	.stall_out(rnode_1to172_bb1_arrayidx5_RM_0_stall_out_reg_172_NO_SHIFT_REG),
	.data_in((local_bb1_arrayidx5_RM & 64'hFFFFFFFFFFFFFFFC)),
	.data_out(rnode_1to172_bb1_arrayidx5_RM_0_reg_172_NO_SHIFT_REG)
);

defparam rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo.DEPTH = 172;
defparam rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo.DATA_WIDTH = 64;
defparam rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo.IMPL = "ram";

assign rnode_1to172_bb1_arrayidx5_RM_0_reg_172_inputs_ready_NO_SHIFT_REG = local_bb1_arrayidx5_RM_valid_out;
assign local_bb1_arrayidx5_RM_stall_in = rnode_1to172_bb1_arrayidx5_RM_0_stall_out_reg_172_NO_SHIFT_REG;
assign rnode_1to172_bb1_arrayidx5_RM_0_NO_SHIFT_REG = rnode_1to172_bb1_arrayidx5_RM_0_reg_172_NO_SHIFT_REG;
assign rnode_1to172_bb1_arrayidx5_RM_0_stall_in_reg_172_NO_SHIFT_REG = rnode_1to172_bb1_arrayidx5_RM_0_stall_in_NO_SHIFT_REG;
assign rnode_1to172_bb1_arrayidx5_RM_0_valid_out_NO_SHIFT_REG = rnode_1to172_bb1_arrayidx5_RM_0_valid_out_reg_172_NO_SHIFT_REG;

// This section implements an unregistered operation.
// 
wire local_bb1_inc_valid_out;
wire local_bb1_inc_stall_in;
wire local_bb1_inc_inputs_ready;
wire local_bb1_inc_stall_local;
wire [31:0] local_bb1_inc;

assign local_bb1_inc_inputs_ready = rnode_331to332_t_01_0_valid_out_NO_SHIFT_REG;
assign local_bb1_inc = ((rnode_331to332_t_01_0_NO_SHIFT_REG & 32'h3FF) + 32'h1);
assign local_bb1_inc_valid_out = local_bb1_inc_inputs_ready;
assign local_bb1_inc_stall_local = local_bb1_inc_stall_in;
assign rnode_331to332_t_01_0_stall_in_NO_SHIFT_REG = (|local_bb1_inc_stall_local);

// This section implements a registered operation.
// 
wire local_bb1_ld__inputs_ready;
 reg local_bb1_ld__valid_out_NO_SHIFT_REG;
wire local_bb1_ld__stall_in;
wire local_bb1_ld__output_regs_ready;
wire local_bb1_ld__fu_stall_out;
wire local_bb1_ld__fu_valid_out;
wire [31:0] local_bb1_ld__lsu_dataout;
 reg [31:0] local_bb1_ld__NO_SHIFT_REG;
wire local_bb1_ld__causedstall;

lsu_top lsu_local_bb1_ld_ (
	.clock(clock),
	.clock2x(clock2x),
	.resetn(resetn),
	.flush(start),
	.stream_base_addr(),
	.stream_size(),
	.stream_reset(),
	.o_stall(local_bb1_ld__fu_stall_out),
	.i_valid(local_bb1_ld__inputs_ready),
	.i_address((rstag_1to1_bb1_arrayidx_RM & 64'hFFFFFFFFFFFFFFFC)),
	.i_writedata(),
	.i_cmpdata(),
	.i_predicate(1'b0),
	.i_bitwiseor(64'h0),
	.i_byteenable(),
	.i_stall(~(local_bb1_ld__output_regs_ready)),
	.o_valid(local_bb1_ld__fu_valid_out),
	.o_readdata(local_bb1_ld__lsu_dataout),
	.o_input_fifo_depth(),
	.o_writeack(),
	.i_atomic_op(3'h0),
	.o_active(local_bb1_ld__active),
	.avm_address(avm_local_bb1_ld__address),
	.avm_read(avm_local_bb1_ld__read),
	.avm_enable(avm_local_bb1_ld__enable),
	.avm_readdata(avm_local_bb1_ld__readdata),
	.avm_write(avm_local_bb1_ld__write),
	.avm_writeack(avm_local_bb1_ld__writeack),
	.avm_burstcount(avm_local_bb1_ld__burstcount),
	.avm_writedata(avm_local_bb1_ld__writedata),
	.avm_byteenable(avm_local_bb1_ld__byteenable),
	.avm_waitrequest(avm_local_bb1_ld__waitrequest),
	.avm_readdatavalid(avm_local_bb1_ld__readdatavalid),
	.profile_bw(),
	.profile_bw_incr(),
	.profile_total_ivalid(),
	.profile_total_req(),
	.profile_i_stall_count(),
	.profile_o_stall_count(),
	.profile_avm_readwrite_count(),
	.profile_avm_burstcount_total(),
	.profile_avm_burstcount_total_incr(),
	.profile_req_cache_hit_count(),
	.profile_extra_unaligned_reqs(),
	.profile_avm_stall()
);

defparam lsu_local_bb1_ld_.AWIDTH = 31;
defparam lsu_local_bb1_ld_.WIDTH_BYTES = 4;
defparam lsu_local_bb1_ld_.MWIDTH_BYTES = 32;
defparam lsu_local_bb1_ld_.WRITEDATAWIDTH_BYTES = 32;
defparam lsu_local_bb1_ld_.ALIGNMENT_BYTES = 4;
defparam lsu_local_bb1_ld_.READ = 1;
defparam lsu_local_bb1_ld_.ATOMIC = 0;
defparam lsu_local_bb1_ld_.WIDTH = 32;
defparam lsu_local_bb1_ld_.MWIDTH = 256;
defparam lsu_local_bb1_ld_.ATOMIC_WIDTH = 3;
defparam lsu_local_bb1_ld_.BURSTCOUNT_WIDTH = 5;
defparam lsu_local_bb1_ld_.KERNEL_SIDE_MEM_LATENCY = 160;
defparam lsu_local_bb1_ld_.MEMORY_SIDE_MEM_LATENCY = 89;
defparam lsu_local_bb1_ld_.USE_WRITE_ACK = 0;
defparam lsu_local_bb1_ld_.ENABLE_BANKED_MEMORY = 0;
defparam lsu_local_bb1_ld_.ABITS_PER_LMEM_BANK = 0;
defparam lsu_local_bb1_ld_.NUMBER_BANKS = 1;
defparam lsu_local_bb1_ld_.LMEM_ADDR_PERMUTATION_STYLE = 0;
defparam lsu_local_bb1_ld_.INTENDED_DEVICE_FAMILY = "Cyclone V";
defparam lsu_local_bb1_ld_.USEINPUTFIFO = 0;
defparam lsu_local_bb1_ld_.USECACHING = 0;
defparam lsu_local_bb1_ld_.USEOUTPUTFIFO = 1;
defparam lsu_local_bb1_ld_.FORCE_NOP_SUPPORT = 0;
defparam lsu_local_bb1_ld_.ADDRSPACE = 1;
defparam lsu_local_bb1_ld_.STYLE = "BURST-COALESCED";

assign local_bb1_ld__inputs_ready = rstag_1to1_bb1_arrayidx_RM_valid_out;
assign local_bb1_ld__output_regs_ready = (&(~(local_bb1_ld__valid_out_NO_SHIFT_REG) | ~(local_bb1_ld__stall_in)));
assign rstag_1to1_bb1_arrayidx_RM_stall_in = (local_bb1_ld__fu_stall_out | ~(local_bb1_ld__inputs_ready));
assign local_bb1_ld__causedstall = (local_bb1_ld__inputs_ready && (local_bb1_ld__fu_stall_out && !(~(local_bb1_ld__output_regs_ready))));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_ld__NO_SHIFT_REG <= 'x;
		local_bb1_ld__valid_out_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (local_bb1_ld__output_regs_ready)
		begin
			local_bb1_ld__NO_SHIFT_REG <= local_bb1_ld__lsu_dataout;
			local_bb1_ld__valid_out_NO_SHIFT_REG <= local_bb1_ld__fu_valid_out;
		end
		else
		begin
			if (~(local_bb1_ld__stall_in))
			begin
				local_bb1_ld__valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end


// This section implements a registered operation.
// 
wire local_bb1_ld__u0_inputs_ready;
 reg local_bb1_ld__u0_valid_out_NO_SHIFT_REG;
wire local_bb1_ld__u0_stall_in;
wire local_bb1_ld__u0_output_regs_ready;
wire local_bb1_ld__u0_fu_stall_out;
wire local_bb1_ld__u0_fu_valid_out;
wire [31:0] local_bb1_ld__u0_lsu_dataout;
 reg [31:0] local_bb1_ld__u0_NO_SHIFT_REG;
wire local_bb1_ld__u0_causedstall;

lsu_top lsu_local_bb1_ld__u0 (
	.clock(clock),
	.clock2x(clock2x),
	.resetn(resetn),
	.flush(start),
	.stream_base_addr(),
	.stream_size(),
	.stream_reset(),
	.o_stall(local_bb1_ld__u0_fu_stall_out),
	.i_valid(local_bb1_ld__u0_inputs_ready),
	.i_address((rstag_1to1_bb1_arrayidx3_RM & 64'hFFFFFFFFFFFFFFFC)),
	.i_writedata(),
	.i_cmpdata(),
	.i_predicate(1'b0),
	.i_bitwiseor(64'h0),
	.i_byteenable(),
	.i_stall(~(local_bb1_ld__u0_output_regs_ready)),
	.o_valid(local_bb1_ld__u0_fu_valid_out),
	.o_readdata(local_bb1_ld__u0_lsu_dataout),
	.o_input_fifo_depth(),
	.o_writeack(),
	.i_atomic_op(3'h0),
	.o_active(local_bb1_ld__u0_active),
	.avm_address(avm_local_bb1_ld__u0_address),
	.avm_read(avm_local_bb1_ld__u0_read),
	.avm_enable(avm_local_bb1_ld__u0_enable),
	.avm_readdata(avm_local_bb1_ld__u0_readdata),
	.avm_write(avm_local_bb1_ld__u0_write),
	.avm_writeack(avm_local_bb1_ld__u0_writeack),
	.avm_burstcount(avm_local_bb1_ld__u0_burstcount),
	.avm_writedata(avm_local_bb1_ld__u0_writedata),
	.avm_byteenable(avm_local_bb1_ld__u0_byteenable),
	.avm_waitrequest(avm_local_bb1_ld__u0_waitrequest),
	.avm_readdatavalid(avm_local_bb1_ld__u0_readdatavalid),
	.profile_bw(),
	.profile_bw_incr(),
	.profile_total_ivalid(),
	.profile_total_req(),
	.profile_i_stall_count(),
	.profile_o_stall_count(),
	.profile_avm_readwrite_count(),
	.profile_avm_burstcount_total(),
	.profile_avm_burstcount_total_incr(),
	.profile_req_cache_hit_count(),
	.profile_extra_unaligned_reqs(),
	.profile_avm_stall()
);

defparam lsu_local_bb1_ld__u0.AWIDTH = 31;
defparam lsu_local_bb1_ld__u0.WIDTH_BYTES = 4;
defparam lsu_local_bb1_ld__u0.MWIDTH_BYTES = 32;
defparam lsu_local_bb1_ld__u0.WRITEDATAWIDTH_BYTES = 32;
defparam lsu_local_bb1_ld__u0.ALIGNMENT_BYTES = 4;
defparam lsu_local_bb1_ld__u0.READ = 1;
defparam lsu_local_bb1_ld__u0.ATOMIC = 0;
defparam lsu_local_bb1_ld__u0.WIDTH = 32;
defparam lsu_local_bb1_ld__u0.MWIDTH = 256;
defparam lsu_local_bb1_ld__u0.ATOMIC_WIDTH = 3;
defparam lsu_local_bb1_ld__u0.BURSTCOUNT_WIDTH = 5;
defparam lsu_local_bb1_ld__u0.KERNEL_SIDE_MEM_LATENCY = 160;
defparam lsu_local_bb1_ld__u0.MEMORY_SIDE_MEM_LATENCY = 89;
defparam lsu_local_bb1_ld__u0.USE_WRITE_ACK = 0;
defparam lsu_local_bb1_ld__u0.ENABLE_BANKED_MEMORY = 0;
defparam lsu_local_bb1_ld__u0.ABITS_PER_LMEM_BANK = 0;
defparam lsu_local_bb1_ld__u0.NUMBER_BANKS = 1;
defparam lsu_local_bb1_ld__u0.LMEM_ADDR_PERMUTATION_STYLE = 0;
defparam lsu_local_bb1_ld__u0.INTENDED_DEVICE_FAMILY = "Cyclone V";
defparam lsu_local_bb1_ld__u0.USEINPUTFIFO = 0;
defparam lsu_local_bb1_ld__u0.USECACHING = 0;
defparam lsu_local_bb1_ld__u0.USEOUTPUTFIFO = 1;
defparam lsu_local_bb1_ld__u0.FORCE_NOP_SUPPORT = 0;
defparam lsu_local_bb1_ld__u0.ADDRSPACE = 1;
defparam lsu_local_bb1_ld__u0.STYLE = "BURST-COALESCED";

assign local_bb1_ld__u0_inputs_ready = rstag_1to1_bb1_arrayidx3_RM_valid_out;
assign local_bb1_ld__u0_output_regs_ready = (&(~(local_bb1_ld__u0_valid_out_NO_SHIFT_REG) | ~(local_bb1_ld__u0_stall_in)));
assign rstag_1to1_bb1_arrayidx3_RM_stall_in = (local_bb1_ld__u0_fu_stall_out | ~(local_bb1_ld__u0_inputs_ready));
assign local_bb1_ld__u0_causedstall = (local_bb1_ld__u0_inputs_ready && (local_bb1_ld__u0_fu_stall_out && !(~(local_bb1_ld__u0_output_regs_ready))));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_ld__u0_NO_SHIFT_REG <= 'x;
		local_bb1_ld__u0_valid_out_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (local_bb1_ld__u0_output_regs_ready)
		begin
			local_bb1_ld__u0_NO_SHIFT_REG <= local_bb1_ld__u0_lsu_dataout;
			local_bb1_ld__u0_valid_out_NO_SHIFT_REG <= local_bb1_ld__u0_fu_valid_out;
		end
		else
		begin
			if (~(local_bb1_ld__u0_stall_in))
			begin
				local_bb1_ld__u0_valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end


// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_172to173_bb1_arrayidx5_RM_0_valid_out_NO_SHIFT_REG;
 logic rnode_172to173_bb1_arrayidx5_RM_0_stall_in_NO_SHIFT_REG;
 logic [63:0] rnode_172to173_bb1_arrayidx5_RM_0_NO_SHIFT_REG;
 logic rnode_172to173_bb1_arrayidx5_RM_0_reg_173_inputs_ready_NO_SHIFT_REG;
 logic [63:0] rnode_172to173_bb1_arrayidx5_RM_0_reg_173_NO_SHIFT_REG;
 logic rnode_172to173_bb1_arrayidx5_RM_0_valid_out_reg_173_NO_SHIFT_REG;
 logic rnode_172to173_bb1_arrayidx5_RM_0_stall_in_reg_173_NO_SHIFT_REG;
 logic rnode_172to173_bb1_arrayidx5_RM_0_stall_out_reg_173_NO_SHIFT_REG;
wire [63:0] rci_rcnode_332to333_rc0_bb1_inc_0_reg_332;

acl_data_fifo rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_172to173_bb1_arrayidx5_RM_0_reg_173_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_172to173_bb1_arrayidx5_RM_0_stall_in_reg_173_NO_SHIFT_REG),
	.valid_out(rnode_172to173_bb1_arrayidx5_RM_0_valid_out_reg_173_NO_SHIFT_REG),
	.stall_out(rnode_172to173_bb1_arrayidx5_RM_0_stall_out_reg_173_NO_SHIFT_REG),
	.data_in((rnode_1to172_bb1_arrayidx5_RM_0_NO_SHIFT_REG & 64'hFFFFFFFFFFFFFFFC)),
	.data_out(rnode_172to173_bb1_arrayidx5_RM_0_reg_173_NO_SHIFT_REG)
);

defparam rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo.DEPTH = 2;
defparam rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo.DATA_WIDTH = 64;
defparam rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo.ALLOW_FULL_WRITE = 0;
defparam rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo.IMPL = "ll_reg";

assign rnode_172to173_bb1_arrayidx5_RM_0_reg_173_inputs_ready_NO_SHIFT_REG = rnode_1to172_bb1_arrayidx5_RM_0_valid_out_NO_SHIFT_REG;
assign rnode_1to172_bb1_arrayidx5_RM_0_stall_in_NO_SHIFT_REG = rnode_172to173_bb1_arrayidx5_RM_0_stall_out_reg_173_NO_SHIFT_REG;
assign rnode_172to173_bb1_arrayidx5_RM_0_NO_SHIFT_REG = rnode_172to173_bb1_arrayidx5_RM_0_reg_173_NO_SHIFT_REG;
assign rnode_172to173_bb1_arrayidx5_RM_0_stall_in_reg_173_NO_SHIFT_REG = rnode_172to173_bb1_arrayidx5_RM_0_stall_in_NO_SHIFT_REG;
assign rnode_172to173_bb1_arrayidx5_RM_0_valid_out_NO_SHIFT_REG = rnode_172to173_bb1_arrayidx5_RM_0_valid_out_reg_173_NO_SHIFT_REG;
assign rci_rcnode_332to333_rc0_bb1_inc_0_reg_332[31:0] = (local_bb1_inc & 32'h7FF);
assign rci_rcnode_332to333_rc0_bb1_inc_0_reg_332[63:32] = rnode_1to332_input_global_id_0_0_NO_SHIFT_REG;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rcnode_332to333_rc0_bb1_inc_0_valid_out_0_NO_SHIFT_REG;
 logic rcnode_332to333_rc0_bb1_inc_0_stall_in_0_NO_SHIFT_REG;
 logic [63:0] rcnode_332to333_rc0_bb1_inc_0_NO_SHIFT_REG;
 logic rcnode_332to333_rc0_bb1_inc_0_valid_out_1_NO_SHIFT_REG;
 logic rcnode_332to333_rc0_bb1_inc_0_stall_in_1_NO_SHIFT_REG;
 logic [63:0] rcnode_332to333_rc0_bb1_inc_1_NO_SHIFT_REG;
 logic rcnode_332to333_rc0_bb1_inc_0_reg_333_inputs_ready_NO_SHIFT_REG;
 logic [63:0] rcnode_332to333_rc0_bb1_inc_0_reg_333_NO_SHIFT_REG;
 logic rcnode_332to333_rc0_bb1_inc_0_valid_out_0_reg_333_NO_SHIFT_REG;
 logic rcnode_332to333_rc0_bb1_inc_0_stall_in_0_reg_333_NO_SHIFT_REG;
 logic rcnode_332to333_rc0_bb1_inc_0_stall_out_0_reg_333_IP_NO_SHIFT_REG;
 logic rcnode_332to333_rc0_bb1_inc_0_stall_out_0_reg_333_NO_SHIFT_REG;

acl_data_fifo rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rcnode_332to333_rc0_bb1_inc_0_reg_333_inputs_ready_NO_SHIFT_REG),
	.stall_in(rcnode_332to333_rc0_bb1_inc_0_stall_in_0_reg_333_NO_SHIFT_REG),
	.valid_out(rcnode_332to333_rc0_bb1_inc_0_valid_out_0_reg_333_NO_SHIFT_REG),
	.stall_out(rcnode_332to333_rc0_bb1_inc_0_stall_out_0_reg_333_IP_NO_SHIFT_REG),
	.data_in(rci_rcnode_332to333_rc0_bb1_inc_0_reg_332),
	.data_out(rcnode_332to333_rc0_bb1_inc_0_reg_333_NO_SHIFT_REG)
);

defparam rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo.DEPTH = 1;
defparam rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo.DATA_WIDTH = 64;
defparam rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo.ALLOW_FULL_WRITE = 1;
defparam rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo.IMPL = "ll_reg";

assign rcnode_332to333_rc0_bb1_inc_0_reg_333_inputs_ready_NO_SHIFT_REG = (local_bb1_inc_valid_out & rnode_1to332_input_global_id_0_0_valid_out_NO_SHIFT_REG);
assign rcnode_332to333_rc0_bb1_inc_0_stall_out_0_reg_333_NO_SHIFT_REG = (~(rcnode_332to333_rc0_bb1_inc_0_reg_333_inputs_ready_NO_SHIFT_REG) | rcnode_332to333_rc0_bb1_inc_0_stall_out_0_reg_333_IP_NO_SHIFT_REG);
assign local_bb1_inc_stall_in = rcnode_332to333_rc0_bb1_inc_0_stall_out_0_reg_333_NO_SHIFT_REG;
assign rnode_1to332_input_global_id_0_0_stall_in_NO_SHIFT_REG = rcnode_332to333_rc0_bb1_inc_0_stall_out_0_reg_333_NO_SHIFT_REG;
assign rcnode_332to333_rc0_bb1_inc_0_stall_in_0_reg_333_NO_SHIFT_REG = (rcnode_332to333_rc0_bb1_inc_0_stall_in_0_NO_SHIFT_REG | rcnode_332to333_rc0_bb1_inc_0_stall_in_1_NO_SHIFT_REG);
assign rcnode_332to333_rc0_bb1_inc_0_valid_out_0_NO_SHIFT_REG = rcnode_332to333_rc0_bb1_inc_0_valid_out_0_reg_333_NO_SHIFT_REG;
assign rcnode_332to333_rc0_bb1_inc_0_valid_out_1_NO_SHIFT_REG = rcnode_332to333_rc0_bb1_inc_0_valid_out_0_reg_333_NO_SHIFT_REG;
assign rcnode_332to333_rc0_bb1_inc_0_NO_SHIFT_REG = rcnode_332to333_rc0_bb1_inc_0_reg_333_NO_SHIFT_REG;
assign rcnode_332to333_rc0_bb1_inc_1_NO_SHIFT_REG = rcnode_332to333_rc0_bb1_inc_0_reg_333_NO_SHIFT_REG;

// This section implements a staging register.
// 
wire rstag_161to161_bb1_ld__valid_out;
wire rstag_161to161_bb1_ld__stall_in;
wire rstag_161to161_bb1_ld__inputs_ready;
wire rstag_161to161_bb1_ld__stall_local;
 reg rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG;
wire rstag_161to161_bb1_ld__combined_valid;
 reg [31:0] rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG;
wire [31:0] rstag_161to161_bb1_ld_;

assign rstag_161to161_bb1_ld__inputs_ready = local_bb1_ld__valid_out_NO_SHIFT_REG;
assign rstag_161to161_bb1_ld_ = (rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ? rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG : local_bb1_ld__NO_SHIFT_REG);
assign rstag_161to161_bb1_ld__combined_valid = (rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG | rstag_161to161_bb1_ld__inputs_ready);
assign rstag_161to161_bb1_ld__valid_out = rstag_161to161_bb1_ld__combined_valid;
assign rstag_161to161_bb1_ld__stall_local = rstag_161to161_bb1_ld__stall_in;
assign local_bb1_ld__stall_in = (|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG <= 1'b0;
		rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (rstag_161to161_bb1_ld__stall_local)
		begin
			if (~(rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG))
			begin
				rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG <= rstag_161to161_bb1_ld__inputs_ready;
			end
		end
		else
		begin
			rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG <= 1'b0;
		end
		if (~(rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG))
		begin
			rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG <= local_bb1_ld__NO_SHIFT_REG;
		end
	end
end


// This section implements a staging register.
// 
wire rstag_161to161_bb1_ld__u0_valid_out;
wire rstag_161to161_bb1_ld__u0_stall_in;
wire rstag_161to161_bb1_ld__u0_inputs_ready;
wire rstag_161to161_bb1_ld__u0_stall_local;
 reg rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG;
wire rstag_161to161_bb1_ld__u0_combined_valid;
 reg [31:0] rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG;
wire [31:0] rstag_161to161_bb1_ld__u0;

assign rstag_161to161_bb1_ld__u0_inputs_ready = local_bb1_ld__u0_valid_out_NO_SHIFT_REG;
assign rstag_161to161_bb1_ld__u0 = (rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ? rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG : local_bb1_ld__u0_NO_SHIFT_REG);
assign rstag_161to161_bb1_ld__u0_combined_valid = (rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG | rstag_161to161_bb1_ld__u0_inputs_ready);
assign rstag_161to161_bb1_ld__u0_valid_out = rstag_161to161_bb1_ld__u0_combined_valid;
assign rstag_161to161_bb1_ld__u0_stall_local = rstag_161to161_bb1_ld__u0_stall_in;
assign local_bb1_ld__u0_stall_in = (|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG <= 1'b0;
		rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (rstag_161to161_bb1_ld__u0_stall_local)
		begin
			if (~(rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG))
			begin
				rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG <= rstag_161to161_bb1_ld__u0_inputs_ready;
			end
		end
		else
		begin
			rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG <= 1'b0;
		end
		if (~(rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG))
		begin
			rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG <= local_bb1_ld__u0_NO_SHIFT_REG;
		end
	end
end


// This section implements an unregistered operation.
// 
wire local_bb1_exitcond_valid_out;
wire local_bb1_exitcond_stall_in;
wire local_bb1_exitcond_inputs_ready;
wire local_bb1_exitcond_stall_local;
wire local_bb1_exitcond;

assign local_bb1_exitcond_inputs_ready = rcnode_332to333_rc0_bb1_inc_0_valid_out_0_NO_SHIFT_REG;
assign local_bb1_exitcond = ((rcnode_332to333_rc0_bb1_inc_0_NO_SHIFT_REG[31:0] & 32'h7FF) == 32'h3E8);
assign local_bb1_exitcond_valid_out = local_bb1_exitcond_inputs_ready;
assign local_bb1_exitcond_stall_local = local_bb1_exitcond_stall_in;
assign rcnode_332to333_rc0_bb1_inc_0_stall_in_0_NO_SHIFT_REG = (|local_bb1_exitcond_stall_local);

// This section implements an unregistered operation.
// 
wire local_bb1_c0_eni1_stall_local;
wire [95:0] local_bb1_c0_eni1;

assign local_bb1_c0_eni1[31:0] = 32'bx;
assign local_bb1_c0_eni1[63:32] = rstag_161to161_bb1_ld_;
assign local_bb1_c0_eni1[95:64] = 32'bx;

// This section implements an unregistered operation.
// 
wire local_bb1_c0_eni2_valid_out;
wire local_bb1_c0_eni2_stall_in;
wire local_bb1_c0_eni2_inputs_ready;
wire local_bb1_c0_eni2_stall_local;
wire [95:0] local_bb1_c0_eni2;

assign local_bb1_c0_eni2_inputs_ready = (rstag_161to161_bb1_ld__valid_out & rstag_161to161_bb1_ld__u0_valid_out);
assign local_bb1_c0_eni2[63:0] = local_bb1_c0_eni1[63:0];
assign local_bb1_c0_eni2[95:64] = rstag_161to161_bb1_ld__u0;
assign local_bb1_c0_eni2_valid_out = local_bb1_c0_eni2_inputs_ready;
assign local_bb1_c0_eni2_stall_local = local_bb1_c0_eni2_stall_in;
assign rstag_161to161_bb1_ld__stall_in = (local_bb1_c0_eni2_stall_local | ~(local_bb1_c0_eni2_inputs_ready));
assign rstag_161to161_bb1_ld__u0_stall_in = (local_bb1_c0_eni2_stall_local | ~(local_bb1_c0_eni2_inputs_ready));

// This section implements a registered operation.
// 
wire local_bb1_c0_enter_c0_eni2_inputs_ready;
 reg local_bb1_c0_enter_c0_eni2_valid_out_0_NO_SHIFT_REG;
wire local_bb1_c0_enter_c0_eni2_stall_in_0;
 reg local_bb1_c0_enter_c0_eni2_valid_out_1_NO_SHIFT_REG;
wire local_bb1_c0_enter_c0_eni2_stall_in_1;
 reg local_bb1_c0_enter_c0_eni2_valid_out_2_NO_SHIFT_REG;
wire local_bb1_c0_enter_c0_eni2_stall_in_2;
wire local_bb1_c0_enter_c0_eni2_output_regs_ready;
 reg [95:0] local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG;
wire local_bb1_c0_enter_c0_eni2_input_accepted;
 reg local_bb1_c0_enter_c0_eni2_valid_bit_NO_SHIFT_REG;
wire local_bb1_c0_exit_c0_exi1_entry_stall;
wire local_bb1_c0_exit_c0_exi1_output_regs_ready;
wire local_bb1_c0_exit_c0_exi1_valid_in;
wire local_bb1_c0_exit_c0_exi1_phases;
wire local_bb1_c0_enter_c0_eni2_inc_pipelined_thread;
wire local_bb1_c0_enter_c0_eni2_dec_pipelined_thread;
wire local_bb1_c0_enter_c0_eni2_causedstall;

assign local_bb1_c0_enter_c0_eni2_inputs_ready = local_bb1_c0_eni2_valid_out;
assign local_bb1_c0_enter_c0_eni2_output_regs_ready = 1'b1;
assign local_bb1_c0_enter_c0_eni2_input_accepted = (local_bb1_c0_enter_c0_eni2_inputs_ready && !(local_bb1_c0_exit_c0_exi1_entry_stall));
assign local_bb1_c0_enter_c0_eni2_inc_pipelined_thread = 1'b1;
assign local_bb1_c0_enter_c0_eni2_dec_pipelined_thread = ~(1'b0);
assign local_bb1_c0_eni2_stall_in = ((~(local_bb1_c0_enter_c0_eni2_inputs_ready) | local_bb1_c0_exit_c0_exi1_entry_stall) | ~(1'b1));
assign local_bb1_c0_enter_c0_eni2_causedstall = (1'b1 && ((~(local_bb1_c0_enter_c0_eni2_inputs_ready) | local_bb1_c0_exit_c0_exi1_entry_stall) && !(1'b0)));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_c0_enter_c0_eni2_valid_bit_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		local_bb1_c0_enter_c0_eni2_valid_bit_NO_SHIFT_REG <= local_bb1_c0_enter_c0_eni2_input_accepted;
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG <= 'x;
		local_bb1_c0_enter_c0_eni2_valid_out_0_NO_SHIFT_REG <= 1'b0;
		local_bb1_c0_enter_c0_eni2_valid_out_1_NO_SHIFT_REG <= 1'b0;
		local_bb1_c0_enter_c0_eni2_valid_out_2_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (local_bb1_c0_enter_c0_eni2_output_regs_ready)
		begin
			local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG <= local_bb1_c0_eni2;
			local_bb1_c0_enter_c0_eni2_valid_out_0_NO_SHIFT_REG <= 1'b1;
			local_bb1_c0_enter_c0_eni2_valid_out_1_NO_SHIFT_REG <= 1'b1;
			local_bb1_c0_enter_c0_eni2_valid_out_2_NO_SHIFT_REG <= 1'b1;
		end
		else
		begin
			if (~(local_bb1_c0_enter_c0_eni2_stall_in_0))
			begin
				local_bb1_c0_enter_c0_eni2_valid_out_0_NO_SHIFT_REG <= 1'b0;
			end
			if (~(local_bb1_c0_enter_c0_eni2_stall_in_1))
			begin
				local_bb1_c0_enter_c0_eni2_valid_out_1_NO_SHIFT_REG <= 1'b0;
			end
			if (~(local_bb1_c0_enter_c0_eni2_stall_in_2))
			begin
				local_bb1_c0_enter_c0_eni2_valid_out_2_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end


// This section implements an unregistered operation.
// 
wire local_bb1_c0_ene1_stall_local;
wire [31:0] local_bb1_c0_ene1;

assign local_bb1_c0_ene1 = local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63:32];

// This section implements an unregistered operation.
// 
wire local_bb1_c0_ene2_stall_local;
wire [31:0] local_bb1_c0_ene2;

assign local_bb1_c0_ene2 = local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95:64];

// This section implements an unregistered operation.
// 
wire SFC_1_VALID_162_162_0_valid_out;
wire SFC_1_VALID_162_162_0_stall_in;
wire SFC_1_VALID_162_162_0_inputs_ready;
wire SFC_1_VALID_162_162_0_stall_local;
wire SFC_1_VALID_162_162_0;

assign SFC_1_VALID_162_162_0_inputs_ready = local_bb1_c0_enter_c0_eni2_valid_out_2_NO_SHIFT_REG;
assign SFC_1_VALID_162_162_0 = local_bb1_c0_enter_c0_eni2_valid_bit_NO_SHIFT_REG;
assign SFC_1_VALID_162_162_0_valid_out = 1'b1;
assign local_bb1_c0_enter_c0_eni2_stall_in_2 = 1'b0;

// This section implements an unregistered operation.
// 
wire local_bb1_var__stall_local;
wire [31:0] local_bb1_var_;

assign local_bb1_var_ = local_bb1_c0_ene1;

// This section implements an unregistered operation.
// 
wire local_bb1_var__u1_stall_local;
wire [31:0] local_bb1_var__u1;

assign local_bb1_var__u1 = local_bb1_c0_ene2;

// This section implements a registered operation.
// 
wire SFC_1_VALID_162_163_0_inputs_ready;
 reg SFC_1_VALID_162_163_0_valid_out_NO_SHIFT_REG;
wire SFC_1_VALID_162_163_0_stall_in;
wire SFC_1_VALID_162_163_0_output_regs_ready;
 reg SFC_1_VALID_162_163_0_NO_SHIFT_REG /* synthesis  preserve  */;
wire SFC_1_VALID_162_163_0_causedstall;

assign SFC_1_VALID_162_163_0_inputs_ready = 1'b1;
assign SFC_1_VALID_162_163_0_output_regs_ready = 1'b1;
assign SFC_1_VALID_162_162_0_stall_in = 1'b0;
assign SFC_1_VALID_162_163_0_causedstall = (1'b1 && (1'b0 && !(1'b0)));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		SFC_1_VALID_162_163_0_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (SFC_1_VALID_162_163_0_output_regs_ready)
		begin
			SFC_1_VALID_162_163_0_NO_SHIFT_REG <= SFC_1_VALID_162_162_0;
		end
	end
end


// This section implements an unregistered operation.
// 
wire local_bb1_and2_i_stall_local;
wire [31:0] local_bb1_and2_i;

assign local_bb1_and2_i = (local_bb1_var_ >> 32'h10);

// This section implements an unregistered operation.
// 
wire local_bb1_and12_i_stall_local;
wire [31:0] local_bb1_and12_i;

assign local_bb1_and12_i = (local_bb1_var_ & 32'hFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1_and_i_stall_local;
wire [31:0] local_bb1_and_i;

assign local_bb1_and_i = (local_bb1_var__u1 >> 32'h10);

// This section implements an unregistered operation.
// 
wire local_bb1_and10_i_stall_local;
wire [31:0] local_bb1_and10_i;

assign local_bb1_and10_i = (local_bb1_var__u1 & 32'hFFFF);

// This section implements a registered operation.
// 
wire SFC_1_VALID_163_164_0_inputs_ready;
 reg SFC_1_VALID_163_164_0_valid_out_NO_SHIFT_REG;
wire SFC_1_VALID_163_164_0_stall_in;
wire SFC_1_VALID_163_164_0_output_regs_ready;
 reg SFC_1_VALID_163_164_0_NO_SHIFT_REG /* synthesis  preserve  */;
wire SFC_1_VALID_163_164_0_causedstall;

assign SFC_1_VALID_163_164_0_inputs_ready = 1'b1;
assign SFC_1_VALID_163_164_0_output_regs_ready = 1'b1;
assign SFC_1_VALID_162_163_0_stall_in = 1'b0;
assign SFC_1_VALID_163_164_0_causedstall = (1'b1 && (1'b0 && !(1'b0)));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		SFC_1_VALID_163_164_0_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (SFC_1_VALID_163_164_0_output_regs_ready)
		begin
			SFC_1_VALID_163_164_0_NO_SHIFT_REG <= SFC_1_VALID_162_163_0_NO_SHIFT_REG;
		end
	end
end


// This section implements an unregistered operation.
// 
wire local_bb1_shr3_i_stall_local;
wire [31:0] local_bb1_shr3_i;

assign local_bb1_shr3_i = ((local_bb1_and2_i & 32'hFFFF) & 32'h7FFF);

// This section implements an unregistered operation.
// 
wire local_bb1_shr_i_stall_local;
wire [31:0] local_bb1_shr_i;

assign local_bb1_shr_i = ((local_bb1_and_i & 32'hFFFF) & 32'h7FFF);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp13_i_stall_local;
wire local_bb1_cmp13_i;

assign local_bb1_cmp13_i = ((local_bb1_and10_i & 32'hFFFF) > (local_bb1_and12_i & 32'hFFFF));

// This section implements a registered operation.
// 
wire SFC_1_VALID_164_165_0_inputs_ready;
 reg SFC_1_VALID_164_165_0_valid_out_NO_SHIFT_REG;
wire SFC_1_VALID_164_165_0_stall_in;
wire SFC_1_VALID_164_165_0_output_regs_ready;
 reg SFC_1_VALID_164_165_0_NO_SHIFT_REG /* synthesis  preserve  */;
wire SFC_1_VALID_164_165_0_causedstall;

assign SFC_1_VALID_164_165_0_inputs_ready = 1'b1;
assign SFC_1_VALID_164_165_0_output_regs_ready = 1'b1;
assign SFC_1_VALID_163_164_0_stall_in = 1'b0;
assign SFC_1_VALID_164_165_0_causedstall = (1'b1 && (1'b0 && !(1'b0)));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		SFC_1_VALID_164_165_0_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (SFC_1_VALID_164_165_0_output_regs_ready)
		begin
			SFC_1_VALID_164_165_0_NO_SHIFT_REG <= SFC_1_VALID_163_164_0_NO_SHIFT_REG;
		end
	end
end


// This section implements an unregistered operation.
// 
wire local_bb1_cmp_i_stall_local;
wire local_bb1_cmp_i;

assign local_bb1_cmp_i = ((local_bb1_shr_i & 32'h7FFF) > (local_bb1_shr3_i & 32'h7FFF));

// This section implements an unregistered operation.
// 
wire local_bb1_cmp8_i_stall_local;
wire local_bb1_cmp8_i;

assign local_bb1_cmp8_i = ((local_bb1_shr_i & 32'h7FFF) == (local_bb1_shr3_i & 32'h7FFF));

// This section implements a registered operation.
// 
wire SFC_1_VALID_165_166_0_inputs_ready;
 reg SFC_1_VALID_165_166_0_valid_out_NO_SHIFT_REG;
wire SFC_1_VALID_165_166_0_stall_in;
wire SFC_1_VALID_165_166_0_output_regs_ready;
 reg SFC_1_VALID_165_166_0_NO_SHIFT_REG /* synthesis  preserve  */;
wire SFC_1_VALID_165_166_0_causedstall;

assign SFC_1_VALID_165_166_0_inputs_ready = 1'b1;
assign SFC_1_VALID_165_166_0_output_regs_ready = 1'b1;
assign SFC_1_VALID_164_165_0_stall_in = 1'b0;
assign SFC_1_VALID_165_166_0_causedstall = (1'b1 && (1'b0 && !(1'b0)));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		SFC_1_VALID_165_166_0_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (SFC_1_VALID_165_166_0_output_regs_ready)
		begin
			SFC_1_VALID_165_166_0_NO_SHIFT_REG <= SFC_1_VALID_164_165_0_NO_SHIFT_REG;
		end
	end
end


// This section implements an unregistered operation.
// 
wire local_bb1___i_stall_local;
wire local_bb1___i;

assign local_bb1___i = (local_bb1_cmp8_i & local_bb1_cmp13_i);

// This section implements a registered operation.
// 
wire SFC_1_VALID_166_167_0_inputs_ready;
 reg SFC_1_VALID_166_167_0_valid_out_NO_SHIFT_REG;
wire SFC_1_VALID_166_167_0_stall_in;
wire SFC_1_VALID_166_167_0_output_regs_ready;
 reg SFC_1_VALID_166_167_0_NO_SHIFT_REG /* synthesis  preserve  */;
wire SFC_1_VALID_166_167_0_causedstall;

assign SFC_1_VALID_166_167_0_inputs_ready = 1'b1;
assign SFC_1_VALID_166_167_0_output_regs_ready = 1'b1;
assign SFC_1_VALID_165_166_0_stall_in = 1'b0;
assign SFC_1_VALID_166_167_0_causedstall = (1'b1 && (1'b0 && !(1'b0)));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		SFC_1_VALID_166_167_0_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (SFC_1_VALID_166_167_0_output_regs_ready)
		begin
			SFC_1_VALID_166_167_0_NO_SHIFT_REG <= SFC_1_VALID_165_166_0_NO_SHIFT_REG;
		end
	end
end


// This section implements an unregistered operation.
// 
wire local_bb1__8_i_stall_local;
wire local_bb1__8_i;

assign local_bb1__8_i = (local_bb1_cmp_i | local_bb1___i);

// This section implements a registered operation.
// 
wire SFC_1_VALID_167_168_0_inputs_ready;
 reg SFC_1_VALID_167_168_0_valid_out_NO_SHIFT_REG;
wire SFC_1_VALID_167_168_0_stall_in;
wire SFC_1_VALID_167_168_0_output_regs_ready;
 reg SFC_1_VALID_167_168_0_NO_SHIFT_REG /* synthesis  preserve  */;
wire SFC_1_VALID_167_168_0_causedstall;

assign SFC_1_VALID_167_168_0_inputs_ready = 1'b1;
assign SFC_1_VALID_167_168_0_output_regs_ready = 1'b1;
assign SFC_1_VALID_166_167_0_stall_in = 1'b0;
assign SFC_1_VALID_167_168_0_causedstall = (1'b1 && (1'b0 && !(1'b0)));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		SFC_1_VALID_167_168_0_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (SFC_1_VALID_167_168_0_output_regs_ready)
		begin
			SFC_1_VALID_167_168_0_NO_SHIFT_REG <= SFC_1_VALID_166_167_0_NO_SHIFT_REG;
		end
	end
end


// This section implements an unregistered operation.
// 
wire local_bb1__9_i_stall_local;
wire [31:0] local_bb1__9_i;

assign local_bb1__9_i = (local_bb1__8_i ? local_bb1_var_ : local_bb1_var__u1);

// This section implements an unregistered operation.
// 
wire local_bb1__9_i_valid_out;
wire local_bb1__9_i_stall_in;
wire local_bb1__10_i_valid_out;
wire local_bb1__10_i_stall_in;
wire local_bb1__10_i_inputs_ready;
wire local_bb1__10_i_stall_local;
wire [31:0] local_bb1__10_i;

assign local_bb1__10_i_inputs_ready = (local_bb1_c0_enter_c0_eni2_valid_out_0_NO_SHIFT_REG & local_bb1_c0_enter_c0_eni2_valid_out_1_NO_SHIFT_REG);
assign local_bb1__10_i = (local_bb1__8_i ? local_bb1_var__u1 : local_bb1_var_);
assign local_bb1__9_i_valid_out = 1'b1;
assign local_bb1__10_i_valid_out = 1'b1;
assign local_bb1_c0_enter_c0_eni2_stall_in_0 = 1'b0;
assign local_bb1_c0_enter_c0_eni2_stall_in_1 = 1'b0;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_162to163_bb1__9_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_162to163_bb1__9_i_0_stall_in_0_NO_SHIFT_REG;
 logic [31:0] rnode_162to163_bb1__9_i_0_NO_SHIFT_REG;
 logic rnode_162to163_bb1__9_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_162to163_bb1__9_i_0_stall_in_1_NO_SHIFT_REG;
 logic [31:0] rnode_162to163_bb1__9_i_1_NO_SHIFT_REG;
 logic rnode_162to163_bb1__9_i_0_valid_out_2_NO_SHIFT_REG;
 logic rnode_162to163_bb1__9_i_0_stall_in_2_NO_SHIFT_REG;
 logic [31:0] rnode_162to163_bb1__9_i_2_NO_SHIFT_REG;
 logic rnode_162to163_bb1__9_i_0_reg_163_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_162to163_bb1__9_i_0_reg_163_NO_SHIFT_REG;
 logic rnode_162to163_bb1__9_i_0_valid_out_0_reg_163_NO_SHIFT_REG;
 logic rnode_162to163_bb1__9_i_0_stall_in_0_reg_163_NO_SHIFT_REG;
 logic rnode_162to163_bb1__9_i_0_stall_out_reg_163_NO_SHIFT_REG;

acl_data_fifo rnode_162to163_bb1__9_i_0_reg_163_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_162to163_bb1__9_i_0_reg_163_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_162to163_bb1__9_i_0_stall_in_0_reg_163_NO_SHIFT_REG),
	.valid_out(rnode_162to163_bb1__9_i_0_valid_out_0_reg_163_NO_SHIFT_REG),
	.stall_out(rnode_162to163_bb1__9_i_0_stall_out_reg_163_NO_SHIFT_REG),
	.data_in(local_bb1__9_i),
	.data_out(rnode_162to163_bb1__9_i_0_reg_163_NO_SHIFT_REG)
);

defparam rnode_162to163_bb1__9_i_0_reg_163_fifo.DEPTH = 1;
defparam rnode_162to163_bb1__9_i_0_reg_163_fifo.DATA_WIDTH = 32;
defparam rnode_162to163_bb1__9_i_0_reg_163_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_162to163_bb1__9_i_0_reg_163_fifo.IMPL = "shift_reg";

assign rnode_162to163_bb1__9_i_0_reg_163_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__9_i_stall_in = 1'b0;
assign rnode_162to163_bb1__9_i_0_stall_in_0_reg_163_NO_SHIFT_REG = 1'b0;
assign rnode_162to163_bb1__9_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_162to163_bb1__9_i_0_NO_SHIFT_REG = rnode_162to163_bb1__9_i_0_reg_163_NO_SHIFT_REG;
assign rnode_162to163_bb1__9_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_162to163_bb1__9_i_1_NO_SHIFT_REG = rnode_162to163_bb1__9_i_0_reg_163_NO_SHIFT_REG;
assign rnode_162to163_bb1__9_i_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_162to163_bb1__9_i_2_NO_SHIFT_REG = rnode_162to163_bb1__9_i_0_reg_163_NO_SHIFT_REG;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_162to163_bb1__10_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_162to163_bb1__10_i_0_stall_in_0_NO_SHIFT_REG;
 logic [31:0] rnode_162to163_bb1__10_i_0_NO_SHIFT_REG;
 logic rnode_162to163_bb1__10_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_162to163_bb1__10_i_0_stall_in_1_NO_SHIFT_REG;
 logic [31:0] rnode_162to163_bb1__10_i_1_NO_SHIFT_REG;
 logic rnode_162to163_bb1__10_i_0_valid_out_2_NO_SHIFT_REG;
 logic rnode_162to163_bb1__10_i_0_stall_in_2_NO_SHIFT_REG;
 logic [31:0] rnode_162to163_bb1__10_i_2_NO_SHIFT_REG;
 logic rnode_162to163_bb1__10_i_0_valid_out_3_NO_SHIFT_REG;
 logic rnode_162to163_bb1__10_i_0_stall_in_3_NO_SHIFT_REG;
 logic [31:0] rnode_162to163_bb1__10_i_3_NO_SHIFT_REG;
 logic rnode_162to163_bb1__10_i_0_reg_163_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_162to163_bb1__10_i_0_reg_163_NO_SHIFT_REG;
 logic rnode_162to163_bb1__10_i_0_valid_out_0_reg_163_NO_SHIFT_REG;
 logic rnode_162to163_bb1__10_i_0_stall_in_0_reg_163_NO_SHIFT_REG;
 logic rnode_162to163_bb1__10_i_0_stall_out_reg_163_NO_SHIFT_REG;

acl_data_fifo rnode_162to163_bb1__10_i_0_reg_163_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_162to163_bb1__10_i_0_reg_163_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_162to163_bb1__10_i_0_stall_in_0_reg_163_NO_SHIFT_REG),
	.valid_out(rnode_162to163_bb1__10_i_0_valid_out_0_reg_163_NO_SHIFT_REG),
	.stall_out(rnode_162to163_bb1__10_i_0_stall_out_reg_163_NO_SHIFT_REG),
	.data_in(local_bb1__10_i),
	.data_out(rnode_162to163_bb1__10_i_0_reg_163_NO_SHIFT_REG)
);

defparam rnode_162to163_bb1__10_i_0_reg_163_fifo.DEPTH = 1;
defparam rnode_162to163_bb1__10_i_0_reg_163_fifo.DATA_WIDTH = 32;
defparam rnode_162to163_bb1__10_i_0_reg_163_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_162to163_bb1__10_i_0_reg_163_fifo.IMPL = "shift_reg";

assign rnode_162to163_bb1__10_i_0_reg_163_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__10_i_stall_in = 1'b0;
assign rnode_162to163_bb1__10_i_0_stall_in_0_reg_163_NO_SHIFT_REG = 1'b0;
assign rnode_162to163_bb1__10_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_162to163_bb1__10_i_0_NO_SHIFT_REG = rnode_162to163_bb1__10_i_0_reg_163_NO_SHIFT_REG;
assign rnode_162to163_bb1__10_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_162to163_bb1__10_i_1_NO_SHIFT_REG = rnode_162to163_bb1__10_i_0_reg_163_NO_SHIFT_REG;
assign rnode_162to163_bb1__10_i_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_162to163_bb1__10_i_2_NO_SHIFT_REG = rnode_162to163_bb1__10_i_0_reg_163_NO_SHIFT_REG;
assign rnode_162to163_bb1__10_i_0_valid_out_3_NO_SHIFT_REG = 1'b1;
assign rnode_162to163_bb1__10_i_3_NO_SHIFT_REG = rnode_162to163_bb1__10_i_0_reg_163_NO_SHIFT_REG;

// This section implements an unregistered operation.
// 
wire local_bb1_shr18_i_stall_local;
wire [31:0] local_bb1_shr18_i;

assign local_bb1_shr18_i = (rnode_162to163_bb1__9_i_0_NO_SHIFT_REG >> 32'h17);

// This section implements an unregistered operation.
// 
wire local_bb1_and21_i_stall_local;
wire [31:0] local_bb1_and21_i;

assign local_bb1_and21_i = (rnode_162to163_bb1__9_i_1_NO_SHIFT_REG & 32'h7FFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1_shr16_i_stall_local;
wire [31:0] local_bb1_shr16_i;

assign local_bb1_shr16_i = (rnode_162to163_bb1__10_i_0_NO_SHIFT_REG >> 32'h17);

// This section implements an unregistered operation.
// 
wire local_bb1_and20_i_valid_out;
wire local_bb1_and20_i_stall_in;
wire local_bb1_and20_i_inputs_ready;
wire local_bb1_and20_i_stall_local;
wire [31:0] local_bb1_and20_i;

assign local_bb1_and20_i_inputs_ready = rnode_162to163_bb1__10_i_0_valid_out_1_NO_SHIFT_REG;
assign local_bb1_and20_i = (rnode_162to163_bb1__10_i_1_NO_SHIFT_REG & 32'h7FFFFF);
assign local_bb1_and20_i_valid_out = 1'b1;
assign rnode_162to163_bb1__10_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;

// This section implements an unregistered operation.
// 
wire local_bb1_and35_i_valid_out;
wire local_bb1_and35_i_stall_in;
wire local_bb1_and35_i_inputs_ready;
wire local_bb1_and35_i_stall_local;
wire [31:0] local_bb1_and35_i;

assign local_bb1_and35_i_inputs_ready = rnode_162to163_bb1__10_i_0_valid_out_2_NO_SHIFT_REG;
assign local_bb1_and35_i = (rnode_162to163_bb1__10_i_2_NO_SHIFT_REG & 32'h80000000);
assign local_bb1_and35_i_valid_out = 1'b1;
assign rnode_162to163_bb1__10_i_0_stall_in_2_NO_SHIFT_REG = 1'b0;

// This section implements an unregistered operation.
// 
wire local_bb1_xor_i_valid_out;
wire local_bb1_xor_i_stall_in;
wire local_bb1_xor_i_inputs_ready;
wire local_bb1_xor_i_stall_local;
wire [31:0] local_bb1_xor_i;

assign local_bb1_xor_i_inputs_ready = (rnode_162to163_bb1__10_i_0_valid_out_3_NO_SHIFT_REG & rnode_162to163_bb1__9_i_0_valid_out_2_NO_SHIFT_REG);
assign local_bb1_xor_i = (rnode_162to163_bb1__10_i_3_NO_SHIFT_REG ^ rnode_162to163_bb1__9_i_2_NO_SHIFT_REG);
assign local_bb1_xor_i_valid_out = 1'b1;
assign rnode_162to163_bb1__10_i_0_stall_in_3_NO_SHIFT_REG = 1'b0;
assign rnode_162to163_bb1__9_i_0_stall_in_2_NO_SHIFT_REG = 1'b0;

// This section implements an unregistered operation.
// 
wire local_bb1_and19_i_stall_local;
wire [31:0] local_bb1_and19_i;

assign local_bb1_and19_i = ((local_bb1_shr18_i & 32'h1FF) & 32'hFF);

// This section implements an unregistered operation.
// 
wire local_bb1_lnot33_not_i_stall_local;
wire local_bb1_lnot33_not_i;

assign local_bb1_lnot33_not_i = ((local_bb1_and21_i & 32'h7FFFFF) != 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_or64_i_stall_local;
wire [31:0] local_bb1_or64_i;

assign local_bb1_or64_i = ((local_bb1_and21_i & 32'h7FFFFF) << 32'h3);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u2_stall_local;
wire [31:0] local_bb1_var__u2;

assign local_bb1_var__u2 = ((local_bb1_shr18_i & 32'h1FF) & (local_bb1_shr16_i & 32'h1FF));

// This section implements an unregistered operation.
// 
wire local_bb1_sub_i_stall_local;
wire [31:0] local_bb1_sub_i;

assign local_bb1_sub_i = ((local_bb1_shr16_i & 32'h1FF) - (local_bb1_shr18_i & 32'h1FF));

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_163to164_bb1_and20_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and20_i_0_stall_in_0_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_and20_i_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and20_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and20_i_0_stall_in_1_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_and20_i_1_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and20_i_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_and20_i_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and20_i_0_valid_out_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and20_i_0_stall_in_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and20_i_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_163to164_bb1_and20_i_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_163to164_bb1_and20_i_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_163to164_bb1_and20_i_0_stall_in_0_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_163to164_bb1_and20_i_0_valid_out_0_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_163to164_bb1_and20_i_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in((local_bb1_and20_i & 32'h7FFFFF)),
	.data_out(rnode_163to164_bb1_and20_i_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_163to164_bb1_and20_i_0_reg_164_fifo.DEPTH = 1;
defparam rnode_163to164_bb1_and20_i_0_reg_164_fifo.DATA_WIDTH = 32;
defparam rnode_163to164_bb1_and20_i_0_reg_164_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_163to164_bb1_and20_i_0_reg_164_fifo.IMPL = "shift_reg";

assign rnode_163to164_bb1_and20_i_0_reg_164_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_and20_i_stall_in = 1'b0;
assign rnode_163to164_bb1_and20_i_0_stall_in_0_reg_164_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_and20_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_and20_i_0_NO_SHIFT_REG = rnode_163to164_bb1_and20_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_and20_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_and20_i_1_NO_SHIFT_REG = rnode_163to164_bb1_and20_i_0_reg_164_NO_SHIFT_REG;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_163to164_bb1_and35_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and35_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_and35_i_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and35_i_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_and35_i_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and35_i_0_valid_out_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and35_i_0_stall_in_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and35_i_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_163to164_bb1_and35_i_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_163to164_bb1_and35_i_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_163to164_bb1_and35_i_0_stall_in_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_163to164_bb1_and35_i_0_valid_out_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_163to164_bb1_and35_i_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in((local_bb1_and35_i & 32'h80000000)),
	.data_out(rnode_163to164_bb1_and35_i_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_163to164_bb1_and35_i_0_reg_164_fifo.DEPTH = 1;
defparam rnode_163to164_bb1_and35_i_0_reg_164_fifo.DATA_WIDTH = 32;
defparam rnode_163to164_bb1_and35_i_0_reg_164_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_163to164_bb1_and35_i_0_reg_164_fifo.IMPL = "shift_reg";

assign rnode_163to164_bb1_and35_i_0_reg_164_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_and35_i_stall_in = 1'b0;
assign rnode_163to164_bb1_and35_i_0_NO_SHIFT_REG = rnode_163to164_bb1_and35_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_and35_i_0_stall_in_reg_164_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_and35_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_163to164_bb1_xor_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_xor_i_0_stall_in_0_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_xor_i_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_xor_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_163to164_bb1_xor_i_0_stall_in_1_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_xor_i_1_NO_SHIFT_REG;
 logic rnode_163to164_bb1_xor_i_0_valid_out_2_NO_SHIFT_REG;
 logic rnode_163to164_bb1_xor_i_0_stall_in_2_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_xor_i_2_NO_SHIFT_REG;
 logic rnode_163to164_bb1_xor_i_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_xor_i_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_xor_i_0_valid_out_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_xor_i_0_stall_in_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_xor_i_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_163to164_bb1_xor_i_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_163to164_bb1_xor_i_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_163to164_bb1_xor_i_0_stall_in_0_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_163to164_bb1_xor_i_0_valid_out_0_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_163to164_bb1_xor_i_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in(local_bb1_xor_i),
	.data_out(rnode_163to164_bb1_xor_i_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_163to164_bb1_xor_i_0_reg_164_fifo.DEPTH = 1;
defparam rnode_163to164_bb1_xor_i_0_reg_164_fifo.DATA_WIDTH = 32;
defparam rnode_163to164_bb1_xor_i_0_reg_164_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_163to164_bb1_xor_i_0_reg_164_fifo.IMPL = "shift_reg";

assign rnode_163to164_bb1_xor_i_0_reg_164_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_xor_i_stall_in = 1'b0;
assign rnode_163to164_bb1_xor_i_0_stall_in_0_reg_164_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_xor_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_xor_i_0_NO_SHIFT_REG = rnode_163to164_bb1_xor_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_xor_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_xor_i_1_NO_SHIFT_REG = rnode_163to164_bb1_xor_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_xor_i_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_xor_i_2_NO_SHIFT_REG = rnode_163to164_bb1_xor_i_0_reg_164_NO_SHIFT_REG;

// This section implements an unregistered operation.
// 
wire local_bb1_lnot23_i_stall_local;
wire local_bb1_lnot23_i;

assign local_bb1_lnot23_i = ((local_bb1_and19_i & 32'hFF) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp27_i_stall_local;
wire local_bb1_cmp27_i;

assign local_bb1_cmp27_i = ((local_bb1_and19_i & 32'hFF) == 32'hFF);

// This section implements an unregistered operation.
// 
wire local_bb1_shl65_i_stall_local;
wire [31:0] local_bb1_shl65_i;

assign local_bb1_shl65_i = ((local_bb1_or64_i & 32'h3FFFFF8) | 32'h4000000);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u3_stall_local;
wire [31:0] local_bb1_var__u3;

assign local_bb1_var__u3 = ((local_bb1_var__u2 & 32'h1FF) & 32'hFF);

// This section implements an unregistered operation.
// 
wire local_bb1_and68_i_stall_local;
wire [31:0] local_bb1_and68_i;

assign local_bb1_and68_i = (local_bb1_sub_i & 32'hFF);

// This section implements an unregistered operation.
// 
wire local_bb1_lnot30_i_stall_local;
wire local_bb1_lnot30_i;

assign local_bb1_lnot30_i = ((rnode_163to164_bb1_and20_i_0_NO_SHIFT_REG & 32'h7FFFFF) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_or_i_stall_local;
wire [31:0] local_bb1_or_i;

assign local_bb1_or_i = ((rnode_163to164_bb1_and20_i_1_NO_SHIFT_REG & 32'h7FFFFF) << 32'h3);

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_164to165_bb1_and35_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_164to165_bb1_and35_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_164to165_bb1_and35_i_0_NO_SHIFT_REG;
 logic rnode_164to165_bb1_and35_i_0_reg_165_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_164to165_bb1_and35_i_0_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1_and35_i_0_valid_out_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1_and35_i_0_stall_in_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1_and35_i_0_stall_out_reg_165_NO_SHIFT_REG;

acl_data_fifo rnode_164to165_bb1_and35_i_0_reg_165_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_164to165_bb1_and35_i_0_reg_165_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_164to165_bb1_and35_i_0_stall_in_reg_165_NO_SHIFT_REG),
	.valid_out(rnode_164to165_bb1_and35_i_0_valid_out_reg_165_NO_SHIFT_REG),
	.stall_out(rnode_164to165_bb1_and35_i_0_stall_out_reg_165_NO_SHIFT_REG),
	.data_in((rnode_163to164_bb1_and35_i_0_NO_SHIFT_REG & 32'h80000000)),
	.data_out(rnode_164to165_bb1_and35_i_0_reg_165_NO_SHIFT_REG)
);

defparam rnode_164to165_bb1_and35_i_0_reg_165_fifo.DEPTH = 1;
defparam rnode_164to165_bb1_and35_i_0_reg_165_fifo.DATA_WIDTH = 32;
defparam rnode_164to165_bb1_and35_i_0_reg_165_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_164to165_bb1_and35_i_0_reg_165_fifo.IMPL = "shift_reg";

assign rnode_164to165_bb1_and35_i_0_reg_165_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_and35_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_and35_i_0_NO_SHIFT_REG = rnode_164to165_bb1_and35_i_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_and35_i_0_stall_in_reg_165_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_and35_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// This section implements an unregistered operation.
// 
wire local_bb1_cmp37_i_stall_local;
wire local_bb1_cmp37_i;

assign local_bb1_cmp37_i = ($signed(rnode_163to164_bb1_xor_i_0_NO_SHIFT_REG) < $signed(32'h0));

// This section implements an unregistered operation.
// 
wire local_bb1_xor_lobit_i_stall_local;
wire [31:0] local_bb1_xor_lobit_i;

assign local_bb1_xor_lobit_i = ($signed(rnode_163to164_bb1_xor_i_1_NO_SHIFT_REG) >>> 32'h1F);

// This section implements an unregistered operation.
// 
wire local_bb1_and36_lobit_i_stall_local;
wire [31:0] local_bb1_and36_lobit_i;

assign local_bb1_and36_lobit_i = (rnode_163to164_bb1_xor_i_2_NO_SHIFT_REG >> 32'h1F);

// This section implements an unregistered operation.
// 
wire local_bb1__15_i_stall_local;
wire [31:0] local_bb1__15_i;

assign local_bb1__15_i = (local_bb1_lnot23_i ? 32'h0 : ((local_bb1_shl65_i & 32'h7FFFFF8) | 32'h4000000));

// This section implements an unregistered operation.
// 
wire local_bb1_var__u4_stall_local;
wire local_bb1_var__u4;

assign local_bb1_var__u4 = ((local_bb1_var__u3 & 32'hFF) == 32'hFF);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp69_i_stall_local;
wire local_bb1_cmp69_i;

assign local_bb1_cmp69_i = ((local_bb1_and68_i & 32'hFF) > 32'h1F);

// This section implements an unregistered operation.
// 
wire local_bb1_lnot30_not_i_stall_local;
wire local_bb1_lnot30_not_i;

assign local_bb1_lnot30_not_i = (local_bb1_lnot30_i ^ 1'b1);

// This section implements an unregistered operation.
// 
wire local_bb1_shl_i_stall_local;
wire [31:0] local_bb1_shl_i;

assign local_bb1_shl_i = ((local_bb1_or_i & 32'h3FFFFF8) | 32'h4000000);

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_165to166_bb1_and35_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and35_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1_and35_i_0_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and35_i_0_reg_166_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1_and35_i_0_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and35_i_0_valid_out_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and35_i_0_stall_in_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and35_i_0_stall_out_reg_166_NO_SHIFT_REG;

acl_data_fifo rnode_165to166_bb1_and35_i_0_reg_166_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_165to166_bb1_and35_i_0_reg_166_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_165to166_bb1_and35_i_0_stall_in_reg_166_NO_SHIFT_REG),
	.valid_out(rnode_165to166_bb1_and35_i_0_valid_out_reg_166_NO_SHIFT_REG),
	.stall_out(rnode_165to166_bb1_and35_i_0_stall_out_reg_166_NO_SHIFT_REG),
	.data_in((rnode_164to165_bb1_and35_i_0_NO_SHIFT_REG & 32'h80000000)),
	.data_out(rnode_165to166_bb1_and35_i_0_reg_166_NO_SHIFT_REG)
);

defparam rnode_165to166_bb1_and35_i_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_and35_i_0_reg_166_fifo.DATA_WIDTH = 32;
defparam rnode_165to166_bb1_and35_i_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_and35_i_0_reg_166_fifo.IMPL = "shift_reg";

assign rnode_165to166_bb1_and35_i_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_and35_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_and35_i_0_NO_SHIFT_REG = rnode_165to166_bb1_and35_i_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_and35_i_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_and35_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// This section implements an unregistered operation.
// 
wire local_bb1_and72_i_stall_local;
wire [31:0] local_bb1_and72_i;

assign local_bb1_and72_i = ((local_bb1__15_i & 32'h7FFFFF8) >> 32'h3);

// This section implements an unregistered operation.
// 
wire local_bb1_and75_i_stall_local;
wire [31:0] local_bb1_and75_i;

assign local_bb1_and75_i = ((local_bb1__15_i & 32'h7FFFFF8) & 32'hF0);

// This section implements an unregistered operation.
// 
wire local_bb1_and78_i_stall_local;
wire [31:0] local_bb1_and78_i;

assign local_bb1_and78_i = ((local_bb1__15_i & 32'h7FFFFF8) & 32'hF00);

// This section implements an unregistered operation.
// 
wire local_bb1_and90_i_stall_local;
wire [31:0] local_bb1_and90_i;

assign local_bb1_and90_i = ((local_bb1__15_i & 32'h7FFFFF8) & 32'h7000000);

// This section implements an unregistered operation.
// 
wire local_bb1_and87_i_stall_local;
wire [31:0] local_bb1_and87_i;

assign local_bb1_and87_i = ((local_bb1__15_i & 32'h7FFFFF8) & 32'hF00000);

// This section implements an unregistered operation.
// 
wire local_bb1_and84_i_stall_local;
wire [31:0] local_bb1_and84_i;

assign local_bb1_and84_i = ((local_bb1__15_i & 32'h7FFFFF8) & 32'hF0000);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u5_stall_local;
wire [31:0] local_bb1_var__u5;

assign local_bb1_var__u5 = ((local_bb1__15_i & 32'h7FFFFF8) & 32'hFFF8);

// This section implements an unregistered operation.
// 
wire local_bb1_align_0_i_stall_local;
wire [31:0] local_bb1_align_0_i;

assign local_bb1_align_0_i = (local_bb1_cmp69_i ? 32'h1F : (local_bb1_and68_i & 32'hFF));

// This section implements an unregistered operation.
// 
wire local_bb1_and72_tr_i_stall_local;
wire [7:0] local_bb1_and72_tr_i;
wire [31:0] local_bb1_and72_tr_i$ps;

assign local_bb1_and72_tr_i$ps = (local_bb1_and72_i & 32'hFFFFFF);
assign local_bb1_and72_tr_i = local_bb1_and72_tr_i$ps[7:0];

// This section implements an unregistered operation.
// 
wire local_bb1_cmp76_i_stall_local;
wire local_bb1_cmp76_i;

assign local_bb1_cmp76_i = ((local_bb1_and75_i & 32'hF0) != 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp79_i_stall_local;
wire local_bb1_cmp79_i;

assign local_bb1_cmp79_i = ((local_bb1_and78_i & 32'hF00) != 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp91_i_stall_local;
wire local_bb1_cmp91_i;

assign local_bb1_cmp91_i = ((local_bb1_and90_i & 32'h7000000) != 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp88_i_stall_local;
wire local_bb1_cmp88_i;

assign local_bb1_cmp88_i = ((local_bb1_and87_i & 32'hF00000) != 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp85_i_stall_local;
wire local_bb1_cmp85_i;

assign local_bb1_cmp85_i = ((local_bb1_and84_i & 32'hF0000) != 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u6_stall_local;
wire local_bb1_var__u6;

assign local_bb1_var__u6 = ((local_bb1_var__u5 & 32'hFFF8) != 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_and93_i_stall_local;
wire [31:0] local_bb1_and93_i;

assign local_bb1_and93_i = ((local_bb1_align_0_i & 32'hFF) & 32'h1C);

// This section implements an unregistered operation.
// 
wire local_bb1_and95_i_stall_local;
wire [31:0] local_bb1_and95_i;

assign local_bb1_and95_i = ((local_bb1_align_0_i & 32'hFF) & 32'h10);

// This section implements an unregistered operation.
// 
wire local_bb1_and112_i_stall_local;
wire [31:0] local_bb1_and112_i;

assign local_bb1_and112_i = ((local_bb1_align_0_i & 32'hFF) & 32'h8);

// This section implements an unregistered operation.
// 
wire local_bb1_and125_i_stall_local;
wire [31:0] local_bb1_and125_i;

assign local_bb1_and125_i = ((local_bb1_align_0_i & 32'hFF) & 32'h4);

// This section implements an unregistered operation.
// 
wire local_bb1_and143_i_stall_local;
wire [31:0] local_bb1_and143_i;

assign local_bb1_and143_i = ((local_bb1_align_0_i & 32'hFF) & 32'h3);

// This section implements an unregistered operation.
// 
wire local_bb1_frombool74_i_stall_local;
wire [7:0] local_bb1_frombool74_i;

assign local_bb1_frombool74_i = (local_bb1_and72_tr_i & 8'h1);

// This section implements an unregistered operation.
// 
wire local_bb1_frombool106_i_stall_local;
wire [7:0] local_bb1_frombool106_i;

assign local_bb1_frombool106_i[7:1] = 7'h0;
assign local_bb1_frombool106_i[0] = local_bb1_cmp85_i;

// This section implements an unregistered operation.
// 
wire local_bb1_conv_i_stall_local;
wire [31:0] local_bb1_conv_i;

assign local_bb1_conv_i[31:1] = 31'h0;
assign local_bb1_conv_i[0] = local_bb1_var__u6;

// This section implements an unregistered operation.
// 
wire local_bb1_cmp96_i_stall_local;
wire local_bb1_cmp96_i;

assign local_bb1_cmp96_i = ((local_bb1_and95_i & 32'h10) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp113_i_stall_local;
wire local_bb1_cmp113_i;

assign local_bb1_cmp113_i = ((local_bb1_and112_i & 32'h8) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp126_not_i_stall_local;
wire local_bb1_cmp126_not_i;

assign local_bb1_cmp126_not_i = ((local_bb1_and125_i & 32'h4) != 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1__16_i_stall_local;
wire [7:0] local_bb1__16_i;

assign local_bb1__16_i = (local_bb1_cmp96_i ? (local_bb1_frombool74_i & 8'h1) : (local_bb1_frombool106_i & 8'h1));

// This section implements an unregistered operation.
// 
wire local_bb1__17_v_i_stall_local;
wire local_bb1__17_v_i;

assign local_bb1__17_v_i = (local_bb1_cmp96_i ? local_bb1_cmp76_i : local_bb1_cmp88_i);

// This section implements an unregistered operation.
// 
wire local_bb1__18_v_i_stall_local;
wire local_bb1__18_v_i;

assign local_bb1__18_v_i = (local_bb1_cmp96_i ? local_bb1_cmp79_i : local_bb1_cmp91_i);

// This section implements an unregistered operation.
// 
wire local_bb1__19_i_stall_local;
wire [31:0] local_bb1__19_i;

assign local_bb1__19_i = (local_bb1_cmp96_i ? 32'h0 : (local_bb1_conv_i & 32'h1));

// This section implements an unregistered operation.
// 
wire local_bb1__17_i_stall_local;
wire [7:0] local_bb1__17_i;

assign local_bb1__17_i[7:1] = 7'h0;
assign local_bb1__17_i[0] = local_bb1__17_v_i;

// This section implements an unregistered operation.
// 
wire local_bb1__18_i_stall_local;
wire [7:0] local_bb1__18_i;

assign local_bb1__18_i[7:1] = 7'h0;
assign local_bb1__18_i[0] = local_bb1__18_v_i;

// This section implements an unregistered operation.
// 
wire local_bb1_var__u7_stall_local;
wire [7:0] local_bb1_var__u7;

assign local_bb1_var__u7 = ((local_bb1__17_i & 8'h1) | (local_bb1__16_i & 8'h1));

// This section implements an unregistered operation.
// 
wire local_bb1__20_i_stall_local;
wire [7:0] local_bb1__20_i;

assign local_bb1__20_i = (local_bb1_cmp113_i ? (local_bb1__16_i & 8'h1) : (local_bb1__18_i & 8'h1));

// This section implements an unregistered operation.
// 
wire local_bb1_conv118_i_stall_local;
wire [31:0] local_bb1_conv118_i;

assign local_bb1_conv118_i[31:8] = 24'h0;
assign local_bb1_conv118_i[7:0] = (local_bb1_var__u7 & 8'h1);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u8_stall_local;
wire [7:0] local_bb1_var__u8;

assign local_bb1_var__u8 = ((local_bb1__20_i & 8'h1) & 8'h1);

// This section implements an unregistered operation.
// 
wire local_bb1_or119_i_stall_local;
wire [31:0] local_bb1_or119_i;

assign local_bb1_or119_i = (local_bb1_cmp113_i ? 32'h0 : (local_bb1_conv118_i & 32'h1));

// This section implements an unregistered operation.
// 
wire local_bb1_conv129_i_stall_local;
wire [31:0] local_bb1_conv129_i;

assign local_bb1_conv129_i[31:8] = 24'h0;
assign local_bb1_conv129_i[7:0] = (local_bb1_var__u8 & 8'h1);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_3_i_stall_local;
wire [31:0] local_bb1_reduction_3_i;

assign local_bb1_reduction_3_i = ((local_bb1__19_i & 32'h1) | (local_bb1_or119_i & 32'h1));

// This section implements an unregistered operation.
// 
wire local_bb1_shr16_i_valid_out_2;
wire local_bb1_shr16_i_stall_in_2;
wire local_bb1_cmp27_i_valid_out;
wire local_bb1_cmp27_i_stall_in;
wire local_bb1__15_i_valid_out_7;
wire local_bb1__15_i_stall_in_7;
wire local_bb1_var__u4_valid_out;
wire local_bb1_var__u4_stall_in;
wire local_bb1_lnot33_not_i_valid_out;
wire local_bb1_lnot33_not_i_stall_in;
wire local_bb1_and93_i_valid_out;
wire local_bb1_and93_i_stall_in;
wire local_bb1_and143_i_valid_out;
wire local_bb1_and143_i_stall_in;
wire local_bb1_or130_i_valid_out;
wire local_bb1_or130_i_stall_in;
wire local_bb1_reduction_3_i_valid_out;
wire local_bb1_reduction_3_i_stall_in;
wire local_bb1_or130_i_inputs_ready;
wire local_bb1_or130_i_stall_local;
wire [31:0] local_bb1_or130_i;

assign local_bb1_or130_i_inputs_ready = (rnode_162to163_bb1__9_i_0_valid_out_0_NO_SHIFT_REG & rnode_162to163_bb1__10_i_0_valid_out_0_NO_SHIFT_REG & rnode_162to163_bb1__9_i_0_valid_out_1_NO_SHIFT_REG);
assign local_bb1_or130_i = (local_bb1_cmp126_not_i ? (local_bb1_conv129_i & 32'h1) : 32'h0);
assign local_bb1_shr16_i_valid_out_2 = 1'b1;
assign local_bb1_cmp27_i_valid_out = 1'b1;
assign local_bb1__15_i_valid_out_7 = 1'b1;
assign local_bb1_var__u4_valid_out = 1'b1;
assign local_bb1_lnot33_not_i_valid_out = 1'b1;
assign local_bb1_and93_i_valid_out = 1'b1;
assign local_bb1_and143_i_valid_out = 1'b1;
assign local_bb1_or130_i_valid_out = 1'b1;
assign local_bb1_reduction_3_i_valid_out = 1'b1;
assign rnode_162to163_bb1__9_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_162to163_bb1__10_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_162to163_bb1__9_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_163to164_bb1_shr16_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_shr16_i_0_stall_in_0_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_shr16_i_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_shr16_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_163to164_bb1_shr16_i_0_stall_in_1_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_shr16_i_1_NO_SHIFT_REG;
 logic rnode_163to164_bb1_shr16_i_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_shr16_i_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_shr16_i_0_valid_out_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_shr16_i_0_stall_in_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_shr16_i_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_163to164_bb1_shr16_i_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_163to164_bb1_shr16_i_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_163to164_bb1_shr16_i_0_stall_in_0_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_163to164_bb1_shr16_i_0_valid_out_0_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_163to164_bb1_shr16_i_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in((local_bb1_shr16_i & 32'h1FF)),
	.data_out(rnode_163to164_bb1_shr16_i_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_163to164_bb1_shr16_i_0_reg_164_fifo.DEPTH = 1;
defparam rnode_163to164_bb1_shr16_i_0_reg_164_fifo.DATA_WIDTH = 32;
defparam rnode_163to164_bb1_shr16_i_0_reg_164_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_163to164_bb1_shr16_i_0_reg_164_fifo.IMPL = "shift_reg";

assign rnode_163to164_bb1_shr16_i_0_reg_164_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_shr16_i_stall_in_2 = 1'b0;
assign rnode_163to164_bb1_shr16_i_0_stall_in_0_reg_164_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_shr16_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_shr16_i_0_NO_SHIFT_REG = rnode_163to164_bb1_shr16_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_shr16_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_shr16_i_1_NO_SHIFT_REG = rnode_163to164_bb1_shr16_i_0_reg_164_NO_SHIFT_REG;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_163to164_bb1_cmp27_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_cmp27_i_0_stall_in_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_cmp27_i_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_cmp27_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_163to164_bb1_cmp27_i_0_stall_in_1_NO_SHIFT_REG;
 logic rnode_163to164_bb1_cmp27_i_1_NO_SHIFT_REG;
 logic rnode_163to164_bb1_cmp27_i_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic rnode_163to164_bb1_cmp27_i_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_cmp27_i_0_valid_out_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_cmp27_i_0_stall_in_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_cmp27_i_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_163to164_bb1_cmp27_i_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_163to164_bb1_cmp27_i_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_163to164_bb1_cmp27_i_0_stall_in_0_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_163to164_bb1_cmp27_i_0_valid_out_0_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_163to164_bb1_cmp27_i_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in(local_bb1_cmp27_i),
	.data_out(rnode_163to164_bb1_cmp27_i_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_163to164_bb1_cmp27_i_0_reg_164_fifo.DEPTH = 1;
defparam rnode_163to164_bb1_cmp27_i_0_reg_164_fifo.DATA_WIDTH = 1;
defparam rnode_163to164_bb1_cmp27_i_0_reg_164_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_163to164_bb1_cmp27_i_0_reg_164_fifo.IMPL = "shift_reg";

assign rnode_163to164_bb1_cmp27_i_0_reg_164_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp27_i_stall_in = 1'b0;
assign rnode_163to164_bb1_cmp27_i_0_stall_in_0_reg_164_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_cmp27_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_cmp27_i_0_NO_SHIFT_REG = rnode_163to164_bb1_cmp27_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_cmp27_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_cmp27_i_1_NO_SHIFT_REG = rnode_163to164_bb1_cmp27_i_0_reg_164_NO_SHIFT_REG;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_163to164_bb1__15_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_163to164_bb1__15_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1__15_i_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1__15_i_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1__15_i_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1__15_i_0_valid_out_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1__15_i_0_stall_in_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1__15_i_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_163to164_bb1__15_i_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_163to164_bb1__15_i_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_163to164_bb1__15_i_0_stall_in_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_163to164_bb1__15_i_0_valid_out_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_163to164_bb1__15_i_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in((local_bb1__15_i & 32'h7FFFFF8)),
	.data_out(rnode_163to164_bb1__15_i_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_163to164_bb1__15_i_0_reg_164_fifo.DEPTH = 1;
defparam rnode_163to164_bb1__15_i_0_reg_164_fifo.DATA_WIDTH = 32;
defparam rnode_163to164_bb1__15_i_0_reg_164_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_163to164_bb1__15_i_0_reg_164_fifo.IMPL = "shift_reg";

assign rnode_163to164_bb1__15_i_0_reg_164_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__15_i_stall_in_7 = 1'b0;
assign rnode_163to164_bb1__15_i_0_NO_SHIFT_REG = rnode_163to164_bb1__15_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1__15_i_0_stall_in_reg_164_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1__15_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_163to164_bb1_var__u4_0_valid_out_NO_SHIFT_REG;
 logic rnode_163to164_bb1_var__u4_0_stall_in_NO_SHIFT_REG;
 logic rnode_163to164_bb1_var__u4_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_var__u4_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic rnode_163to164_bb1_var__u4_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_var__u4_0_valid_out_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_var__u4_0_stall_in_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_var__u4_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_163to164_bb1_var__u4_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_163to164_bb1_var__u4_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_163to164_bb1_var__u4_0_stall_in_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_163to164_bb1_var__u4_0_valid_out_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_163to164_bb1_var__u4_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in(local_bb1_var__u4),
	.data_out(rnode_163to164_bb1_var__u4_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_163to164_bb1_var__u4_0_reg_164_fifo.DEPTH = 1;
defparam rnode_163to164_bb1_var__u4_0_reg_164_fifo.DATA_WIDTH = 1;
defparam rnode_163to164_bb1_var__u4_0_reg_164_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_163to164_bb1_var__u4_0_reg_164_fifo.IMPL = "shift_reg";

assign rnode_163to164_bb1_var__u4_0_reg_164_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_var__u4_stall_in = 1'b0;
assign rnode_163to164_bb1_var__u4_0_NO_SHIFT_REG = rnode_163to164_bb1_var__u4_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_var__u4_0_stall_in_reg_164_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_var__u4_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_163to164_bb1_lnot33_not_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_163to164_bb1_lnot33_not_i_0_stall_in_NO_SHIFT_REG;
 logic rnode_163to164_bb1_lnot33_not_i_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_lnot33_not_i_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic rnode_163to164_bb1_lnot33_not_i_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_lnot33_not_i_0_valid_out_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_lnot33_not_i_0_stall_in_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_lnot33_not_i_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_163to164_bb1_lnot33_not_i_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_163to164_bb1_lnot33_not_i_0_stall_in_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_163to164_bb1_lnot33_not_i_0_valid_out_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_163to164_bb1_lnot33_not_i_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in(local_bb1_lnot33_not_i),
	.data_out(rnode_163to164_bb1_lnot33_not_i_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo.DEPTH = 1;
defparam rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo.DATA_WIDTH = 1;
defparam rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo.IMPL = "shift_reg";

assign rnode_163to164_bb1_lnot33_not_i_0_reg_164_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_lnot33_not_i_stall_in = 1'b0;
assign rnode_163to164_bb1_lnot33_not_i_0_NO_SHIFT_REG = rnode_163to164_bb1_lnot33_not_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_lnot33_not_i_0_stall_in_reg_164_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_lnot33_not_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_163to164_bb1_and93_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and93_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_and93_i_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and93_i_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_and93_i_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and93_i_0_valid_out_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and93_i_0_stall_in_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and93_i_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_163to164_bb1_and93_i_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_163to164_bb1_and93_i_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_163to164_bb1_and93_i_0_stall_in_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_163to164_bb1_and93_i_0_valid_out_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_163to164_bb1_and93_i_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in((local_bb1_and93_i & 32'h1C)),
	.data_out(rnode_163to164_bb1_and93_i_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_163to164_bb1_and93_i_0_reg_164_fifo.DEPTH = 1;
defparam rnode_163to164_bb1_and93_i_0_reg_164_fifo.DATA_WIDTH = 32;
defparam rnode_163to164_bb1_and93_i_0_reg_164_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_163to164_bb1_and93_i_0_reg_164_fifo.IMPL = "shift_reg";

assign rnode_163to164_bb1_and93_i_0_reg_164_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_and93_i_stall_in = 1'b0;
assign rnode_163to164_bb1_and93_i_0_NO_SHIFT_REG = rnode_163to164_bb1_and93_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_and93_i_0_stall_in_reg_164_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_and93_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_163to164_bb1_and143_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and143_i_0_stall_in_0_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_and143_i_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and143_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and143_i_0_stall_in_1_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_and143_i_1_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and143_i_0_valid_out_2_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and143_i_0_stall_in_2_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_and143_i_2_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and143_i_0_valid_out_3_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and143_i_0_stall_in_3_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_and143_i_3_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and143_i_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_and143_i_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and143_i_0_valid_out_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and143_i_0_stall_in_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_and143_i_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_163to164_bb1_and143_i_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_163to164_bb1_and143_i_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_163to164_bb1_and143_i_0_stall_in_0_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_163to164_bb1_and143_i_0_valid_out_0_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_163to164_bb1_and143_i_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in((local_bb1_and143_i & 32'h3)),
	.data_out(rnode_163to164_bb1_and143_i_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_163to164_bb1_and143_i_0_reg_164_fifo.DEPTH = 1;
defparam rnode_163to164_bb1_and143_i_0_reg_164_fifo.DATA_WIDTH = 32;
defparam rnode_163to164_bb1_and143_i_0_reg_164_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_163to164_bb1_and143_i_0_reg_164_fifo.IMPL = "shift_reg";

assign rnode_163to164_bb1_and143_i_0_reg_164_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_and143_i_stall_in = 1'b0;
assign rnode_163to164_bb1_and143_i_0_stall_in_0_reg_164_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_and143_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_and143_i_0_NO_SHIFT_REG = rnode_163to164_bb1_and143_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_and143_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_and143_i_1_NO_SHIFT_REG = rnode_163to164_bb1_and143_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_and143_i_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_and143_i_2_NO_SHIFT_REG = rnode_163to164_bb1_and143_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_and143_i_0_valid_out_3_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_and143_i_3_NO_SHIFT_REG = rnode_163to164_bb1_and143_i_0_reg_164_NO_SHIFT_REG;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_163to164_bb1_or130_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_163to164_bb1_or130_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_or130_i_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_or130_i_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_or130_i_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_or130_i_0_valid_out_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_or130_i_0_stall_in_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_or130_i_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_163to164_bb1_or130_i_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_163to164_bb1_or130_i_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_163to164_bb1_or130_i_0_stall_in_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_163to164_bb1_or130_i_0_valid_out_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_163to164_bb1_or130_i_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in((local_bb1_or130_i & 32'h1)),
	.data_out(rnode_163to164_bb1_or130_i_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_163to164_bb1_or130_i_0_reg_164_fifo.DEPTH = 1;
defparam rnode_163to164_bb1_or130_i_0_reg_164_fifo.DATA_WIDTH = 32;
defparam rnode_163to164_bb1_or130_i_0_reg_164_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_163to164_bb1_or130_i_0_reg_164_fifo.IMPL = "shift_reg";

assign rnode_163to164_bb1_or130_i_0_reg_164_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_or130_i_stall_in = 1'b0;
assign rnode_163to164_bb1_or130_i_0_NO_SHIFT_REG = rnode_163to164_bb1_or130_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_or130_i_0_stall_in_reg_164_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_or130_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_163to164_bb1_reduction_3_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_163to164_bb1_reduction_3_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_reduction_3_i_0_NO_SHIFT_REG;
 logic rnode_163to164_bb1_reduction_3_i_0_reg_164_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_163to164_bb1_reduction_3_i_0_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_reduction_3_i_0_valid_out_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_reduction_3_i_0_stall_in_reg_164_NO_SHIFT_REG;
 logic rnode_163to164_bb1_reduction_3_i_0_stall_out_reg_164_NO_SHIFT_REG;

acl_data_fifo rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_163to164_bb1_reduction_3_i_0_reg_164_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_163to164_bb1_reduction_3_i_0_stall_in_reg_164_NO_SHIFT_REG),
	.valid_out(rnode_163to164_bb1_reduction_3_i_0_valid_out_reg_164_NO_SHIFT_REG),
	.stall_out(rnode_163to164_bb1_reduction_3_i_0_stall_out_reg_164_NO_SHIFT_REG),
	.data_in((local_bb1_reduction_3_i & 32'h1)),
	.data_out(rnode_163to164_bb1_reduction_3_i_0_reg_164_NO_SHIFT_REG)
);

defparam rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo.DEPTH = 1;
defparam rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo.DATA_WIDTH = 32;
defparam rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo.IMPL = "shift_reg";

assign rnode_163to164_bb1_reduction_3_i_0_reg_164_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_reduction_3_i_stall_in = 1'b0;
assign rnode_163to164_bb1_reduction_3_i_0_NO_SHIFT_REG = rnode_163to164_bb1_reduction_3_i_0_reg_164_NO_SHIFT_REG;
assign rnode_163to164_bb1_reduction_3_i_0_stall_in_reg_164_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_reduction_3_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// This section implements an unregistered operation.
// 
wire local_bb1_and17_i_stall_local;
wire [31:0] local_bb1_and17_i;

assign local_bb1_and17_i = ((rnode_163to164_bb1_shr16_i_0_NO_SHIFT_REG & 32'h1FF) & 32'hFF);

// Register node:
//  * latency = 2
//  * capacity = 2
 logic rnode_164to166_bb1_shr16_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_164to166_bb1_shr16_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_164to166_bb1_shr16_i_0_NO_SHIFT_REG;
 logic rnode_164to166_bb1_shr16_i_0_reg_166_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_164to166_bb1_shr16_i_0_reg_166_NO_SHIFT_REG;
 logic rnode_164to166_bb1_shr16_i_0_valid_out_reg_166_NO_SHIFT_REG;
 logic rnode_164to166_bb1_shr16_i_0_stall_in_reg_166_NO_SHIFT_REG;
 logic rnode_164to166_bb1_shr16_i_0_stall_out_reg_166_NO_SHIFT_REG;

acl_data_fifo rnode_164to166_bb1_shr16_i_0_reg_166_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_164to166_bb1_shr16_i_0_reg_166_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_164to166_bb1_shr16_i_0_stall_in_reg_166_NO_SHIFT_REG),
	.valid_out(rnode_164to166_bb1_shr16_i_0_valid_out_reg_166_NO_SHIFT_REG),
	.stall_out(rnode_164to166_bb1_shr16_i_0_stall_out_reg_166_NO_SHIFT_REG),
	.data_in((rnode_163to164_bb1_shr16_i_1_NO_SHIFT_REG & 32'h1FF)),
	.data_out(rnode_164to166_bb1_shr16_i_0_reg_166_NO_SHIFT_REG)
);

defparam rnode_164to166_bb1_shr16_i_0_reg_166_fifo.DEPTH = 2;
defparam rnode_164to166_bb1_shr16_i_0_reg_166_fifo.DATA_WIDTH = 32;
defparam rnode_164to166_bb1_shr16_i_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_164to166_bb1_shr16_i_0_reg_166_fifo.IMPL = "shift_reg";

assign rnode_164to166_bb1_shr16_i_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_163to164_bb1_shr16_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_164to166_bb1_shr16_i_0_NO_SHIFT_REG = rnode_164to166_bb1_shr16_i_0_reg_166_NO_SHIFT_REG;
assign rnode_164to166_bb1_shr16_i_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_164to166_bb1_shr16_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// This section implements an unregistered operation.
// 
wire local_bb1_brmerge_not_i_stall_local;
wire local_bb1_brmerge_not_i;

assign local_bb1_brmerge_not_i = (rnode_163to164_bb1_cmp27_i_0_NO_SHIFT_REG & rnode_163to164_bb1_lnot33_not_i_0_NO_SHIFT_REG);

// This section implements an unregistered operation.
// 
wire local_bb1_shr94_i_stall_local;
wire [31:0] local_bb1_shr94_i;

assign local_bb1_shr94_i = ((rnode_163to164_bb1__15_i_0_NO_SHIFT_REG & 32'h7FFFFF8) >> (rnode_163to164_bb1_and93_i_0_NO_SHIFT_REG & 32'h1C));

// This section implements an unregistered operation.
// 
wire local_bb1_cmp146_i_stall_local;
wire local_bb1_cmp146_i;

assign local_bb1_cmp146_i = ((rnode_163to164_bb1_and143_i_1_NO_SHIFT_REG & 32'h3) == 32'h3);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp157_i_stall_local;
wire local_bb1_cmp157_i;

assign local_bb1_cmp157_i = ((rnode_163to164_bb1_and143_i_2_NO_SHIFT_REG & 32'h3) == 32'h2);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp166_i_stall_local;
wire local_bb1_cmp166_i;

assign local_bb1_cmp166_i = ((rnode_163to164_bb1_and143_i_3_NO_SHIFT_REG & 32'h3) == 32'h1);

// This section implements an unregistered operation.
// 
wire local_bb1_lnot_i_stall_local;
wire local_bb1_lnot_i;

assign local_bb1_lnot_i = ((local_bb1_and17_i & 32'hFF) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp25_i_stall_local;
wire local_bb1_cmp25_i;

assign local_bb1_cmp25_i = ((local_bb1_and17_i & 32'hFF) == 32'hFF);

// This section implements an unregistered operation.
// 
wire local_bb1_brmerge_not_not_i_stall_local;
wire local_bb1_brmerge_not_not_i;

assign local_bb1_brmerge_not_not_i = (local_bb1_brmerge_not_i ^ 1'b1);

// This section implements an unregistered operation.
// 
wire local_bb1_and136_i_stall_local;
wire [31:0] local_bb1_and136_i;

assign local_bb1_and136_i = (local_bb1_shr94_i >> 32'h1);

// This section implements an unregistered operation.
// 
wire local_bb1_shr144_i_stall_local;
wire [31:0] local_bb1_shr144_i;

assign local_bb1_shr144_i = (local_bb1_shr94_i >> (rnode_163to164_bb1_and143_i_0_NO_SHIFT_REG & 32'h3));

// This section implements an unregistered operation.
// 
wire local_bb1_and140_i_stall_local;
wire [31:0] local_bb1_and140_i;

assign local_bb1_and140_i = (local_bb1_shr94_i & 32'h4);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u9_stall_local;
wire [31:0] local_bb1_var__u9;

assign local_bb1_var__u9 = (local_bb1_shr94_i & 32'h1);

// This section implements an unregistered operation.
// 
wire local_bb1__14_i_stall_local;
wire [31:0] local_bb1__14_i;

assign local_bb1__14_i = (local_bb1_lnot_i ? 32'h0 : ((local_bb1_shl_i & 32'h7FFFFF8) | 32'h4000000));

// This section implements an unregistered operation.
// 
wire local_bb1_cmp25_not_i_stall_local;
wire local_bb1_cmp25_not_i;

assign local_bb1_cmp25_not_i = (local_bb1_cmp25_i ^ 1'b1);

// This section implements an unregistered operation.
// 
wire local_bb1_or_cond2_not_i_stall_local;
wire local_bb1_or_cond2_not_i;

assign local_bb1_or_cond2_not_i = (local_bb1_cmp25_i & local_bb1_lnot30_not_i);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u10_stall_local;
wire local_bb1_var__u10;

assign local_bb1_var__u10 = (local_bb1_cmp25_i | rnode_163to164_bb1_cmp27_i_1_NO_SHIFT_REG);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u11_stall_local;
wire [31:0] local_bb1_var__u11;

assign local_bb1_var__u11 = ((local_bb1_and136_i & 32'h7FFFFFFF) | local_bb1_shr94_i);

// This section implements an unregistered operation.
// 
wire local_bb1_or170_i_stall_local;
wire [31:0] local_bb1_or170_i;

assign local_bb1_or170_i = (local_bb1_cmp166_i ? (local_bb1_var__u9 & 32'h1) : 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_add_i_stall_local;
wire [31:0] local_bb1_add_i;

assign local_bb1_add_i = ((local_bb1__14_i & 32'h7FFFFF8) | (local_bb1_and36_lobit_i & 32'h1));

// This section implements an unregistered operation.
// 
wire local_bb1_or_cond2_i_stall_local;
wire local_bb1_or_cond2_i;

assign local_bb1_or_cond2_i = (local_bb1_lnot30_i | local_bb1_cmp25_not_i);

// This section implements an unregistered operation.
// 
wire local_bb1__11_i_stall_local;
wire local_bb1__11_i;

assign local_bb1__11_i = (local_bb1_or_cond2_not_i | local_bb1_brmerge_not_i);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u12_stall_local;
wire [31:0] local_bb1_var__u12;

assign local_bb1_var__u12 = (local_bb1_var__u11 & 32'h1);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_1_i_stall_local;
wire local_bb1_reduction_1_i;

assign local_bb1_reduction_1_i = (local_bb1_or_cond2_i & local_bb1_brmerge_not_not_i);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u13_stall_local;
wire [31:0] local_bb1_var__u13;

assign local_bb1_var__u13 = ((local_bb1_var__u12 & 32'h1) | (local_bb1_and140_i & 32'h4));

// This section implements an unregistered operation.
// 
wire local_bb1_or163_i_stall_local;
wire [31:0] local_bb1_or163_i;

assign local_bb1_or163_i = (local_bb1_cmp157_i ? (local_bb1_var__u12 & 32'h1) : 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_2_i_stall_local;
wire local_bb1_reduction_2_i;

assign local_bb1_reduction_2_i = (rnode_163to164_bb1_var__u4_0_NO_SHIFT_REG & local_bb1_reduction_1_i);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u14_stall_local;
wire local_bb1_var__u14;

assign local_bb1_var__u14 = ((local_bb1_var__u13 & 32'h5) != 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_5_i_stall_local;
wire [31:0] local_bb1_reduction_5_i;

assign local_bb1_reduction_5_i = ((local_bb1_or163_i & 32'h1) | (local_bb1_or170_i & 32'h1));

// This section implements an unregistered operation.
// 
wire local_bb1__13_i_stall_local;
wire local_bb1__13_i;

assign local_bb1__13_i = (local_bb1_reduction_2_i ? local_bb1_cmp37_i : local_bb1__11_i);

// This section implements an unregistered operation.
// 
wire local_bb1_conv153_i_stall_local;
wire [31:0] local_bb1_conv153_i;

assign local_bb1_conv153_i[31:1] = 31'h0;
assign local_bb1_conv153_i[0] = local_bb1_var__u14;

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_7_i_stall_local;
wire [31:0] local_bb1_reduction_7_i;

assign local_bb1_reduction_7_i = (local_bb1_shr144_i | (local_bb1_reduction_5_i & 32'h1));

// This section implements an unregistered operation.
// 
wire local_bb1_or154_i_stall_local;
wire [31:0] local_bb1_or154_i;

assign local_bb1_or154_i = (local_bb1_cmp146_i ? (local_bb1_conv153_i & 32'h1) : 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_4_i_stall_local;
wire [31:0] local_bb1_reduction_4_i;

assign local_bb1_reduction_4_i = ((rnode_163to164_bb1_or130_i_0_NO_SHIFT_REG & 32'h1) | (local_bb1_or154_i & 32'h1));

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_6_i_stall_local;
wire [31:0] local_bb1_reduction_6_i;

assign local_bb1_reduction_6_i = ((rnode_163to164_bb1_reduction_3_i_0_NO_SHIFT_REG & 32'h1) | (local_bb1_reduction_4_i & 32'h1));

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_8_i_stall_local;
wire [31:0] local_bb1_reduction_8_i;

assign local_bb1_reduction_8_i = ((local_bb1_reduction_6_i & 32'h1) | local_bb1_reduction_7_i);

// This section implements an unregistered operation.
// 
wire local_bb1_xor175_i_stall_local;
wire [31:0] local_bb1_xor175_i;

assign local_bb1_xor175_i = (local_bb1_reduction_8_i ^ local_bb1_xor_lobit_i);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp37_i_valid_out_1;
wire local_bb1_cmp37_i_stall_in_1;
wire local_bb1__13_i_valid_out;
wire local_bb1__13_i_stall_in;
wire local_bb1_and17_i_valid_out_2;
wire local_bb1_and17_i_stall_in_2;
wire local_bb1_var__u10_valid_out;
wire local_bb1_var__u10_stall_in;
wire local_bb1_add178_i_valid_out;
wire local_bb1_add178_i_stall_in;
wire local_bb1_add178_i_inputs_ready;
wire local_bb1_add178_i_stall_local;
wire [31:0] local_bb1_add178_i;

assign local_bb1_add178_i_inputs_ready = (rnode_163to164_bb1_xor_i_0_valid_out_0_NO_SHIFT_REG & rnode_163to164_bb1_shr16_i_0_valid_out_0_NO_SHIFT_REG & rnode_163to164_bb1_cmp27_i_0_valid_out_1_NO_SHIFT_REG & rnode_163to164_bb1_and20_i_0_valid_out_0_NO_SHIFT_REG & rnode_163to164_bb1_and20_i_0_valid_out_1_NO_SHIFT_REG & rnode_163to164_bb1_cmp27_i_0_valid_out_0_NO_SHIFT_REG & rnode_163to164_bb1_lnot33_not_i_0_valid_out_NO_SHIFT_REG & rnode_163to164_bb1_xor_i_0_valid_out_1_NO_SHIFT_REG & rnode_163to164_bb1_xor_i_0_valid_out_2_NO_SHIFT_REG & rnode_163to164_bb1_var__u4_0_valid_out_NO_SHIFT_REG & rnode_163to164_bb1__15_i_0_valid_out_NO_SHIFT_REG & rnode_163to164_bb1_and93_i_0_valid_out_NO_SHIFT_REG & rnode_163to164_bb1_and143_i_0_valid_out_0_NO_SHIFT_REG & rnode_163to164_bb1_and143_i_0_valid_out_3_NO_SHIFT_REG & rnode_163to164_bb1_and143_i_0_valid_out_2_NO_SHIFT_REG & rnode_163to164_bb1_and143_i_0_valid_out_1_NO_SHIFT_REG & rnode_163to164_bb1_or130_i_0_valid_out_NO_SHIFT_REG & rnode_163to164_bb1_reduction_3_i_0_valid_out_NO_SHIFT_REG);
assign local_bb1_add178_i = ((local_bb1_add_i & 32'h7FFFFF9) + local_bb1_xor175_i);
assign local_bb1_cmp37_i_valid_out_1 = 1'b1;
assign local_bb1__13_i_valid_out = 1'b1;
assign local_bb1_and17_i_valid_out_2 = 1'b1;
assign local_bb1_var__u10_valid_out = 1'b1;
assign local_bb1_add178_i_valid_out = 1'b1;
assign rnode_163to164_bb1_xor_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_shr16_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_cmp27_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_and20_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_and20_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_cmp27_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_lnot33_not_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_xor_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_xor_i_0_stall_in_2_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_var__u4_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1__15_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_and93_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_and143_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_and143_i_0_stall_in_3_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_and143_i_0_stall_in_2_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_and143_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_or130_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_163to164_bb1_reduction_3_i_0_stall_in_NO_SHIFT_REG = 1'b0;

// Register node:
//  * latency = 2
//  * capacity = 2
 logic rnode_164to166_bb1_cmp37_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_164to166_bb1_cmp37_i_0_stall_in_0_NO_SHIFT_REG;
 logic rnode_164to166_bb1_cmp37_i_0_NO_SHIFT_REG;
 logic rnode_164to166_bb1_cmp37_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_164to166_bb1_cmp37_i_0_stall_in_1_NO_SHIFT_REG;
 logic rnode_164to166_bb1_cmp37_i_1_NO_SHIFT_REG;
 logic rnode_164to166_bb1_cmp37_i_0_valid_out_2_NO_SHIFT_REG;
 logic rnode_164to166_bb1_cmp37_i_0_stall_in_2_NO_SHIFT_REG;
 logic rnode_164to166_bb1_cmp37_i_2_NO_SHIFT_REG;
 logic rnode_164to166_bb1_cmp37_i_0_reg_166_inputs_ready_NO_SHIFT_REG;
 logic rnode_164to166_bb1_cmp37_i_0_reg_166_NO_SHIFT_REG;
 logic rnode_164to166_bb1_cmp37_i_0_valid_out_0_reg_166_NO_SHIFT_REG;
 logic rnode_164to166_bb1_cmp37_i_0_stall_in_0_reg_166_NO_SHIFT_REG;
 logic rnode_164to166_bb1_cmp37_i_0_stall_out_reg_166_NO_SHIFT_REG;

acl_data_fifo rnode_164to166_bb1_cmp37_i_0_reg_166_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_164to166_bb1_cmp37_i_0_reg_166_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_164to166_bb1_cmp37_i_0_stall_in_0_reg_166_NO_SHIFT_REG),
	.valid_out(rnode_164to166_bb1_cmp37_i_0_valid_out_0_reg_166_NO_SHIFT_REG),
	.stall_out(rnode_164to166_bb1_cmp37_i_0_stall_out_reg_166_NO_SHIFT_REG),
	.data_in(local_bb1_cmp37_i),
	.data_out(rnode_164to166_bb1_cmp37_i_0_reg_166_NO_SHIFT_REG)
);

defparam rnode_164to166_bb1_cmp37_i_0_reg_166_fifo.DEPTH = 2;
defparam rnode_164to166_bb1_cmp37_i_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_164to166_bb1_cmp37_i_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_164to166_bb1_cmp37_i_0_reg_166_fifo.IMPL = "shift_reg";

assign rnode_164to166_bb1_cmp37_i_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp37_i_stall_in_1 = 1'b0;
assign rnode_164to166_bb1_cmp37_i_0_stall_in_0_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_164to166_bb1_cmp37_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_164to166_bb1_cmp37_i_0_NO_SHIFT_REG = rnode_164to166_bb1_cmp37_i_0_reg_166_NO_SHIFT_REG;
assign rnode_164to166_bb1_cmp37_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_164to166_bb1_cmp37_i_1_NO_SHIFT_REG = rnode_164to166_bb1_cmp37_i_0_reg_166_NO_SHIFT_REG;
assign rnode_164to166_bb1_cmp37_i_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_164to166_bb1_cmp37_i_2_NO_SHIFT_REG = rnode_164to166_bb1_cmp37_i_0_reg_166_NO_SHIFT_REG;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_164to165_bb1__13_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_164to165_bb1__13_i_0_stall_in_NO_SHIFT_REG;
 logic rnode_164to165_bb1__13_i_0_NO_SHIFT_REG;
 logic rnode_164to165_bb1__13_i_0_reg_165_inputs_ready_NO_SHIFT_REG;
 logic rnode_164to165_bb1__13_i_0_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1__13_i_0_valid_out_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1__13_i_0_stall_in_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1__13_i_0_stall_out_reg_165_NO_SHIFT_REG;

acl_data_fifo rnode_164to165_bb1__13_i_0_reg_165_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_164to165_bb1__13_i_0_reg_165_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_164to165_bb1__13_i_0_stall_in_reg_165_NO_SHIFT_REG),
	.valid_out(rnode_164to165_bb1__13_i_0_valid_out_reg_165_NO_SHIFT_REG),
	.stall_out(rnode_164to165_bb1__13_i_0_stall_out_reg_165_NO_SHIFT_REG),
	.data_in(local_bb1__13_i),
	.data_out(rnode_164to165_bb1__13_i_0_reg_165_NO_SHIFT_REG)
);

defparam rnode_164to165_bb1__13_i_0_reg_165_fifo.DEPTH = 1;
defparam rnode_164to165_bb1__13_i_0_reg_165_fifo.DATA_WIDTH = 1;
defparam rnode_164to165_bb1__13_i_0_reg_165_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_164to165_bb1__13_i_0_reg_165_fifo.IMPL = "shift_reg";

assign rnode_164to165_bb1__13_i_0_reg_165_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__13_i_stall_in = 1'b0;
assign rnode_164to165_bb1__13_i_0_NO_SHIFT_REG = rnode_164to165_bb1__13_i_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1__13_i_0_stall_in_reg_165_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1__13_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 2
//  * capacity = 2
 logic rnode_164to166_bb1_and17_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_164to166_bb1_and17_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_164to166_bb1_and17_i_0_NO_SHIFT_REG;
 logic rnode_164to166_bb1_and17_i_0_reg_166_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_164to166_bb1_and17_i_0_reg_166_NO_SHIFT_REG;
 logic rnode_164to166_bb1_and17_i_0_valid_out_reg_166_NO_SHIFT_REG;
 logic rnode_164to166_bb1_and17_i_0_stall_in_reg_166_NO_SHIFT_REG;
 logic rnode_164to166_bb1_and17_i_0_stall_out_reg_166_NO_SHIFT_REG;

acl_data_fifo rnode_164to166_bb1_and17_i_0_reg_166_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_164to166_bb1_and17_i_0_reg_166_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_164to166_bb1_and17_i_0_stall_in_reg_166_NO_SHIFT_REG),
	.valid_out(rnode_164to166_bb1_and17_i_0_valid_out_reg_166_NO_SHIFT_REG),
	.stall_out(rnode_164to166_bb1_and17_i_0_stall_out_reg_166_NO_SHIFT_REG),
	.data_in((local_bb1_and17_i & 32'hFF)),
	.data_out(rnode_164to166_bb1_and17_i_0_reg_166_NO_SHIFT_REG)
);

defparam rnode_164to166_bb1_and17_i_0_reg_166_fifo.DEPTH = 2;
defparam rnode_164to166_bb1_and17_i_0_reg_166_fifo.DATA_WIDTH = 32;
defparam rnode_164to166_bb1_and17_i_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_164to166_bb1_and17_i_0_reg_166_fifo.IMPL = "shift_reg";

assign rnode_164to166_bb1_and17_i_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_and17_i_stall_in_2 = 1'b0;
assign rnode_164to166_bb1_and17_i_0_NO_SHIFT_REG = rnode_164to166_bb1_and17_i_0_reg_166_NO_SHIFT_REG;
assign rnode_164to166_bb1_and17_i_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_164to166_bb1_and17_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_164to165_bb1_var__u10_0_valid_out_NO_SHIFT_REG;
 logic rnode_164to165_bb1_var__u10_0_stall_in_NO_SHIFT_REG;
 logic rnode_164to165_bb1_var__u10_0_NO_SHIFT_REG;
 logic rnode_164to165_bb1_var__u10_0_reg_165_inputs_ready_NO_SHIFT_REG;
 logic rnode_164to165_bb1_var__u10_0_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1_var__u10_0_valid_out_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1_var__u10_0_stall_in_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1_var__u10_0_stall_out_reg_165_NO_SHIFT_REG;

acl_data_fifo rnode_164to165_bb1_var__u10_0_reg_165_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_164to165_bb1_var__u10_0_reg_165_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_164to165_bb1_var__u10_0_stall_in_reg_165_NO_SHIFT_REG),
	.valid_out(rnode_164to165_bb1_var__u10_0_valid_out_reg_165_NO_SHIFT_REG),
	.stall_out(rnode_164to165_bb1_var__u10_0_stall_out_reg_165_NO_SHIFT_REG),
	.data_in(local_bb1_var__u10),
	.data_out(rnode_164to165_bb1_var__u10_0_reg_165_NO_SHIFT_REG)
);

defparam rnode_164to165_bb1_var__u10_0_reg_165_fifo.DEPTH = 1;
defparam rnode_164to165_bb1_var__u10_0_reg_165_fifo.DATA_WIDTH = 1;
defparam rnode_164to165_bb1_var__u10_0_reg_165_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_164to165_bb1_var__u10_0_reg_165_fifo.IMPL = "shift_reg";

assign rnode_164to165_bb1_var__u10_0_reg_165_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_var__u10_stall_in = 1'b0;
assign rnode_164to165_bb1_var__u10_0_NO_SHIFT_REG = rnode_164to165_bb1_var__u10_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_var__u10_0_stall_in_reg_165_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_var__u10_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_164to165_bb1_add178_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_164to165_bb1_add178_i_0_stall_in_0_NO_SHIFT_REG;
 logic [31:0] rnode_164to165_bb1_add178_i_0_NO_SHIFT_REG;
 logic rnode_164to165_bb1_add178_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_164to165_bb1_add178_i_0_stall_in_1_NO_SHIFT_REG;
 logic [31:0] rnode_164to165_bb1_add178_i_1_NO_SHIFT_REG;
 logic rnode_164to165_bb1_add178_i_0_valid_out_2_NO_SHIFT_REG;
 logic rnode_164to165_bb1_add178_i_0_stall_in_2_NO_SHIFT_REG;
 logic [31:0] rnode_164to165_bb1_add178_i_2_NO_SHIFT_REG;
 logic rnode_164to165_bb1_add178_i_0_valid_out_3_NO_SHIFT_REG;
 logic rnode_164to165_bb1_add178_i_0_stall_in_3_NO_SHIFT_REG;
 logic [31:0] rnode_164to165_bb1_add178_i_3_NO_SHIFT_REG;
 logic rnode_164to165_bb1_add178_i_0_reg_165_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_164to165_bb1_add178_i_0_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1_add178_i_0_valid_out_0_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1_add178_i_0_stall_in_0_reg_165_NO_SHIFT_REG;
 logic rnode_164to165_bb1_add178_i_0_stall_out_reg_165_NO_SHIFT_REG;

acl_data_fifo rnode_164to165_bb1_add178_i_0_reg_165_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_164to165_bb1_add178_i_0_reg_165_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_164to165_bb1_add178_i_0_stall_in_0_reg_165_NO_SHIFT_REG),
	.valid_out(rnode_164to165_bb1_add178_i_0_valid_out_0_reg_165_NO_SHIFT_REG),
	.stall_out(rnode_164to165_bb1_add178_i_0_stall_out_reg_165_NO_SHIFT_REG),
	.data_in(local_bb1_add178_i),
	.data_out(rnode_164to165_bb1_add178_i_0_reg_165_NO_SHIFT_REG)
);

defparam rnode_164to165_bb1_add178_i_0_reg_165_fifo.DEPTH = 1;
defparam rnode_164to165_bb1_add178_i_0_reg_165_fifo.DATA_WIDTH = 32;
defparam rnode_164to165_bb1_add178_i_0_reg_165_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_164to165_bb1_add178_i_0_reg_165_fifo.IMPL = "shift_reg";

assign rnode_164to165_bb1_add178_i_0_reg_165_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_add178_i_stall_in = 1'b0;
assign rnode_164to165_bb1_add178_i_0_stall_in_0_reg_165_NO_SHIFT_REG = 1'b0;
assign rnode_164to165_bb1_add178_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_add178_i_0_NO_SHIFT_REG = rnode_164to165_bb1_add178_i_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_add178_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_add178_i_1_NO_SHIFT_REG = rnode_164to165_bb1_add178_i_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_add178_i_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_add178_i_2_NO_SHIFT_REG = rnode_164to165_bb1_add178_i_0_reg_165_NO_SHIFT_REG;
assign rnode_164to165_bb1_add178_i_0_valid_out_3_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_add178_i_3_NO_SHIFT_REG = rnode_164to165_bb1_add178_i_0_reg_165_NO_SHIFT_REG;

// This section implements an unregistered operation.
// 
wire local_bb1_not_cmp37_i_stall_local;
wire local_bb1_not_cmp37_i;

assign local_bb1_not_cmp37_i = (rnode_164to166_bb1_cmp37_i_0_NO_SHIFT_REG ^ 1'b1);

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_165to166_bb1__13_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_165to166_bb1__13_i_0_stall_in_NO_SHIFT_REG;
 logic rnode_165to166_bb1__13_i_0_NO_SHIFT_REG;
 logic rnode_165to166_bb1__13_i_0_reg_166_inputs_ready_NO_SHIFT_REG;
 logic rnode_165to166_bb1__13_i_0_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1__13_i_0_valid_out_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1__13_i_0_stall_in_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1__13_i_0_stall_out_reg_166_NO_SHIFT_REG;

acl_data_fifo rnode_165to166_bb1__13_i_0_reg_166_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_165to166_bb1__13_i_0_reg_166_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_165to166_bb1__13_i_0_stall_in_reg_166_NO_SHIFT_REG),
	.valid_out(rnode_165to166_bb1__13_i_0_valid_out_reg_166_NO_SHIFT_REG),
	.stall_out(rnode_165to166_bb1__13_i_0_stall_out_reg_166_NO_SHIFT_REG),
	.data_in(rnode_164to165_bb1__13_i_0_NO_SHIFT_REG),
	.data_out(rnode_165to166_bb1__13_i_0_reg_166_NO_SHIFT_REG)
);

defparam rnode_165to166_bb1__13_i_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1__13_i_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_165to166_bb1__13_i_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1__13_i_0_reg_166_fifo.IMPL = "shift_reg";

assign rnode_165to166_bb1__13_i_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1__13_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1__13_i_0_NO_SHIFT_REG = rnode_165to166_bb1__13_i_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1__13_i_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1__13_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_165to166_bb1_var__u10_0_valid_out_NO_SHIFT_REG;
 logic rnode_165to166_bb1_var__u10_0_stall_in_NO_SHIFT_REG;
 logic rnode_165to166_bb1_var__u10_0_NO_SHIFT_REG;
 logic rnode_165to166_bb1_var__u10_0_reg_166_inputs_ready_NO_SHIFT_REG;
 logic rnode_165to166_bb1_var__u10_0_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_var__u10_0_valid_out_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_var__u10_0_stall_in_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_var__u10_0_stall_out_reg_166_NO_SHIFT_REG;

acl_data_fifo rnode_165to166_bb1_var__u10_0_reg_166_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_165to166_bb1_var__u10_0_reg_166_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_165to166_bb1_var__u10_0_stall_in_reg_166_NO_SHIFT_REG),
	.valid_out(rnode_165to166_bb1_var__u10_0_valid_out_reg_166_NO_SHIFT_REG),
	.stall_out(rnode_165to166_bb1_var__u10_0_stall_out_reg_166_NO_SHIFT_REG),
	.data_in(rnode_164to165_bb1_var__u10_0_NO_SHIFT_REG),
	.data_out(rnode_165to166_bb1_var__u10_0_reg_166_NO_SHIFT_REG)
);

defparam rnode_165to166_bb1_var__u10_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_var__u10_0_reg_166_fifo.DATA_WIDTH = 1;
defparam rnode_165to166_bb1_var__u10_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_var__u10_0_reg_166_fifo.IMPL = "shift_reg";

assign rnode_165to166_bb1_var__u10_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_164to165_bb1_var__u10_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_var__u10_0_NO_SHIFT_REG = rnode_165to166_bb1_var__u10_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_var__u10_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_var__u10_0_valid_out_NO_SHIFT_REG = 1'b1;

// This section implements an unregistered operation.
// 
wire local_bb1_and179_i_valid_out;
wire local_bb1_and179_i_stall_in;
wire local_bb1_and179_i_inputs_ready;
wire local_bb1_and179_i_stall_local;
wire [31:0] local_bb1_and179_i;

assign local_bb1_and179_i_inputs_ready = rnode_164to165_bb1_add178_i_0_valid_out_0_NO_SHIFT_REG;
assign local_bb1_and179_i = (rnode_164to165_bb1_add178_i_0_NO_SHIFT_REG & 32'hFFFFFFF);
assign local_bb1_and179_i_valid_out = 1'b1;
assign rnode_164to165_bb1_add178_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;

// This section implements an unregistered operation.
// 
wire local_bb1_and181_i_valid_out;
wire local_bb1_and181_i_stall_in;
wire local_bb1_and181_i_inputs_ready;
wire local_bb1_and181_i_stall_local;
wire [31:0] local_bb1_and181_i;

assign local_bb1_and181_i_inputs_ready = rnode_164to165_bb1_add178_i_0_valid_out_1_NO_SHIFT_REG;
assign local_bb1_and181_i = (rnode_164to165_bb1_add178_i_1_NO_SHIFT_REG >> 32'h1B);
assign local_bb1_and181_i_valid_out = 1'b1;
assign rnode_164to165_bb1_add178_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;

// This section implements an unregistered operation.
// 
wire local_bb1_and184_i_valid_out;
wire local_bb1_and184_i_stall_in;
wire local_bb1_and184_i_inputs_ready;
wire local_bb1_and184_i_stall_local;
wire [31:0] local_bb1_and184_i;

assign local_bb1_and184_i_inputs_ready = rnode_164to165_bb1_add178_i_0_valid_out_2_NO_SHIFT_REG;
assign local_bb1_and184_i = (rnode_164to165_bb1_add178_i_2_NO_SHIFT_REG & 32'h1);
assign local_bb1_and184_i_valid_out = 1'b1;
assign rnode_164to165_bb1_add178_i_0_stall_in_2_NO_SHIFT_REG = 1'b0;

// This section implements an unregistered operation.
// 
wire local_bb1_and187_i_stall_local;
wire [31:0] local_bb1_and187_i;

assign local_bb1_and187_i = (rnode_164to165_bb1_add178_i_3_NO_SHIFT_REG & 32'h7FFFFFF);

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_166to167_bb1__13_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1__13_i_0_stall_in_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1__13_i_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1__13_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_166to167_bb1__13_i_0_stall_in_1_NO_SHIFT_REG;
 logic rnode_166to167_bb1__13_i_1_NO_SHIFT_REG;
 logic rnode_166to167_bb1__13_i_0_valid_out_2_NO_SHIFT_REG;
 logic rnode_166to167_bb1__13_i_0_stall_in_2_NO_SHIFT_REG;
 logic rnode_166to167_bb1__13_i_2_NO_SHIFT_REG;
 logic rnode_166to167_bb1__13_i_0_reg_167_inputs_ready_NO_SHIFT_REG;
 logic rnode_166to167_bb1__13_i_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1__13_i_0_valid_out_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1__13_i_0_stall_in_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1__13_i_0_stall_out_reg_167_NO_SHIFT_REG;

acl_data_fifo rnode_166to167_bb1__13_i_0_reg_167_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_166to167_bb1__13_i_0_reg_167_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_166to167_bb1__13_i_0_stall_in_0_reg_167_NO_SHIFT_REG),
	.valid_out(rnode_166to167_bb1__13_i_0_valid_out_0_reg_167_NO_SHIFT_REG),
	.stall_out(rnode_166to167_bb1__13_i_0_stall_out_reg_167_NO_SHIFT_REG),
	.data_in(rnode_165to166_bb1__13_i_0_NO_SHIFT_REG),
	.data_out(rnode_166to167_bb1__13_i_0_reg_167_NO_SHIFT_REG)
);

defparam rnode_166to167_bb1__13_i_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1__13_i_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1__13_i_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1__13_i_0_reg_167_fifo.IMPL = "shift_reg";

assign rnode_166to167_bb1__13_i_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1__13_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1__13_i_0_stall_in_0_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1__13_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1__13_i_0_NO_SHIFT_REG = rnode_166to167_bb1__13_i_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1__13_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1__13_i_1_NO_SHIFT_REG = rnode_166to167_bb1__13_i_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1__13_i_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1__13_i_2_NO_SHIFT_REG = rnode_166to167_bb1__13_i_0_reg_167_NO_SHIFT_REG;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_166to167_bb1_var__u10_0_valid_out_NO_SHIFT_REG;
 logic rnode_166to167_bb1_var__u10_0_stall_in_NO_SHIFT_REG;
 logic rnode_166to167_bb1_var__u10_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1_var__u10_0_reg_167_inputs_ready_NO_SHIFT_REG;
 logic rnode_166to167_bb1_var__u10_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_var__u10_0_valid_out_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_var__u10_0_stall_in_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_var__u10_0_stall_out_reg_167_NO_SHIFT_REG;

acl_data_fifo rnode_166to167_bb1_var__u10_0_reg_167_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_166to167_bb1_var__u10_0_reg_167_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_166to167_bb1_var__u10_0_stall_in_reg_167_NO_SHIFT_REG),
	.valid_out(rnode_166to167_bb1_var__u10_0_valid_out_reg_167_NO_SHIFT_REG),
	.stall_out(rnode_166to167_bb1_var__u10_0_stall_out_reg_167_NO_SHIFT_REG),
	.data_in(rnode_165to166_bb1_var__u10_0_NO_SHIFT_REG),
	.data_out(rnode_166to167_bb1_var__u10_0_reg_167_NO_SHIFT_REG)
);

defparam rnode_166to167_bb1_var__u10_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_var__u10_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1_var__u10_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_var__u10_0_reg_167_fifo.IMPL = "shift_reg";

assign rnode_166to167_bb1_var__u10_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_var__u10_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_var__u10_0_NO_SHIFT_REG = rnode_166to167_bb1_var__u10_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_var__u10_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_var__u10_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_165to166_bb1_and179_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and179_i_0_stall_in_0_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1_and179_i_0_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and179_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and179_i_0_stall_in_1_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1_and179_i_1_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and179_i_0_valid_out_2_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and179_i_0_stall_in_2_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1_and179_i_2_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and179_i_0_reg_166_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1_and179_i_0_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and179_i_0_valid_out_0_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and179_i_0_stall_in_0_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and179_i_0_stall_out_reg_166_NO_SHIFT_REG;

acl_data_fifo rnode_165to166_bb1_and179_i_0_reg_166_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_165to166_bb1_and179_i_0_reg_166_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_165to166_bb1_and179_i_0_stall_in_0_reg_166_NO_SHIFT_REG),
	.valid_out(rnode_165to166_bb1_and179_i_0_valid_out_0_reg_166_NO_SHIFT_REG),
	.stall_out(rnode_165to166_bb1_and179_i_0_stall_out_reg_166_NO_SHIFT_REG),
	.data_in((local_bb1_and179_i & 32'hFFFFFFF)),
	.data_out(rnode_165to166_bb1_and179_i_0_reg_166_NO_SHIFT_REG)
);

defparam rnode_165to166_bb1_and179_i_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_and179_i_0_reg_166_fifo.DATA_WIDTH = 32;
defparam rnode_165to166_bb1_and179_i_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_and179_i_0_reg_166_fifo.IMPL = "shift_reg";

assign rnode_165to166_bb1_and179_i_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_and179_i_stall_in = 1'b0;
assign rnode_165to166_bb1_and179_i_0_stall_in_0_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_and179_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_and179_i_0_NO_SHIFT_REG = rnode_165to166_bb1_and179_i_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_and179_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_and179_i_1_NO_SHIFT_REG = rnode_165to166_bb1_and179_i_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_and179_i_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1_and179_i_2_NO_SHIFT_REG = rnode_165to166_bb1_and179_i_0_reg_166_NO_SHIFT_REG;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_165to166_bb1_and181_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and181_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1_and181_i_0_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and181_i_0_reg_166_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1_and181_i_0_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and181_i_0_valid_out_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and181_i_0_stall_in_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and181_i_0_stall_out_reg_166_NO_SHIFT_REG;

acl_data_fifo rnode_165to166_bb1_and181_i_0_reg_166_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_165to166_bb1_and181_i_0_reg_166_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_165to166_bb1_and181_i_0_stall_in_reg_166_NO_SHIFT_REG),
	.valid_out(rnode_165to166_bb1_and181_i_0_valid_out_reg_166_NO_SHIFT_REG),
	.stall_out(rnode_165to166_bb1_and181_i_0_stall_out_reg_166_NO_SHIFT_REG),
	.data_in((local_bb1_and181_i & 32'h1F)),
	.data_out(rnode_165to166_bb1_and181_i_0_reg_166_NO_SHIFT_REG)
);

defparam rnode_165to166_bb1_and181_i_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_and181_i_0_reg_166_fifo.DATA_WIDTH = 32;
defparam rnode_165to166_bb1_and181_i_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_and181_i_0_reg_166_fifo.IMPL = "shift_reg";

assign rnode_165to166_bb1_and181_i_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_and181_i_stall_in = 1'b0;
assign rnode_165to166_bb1_and181_i_0_NO_SHIFT_REG = rnode_165to166_bb1_and181_i_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_and181_i_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_and181_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_165to166_bb1_and184_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and184_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1_and184_i_0_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and184_i_0_reg_166_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1_and184_i_0_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and184_i_0_valid_out_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and184_i_0_stall_in_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1_and184_i_0_stall_out_reg_166_NO_SHIFT_REG;

acl_data_fifo rnode_165to166_bb1_and184_i_0_reg_166_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_165to166_bb1_and184_i_0_reg_166_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_165to166_bb1_and184_i_0_stall_in_reg_166_NO_SHIFT_REG),
	.valid_out(rnode_165to166_bb1_and184_i_0_valid_out_reg_166_NO_SHIFT_REG),
	.stall_out(rnode_165to166_bb1_and184_i_0_stall_out_reg_166_NO_SHIFT_REG),
	.data_in((local_bb1_and184_i & 32'h1)),
	.data_out(rnode_165to166_bb1_and184_i_0_reg_166_NO_SHIFT_REG)
);

defparam rnode_165to166_bb1_and184_i_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1_and184_i_0_reg_166_fifo.DATA_WIDTH = 32;
defparam rnode_165to166_bb1_and184_i_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1_and184_i_0_reg_166_fifo.IMPL = "shift_reg";

assign rnode_165to166_bb1_and184_i_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_and184_i_stall_in = 1'b0;
assign rnode_165to166_bb1_and184_i_0_NO_SHIFT_REG = rnode_165to166_bb1_and184_i_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1_and184_i_0_stall_in_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_and184_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// This section implements an unregistered operation.
// 
wire local_bb1_shr_i_i_stall_local;
wire [31:0] local_bb1_shr_i_i;

assign local_bb1_shr_i_i = ((local_bb1_and187_i & 32'h7FFFFFF) >> 32'h1);

// This section implements an unregistered operation.
// 
wire local_bb1_cond260_i_stall_local;
wire [31:0] local_bb1_cond260_i;

assign local_bb1_cond260_i = (rnode_166to167_bb1__13_i_1_NO_SHIFT_REG ? 32'h400000 : 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_shr200_i_stall_local;
wire [31:0] local_bb1_shr200_i;

assign local_bb1_shr200_i = ((rnode_165to166_bb1_and179_i_1_NO_SHIFT_REG & 32'hFFFFFFF) >> 32'h1);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u15_stall_local;
wire [31:0] local_bb1_var__u15;

assign local_bb1_var__u15 = ((rnode_165to166_bb1_and181_i_0_NO_SHIFT_REG & 32'h1F) & 32'h1);

// This section implements an unregistered operation.
// 
wire local_bb1_or_i_i_stall_local;
wire [31:0] local_bb1_or_i_i;

assign local_bb1_or_i_i = ((local_bb1_shr_i_i & 32'h3FFFFFF) | (local_bb1_and187_i & 32'h7FFFFFF));

// This section implements an unregistered operation.
// 
wire local_bb1_or203_i_stall_local;
wire [31:0] local_bb1_or203_i;

assign local_bb1_or203_i = ((local_bb1_shr200_i & 32'h7FFFFFF) | (rnode_165to166_bb1_and184_i_0_NO_SHIFT_REG & 32'h1));

// This section implements an unregistered operation.
// 
wire local_bb1_tobool198_i_stall_local;
wire local_bb1_tobool198_i;

assign local_bb1_tobool198_i = ((local_bb1_var__u15 & 32'h1) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_shr1_i_i_stall_local;
wire [31:0] local_bb1_shr1_i_i;

assign local_bb1_shr1_i_i = ((local_bb1_or_i_i & 32'h7FFFFFF) >> 32'h2);

// This section implements an unregistered operation.
// 
wire local_bb1__26_i_stall_local;
wire local_bb1__26_i;

assign local_bb1__26_i = (local_bb1_tobool198_i & local_bb1_not_cmp37_i);

// This section implements an unregistered operation.
// 
wire local_bb1_or2_i_i_stall_local;
wire [31:0] local_bb1_or2_i_i;

assign local_bb1_or2_i_i = ((local_bb1_shr1_i_i & 32'h1FFFFFF) | (local_bb1_or_i_i & 32'h7FFFFFF));

// This section implements an unregistered operation.
// 
wire local_bb1__27_i_stall_local;
wire [31:0] local_bb1__27_i;

assign local_bb1__27_i = (local_bb1__26_i ? 32'h0 : (local_bb1_var__u15 & 32'h1));

// This section implements an unregistered operation.
// 
wire local_bb1__29_i_stall_local;
wire [31:0] local_bb1__29_i;

assign local_bb1__29_i = (local_bb1__26_i ? (rnode_165to166_bb1_and179_i_2_NO_SHIFT_REG & 32'hFFFFFFF) : (local_bb1_or203_i & 32'h7FFFFFF));

// This section implements an unregistered operation.
// 
wire local_bb1_shr3_i_i_stall_local;
wire [31:0] local_bb1_shr3_i_i;

assign local_bb1_shr3_i_i = ((local_bb1_or2_i_i & 32'h7FFFFFF) >> 32'h4);

// This section implements an unregistered operation.
// 
wire local_bb1_or4_i_i_stall_local;
wire [31:0] local_bb1_or4_i_i;

assign local_bb1_or4_i_i = ((local_bb1_shr3_i_i & 32'h7FFFFF) | (local_bb1_or2_i_i & 32'h7FFFFFF));

// This section implements an unregistered operation.
// 
wire local_bb1_shr5_i_i_stall_local;
wire [31:0] local_bb1_shr5_i_i;

assign local_bb1_shr5_i_i = ((local_bb1_or4_i_i & 32'h7FFFFFF) >> 32'h8);

// This section implements an unregistered operation.
// 
wire local_bb1_or6_i_i_stall_local;
wire [31:0] local_bb1_or6_i_i;

assign local_bb1_or6_i_i = ((local_bb1_shr5_i_i & 32'h7FFFF) | (local_bb1_or4_i_i & 32'h7FFFFFF));

// This section implements an unregistered operation.
// 
wire local_bb1_shr7_i_i_stall_local;
wire [31:0] local_bb1_shr7_i_i;

assign local_bb1_shr7_i_i = ((local_bb1_or6_i_i & 32'h7FFFFFF) >> 32'h10);

// This section implements an unregistered operation.
// 
wire local_bb1_or8_i_i_stall_local;
wire [31:0] local_bb1_or8_i_i;

assign local_bb1_or8_i_i = ((local_bb1_shr7_i_i & 32'h7FF) | (local_bb1_or6_i_i & 32'h7FFFFFF));

// This section implements an unregistered operation.
// 
wire local_bb1_and_i_i_stall_local;
wire [31:0] local_bb1_and_i_i;

assign local_bb1_and_i_i = ((local_bb1_or8_i_i & 32'h7FFFFFF) ^ 32'h7FFFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1__and_i_i_valid_out;
wire local_bb1__and_i_i_stall_in;
wire local_bb1__and_i_i_inputs_ready;
wire local_bb1__and_i_i_stall_local;
wire [31:0] local_bb1__and_i_i;

thirtysix_six_comp local_bb1__and_i_i_popcnt_instance (
	.data((local_bb1_and_i_i & 32'h1FFFFFFF)),
	.sum(local_bb1__and_i_i)
);


assign local_bb1__and_i_i_inputs_ready = rnode_164to165_bb1_add178_i_0_valid_out_3_NO_SHIFT_REG;
assign local_bb1__and_i_i_valid_out = 1'b1;
assign rnode_164to165_bb1_add178_i_0_stall_in_3_NO_SHIFT_REG = 1'b0;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_165to166_bb1__and_i_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_165to166_bb1__and_i_i_0_stall_in_0_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1__and_i_i_0_NO_SHIFT_REG;
 logic rnode_165to166_bb1__and_i_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_165to166_bb1__and_i_i_0_stall_in_1_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1__and_i_i_1_NO_SHIFT_REG;
 logic rnode_165to166_bb1__and_i_i_0_valid_out_2_NO_SHIFT_REG;
 logic rnode_165to166_bb1__and_i_i_0_stall_in_2_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1__and_i_i_2_NO_SHIFT_REG;
 logic rnode_165to166_bb1__and_i_i_0_reg_166_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_165to166_bb1__and_i_i_0_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1__and_i_i_0_valid_out_0_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1__and_i_i_0_stall_in_0_reg_166_NO_SHIFT_REG;
 logic rnode_165to166_bb1__and_i_i_0_stall_out_reg_166_NO_SHIFT_REG;

acl_data_fifo rnode_165to166_bb1__and_i_i_0_reg_166_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_165to166_bb1__and_i_i_0_reg_166_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_165to166_bb1__and_i_i_0_stall_in_0_reg_166_NO_SHIFT_REG),
	.valid_out(rnode_165to166_bb1__and_i_i_0_valid_out_0_reg_166_NO_SHIFT_REG),
	.stall_out(rnode_165to166_bb1__and_i_i_0_stall_out_reg_166_NO_SHIFT_REG),
	.data_in((local_bb1__and_i_i & 32'h3F)),
	.data_out(rnode_165to166_bb1__and_i_i_0_reg_166_NO_SHIFT_REG)
);

defparam rnode_165to166_bb1__and_i_i_0_reg_166_fifo.DEPTH = 1;
defparam rnode_165to166_bb1__and_i_i_0_reg_166_fifo.DATA_WIDTH = 32;
defparam rnode_165to166_bb1__and_i_i_0_reg_166_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_165to166_bb1__and_i_i_0_reg_166_fifo.IMPL = "shift_reg";

assign rnode_165to166_bb1__and_i_i_0_reg_166_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__and_i_i_stall_in = 1'b0;
assign rnode_165to166_bb1__and_i_i_0_stall_in_0_reg_166_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1__and_i_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1__and_i_i_0_NO_SHIFT_REG = rnode_165to166_bb1__and_i_i_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1__and_i_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1__and_i_i_1_NO_SHIFT_REG = rnode_165to166_bb1__and_i_i_0_reg_166_NO_SHIFT_REG;
assign rnode_165to166_bb1__and_i_i_0_valid_out_2_NO_SHIFT_REG = 1'b1;
assign rnode_165to166_bb1__and_i_i_2_NO_SHIFT_REG = rnode_165to166_bb1__and_i_i_0_reg_166_NO_SHIFT_REG;

// This section implements an unregistered operation.
// 
wire local_bb1_and9_i_i_stall_local;
wire [31:0] local_bb1_and9_i_i;

assign local_bb1_and9_i_i = ((rnode_165to166_bb1__and_i_i_0_NO_SHIFT_REG & 32'h3F) & 32'h1F);

// This section implements an unregistered operation.
// 
wire local_bb1_and189_i_stall_local;
wire [31:0] local_bb1_and189_i;

assign local_bb1_and189_i = ((rnode_165to166_bb1__and_i_i_1_NO_SHIFT_REG & 32'h3F) & 32'h18);

// This section implements an unregistered operation.
// 
wire local_bb1_and192_i_stall_local;
wire [31:0] local_bb1_and192_i;

assign local_bb1_and192_i = ((rnode_165to166_bb1__and_i_i_2_NO_SHIFT_REG & 32'h3F) & 32'h7);

// This section implements an unregistered operation.
// 
wire local_bb1_sub219_i_stall_local;
wire [31:0] local_bb1_sub219_i;

assign local_bb1_sub219_i = (32'h0 - (local_bb1_and9_i_i & 32'h1F));

// This section implements an unregistered operation.
// 
wire local_bb1_shl190_i_stall_local;
wire [31:0] local_bb1_shl190_i;

assign local_bb1_shl190_i = ((rnode_165to166_bb1_and179_i_0_NO_SHIFT_REG & 32'hFFFFFFF) << (local_bb1_and189_i & 32'h18));

// This section implements an unregistered operation.
// 
wire local_bb1_cond224_i_stall_local;
wire [31:0] local_bb1_cond224_i;

assign local_bb1_cond224_i = (rnode_164to166_bb1_cmp37_i_2_NO_SHIFT_REG ? local_bb1_sub219_i : (local_bb1__27_i & 32'h1));

// This section implements an unregistered operation.
// 
wire local_bb1_and191_i_stall_local;
wire [31:0] local_bb1_and191_i;

assign local_bb1_and191_i = (local_bb1_shl190_i & 32'h7FFFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1_add225_i_stall_local;
wire [31:0] local_bb1_add225_i;

assign local_bb1_add225_i = (local_bb1_cond224_i + (rnode_164to166_bb1_and17_i_0_NO_SHIFT_REG & 32'hFF));

// This section implements an unregistered operation.
// 
wire local_bb1_fold_i_stall_local;
wire [31:0] local_bb1_fold_i;

assign local_bb1_fold_i = (local_bb1_cond224_i + (rnode_164to166_bb1_shr16_i_0_NO_SHIFT_REG & 32'h1FF));

// This section implements an unregistered operation.
// 
wire local_bb1_shl193_i_stall_local;
wire [31:0] local_bb1_shl193_i;

assign local_bb1_shl193_i = ((local_bb1_and191_i & 32'h7FFFFFF) << (local_bb1_and192_i & 32'h7));

// This section implements an unregistered operation.
// 
wire local_bb1_and230_i_stall_local;
wire [31:0] local_bb1_and230_i;

assign local_bb1_and230_i = (local_bb1_fold_i & 32'hFF);

// This section implements an unregistered operation.
// 
wire local_bb1_and194_i_stall_local;
wire [31:0] local_bb1_and194_i;

assign local_bb1_and194_i = (local_bb1_shl193_i & 32'h7FFFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1__30_i_stall_local;
wire [31:0] local_bb1__30_i;

assign local_bb1__30_i = (rnode_164to166_bb1_cmp37_i_1_NO_SHIFT_REG ? (local_bb1_and194_i & 32'h7FFFFFF) : (local_bb1__29_i & 32'hFFFFFFF));

// This section implements an unregistered operation.
// 
wire local_bb1_and209_i_stall_local;
wire [31:0] local_bb1_and209_i;

assign local_bb1_and209_i = ((local_bb1__30_i & 32'hFFFFFFF) & 32'h7FFFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1_and245_i_stall_local;
wire [31:0] local_bb1_and245_i;

assign local_bb1_and245_i = ((local_bb1__30_i & 32'hFFFFFFF) & 32'h7);

// This section implements an unregistered operation.
// 
wire local_bb1_shr246_i_stall_local;
wire [31:0] local_bb1_shr246_i;

assign local_bb1_shr246_i = ((local_bb1__30_i & 32'hFFFFFFF) >> 32'h3);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp210_i_stall_local;
wire local_bb1_cmp210_i;

assign local_bb1_cmp210_i = ((local_bb1_and209_i & 32'h7FFFFFF) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp264_i_stall_local;
wire local_bb1_cmp264_i;

assign local_bb1_cmp264_i = ((local_bb1_and245_i & 32'h7) > 32'h4);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp266_i_stall_local;
wire local_bb1_cmp266_i;

assign local_bb1_cmp266_i = ((local_bb1_and245_i & 32'h7) == 32'h4);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp210_not_i_stall_local;
wire local_bb1_cmp210_not_i;

assign local_bb1_cmp210_not_i = (local_bb1_cmp210_i ^ 1'b1);

// This section implements an unregistered operation.
// 
wire local_bb1_brmerge7_i_stall_local;
wire local_bb1_brmerge7_i;

assign local_bb1_brmerge7_i = (local_bb1_cmp210_not_i | local_bb1_not_cmp37_i);

// This section implements an unregistered operation.
// 
wire local_bb1_and230_i_valid_out;
wire local_bb1_and230_i_stall_in;
wire local_bb1_add225_i_valid_out;
wire local_bb1_add225_i_stall_in;
wire local_bb1_resultSign_0_i_valid_out;
wire local_bb1_resultSign_0_i_stall_in;
wire local_bb1_shr246_i_valid_out;
wire local_bb1_shr246_i_stall_in;
wire local_bb1_cmp210_i_valid_out_1;
wire local_bb1_cmp210_i_stall_in_1;
wire local_bb1_cmp264_i_valid_out;
wire local_bb1_cmp264_i_stall_in;
wire local_bb1_cmp266_i_valid_out;
wire local_bb1_cmp266_i_stall_in;
wire local_bb1_cmp210_not_i_valid_out_1;
wire local_bb1_cmp210_not_i_stall_in_1;
wire local_bb1_resultSign_0_i_inputs_ready;
wire local_bb1_resultSign_0_i_stall_local;
wire [31:0] local_bb1_resultSign_0_i;

assign local_bb1_resultSign_0_i_inputs_ready = (rnode_164to166_bb1_shr16_i_0_valid_out_NO_SHIFT_REG & rnode_164to166_bb1_cmp37_i_0_valid_out_2_NO_SHIFT_REG & rnode_164to166_bb1_and17_i_0_valid_out_NO_SHIFT_REG & rnode_164to166_bb1_cmp37_i_0_valid_out_0_NO_SHIFT_REG & rnode_165to166_bb1_and179_i_0_valid_out_2_NO_SHIFT_REG & rnode_165to166_bb1_and35_i_0_valid_out_NO_SHIFT_REG & rnode_164to166_bb1_cmp37_i_0_valid_out_1_NO_SHIFT_REG & rnode_165to166_bb1_and181_i_0_valid_out_NO_SHIFT_REG & rnode_165to166_bb1_and179_i_0_valid_out_1_NO_SHIFT_REG & rnode_165to166_bb1_and184_i_0_valid_out_NO_SHIFT_REG & rnode_165to166_bb1_and179_i_0_valid_out_0_NO_SHIFT_REG & rnode_165to166_bb1__and_i_i_0_valid_out_1_NO_SHIFT_REG & rnode_165to166_bb1__and_i_i_0_valid_out_2_NO_SHIFT_REG & rnode_165to166_bb1__and_i_i_0_valid_out_0_NO_SHIFT_REG);
assign local_bb1_resultSign_0_i = (local_bb1_brmerge7_i ? (rnode_165to166_bb1_and35_i_0_NO_SHIFT_REG & 32'h80000000) : 32'h0);
assign local_bb1_and230_i_valid_out = 1'b1;
assign local_bb1_add225_i_valid_out = 1'b1;
assign local_bb1_resultSign_0_i_valid_out = 1'b1;
assign local_bb1_shr246_i_valid_out = 1'b1;
assign local_bb1_cmp210_i_valid_out_1 = 1'b1;
assign local_bb1_cmp264_i_valid_out = 1'b1;
assign local_bb1_cmp266_i_valid_out = 1'b1;
assign local_bb1_cmp210_not_i_valid_out_1 = 1'b1;
assign rnode_164to166_bb1_shr16_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_164to166_bb1_cmp37_i_0_stall_in_2_NO_SHIFT_REG = 1'b0;
assign rnode_164to166_bb1_and17_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_164to166_bb1_cmp37_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_and179_i_0_stall_in_2_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_and35_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_164to166_bb1_cmp37_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_and181_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_and179_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_and184_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1_and179_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1__and_i_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1__and_i_i_0_stall_in_2_NO_SHIFT_REG = 1'b0;
assign rnode_165to166_bb1__and_i_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_166to167_bb1_and230_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1_and230_i_0_stall_in_0_NO_SHIFT_REG;
 logic [31:0] rnode_166to167_bb1_and230_i_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1_and230_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_166to167_bb1_and230_i_0_stall_in_1_NO_SHIFT_REG;
 logic [31:0] rnode_166to167_bb1_and230_i_1_NO_SHIFT_REG;
 logic rnode_166to167_bb1_and230_i_0_reg_167_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_166to167_bb1_and230_i_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_and230_i_0_valid_out_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_and230_i_0_stall_in_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_and230_i_0_stall_out_reg_167_NO_SHIFT_REG;

acl_data_fifo rnode_166to167_bb1_and230_i_0_reg_167_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_166to167_bb1_and230_i_0_reg_167_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_166to167_bb1_and230_i_0_stall_in_0_reg_167_NO_SHIFT_REG),
	.valid_out(rnode_166to167_bb1_and230_i_0_valid_out_0_reg_167_NO_SHIFT_REG),
	.stall_out(rnode_166to167_bb1_and230_i_0_stall_out_reg_167_NO_SHIFT_REG),
	.data_in((local_bb1_and230_i & 32'hFF)),
	.data_out(rnode_166to167_bb1_and230_i_0_reg_167_NO_SHIFT_REG)
);

defparam rnode_166to167_bb1_and230_i_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_and230_i_0_reg_167_fifo.DATA_WIDTH = 32;
defparam rnode_166to167_bb1_and230_i_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_and230_i_0_reg_167_fifo.IMPL = "shift_reg";

assign rnode_166to167_bb1_and230_i_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_and230_i_stall_in = 1'b0;
assign rnode_166to167_bb1_and230_i_0_stall_in_0_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_and230_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_and230_i_0_NO_SHIFT_REG = rnode_166to167_bb1_and230_i_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_and230_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_and230_i_1_NO_SHIFT_REG = rnode_166to167_bb1_and230_i_0_reg_167_NO_SHIFT_REG;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_166to167_bb1_add225_i_0_valid_out_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1_add225_i_0_stall_in_0_NO_SHIFT_REG;
 logic [31:0] rnode_166to167_bb1_add225_i_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1_add225_i_0_valid_out_1_NO_SHIFT_REG;
 logic rnode_166to167_bb1_add225_i_0_stall_in_1_NO_SHIFT_REG;
 logic [31:0] rnode_166to167_bb1_add225_i_1_NO_SHIFT_REG;
 logic rnode_166to167_bb1_add225_i_0_reg_167_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_166to167_bb1_add225_i_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_add225_i_0_valid_out_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_add225_i_0_stall_in_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_add225_i_0_stall_out_reg_167_NO_SHIFT_REG;

acl_data_fifo rnode_166to167_bb1_add225_i_0_reg_167_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_166to167_bb1_add225_i_0_reg_167_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_166to167_bb1_add225_i_0_stall_in_0_reg_167_NO_SHIFT_REG),
	.valid_out(rnode_166to167_bb1_add225_i_0_valid_out_0_reg_167_NO_SHIFT_REG),
	.stall_out(rnode_166to167_bb1_add225_i_0_stall_out_reg_167_NO_SHIFT_REG),
	.data_in(local_bb1_add225_i),
	.data_out(rnode_166to167_bb1_add225_i_0_reg_167_NO_SHIFT_REG)
);

defparam rnode_166to167_bb1_add225_i_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_add225_i_0_reg_167_fifo.DATA_WIDTH = 32;
defparam rnode_166to167_bb1_add225_i_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_add225_i_0_reg_167_fifo.IMPL = "shift_reg";

assign rnode_166to167_bb1_add225_i_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_add225_i_stall_in = 1'b0;
assign rnode_166to167_bb1_add225_i_0_stall_in_0_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_add225_i_0_valid_out_0_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_add225_i_0_NO_SHIFT_REG = rnode_166to167_bb1_add225_i_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_add225_i_0_valid_out_1_NO_SHIFT_REG = 1'b1;
assign rnode_166to167_bb1_add225_i_1_NO_SHIFT_REG = rnode_166to167_bb1_add225_i_0_reg_167_NO_SHIFT_REG;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_166to167_bb1_resultSign_0_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_166to167_bb1_resultSign_0_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_166to167_bb1_resultSign_0_i_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1_resultSign_0_i_0_reg_167_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_166to167_bb1_resultSign_0_i_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_resultSign_0_i_0_valid_out_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_resultSign_0_i_0_stall_in_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_resultSign_0_i_0_stall_out_reg_167_NO_SHIFT_REG;

acl_data_fifo rnode_166to167_bb1_resultSign_0_i_0_reg_167_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_166to167_bb1_resultSign_0_i_0_reg_167_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_166to167_bb1_resultSign_0_i_0_stall_in_reg_167_NO_SHIFT_REG),
	.valid_out(rnode_166to167_bb1_resultSign_0_i_0_valid_out_reg_167_NO_SHIFT_REG),
	.stall_out(rnode_166to167_bb1_resultSign_0_i_0_stall_out_reg_167_NO_SHIFT_REG),
	.data_in((local_bb1_resultSign_0_i & 32'h80000000)),
	.data_out(rnode_166to167_bb1_resultSign_0_i_0_reg_167_NO_SHIFT_REG)
);

defparam rnode_166to167_bb1_resultSign_0_i_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_resultSign_0_i_0_reg_167_fifo.DATA_WIDTH = 32;
defparam rnode_166to167_bb1_resultSign_0_i_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_resultSign_0_i_0_reg_167_fifo.IMPL = "shift_reg";

assign rnode_166to167_bb1_resultSign_0_i_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_resultSign_0_i_stall_in = 1'b0;
assign rnode_166to167_bb1_resultSign_0_i_0_NO_SHIFT_REG = rnode_166to167_bb1_resultSign_0_i_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_resultSign_0_i_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_resultSign_0_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_166to167_bb1_shr246_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_166to167_bb1_shr246_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_166to167_bb1_shr246_i_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1_shr246_i_0_reg_167_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_166to167_bb1_shr246_i_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_shr246_i_0_valid_out_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_shr246_i_0_stall_in_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_shr246_i_0_stall_out_reg_167_NO_SHIFT_REG;

acl_data_fifo rnode_166to167_bb1_shr246_i_0_reg_167_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_166to167_bb1_shr246_i_0_reg_167_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_166to167_bb1_shr246_i_0_stall_in_reg_167_NO_SHIFT_REG),
	.valid_out(rnode_166to167_bb1_shr246_i_0_valid_out_reg_167_NO_SHIFT_REG),
	.stall_out(rnode_166to167_bb1_shr246_i_0_stall_out_reg_167_NO_SHIFT_REG),
	.data_in((local_bb1_shr246_i & 32'h1FFFFFF)),
	.data_out(rnode_166to167_bb1_shr246_i_0_reg_167_NO_SHIFT_REG)
);

defparam rnode_166to167_bb1_shr246_i_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_shr246_i_0_reg_167_fifo.DATA_WIDTH = 32;
defparam rnode_166to167_bb1_shr246_i_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_shr246_i_0_reg_167_fifo.IMPL = "shift_reg";

assign rnode_166to167_bb1_shr246_i_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_shr246_i_stall_in = 1'b0;
assign rnode_166to167_bb1_shr246_i_0_NO_SHIFT_REG = rnode_166to167_bb1_shr246_i_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_shr246_i_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_shr246_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_166to167_bb1_cmp210_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_i_0_stall_in_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_i_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_i_0_reg_167_inputs_ready_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_i_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_i_0_valid_out_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_i_0_stall_in_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_i_0_stall_out_reg_167_NO_SHIFT_REG;

acl_data_fifo rnode_166to167_bb1_cmp210_i_0_reg_167_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_166to167_bb1_cmp210_i_0_reg_167_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_166to167_bb1_cmp210_i_0_stall_in_reg_167_NO_SHIFT_REG),
	.valid_out(rnode_166to167_bb1_cmp210_i_0_valid_out_reg_167_NO_SHIFT_REG),
	.stall_out(rnode_166to167_bb1_cmp210_i_0_stall_out_reg_167_NO_SHIFT_REG),
	.data_in(local_bb1_cmp210_i),
	.data_out(rnode_166to167_bb1_cmp210_i_0_reg_167_NO_SHIFT_REG)
);

defparam rnode_166to167_bb1_cmp210_i_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_cmp210_i_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1_cmp210_i_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_cmp210_i_0_reg_167_fifo.IMPL = "shift_reg";

assign rnode_166to167_bb1_cmp210_i_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp210_i_stall_in_1 = 1'b0;
assign rnode_166to167_bb1_cmp210_i_0_NO_SHIFT_REG = rnode_166to167_bb1_cmp210_i_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_cmp210_i_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp210_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_166to167_bb1_cmp264_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp264_i_0_stall_in_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp264_i_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp264_i_0_reg_167_inputs_ready_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp264_i_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp264_i_0_valid_out_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp264_i_0_stall_in_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp264_i_0_stall_out_reg_167_NO_SHIFT_REG;

acl_data_fifo rnode_166to167_bb1_cmp264_i_0_reg_167_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_166to167_bb1_cmp264_i_0_reg_167_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_166to167_bb1_cmp264_i_0_stall_in_reg_167_NO_SHIFT_REG),
	.valid_out(rnode_166to167_bb1_cmp264_i_0_valid_out_reg_167_NO_SHIFT_REG),
	.stall_out(rnode_166to167_bb1_cmp264_i_0_stall_out_reg_167_NO_SHIFT_REG),
	.data_in(local_bb1_cmp264_i),
	.data_out(rnode_166to167_bb1_cmp264_i_0_reg_167_NO_SHIFT_REG)
);

defparam rnode_166to167_bb1_cmp264_i_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_cmp264_i_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1_cmp264_i_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_cmp264_i_0_reg_167_fifo.IMPL = "shift_reg";

assign rnode_166to167_bb1_cmp264_i_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp264_i_stall_in = 1'b0;
assign rnode_166to167_bb1_cmp264_i_0_NO_SHIFT_REG = rnode_166to167_bb1_cmp264_i_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_cmp264_i_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp264_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_166to167_bb1_cmp266_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp266_i_0_stall_in_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp266_i_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp266_i_0_reg_167_inputs_ready_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp266_i_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp266_i_0_valid_out_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp266_i_0_stall_in_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp266_i_0_stall_out_reg_167_NO_SHIFT_REG;

acl_data_fifo rnode_166to167_bb1_cmp266_i_0_reg_167_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_166to167_bb1_cmp266_i_0_reg_167_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_166to167_bb1_cmp266_i_0_stall_in_reg_167_NO_SHIFT_REG),
	.valid_out(rnode_166to167_bb1_cmp266_i_0_valid_out_reg_167_NO_SHIFT_REG),
	.stall_out(rnode_166to167_bb1_cmp266_i_0_stall_out_reg_167_NO_SHIFT_REG),
	.data_in(local_bb1_cmp266_i),
	.data_out(rnode_166to167_bb1_cmp266_i_0_reg_167_NO_SHIFT_REG)
);

defparam rnode_166to167_bb1_cmp266_i_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_cmp266_i_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1_cmp266_i_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_cmp266_i_0_reg_167_fifo.IMPL = "shift_reg";

assign rnode_166to167_bb1_cmp266_i_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp266_i_stall_in = 1'b0;
assign rnode_166to167_bb1_cmp266_i_0_NO_SHIFT_REG = rnode_166to167_bb1_cmp266_i_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_cmp266_i_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp266_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_166to167_bb1_cmp210_not_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_not_i_0_stall_in_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_not_i_0_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_not_i_0_reg_167_inputs_ready_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_not_i_0_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_not_i_0_valid_out_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_not_i_0_stall_in_reg_167_NO_SHIFT_REG;
 logic rnode_166to167_bb1_cmp210_not_i_0_stall_out_reg_167_NO_SHIFT_REG;

acl_data_fifo rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_166to167_bb1_cmp210_not_i_0_reg_167_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_166to167_bb1_cmp210_not_i_0_stall_in_reg_167_NO_SHIFT_REG),
	.valid_out(rnode_166to167_bb1_cmp210_not_i_0_valid_out_reg_167_NO_SHIFT_REG),
	.stall_out(rnode_166to167_bb1_cmp210_not_i_0_stall_out_reg_167_NO_SHIFT_REG),
	.data_in(local_bb1_cmp210_not_i),
	.data_out(rnode_166to167_bb1_cmp210_not_i_0_reg_167_NO_SHIFT_REG)
);

defparam rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo.DEPTH = 1;
defparam rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo.DATA_WIDTH = 1;
defparam rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo.IMPL = "shift_reg";

assign rnode_166to167_bb1_cmp210_not_i_0_reg_167_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_cmp210_not_i_stall_in_1 = 1'b0;
assign rnode_166to167_bb1_cmp210_not_i_0_NO_SHIFT_REG = rnode_166to167_bb1_cmp210_not_i_0_reg_167_NO_SHIFT_REG;
assign rnode_166to167_bb1_cmp210_not_i_0_stall_in_reg_167_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp210_not_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// This section implements an unregistered operation.
// 
wire local_bb1_cmp231_i_stall_local;
wire local_bb1_cmp231_i;

assign local_bb1_cmp231_i = ((rnode_166to167_bb1_and230_i_0_NO_SHIFT_REG & 32'hFF) == 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_shl248_i_stall_local;
wire [31:0] local_bb1_shl248_i;

assign local_bb1_shl248_i = ((rnode_166to167_bb1_and230_i_1_NO_SHIFT_REG & 32'hFF) << 32'h17);

// This section implements an unregistered operation.
// 
wire local_bb1_and227_i_stall_local;
wire [31:0] local_bb1_and227_i;

assign local_bb1_and227_i = (rnode_166to167_bb1_add225_i_0_NO_SHIFT_REG & 32'h100);

// This section implements an unregistered operation.
// 
wire local_bb1_cmp236_i_stall_local;
wire local_bb1_cmp236_i;

assign local_bb1_cmp236_i = ($signed(rnode_166to167_bb1_add225_i_1_NO_SHIFT_REG) > $signed(32'hFE));

// This section implements an unregistered operation.
// 
wire local_bb1_and247_i_stall_local;
wire [31:0] local_bb1_and247_i;

assign local_bb1_and247_i = ((rnode_166to167_bb1_shr246_i_0_NO_SHIFT_REG & 32'h1FFFFFF) & 32'h7FFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1_conv267_i_stall_local;
wire [31:0] local_bb1_conv267_i;

assign local_bb1_conv267_i[31:1] = 31'h0;
assign local_bb1_conv267_i[0] = rnode_166to167_bb1_cmp266_i_0_NO_SHIFT_REG;

// This section implements an unregistered operation.
// 
wire local_bb1_tobool228_i_stall_local;
wire local_bb1_tobool228_i;

assign local_bb1_tobool228_i = ((local_bb1_and227_i & 32'h100) != 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_lnot239__i_stall_local;
wire local_bb1_lnot239__i;

assign local_bb1_lnot239__i = (local_bb1_cmp236_i & rnode_166to167_bb1_cmp210_not_i_0_NO_SHIFT_REG);

// This section implements an unregistered operation.
// 
wire local_bb1_or249_i_stall_local;
wire [31:0] local_bb1_or249_i;

assign local_bb1_or249_i = ((local_bb1_and247_i & 32'h7FFFFF) | (local_bb1_shl248_i & 32'h7F800000));

// This section implements an unregistered operation.
// 
wire local_bb1_or_cond_i_stall_local;
wire local_bb1_or_cond_i;

assign local_bb1_or_cond_i = (local_bb1_tobool228_i | local_bb1_cmp231_i);

// This section implements an unregistered operation.
// 
wire local_bb1_or242_i_stall_local;
wire local_bb1_or242_i;

assign local_bb1_or242_i = (rnode_166to167_bb1_var__u10_0_NO_SHIFT_REG | local_bb1_lnot239__i);

// This section implements an unregistered operation.
// 
wire local_bb1_or250_i_stall_local;
wire [31:0] local_bb1_or250_i;

assign local_bb1_or250_i = ((local_bb1_or249_i & 32'h7FFFFFFF) | (rnode_166to167_bb1_resultSign_0_i_0_NO_SHIFT_REG & 32'h80000000));

// This section implements an unregistered operation.
// 
wire local_bb1__31_i_stall_local;
wire local_bb1__31_i;

assign local_bb1__31_i = (local_bb1_or_cond_i | rnode_166to167_bb1_cmp210_i_0_NO_SHIFT_REG);

// This section implements an unregistered operation.
// 
wire local_bb1_or257_i_stall_local;
wire local_bb1_or257_i;

assign local_bb1_or257_i = (local_bb1_or242_i | rnode_166to167_bb1__13_i_0_NO_SHIFT_REG);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_9_demorgan_i_stall_local;
wire local_bb1_reduction_9_demorgan_i;

assign local_bb1_reduction_9_demorgan_i = (rnode_166to167_bb1__13_i_2_NO_SHIFT_REG | local_bb1_or242_i);

// This section implements an unregistered operation.
// 
wire local_bb1_or253_i_stall_local;
wire local_bb1_or253_i;

assign local_bb1_or253_i = (local_bb1__31_i | local_bb1_or242_i);

// This section implements an unregistered operation.
// 
wire local_bb1_lnot279_i_stall_local;
wire local_bb1_lnot279_i;

assign local_bb1_lnot279_i = (local_bb1__31_i ^ 1'b1);

// This section implements an unregistered operation.
// 
wire local_bb1_cond258_i_stall_local;
wire [31:0] local_bb1_cond258_i;

assign local_bb1_cond258_i = (local_bb1_or257_i ? 32'h7F800000 : 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_cond254_i_stall_local;
wire [31:0] local_bb1_cond254_i;

assign local_bb1_cond254_i = (local_bb1_or253_i ? 32'h80000000 : 32'hFFFFFFFF);

// This section implements an unregistered operation.
// 
wire local_bb1_or262_i_stall_local;
wire [31:0] local_bb1_or262_i;

assign local_bb1_or262_i = ((local_bb1_cond258_i & 32'h7F800000) | (local_bb1_cond260_i & 32'h400000));

// This section implements an unregistered operation.
// 
wire local_bb1_and261_i_stall_local;
wire [31:0] local_bb1_and261_i;

assign local_bb1_and261_i = ((local_bb1_cond254_i | 32'h80000000) & local_bb1_or250_i);

// This section implements an unregistered operation.
// 
wire local_bb1_or263_i_stall_local;
wire [31:0] local_bb1_or263_i;

assign local_bb1_or263_i = ((local_bb1_or262_i & 32'h7FC00000) | local_bb1_and261_i);

// This section implements an unregistered operation.
// 
wire local_bb1_and269_i_stall_local;
wire [31:0] local_bb1_and269_i;

assign local_bb1_and269_i = ((local_bb1_conv267_i & 32'h1) & local_bb1_and261_i);

// This section implements an unregistered operation.
// 
wire local_bb1_tobool270_i_stall_local;
wire local_bb1_tobool270_i;

assign local_bb1_tobool270_i = ((local_bb1_and269_i & 32'h1) != 32'h0);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_9_demorgan_i_valid_out;
wire local_bb1_reduction_9_demorgan_i_stall_in;
wire local_bb1_or263_i_valid_out;
wire local_bb1_or263_i_stall_in;
wire local_bb1_lnot279_i_valid_out;
wire local_bb1_lnot279_i_stall_in;
wire local_bb1__32_i_valid_out;
wire local_bb1__32_i_stall_in;
wire local_bb1__32_i_inputs_ready;
wire local_bb1__32_i_stall_local;
wire local_bb1__32_i;

assign local_bb1__32_i_inputs_ready = (rnode_166to167_bb1_add225_i_0_valid_out_0_NO_SHIFT_REG & rnode_166to167_bb1_and230_i_0_valid_out_0_NO_SHIFT_REG & rnode_166to167_bb1_cmp210_i_0_valid_out_NO_SHIFT_REG & rnode_166to167_bb1_add225_i_0_valid_out_1_NO_SHIFT_REG & rnode_166to167_bb1_cmp210_not_i_0_valid_out_NO_SHIFT_REG & rnode_166to167_bb1_var__u10_0_valid_out_NO_SHIFT_REG & rnode_166to167_bb1__13_i_0_valid_out_0_NO_SHIFT_REG & rnode_166to167_bb1__13_i_0_valid_out_2_NO_SHIFT_REG & rnode_166to167_bb1__13_i_0_valid_out_1_NO_SHIFT_REG & rnode_166to167_bb1_and230_i_0_valid_out_1_NO_SHIFT_REG & rnode_166to167_bb1_shr246_i_0_valid_out_NO_SHIFT_REG & rnode_166to167_bb1_resultSign_0_i_0_valid_out_NO_SHIFT_REG & rnode_166to167_bb1_cmp266_i_0_valid_out_NO_SHIFT_REG & rnode_166to167_bb1_cmp264_i_0_valid_out_NO_SHIFT_REG);
assign local_bb1__32_i = (rnode_166to167_bb1_cmp264_i_0_NO_SHIFT_REG | local_bb1_tobool270_i);
assign local_bb1_reduction_9_demorgan_i_valid_out = 1'b1;
assign local_bb1_or263_i_valid_out = 1'b1;
assign local_bb1_lnot279_i_valid_out = 1'b1;
assign local_bb1__32_i_valid_out = 1'b1;
assign rnode_166to167_bb1_add225_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_and230_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp210_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_add225_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp210_not_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_var__u10_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1__13_i_0_stall_in_0_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1__13_i_0_stall_in_2_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1__13_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_and230_i_0_stall_in_1_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_shr246_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_resultSign_0_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp266_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_166to167_bb1_cmp264_i_0_stall_in_NO_SHIFT_REG = 1'b0;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_167to168_bb1_reduction_9_demorgan_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_167to168_bb1_reduction_9_demorgan_i_0_stall_in_NO_SHIFT_REG;
 logic rnode_167to168_bb1_reduction_9_demorgan_i_0_NO_SHIFT_REG;
 logic rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_inputs_ready_NO_SHIFT_REG;
 logic rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_NO_SHIFT_REG;
 logic rnode_167to168_bb1_reduction_9_demorgan_i_0_valid_out_reg_168_NO_SHIFT_REG;
 logic rnode_167to168_bb1_reduction_9_demorgan_i_0_stall_in_reg_168_NO_SHIFT_REG;
 logic rnode_167to168_bb1_reduction_9_demorgan_i_0_stall_out_reg_168_NO_SHIFT_REG;

acl_data_fifo rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_167to168_bb1_reduction_9_demorgan_i_0_stall_in_reg_168_NO_SHIFT_REG),
	.valid_out(rnode_167to168_bb1_reduction_9_demorgan_i_0_valid_out_reg_168_NO_SHIFT_REG),
	.stall_out(rnode_167to168_bb1_reduction_9_demorgan_i_0_stall_out_reg_168_NO_SHIFT_REG),
	.data_in(local_bb1_reduction_9_demorgan_i),
	.data_out(rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_NO_SHIFT_REG)
);

defparam rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo.DATA_WIDTH = 1;
defparam rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo.IMPL = "shift_reg";

assign rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_reduction_9_demorgan_i_stall_in = 1'b0;
assign rnode_167to168_bb1_reduction_9_demorgan_i_0_NO_SHIFT_REG = rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_reduction_9_demorgan_i_0_stall_in_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_reduction_9_demorgan_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_167to168_bb1_or263_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_167to168_bb1_or263_i_0_stall_in_NO_SHIFT_REG;
 logic [31:0] rnode_167to168_bb1_or263_i_0_NO_SHIFT_REG;
 logic rnode_167to168_bb1_or263_i_0_reg_168_inputs_ready_NO_SHIFT_REG;
 logic [31:0] rnode_167to168_bb1_or263_i_0_reg_168_NO_SHIFT_REG;
 logic rnode_167to168_bb1_or263_i_0_valid_out_reg_168_NO_SHIFT_REG;
 logic rnode_167to168_bb1_or263_i_0_stall_in_reg_168_NO_SHIFT_REG;
 logic rnode_167to168_bb1_or263_i_0_stall_out_reg_168_NO_SHIFT_REG;

acl_data_fifo rnode_167to168_bb1_or263_i_0_reg_168_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_167to168_bb1_or263_i_0_reg_168_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_167to168_bb1_or263_i_0_stall_in_reg_168_NO_SHIFT_REG),
	.valid_out(rnode_167to168_bb1_or263_i_0_valid_out_reg_168_NO_SHIFT_REG),
	.stall_out(rnode_167to168_bb1_or263_i_0_stall_out_reg_168_NO_SHIFT_REG),
	.data_in(local_bb1_or263_i),
	.data_out(rnode_167to168_bb1_or263_i_0_reg_168_NO_SHIFT_REG)
);

defparam rnode_167to168_bb1_or263_i_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_or263_i_0_reg_168_fifo.DATA_WIDTH = 32;
defparam rnode_167to168_bb1_or263_i_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_or263_i_0_reg_168_fifo.IMPL = "shift_reg";

assign rnode_167to168_bb1_or263_i_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_or263_i_stall_in = 1'b0;
assign rnode_167to168_bb1_or263_i_0_NO_SHIFT_REG = rnode_167to168_bb1_or263_i_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_or263_i_0_stall_in_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_or263_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_167to168_bb1_lnot279_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_167to168_bb1_lnot279_i_0_stall_in_NO_SHIFT_REG;
 logic rnode_167to168_bb1_lnot279_i_0_NO_SHIFT_REG;
 logic rnode_167to168_bb1_lnot279_i_0_reg_168_inputs_ready_NO_SHIFT_REG;
 logic rnode_167to168_bb1_lnot279_i_0_reg_168_NO_SHIFT_REG;
 logic rnode_167to168_bb1_lnot279_i_0_valid_out_reg_168_NO_SHIFT_REG;
 logic rnode_167to168_bb1_lnot279_i_0_stall_in_reg_168_NO_SHIFT_REG;
 logic rnode_167to168_bb1_lnot279_i_0_stall_out_reg_168_NO_SHIFT_REG;

acl_data_fifo rnode_167to168_bb1_lnot279_i_0_reg_168_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_167to168_bb1_lnot279_i_0_reg_168_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_167to168_bb1_lnot279_i_0_stall_in_reg_168_NO_SHIFT_REG),
	.valid_out(rnode_167to168_bb1_lnot279_i_0_valid_out_reg_168_NO_SHIFT_REG),
	.stall_out(rnode_167to168_bb1_lnot279_i_0_stall_out_reg_168_NO_SHIFT_REG),
	.data_in(local_bb1_lnot279_i),
	.data_out(rnode_167to168_bb1_lnot279_i_0_reg_168_NO_SHIFT_REG)
);

defparam rnode_167to168_bb1_lnot279_i_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1_lnot279_i_0_reg_168_fifo.DATA_WIDTH = 1;
defparam rnode_167to168_bb1_lnot279_i_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1_lnot279_i_0_reg_168_fifo.IMPL = "shift_reg";

assign rnode_167to168_bb1_lnot279_i_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1_lnot279_i_stall_in = 1'b0;
assign rnode_167to168_bb1_lnot279_i_0_NO_SHIFT_REG = rnode_167to168_bb1_lnot279_i_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1_lnot279_i_0_stall_in_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_lnot279_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// Register node:
//  * latency = 1
//  * capacity = 1
 logic rnode_167to168_bb1__32_i_0_valid_out_NO_SHIFT_REG;
 logic rnode_167to168_bb1__32_i_0_stall_in_NO_SHIFT_REG;
 logic rnode_167to168_bb1__32_i_0_NO_SHIFT_REG;
 logic rnode_167to168_bb1__32_i_0_reg_168_inputs_ready_NO_SHIFT_REG;
 logic rnode_167to168_bb1__32_i_0_reg_168_NO_SHIFT_REG;
 logic rnode_167to168_bb1__32_i_0_valid_out_reg_168_NO_SHIFT_REG;
 logic rnode_167to168_bb1__32_i_0_stall_in_reg_168_NO_SHIFT_REG;
 logic rnode_167to168_bb1__32_i_0_stall_out_reg_168_NO_SHIFT_REG;

acl_data_fifo rnode_167to168_bb1__32_i_0_reg_168_fifo (
	.clock(clock),
	.resetn(resetn),
	.valid_in(rnode_167to168_bb1__32_i_0_reg_168_inputs_ready_NO_SHIFT_REG),
	.stall_in(rnode_167to168_bb1__32_i_0_stall_in_reg_168_NO_SHIFT_REG),
	.valid_out(rnode_167to168_bb1__32_i_0_valid_out_reg_168_NO_SHIFT_REG),
	.stall_out(rnode_167to168_bb1__32_i_0_stall_out_reg_168_NO_SHIFT_REG),
	.data_in(local_bb1__32_i),
	.data_out(rnode_167to168_bb1__32_i_0_reg_168_NO_SHIFT_REG)
);

defparam rnode_167to168_bb1__32_i_0_reg_168_fifo.DEPTH = 1;
defparam rnode_167to168_bb1__32_i_0_reg_168_fifo.DATA_WIDTH = 1;
defparam rnode_167to168_bb1__32_i_0_reg_168_fifo.ALLOW_FULL_WRITE = 1;
defparam rnode_167to168_bb1__32_i_0_reg_168_fifo.IMPL = "shift_reg";

assign rnode_167to168_bb1__32_i_0_reg_168_inputs_ready_NO_SHIFT_REG = 1'b1;
assign local_bb1__32_i_stall_in = 1'b0;
assign rnode_167to168_bb1__32_i_0_NO_SHIFT_REG = rnode_167to168_bb1__32_i_0_reg_168_NO_SHIFT_REG;
assign rnode_167to168_bb1__32_i_0_stall_in_reg_168_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1__32_i_0_valid_out_NO_SHIFT_REG = 1'b1;

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_9_i_stall_local;
wire local_bb1_reduction_9_i;

assign local_bb1_reduction_9_i = (rnode_167to168_bb1_reduction_9_demorgan_i_0_NO_SHIFT_REG ^ 1'b1);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_10_i_stall_local;
wire local_bb1_reduction_10_i;

assign local_bb1_reduction_10_i = (rnode_167to168_bb1__32_i_0_NO_SHIFT_REG & rnode_167to168_bb1_lnot279_i_0_NO_SHIFT_REG);

// This section implements an unregistered operation.
// 
wire local_bb1_reduction_11_i_stall_local;
wire local_bb1_reduction_11_i;

assign local_bb1_reduction_11_i = (local_bb1_reduction_10_i & local_bb1_reduction_9_i);

// This section implements an unregistered operation.
// 
wire local_bb1_conv283_i_stall_local;
wire [31:0] local_bb1_conv283_i;

assign local_bb1_conv283_i[31:1] = 31'h0;
assign local_bb1_conv283_i[0] = local_bb1_reduction_11_i;

// This section implements an unregistered operation.
// 
wire local_bb1_add284_i_stall_local;
wire [31:0] local_bb1_add284_i;

assign local_bb1_add284_i = ((local_bb1_conv283_i & 32'h1) + rnode_167to168_bb1_or263_i_0_NO_SHIFT_REG);

// This section implements an unregistered operation.
// 
wire local_bb1_var__u16_stall_local;
wire [31:0] local_bb1_var__u16;

assign local_bb1_var__u16 = local_bb1_add284_i;

// This section implements an unregistered operation.
// 
wire local_bb1_c0_exi1_valid_out;
wire local_bb1_c0_exi1_stall_in;
wire local_bb1_c0_exi1_inputs_ready;
wire local_bb1_c0_exi1_stall_local;
wire [63:0] local_bb1_c0_exi1;

assign local_bb1_c0_exi1_inputs_ready = (rnode_167to168_bb1_reduction_9_demorgan_i_0_valid_out_NO_SHIFT_REG & rnode_167to168_bb1__32_i_0_valid_out_NO_SHIFT_REG & rnode_167to168_bb1_lnot279_i_0_valid_out_NO_SHIFT_REG & rnode_167to168_bb1_or263_i_0_valid_out_NO_SHIFT_REG);
assign local_bb1_c0_exi1[31:0] = 32'bx;
assign local_bb1_c0_exi1[63:32] = local_bb1_var__u16;
assign local_bb1_c0_exi1_valid_out = 1'b1;
assign rnode_167to168_bb1_reduction_9_demorgan_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1__32_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_lnot279_i_0_stall_in_NO_SHIFT_REG = 1'b0;
assign rnode_167to168_bb1_or263_i_0_stall_in_NO_SHIFT_REG = 1'b0;

// This section implements a registered operation.
// 
wire local_bb1_c0_exit_c0_exi1_inputs_ready;
 reg local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG;
wire local_bb1_c0_exit_c0_exi1_stall_in;
 reg [63:0] local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG;
wire [63:0] local_bb1_c0_exit_c0_exi1_in;
wire local_bb1_c0_exit_c0_exi1_valid;
wire local_bb1_c0_exit_c0_exi1_causedstall;

acl_stall_free_sink local_bb1_c0_exit_c0_exi1_instance (
	.clock(clock),
	.resetn(resetn),
	.data_in(local_bb1_c0_exi1),
	.data_out(local_bb1_c0_exit_c0_exi1_in),
	.input_accepted(local_bb1_c0_enter_c0_eni2_input_accepted),
	.valid_out(local_bb1_c0_exit_c0_exi1_valid),
	.stall_in(~(local_bb1_c0_exit_c0_exi1_output_regs_ready)),
	.stall_entry(local_bb1_c0_exit_c0_exi1_entry_stall),
	.valid_in(local_bb1_c0_exit_c0_exi1_valid_in),
	.IIphases(local_bb1_c0_exit_c0_exi1_phases),
	.inc_pipelined_thread(local_bb1_c0_enter_c0_eni2_inc_pipelined_thread),
	.dec_pipelined_thread(local_bb1_c0_enter_c0_eni2_dec_pipelined_thread)
);

defparam local_bb1_c0_exit_c0_exi1_instance.DATA_WIDTH = 64;
defparam local_bb1_c0_exit_c0_exi1_instance.PIPELINE_DEPTH = 12;
defparam local_bb1_c0_exit_c0_exi1_instance.SHARINGII = 1;
defparam local_bb1_c0_exit_c0_exi1_instance.SCHEDULEII = 1;
defparam local_bb1_c0_exit_c0_exi1_instance.ALWAYS_THROTTLE = 0;

assign local_bb1_c0_exit_c0_exi1_inputs_ready = 1'b1;
assign local_bb1_c0_exit_c0_exi1_output_regs_ready = (&(~(local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG) | ~(local_bb1_c0_exit_c0_exi1_stall_in)));
assign local_bb1_c0_exit_c0_exi1_valid_in = SFC_1_VALID_167_168_0_NO_SHIFT_REG;
assign local_bb1_c0_exi1_stall_in = 1'b0;
assign SFC_1_VALID_167_168_0_stall_in = 1'b0;
assign local_bb1_c0_exit_c0_exi1_causedstall = (1'b1 && (1'b0 && !(~(local_bb1_c0_exit_c0_exi1_output_regs_ready))));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG <= 'x;
		local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (local_bb1_c0_exit_c0_exi1_output_regs_ready)
		begin
			local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG <= local_bb1_c0_exit_c0_exi1_in;
			local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG <= local_bb1_c0_exit_c0_exi1_valid;
		end
		else
		begin
			if (~(local_bb1_c0_exit_c0_exi1_stall_in))
			begin
				local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end


// This section implements an unregistered operation.
// 
wire local_bb1_c0_exe1_valid_out;
wire local_bb1_c0_exe1_stall_in;
wire local_bb1_c0_exe1_inputs_ready;
wire local_bb1_c0_exe1_stall_local;
wire [31:0] local_bb1_c0_exe1;

assign local_bb1_c0_exe1_inputs_ready = local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG;
assign local_bb1_c0_exe1 = local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63:32];
assign local_bb1_c0_exe1_valid_out = local_bb1_c0_exe1_inputs_ready;
assign local_bb1_c0_exe1_stall_local = local_bb1_c0_exe1_stall_in;
assign local_bb1_c0_exit_c0_exi1_stall_in = (|local_bb1_c0_exe1_stall_local);

// This section implements a registered operation.
// 
wire local_bb1_st_c0_exe1_inputs_ready;
 reg local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG;
wire local_bb1_st_c0_exe1_stall_in;
wire local_bb1_st_c0_exe1_output_regs_ready;
wire local_bb1_st_c0_exe1_fu_stall_out;
wire local_bb1_st_c0_exe1_fu_valid_out;
wire local_bb1_st_c0_exe1_causedstall;

lsu_top lsu_local_bb1_st_c0_exe1 (
	.clock(clock),
	.clock2x(clock2x),
	.resetn(resetn),
	.flush(start),
	.stream_base_addr(),
	.stream_size(),
	.stream_reset(),
	.o_stall(local_bb1_st_c0_exe1_fu_stall_out),
	.i_valid(local_bb1_st_c0_exe1_inputs_ready),
	.i_address((rnode_172to173_bb1_arrayidx5_RM_0_NO_SHIFT_REG & 64'hFFFFFFFFFFFFFFFC)),
	.i_writedata(local_bb1_c0_exe1),
	.i_cmpdata(),
	.i_predicate(1'b0),
	.i_bitwiseor(64'h0),
	.i_byteenable(),
	.i_stall(~(local_bb1_st_c0_exe1_output_regs_ready)),
	.o_valid(local_bb1_st_c0_exe1_fu_valid_out),
	.o_readdata(),
	.o_input_fifo_depth(),
	.o_writeack(),
	.i_atomic_op(3'h0),
	.o_active(local_bb1_st_c0_exe1_active),
	.avm_address(avm_local_bb1_st_c0_exe1_address),
	.avm_read(avm_local_bb1_st_c0_exe1_read),
	.avm_enable(avm_local_bb1_st_c0_exe1_enable),
	.avm_readdata(avm_local_bb1_st_c0_exe1_readdata),
	.avm_write(avm_local_bb1_st_c0_exe1_write),
	.avm_writeack(avm_local_bb1_st_c0_exe1_writeack),
	.avm_burstcount(avm_local_bb1_st_c0_exe1_burstcount),
	.avm_writedata(avm_local_bb1_st_c0_exe1_writedata),
	.avm_byteenable(avm_local_bb1_st_c0_exe1_byteenable),
	.avm_waitrequest(avm_local_bb1_st_c0_exe1_waitrequest),
	.avm_readdatavalid(avm_local_bb1_st_c0_exe1_readdatavalid),
	.profile_bw(),
	.profile_bw_incr(),
	.profile_total_ivalid(),
	.profile_total_req(),
	.profile_i_stall_count(),
	.profile_o_stall_count(),
	.profile_avm_readwrite_count(),
	.profile_avm_burstcount_total(),
	.profile_avm_burstcount_total_incr(),
	.profile_req_cache_hit_count(),
	.profile_extra_unaligned_reqs(),
	.profile_avm_stall()
);

defparam lsu_local_bb1_st_c0_exe1.AWIDTH = 31;
defparam lsu_local_bb1_st_c0_exe1.WIDTH_BYTES = 4;
defparam lsu_local_bb1_st_c0_exe1.MWIDTH_BYTES = 32;
defparam lsu_local_bb1_st_c0_exe1.WRITEDATAWIDTH_BYTES = 32;
defparam lsu_local_bb1_st_c0_exe1.ALIGNMENT_BYTES = 4;
defparam lsu_local_bb1_st_c0_exe1.READ = 0;
defparam lsu_local_bb1_st_c0_exe1.ATOMIC = 0;
defparam lsu_local_bb1_st_c0_exe1.WIDTH = 32;
defparam lsu_local_bb1_st_c0_exe1.MWIDTH = 256;
defparam lsu_local_bb1_st_c0_exe1.ATOMIC_WIDTH = 3;
defparam lsu_local_bb1_st_c0_exe1.BURSTCOUNT_WIDTH = 5;
defparam lsu_local_bb1_st_c0_exe1.KERNEL_SIDE_MEM_LATENCY = 160;
defparam lsu_local_bb1_st_c0_exe1.MEMORY_SIDE_MEM_LATENCY = 10;
defparam lsu_local_bb1_st_c0_exe1.USE_WRITE_ACK = 1;
defparam lsu_local_bb1_st_c0_exe1.ENABLE_BANKED_MEMORY = 0;
defparam lsu_local_bb1_st_c0_exe1.ABITS_PER_LMEM_BANK = 0;
defparam lsu_local_bb1_st_c0_exe1.NUMBER_BANKS = 1;
defparam lsu_local_bb1_st_c0_exe1.LMEM_ADDR_PERMUTATION_STYLE = 0;
defparam lsu_local_bb1_st_c0_exe1.INTENDED_DEVICE_FAMILY = "Cyclone V";
defparam lsu_local_bb1_st_c0_exe1.USEINPUTFIFO = 0;
defparam lsu_local_bb1_st_c0_exe1.USECACHING = 0;
defparam lsu_local_bb1_st_c0_exe1.USEOUTPUTFIFO = 1;
defparam lsu_local_bb1_st_c0_exe1.FORCE_NOP_SUPPORT = 0;
defparam lsu_local_bb1_st_c0_exe1.ADDRSPACE = 1;
defparam lsu_local_bb1_st_c0_exe1.STYLE = "BURST-COALESCED";
defparam lsu_local_bb1_st_c0_exe1.USE_BYTE_EN = 0;

assign local_bb1_st_c0_exe1_inputs_ready = (local_bb1_c0_exe1_valid_out & rnode_172to173_bb1_arrayidx5_RM_0_valid_out_NO_SHIFT_REG);
assign local_bb1_st_c0_exe1_output_regs_ready = (&(~(local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG) | ~(local_bb1_st_c0_exe1_stall_in)));
assign local_bb1_c0_exe1_stall_in = (local_bb1_st_c0_exe1_fu_stall_out | ~(local_bb1_st_c0_exe1_inputs_ready));
assign rnode_172to173_bb1_arrayidx5_RM_0_stall_in_NO_SHIFT_REG = (local_bb1_st_c0_exe1_fu_stall_out | ~(local_bb1_st_c0_exe1_inputs_ready));
assign local_bb1_st_c0_exe1_causedstall = (local_bb1_st_c0_exe1_inputs_ready && (local_bb1_st_c0_exe1_fu_stall_out && !(~(local_bb1_st_c0_exe1_output_regs_ready))));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (local_bb1_st_c0_exe1_output_regs_ready)
		begin
			local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG <= local_bb1_st_c0_exe1_fu_valid_out;
		end
		else
		begin
			if (~(local_bb1_st_c0_exe1_stall_in))
			begin
				local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end


// This section implements a staging register.
// 
wire rstag_333to333_bb1_st_c0_exe1_valid_out;
wire rstag_333to333_bb1_st_c0_exe1_stall_in;
wire rstag_333to333_bb1_st_c0_exe1_inputs_ready;
wire rstag_333to333_bb1_st_c0_exe1_stall_local;
 reg rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG;
wire rstag_333to333_bb1_st_c0_exe1_combined_valid;

assign rstag_333to333_bb1_st_c0_exe1_inputs_ready = local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG;
assign rstag_333to333_bb1_st_c0_exe1_combined_valid = (rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG | rstag_333to333_bb1_st_c0_exe1_inputs_ready);
assign rstag_333to333_bb1_st_c0_exe1_valid_out = rstag_333to333_bb1_st_c0_exe1_combined_valid;
assign rstag_333to333_bb1_st_c0_exe1_stall_local = rstag_333to333_bb1_st_c0_exe1_stall_in;
assign local_bb1_st_c0_exe1_stall_in = (|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (rstag_333to333_bb1_st_c0_exe1_stall_local)
		begin
			if (~(rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG))
			begin
				rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG <= rstag_333to333_bb1_st_c0_exe1_inputs_ready;
			end
		end
		else
		begin
			rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG <= 1'b0;
		end
	end
end


// This section describes the behaviour of the BRANCH node.
wire branch_var__inputs_ready;
 reg branch_node_valid_out_0_NO_SHIFT_REG;
 reg branch_compare_result_NO_SHIFT_REG;
wire branch_var__output_regs_ready;
wire combined_branch_stall_in_signal;
 reg [31:0] lvb_bb1_inc_0_reg_NO_SHIFT_REG;
 reg [31:0] lvb_input_global_id_0_0_reg_NO_SHIFT_REG;

assign branch_var__inputs_ready = (local_bb1_exitcond_valid_out & rcnode_332to333_rc0_bb1_inc_0_valid_out_1_NO_SHIFT_REG & rstag_333to333_bb1_st_c0_exe1_valid_out);
assign branch_var__output_regs_ready = (~(branch_node_valid_out_0_NO_SHIFT_REG) | (((branch_compare_result_NO_SHIFT_REG != 1'b1) & ~(stall_in_1)) | (~((branch_compare_result_NO_SHIFT_REG != 1'b1)) & ~(stall_in_0))));
assign local_bb1_exitcond_stall_in = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign rcnode_332to333_rc0_bb1_inc_0_stall_in_1_NO_SHIFT_REG = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign rstag_333to333_bb1_st_c0_exe1_stall_in = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign lvb_bb1_inc_0 = lvb_bb1_inc_0_reg_NO_SHIFT_REG;
assign lvb_bb1_inc_1 = lvb_bb1_inc_0_reg_NO_SHIFT_REG;
assign lvb_input_global_id_0_0 = lvb_input_global_id_0_0_reg_NO_SHIFT_REG;
assign lvb_input_global_id_0_1 = lvb_input_global_id_0_0_reg_NO_SHIFT_REG;
assign valid_out_0 = (~((branch_compare_result_NO_SHIFT_REG != 1'b1)) & branch_node_valid_out_0_NO_SHIFT_REG);
assign valid_out_1 = ((branch_compare_result_NO_SHIFT_REG != 1'b1) & branch_node_valid_out_0_NO_SHIFT_REG);
assign combined_branch_stall_in_signal = ((((branch_compare_result_NO_SHIFT_REG != 1'b1) & branch_node_valid_out_0_NO_SHIFT_REG) & stall_in_1) | ((~((branch_compare_result_NO_SHIFT_REG != 1'b1)) & branch_node_valid_out_0_NO_SHIFT_REG) & stall_in_0));

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		branch_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
		lvb_bb1_inc_0_reg_NO_SHIFT_REG <= 'x;
		lvb_input_global_id_0_0_reg_NO_SHIFT_REG <= 'x;
		branch_compare_result_NO_SHIFT_REG <= 'x;
	end
	else
	begin
		if (branch_var__output_regs_ready)
		begin
			branch_node_valid_out_0_NO_SHIFT_REG <= branch_var__inputs_ready;
			lvb_bb1_inc_0_reg_NO_SHIFT_REG <= (rcnode_332to333_rc0_bb1_inc_0_NO_SHIFT_REG[31:0] & 32'h7FF);
			lvb_input_global_id_0_0_reg_NO_SHIFT_REG <= rcnode_332to333_rc0_bb1_inc_0_NO_SHIFT_REG[63:32];
			branch_compare_result_NO_SHIFT_REG <= local_bb1_exitcond;
		end
		else
		begin
			if (~(combined_branch_stall_in_signal))
			begin
				branch_node_valid_out_0_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end


endmodule

//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////

// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module float_add_basic_block_2
	(
		input 		clock,
		input 		resetn,
		input 		valid_in,
		output 		stall_out,
		output 		valid_out,
		input 		stall_in,
		input [31:0] 		workgroup_size,
		input 		start
	);


// Values used for debugging.  These are swept away by synthesis.
wire _entry;
wire _exit;
 reg [31:0] _num_entry_NO_SHIFT_REG;
 reg [31:0] _num_exit_NO_SHIFT_REG;
wire [31:0] _num_live;

assign _entry = ((&valid_in) & ~((|stall_out)));
assign _exit = ((&valid_out) & ~((|stall_in)));
assign _num_live = (_num_entry_NO_SHIFT_REG - _num_exit_NO_SHIFT_REG);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		_num_entry_NO_SHIFT_REG <= 32'h0;
		_num_exit_NO_SHIFT_REG <= 32'h0;
	end
	else
	begin
		if (_entry)
		begin
			_num_entry_NO_SHIFT_REG <= (_num_entry_NO_SHIFT_REG + 2'h1);
		end
		if (_exit)
		begin
			_num_exit_NO_SHIFT_REG <= (_num_exit_NO_SHIFT_REG + 2'h1);
		end
	end
end



// This section defines the behaviour of the MERGE node
wire merge_node_stall_in;
 reg merge_node_valid_out_NO_SHIFT_REG;
wire merge_stalled_by_successors;
 reg merge_block_selector_NO_SHIFT_REG;
 reg merge_node_valid_in_staging_reg_NO_SHIFT_REG;
 reg is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
 reg invariant_valid_NO_SHIFT_REG;

assign merge_stalled_by_successors = (|(merge_node_stall_in & merge_node_valid_out_NO_SHIFT_REG));
assign stall_out = merge_node_valid_in_staging_reg_NO_SHIFT_REG;

always @(*)
begin
	if ((merge_node_valid_in_staging_reg_NO_SHIFT_REG | valid_in))
	begin
		merge_block_selector_NO_SHIFT_REG = 1'b0;
		is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b1;
	end
	else
	begin
		merge_block_selector_NO_SHIFT_REG = 1'b0;
		is_merge_data_to_local_regs_valid_NO_SHIFT_REG = 1'b0;
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (((merge_block_selector_NO_SHIFT_REG != 1'b0) | merge_stalled_by_successors))
		begin
			if (~(merge_node_valid_in_staging_reg_NO_SHIFT_REG))
			begin
				merge_node_valid_in_staging_reg_NO_SHIFT_REG <= valid_in;
			end
		end
		else
		begin
			merge_node_valid_in_staging_reg_NO_SHIFT_REG <= 1'b0;
		end
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		merge_node_valid_out_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		if (~(merge_stalled_by_successors))
		begin
			merge_node_valid_out_NO_SHIFT_REG <= is_merge_data_to_local_regs_valid_NO_SHIFT_REG;
		end
		else
		begin
			if (~(merge_node_stall_in))
			begin
				merge_node_valid_out_NO_SHIFT_REG <= 1'b0;
			end
		end
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		invariant_valid_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		invariant_valid_NO_SHIFT_REG <= (~(start) & (invariant_valid_NO_SHIFT_REG | is_merge_data_to_local_regs_valid_NO_SHIFT_REG));
	end
end


// This section describes the behaviour of the BRANCH node.
wire branch_var__inputs_ready;
wire branch_var__output_regs_ready;

assign branch_var__inputs_ready = merge_node_valid_out_NO_SHIFT_REG;
assign branch_var__output_regs_ready = ~(stall_in);
assign merge_node_stall_in = (~(branch_var__output_regs_ready) | ~(branch_var__inputs_ready));
assign valid_out = branch_var__inputs_ready;

endmodule

//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////

// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module float_add_function
	(
		input 		clock,
		input 		resetn,
		input [31:0] 		input_global_id_0,
		output 		stall_out,
		input 		valid_in,
		output 		valid_out,
		input 		stall_in,
		input [31:0] 		workgroup_size,
		output 		avm_local_bb1_ld__enable,
		input [255:0] 		avm_local_bb1_ld__readdata,
		input 		avm_local_bb1_ld__readdatavalid,
		input 		avm_local_bb1_ld__waitrequest,
		output [30:0] 		avm_local_bb1_ld__address,
		output 		avm_local_bb1_ld__read,
		output 		avm_local_bb1_ld__write,
		input 		avm_local_bb1_ld__writeack,
		output [255:0] 		avm_local_bb1_ld__writedata,
		output [31:0] 		avm_local_bb1_ld__byteenable,
		output [4:0] 		avm_local_bb1_ld__burstcount,
		output 		avm_local_bb1_ld__u0_enable,
		input [255:0] 		avm_local_bb1_ld__u0_readdata,
		input 		avm_local_bb1_ld__u0_readdatavalid,
		input 		avm_local_bb1_ld__u0_waitrequest,
		output [30:0] 		avm_local_bb1_ld__u0_address,
		output 		avm_local_bb1_ld__u0_read,
		output 		avm_local_bb1_ld__u0_write,
		input 		avm_local_bb1_ld__u0_writeack,
		output [255:0] 		avm_local_bb1_ld__u0_writedata,
		output [31:0] 		avm_local_bb1_ld__u0_byteenable,
		output [4:0] 		avm_local_bb1_ld__u0_burstcount,
		output 		avm_local_bb1_st_c0_exe1_enable,
		input [255:0] 		avm_local_bb1_st_c0_exe1_readdata,
		input 		avm_local_bb1_st_c0_exe1_readdatavalid,
		input 		avm_local_bb1_st_c0_exe1_waitrequest,
		output [30:0] 		avm_local_bb1_st_c0_exe1_address,
		output 		avm_local_bb1_st_c0_exe1_read,
		output 		avm_local_bb1_st_c0_exe1_write,
		input 		avm_local_bb1_st_c0_exe1_writeack,
		output [255:0] 		avm_local_bb1_st_c0_exe1_writedata,
		output [31:0] 		avm_local_bb1_st_c0_exe1_byteenable,
		output [4:0] 		avm_local_bb1_st_c0_exe1_burstcount,
		input 		start,
		input 		clock2x,
		input [63:0] 		input_x,
		input [63:0] 		input_y,
		input [63:0] 		input_z,
		output reg 		has_a_write_pending,
		output reg 		has_a_lsu_active
	);


wire [31:0] cur_cycle;
wire bb_0_stall_out;
wire bb_0_valid_out;
wire [31:0] bb_0_lvb_input_global_id_0;
wire bb_1_stall_out_0;
wire bb_1_stall_out_1;
wire bb_1_valid_out_0;
wire [31:0] bb_1_lvb_bb1_inc_0;
wire [31:0] bb_1_lvb_input_global_id_0_0;
wire bb_1_valid_out_1;
wire [31:0] bb_1_lvb_bb1_inc_1;
wire [31:0] bb_1_lvb_input_global_id_0_1;
wire bb_1_local_bb1_ld__active;
wire bb_1_local_bb1_ld__u0_active;
wire bb_1_local_bb1_st_c0_exe1_active;
wire bb_2_stall_out;
wire bb_2_valid_out;
wire loop_limiter_0_stall_out;
wire loop_limiter_0_valid_out;
wire writes_pending;
wire [2:0] lsus_active;

float_add_basic_block_0 float_add_basic_block_0 (
	.clock(clock),
	.resetn(resetn),
	.valid_in(valid_in),
	.stall_out(bb_0_stall_out),
	.input_global_id_0(input_global_id_0),
	.valid_out(bb_0_valid_out),
	.stall_in(loop_limiter_0_stall_out),
	.lvb_input_global_id_0(bb_0_lvb_input_global_id_0),
	.workgroup_size(workgroup_size),
	.start(start)
);


float_add_basic_block_1 float_add_basic_block_1 (
	.clock(clock),
	.resetn(resetn),
	.input_x(input_x),
	.input_y(input_y),
	.input_z(input_z),
	.valid_in_0(bb_1_valid_out_1),
	.stall_out_0(bb_1_stall_out_0),
	.input_t_01_0(bb_1_lvb_bb1_inc_1),
	.input_global_id_0_0(bb_1_lvb_input_global_id_0_1),
	.valid_in_1(loop_limiter_0_valid_out),
	.stall_out_1(bb_1_stall_out_1),
	.input_t_01_1(32'h0),
	.input_global_id_0_1(bb_0_lvb_input_global_id_0),
	.valid_out_0(bb_1_valid_out_0),
	.stall_in_0(bb_2_stall_out),
	.lvb_bb1_inc_0(bb_1_lvb_bb1_inc_0),
	.lvb_input_global_id_0_0(bb_1_lvb_input_global_id_0_0),
	.valid_out_1(bb_1_valid_out_1),
	.stall_in_1(bb_1_stall_out_0),
	.lvb_bb1_inc_1(bb_1_lvb_bb1_inc_1),
	.lvb_input_global_id_0_1(bb_1_lvb_input_global_id_0_1),
	.workgroup_size(workgroup_size),
	.start(start),
	.avm_local_bb1_ld__enable(avm_local_bb1_ld__enable),
	.avm_local_bb1_ld__readdata(avm_local_bb1_ld__readdata),
	.avm_local_bb1_ld__readdatavalid(avm_local_bb1_ld__readdatavalid),
	.avm_local_bb1_ld__waitrequest(avm_local_bb1_ld__waitrequest),
	.avm_local_bb1_ld__address(avm_local_bb1_ld__address),
	.avm_local_bb1_ld__read(avm_local_bb1_ld__read),
	.avm_local_bb1_ld__write(avm_local_bb1_ld__write),
	.avm_local_bb1_ld__writeack(avm_local_bb1_ld__writeack),
	.avm_local_bb1_ld__writedata(avm_local_bb1_ld__writedata),
	.avm_local_bb1_ld__byteenable(avm_local_bb1_ld__byteenable),
	.avm_local_bb1_ld__burstcount(avm_local_bb1_ld__burstcount),
	.local_bb1_ld__active(bb_1_local_bb1_ld__active),
	.clock2x(clock2x),
	.avm_local_bb1_ld__u0_enable(avm_local_bb1_ld__u0_enable),
	.avm_local_bb1_ld__u0_readdata(avm_local_bb1_ld__u0_readdata),
	.avm_local_bb1_ld__u0_readdatavalid(avm_local_bb1_ld__u0_readdatavalid),
	.avm_local_bb1_ld__u0_waitrequest(avm_local_bb1_ld__u0_waitrequest),
	.avm_local_bb1_ld__u0_address(avm_local_bb1_ld__u0_address),
	.avm_local_bb1_ld__u0_read(avm_local_bb1_ld__u0_read),
	.avm_local_bb1_ld__u0_write(avm_local_bb1_ld__u0_write),
	.avm_local_bb1_ld__u0_writeack(avm_local_bb1_ld__u0_writeack),
	.avm_local_bb1_ld__u0_writedata(avm_local_bb1_ld__u0_writedata),
	.avm_local_bb1_ld__u0_byteenable(avm_local_bb1_ld__u0_byteenable),
	.avm_local_bb1_ld__u0_burstcount(avm_local_bb1_ld__u0_burstcount),
	.local_bb1_ld__u0_active(bb_1_local_bb1_ld__u0_active),
	.avm_local_bb1_st_c0_exe1_enable(avm_local_bb1_st_c0_exe1_enable),
	.avm_local_bb1_st_c0_exe1_readdata(avm_local_bb1_st_c0_exe1_readdata),
	.avm_local_bb1_st_c0_exe1_readdatavalid(avm_local_bb1_st_c0_exe1_readdatavalid),
	.avm_local_bb1_st_c0_exe1_waitrequest(avm_local_bb1_st_c0_exe1_waitrequest),
	.avm_local_bb1_st_c0_exe1_address(avm_local_bb1_st_c0_exe1_address),
	.avm_local_bb1_st_c0_exe1_read(avm_local_bb1_st_c0_exe1_read),
	.avm_local_bb1_st_c0_exe1_write(avm_local_bb1_st_c0_exe1_write),
	.avm_local_bb1_st_c0_exe1_writeack(avm_local_bb1_st_c0_exe1_writeack),
	.avm_local_bb1_st_c0_exe1_writedata(avm_local_bb1_st_c0_exe1_writedata),
	.avm_local_bb1_st_c0_exe1_byteenable(avm_local_bb1_st_c0_exe1_byteenable),
	.avm_local_bb1_st_c0_exe1_burstcount(avm_local_bb1_st_c0_exe1_burstcount),
	.local_bb1_st_c0_exe1_active(bb_1_local_bb1_st_c0_exe1_active)
);


float_add_basic_block_2 float_add_basic_block_2 (
	.clock(clock),
	.resetn(resetn),
	.valid_in(bb_1_valid_out_0),
	.stall_out(bb_2_stall_out),
	.valid_out(bb_2_valid_out),
	.stall_in(stall_in),
	.workgroup_size(workgroup_size),
	.start(start)
);


acl_loop_limiter loop_limiter_0 (
	.clock(clock),
	.resetn(resetn),
	.i_valid(bb_0_valid_out),
	.i_stall(bb_1_stall_out_1),
	.i_valid_exit(bb_1_valid_out_0),
	.i_stall_exit(bb_2_stall_out),
	.o_valid(loop_limiter_0_valid_out),
	.o_stall(loop_limiter_0_stall_out)
);

defparam loop_limiter_0.ENTRY_WIDTH = 1;
defparam loop_limiter_0.EXIT_WIDTH = 1;
defparam loop_limiter_0.THRESHOLD = 334;

float_add_sys_cycle_time system_cycle_time_module (
	.clock(clock),
	.resetn(resetn),
	.cur_cycle(cur_cycle)
);


assign valid_out = bb_2_valid_out;
assign stall_out = bb_0_stall_out;
assign writes_pending = bb_1_local_bb1_st_c0_exe1_active;
assign lsus_active[0] = bb_1_local_bb1_ld__active;
assign lsus_active[1] = bb_1_local_bb1_ld__u0_active;
assign lsus_active[2] = bb_1_local_bb1_st_c0_exe1_active;

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		has_a_write_pending <= 1'b0;
		has_a_lsu_active <= 1'b0;
	end
	else
	begin
		has_a_write_pending <= (|writes_pending);
		has_a_lsu_active <= (|lsus_active);
	end
end

endmodule

//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////

// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module float_add_function_wrapper
	(
		input 		clock,
		input 		resetn,
		input 		clock2x,
		input 		local_router_hang,
		input 		avs_cra_enable,
		input 		avs_cra_read,
		input 		avs_cra_write,
		input [3:0] 		avs_cra_address,
		input [63:0] 		avs_cra_writedata,
		input [7:0] 		avs_cra_byteenable,
		output reg [63:0] 		avs_cra_readdata,
		output reg 		avs_cra_readdatavalid,
		output 		cra_irq,
		output 		avm_local_bb1_ld__inst0_enable,
		input [255:0] 		avm_local_bb1_ld__inst0_readdata,
		input 		avm_local_bb1_ld__inst0_readdatavalid,
		input 		avm_local_bb1_ld__inst0_waitrequest,
		output [30:0] 		avm_local_bb1_ld__inst0_address,
		output 		avm_local_bb1_ld__inst0_read,
		output 		avm_local_bb1_ld__inst0_write,
		input 		avm_local_bb1_ld__inst0_writeack,
		output [255:0] 		avm_local_bb1_ld__inst0_writedata,
		output [31:0] 		avm_local_bb1_ld__inst0_byteenable,
		output [4:0] 		avm_local_bb1_ld__inst0_burstcount,
		output 		avm_local_bb1_ld__u0_inst0_enable,
		input [255:0] 		avm_local_bb1_ld__u0_inst0_readdata,
		input 		avm_local_bb1_ld__u0_inst0_readdatavalid,
		input 		avm_local_bb1_ld__u0_inst0_waitrequest,
		output [30:0] 		avm_local_bb1_ld__u0_inst0_address,
		output 		avm_local_bb1_ld__u0_inst0_read,
		output 		avm_local_bb1_ld__u0_inst0_write,
		input 		avm_local_bb1_ld__u0_inst0_writeack,
		output [255:0] 		avm_local_bb1_ld__u0_inst0_writedata,
		output [31:0] 		avm_local_bb1_ld__u0_inst0_byteenable,
		output [4:0] 		avm_local_bb1_ld__u0_inst0_burstcount,
		output 		avm_local_bb1_st_c0_exe1_inst0_enable,
		input [255:0] 		avm_local_bb1_st_c0_exe1_inst0_readdata,
		input 		avm_local_bb1_st_c0_exe1_inst0_readdatavalid,
		input 		avm_local_bb1_st_c0_exe1_inst0_waitrequest,
		output [30:0] 		avm_local_bb1_st_c0_exe1_inst0_address,
		output 		avm_local_bb1_st_c0_exe1_inst0_read,
		output 		avm_local_bb1_st_c0_exe1_inst0_write,
		input 		avm_local_bb1_st_c0_exe1_inst0_writeack,
		output [255:0] 		avm_local_bb1_st_c0_exe1_inst0_writedata,
		output [31:0] 		avm_local_bb1_st_c0_exe1_inst0_byteenable,
		output [4:0] 		avm_local_bb1_st_c0_exe1_inst0_burstcount
	);

// Responsible for interfacing a kernel with the outside world. It comprises a
// slave interface to specify the kernel arguments and retain kernel status. 

// This section of the wrapper implements the slave interface.
// twoXclock_consumer uses clock2x, even if nobody inside the kernel does. Keeps interface to acl_iface consistent for all kernels.
 reg start_NO_SHIFT_REG;
 reg started_NO_SHIFT_REG;
wire finish;
 reg [31:0] status_NO_SHIFT_REG;
wire has_a_write_pending;
wire has_a_lsu_active;
 reg [191:0] kernel_arguments_NO_SHIFT_REG;
 reg twoXclock_consumer_NO_SHIFT_REG /* synthesis  preserve  noprune  */;
 reg [31:0] workgroup_size_NO_SHIFT_REG;
 reg [31:0] global_size_NO_SHIFT_REG[2:0];
 reg [31:0] num_groups_NO_SHIFT_REG[2:0];
 reg [31:0] local_size_NO_SHIFT_REG[2:0];
 reg [31:0] work_dim_NO_SHIFT_REG;
 reg [31:0] global_offset_NO_SHIFT_REG[2:0];
 reg [63:0] profile_data_NO_SHIFT_REG;
 reg [31:0] profile_ctrl_NO_SHIFT_REG;
 reg [63:0] profile_start_cycle_NO_SHIFT_REG;
 reg [63:0] profile_stop_cycle_NO_SHIFT_REG;
wire dispatched_all_groups;
wire [31:0] group_id_tmp[2:0];
wire [31:0] global_id_base_out[2:0];
wire start_out;
wire [31:0] local_id[0:0][2:0];
wire [31:0] global_id[0:0][2:0];
wire [31:0] group_id[0:0][2:0];
wire iter_valid_in;
wire iter_stall_out;
wire stall_in;
wire stall_out;
wire valid_in;
wire valid_out;

always @(posedge clock2x or negedge resetn)
begin
	if (~(resetn))
	begin
		twoXclock_consumer_NO_SHIFT_REG <= 1'b0;
	end
	else
	begin
		twoXclock_consumer_NO_SHIFT_REG <= 1'b1;
	end
end



// Work group dispatcher is responsible for issuing work-groups to id iterator(s)
acl_work_group_dispatcher group_dispatcher (
	.clock(clock),
	.resetn(resetn),
	.start(start_NO_SHIFT_REG),
	.num_groups(num_groups_NO_SHIFT_REG),
	.local_size(local_size_NO_SHIFT_REG),
	.stall_in(iter_stall_out),
	.valid_out(iter_valid_in),
	.group_id_out(group_id_tmp),
	.global_id_base_out(global_id_base_out),
	.start_out(start_out),
	.dispatched_all_groups(dispatched_all_groups)
);

defparam group_dispatcher.NUM_COPIES = 1;
defparam group_dispatcher.RUN_FOREVER = 0;


// This section of the wrapper implements an Avalon Slave Interface used to configure a kernel invocation.
// The few words words contain the status and the workgroup size registers.
// The remaining addressable space is reserved for kernel arguments.
 reg [63:0] cra_readdata_st1_NO_SHIFT_REG;
 reg [3:0] cra_addr_st1_NO_SHIFT_REG;
 reg cra_read_st1_NO_SHIFT_REG;
wire [63:0] bitenable;

assign bitenable[7:0] = (avs_cra_byteenable[0] ? 8'hFF : 8'h0);
assign bitenable[15:8] = (avs_cra_byteenable[1] ? 8'hFF : 8'h0);
assign bitenable[23:16] = (avs_cra_byteenable[2] ? 8'hFF : 8'h0);
assign bitenable[31:24] = (avs_cra_byteenable[3] ? 8'hFF : 8'h0);
assign bitenable[39:32] = (avs_cra_byteenable[4] ? 8'hFF : 8'h0);
assign bitenable[47:40] = (avs_cra_byteenable[5] ? 8'hFF : 8'h0);
assign bitenable[55:48] = (avs_cra_byteenable[6] ? 8'hFF : 8'h0);
assign bitenable[63:56] = (avs_cra_byteenable[7] ? 8'hFF : 8'h0);
assign cra_irq = (status_NO_SHIFT_REG[1] | status_NO_SHIFT_REG[3]);

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		start_NO_SHIFT_REG <= 1'b0;
		started_NO_SHIFT_REG <= 1'b0;
		kernel_arguments_NO_SHIFT_REG <= 192'h0;
		status_NO_SHIFT_REG <= 32'h30000;
		profile_ctrl_NO_SHIFT_REG <= 32'h4;
		profile_start_cycle_NO_SHIFT_REG <= 64'h0;
		profile_stop_cycle_NO_SHIFT_REG <= 64'hFFFFFFFFFFFFFFFF;
		work_dim_NO_SHIFT_REG <= 32'h0;
		workgroup_size_NO_SHIFT_REG <= 32'h0;
		global_size_NO_SHIFT_REG[0] <= 32'h0;
		global_size_NO_SHIFT_REG[1] <= 32'h0;
		global_size_NO_SHIFT_REG[2] <= 32'h0;
		num_groups_NO_SHIFT_REG[0] <= 32'h0;
		num_groups_NO_SHIFT_REG[1] <= 32'h0;
		num_groups_NO_SHIFT_REG[2] <= 32'h0;
		local_size_NO_SHIFT_REG[0] <= 32'h0;
		local_size_NO_SHIFT_REG[1] <= 32'h0;
		local_size_NO_SHIFT_REG[2] <= 32'h0;
		global_offset_NO_SHIFT_REG[0] <= 32'h0;
		global_offset_NO_SHIFT_REG[1] <= 32'h0;
		global_offset_NO_SHIFT_REG[2] <= 32'h0;
	end
	else
	begin
		if (avs_cra_write)
		begin
			case (avs_cra_address)
				4'h0:
				begin
					status_NO_SHIFT_REG[31:16] <= 16'h3;
					status_NO_SHIFT_REG[15:0] <= ((status_NO_SHIFT_REG[15:0] & ~(bitenable[15:0])) | (avs_cra_writedata[15:0] & bitenable[15:0]));
				end

				4'h1:
				begin
					profile_ctrl_NO_SHIFT_REG <= ((profile_ctrl_NO_SHIFT_REG & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h3:
				begin
					profile_start_cycle_NO_SHIFT_REG[31:0] <= ((profile_start_cycle_NO_SHIFT_REG[31:0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					profile_start_cycle_NO_SHIFT_REG[63:32] <= ((profile_start_cycle_NO_SHIFT_REG[63:32] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h4:
				begin
					profile_stop_cycle_NO_SHIFT_REG[31:0] <= ((profile_stop_cycle_NO_SHIFT_REG[31:0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					profile_stop_cycle_NO_SHIFT_REG[63:32] <= ((profile_stop_cycle_NO_SHIFT_REG[63:32] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h5:
				begin
					work_dim_NO_SHIFT_REG <= ((work_dim_NO_SHIFT_REG & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					workgroup_size_NO_SHIFT_REG <= ((workgroup_size_NO_SHIFT_REG & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h6:
				begin
					global_size_NO_SHIFT_REG[0] <= ((global_size_NO_SHIFT_REG[0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					global_size_NO_SHIFT_REG[1] <= ((global_size_NO_SHIFT_REG[1] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h7:
				begin
					global_size_NO_SHIFT_REG[2] <= ((global_size_NO_SHIFT_REG[2] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					num_groups_NO_SHIFT_REG[0] <= ((num_groups_NO_SHIFT_REG[0] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h8:
				begin
					num_groups_NO_SHIFT_REG[1] <= ((num_groups_NO_SHIFT_REG[1] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					num_groups_NO_SHIFT_REG[2] <= ((num_groups_NO_SHIFT_REG[2] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'h9:
				begin
					local_size_NO_SHIFT_REG[0] <= ((local_size_NO_SHIFT_REG[0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					local_size_NO_SHIFT_REG[1] <= ((local_size_NO_SHIFT_REG[1] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'hA:
				begin
					local_size_NO_SHIFT_REG[2] <= ((local_size_NO_SHIFT_REG[2] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					global_offset_NO_SHIFT_REG[0] <= ((global_offset_NO_SHIFT_REG[0] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'hB:
				begin
					global_offset_NO_SHIFT_REG[1] <= ((global_offset_NO_SHIFT_REG[1] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					global_offset_NO_SHIFT_REG[2] <= ((global_offset_NO_SHIFT_REG[2] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'hC:
				begin
					kernel_arguments_NO_SHIFT_REG[31:0] <= ((kernel_arguments_NO_SHIFT_REG[31:0] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					kernel_arguments_NO_SHIFT_REG[63:32] <= ((kernel_arguments_NO_SHIFT_REG[63:32] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'hD:
				begin
					kernel_arguments_NO_SHIFT_REG[95:64] <= ((kernel_arguments_NO_SHIFT_REG[95:64] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					kernel_arguments_NO_SHIFT_REG[127:96] <= ((kernel_arguments_NO_SHIFT_REG[127:96] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				4'hE:
				begin
					kernel_arguments_NO_SHIFT_REG[159:128] <= ((kernel_arguments_NO_SHIFT_REG[159:128] & ~(bitenable[31:0])) | (avs_cra_writedata[31:0] & bitenable[31:0]));
					kernel_arguments_NO_SHIFT_REG[191:160] <= ((kernel_arguments_NO_SHIFT_REG[191:160] & ~(bitenable[63:32])) | (avs_cra_writedata[63:32] & bitenable[63:32]));
				end

				default:
				begin
				end

			endcase
		end
		else
		begin
			if (status_NO_SHIFT_REG[0])
			begin
				start_NO_SHIFT_REG <= 1'b1;
			end
			if (start_NO_SHIFT_REG)
			begin
				status_NO_SHIFT_REG[0] <= 1'b0;
				started_NO_SHIFT_REG <= 1'b1;
			end
			if (started_NO_SHIFT_REG)
			begin
				start_NO_SHIFT_REG <= 1'b0;
			end
			if (finish)
			begin
				status_NO_SHIFT_REG[1] <= 1'b1;
				started_NO_SHIFT_REG <= 1'b0;
			end
		end
		status_NO_SHIFT_REG[11] <= 1'b0;
		status_NO_SHIFT_REG[12] <= (|has_a_lsu_active);
		status_NO_SHIFT_REG[13] <= (|has_a_write_pending);
		status_NO_SHIFT_REG[14] <= (|valid_in);
		status_NO_SHIFT_REG[15] <= started_NO_SHIFT_REG;
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		cra_read_st1_NO_SHIFT_REG <= 1'b0;
		cra_addr_st1_NO_SHIFT_REG <= 4'h0;
		cra_readdata_st1_NO_SHIFT_REG <= 64'h0;
	end
	else
	begin
		cra_read_st1_NO_SHIFT_REG <= avs_cra_read;
		cra_addr_st1_NO_SHIFT_REG <= avs_cra_address;
		case (avs_cra_address)
			4'h0:
			begin
				cra_readdata_st1_NO_SHIFT_REG[31:0] <= status_NO_SHIFT_REG;
				cra_readdata_st1_NO_SHIFT_REG[63:32] <= 32'h0;
			end

			4'h1:
			begin
				cra_readdata_st1_NO_SHIFT_REG[31:0] <= 'x;
				cra_readdata_st1_NO_SHIFT_REG[63:32] <= 32'h0;
			end

			4'h2:
			begin
				cra_readdata_st1_NO_SHIFT_REG[63:0] <= 64'h0;
			end

			4'h3:
			begin
				cra_readdata_st1_NO_SHIFT_REG[63:0] <= 64'h0;
			end

			4'h4:
			begin
				cra_readdata_st1_NO_SHIFT_REG[63:0] <= 64'h0;
			end

			default:
			begin
				cra_readdata_st1_NO_SHIFT_REG <= status_NO_SHIFT_REG;
			end

		endcase
	end
end

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		avs_cra_readdatavalid <= 1'b0;
		avs_cra_readdata <= 64'h0;
	end
	else
	begin
		avs_cra_readdatavalid <= cra_read_st1_NO_SHIFT_REG;
		case (cra_addr_st1_NO_SHIFT_REG)
			4'h2:
			begin
				avs_cra_readdata[63:0] <= profile_data_NO_SHIFT_REG;
			end

			default:
			begin
				avs_cra_readdata <= cra_readdata_st1_NO_SHIFT_REG;
			end

		endcase
	end
end


// Handshaking signals used to control data through the pipeline

// Determine when the kernel is finished.
acl_kernel_finish_detector kernel_finish_detector (
	.clock(clock),
	.resetn(resetn),
	.start(start_NO_SHIFT_REG),
	.wg_size(workgroup_size_NO_SHIFT_REG),
	.wg_dispatch_valid_out(iter_valid_in),
	.wg_dispatch_stall_in(iter_stall_out),
	.dispatched_all_groups(dispatched_all_groups),
	.kernel_copy_valid_out(valid_out),
	.kernel_copy_stall_in(stall_in),
	.pending_writes(has_a_write_pending),
	.finish(finish)
);

defparam kernel_finish_detector.TESSELLATION_SIZE = 0;
defparam kernel_finish_detector.NUM_COPIES = 1;
defparam kernel_finish_detector.WG_SIZE_W = 32;

assign stall_in = 1'b0;

// Creating ID iterator and kernel instance for every requested kernel copy

// ID iterator is responsible for iterating over all local ids for given work-groups
acl_id_iterator id_iter_inst0 (
	.clock(clock),
	.resetn(resetn),
	.start(start_out),
	.valid_in(iter_valid_in),
	.stall_out(iter_stall_out),
	.stall_in(stall_out),
	.valid_out(valid_in),
	.group_id_in(group_id_tmp),
	.global_id_base_in(global_id_base_out),
	.local_size(local_size_NO_SHIFT_REG),
	.global_size(global_size_NO_SHIFT_REG),
	.local_id(local_id[0]),
	.global_id(global_id[0]),
	.group_id(group_id[0])
);

defparam id_iter_inst0.LOCAL_WIDTH_X = 32;
defparam id_iter_inst0.LOCAL_WIDTH_Y = 32;
defparam id_iter_inst0.LOCAL_WIDTH_Z = 32;


// This section instantiates a kernel function block
float_add_function float_add_function_inst0 (
	.clock(clock),
	.resetn(resetn),
	.input_global_id_0(global_id[0][0]),
	.stall_out(stall_out),
	.valid_in(valid_in),
	.valid_out(valid_out),
	.stall_in(stall_in),
	.workgroup_size(workgroup_size_NO_SHIFT_REG),
	.avm_local_bb1_ld__enable(avm_local_bb1_ld__inst0_enable),
	.avm_local_bb1_ld__readdata(avm_local_bb1_ld__inst0_readdata),
	.avm_local_bb1_ld__readdatavalid(avm_local_bb1_ld__inst0_readdatavalid),
	.avm_local_bb1_ld__waitrequest(avm_local_bb1_ld__inst0_waitrequest),
	.avm_local_bb1_ld__address(avm_local_bb1_ld__inst0_address),
	.avm_local_bb1_ld__read(avm_local_bb1_ld__inst0_read),
	.avm_local_bb1_ld__write(avm_local_bb1_ld__inst0_write),
	.avm_local_bb1_ld__writeack(avm_local_bb1_ld__inst0_writeack),
	.avm_local_bb1_ld__writedata(avm_local_bb1_ld__inst0_writedata),
	.avm_local_bb1_ld__byteenable(avm_local_bb1_ld__inst0_byteenable),
	.avm_local_bb1_ld__burstcount(avm_local_bb1_ld__inst0_burstcount),
	.avm_local_bb1_ld__u0_enable(avm_local_bb1_ld__u0_inst0_enable),
	.avm_local_bb1_ld__u0_readdata(avm_local_bb1_ld__u0_inst0_readdata),
	.avm_local_bb1_ld__u0_readdatavalid(avm_local_bb1_ld__u0_inst0_readdatavalid),
	.avm_local_bb1_ld__u0_waitrequest(avm_local_bb1_ld__u0_inst0_waitrequest),
	.avm_local_bb1_ld__u0_address(avm_local_bb1_ld__u0_inst0_address),
	.avm_local_bb1_ld__u0_read(avm_local_bb1_ld__u0_inst0_read),
	.avm_local_bb1_ld__u0_write(avm_local_bb1_ld__u0_inst0_write),
	.avm_local_bb1_ld__u0_writeack(avm_local_bb1_ld__u0_inst0_writeack),
	.avm_local_bb1_ld__u0_writedata(avm_local_bb1_ld__u0_inst0_writedata),
	.avm_local_bb1_ld__u0_byteenable(avm_local_bb1_ld__u0_inst0_byteenable),
	.avm_local_bb1_ld__u0_burstcount(avm_local_bb1_ld__u0_inst0_burstcount),
	.avm_local_bb1_st_c0_exe1_enable(avm_local_bb1_st_c0_exe1_inst0_enable),
	.avm_local_bb1_st_c0_exe1_readdata(avm_local_bb1_st_c0_exe1_inst0_readdata),
	.avm_local_bb1_st_c0_exe1_readdatavalid(avm_local_bb1_st_c0_exe1_inst0_readdatavalid),
	.avm_local_bb1_st_c0_exe1_waitrequest(avm_local_bb1_st_c0_exe1_inst0_waitrequest),
	.avm_local_bb1_st_c0_exe1_address(avm_local_bb1_st_c0_exe1_inst0_address),
	.avm_local_bb1_st_c0_exe1_read(avm_local_bb1_st_c0_exe1_inst0_read),
	.avm_local_bb1_st_c0_exe1_write(avm_local_bb1_st_c0_exe1_inst0_write),
	.avm_local_bb1_st_c0_exe1_writeack(avm_local_bb1_st_c0_exe1_inst0_writeack),
	.avm_local_bb1_st_c0_exe1_writedata(avm_local_bb1_st_c0_exe1_inst0_writedata),
	.avm_local_bb1_st_c0_exe1_byteenable(avm_local_bb1_st_c0_exe1_inst0_byteenable),
	.avm_local_bb1_st_c0_exe1_burstcount(avm_local_bb1_st_c0_exe1_inst0_burstcount),
	.start(start_out),
	.clock2x(clock2x),
	.input_x(kernel_arguments_NO_SHIFT_REG[63:0]),
	.input_y(kernel_arguments_NO_SHIFT_REG[127:64]),
	.input_z(kernel_arguments_NO_SHIFT_REG[191:128]),
	.has_a_write_pending(has_a_write_pending),
	.has_a_lsu_active(has_a_lsu_active)
);



endmodule

//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////

// altera message_off 10036
// altera message_off 10230
// altera message_off 10858
module float_add_sys_cycle_time
	(
		input 		clock,
		input 		resetn,
		output [31:0] 		cur_cycle
	);


 reg [31:0] cur_count_NO_SHIFT_REG;

assign cur_cycle = cur_count_NO_SHIFT_REG;

always @(posedge clock or negedge resetn)
begin
	if (~(resetn))
	begin
		cur_count_NO_SHIFT_REG <= 32'h0;
	end
	else
	begin
		cur_count_NO_SHIFT_REG <= (cur_count_NO_SHIFT_REG + 32'h1);
	end
end

endmodule

