// system_mm_interconnect_5.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 15.1 193

`timescale 1 ps / 1 ps
module system_mm_interconnect_5 (
		input  wire        acl_iface_prime_clk_clk,                                          //                                        acl_iface_prime_clk.clk
		input  wire        ext_clk_50_clk_clk,                                               //                                             ext_clk_50_clk.clk
		input  wire        acl_iface_global_reset_reset_bridge_in_reset_reset,               //               acl_iface_global_reset_reset_bridge_in_reset.reset
		input  wire        acl_iface_prime_bus_translator_reset_reset_bridge_in_reset_reset, // acl_iface_prime_bus_translator_reset_reset_bridge_in_reset.reset
		input  wire        float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset,           //           float_mult_smack_ctrl_rstn_reset_bridge_in_reset.reset
		input  wire [5:0]  acl_iface_prime_bus_address,                                      //                                        acl_iface_prime_bus.address
		output wire        acl_iface_prime_bus_waitrequest,                                  //                                                           .waitrequest
		input  wire [0:0]  acl_iface_prime_bus_burstcount,                                   //                                                           .burstcount
		input  wire [3:0]  acl_iface_prime_bus_byteenable,                                   //                                                           .byteenable
		input  wire        acl_iface_prime_bus_read,                                         //                                                           .read
		output wire [31:0] acl_iface_prime_bus_readdata,                                     //                                                           .readdata
		output wire        acl_iface_prime_bus_readdatavalid,                                //                                                           .readdatavalid
		input  wire        acl_iface_prime_bus_write,                                        //                                                           .write
		input  wire [31:0] acl_iface_prime_bus_writedata,                                    //                                                           .writedata
		input  wire        acl_iface_prime_bus_debugaccess,                                  //                                                           .debugaccess
		output wire [2:0]  float_add_smack_ctrl_bus_address,                                 //                                   float_add_smack_ctrl_bus.address
		output wire        float_add_smack_ctrl_bus_write,                                   //                                                           .write
		output wire        float_add_smack_ctrl_bus_read,                                    //                                                           .read
		input  wire [31:0] float_add_smack_ctrl_bus_readdata,                                //                                                           .readdata
		output wire [31:0] float_add_smack_ctrl_bus_writedata,                               //                                                           .writedata
		input  wire        float_add_smack_ctrl_bus_waitrequest,                             //                                                           .waitrequest
		output wire [2:0]  float_mult_smack_ctrl_bus_address,                                //                                  float_mult_smack_ctrl_bus.address
		output wire        float_mult_smack_ctrl_bus_write,                                  //                                                           .write
		output wire        float_mult_smack_ctrl_bus_read,                                   //                                                           .read
		input  wire [31:0] float_mult_smack_ctrl_bus_readdata,                               //                                                           .readdata
		output wire [31:0] float_mult_smack_ctrl_bus_writedata,                              //                                                           .writedata
		input  wire        float_mult_smack_ctrl_bus_waitrequest                             //                                                           .waitrequest
	);

	wire         acl_iface_prime_bus_translator_avalon_universal_master_0_waitrequest;   // acl_iface_prime_bus_agent:av_waitrequest -> acl_iface_prime_bus_translator:uav_waitrequest
	wire  [31:0] acl_iface_prime_bus_translator_avalon_universal_master_0_readdata;      // acl_iface_prime_bus_agent:av_readdata -> acl_iface_prime_bus_translator:uav_readdata
	wire         acl_iface_prime_bus_translator_avalon_universal_master_0_debugaccess;   // acl_iface_prime_bus_translator:uav_debugaccess -> acl_iface_prime_bus_agent:av_debugaccess
	wire   [5:0] acl_iface_prime_bus_translator_avalon_universal_master_0_address;       // acl_iface_prime_bus_translator:uav_address -> acl_iface_prime_bus_agent:av_address
	wire         acl_iface_prime_bus_translator_avalon_universal_master_0_read;          // acl_iface_prime_bus_translator:uav_read -> acl_iface_prime_bus_agent:av_read
	wire   [3:0] acl_iface_prime_bus_translator_avalon_universal_master_0_byteenable;    // acl_iface_prime_bus_translator:uav_byteenable -> acl_iface_prime_bus_agent:av_byteenable
	wire         acl_iface_prime_bus_translator_avalon_universal_master_0_readdatavalid; // acl_iface_prime_bus_agent:av_readdatavalid -> acl_iface_prime_bus_translator:uav_readdatavalid
	wire         acl_iface_prime_bus_translator_avalon_universal_master_0_lock;          // acl_iface_prime_bus_translator:uav_lock -> acl_iface_prime_bus_agent:av_lock
	wire         acl_iface_prime_bus_translator_avalon_universal_master_0_write;         // acl_iface_prime_bus_translator:uav_write -> acl_iface_prime_bus_agent:av_write
	wire  [31:0] acl_iface_prime_bus_translator_avalon_universal_master_0_writedata;     // acl_iface_prime_bus_translator:uav_writedata -> acl_iface_prime_bus_agent:av_writedata
	wire   [2:0] acl_iface_prime_bus_translator_avalon_universal_master_0_burstcount;    // acl_iface_prime_bus_translator:uav_burstcount -> acl_iface_prime_bus_agent:av_burstcount
	wire  [31:0] float_mult_smack_ctrl_bus_agent_m0_readdata;                            // float_mult_smack_ctrl_bus_translator:uav_readdata -> float_mult_smack_ctrl_bus_agent:m0_readdata
	wire         float_mult_smack_ctrl_bus_agent_m0_waitrequest;                         // float_mult_smack_ctrl_bus_translator:uav_waitrequest -> float_mult_smack_ctrl_bus_agent:m0_waitrequest
	wire         float_mult_smack_ctrl_bus_agent_m0_debugaccess;                         // float_mult_smack_ctrl_bus_agent:m0_debugaccess -> float_mult_smack_ctrl_bus_translator:uav_debugaccess
	wire   [5:0] float_mult_smack_ctrl_bus_agent_m0_address;                             // float_mult_smack_ctrl_bus_agent:m0_address -> float_mult_smack_ctrl_bus_translator:uav_address
	wire   [3:0] float_mult_smack_ctrl_bus_agent_m0_byteenable;                          // float_mult_smack_ctrl_bus_agent:m0_byteenable -> float_mult_smack_ctrl_bus_translator:uav_byteenable
	wire         float_mult_smack_ctrl_bus_agent_m0_read;                                // float_mult_smack_ctrl_bus_agent:m0_read -> float_mult_smack_ctrl_bus_translator:uav_read
	wire         float_mult_smack_ctrl_bus_agent_m0_readdatavalid;                       // float_mult_smack_ctrl_bus_translator:uav_readdatavalid -> float_mult_smack_ctrl_bus_agent:m0_readdatavalid
	wire         float_mult_smack_ctrl_bus_agent_m0_lock;                                // float_mult_smack_ctrl_bus_agent:m0_lock -> float_mult_smack_ctrl_bus_translator:uav_lock
	wire  [31:0] float_mult_smack_ctrl_bus_agent_m0_writedata;                           // float_mult_smack_ctrl_bus_agent:m0_writedata -> float_mult_smack_ctrl_bus_translator:uav_writedata
	wire         float_mult_smack_ctrl_bus_agent_m0_write;                               // float_mult_smack_ctrl_bus_agent:m0_write -> float_mult_smack_ctrl_bus_translator:uav_write
	wire   [2:0] float_mult_smack_ctrl_bus_agent_m0_burstcount;                          // float_mult_smack_ctrl_bus_agent:m0_burstcount -> float_mult_smack_ctrl_bus_translator:uav_burstcount
	wire         float_mult_smack_ctrl_bus_agent_rf_source_valid;                        // float_mult_smack_ctrl_bus_agent:rf_source_valid -> float_mult_smack_ctrl_bus_agent_rsp_fifo:in_valid
	wire  [76:0] float_mult_smack_ctrl_bus_agent_rf_source_data;                         // float_mult_smack_ctrl_bus_agent:rf_source_data -> float_mult_smack_ctrl_bus_agent_rsp_fifo:in_data
	wire         float_mult_smack_ctrl_bus_agent_rf_source_ready;                        // float_mult_smack_ctrl_bus_agent_rsp_fifo:in_ready -> float_mult_smack_ctrl_bus_agent:rf_source_ready
	wire         float_mult_smack_ctrl_bus_agent_rf_source_startofpacket;                // float_mult_smack_ctrl_bus_agent:rf_source_startofpacket -> float_mult_smack_ctrl_bus_agent_rsp_fifo:in_startofpacket
	wire         float_mult_smack_ctrl_bus_agent_rf_source_endofpacket;                  // float_mult_smack_ctrl_bus_agent:rf_source_endofpacket -> float_mult_smack_ctrl_bus_agent_rsp_fifo:in_endofpacket
	wire         float_mult_smack_ctrl_bus_agent_rsp_fifo_out_valid;                     // float_mult_smack_ctrl_bus_agent_rsp_fifo:out_valid -> float_mult_smack_ctrl_bus_agent:rf_sink_valid
	wire  [76:0] float_mult_smack_ctrl_bus_agent_rsp_fifo_out_data;                      // float_mult_smack_ctrl_bus_agent_rsp_fifo:out_data -> float_mult_smack_ctrl_bus_agent:rf_sink_data
	wire         float_mult_smack_ctrl_bus_agent_rsp_fifo_out_ready;                     // float_mult_smack_ctrl_bus_agent:rf_sink_ready -> float_mult_smack_ctrl_bus_agent_rsp_fifo:out_ready
	wire         float_mult_smack_ctrl_bus_agent_rsp_fifo_out_startofpacket;             // float_mult_smack_ctrl_bus_agent_rsp_fifo:out_startofpacket -> float_mult_smack_ctrl_bus_agent:rf_sink_startofpacket
	wire         float_mult_smack_ctrl_bus_agent_rsp_fifo_out_endofpacket;               // float_mult_smack_ctrl_bus_agent_rsp_fifo:out_endofpacket -> float_mult_smack_ctrl_bus_agent:rf_sink_endofpacket
	wire         float_mult_smack_ctrl_bus_agent_rdata_fifo_src_valid;                   // float_mult_smack_ctrl_bus_agent:rdata_fifo_src_valid -> float_mult_smack_ctrl_bus_agent_rdata_fifo:in_valid
	wire  [33:0] float_mult_smack_ctrl_bus_agent_rdata_fifo_src_data;                    // float_mult_smack_ctrl_bus_agent:rdata_fifo_src_data -> float_mult_smack_ctrl_bus_agent_rdata_fifo:in_data
	wire         float_mult_smack_ctrl_bus_agent_rdata_fifo_src_ready;                   // float_mult_smack_ctrl_bus_agent_rdata_fifo:in_ready -> float_mult_smack_ctrl_bus_agent:rdata_fifo_src_ready
	wire         cmd_mux_src_valid;                                                      // cmd_mux:src_valid -> float_mult_smack_ctrl_bus_agent:cp_valid
	wire  [75:0] cmd_mux_src_data;                                                       // cmd_mux:src_data -> float_mult_smack_ctrl_bus_agent:cp_data
	wire         cmd_mux_src_ready;                                                      // float_mult_smack_ctrl_bus_agent:cp_ready -> cmd_mux:src_ready
	wire   [1:0] cmd_mux_src_channel;                                                    // cmd_mux:src_channel -> float_mult_smack_ctrl_bus_agent:cp_channel
	wire         cmd_mux_src_startofpacket;                                              // cmd_mux:src_startofpacket -> float_mult_smack_ctrl_bus_agent:cp_startofpacket
	wire         cmd_mux_src_endofpacket;                                                // cmd_mux:src_endofpacket -> float_mult_smack_ctrl_bus_agent:cp_endofpacket
	wire  [31:0] float_add_smack_ctrl_bus_agent_m0_readdata;                             // float_add_smack_ctrl_bus_translator:uav_readdata -> float_add_smack_ctrl_bus_agent:m0_readdata
	wire         float_add_smack_ctrl_bus_agent_m0_waitrequest;                          // float_add_smack_ctrl_bus_translator:uav_waitrequest -> float_add_smack_ctrl_bus_agent:m0_waitrequest
	wire         float_add_smack_ctrl_bus_agent_m0_debugaccess;                          // float_add_smack_ctrl_bus_agent:m0_debugaccess -> float_add_smack_ctrl_bus_translator:uav_debugaccess
	wire   [5:0] float_add_smack_ctrl_bus_agent_m0_address;                              // float_add_smack_ctrl_bus_agent:m0_address -> float_add_smack_ctrl_bus_translator:uav_address
	wire   [3:0] float_add_smack_ctrl_bus_agent_m0_byteenable;                           // float_add_smack_ctrl_bus_agent:m0_byteenable -> float_add_smack_ctrl_bus_translator:uav_byteenable
	wire         float_add_smack_ctrl_bus_agent_m0_read;                                 // float_add_smack_ctrl_bus_agent:m0_read -> float_add_smack_ctrl_bus_translator:uav_read
	wire         float_add_smack_ctrl_bus_agent_m0_readdatavalid;                        // float_add_smack_ctrl_bus_translator:uav_readdatavalid -> float_add_smack_ctrl_bus_agent:m0_readdatavalid
	wire         float_add_smack_ctrl_bus_agent_m0_lock;                                 // float_add_smack_ctrl_bus_agent:m0_lock -> float_add_smack_ctrl_bus_translator:uav_lock
	wire  [31:0] float_add_smack_ctrl_bus_agent_m0_writedata;                            // float_add_smack_ctrl_bus_agent:m0_writedata -> float_add_smack_ctrl_bus_translator:uav_writedata
	wire         float_add_smack_ctrl_bus_agent_m0_write;                                // float_add_smack_ctrl_bus_agent:m0_write -> float_add_smack_ctrl_bus_translator:uav_write
	wire   [2:0] float_add_smack_ctrl_bus_agent_m0_burstcount;                           // float_add_smack_ctrl_bus_agent:m0_burstcount -> float_add_smack_ctrl_bus_translator:uav_burstcount
	wire         float_add_smack_ctrl_bus_agent_rf_source_valid;                         // float_add_smack_ctrl_bus_agent:rf_source_valid -> float_add_smack_ctrl_bus_agent_rsp_fifo:in_valid
	wire  [76:0] float_add_smack_ctrl_bus_agent_rf_source_data;                          // float_add_smack_ctrl_bus_agent:rf_source_data -> float_add_smack_ctrl_bus_agent_rsp_fifo:in_data
	wire         float_add_smack_ctrl_bus_agent_rf_source_ready;                         // float_add_smack_ctrl_bus_agent_rsp_fifo:in_ready -> float_add_smack_ctrl_bus_agent:rf_source_ready
	wire         float_add_smack_ctrl_bus_agent_rf_source_startofpacket;                 // float_add_smack_ctrl_bus_agent:rf_source_startofpacket -> float_add_smack_ctrl_bus_agent_rsp_fifo:in_startofpacket
	wire         float_add_smack_ctrl_bus_agent_rf_source_endofpacket;                   // float_add_smack_ctrl_bus_agent:rf_source_endofpacket -> float_add_smack_ctrl_bus_agent_rsp_fifo:in_endofpacket
	wire         float_add_smack_ctrl_bus_agent_rsp_fifo_out_valid;                      // float_add_smack_ctrl_bus_agent_rsp_fifo:out_valid -> float_add_smack_ctrl_bus_agent:rf_sink_valid
	wire  [76:0] float_add_smack_ctrl_bus_agent_rsp_fifo_out_data;                       // float_add_smack_ctrl_bus_agent_rsp_fifo:out_data -> float_add_smack_ctrl_bus_agent:rf_sink_data
	wire         float_add_smack_ctrl_bus_agent_rsp_fifo_out_ready;                      // float_add_smack_ctrl_bus_agent:rf_sink_ready -> float_add_smack_ctrl_bus_agent_rsp_fifo:out_ready
	wire         float_add_smack_ctrl_bus_agent_rsp_fifo_out_startofpacket;              // float_add_smack_ctrl_bus_agent_rsp_fifo:out_startofpacket -> float_add_smack_ctrl_bus_agent:rf_sink_startofpacket
	wire         float_add_smack_ctrl_bus_agent_rsp_fifo_out_endofpacket;                // float_add_smack_ctrl_bus_agent_rsp_fifo:out_endofpacket -> float_add_smack_ctrl_bus_agent:rf_sink_endofpacket
	wire         float_add_smack_ctrl_bus_agent_rdata_fifo_src_valid;                    // float_add_smack_ctrl_bus_agent:rdata_fifo_src_valid -> float_add_smack_ctrl_bus_agent_rdata_fifo:in_valid
	wire  [33:0] float_add_smack_ctrl_bus_agent_rdata_fifo_src_data;                     // float_add_smack_ctrl_bus_agent:rdata_fifo_src_data -> float_add_smack_ctrl_bus_agent_rdata_fifo:in_data
	wire         float_add_smack_ctrl_bus_agent_rdata_fifo_src_ready;                    // float_add_smack_ctrl_bus_agent_rdata_fifo:in_ready -> float_add_smack_ctrl_bus_agent:rdata_fifo_src_ready
	wire         cmd_mux_001_src_valid;                                                  // cmd_mux_001:src_valid -> float_add_smack_ctrl_bus_agent:cp_valid
	wire  [75:0] cmd_mux_001_src_data;                                                   // cmd_mux_001:src_data -> float_add_smack_ctrl_bus_agent:cp_data
	wire         cmd_mux_001_src_ready;                                                  // float_add_smack_ctrl_bus_agent:cp_ready -> cmd_mux_001:src_ready
	wire   [1:0] cmd_mux_001_src_channel;                                                // cmd_mux_001:src_channel -> float_add_smack_ctrl_bus_agent:cp_channel
	wire         cmd_mux_001_src_startofpacket;                                          // cmd_mux_001:src_startofpacket -> float_add_smack_ctrl_bus_agent:cp_startofpacket
	wire         cmd_mux_001_src_endofpacket;                                            // cmd_mux_001:src_endofpacket -> float_add_smack_ctrl_bus_agent:cp_endofpacket
	wire         acl_iface_prime_bus_agent_cp_valid;                                     // acl_iface_prime_bus_agent:cp_valid -> router:sink_valid
	wire  [75:0] acl_iface_prime_bus_agent_cp_data;                                      // acl_iface_prime_bus_agent:cp_data -> router:sink_data
	wire         acl_iface_prime_bus_agent_cp_ready;                                     // router:sink_ready -> acl_iface_prime_bus_agent:cp_ready
	wire         acl_iface_prime_bus_agent_cp_startofpacket;                             // acl_iface_prime_bus_agent:cp_startofpacket -> router:sink_startofpacket
	wire         acl_iface_prime_bus_agent_cp_endofpacket;                               // acl_iface_prime_bus_agent:cp_endofpacket -> router:sink_endofpacket
	wire         float_mult_smack_ctrl_bus_agent_rp_valid;                               // float_mult_smack_ctrl_bus_agent:rp_valid -> router_001:sink_valid
	wire  [75:0] float_mult_smack_ctrl_bus_agent_rp_data;                                // float_mult_smack_ctrl_bus_agent:rp_data -> router_001:sink_data
	wire         float_mult_smack_ctrl_bus_agent_rp_ready;                               // router_001:sink_ready -> float_mult_smack_ctrl_bus_agent:rp_ready
	wire         float_mult_smack_ctrl_bus_agent_rp_startofpacket;                       // float_mult_smack_ctrl_bus_agent:rp_startofpacket -> router_001:sink_startofpacket
	wire         float_mult_smack_ctrl_bus_agent_rp_endofpacket;                         // float_mult_smack_ctrl_bus_agent:rp_endofpacket -> router_001:sink_endofpacket
	wire         router_001_src_valid;                                                   // router_001:src_valid -> rsp_demux:sink_valid
	wire  [75:0] router_001_src_data;                                                    // router_001:src_data -> rsp_demux:sink_data
	wire         router_001_src_ready;                                                   // rsp_demux:sink_ready -> router_001:src_ready
	wire   [1:0] router_001_src_channel;                                                 // router_001:src_channel -> rsp_demux:sink_channel
	wire         router_001_src_startofpacket;                                           // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
	wire         router_001_src_endofpacket;                                             // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
	wire         float_add_smack_ctrl_bus_agent_rp_valid;                                // float_add_smack_ctrl_bus_agent:rp_valid -> router_002:sink_valid
	wire  [75:0] float_add_smack_ctrl_bus_agent_rp_data;                                 // float_add_smack_ctrl_bus_agent:rp_data -> router_002:sink_data
	wire         float_add_smack_ctrl_bus_agent_rp_ready;                                // router_002:sink_ready -> float_add_smack_ctrl_bus_agent:rp_ready
	wire         float_add_smack_ctrl_bus_agent_rp_startofpacket;                        // float_add_smack_ctrl_bus_agent:rp_startofpacket -> router_002:sink_startofpacket
	wire         float_add_smack_ctrl_bus_agent_rp_endofpacket;                          // float_add_smack_ctrl_bus_agent:rp_endofpacket -> router_002:sink_endofpacket
	wire         router_002_src_valid;                                                   // router_002:src_valid -> rsp_demux_001:sink_valid
	wire  [75:0] router_002_src_data;                                                    // router_002:src_data -> rsp_demux_001:sink_data
	wire         router_002_src_ready;                                                   // rsp_demux_001:sink_ready -> router_002:src_ready
	wire   [1:0] router_002_src_channel;                                                 // router_002:src_channel -> rsp_demux_001:sink_channel
	wire         router_002_src_startofpacket;                                           // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire         router_002_src_endofpacket;                                             // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire         router_src_valid;                                                       // router:src_valid -> acl_iface_prime_bus_limiter:cmd_sink_valid
	wire  [75:0] router_src_data;                                                        // router:src_data -> acl_iface_prime_bus_limiter:cmd_sink_data
	wire         router_src_ready;                                                       // acl_iface_prime_bus_limiter:cmd_sink_ready -> router:src_ready
	wire   [1:0] router_src_channel;                                                     // router:src_channel -> acl_iface_prime_bus_limiter:cmd_sink_channel
	wire         router_src_startofpacket;                                               // router:src_startofpacket -> acl_iface_prime_bus_limiter:cmd_sink_startofpacket
	wire         router_src_endofpacket;                                                 // router:src_endofpacket -> acl_iface_prime_bus_limiter:cmd_sink_endofpacket
	wire  [75:0] acl_iface_prime_bus_limiter_cmd_src_data;                               // acl_iface_prime_bus_limiter:cmd_src_data -> cmd_demux:sink_data
	wire         acl_iface_prime_bus_limiter_cmd_src_ready;                              // cmd_demux:sink_ready -> acl_iface_prime_bus_limiter:cmd_src_ready
	wire   [1:0] acl_iface_prime_bus_limiter_cmd_src_channel;                            // acl_iface_prime_bus_limiter:cmd_src_channel -> cmd_demux:sink_channel
	wire         acl_iface_prime_bus_limiter_cmd_src_startofpacket;                      // acl_iface_prime_bus_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
	wire         acl_iface_prime_bus_limiter_cmd_src_endofpacket;                        // acl_iface_prime_bus_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
	wire         rsp_mux_src_valid;                                                      // rsp_mux:src_valid -> acl_iface_prime_bus_limiter:rsp_sink_valid
	wire  [75:0] rsp_mux_src_data;                                                       // rsp_mux:src_data -> acl_iface_prime_bus_limiter:rsp_sink_data
	wire         rsp_mux_src_ready;                                                      // acl_iface_prime_bus_limiter:rsp_sink_ready -> rsp_mux:src_ready
	wire   [1:0] rsp_mux_src_channel;                                                    // rsp_mux:src_channel -> acl_iface_prime_bus_limiter:rsp_sink_channel
	wire         rsp_mux_src_startofpacket;                                              // rsp_mux:src_startofpacket -> acl_iface_prime_bus_limiter:rsp_sink_startofpacket
	wire         rsp_mux_src_endofpacket;                                                // rsp_mux:src_endofpacket -> acl_iface_prime_bus_limiter:rsp_sink_endofpacket
	wire         acl_iface_prime_bus_limiter_rsp_src_valid;                              // acl_iface_prime_bus_limiter:rsp_src_valid -> acl_iface_prime_bus_agent:rp_valid
	wire  [75:0] acl_iface_prime_bus_limiter_rsp_src_data;                               // acl_iface_prime_bus_limiter:rsp_src_data -> acl_iface_prime_bus_agent:rp_data
	wire         acl_iface_prime_bus_limiter_rsp_src_ready;                              // acl_iface_prime_bus_agent:rp_ready -> acl_iface_prime_bus_limiter:rsp_src_ready
	wire   [1:0] acl_iface_prime_bus_limiter_rsp_src_channel;                            // acl_iface_prime_bus_limiter:rsp_src_channel -> acl_iface_prime_bus_agent:rp_channel
	wire         acl_iface_prime_bus_limiter_rsp_src_startofpacket;                      // acl_iface_prime_bus_limiter:rsp_src_startofpacket -> acl_iface_prime_bus_agent:rp_startofpacket
	wire         acl_iface_prime_bus_limiter_rsp_src_endofpacket;                        // acl_iface_prime_bus_limiter:rsp_src_endofpacket -> acl_iface_prime_bus_agent:rp_endofpacket
	wire         cmd_demux_src0_valid;                                                   // cmd_demux:src0_valid -> async_fifo:in_valid
	wire  [75:0] cmd_demux_src0_data;                                                    // cmd_demux:src0_data -> async_fifo:in_data
	wire         cmd_demux_src0_ready;                                                   // async_fifo:in_ready -> cmd_demux:src0_ready
	wire   [1:0] cmd_demux_src0_channel;                                                 // cmd_demux:src0_channel -> async_fifo:in_channel
	wire         cmd_demux_src0_startofpacket;                                           // cmd_demux:src0_startofpacket -> async_fifo:in_startofpacket
	wire         cmd_demux_src0_endofpacket;                                             // cmd_demux:src0_endofpacket -> async_fifo:in_endofpacket
	wire         async_fifo_out_valid;                                                   // async_fifo:out_valid -> cmd_mux:sink0_valid
	wire  [75:0] async_fifo_out_data;                                                    // async_fifo:out_data -> cmd_mux:sink0_data
	wire         async_fifo_out_ready;                                                   // cmd_mux:sink0_ready -> async_fifo:out_ready
	wire   [1:0] async_fifo_out_channel;                                                 // async_fifo:out_channel -> cmd_mux:sink0_channel
	wire         async_fifo_out_startofpacket;                                           // async_fifo:out_startofpacket -> cmd_mux:sink0_startofpacket
	wire         async_fifo_out_endofpacket;                                             // async_fifo:out_endofpacket -> cmd_mux:sink0_endofpacket
	wire         cmd_demux_src1_valid;                                                   // cmd_demux:src1_valid -> async_fifo_001:in_valid
	wire  [75:0] cmd_demux_src1_data;                                                    // cmd_demux:src1_data -> async_fifo_001:in_data
	wire         cmd_demux_src1_ready;                                                   // async_fifo_001:in_ready -> cmd_demux:src1_ready
	wire   [1:0] cmd_demux_src1_channel;                                                 // cmd_demux:src1_channel -> async_fifo_001:in_channel
	wire         cmd_demux_src1_startofpacket;                                           // cmd_demux:src1_startofpacket -> async_fifo_001:in_startofpacket
	wire         cmd_demux_src1_endofpacket;                                             // cmd_demux:src1_endofpacket -> async_fifo_001:in_endofpacket
	wire         async_fifo_001_out_valid;                                               // async_fifo_001:out_valid -> cmd_mux_001:sink0_valid
	wire  [75:0] async_fifo_001_out_data;                                                // async_fifo_001:out_data -> cmd_mux_001:sink0_data
	wire         async_fifo_001_out_ready;                                               // cmd_mux_001:sink0_ready -> async_fifo_001:out_ready
	wire   [1:0] async_fifo_001_out_channel;                                             // async_fifo_001:out_channel -> cmd_mux_001:sink0_channel
	wire         async_fifo_001_out_startofpacket;                                       // async_fifo_001:out_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire         async_fifo_001_out_endofpacket;                                         // async_fifo_001:out_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire         rsp_demux_src0_valid;                                                   // rsp_demux:src0_valid -> async_fifo_002:in_valid
	wire  [75:0] rsp_demux_src0_data;                                                    // rsp_demux:src0_data -> async_fifo_002:in_data
	wire         rsp_demux_src0_ready;                                                   // async_fifo_002:in_ready -> rsp_demux:src0_ready
	wire   [1:0] rsp_demux_src0_channel;                                                 // rsp_demux:src0_channel -> async_fifo_002:in_channel
	wire         rsp_demux_src0_startofpacket;                                           // rsp_demux:src0_startofpacket -> async_fifo_002:in_startofpacket
	wire         rsp_demux_src0_endofpacket;                                             // rsp_demux:src0_endofpacket -> async_fifo_002:in_endofpacket
	wire         async_fifo_002_out_valid;                                               // async_fifo_002:out_valid -> rsp_mux:sink0_valid
	wire  [75:0] async_fifo_002_out_data;                                                // async_fifo_002:out_data -> rsp_mux:sink0_data
	wire         async_fifo_002_out_ready;                                               // rsp_mux:sink0_ready -> async_fifo_002:out_ready
	wire   [1:0] async_fifo_002_out_channel;                                             // async_fifo_002:out_channel -> rsp_mux:sink0_channel
	wire         async_fifo_002_out_startofpacket;                                       // async_fifo_002:out_startofpacket -> rsp_mux:sink0_startofpacket
	wire         async_fifo_002_out_endofpacket;                                         // async_fifo_002:out_endofpacket -> rsp_mux:sink0_endofpacket
	wire         rsp_demux_001_src0_valid;                                               // rsp_demux_001:src0_valid -> async_fifo_003:in_valid
	wire  [75:0] rsp_demux_001_src0_data;                                                // rsp_demux_001:src0_data -> async_fifo_003:in_data
	wire         rsp_demux_001_src0_ready;                                               // async_fifo_003:in_ready -> rsp_demux_001:src0_ready
	wire   [1:0] rsp_demux_001_src0_channel;                                             // rsp_demux_001:src0_channel -> async_fifo_003:in_channel
	wire         rsp_demux_001_src0_startofpacket;                                       // rsp_demux_001:src0_startofpacket -> async_fifo_003:in_startofpacket
	wire         rsp_demux_001_src0_endofpacket;                                         // rsp_demux_001:src0_endofpacket -> async_fifo_003:in_endofpacket
	wire         async_fifo_003_out_valid;                                               // async_fifo_003:out_valid -> rsp_mux:sink1_valid
	wire  [75:0] async_fifo_003_out_data;                                                // async_fifo_003:out_data -> rsp_mux:sink1_data
	wire         async_fifo_003_out_ready;                                               // rsp_mux:sink1_ready -> async_fifo_003:out_ready
	wire   [1:0] async_fifo_003_out_channel;                                             // async_fifo_003:out_channel -> rsp_mux:sink1_channel
	wire         async_fifo_003_out_startofpacket;                                       // async_fifo_003:out_startofpacket -> rsp_mux:sink1_startofpacket
	wire         async_fifo_003_out_endofpacket;                                         // async_fifo_003:out_endofpacket -> rsp_mux:sink1_endofpacket
	wire   [1:0] acl_iface_prime_bus_limiter_cmd_valid_data;                             // acl_iface_prime_bus_limiter:cmd_src_valid -> cmd_demux:sink_valid
	wire         float_mult_smack_ctrl_bus_agent_rdata_fifo_out_valid;                   // float_mult_smack_ctrl_bus_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
	wire  [33:0] float_mult_smack_ctrl_bus_agent_rdata_fifo_out_data;                    // float_mult_smack_ctrl_bus_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
	wire         float_mult_smack_ctrl_bus_agent_rdata_fifo_out_ready;                   // avalon_st_adapter:in_0_ready -> float_mult_smack_ctrl_bus_agent_rdata_fifo:out_ready
	wire         avalon_st_adapter_out_0_valid;                                          // avalon_st_adapter:out_0_valid -> float_mult_smack_ctrl_bus_agent:rdata_fifo_sink_valid
	wire  [33:0] avalon_st_adapter_out_0_data;                                           // avalon_st_adapter:out_0_data -> float_mult_smack_ctrl_bus_agent:rdata_fifo_sink_data
	wire         avalon_st_adapter_out_0_ready;                                          // float_mult_smack_ctrl_bus_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire   [0:0] avalon_st_adapter_out_0_error;                                          // avalon_st_adapter:out_0_error -> float_mult_smack_ctrl_bus_agent:rdata_fifo_sink_error
	wire         float_add_smack_ctrl_bus_agent_rdata_fifo_out_valid;                    // float_add_smack_ctrl_bus_agent_rdata_fifo:out_valid -> avalon_st_adapter_001:in_0_valid
	wire  [33:0] float_add_smack_ctrl_bus_agent_rdata_fifo_out_data;                     // float_add_smack_ctrl_bus_agent_rdata_fifo:out_data -> avalon_st_adapter_001:in_0_data
	wire         float_add_smack_ctrl_bus_agent_rdata_fifo_out_ready;                    // avalon_st_adapter_001:in_0_ready -> float_add_smack_ctrl_bus_agent_rdata_fifo:out_ready
	wire         avalon_st_adapter_001_out_0_valid;                                      // avalon_st_adapter_001:out_0_valid -> float_add_smack_ctrl_bus_agent:rdata_fifo_sink_valid
	wire  [33:0] avalon_st_adapter_001_out_0_data;                                       // avalon_st_adapter_001:out_0_data -> float_add_smack_ctrl_bus_agent:rdata_fifo_sink_data
	wire         avalon_st_adapter_001_out_0_ready;                                      // float_add_smack_ctrl_bus_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
	wire   [0:0] avalon_st_adapter_001_out_0_error;                                      // avalon_st_adapter_001:out_0_error -> float_add_smack_ctrl_bus_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (6),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (6),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) acl_iface_prime_bus_translator (
		.clk                    (ext_clk_50_clk_clk),                                                     //                       clk.clk
		.reset                  (acl_iface_prime_bus_translator_reset_reset_bridge_in_reset_reset),       //                     reset.reset
		.uav_address            (acl_iface_prime_bus_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (acl_iface_prime_bus_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (acl_iface_prime_bus_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (acl_iface_prime_bus_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (acl_iface_prime_bus_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (acl_iface_prime_bus_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (acl_iface_prime_bus_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (acl_iface_prime_bus_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (acl_iface_prime_bus_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (acl_iface_prime_bus_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (acl_iface_prime_bus_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (acl_iface_prime_bus_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (acl_iface_prime_bus_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (acl_iface_prime_bus_burstcount),                                         //                          .burstcount
		.av_byteenable          (acl_iface_prime_bus_byteenable),                                         //                          .byteenable
		.av_read                (acl_iface_prime_bus_read),                                               //                          .read
		.av_readdata            (acl_iface_prime_bus_readdata),                                           //                          .readdata
		.av_readdatavalid       (acl_iface_prime_bus_readdatavalid),                                      //                          .readdatavalid
		.av_write               (acl_iface_prime_bus_write),                                              //                          .write
		.av_writedata           (acl_iface_prime_bus_writedata),                                          //                          .writedata
		.av_debugaccess         (acl_iface_prime_bus_debugaccess),                                        //                          .debugaccess
		.av_beginbursttransfer  (1'b0),                                                                   //               (terminated)
		.av_begintransfer       (1'b0),                                                                   //               (terminated)
		.av_chipselect          (1'b0),                                                                   //               (terminated)
		.av_lock                (1'b0),                                                                   //               (terminated)
		.uav_clken              (),                                                                       //               (terminated)
		.av_clken               (1'b1),                                                                   //               (terminated)
		.uav_response           (2'b00),                                                                  //               (terminated)
		.av_response            (),                                                                       //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                   //               (terminated)
		.av_writeresponsevalid  ()                                                                        //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (6),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) float_mult_smack_ctrl_bus_translator (
		.clk                    (acl_iface_prime_clk_clk),                                //                      clk.clk
		.reset                  (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (float_mult_smack_ctrl_bus_agent_m0_address),             // avalon_universal_slave_0.address
		.uav_burstcount         (float_mult_smack_ctrl_bus_agent_m0_burstcount),          //                         .burstcount
		.uav_read               (float_mult_smack_ctrl_bus_agent_m0_read),                //                         .read
		.uav_write              (float_mult_smack_ctrl_bus_agent_m0_write),               //                         .write
		.uav_waitrequest        (float_mult_smack_ctrl_bus_agent_m0_waitrequest),         //                         .waitrequest
		.uav_readdatavalid      (float_mult_smack_ctrl_bus_agent_m0_readdatavalid),       //                         .readdatavalid
		.uav_byteenable         (float_mult_smack_ctrl_bus_agent_m0_byteenable),          //                         .byteenable
		.uav_readdata           (float_mult_smack_ctrl_bus_agent_m0_readdata),            //                         .readdata
		.uav_writedata          (float_mult_smack_ctrl_bus_agent_m0_writedata),           //                         .writedata
		.uav_lock               (float_mult_smack_ctrl_bus_agent_m0_lock),                //                         .lock
		.uav_debugaccess        (float_mult_smack_ctrl_bus_agent_m0_debugaccess),         //                         .debugaccess
		.av_address             (float_mult_smack_ctrl_bus_address),                      //      avalon_anti_slave_0.address
		.av_write               (float_mult_smack_ctrl_bus_write),                        //                         .write
		.av_read                (float_mult_smack_ctrl_bus_read),                         //                         .read
		.av_readdata            (float_mult_smack_ctrl_bus_readdata),                     //                         .readdata
		.av_writedata           (float_mult_smack_ctrl_bus_writedata),                    //                         .writedata
		.av_waitrequest         (float_mult_smack_ctrl_bus_waitrequest),                  //                         .waitrequest
		.av_begintransfer       (),                                                       //              (terminated)
		.av_beginbursttransfer  (),                                                       //              (terminated)
		.av_burstcount          (),                                                       //              (terminated)
		.av_byteenable          (),                                                       //              (terminated)
		.av_readdatavalid       (1'b0),                                                   //              (terminated)
		.av_writebyteenable     (),                                                       //              (terminated)
		.av_lock                (),                                                       //              (terminated)
		.av_chipselect          (),                                                       //              (terminated)
		.av_clken               (),                                                       //              (terminated)
		.uav_clken              (1'b0),                                                   //              (terminated)
		.av_debugaccess         (),                                                       //              (terminated)
		.av_outputenable        (),                                                       //              (terminated)
		.uav_response           (),                                                       //              (terminated)
		.av_response            (2'b00),                                                  //              (terminated)
		.uav_writeresponsevalid (),                                                       //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                    //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (6),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) float_add_smack_ctrl_bus_translator (
		.clk                    (acl_iface_prime_clk_clk),                                //                      clk.clk
		.reset                  (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (float_add_smack_ctrl_bus_agent_m0_address),              // avalon_universal_slave_0.address
		.uav_burstcount         (float_add_smack_ctrl_bus_agent_m0_burstcount),           //                         .burstcount
		.uav_read               (float_add_smack_ctrl_bus_agent_m0_read),                 //                         .read
		.uav_write              (float_add_smack_ctrl_bus_agent_m0_write),                //                         .write
		.uav_waitrequest        (float_add_smack_ctrl_bus_agent_m0_waitrequest),          //                         .waitrequest
		.uav_readdatavalid      (float_add_smack_ctrl_bus_agent_m0_readdatavalid),        //                         .readdatavalid
		.uav_byteenable         (float_add_smack_ctrl_bus_agent_m0_byteenable),           //                         .byteenable
		.uav_readdata           (float_add_smack_ctrl_bus_agent_m0_readdata),             //                         .readdata
		.uav_writedata          (float_add_smack_ctrl_bus_agent_m0_writedata),            //                         .writedata
		.uav_lock               (float_add_smack_ctrl_bus_agent_m0_lock),                 //                         .lock
		.uav_debugaccess        (float_add_smack_ctrl_bus_agent_m0_debugaccess),          //                         .debugaccess
		.av_address             (float_add_smack_ctrl_bus_address),                       //      avalon_anti_slave_0.address
		.av_write               (float_add_smack_ctrl_bus_write),                         //                         .write
		.av_read                (float_add_smack_ctrl_bus_read),                          //                         .read
		.av_readdata            (float_add_smack_ctrl_bus_readdata),                      //                         .readdata
		.av_writedata           (float_add_smack_ctrl_bus_writedata),                     //                         .writedata
		.av_waitrequest         (float_add_smack_ctrl_bus_waitrequest),                   //                         .waitrequest
		.av_begintransfer       (),                                                       //              (terminated)
		.av_beginbursttransfer  (),                                                       //              (terminated)
		.av_burstcount          (),                                                       //              (terminated)
		.av_byteenable          (),                                                       //              (terminated)
		.av_readdatavalid       (1'b0),                                                   //              (terminated)
		.av_writebyteenable     (),                                                       //              (terminated)
		.av_lock                (),                                                       //              (terminated)
		.av_chipselect          (),                                                       //              (terminated)
		.av_clken               (),                                                       //              (terminated)
		.uav_clken              (1'b0),                                                   //              (terminated)
		.av_debugaccess         (),                                                       //              (terminated)
		.av_outputenable        (),                                                       //              (terminated)
		.uav_response           (),                                                       //              (terminated)
		.av_response            (2'b00),                                                  //              (terminated)
		.uav_writeresponsevalid (),                                                       //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                    //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (75),
		.PKT_ORI_BURST_SIZE_L      (73),
		.PKT_RESPONSE_STATUS_H     (72),
		.PKT_RESPONSE_STATUS_L     (71),
		.PKT_QOS_H                 (60),
		.PKT_QOS_L                 (60),
		.PKT_DATA_SIDEBAND_H       (58),
		.PKT_DATA_SIDEBAND_L       (58),
		.PKT_ADDR_SIDEBAND_H       (57),
		.PKT_ADDR_SIDEBAND_L       (57),
		.PKT_BURST_TYPE_H          (56),
		.PKT_BURST_TYPE_L          (55),
		.PKT_CACHE_H               (70),
		.PKT_CACHE_L               (67),
		.PKT_THREAD_ID_H           (63),
		.PKT_THREAD_ID_L           (63),
		.PKT_BURST_SIZE_H          (54),
		.PKT_BURST_SIZE_L          (52),
		.PKT_TRANS_EXCLUSIVE       (47),
		.PKT_TRANS_LOCK            (46),
		.PKT_BEGIN_BURST           (59),
		.PKT_PROTECTION_H          (66),
		.PKT_PROTECTION_L          (64),
		.PKT_BURSTWRAP_H           (51),
		.PKT_BURSTWRAP_L           (51),
		.PKT_BYTE_CNT_H            (50),
		.PKT_BYTE_CNT_L            (48),
		.PKT_ADDR_H                (41),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (42),
		.PKT_TRANS_POSTED          (43),
		.PKT_TRANS_WRITE           (44),
		.PKT_TRANS_READ            (45),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (61),
		.PKT_DEST_ID_H             (62),
		.PKT_DEST_ID_L             (62),
		.ST_DATA_W                 (76),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) acl_iface_prime_bus_agent (
		.clk                   (ext_clk_50_clk_clk),                                                     //       clk.clk
		.reset                 (acl_iface_prime_bus_translator_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
		.av_address            (acl_iface_prime_bus_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (acl_iface_prime_bus_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (acl_iface_prime_bus_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (acl_iface_prime_bus_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (acl_iface_prime_bus_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (acl_iface_prime_bus_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (acl_iface_prime_bus_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (acl_iface_prime_bus_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (acl_iface_prime_bus_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (acl_iface_prime_bus_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (acl_iface_prime_bus_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (acl_iface_prime_bus_agent_cp_valid),                                     //        cp.valid
		.cp_data               (acl_iface_prime_bus_agent_cp_data),                                      //          .data
		.cp_startofpacket      (acl_iface_prime_bus_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (acl_iface_prime_bus_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (acl_iface_prime_bus_agent_cp_ready),                                     //          .ready
		.rp_valid              (acl_iface_prime_bus_limiter_rsp_src_valid),                              //        rp.valid
		.rp_data               (acl_iface_prime_bus_limiter_rsp_src_data),                               //          .data
		.rp_channel            (acl_iface_prime_bus_limiter_rsp_src_channel),                            //          .channel
		.rp_startofpacket      (acl_iface_prime_bus_limiter_rsp_src_startofpacket),                      //          .startofpacket
		.rp_endofpacket        (acl_iface_prime_bus_limiter_rsp_src_endofpacket),                        //          .endofpacket
		.rp_ready              (acl_iface_prime_bus_limiter_rsp_src_ready),                              //          .ready
		.av_response           (),                                                                       // (terminated)
		.av_writeresponsevalid ()                                                                        // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (75),
		.PKT_ORI_BURST_SIZE_L      (73),
		.PKT_RESPONSE_STATUS_H     (72),
		.PKT_RESPONSE_STATUS_L     (71),
		.PKT_BURST_SIZE_H          (54),
		.PKT_BURST_SIZE_L          (52),
		.PKT_TRANS_LOCK            (46),
		.PKT_BEGIN_BURST           (59),
		.PKT_PROTECTION_H          (66),
		.PKT_PROTECTION_L          (64),
		.PKT_BURSTWRAP_H           (51),
		.PKT_BURSTWRAP_L           (51),
		.PKT_BYTE_CNT_H            (50),
		.PKT_BYTE_CNT_L            (48),
		.PKT_ADDR_H                (41),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (42),
		.PKT_TRANS_POSTED          (43),
		.PKT_TRANS_WRITE           (44),
		.PKT_TRANS_READ            (45),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (61),
		.PKT_DEST_ID_H             (62),
		.PKT_DEST_ID_L             (62),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (76),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) float_mult_smack_ctrl_bus_agent (
		.clk                     (acl_iface_prime_clk_clk),                                    //             clk.clk
		.reset                   (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset),     //       clk_reset.reset
		.m0_address              (float_mult_smack_ctrl_bus_agent_m0_address),                 //              m0.address
		.m0_burstcount           (float_mult_smack_ctrl_bus_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (float_mult_smack_ctrl_bus_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (float_mult_smack_ctrl_bus_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (float_mult_smack_ctrl_bus_agent_m0_lock),                    //                .lock
		.m0_readdata             (float_mult_smack_ctrl_bus_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (float_mult_smack_ctrl_bus_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (float_mult_smack_ctrl_bus_agent_m0_read),                    //                .read
		.m0_waitrequest          (float_mult_smack_ctrl_bus_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (float_mult_smack_ctrl_bus_agent_m0_writedata),               //                .writedata
		.m0_write                (float_mult_smack_ctrl_bus_agent_m0_write),                   //                .write
		.rp_endofpacket          (float_mult_smack_ctrl_bus_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (float_mult_smack_ctrl_bus_agent_rp_ready),                   //                .ready
		.rp_valid                (float_mult_smack_ctrl_bus_agent_rp_valid),                   //                .valid
		.rp_data                 (float_mult_smack_ctrl_bus_agent_rp_data),                    //                .data
		.rp_startofpacket        (float_mult_smack_ctrl_bus_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_src_ready),                                          //              cp.ready
		.cp_valid                (cmd_mux_src_valid),                                          //                .valid
		.cp_data                 (cmd_mux_src_data),                                           //                .data
		.cp_startofpacket        (cmd_mux_src_startofpacket),                                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_src_endofpacket),                                    //                .endofpacket
		.cp_channel              (cmd_mux_src_channel),                                        //                .channel
		.rf_sink_ready           (float_mult_smack_ctrl_bus_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (float_mult_smack_ctrl_bus_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (float_mult_smack_ctrl_bus_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (float_mult_smack_ctrl_bus_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (float_mult_smack_ctrl_bus_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (float_mult_smack_ctrl_bus_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (float_mult_smack_ctrl_bus_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (float_mult_smack_ctrl_bus_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (float_mult_smack_ctrl_bus_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (float_mult_smack_ctrl_bus_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                              //                .error
		.rdata_fifo_src_ready    (float_mult_smack_ctrl_bus_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (float_mult_smack_ctrl_bus_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (float_mult_smack_ctrl_bus_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                      //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                        //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (77),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) float_mult_smack_ctrl_bus_agent_rsp_fifo (
		.clk               (acl_iface_prime_clk_clk),                                    //       clk.clk
		.reset             (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset),     // clk_reset.reset
		.in_data           (float_mult_smack_ctrl_bus_agent_rf_source_data),             //        in.data
		.in_valid          (float_mult_smack_ctrl_bus_agent_rf_source_valid),            //          .valid
		.in_ready          (float_mult_smack_ctrl_bus_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (float_mult_smack_ctrl_bus_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (float_mult_smack_ctrl_bus_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (float_mult_smack_ctrl_bus_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (float_mult_smack_ctrl_bus_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (float_mult_smack_ctrl_bus_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (float_mult_smack_ctrl_bus_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (float_mult_smack_ctrl_bus_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                      // (terminated)
		.csr_read          (1'b0),                                                       // (terminated)
		.csr_write         (1'b0),                                                       // (terminated)
		.csr_readdata      (),                                                           // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                       // (terminated)
		.almost_full_data  (),                                                           // (terminated)
		.almost_empty_data (),                                                           // (terminated)
		.in_empty          (1'b0),                                                       // (terminated)
		.out_empty         (),                                                           // (terminated)
		.in_error          (1'b0),                                                       // (terminated)
		.out_error         (),                                                           // (terminated)
		.in_channel        (1'b0),                                                       // (terminated)
		.out_channel       ()                                                            // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) float_mult_smack_ctrl_bus_agent_rdata_fifo (
		.clk               (acl_iface_prime_clk_clk),                                //       clk.clk
		.reset             (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (float_mult_smack_ctrl_bus_agent_rdata_fifo_src_data),    //        in.data
		.in_valid          (float_mult_smack_ctrl_bus_agent_rdata_fifo_src_valid),   //          .valid
		.in_ready          (float_mult_smack_ctrl_bus_agent_rdata_fifo_src_ready),   //          .ready
		.out_data          (float_mult_smack_ctrl_bus_agent_rdata_fifo_out_data),    //       out.data
		.out_valid         (float_mult_smack_ctrl_bus_agent_rdata_fifo_out_valid),   //          .valid
		.out_ready         (float_mult_smack_ctrl_bus_agent_rdata_fifo_out_ready),   //          .ready
		.csr_address       (2'b00),                                                  // (terminated)
		.csr_read          (1'b0),                                                   // (terminated)
		.csr_write         (1'b0),                                                   // (terminated)
		.csr_readdata      (),                                                       // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                   // (terminated)
		.almost_full_data  (),                                                       // (terminated)
		.almost_empty_data (),                                                       // (terminated)
		.in_startofpacket  (1'b0),                                                   // (terminated)
		.in_endofpacket    (1'b0),                                                   // (terminated)
		.out_startofpacket (),                                                       // (terminated)
		.out_endofpacket   (),                                                       // (terminated)
		.in_empty          (1'b0),                                                   // (terminated)
		.out_empty         (),                                                       // (terminated)
		.in_error          (1'b0),                                                   // (terminated)
		.out_error         (),                                                       // (terminated)
		.in_channel        (1'b0),                                                   // (terminated)
		.out_channel       ()                                                        // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (75),
		.PKT_ORI_BURST_SIZE_L      (73),
		.PKT_RESPONSE_STATUS_H     (72),
		.PKT_RESPONSE_STATUS_L     (71),
		.PKT_BURST_SIZE_H          (54),
		.PKT_BURST_SIZE_L          (52),
		.PKT_TRANS_LOCK            (46),
		.PKT_BEGIN_BURST           (59),
		.PKT_PROTECTION_H          (66),
		.PKT_PROTECTION_L          (64),
		.PKT_BURSTWRAP_H           (51),
		.PKT_BURSTWRAP_L           (51),
		.PKT_BYTE_CNT_H            (50),
		.PKT_BYTE_CNT_L            (48),
		.PKT_ADDR_H                (41),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (42),
		.PKT_TRANS_POSTED          (43),
		.PKT_TRANS_WRITE           (44),
		.PKT_TRANS_READ            (45),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (61),
		.PKT_DEST_ID_H             (62),
		.PKT_DEST_ID_L             (62),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (76),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) float_add_smack_ctrl_bus_agent (
		.clk                     (acl_iface_prime_clk_clk),                                   //             clk.clk
		.reset                   (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset),    //       clk_reset.reset
		.m0_address              (float_add_smack_ctrl_bus_agent_m0_address),                 //              m0.address
		.m0_burstcount           (float_add_smack_ctrl_bus_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (float_add_smack_ctrl_bus_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (float_add_smack_ctrl_bus_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (float_add_smack_ctrl_bus_agent_m0_lock),                    //                .lock
		.m0_readdata             (float_add_smack_ctrl_bus_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (float_add_smack_ctrl_bus_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (float_add_smack_ctrl_bus_agent_m0_read),                    //                .read
		.m0_waitrequest          (float_add_smack_ctrl_bus_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (float_add_smack_ctrl_bus_agent_m0_writedata),               //                .writedata
		.m0_write                (float_add_smack_ctrl_bus_agent_m0_write),                   //                .write
		.rp_endofpacket          (float_add_smack_ctrl_bus_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (float_add_smack_ctrl_bus_agent_rp_ready),                   //                .ready
		.rp_valid                (float_add_smack_ctrl_bus_agent_rp_valid),                   //                .valid
		.rp_data                 (float_add_smack_ctrl_bus_agent_rp_data),                    //                .data
		.rp_startofpacket        (float_add_smack_ctrl_bus_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_001_src_ready),                                     //              cp.ready
		.cp_valid                (cmd_mux_001_src_valid),                                     //                .valid
		.cp_data                 (cmd_mux_001_src_data),                                      //                .data
		.cp_startofpacket        (cmd_mux_001_src_startofpacket),                             //                .startofpacket
		.cp_endofpacket          (cmd_mux_001_src_endofpacket),                               //                .endofpacket
		.cp_channel              (cmd_mux_001_src_channel),                                   //                .channel
		.rf_sink_ready           (float_add_smack_ctrl_bus_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (float_add_smack_ctrl_bus_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (float_add_smack_ctrl_bus_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (float_add_smack_ctrl_bus_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (float_add_smack_ctrl_bus_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (float_add_smack_ctrl_bus_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (float_add_smack_ctrl_bus_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (float_add_smack_ctrl_bus_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (float_add_smack_ctrl_bus_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (float_add_smack_ctrl_bus_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),                         // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),                         //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),                          //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),                         //                .error
		.rdata_fifo_src_ready    (float_add_smack_ctrl_bus_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (float_add_smack_ctrl_bus_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (float_add_smack_ctrl_bus_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                     //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                       //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (77),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) float_add_smack_ctrl_bus_agent_rsp_fifo (
		.clk               (acl_iface_prime_clk_clk),                                   //       clk.clk
		.reset             (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset),    // clk_reset.reset
		.in_data           (float_add_smack_ctrl_bus_agent_rf_source_data),             //        in.data
		.in_valid          (float_add_smack_ctrl_bus_agent_rf_source_valid),            //          .valid
		.in_ready          (float_add_smack_ctrl_bus_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (float_add_smack_ctrl_bus_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (float_add_smack_ctrl_bus_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (float_add_smack_ctrl_bus_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (float_add_smack_ctrl_bus_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (float_add_smack_ctrl_bus_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (float_add_smack_ctrl_bus_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (float_add_smack_ctrl_bus_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                     // (terminated)
		.csr_read          (1'b0),                                                      // (terminated)
		.csr_write         (1'b0),                                                      // (terminated)
		.csr_readdata      (),                                                          // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated)
		.almost_full_data  (),                                                          // (terminated)
		.almost_empty_data (),                                                          // (terminated)
		.in_empty          (1'b0),                                                      // (terminated)
		.out_empty         (),                                                          // (terminated)
		.in_error          (1'b0),                                                      // (terminated)
		.out_error         (),                                                          // (terminated)
		.in_channel        (1'b0),                                                      // (terminated)
		.out_channel       ()                                                           // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) float_add_smack_ctrl_bus_agent_rdata_fifo (
		.clk               (acl_iface_prime_clk_clk),                                //       clk.clk
		.reset             (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (float_add_smack_ctrl_bus_agent_rdata_fifo_src_data),     //        in.data
		.in_valid          (float_add_smack_ctrl_bus_agent_rdata_fifo_src_valid),    //          .valid
		.in_ready          (float_add_smack_ctrl_bus_agent_rdata_fifo_src_ready),    //          .ready
		.out_data          (float_add_smack_ctrl_bus_agent_rdata_fifo_out_data),     //       out.data
		.out_valid         (float_add_smack_ctrl_bus_agent_rdata_fifo_out_valid),    //          .valid
		.out_ready         (float_add_smack_ctrl_bus_agent_rdata_fifo_out_ready),    //          .ready
		.csr_address       (2'b00),                                                  // (terminated)
		.csr_read          (1'b0),                                                   // (terminated)
		.csr_write         (1'b0),                                                   // (terminated)
		.csr_readdata      (),                                                       // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                   // (terminated)
		.almost_full_data  (),                                                       // (terminated)
		.almost_empty_data (),                                                       // (terminated)
		.in_startofpacket  (1'b0),                                                   // (terminated)
		.in_endofpacket    (1'b0),                                                   // (terminated)
		.out_startofpacket (),                                                       // (terminated)
		.out_endofpacket   (),                                                       // (terminated)
		.in_empty          (1'b0),                                                   // (terminated)
		.out_empty         (),                                                       // (terminated)
		.in_error          (1'b0),                                                   // (terminated)
		.out_error         (),                                                       // (terminated)
		.in_channel        (1'b0),                                                   // (terminated)
		.out_channel       ()                                                        // (terminated)
	);

	system_mm_interconnect_5_router router (
		.sink_ready         (acl_iface_prime_bus_agent_cp_ready),                               //      sink.ready
		.sink_valid         (acl_iface_prime_bus_agent_cp_valid),                               //          .valid
		.sink_data          (acl_iface_prime_bus_agent_cp_data),                                //          .data
		.sink_startofpacket (acl_iface_prime_bus_agent_cp_startofpacket),                       //          .startofpacket
		.sink_endofpacket   (acl_iface_prime_bus_agent_cp_endofpacket),                         //          .endofpacket
		.clk                (ext_clk_50_clk_clk),                                               //       clk.clk
		.reset              (acl_iface_prime_bus_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                                                 //       src.ready
		.src_valid          (router_src_valid),                                                 //          .valid
		.src_data           (router_src_data),                                                  //          .data
		.src_channel        (router_src_channel),                                               //          .channel
		.src_startofpacket  (router_src_startofpacket),                                         //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                            //          .endofpacket
	);

	system_mm_interconnect_5_router_001 router_001 (
		.sink_ready         (float_mult_smack_ctrl_bus_agent_rp_ready),               //      sink.ready
		.sink_valid         (float_mult_smack_ctrl_bus_agent_rp_valid),               //          .valid
		.sink_data          (float_mult_smack_ctrl_bus_agent_rp_data),                //          .data
		.sink_startofpacket (float_mult_smack_ctrl_bus_agent_rp_startofpacket),       //          .startofpacket
		.sink_endofpacket   (float_mult_smack_ctrl_bus_agent_rp_endofpacket),         //          .endofpacket
		.clk                (acl_iface_prime_clk_clk),                                //       clk.clk
		.reset              (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                                   //       src.ready
		.src_valid          (router_001_src_valid),                                   //          .valid
		.src_data           (router_001_src_data),                                    //          .data
		.src_channel        (router_001_src_channel),                                 //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                           //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                              //          .endofpacket
	);

	system_mm_interconnect_5_router_001 router_002 (
		.sink_ready         (float_add_smack_ctrl_bus_agent_rp_ready),                //      sink.ready
		.sink_valid         (float_add_smack_ctrl_bus_agent_rp_valid),                //          .valid
		.sink_data          (float_add_smack_ctrl_bus_agent_rp_data),                 //          .data
		.sink_startofpacket (float_add_smack_ctrl_bus_agent_rp_startofpacket),        //          .startofpacket
		.sink_endofpacket   (float_add_smack_ctrl_bus_agent_rp_endofpacket),          //          .endofpacket
		.clk                (acl_iface_prime_clk_clk),                                //       clk.clk
		.reset              (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_002_src_ready),                                   //       src.ready
		.src_valid          (router_002_src_valid),                                   //          .valid
		.src_data           (router_002_src_data),                                    //          .data
		.src_channel        (router_002_src_channel),                                 //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                           //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                              //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (62),
		.PKT_DEST_ID_L             (62),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (61),
		.PKT_BYTE_CNT_H            (50),
		.PKT_BYTE_CNT_L            (48),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_TRANS_POSTED          (43),
		.PKT_TRANS_WRITE           (44),
		.MAX_OUTSTANDING_RESPONSES (19),
		.PIPELINED                 (0),
		.ST_DATA_W                 (76),
		.ST_CHANNEL_W              (2),
		.VALID_WIDTH               (2),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.SUPPORTS_POSTED_WRITES    (1),
		.SUPPORTS_NONPOSTED_WRITES (0),
		.REORDER                   (0)
	) acl_iface_prime_bus_limiter (
		.clk                    (ext_clk_50_clk_clk),                                               //       clk.clk
		.reset                  (acl_iface_prime_bus_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                                 //  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                                 //          .valid
		.cmd_sink_data          (router_src_data),                                                  //          .data
		.cmd_sink_channel       (router_src_channel),                                               //          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                                         //          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                                           //          .endofpacket
		.cmd_src_ready          (acl_iface_prime_bus_limiter_cmd_src_ready),                        //   cmd_src.ready
		.cmd_src_data           (acl_iface_prime_bus_limiter_cmd_src_data),                         //          .data
		.cmd_src_channel        (acl_iface_prime_bus_limiter_cmd_src_channel),                      //          .channel
		.cmd_src_startofpacket  (acl_iface_prime_bus_limiter_cmd_src_startofpacket),                //          .startofpacket
		.cmd_src_endofpacket    (acl_iface_prime_bus_limiter_cmd_src_endofpacket),                  //          .endofpacket
		.rsp_sink_ready         (rsp_mux_src_ready),                                                //  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_src_valid),                                                //          .valid
		.rsp_sink_channel       (rsp_mux_src_channel),                                              //          .channel
		.rsp_sink_data          (rsp_mux_src_data),                                                 //          .data
		.rsp_sink_startofpacket (rsp_mux_src_startofpacket),                                        //          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_src_endofpacket),                                          //          .endofpacket
		.rsp_src_ready          (acl_iface_prime_bus_limiter_rsp_src_ready),                        //   rsp_src.ready
		.rsp_src_valid          (acl_iface_prime_bus_limiter_rsp_src_valid),                        //          .valid
		.rsp_src_data           (acl_iface_prime_bus_limiter_rsp_src_data),                         //          .data
		.rsp_src_channel        (acl_iface_prime_bus_limiter_rsp_src_channel),                      //          .channel
		.rsp_src_startofpacket  (acl_iface_prime_bus_limiter_rsp_src_startofpacket),                //          .startofpacket
		.rsp_src_endofpacket    (acl_iface_prime_bus_limiter_rsp_src_endofpacket),                  //          .endofpacket
		.cmd_src_valid          (acl_iface_prime_bus_limiter_cmd_valid_data)                        // cmd_valid.data
	);

	system_mm_interconnect_5_cmd_demux cmd_demux (
		.clk                (ext_clk_50_clk_clk),                                               //        clk.clk
		.reset              (acl_iface_prime_bus_translator_reset_reset_bridge_in_reset_reset), //  clk_reset.reset
		.sink_ready         (acl_iface_prime_bus_limiter_cmd_src_ready),                        //       sink.ready
		.sink_channel       (acl_iface_prime_bus_limiter_cmd_src_channel),                      //           .channel
		.sink_data          (acl_iface_prime_bus_limiter_cmd_src_data),                         //           .data
		.sink_startofpacket (acl_iface_prime_bus_limiter_cmd_src_startofpacket),                //           .startofpacket
		.sink_endofpacket   (acl_iface_prime_bus_limiter_cmd_src_endofpacket),                  //           .endofpacket
		.sink_valid         (acl_iface_prime_bus_limiter_cmd_valid_data),                       // sink_valid.data
		.src0_ready         (cmd_demux_src0_ready),                                             //       src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                             //           .valid
		.src0_data          (cmd_demux_src0_data),                                              //           .data
		.src0_channel       (cmd_demux_src0_channel),                                           //           .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                     //           .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                                       //           .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                                             //       src1.ready
		.src1_valid         (cmd_demux_src1_valid),                                             //           .valid
		.src1_data          (cmd_demux_src1_data),                                              //           .data
		.src1_channel       (cmd_demux_src1_channel),                                           //           .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                                     //           .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket)                                        //           .endofpacket
	);

	system_mm_interconnect_5_cmd_mux cmd_mux (
		.clk                 (acl_iface_prime_clk_clk),                                //       clk.clk
		.reset               (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                      //       src.ready
		.src_valid           (cmd_mux_src_valid),                                      //          .valid
		.src_data            (cmd_mux_src_data),                                       //          .data
		.src_channel         (cmd_mux_src_channel),                                    //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                              //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                //          .endofpacket
		.sink0_ready         (async_fifo_out_ready),                                   //     sink0.ready
		.sink0_valid         (async_fifo_out_valid),                                   //          .valid
		.sink0_channel       (async_fifo_out_channel),                                 //          .channel
		.sink0_data          (async_fifo_out_data),                                    //          .data
		.sink0_startofpacket (async_fifo_out_startofpacket),                           //          .startofpacket
		.sink0_endofpacket   (async_fifo_out_endofpacket)                              //          .endofpacket
	);

	system_mm_interconnect_5_cmd_mux cmd_mux_001 (
		.clk                 (acl_iface_prime_clk_clk),                                //       clk.clk
		.reset               (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                                  //       src.ready
		.src_valid           (cmd_mux_001_src_valid),                                  //          .valid
		.src_data            (cmd_mux_001_src_data),                                   //          .data
		.src_channel         (cmd_mux_001_src_channel),                                //          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                          //          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                            //          .endofpacket
		.sink0_ready         (async_fifo_001_out_ready),                               //     sink0.ready
		.sink0_valid         (async_fifo_001_out_valid),                               //          .valid
		.sink0_channel       (async_fifo_001_out_channel),                             //          .channel
		.sink0_data          (async_fifo_001_out_data),                                //          .data
		.sink0_startofpacket (async_fifo_001_out_startofpacket),                       //          .startofpacket
		.sink0_endofpacket   (async_fifo_001_out_endofpacket)                          //          .endofpacket
	);

	system_mm_interconnect_5_rsp_demux rsp_demux (
		.clk                (acl_iface_prime_clk_clk),                                //       clk.clk
		.reset              (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                                   //      sink.ready
		.sink_channel       (router_001_src_channel),                                 //          .channel
		.sink_data          (router_001_src_data),                                    //          .data
		.sink_startofpacket (router_001_src_startofpacket),                           //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                             //          .endofpacket
		.sink_valid         (router_001_src_valid),                                   //          .valid
		.src0_ready         (rsp_demux_src0_ready),                                   //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                   //          .valid
		.src0_data          (rsp_demux_src0_data),                                    //          .data
		.src0_channel       (rsp_demux_src0_channel),                                 //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                           //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                              //          .endofpacket
	);

	system_mm_interconnect_5_rsp_demux rsp_demux_001 (
		.clk                (acl_iface_prime_clk_clk),                                //       clk.clk
		.reset              (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_002_src_ready),                                   //      sink.ready
		.sink_channel       (router_002_src_channel),                                 //          .channel
		.sink_data          (router_002_src_data),                                    //          .data
		.sink_startofpacket (router_002_src_startofpacket),                           //          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                             //          .endofpacket
		.sink_valid         (router_002_src_valid),                                   //          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                               //      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                               //          .valid
		.src0_data          (rsp_demux_001_src0_data),                                //          .data
		.src0_channel       (rsp_demux_001_src0_channel),                             //          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                       //          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)                          //          .endofpacket
	);

	system_mm_interconnect_5_rsp_mux rsp_mux (
		.clk                 (ext_clk_50_clk_clk),                                               //       clk.clk
		.reset               (acl_iface_prime_bus_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                                //       src.ready
		.src_valid           (rsp_mux_src_valid),                                                //          .valid
		.src_data            (rsp_mux_src_data),                                                 //          .data
		.src_channel         (rsp_mux_src_channel),                                              //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                        //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                          //          .endofpacket
		.sink0_ready         (async_fifo_002_out_ready),                                         //     sink0.ready
		.sink0_valid         (async_fifo_002_out_valid),                                         //          .valid
		.sink0_channel       (async_fifo_002_out_channel),                                       //          .channel
		.sink0_data          (async_fifo_002_out_data),                                          //          .data
		.sink0_startofpacket (async_fifo_002_out_startofpacket),                                 //          .startofpacket
		.sink0_endofpacket   (async_fifo_002_out_endofpacket),                                   //          .endofpacket
		.sink1_ready         (async_fifo_003_out_ready),                                         //     sink1.ready
		.sink1_valid         (async_fifo_003_out_valid),                                         //          .valid
		.sink1_channel       (async_fifo_003_out_channel),                                       //          .channel
		.sink1_data          (async_fifo_003_out_data),                                          //          .data
		.sink1_startofpacket (async_fifo_003_out_startofpacket),                                 //          .startofpacket
		.sink1_endofpacket   (async_fifo_003_out_endofpacket)                                    //          .endofpacket
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (76),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (2),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo (
		.in_clk            (ext_clk_50_clk_clk),                                                //        in_clk.clk
		.in_reset_n        (~acl_iface_prime_bus_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset_n
		.out_clk           (acl_iface_prime_clk_clk),                                           //       out_clk.clk
		.out_reset_n       (~float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset),           // out_clk_reset.reset_n
		.in_data           (cmd_demux_src0_data),                                               //            in.data
		.in_valid          (cmd_demux_src0_valid),                                              //              .valid
		.in_ready          (cmd_demux_src0_ready),                                              //              .ready
		.in_startofpacket  (cmd_demux_src0_startofpacket),                                      //              .startofpacket
		.in_endofpacket    (cmd_demux_src0_endofpacket),                                        //              .endofpacket
		.in_channel        (cmd_demux_src0_channel),                                            //              .channel
		.out_data          (async_fifo_out_data),                                               //           out.data
		.out_valid         (async_fifo_out_valid),                                              //              .valid
		.out_ready         (async_fifo_out_ready),                                              //              .ready
		.out_startofpacket (async_fifo_out_startofpacket),                                      //              .startofpacket
		.out_endofpacket   (async_fifo_out_endofpacket),                                        //              .endofpacket
		.out_channel       (async_fifo_out_channel),                                            //              .channel
		.in_csr_address    (1'b0),                                                              //   (terminated)
		.in_csr_read       (1'b0),                                                              //   (terminated)
		.in_csr_write      (1'b0),                                                              //   (terminated)
		.in_csr_readdata   (),                                                                  //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                              //   (terminated)
		.out_csr_address   (1'b0),                                                              //   (terminated)
		.out_csr_read      (1'b0),                                                              //   (terminated)
		.out_csr_write     (1'b0),                                                              //   (terminated)
		.out_csr_readdata  (),                                                                  //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000)                               //   (terminated)
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (76),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (2),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo_001 (
		.in_clk            (ext_clk_50_clk_clk),                                                //        in_clk.clk
		.in_reset_n        (~acl_iface_prime_bus_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset_n
		.out_clk           (acl_iface_prime_clk_clk),                                           //       out_clk.clk
		.out_reset_n       (~float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset),           // out_clk_reset.reset_n
		.in_data           (cmd_demux_src1_data),                                               //            in.data
		.in_valid          (cmd_demux_src1_valid),                                              //              .valid
		.in_ready          (cmd_demux_src1_ready),                                              //              .ready
		.in_startofpacket  (cmd_demux_src1_startofpacket),                                      //              .startofpacket
		.in_endofpacket    (cmd_demux_src1_endofpacket),                                        //              .endofpacket
		.in_channel        (cmd_demux_src1_channel),                                            //              .channel
		.out_data          (async_fifo_001_out_data),                                           //           out.data
		.out_valid         (async_fifo_001_out_valid),                                          //              .valid
		.out_ready         (async_fifo_001_out_ready),                                          //              .ready
		.out_startofpacket (async_fifo_001_out_startofpacket),                                  //              .startofpacket
		.out_endofpacket   (async_fifo_001_out_endofpacket),                                    //              .endofpacket
		.out_channel       (async_fifo_001_out_channel),                                        //              .channel
		.in_csr_address    (1'b0),                                                              //   (terminated)
		.in_csr_read       (1'b0),                                                              //   (terminated)
		.in_csr_write      (1'b0),                                                              //   (terminated)
		.in_csr_readdata   (),                                                                  //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                              //   (terminated)
		.out_csr_address   (1'b0),                                                              //   (terminated)
		.out_csr_read      (1'b0),                                                              //   (terminated)
		.out_csr_write     (1'b0),                                                              //   (terminated)
		.out_csr_readdata  (),                                                                  //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000)                               //   (terminated)
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (76),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (2),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo_002 (
		.in_clk            (acl_iface_prime_clk_clk),                                           //        in_clk.clk
		.in_reset_n        (~float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset),           //  in_clk_reset.reset_n
		.out_clk           (ext_clk_50_clk_clk),                                                //       out_clk.clk
		.out_reset_n       (~acl_iface_prime_bus_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset_n
		.in_data           (rsp_demux_src0_data),                                               //            in.data
		.in_valid          (rsp_demux_src0_valid),                                              //              .valid
		.in_ready          (rsp_demux_src0_ready),                                              //              .ready
		.in_startofpacket  (rsp_demux_src0_startofpacket),                                      //              .startofpacket
		.in_endofpacket    (rsp_demux_src0_endofpacket),                                        //              .endofpacket
		.in_channel        (rsp_demux_src0_channel),                                            //              .channel
		.out_data          (async_fifo_002_out_data),                                           //           out.data
		.out_valid         (async_fifo_002_out_valid),                                          //              .valid
		.out_ready         (async_fifo_002_out_ready),                                          //              .ready
		.out_startofpacket (async_fifo_002_out_startofpacket),                                  //              .startofpacket
		.out_endofpacket   (async_fifo_002_out_endofpacket),                                    //              .endofpacket
		.out_channel       (async_fifo_002_out_channel),                                        //              .channel
		.in_csr_address    (1'b0),                                                              //   (terminated)
		.in_csr_read       (1'b0),                                                              //   (terminated)
		.in_csr_write      (1'b0),                                                              //   (terminated)
		.in_csr_readdata   (),                                                                  //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                              //   (terminated)
		.out_csr_address   (1'b0),                                                              //   (terminated)
		.out_csr_read      (1'b0),                                                              //   (terminated)
		.out_csr_write     (1'b0),                                                              //   (terminated)
		.out_csr_readdata  (),                                                                  //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000)                               //   (terminated)
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (76),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (2),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo_003 (
		.in_clk            (acl_iface_prime_clk_clk),                                           //        in_clk.clk
		.in_reset_n        (~float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset),           //  in_clk_reset.reset_n
		.out_clk           (ext_clk_50_clk_clk),                                                //       out_clk.clk
		.out_reset_n       (~acl_iface_prime_bus_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset_n
		.in_data           (rsp_demux_001_src0_data),                                           //            in.data
		.in_valid          (rsp_demux_001_src0_valid),                                          //              .valid
		.in_ready          (rsp_demux_001_src0_ready),                                          //              .ready
		.in_startofpacket  (rsp_demux_001_src0_startofpacket),                                  //              .startofpacket
		.in_endofpacket    (rsp_demux_001_src0_endofpacket),                                    //              .endofpacket
		.in_channel        (rsp_demux_001_src0_channel),                                        //              .channel
		.out_data          (async_fifo_003_out_data),                                           //           out.data
		.out_valid         (async_fifo_003_out_valid),                                          //              .valid
		.out_ready         (async_fifo_003_out_ready),                                          //              .ready
		.out_startofpacket (async_fifo_003_out_startofpacket),                                  //              .startofpacket
		.out_endofpacket   (async_fifo_003_out_endofpacket),                                    //              .endofpacket
		.out_channel       (async_fifo_003_out_channel),                                        //              .channel
		.in_csr_address    (1'b0),                                                              //   (terminated)
		.in_csr_read       (1'b0),                                                              //   (terminated)
		.in_csr_write      (1'b0),                                                              //   (terminated)
		.in_csr_readdata   (),                                                                  //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                              //   (terminated)
		.out_csr_address   (1'b0),                                                              //   (terminated)
		.out_csr_read      (1'b0),                                                              //   (terminated)
		.out_csr_write     (1'b0),                                                              //   (terminated)
		.out_csr_readdata  (),                                                                  //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000)                               //   (terminated)
	);

	system_mm_interconnect_5_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (acl_iface_prime_clk_clk),                                // in_clk_0.clk
		.in_rst_0_reset (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (float_mult_smack_ctrl_bus_agent_rdata_fifo_out_data),    //     in_0.data
		.in_0_valid     (float_mult_smack_ctrl_bus_agent_rdata_fifo_out_valid),   //         .valid
		.in_0_ready     (float_mult_smack_ctrl_bus_agent_rdata_fifo_out_ready),   //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                           //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                          //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                          //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                           //         .error
	);

	system_mm_interconnect_5_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_001 (
		.in_clk_0_clk   (acl_iface_prime_clk_clk),                                // in_clk_0.clk
		.in_rst_0_reset (float_mult_smack_ctrl_rstn_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (float_add_smack_ctrl_bus_agent_rdata_fifo_out_data),     //     in_0.data
		.in_0_valid     (float_add_smack_ctrl_bus_agent_rdata_fifo_out_valid),    //         .valid
		.in_0_ready     (float_add_smack_ctrl_bus_agent_rdata_fifo_out_ready),    //         .ready
		.out_0_data     (avalon_st_adapter_001_out_0_data),                       //    out_0.data
		.out_0_valid    (avalon_st_adapter_001_out_0_valid),                      //         .valid
		.out_0_ready    (avalon_st_adapter_001_out_0_ready),                      //         .ready
		.out_0_error    (avalon_st_adapter_001_out_0_error)                       //         .error
	);

endmodule
