// system_mm_interconnect_2.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 15.1 193

`timescale 1 ps / 1 ps
module system_mm_interconnect_2 (
		input  wire        acl_iface_lsu_clk_clk,                                        //                                      acl_iface_lsu_clk.clk
		input  wire        avs_float_add_cra_cra_ring_reset_reset_bridge_in_reset_reset, // avs_float_add_cra_cra_ring_reset_reset_bridge_in_reset.reset
		input  wire [3:0]  avs_float_add_cra_cra_ring_cra_master_address,                //                  avs_float_add_cra_cra_ring_cra_master.address
		output wire        avs_float_add_cra_cra_ring_cra_master_waitrequest,            //                                                       .waitrequest
		input  wire [7:0]  avs_float_add_cra_cra_ring_cra_master_byteenable,             //                                                       .byteenable
		input  wire        avs_float_add_cra_cra_ring_cra_master_read,                   //                                                       .read
		output wire [63:0] avs_float_add_cra_cra_ring_cra_master_readdata,               //                                                       .readdata
		output wire        avs_float_add_cra_cra_ring_cra_master_readdatavalid,          //                                                       .readdatavalid
		input  wire        avs_float_add_cra_cra_ring_cra_master_write,                  //                                                       .write
		input  wire [63:0] avs_float_add_cra_cra_ring_cra_master_writedata,              //                                                       .writedata
		output wire [3:0]  float_add_mult_system_avs_float_add_cra_address,              //                float_add_mult_system_avs_float_add_cra.address
		output wire        float_add_mult_system_avs_float_add_cra_write,                //                                                       .write
		output wire        float_add_mult_system_avs_float_add_cra_read,                 //                                                       .read
		input  wire [63:0] float_add_mult_system_avs_float_add_cra_readdata,             //                                                       .readdata
		output wire [63:0] float_add_mult_system_avs_float_add_cra_writedata,            //                                                       .writedata
		output wire [7:0]  float_add_mult_system_avs_float_add_cra_byteenable,           //                                                       .byteenable
		input  wire        float_add_mult_system_avs_float_add_cra_readdatavalid         //                                                       .readdatavalid
	);

	wire         avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_waitrequest;   // float_add_mult_system_avs_float_add_cra_translator:uav_waitrequest -> avs_float_add_cra_cra_ring_cra_master_translator:uav_waitrequest
	wire  [63:0] avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_readdata;      // float_add_mult_system_avs_float_add_cra_translator:uav_readdata -> avs_float_add_cra_cra_ring_cra_master_translator:uav_readdata
	wire         avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_debugaccess;   // avs_float_add_cra_cra_ring_cra_master_translator:uav_debugaccess -> float_add_mult_system_avs_float_add_cra_translator:uav_debugaccess
	wire   [6:0] avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_address;       // avs_float_add_cra_cra_ring_cra_master_translator:uav_address -> float_add_mult_system_avs_float_add_cra_translator:uav_address
	wire         avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_read;          // avs_float_add_cra_cra_ring_cra_master_translator:uav_read -> float_add_mult_system_avs_float_add_cra_translator:uav_read
	wire   [7:0] avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_byteenable;    // avs_float_add_cra_cra_ring_cra_master_translator:uav_byteenable -> float_add_mult_system_avs_float_add_cra_translator:uav_byteenable
	wire         avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_readdatavalid; // float_add_mult_system_avs_float_add_cra_translator:uav_readdatavalid -> avs_float_add_cra_cra_ring_cra_master_translator:uav_readdatavalid
	wire         avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_lock;          // avs_float_add_cra_cra_ring_cra_master_translator:uav_lock -> float_add_mult_system_avs_float_add_cra_translator:uav_lock
	wire         avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_write;         // avs_float_add_cra_cra_ring_cra_master_translator:uav_write -> float_add_mult_system_avs_float_add_cra_translator:uav_write
	wire  [63:0] avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_writedata;     // avs_float_add_cra_cra_ring_cra_master_translator:uav_writedata -> float_add_mult_system_avs_float_add_cra_translator:uav_writedata
	wire   [3:0] avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_burstcount;    // avs_float_add_cra_cra_ring_cra_master_translator:uav_burstcount -> float_add_mult_system_avs_float_add_cra_translator:uav_burstcount

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (4),
		.AV_DATA_W                   (64),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (8),
		.UAV_ADDRESS_W               (7),
		.UAV_BURSTCOUNT_W            (4),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (8),
		.AV_ADDRESS_SYMBOLS          (0),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) avs_float_add_cra_cra_ring_cra_master_translator (
		.clk                    (acl_iface_lsu_clk_clk),                                                                    //                       clk.clk
		.reset                  (avs_float_add_cra_cra_ring_reset_reset_bridge_in_reset_reset),                             //                     reset.reset
		.uav_address            (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (avs_float_add_cra_cra_ring_cra_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (avs_float_add_cra_cra_ring_cra_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable          (avs_float_add_cra_cra_ring_cra_master_byteenable),                                         //                          .byteenable
		.av_read                (avs_float_add_cra_cra_ring_cra_master_read),                                               //                          .read
		.av_readdata            (avs_float_add_cra_cra_ring_cra_master_readdata),                                           //                          .readdata
		.av_readdatavalid       (avs_float_add_cra_cra_ring_cra_master_readdatavalid),                                      //                          .readdatavalid
		.av_write               (avs_float_add_cra_cra_ring_cra_master_write),                                              //                          .write
		.av_writedata           (avs_float_add_cra_cra_ring_cra_master_writedata),                                          //                          .writedata
		.av_burstcount          (1'b1),                                                                                     //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                                     //               (terminated)
		.av_begintransfer       (1'b0),                                                                                     //               (terminated)
		.av_chipselect          (1'b0),                                                                                     //               (terminated)
		.av_lock                (1'b0),                                                                                     //               (terminated)
		.av_debugaccess         (1'b0),                                                                                     //               (terminated)
		.uav_clken              (),                                                                                         //               (terminated)
		.av_clken               (1'b1),                                                                                     //               (terminated)
		.uav_response           (2'b00),                                                                                    //               (terminated)
		.av_response            (),                                                                                         //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                                     //               (terminated)
		.av_writeresponsevalid  ()                                                                                          //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (4),
		.AV_DATA_W                      (64),
		.UAV_DATA_W                     (64),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (8),
		.UAV_BYTEENABLE_W               (8),
		.UAV_ADDRESS_W                  (7),
		.UAV_BURSTCOUNT_W               (4),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (8),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) float_add_mult_system_avs_float_add_cra_translator (
		.clk                    (acl_iface_lsu_clk_clk),                                                                    //                      clk.clk
		.reset                  (avs_float_add_cra_cra_ring_reset_reset_bridge_in_reset_reset),                             //                    reset.reset
		.uav_address            (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_burstcount),    //                         .burstcount
		.uav_read               (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_read),          //                         .read
		.uav_write              (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_write),         //                         .write
		.uav_waitrequest        (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_byteenable),    //                         .byteenable
		.uav_readdata           (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_readdata),      //                         .readdata
		.uav_writedata          (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_writedata),     //                         .writedata
		.uav_lock               (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_lock),          //                         .lock
		.uav_debugaccess        (avs_float_add_cra_cra_ring_cra_master_translator_avalon_universal_master_0_debugaccess),   //                         .debugaccess
		.av_address             (float_add_mult_system_avs_float_add_cra_address),                                          //      avalon_anti_slave_0.address
		.av_write               (float_add_mult_system_avs_float_add_cra_write),                                            //                         .write
		.av_read                (float_add_mult_system_avs_float_add_cra_read),                                             //                         .read
		.av_readdata            (float_add_mult_system_avs_float_add_cra_readdata),                                         //                         .readdata
		.av_writedata           (float_add_mult_system_avs_float_add_cra_writedata),                                        //                         .writedata
		.av_byteenable          (float_add_mult_system_avs_float_add_cra_byteenable),                                       //                         .byteenable
		.av_readdatavalid       (float_add_mult_system_avs_float_add_cra_readdatavalid),                                    //                         .readdatavalid
		.av_begintransfer       (),                                                                                         //              (terminated)
		.av_beginbursttransfer  (),                                                                                         //              (terminated)
		.av_burstcount          (),                                                                                         //              (terminated)
		.av_waitrequest         (1'b0),                                                                                     //              (terminated)
		.av_writebyteenable     (),                                                                                         //              (terminated)
		.av_lock                (),                                                                                         //              (terminated)
		.av_chipselect          (),                                                                                         //              (terminated)
		.av_clken               (),                                                                                         //              (terminated)
		.uav_clken              (1'b0),                                                                                     //              (terminated)
		.av_debugaccess         (),                                                                                         //              (terminated)
		.av_outputenable        (),                                                                                         //              (terminated)
		.uav_response           (),                                                                                         //              (terminated)
		.av_response            (2'b00),                                                                                    //              (terminated)
		.uav_writeresponsevalid (),                                                                                         //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                                                      //              (terminated)
	);

endmodule
