-- megafunction wizard: %ALTMULT_COMPLEX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altmult_complex 

-- ============================================================
-- File Name: c_mult.vhd
-- Megafunction Name(s):
-- 			altmult_complex
--
-- Simulation Library Files(s):
-- 			
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 22.1std.0 Build 915 10/25/2022 SC Lite Edition
-- ************************************************************


--Copyright (C) 2022  Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions 
--and other software and tools, and any partner logic 
--functions, and any output files from any of the foregoing 
--(including device programming or simulation files), and any 
--associated documentation or information are expressly subject 
--to the terms and conditions of the Intel Program License 
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors.  Please
--refer to the applicable agreement for further details, at
--https://fpgasoftware.intel.com/eula.


--altmult_complex CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" IMPLEMENTATION_STYLE="AUTO" PIPELINE=4 REPRESENTATION_A="SIGNED" REPRESENTATION_B="SIGNED" WIDTH_A=18 WIDTH_B=18 WIDTH_RESULT=36 clock dataa_imag dataa_real datab_imag datab_real ena result_imag result_real
--VERSION_BEGIN 22.1 cbx_alt_ded_mult_y 2022:10:25:15:36:38:SC cbx_altera_mult_add 2022:10:25:15:36:37:SC cbx_altera_mult_add_rtl 2022:10:25:15:36:36:SC cbx_altmult_add 2022:10:25:15:36:38:SC cbx_altmult_complex 2022:10:25:15:36:38:SC cbx_arriav 2022:10:25:15:36:36:SC cbx_cycloneii 2022:10:25:15:36:38:SC cbx_lpm_add_sub 2022:10:25:15:36:38:SC cbx_lpm_compare 2022:10:25:15:36:38:SC cbx_lpm_mult 2022:10:25:15:36:38:SC cbx_mgl 2022:10:25:15:36:55:SC cbx_nadder 2022:10:25:15:36:38:SC cbx_padd 2022:10:25:15:36:38:SC cbx_parallel_add 2022:10:25:15:36:38:SC cbx_stratix 2022:10:25:15:36:38:SC cbx_stratixii 2022:10:25:15:36:38:SC cbx_stratixv 2022:10:25:15:36:38:SC cbx_util_mgl 2022:10:25:15:36:38:SC  VERSION_END

 LIBRARY ieee;
 USE ieee.numeric_std.all;

--synthesis_resources = 
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;

 ENTITY  c_mult_altmult_complex_kcp IS 
	 PORT 
	 ( 
		 clock	:	IN  STD_LOGIC := '0';
		 dataa_imag	:	IN  STD_LOGIC_VECTOR (17 DOWNTO 0);
		 dataa_real	:	IN  STD_LOGIC_VECTOR (17 DOWNTO 0);
		 datab_imag	:	IN  STD_LOGIC_VECTOR (17 DOWNTO 0);
		 datab_real	:	IN  STD_LOGIC_VECTOR (17 DOWNTO 0);
		 ena	:	IN  STD_LOGIC := '1';
		 result_imag	:	OUT  STD_LOGIC_VECTOR (35 DOWNTO 0);
		 result_real	:	OUT  STD_LOGIC_VECTOR (35 DOWNTO 0)
	 ); 
 END c_mult_altmult_complex_kcp;

 ARCHITECTURE RTL OF c_mult_altmult_complex_kcp IS

	 SIGNAL	datab_real_input_reg	:	STD_LOGIC_VECTOR(17 DOWNTO 0)
	 -- synopsys translate_off
	 := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	datab_imag_input_reg	:	STD_LOGIC_VECTOR(17 DOWNTO 0)
	 -- synopsys translate_off
	 := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	dataa_real_input_reg	:	STD_LOGIC_VECTOR(17 DOWNTO 0)
	 -- synopsys translate_off
	 := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	dataa_imag_input_reg	:	STD_LOGIC_VECTOR(17 DOWNTO 0)
	 -- synopsys translate_off
	 := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	result_real_output_reg	:	STD_LOGIC_VECTOR(35 DOWNTO 0)
	 -- synopsys translate_off
	 := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	result_imag_output_reg	:	STD_LOGIC_VECTOR(35 DOWNTO 0)
	 -- synopsys translate_off
	 := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	result_real_extra0_reg	:	STD_LOGIC_VECTOR(35 DOWNTO 0)
	 -- synopsys translate_off
	 := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	result_imag_extra0_reg	:	STD_LOGIC_VECTOR(35 DOWNTO 0)
	 -- synopsys translate_off
	 := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	result_real_extra1_reg	:	STD_LOGIC_VECTOR(35 DOWNTO 0)
	 -- synopsys translate_off
	 := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	result_imag_extra1_reg	:	STD_LOGIC_VECTOR(35 DOWNTO 0)
	 -- synopsys translate_off
	 := (OTHERS => '0')
	 -- synopsys translate_on
	 ;
	 SIGNAL	datab_real_wire	:	SIGNED(17 DOWNTO 0);
	 SIGNAL	datab_imag_wire	:	SIGNED(17 DOWNTO 0);
	 SIGNAL	dataa_real_wire	:	SIGNED(17 DOWNTO 0);
	 SIGNAL	dataa_imag_wire	:	SIGNED(17 DOWNTO 0);
	 SIGNAL	result_real_wire	:	SIGNED(36 DOWNTO 0);
	 SIGNAL	result_imag_wire	:	SIGNED(36 DOWNTO 0);
	 SIGNAL	a1_wire	:	SIGNED(18 DOWNTO 0);
	 SIGNAL	a2_wire	:	SIGNED(18 DOWNTO 0);
	 SIGNAL	a3_wire	:	SIGNED(18 DOWNTO 0);
	 SIGNAL	p1_wire	:	SIGNED(36 DOWNTO 0);
	 SIGNAL	p2_wire	:	SIGNED(36 DOWNTO 0);
	 SIGNAL	p3_wire	:	SIGNED(36 DOWNTO 0);

 BEGIN

	PROCESS (clock)
	BEGIN
		IF (clock = '1' AND clock'event) THEN
			IF (ena = '1') THEN
				datab_real_input_reg <= STD_LOGIC_VECTOR(datab_real);
		END IF;
	END PROCESS;
	PROCESS (clock)
	BEGIN
		IF (clock = '1' AND clock'event) THEN
			IF (ena = '1') THEN
				datab_imag_input_reg <= STD_LOGIC_VECTOR(datab_imag);
		END IF;
	END PROCESS;
	PROCESS (clock)
	BEGIN
		IF (clock = '1' AND clock'event) THEN
			IF (ena = '1') THEN
				dataa_real_input_reg <= STD_LOGIC_VECTOR(dataa_real);
		END IF;
	END PROCESS;
	PROCESS (clock)
	BEGIN
		IF (clock = '1' AND clock'event) THEN
			IF (ena = '1') THEN
				dataa_imag_input_reg <= STD_LOGIC_VECTOR(dataa_imag);
		END IF;
	END PROCESS;
	PROCESS (clock)
	BEGIN
		IF (clock = '1' AND clock'event) THEN
			IF (ena = '1') THEN
				result_real_output_reg <= result_real_extra1_reg;
		END IF;
	END PROCESS;
	PROCESS (clock)
	BEGIN
		IF (clock = '1' AND clock'event) THEN
			IF (ena = '1') THEN
				result_imag_output_reg <= result_imag_extra1_reg;
		END IF;
	END PROCESS;
	PROCESS (clock)
	BEGIN
		IF (clock = '1' AND clock'event) THEN
			IF (ena = '1') THEN
				result_real_extra0_reg <= STD_LOGIC_VECTOR(result_real_wire(35 DOWNTO 0));
		END IF;
	END PROCESS;
	PROCESS (clock)
	BEGIN
		IF (clock = '1' AND clock'event) THEN
			IF (ena = '1') THEN
				result_imag_extra0_reg <= STD_LOGIC_VECTOR(result_imag_wire(35 DOWNTO 0));
		END IF;
	END PROCESS;
	PROCESS (clock)
	BEGIN
		IF (clock = '1' AND clock'event) THEN
			IF (ena = '1') THEN
				result_real_extra1_reg <= result_real_extra0_reg;
		END IF;
	END PROCESS;
	PROCESS (clock)
	BEGIN
		IF (clock = '1' AND clock'event) THEN
			IF (ena = '1') THEN
				result_imag_extra1_reg <= result_imag_extra0_reg;
		END IF;
	END PROCESS;

	datab_real_wire <= SIGNED(datab_real_input_reg);
	datab_imag_wire <= SIGNED(datab_imag_input_reg);
	dataa_real_wire <= SIGNED(dataa_real_input_reg);
	dataa_imag_wire <= SIGNED(dataa_imag_input_reg);
	a1_wire <= (datab_real_wire(17) & datab_real_wire) - (datab_imag_wire(17) & datab_imag_wire);
	p1_wire <= a1_wire * dataa_imag_wire;
	a2_wire <= (dataa_real_wire(17) & dataa_real_wire) - (dataa_imag_wire(17) & dataa_imag_wire);
	p2_wire <= a2_wire * datab_real_wire;
	a3_wire <= (dataa_real_wire(17) & dataa_real_wire) + (dataa_imag_wire(17) & dataa_imag_wire);
	p3_wire <= a3_wire * datab_imag_wire;
	result_real_wire <= p1_wire + p2_wire;
	result_imag_wire <= p1_wire + p3_wire;
	result_real <= (result_real_output_reg);
	result_imag <= (result_imag_output_reg);


 END RTL; --c_mult_altmult_complex_kcp
--VALID FILE


LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY c_mult IS
	PORT
	(
		clock		: IN STD_LOGIC ;
		dataa_imag		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
		dataa_real		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
		datab_imag		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
		datab_real		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
		ena		: IN STD_LOGIC ;
		result_imag		: OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
		result_real		: OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
	);
END c_mult;


ARCHITECTURE RTL OF c_mult IS

	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (35 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (35 DOWNTO 0);



	COMPONENT c_mult_altmult_complex_kcp
	PORT (
			clock	: IN STD_LOGIC ;
			dataa_imag	: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
			dataa_real	: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
			datab_imag	: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
			datab_real	: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
			ena	: IN STD_LOGIC ;
			result_imag	: OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
			result_real	: OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
	);
	END COMPONENT;

BEGIN
	result_imag    <= sub_wire0(35 DOWNTO 0);
	result_real    <= sub_wire1(35 DOWNTO 0);

	c_mult_altmult_complex_kcp_component : c_mult_altmult_complex_kcp
	PORT MAP (
		clock => clock,
		dataa_imag => dataa_imag,
		dataa_real => dataa_real,
		datab_imag => datab_imag,
		datab_real => datab_real,
		ena => ena,
		result_imag => sub_wire0,
		result_real => sub_wire1
	);



END RTL;

-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: IMPLEMENTATION_STYLE STRING "AUTO"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "4"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "36"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa_imag 0 0 18 0 INPUT NODEFVAL "dataa_imag[17..0]"
-- Retrieval info: USED_PORT: dataa_real 0 0 18 0 INPUT NODEFVAL "dataa_real[17..0]"
-- Retrieval info: USED_PORT: datab_imag 0 0 18 0 INPUT NODEFVAL "datab_imag[17..0]"
-- Retrieval info: USED_PORT: datab_real 0 0 18 0 INPUT NODEFVAL "datab_real[17..0]"
-- Retrieval info: USED_PORT: ena 0 0 0 0 INPUT NODEFVAL "ena"
-- Retrieval info: USED_PORT: result_imag 0 0 36 0 OUTPUT NODEFVAL "result_imag[35..0]"
-- Retrieval info: USED_PORT: result_real 0 0 36 0 OUTPUT NODEFVAL "result_real[35..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa_imag 0 0 18 0 dataa_imag 0 0 18 0
-- Retrieval info: CONNECT: @dataa_real 0 0 18 0 dataa_real 0 0 18 0
-- Retrieval info: CONNECT: @datab_imag 0 0 18 0 datab_imag 0 0 18 0
-- Retrieval info: CONNECT: @datab_real 0 0 18 0 datab_real 0 0 18 0
-- Retrieval info: CONNECT: @ena 0 0 0 0 ena 0 0 0 0
-- Retrieval info: CONNECT: result_imag 0 0 36 0 @result_imag 0 0 36 0
-- Retrieval info: CONNECT: result_real 0 0 36 0 @result_real 0 0 36 0