// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// files any  of the foregoing (including  device programming  or simulation
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// SystemVerilog created from and_func_function_wrapper
// Created for function/kernel and_func
// SystemVerilog created on Wed Oct 30 16:13:02 2024


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module and_func_function_wrapper (
    input wire [0:0] A,
    input wire [0:0] B,
    input wire [15:0] avst_iord_bl_call_and_func_data,
    input wire [0:0] avst_iord_bl_call_and_func_valid,
    input wire [0:0] avst_iowr_bl_return_and_func_almostfull,
    input wire [0:0] avst_iowr_bl_return_and_func_ready,
    input wire [0:0] stall,
    input wire [0:0] stall_in,
    input wire [0:0] start,
    input wire [0:0] valid_in,
    output wire [0:0] avst_iord_bl_call_and_func_almost_full,
    output wire [0:0] avst_iord_bl_call_and_func_ready,
    output wire [0:0] avst_iowr_bl_return_and_func_data,
    output wire [0:0] avst_iowr_bl_return_and_func_valid,
    output wire [0:0] busy,
    output wire [0:0] done,
    output wire [0:0] returndata,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    wire [0:0] and_func_function_out_iord_bl_call_and_func_o_fifoalmost_full;
    wire [0:0] and_func_function_out_iord_bl_call_and_func_o_fifoready;
    wire [0:0] and_func_function_out_iowr_bl_return_and_func_o_fifodata;
    wire [0:0] and_func_function_out_iowr_bl_return_and_func_o_fifovalid;
    wire [0:0] and_func_function_out_stall_out;
    wire [0:0] busy_and_q;
    wire [0:0] busy_or_q;
    wire [63:0] call_const_q;
    wire [15:0] implicit_input_q;
    wire [6:0] implicit_input_pad_const_1_q;
    wire [0:0] not_ready_q;
    wire [0:0] not_stall_q;
    wire [0:0] pos_reset_q;
    wire [0:0] start_mask_and_q;
    wire [0:0] start_pulse_out_o_valid;
    wire [0:0] wait_pulse_extender_inst_out_o_sclrn;
    reg [0:0] rst_sync_rst_sclrn;


    // wait_pulse_extender_inst(BLACKBOX,34)
    and_func_wait_pulse_extender_inst thewait_pulse_extender_inst (
        .out_o_sclrn(wait_pulse_extender_inst_out_o_sclrn),
        .clock(clock),
        .resetn(rst_sync_rst_sclrn[0])
    );

    // start_pulse(BLACKBOX,33)
    and_func_start_pulse thestart_pulse (
        .in_i_stall(and_func_function_out_stall_out),
        .in_i_valid(wait_pulse_extender_inst_out_o_sclrn),
        .out_o_valid(start_pulse_out_o_valid),
        .clock(clock),
        .resetn(rst_sync_rst_sclrn[0])
    );

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // not_stall(LOGICAL,21)
    assign not_stall_q = ~ (stall);

    // start_mask_and(LOGICAL,32)
    assign start_mask_and_q = start & wait_pulse_extender_inst_out_o_sclrn;

    // implicit_input_pad_const_1(CONSTANT,8)
    assign implicit_input_pad_const_1_q = $unsigned(7'b0000000);

    // implicit_input(BITJOIN,7)
    assign implicit_input_q = {implicit_input_pad_const_1_q, B, implicit_input_pad_const_1_q, A};

    // call_const(CONSTANT,5)
    assign call_const_q = $unsigned(64'b0000000000000000000000000000000000000000000000000000000000000000);

    // and_func_function(BLACKBOX,2)
    and_func_function theand_func_function (
        .in_arg_call(call_const_q),
        .in_arg_return(call_const_q),
        .in_iord_bl_call_and_func_i_fifodata(implicit_input_q),
        .in_iord_bl_call_and_func_i_fifovalid(start_mask_and_q),
        .in_iowr_bl_return_and_func_i_fifoready(not_stall_q),
        .in_stall_in(GND_q),
        .in_valid_in(start_pulse_out_o_valid),
        .out_iord_bl_call_and_func_o_fifoalmost_full(and_func_function_out_iord_bl_call_and_func_o_fifoalmost_full),
        .out_iord_bl_call_and_func_o_fifoready(and_func_function_out_iord_bl_call_and_func_o_fifoready),
        .out_iowr_bl_return_and_func_o_fifodata(and_func_function_out_iowr_bl_return_and_func_o_fifodata),
        .out_iowr_bl_return_and_func_o_fifovalid(and_func_function_out_iowr_bl_return_and_func_o_fifovalid),
        .out_stall_out(and_func_function_out_stall_out),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // avst_iord_bl_call_and_func_almost_full(GPOUT,22)
    assign avst_iord_bl_call_and_func_almost_full = and_func_function_out_iord_bl_call_and_func_o_fifoalmost_full;

    // avst_iord_bl_call_and_func_ready(GPOUT,23)
    assign avst_iord_bl_call_and_func_ready = and_func_function_out_iord_bl_call_and_func_o_fifoready;

    // avst_iowr_bl_return_and_func_data(GPOUT,24)
    assign avst_iowr_bl_return_and_func_data = and_func_function_out_iowr_bl_return_and_func_o_fifodata;

    // avst_iowr_bl_return_and_func_valid(GPOUT,25)
    assign avst_iowr_bl_return_and_func_valid = and_func_function_out_iowr_bl_return_and_func_o_fifovalid;

    // not_ready(LOGICAL,20)
    assign not_ready_q = ~ (and_func_function_out_iord_bl_call_and_func_o_fifoready);

    // busy_and(LOGICAL,3)
    assign busy_and_q = not_ready_q & start;

    // pos_reset(LOGICAL,29)
    assign pos_reset_q = ~ (wait_pulse_extender_inst_out_o_sclrn);

    // busy_or(LOGICAL,4)
    assign busy_or_q = pos_reset_q | busy_and_q;

    // busy(GPOUT,26)
    assign busy = busy_or_q;

    // done(GPOUT,27)
    assign done = and_func_function_out_iowr_bl_return_and_func_o_fifovalid;

    // returndata(GPOUT,28)
    assign returndata = and_func_function_out_iowr_bl_return_and_func_o_fifodata;

    // rst_sync(RESETSYNC,35)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
