package require -exact qsys 15.0
set_module_property NAME and_func_internal
set_module_property VERSION 1.0
set_module_property INTERNAL true
set_module_property GROUP HLS
set_module_property DISPLAY_NAME and_func_internal
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property SUPPORTED_DEVICE_FAMILIES {"Agilex"}
set_module_assignment hls.cosim.name {\3fand_func@@YA_N_N0@Z}
set_module_assignment hls.compressed.name {and_func}

#### Synthesis fileset
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL and_func_internal
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file "acl_reset_handler.sv" SYSTEM_VERILOG PATH "ip/acl_reset_handler.sv"
add_fileset_file "dspba_library_ver.sv" SYSTEM_VERILOG PATH "windows64/lib/hld_backend/Libraries/sv/base/dspba_library_ver.sv"
add_fileset_file "acl_ecc_pkg.sv" SYSTEM_VERILOG PATH "ip/acl_ecc_pkg.sv"
add_fileset_file "acl_data_fifo.v" SYSTEM_VERILOG PATH "ip/acl_data_fifo.v"
add_fileset_file "acl_fifo.v" SYSTEM_VERILOG PATH "ip/acl_fifo.v"
add_fileset_file "acl_altera_syncram_wrapped.sv" SYSTEM_VERILOG PATH "ip/acl_altera_syncram_wrapped.sv"
add_fileset_file "acl_scfifo_wrapped.sv" SYSTEM_VERILOG PATH "ip/acl_scfifo_wrapped.sv"
add_fileset_file "acl_ecc_decoder.sv" SYSTEM_VERILOG PATH "ip/acl_ecc_decoder.sv"
add_fileset_file "acl_ecc_encoder.sv" SYSTEM_VERILOG PATH "ip/acl_ecc_encoder.sv"
add_fileset_file "acl_ll_fifo.v" SYSTEM_VERILOG PATH "ip/acl_ll_fifo.v"
add_fileset_file "acl_ll_ram_fifo.v" SYSTEM_VERILOG PATH "ip/acl_ll_ram_fifo.v"
add_fileset_file "acl_valid_fifo_counter.v" SYSTEM_VERILOG PATH "ip/acl_valid_fifo_counter.v"
add_fileset_file "acl_dspba_valid_fifo_counter.v" SYSTEM_VERILOG PATH "ip/acl_dspba_valid_fifo_counter.v"
add_fileset_file "acl_staging_reg.v" SYSTEM_VERILOG PATH "ip/acl_staging_reg.v"
add_fileset_file "hld_fifo.sv" SYSTEM_VERILOG PATH "ip/hld_fifo.sv"
add_fileset_file "acl_mid_speed_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_mid_speed_fifo.sv"
add_fileset_file "acl_latency_one_ram_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_latency_one_ram_fifo.sv"
add_fileset_file "acl_latency_zero_ram_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_latency_zero_ram_fifo.sv"
add_fileset_file "hld_fifo_zero_width.sv" SYSTEM_VERILOG PATH "ip/hld_fifo_zero_width.sv"
add_fileset_file "acl_high_speed_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_high_speed_fifo.sv"
add_fileset_file "acl_low_latency_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_low_latency_fifo.sv"
add_fileset_file "acl_zero_latency_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_zero_latency_fifo.sv"
add_fileset_file "acl_fanout_pipeline.sv" SYSTEM_VERILOG PATH "ip/acl_fanout_pipeline.sv"
add_fileset_file "acl_std_synchronizer_nocut.v" SYSTEM_VERILOG PATH "ip/acl_std_synchronizer_nocut.v"
add_fileset_file "acl_tessellated_incr_decr_threshold.sv" SYSTEM_VERILOG PATH "ip/acl_tessellated_incr_decr_threshold.sv"
add_fileset_file "acl_tessellated_incr_lookahead.sv" SYSTEM_VERILOG PATH "ip/acl_tessellated_incr_lookahead.sv"
add_fileset_file "acl_lfsr.sv" SYSTEM_VERILOG PATH "ip/acl_lfsr.sv"
add_fileset_file "acl_mlab_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_mlab_fifo.sv"
add_fileset_file "acl_parameter_assert.svh" SYSTEM_VERILOG PATH "ip/acl_parameter_assert.svh"
add_fileset_file "acl_pop_stall_latency.sv" SYSTEM_VERILOG PATH "ip/acl_pop_stall_latency.sv"
add_fileset_file "acl_sync.sv" SYSTEM_VERILOG PATH "ip/acl_sync.sv"
add_fileset_file "acl_desync.sv" SYSTEM_VERILOG PATH "ip/acl_desync.sv"
add_fileset_file "acl_push_stall_latency.sv" SYSTEM_VERILOG PATH "ip/acl_push_stall_latency.sv"
add_fileset_file "acl_dspba_buffer.v" SYSTEM_VERILOG PATH "ip/acl_dspba_buffer.v"
add_fileset_file "acl_fast_pipeline.v" SYSTEM_VERILOG PATH "ip/acl_fast_pipeline.v"
add_fileset_file "acl_push.v" SYSTEM_VERILOG PATH "ip/acl_push.v"
add_fileset_file "acl_token_fifo_counter.v" SYSTEM_VERILOG PATH "ip/acl_token_fifo_counter.v"
add_fileset_file "acl_full_detector.v" SYSTEM_VERILOG PATH "ip/acl_full_detector.v"
add_fileset_file "acl_tessellated_incr_decr_decr.sv" SYSTEM_VERILOG PATH "ip/acl_tessellated_incr_decr_decr.sv"
add_fileset_file "acl_loop_admit.sv" SYSTEM_VERILOG PATH "ip/acl_loop_admit.sv"
add_fileset_file "acl_shift_register_no_reset_dont_merge.sv" SYSTEM_VERILOG PATH "ip/acl_shift_register_no_reset_dont_merge.sv"
add_fileset_file "hld_memory_depth_quantization_pkg.sv" SYSTEM_VERILOG PATH "ip/hld_memory_depth_quantization_pkg.sv"
add_fileset_file "hld_iord.sv" SYSTEM_VERILOG PATH "ip/hld_iord.sv"
add_fileset_file "hld_iord_stall_latency.sv" SYSTEM_VERILOG PATH "ip/hld_iord_stall_latency.sv"
add_fileset_file "hld_iord_stall_valid.sv" SYSTEM_VERILOG PATH "ip/hld_iord_stall_valid.sv"
add_fileset_file "acl_shift_register_no_reset.sv" SYSTEM_VERILOG PATH "ip/acl_shift_register_no_reset.sv"
add_fileset_file "hld_iowr.sv" SYSTEM_VERILOG PATH "ip/hld_iowr.sv"
add_fileset_file "hld_iowr_stall_latency.sv" SYSTEM_VERILOG PATH "ip/hld_iowr_stall_latency.sv"
add_fileset_file "hld_iowr_stall_valid.sv" SYSTEM_VERILOG PATH "ip/hld_iowr_stall_valid.sv"
add_fileset_file "hld_loop_profiler.sv" SYSTEM_VERILOG PATH "ip/hld_loop_profiler.sv"
add_fileset_file "hld_sim_latency_tracker.sv" SYSTEM_VERILOG PATH "ip/hld_sim_latency_tracker.sv"
add_fileset_file "and_func_function_wrapper.sv" SYSTEM_VERILOG PATH "ip/and_func_function_wrapper.sv"
add_fileset_file "and_func_function.sv" SYSTEM_VERILOG PATH "ip/and_func_function.sv"
add_fileset_file "and_func_bb_B0_runOnce.sv" SYSTEM_VERILOG PATH "ip/and_func_bb_B0_runOnce.sv"
add_fileset_file "and_func_B0_runOnce_branch.sv" SYSTEM_VERILOG PATH "ip/and_func_B0_runOnce_branch.sv"
add_fileset_file "and_func_B0_runOnce_merge.sv" SYSTEM_VERILOG PATH "ip/and_func_B0_runOnce_merge.sv"
add_fileset_file "and_func_B0_runOnce_merge_storage.sv" SYSTEM_VERILOG PATH "ip/and_func_B0_runOnce_merge_storage.sv"
add_fileset_file "and_func_bb_B0_runOnce_stall_region.sv" SYSTEM_VERILOG PATH "ip/and_func_bb_B0_runOnce_stall_region.sv"
add_fileset_file "and_func_i_llvm_fpga_pop_token_i1_wt_limpop_0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_pop_token_i1_wt_limpop_0.sv"
add_fileset_file "and_func_i_llvm_fpga_push_token_i1_wt_limpush_0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_push_token_i1_wt_limpush_0.sv"
add_fileset_file "and_func_bb_B1_start.sv" SYSTEM_VERILOG PATH "ip/and_func_bb_B1_start.sv"
add_fileset_file "and_func_B1_start_branch.sv" SYSTEM_VERILOG PATH "ip/and_func_B1_start_branch.sv"
add_fileset_file "and_func_B1_start_merge.sv" SYSTEM_VERILOG PATH "ip/and_func_B1_start_merge.sv"
add_fileset_file "and_func_B1_start_merge_storage.sv" SYSTEM_VERILOG PATH "ip/and_func_B1_start_merge_storage.sv"
add_fileset_file "and_func_bb_B1_start_stall_region.sv" SYSTEM_VERILOG PATH "ip/and_func_bb_B1_start_stall_region.sv"
add_fileset_file "and_func_i_iord_bl_call_unnamed_and_func1_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_iord_bl_call_unnamed_and_func1_and_func0.sv"
add_fileset_file "and_func_i_sfc_s_c0_in_wt_entry_s_c0_enter1_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_sfc_s_c0_in_wt_entry_s_c0_enter1_and_func0.sv"
add_fileset_file "and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_s_c0_exit_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_s_c0_exit_and_func0.sv"
add_fileset_file "and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_and_func1_data_fifo.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_and_func1_data_fifo.sv"
add_fileset_file "and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_func1_full_detector.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_func1_full_detector.sv"
add_fileset_file "and_func_i_sfc_logic_s_c0_in_wt_entry_s_c0_enter1_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_sfc_logic_s_c0_in_wt_entry_s_c0_enter1_and_func0.sv"
add_fileset_file "and_func_i_llvm_fpga_dummy_thread_b1_start_dummy_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_dummy_thread_b1_start_dummy_and_func0.sv"
add_fileset_file "and_func_i_llvm_fpga_forked_b1_start_forked_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_forked_b1_start_forked_and_func0.sv"
add_fileset_file "and_func_i_llvm_fpga_pipeline_keep_going_0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_pipeline_keep_going_0.sv"
add_fileset_file "and_func_i_llvm_fpga_push_i1_notexitcond_0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_push_i1_notexitcond_0.sv"
add_fileset_file "and_func_i_sfc_s_c1_in_wt_entry_s_c1_enter_and_func3.sv" SYSTEM_VERILOG PATH "ip/and_func_i_sfc_s_c1_in_wt_entry_s_c1_enter_and_func3.sv"
add_fileset_file "and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_s_c1_exit_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_s_c1_exit_and_func0.sv"
add_fileset_file "and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_and_func1_data_fifo.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_and_func1_data_fifo.sv"
add_fileset_file "and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_func1_full_detector.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_func1_full_detector.sv"
add_fileset_file "and_func_i_sfc_logic_s_c1_in_wt_entry_s_c1_enter_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_sfc_logic_s_c1_in_wt_entry_s_c1_enter_and_func0.sv"
add_fileset_file "and_func_i_iowr_bl_return_unnamed_and_func3_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_iowr_bl_return_unnamed_and_func3_and_func0.sv"
add_fileset_file "and_func_start_pulse.sv" SYSTEM_VERILOG PATH "ip/and_func_start_pulse.sv"
add_fileset_file "and_func_wait_pulse_extender_inst.sv" SYSTEM_VERILOG PATH "ip/and_func_wait_pulse_extender_inst.sv"
add_fileset_file "and_func_internal.v" SYSTEM_VERILOG PATH "and_func_internal.v"

#### Simulation fileset
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL and_func_internal
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file "acl_reset_handler.sv" SYSTEM_VERILOG PATH "ip/acl_reset_handler.sv"
add_fileset_file "dspba_library_ver.sv" SYSTEM_VERILOG PATH "windows64/lib/hld_backend/Libraries/sv/base/dspba_library_ver.sv"
add_fileset_file "acl_ecc_pkg.sv" SYSTEM_VERILOG PATH "ip/acl_ecc_pkg.sv"
add_fileset_file "acl_data_fifo.v" SYSTEM_VERILOG PATH "ip/acl_data_fifo.v"
add_fileset_file "acl_fifo.v" SYSTEM_VERILOG PATH "ip/acl_fifo.v"
add_fileset_file "acl_altera_syncram_wrapped.sv" SYSTEM_VERILOG PATH "ip/acl_altera_syncram_wrapped.sv"
add_fileset_file "acl_scfifo_wrapped.sv" SYSTEM_VERILOG PATH "ip/acl_scfifo_wrapped.sv"
add_fileset_file "acl_ecc_decoder.sv" SYSTEM_VERILOG PATH "ip/acl_ecc_decoder.sv"
add_fileset_file "acl_ecc_encoder.sv" SYSTEM_VERILOG PATH "ip/acl_ecc_encoder.sv"
add_fileset_file "acl_ll_fifo.v" SYSTEM_VERILOG PATH "ip/acl_ll_fifo.v"
add_fileset_file "acl_ll_ram_fifo.v" SYSTEM_VERILOG PATH "ip/acl_ll_ram_fifo.v"
add_fileset_file "acl_valid_fifo_counter.v" SYSTEM_VERILOG PATH "ip/acl_valid_fifo_counter.v"
add_fileset_file "acl_dspba_valid_fifo_counter.v" SYSTEM_VERILOG PATH "ip/acl_dspba_valid_fifo_counter.v"
add_fileset_file "acl_staging_reg.v" SYSTEM_VERILOG PATH "ip/acl_staging_reg.v"
add_fileset_file "hld_fifo.sv" SYSTEM_VERILOG PATH "ip/hld_fifo.sv"
add_fileset_file "acl_mid_speed_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_mid_speed_fifo.sv"
add_fileset_file "acl_latency_one_ram_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_latency_one_ram_fifo.sv"
add_fileset_file "acl_latency_zero_ram_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_latency_zero_ram_fifo.sv"
add_fileset_file "hld_fifo_zero_width.sv" SYSTEM_VERILOG PATH "ip/hld_fifo_zero_width.sv"
add_fileset_file "acl_high_speed_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_high_speed_fifo.sv"
add_fileset_file "acl_low_latency_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_low_latency_fifo.sv"
add_fileset_file "acl_zero_latency_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_zero_latency_fifo.sv"
add_fileset_file "acl_fanout_pipeline.sv" SYSTEM_VERILOG PATH "ip/acl_fanout_pipeline.sv"
add_fileset_file "acl_std_synchronizer_nocut.v" SYSTEM_VERILOG PATH "ip/acl_std_synchronizer_nocut.v"
add_fileset_file "acl_tessellated_incr_decr_threshold.sv" SYSTEM_VERILOG PATH "ip/acl_tessellated_incr_decr_threshold.sv"
add_fileset_file "acl_tessellated_incr_lookahead.sv" SYSTEM_VERILOG PATH "ip/acl_tessellated_incr_lookahead.sv"
add_fileset_file "acl_lfsr.sv" SYSTEM_VERILOG PATH "ip/acl_lfsr.sv"
add_fileset_file "acl_mlab_fifo.sv" SYSTEM_VERILOG PATH "ip/acl_mlab_fifo.sv"
add_fileset_file "acl_parameter_assert.svh" SYSTEM_VERILOG PATH "ip/acl_parameter_assert.svh"
add_fileset_file "acl_pop_stall_latency.sv" SYSTEM_VERILOG PATH "ip/acl_pop_stall_latency.sv"
add_fileset_file "acl_sync.sv" SYSTEM_VERILOG PATH "ip/acl_sync.sv"
add_fileset_file "acl_desync.sv" SYSTEM_VERILOG PATH "ip/acl_desync.sv"
add_fileset_file "acl_push_stall_latency.sv" SYSTEM_VERILOG PATH "ip/acl_push_stall_latency.sv"
add_fileset_file "acl_dspba_buffer.v" SYSTEM_VERILOG PATH "ip/acl_dspba_buffer.v"
add_fileset_file "acl_fast_pipeline.v" SYSTEM_VERILOG PATH "ip/acl_fast_pipeline.v"
add_fileset_file "acl_push.v" SYSTEM_VERILOG PATH "ip/acl_push.v"
add_fileset_file "acl_token_fifo_counter.v" SYSTEM_VERILOG PATH "ip/acl_token_fifo_counter.v"
add_fileset_file "acl_full_detector.v" SYSTEM_VERILOG PATH "ip/acl_full_detector.v"
add_fileset_file "acl_tessellated_incr_decr_decr.sv" SYSTEM_VERILOG PATH "ip/acl_tessellated_incr_decr_decr.sv"
add_fileset_file "acl_loop_admit.sv" SYSTEM_VERILOG PATH "ip/acl_loop_admit.sv"
add_fileset_file "acl_shift_register_no_reset_dont_merge.sv" SYSTEM_VERILOG PATH "ip/acl_shift_register_no_reset_dont_merge.sv"
add_fileset_file "hld_memory_depth_quantization_pkg.sv" SYSTEM_VERILOG PATH "ip/hld_memory_depth_quantization_pkg.sv"
add_fileset_file "hld_iord.sv" SYSTEM_VERILOG PATH "ip/hld_iord.sv"
add_fileset_file "hld_iord_stall_latency.sv" SYSTEM_VERILOG PATH "ip/hld_iord_stall_latency.sv"
add_fileset_file "hld_iord_stall_valid.sv" SYSTEM_VERILOG PATH "ip/hld_iord_stall_valid.sv"
add_fileset_file "acl_shift_register_no_reset.sv" SYSTEM_VERILOG PATH "ip/acl_shift_register_no_reset.sv"
add_fileset_file "hld_iowr.sv" SYSTEM_VERILOG PATH "ip/hld_iowr.sv"
add_fileset_file "hld_iowr_stall_latency.sv" SYSTEM_VERILOG PATH "ip/hld_iowr_stall_latency.sv"
add_fileset_file "hld_iowr_stall_valid.sv" SYSTEM_VERILOG PATH "ip/hld_iowr_stall_valid.sv"
add_fileset_file "hld_loop_profiler.sv" SYSTEM_VERILOG PATH "ip/hld_loop_profiler.sv"
add_fileset_file "hld_sim_latency_tracker.sv" SYSTEM_VERILOG PATH "ip/hld_sim_latency_tracker.sv"
add_fileset_file "and_func_function_wrapper.sv" SYSTEM_VERILOG PATH "ip/and_func_function_wrapper.sv"
add_fileset_file "and_func_function.sv" SYSTEM_VERILOG PATH "ip/and_func_function.sv"
add_fileset_file "and_func_bb_B0_runOnce.sv" SYSTEM_VERILOG PATH "ip/and_func_bb_B0_runOnce.sv"
add_fileset_file "and_func_B0_runOnce_branch.sv" SYSTEM_VERILOG PATH "ip/and_func_B0_runOnce_branch.sv"
add_fileset_file "and_func_B0_runOnce_merge.sv" SYSTEM_VERILOG PATH "ip/and_func_B0_runOnce_merge.sv"
add_fileset_file "and_func_B0_runOnce_merge_storage.sv" SYSTEM_VERILOG PATH "ip/and_func_B0_runOnce_merge_storage.sv"
add_fileset_file "and_func_bb_B0_runOnce_stall_region.sv" SYSTEM_VERILOG PATH "ip/and_func_bb_B0_runOnce_stall_region.sv"
add_fileset_file "and_func_i_llvm_fpga_pop_token_i1_wt_limpop_0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_pop_token_i1_wt_limpop_0.sv"
add_fileset_file "and_func_i_llvm_fpga_push_token_i1_wt_limpush_0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_push_token_i1_wt_limpush_0.sv"
add_fileset_file "and_func_bb_B1_start.sv" SYSTEM_VERILOG PATH "ip/and_func_bb_B1_start.sv"
add_fileset_file "and_func_B1_start_branch.sv" SYSTEM_VERILOG PATH "ip/and_func_B1_start_branch.sv"
add_fileset_file "and_func_B1_start_merge.sv" SYSTEM_VERILOG PATH "ip/and_func_B1_start_merge.sv"
add_fileset_file "and_func_B1_start_merge_storage.sv" SYSTEM_VERILOG PATH "ip/and_func_B1_start_merge_storage.sv"
add_fileset_file "and_func_bb_B1_start_stall_region.sv" SYSTEM_VERILOG PATH "ip/and_func_bb_B1_start_stall_region.sv"
add_fileset_file "and_func_i_iord_bl_call_unnamed_and_func1_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_iord_bl_call_unnamed_and_func1_and_func0.sv"
add_fileset_file "and_func_i_sfc_s_c0_in_wt_entry_s_c0_enter1_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_sfc_s_c0_in_wt_entry_s_c0_enter1_and_func0.sv"
add_fileset_file "and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_s_c0_exit_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_s_c0_exit_and_func0.sv"
add_fileset_file "and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_and_func1_data_fifo.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_and_func1_data_fifo.sv"
add_fileset_file "and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_func1_full_detector.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_func1_full_detector.sv"
add_fileset_file "and_func_i_sfc_logic_s_c0_in_wt_entry_s_c0_enter1_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_sfc_logic_s_c0_in_wt_entry_s_c0_enter1_and_func0.sv"
add_fileset_file "and_func_i_llvm_fpga_dummy_thread_b1_start_dummy_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_dummy_thread_b1_start_dummy_and_func0.sv"
add_fileset_file "and_func_i_llvm_fpga_forked_b1_start_forked_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_forked_b1_start_forked_and_func0.sv"
add_fileset_file "and_func_i_llvm_fpga_pipeline_keep_going_0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_pipeline_keep_going_0.sv"
add_fileset_file "and_func_i_llvm_fpga_push_i1_notexitcond_0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_push_i1_notexitcond_0.sv"
add_fileset_file "and_func_i_sfc_s_c1_in_wt_entry_s_c1_enter_and_func3.sv" SYSTEM_VERILOG PATH "ip/and_func_i_sfc_s_c1_in_wt_entry_s_c1_enter_and_func3.sv"
add_fileset_file "and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_s_c1_exit_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_s_c1_exit_and_func0.sv"
add_fileset_file "and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_and_func1_data_fifo.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_and_func1_data_fifo.sv"
add_fileset_file "and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_func1_full_detector.sv" SYSTEM_VERILOG PATH "ip/and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_func1_full_detector.sv"
add_fileset_file "and_func_i_sfc_logic_s_c1_in_wt_entry_s_c1_enter_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_sfc_logic_s_c1_in_wt_entry_s_c1_enter_and_func0.sv"
add_fileset_file "and_func_i_iowr_bl_return_unnamed_and_func3_and_func0.sv" SYSTEM_VERILOG PATH "ip/and_func_i_iowr_bl_return_unnamed_and_func3_and_func0.sv"
add_fileset_file "and_func_start_pulse.sv" SYSTEM_VERILOG PATH "ip/and_func_start_pulse.sv"
add_fileset_file "and_func_wait_pulse_extender_inst.sv" SYSTEM_VERILOG PATH "ip/and_func_wait_pulse_extender_inst.sv"
add_fileset_file "and_func_internal.v" SYSTEM_VERILOG PATH "and_func_internal.v"

#### Primary clock for the component
add_interface clock clock end
set_interface_property clock ENABLED true
set_interface_assignment clock hls.cosim.name {$clock}
add_interface_port clock clock clk input 1

#### Primary reset for the component
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_assignment reset hls.cosim.name {$reset}
add_interface_port reset resetn reset_n input 1

#### The component invocation protocol interface (call)
add_interface call conduit sink
set_interface_property call associatedClock clock
set_interface_property call associatedReset reset
set_interface_assignment call hls.cosim.name {$call}
add_interface_port call start valid input 1
add_interface_port call busy stall output 1

#### The component return protocol interface (return)
add_interface return conduit source
set_interface_property return associatedClock clock
set_interface_property return associatedReset reset
set_interface_assignment return hls.cosim.name {$return}
add_interface_port return done valid output 1
add_interface_port return stall stall input 1

#### The component return data interface (returndata)
add_interface returndata conduit source
set_interface_property returndata associatedClock clock
set_interface_property returndata associatedReset reset
set_interface_assignment returndata hls.cosim.name {$returndata}
add_interface_port returndata returndata data output 1

#### Parameter A interface
add_interface A conduit sink
set_interface_property A associatedClock clock
set_interface_property A associatedReset reset
set_interface_assignment A hls.cosim.name {A}
add_interface_port A A data input 1

#### Parameter B interface
add_interface B conduit sink
set_interface_property B associatedClock clock
set_interface_property B associatedReset reset
set_interface_assignment B hls.cosim.name {B}
add_interface_port B B data input 1

#### Quartus settings (QIP strings)
set_qip_strings { "set_instance_assignment -entity \"%entityName%\" -library \"%libraryName%\" -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to *_NO_SHIFT_REG*"  }
