// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from and_func_function
// Created for function/kernel and_func
// SystemVerilog created on Wed Oct 30 16:13:02 2024


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module and_func_function (
    input wire [63:0] in_arg_call,
    input wire [63:0] in_arg_return,
    input wire [15:0] in_iord_bl_call_and_func_i_fifodata,
    input wire [0:0] in_iord_bl_call_and_func_i_fifovalid,
    input wire [0:0] in_iowr_bl_return_and_func_i_fifoready,
    input wire [0:0] in_stall_in,
    input wire [0:0] in_valid_in,
    output wire [0:0] out_iord_bl_call_and_func_o_fifoalmost_full,
    output wire [0:0] out_iord_bl_call_and_func_o_fifoready,
    output wire [0:0] out_iowr_bl_return_and_func_o_fifodata,
    output wire [0:0] out_iowr_bl_return_and_func_o_fifovalid,
    output wire [0:0] out_stall_out,
    output wire [0:0] out_valid_out,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    wire [0:0] and_func_B1_start_x_i_capture;
    wire and_func_B1_start_x_i_capture_bitsignaltemp;
    wire [0:0] and_func_B1_start_x_i_clear;
    wire and_func_B1_start_x_i_clear_bitsignaltemp;
    wire [0:0] and_func_B1_start_x_i_enable;
    wire and_func_B1_start_x_i_enable_bitsignaltemp;
    wire [0:0] and_func_B1_start_x_i_shift;
    wire and_func_B1_start_x_i_shift_bitsignaltemp;
    wire [0:0] and_func_B1_start_x_i_stall_pred;
    wire and_func_B1_start_x_i_stall_pred_bitsignaltemp;
    wire [0:0] and_func_B1_start_x_i_stall_succ;
    wire and_func_B1_start_x_i_stall_succ_bitsignaltemp;
    wire [0:0] and_func_B1_start_x_i_valid_loop;
    wire and_func_B1_start_x_i_valid_loop_bitsignaltemp;
    wire [0:0] and_func_B1_start_x_i_valid_pred;
    wire and_func_B1_start_x_i_valid_pred_bitsignaltemp;
    wire [0:0] and_func_B1_start_x_i_valid_succ;
    wire and_func_B1_start_x_i_valid_succ_bitsignaltemp;
    wire [0:0] bb_and_func_B0_runOnce_out_stall_out_0;
    wire [0:0] bb_and_func_B0_runOnce_out_valid_out_0;
    wire [0:0] bb_and_func_B1_start_out_iord_bl_call_and_func_o_fifoalmost_full;
    wire [0:0] bb_and_func_B1_start_out_iord_bl_call_and_func_o_fifoready;
    wire [0:0] bb_and_func_B1_start_out_iowr_bl_return_and_func_o_fifodata;
    wire [0:0] bb_and_func_B1_start_out_iowr_bl_return_and_func_o_fifovalid;
    wire [0:0] bb_and_func_B1_start_out_profile_loop_o_valid;
    wire [0:0] bb_and_func_B1_start_out_stall_in_0;
    wire [0:0] bb_and_func_B1_start_out_stall_out_0;
    wire [0:0] bb_and_func_B1_start_out_valid_in_0;
    wire [0:0] bb_and_func_B1_start_out_valid_out_0;
    reg [0:0] rst_sync_rst_sclrn;


    // bb_and_func_B0_runOnce(BLACKBOX,3)
    and_func_bb_B0_runOnce thebb_and_func_B0_runOnce (
        .in_stall_in_0(bb_and_func_B1_start_out_stall_out_0),
        .in_valid_in_0(in_valid_in),
        .out_stall_out_0(bb_and_func_B0_runOnce_out_stall_out_0),
        .out_valid_out_0(bb_and_func_B0_runOnce_out_valid_out_0),
        .clock(clock),
        .resetn(resetn)
    );

    // bb_and_func_B1_start(BLACKBOX,4)
    and_func_bb_B1_start thebb_and_func_B1_start (
        .in_iord_bl_call_and_func_i_fifodata(in_iord_bl_call_and_func_i_fifodata),
        .in_iord_bl_call_and_func_i_fifovalid(in_iord_bl_call_and_func_i_fifovalid),
        .in_iowr_bl_return_and_func_i_fifoready(in_iowr_bl_return_and_func_i_fifoready),
        .in_stall_in_0(in_stall_in),
        .in_valid_in_0(bb_and_func_B0_runOnce_out_valid_out_0),
        .out_iord_bl_call_and_func_o_fifoalmost_full(bb_and_func_B1_start_out_iord_bl_call_and_func_o_fifoalmost_full),
        .out_iord_bl_call_and_func_o_fifoready(bb_and_func_B1_start_out_iord_bl_call_and_func_o_fifoready),
        .out_iowr_bl_return_and_func_o_fifodata(bb_and_func_B1_start_out_iowr_bl_return_and_func_o_fifodata),
        .out_iowr_bl_return_and_func_o_fifovalid(bb_and_func_B1_start_out_iowr_bl_return_and_func_o_fifovalid),
        .out_profile_loop_o_valid(bb_and_func_B1_start_out_profile_loop_o_valid),
        .out_stall_in_0(bb_and_func_B1_start_out_stall_in_0),
        .out_stall_out_0(bb_and_func_B1_start_out_stall_out_0),
        .out_valid_in_0(bb_and_func_B1_start_out_valid_in_0),
        .out_valid_out_0(bb_and_func_B1_start_out_valid_out_0),
        .clock(clock),
        .resetn(resetn)
    );

    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // and_func_B1_start_x(EXTIFACE,2)
    assign and_func_B1_start_x_i_capture = GND_q;
    assign and_func_B1_start_x_i_clear = GND_q;
    assign and_func_B1_start_x_i_enable = VCC_q;
    assign and_func_B1_start_x_i_shift = GND_q;
    assign and_func_B1_start_x_i_stall_pred = bb_and_func_B1_start_out_stall_out_0;
    assign and_func_B1_start_x_i_stall_succ = bb_and_func_B1_start_out_stall_in_0;
    assign and_func_B1_start_x_i_valid_loop = bb_and_func_B1_start_out_profile_loop_o_valid;
    assign and_func_B1_start_x_i_valid_pred = bb_and_func_B1_start_out_valid_in_0;
    assign and_func_B1_start_x_i_valid_succ = bb_and_func_B1_start_out_valid_out_0;
    assign and_func_B1_start_x_i_capture_bitsignaltemp = and_func_B1_start_x_i_capture[0];
    assign and_func_B1_start_x_i_clear_bitsignaltemp = and_func_B1_start_x_i_clear[0];
    assign and_func_B1_start_x_i_enable_bitsignaltemp = and_func_B1_start_x_i_enable[0];
    assign and_func_B1_start_x_i_shift_bitsignaltemp = and_func_B1_start_x_i_shift[0];
    assign and_func_B1_start_x_i_stall_pred_bitsignaltemp = and_func_B1_start_x_i_stall_pred[0];
    assign and_func_B1_start_x_i_stall_succ_bitsignaltemp = and_func_B1_start_x_i_stall_succ[0];
    assign and_func_B1_start_x_i_valid_loop_bitsignaltemp = and_func_B1_start_x_i_valid_loop[0];
    assign and_func_B1_start_x_i_valid_pred_bitsignaltemp = and_func_B1_start_x_i_valid_pred[0];
    assign and_func_B1_start_x_i_valid_succ_bitsignaltemp = and_func_B1_start_x_i_valid_succ[0];
    hld_loop_profiler #(
        .LOOP_NAME("and_func.B1.start")
    ) theand_func_B1_start_x (
        .i_capture(and_func_B1_start_x_i_capture_bitsignaltemp),
        .i_clear(and_func_B1_start_x_i_clear_bitsignaltemp),
        .i_enable(and_func_B1_start_x_i_enable_bitsignaltemp),
        .i_shift(and_func_B1_start_x_i_shift_bitsignaltemp),
        .i_stall_pred(and_func_B1_start_x_i_stall_pred_bitsignaltemp),
        .i_stall_succ(and_func_B1_start_x_i_stall_succ_bitsignaltemp),
        .i_valid_loop(and_func_B1_start_x_i_valid_loop_bitsignaltemp),
        .i_valid_pred(and_func_B1_start_x_i_valid_pred_bitsignaltemp),
        .i_valid_succ(and_func_B1_start_x_i_valid_succ_bitsignaltemp),
        .clock(clock),
        .resetn(rst_sync_rst_sclrn[0])
    );

    // out_iord_bl_call_and_func_o_fifoalmost_full(GPOUT,14)
    assign out_iord_bl_call_and_func_o_fifoalmost_full = bb_and_func_B1_start_out_iord_bl_call_and_func_o_fifoalmost_full;

    // out_iord_bl_call_and_func_o_fifoready(GPOUT,15)
    assign out_iord_bl_call_and_func_o_fifoready = bb_and_func_B1_start_out_iord_bl_call_and_func_o_fifoready;

    // out_iowr_bl_return_and_func_o_fifodata(GPOUT,16)
    assign out_iowr_bl_return_and_func_o_fifodata = bb_and_func_B1_start_out_iowr_bl_return_and_func_o_fifodata;

    // out_iowr_bl_return_and_func_o_fifovalid(GPOUT,17)
    assign out_iowr_bl_return_and_func_o_fifovalid = bb_and_func_B1_start_out_iowr_bl_return_and_func_o_fifovalid;

    // out_stall_out(GPOUT,18)
    assign out_stall_out = bb_and_func_B0_runOnce_out_stall_out_0;

    // out_valid_out(GPOUT,19)
    assign out_valid_out = bb_and_func_B1_start_out_valid_out_0;

    // rst_sync(RESETSYNC,20)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
