
namespace eval and_func {
  proc get_design_libraries {} {
    set libraries [dict create]
    dict set libraries and_func_internal_10 1
    dict set libraries and_func             1
    return $libraries
  }
  
  proc get_memory_files {QSYS_SIMDIR} {
    set memory_files [list]
    return $memory_files
  }
  
  proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
    set design_files [dict create]
    return $design_files
  }
  
  proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
    set design_files [list]
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_reset_handler.sv"]\"  -work and_func_internal_10"                                               
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/dspba_library_ver.sv"]\"  -work and_func_internal_10"                                               
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_ecc_pkg.sv"]\"  -work and_func_internal_10"                                                     
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_data_fifo.v"]\"  -work and_func_internal_10"                                                    
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_fifo.v"]\"  -work and_func_internal_10"                                                         
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_altera_syncram_wrapped.sv"]\"  -work and_func_internal_10"                                      
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_scfifo_wrapped.sv"]\"  -work and_func_internal_10"                                              
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_ecc_decoder.sv"]\"  -work and_func_internal_10"                                                 
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_ecc_encoder.sv"]\"  -work and_func_internal_10"                                                 
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_ll_fifo.v"]\"  -work and_func_internal_10"                                                      
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_ll_ram_fifo.v"]\"  -work and_func_internal_10"                                                  
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_valid_fifo_counter.v"]\"  -work and_func_internal_10"                                           
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_dspba_valid_fifo_counter.v"]\"  -work and_func_internal_10"                                     
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_staging_reg.v"]\"  -work and_func_internal_10"                                                  
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/hld_fifo.sv"]\"  -work and_func_internal_10"                                                        
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_mid_speed_fifo.sv"]\"  -work and_func_internal_10"                                              
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_latency_one_ram_fifo.sv"]\"  -work and_func_internal_10"                                        
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_latency_zero_ram_fifo.sv"]\"  -work and_func_internal_10"                                       
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/hld_fifo_zero_width.sv"]\"  -work and_func_internal_10"                                             
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_high_speed_fifo.sv"]\"  -work and_func_internal_10"                                             
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_low_latency_fifo.sv"]\"  -work and_func_internal_10"                                            
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_zero_latency_fifo.sv"]\"  -work and_func_internal_10"                                           
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_fanout_pipeline.sv"]\"  -work and_func_internal_10"                                             
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_std_synchronizer_nocut.v"]\"  -work and_func_internal_10"                                       
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_tessellated_incr_decr_threshold.sv"]\"  -work and_func_internal_10"                             
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_tessellated_incr_lookahead.sv"]\"  -work and_func_internal_10"                                  
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_lfsr.sv"]\"  -work and_func_internal_10"                                                        
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_mlab_fifo.sv"]\"  -work and_func_internal_10"                                                   
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_parameter_assert.svh"]\"  -work and_func_internal_10"                                           
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_pop_stall_latency.sv"]\"  -work and_func_internal_10"                                           
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_sync.sv"]\"  -work and_func_internal_10"                                                        
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_desync.sv"]\"  -work and_func_internal_10"                                                      
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_push_stall_latency.sv"]\"  -work and_func_internal_10"                                          
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_dspba_buffer.v"]\"  -work and_func_internal_10"                                                 
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_fast_pipeline.v"]\"  -work and_func_internal_10"                                                
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_push.v"]\"  -work and_func_internal_10"                                                         
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_token_fifo_counter.v"]\"  -work and_func_internal_10"                                           
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_full_detector.v"]\"  -work and_func_internal_10"                                                
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_tessellated_incr_decr_decr.sv"]\"  -work and_func_internal_10"                                  
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_loop_admit.sv"]\"  -work and_func_internal_10"                                                  
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_shift_register_no_reset_dont_merge.sv"]\"  -work and_func_internal_10"                          
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/hld_memory_depth_quantization_pkg.sv"]\"  -work and_func_internal_10"                               
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/hld_iord.sv"]\"  -work and_func_internal_10"                                                        
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/hld_iord_stall_latency.sv"]\"  -work and_func_internal_10"                                          
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/hld_iord_stall_valid.sv"]\"  -work and_func_internal_10"                                            
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/acl_shift_register_no_reset.sv"]\"  -work and_func_internal_10"                                     
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/hld_iowr.sv"]\"  -work and_func_internal_10"                                                        
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/hld_iowr_stall_latency.sv"]\"  -work and_func_internal_10"                                          
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/hld_iowr_stall_valid.sv"]\"  -work and_func_internal_10"                                            
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/hld_loop_profiler.sv"]\"  -work and_func_internal_10"                                               
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/hld_sim_latency_tracker.sv"]\"  -work and_func_internal_10"                                         
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_function_wrapper.sv"]\"  -work and_func_internal_10"                                       
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_function.sv"]\"  -work and_func_internal_10"                                               
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_bb_B0_runOnce.sv"]\"  -work and_func_internal_10"                                          
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_B0_runOnce_branch.sv"]\"  -work and_func_internal_10"                                      
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_B0_runOnce_merge.sv"]\"  -work and_func_internal_10"                                       
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_B0_runOnce_merge_storage.sv"]\"  -work and_func_internal_10"                               
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_bb_B0_runOnce_stall_region.sv"]\"  -work and_func_internal_10"                             
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_llvm_fpga_pop_token_i1_wt_limpop_0.sv"]\"  -work and_func_internal_10"                   
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_llvm_fpga_push_token_i1_wt_limpush_0.sv"]\"  -work and_func_internal_10"                 
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_bb_B1_start.sv"]\"  -work and_func_internal_10"                                            
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_B1_start_branch.sv"]\"  -work and_func_internal_10"                                        
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_B1_start_merge.sv"]\"  -work and_func_internal_10"                                         
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_B1_start_merge_storage.sv"]\"  -work and_func_internal_10"                                 
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_bb_B1_start_stall_region.sv"]\"  -work and_func_internal_10"                               
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_iord_bl_call_unnamed_and_func1_and_func0.sv"]\"  -work and_func_internal_10"             
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_sfc_s_c0_in_wt_entry_s_c0_enter1_and_func0.sv"]\"  -work and_func_internal_10"           
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_s_c0_exit_and_func0.sv"]\"  -work and_func_internal_10"
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_and_func1_data_fifo.sv"]\"  -work and_func_internal_10"
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_llvm_fpga_sfc_exit_s_c0_out_w0000_func1_full_detector.sv"]\"  -work and_func_internal_10"
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_sfc_logic_s_c0_in_wt_entry_s_c0_enter1_and_func0.sv"]\"  -work and_func_internal_10"     
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_llvm_fpga_dummy_thread_b1_start_dummy_and_func0.sv"]\"  -work and_func_internal_10"      
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_llvm_fpga_forked_b1_start_forked_and_func0.sv"]\"  -work and_func_internal_10"           
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_llvm_fpga_pipeline_keep_going_0.sv"]\"  -work and_func_internal_10"                      
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_llvm_fpga_push_i1_notexitcond_0.sv"]\"  -work and_func_internal_10"                      
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_sfc_s_c1_in_wt_entry_s_c1_enter_and_func3.sv"]\"  -work and_func_internal_10"            
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_s_c1_exit_and_func0.sv"]\"  -work and_func_internal_10"
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_and_func1_data_fifo.sv"]\"  -work and_func_internal_10"
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_func1_full_detector.sv"]\"  -work and_func_internal_10"
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_sfc_logic_s_c1_in_wt_entry_s_c1_enter_and_func0.sv"]\"  -work and_func_internal_10"      
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_i_iowr_bl_return_unnamed_and_func3_and_func0.sv"]\"  -work and_func_internal_10"           
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_start_pulse.sv"]\"  -work and_func_internal_10"                                            
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_wait_pulse_extender_inst.sv"]\"  -work and_func_internal_10"                               
    lappend design_files "vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../and_func_internal_10/sim/and_func_internal.v"]\"  -work and_func_internal_10"                                                
    lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/and_func.v"]\"  -work and_func"                                                                                                     
    return $design_files
  }
  
  proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
    set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
    if {$IS_DUPLICATE == -1} {
      return $NEW_ELAB_OPTION
    } else {
      return ""
    }
  }
  
  
  proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
    set ELAB_OPTIONS ""
    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
    } else {
    }
    return $ELAB_OPTIONS
  }
  
  
  proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
    set SIM_OPTIONS ""
    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
    } else {
    }
    return $SIM_OPTIONS
  }
  
  
  proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
    set ENV_VARIABLES [dict create]
    set LD_LIBRARY_PATH [dict create]
    dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
    } else {
    }
    return $ENV_VARIABLES
  }
  
  
  proc normalize_path {FILEPATH} {
      if {[catch { package require fileutil } err]} { 
          return $FILEPATH 
      } 
      set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]  
      if {[file pathtype $FILEPATH] eq "relative"} { 
          set path [fileutil::relative [pwd] $path] 
      } 
      return $path 
  } 
  proc get_dpi_libraries {QSYS_SIMDIR} {
    set libraries [dict create]
    
    return $libraries
  }
  
}
