// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from i_sfc_logic_s_c0_in_wt_entry_and_funcs_c0_enter1_and_func0
// Created for function/kernel and_func
// SystemVerilog created on Wed Oct 30 16:13:02 2024


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module and_func_i_sfc_logic_s_c0_in_wt_entry_s_c0_enter1_and_func0 (
    output wire [0:0] out_pipeline_dummy_out,
    output wire [0:0] out_pipeline_forked_out,
    output wire [0:0] out_pipeline_valid_out,
    output wire [0:0] out_and_func_B1_start_current_iter_isspec,
    output wire [0:0] out_c0_exi1_0_tpl,
    output wire [0:0] out_c0_exi1_1_tpl,
    output wire [0:0] out_o_valid,
    output wire [0:0] out_exiting_valid_out,
    input wire [0:0] in_buffer_in,
    input wire [0:0] in_dummy_in,
    input wire [0:0] in_i_valid,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    wire [0:0] i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func0_i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func3_mux_x_s;
    reg [0:0] i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func0_i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func3_mux_x_q;
    wire [0:0] i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_adapt_scalar_trunc4_sel_x_b;
    wire [6:0] i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_c_i7_03_x_q;
    wire [7:0] i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_element_extension2_x_q;
    wire [0:0] i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_valid;
    wire i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_stall;
    wire i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_stall_bitsignaltemp;
    wire [7:0] i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_data;
    wire [7:0] i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_o_data;
    wire [0:0] i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_inv_pred_x_q;
    wire [0:0] i_and_func_b1_start_current_iter_isspec_and_func4_q;
    wire [0:0] i_and_func_b1_start_next_iter_isreal_and_func6_q;
    wire [0:0] i_llvm_fpga_dummy_thread_and_func_b1_start_dummy_and_func1_out_dummy_out;
    wire [0:0] i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_and_func5_out_data_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_and_func5_out_exiting_valid_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_and_func5_out_not_exitcond_stall_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_and_func5_out_pipeline_dummy_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_and_func5_out_pipeline_forked_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_and_func5_out_pipeline_valid_out;
    wire [0:0] i_llvm_fpga_push_i1_notexitcond_and_func8_out_data_out;
    wire [0:0] i_llvm_fpga_push_i1_notexitcond_and_func8_out_feedback_out_2;
    wire [0:0] i_llvm_fpga_push_i1_notexitcond_and_func8_out_feedback_valid_out_2;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg0_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg2_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg3_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg4_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg5_q;
    reg [0:0] redist0_sync_together25_in_i_valid_2_q;
    reg [0:0] redist0_sync_together25_in_i_valid_2_delay_0;
    reg [0:0] redist1_sync_together25_in_i_valid_3_q;
    reg [0:0] redist2_i_llvm_fpga_push_i1_notexitcond_and_func8_out_data_out_3_q;
    reg [0:0] redist2_i_llvm_fpga_push_i1_notexitcond_and_func8_out_data_out_3_delay_0;
    reg [0:0] redist2_i_llvm_fpga_push_i1_notexitcond_and_func8_out_data_out_3_delay_1;
    reg [0:0] redist3_i_llvm_fpga_pipeline_keep_going_and_func5_out_data_out_3_q;
    reg [0:0] redist3_i_llvm_fpga_pipeline_keep_going_and_func5_out_data_out_3_delay_0;
    reg [0:0] redist3_i_llvm_fpga_pipeline_keep_going_and_func5_out_data_out_3_delay_1;
    reg [0:0] redist4_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_1_q;
    reg [0:0] redist5_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_4_q;
    reg [0:0] redist5_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_4_delay_0;
    reg [0:0] redist5_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_4_delay_1;
    reg [0:0] redist6_i_llvm_fpga_dummy_thread_and_func_b1_start_dummy_and_func1_out_dummy_out_1_q;
    reg [0:0] redist7_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_inv_pred_x_q_2_q;
    reg [0:0] redist7_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_inv_pred_x_q_2_delay_0;


    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // valid_fanout_reg2(REG,35)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg2_q <= $unsigned(in_i_valid);
        end
    end

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // valid_fanout_reg5(REG,38)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg5_q <= $unsigned(in_i_valid);
        end
    end

    // i_llvm_fpga_push_i1_notexitcond_and_func8(BLACKBOX,29)@1
    // in in_empty_in@20000000
    // out out_feedback_out_2@20000000
    // out out_feedback_valid_out_2@20000000
    and_func_i_llvm_fpga_push_i1_notexitcond_0 thei_llvm_fpga_push_i1_notexitcond_and_func8 (
        .in_almost_empty_in(GND_q),
        .in_data_in(VCC_q),
        .in_empty_in(GND_q),
        .in_feedback_stall_in_2(i_llvm_fpga_pipeline_keep_going_and_func5_out_not_exitcond_stall_out),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg5_q),
        .out_data_out(i_llvm_fpga_push_i1_notexitcond_and_func8_out_data_out),
        .out_feedback_out_2(i_llvm_fpga_push_i1_notexitcond_and_func8_out_feedback_out_2),
        .out_feedback_valid_out_2(i_llvm_fpga_push_i1_notexitcond_and_func8_out_feedback_valid_out_2),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dummy_thread_and_func_b1_start_dummy_and_func1(BLACKBOX,26)@0
    // in in_stall_in@20000000
    and_func_i_llvm_fpga_dummy_thread_b1_start_dummy_and_func0 thei_llvm_fpga_dummy_thread_and_func_b1_start_dummy_and_func1 (
        .in_dummy_in(in_dummy_in),
        .in_stall_in(GND_q),
        .in_valid_in(in_i_valid),
        .out_dummy_out(i_llvm_fpga_dummy_thread_and_func_b1_start_dummy_and_func1_out_dummy_out),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist6_i_llvm_fpga_dummy_thread_and_func_b1_start_dummy_and_func1_out_dummy_out_1(DELAY,46)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist6_i_llvm_fpga_dummy_thread_and_func_b1_start_dummy_and_func1_out_dummy_out_1_q <= $unsigned(i_llvm_fpga_dummy_thread_and_func_b1_start_dummy_and_func1_out_dummy_out);
        end
    end

    // i_llvm_fpga_forked_and_func_b1_start_forked_and_func2(BLACKBOX,27)@0
    // in in_stall_in@20000000
    and_func_i_llvm_fpga_forked_b1_start_forked_and_func0 thei_llvm_fpga_forked_and_func_b1_start_forked_and_func2 (
        .in_buffer_in(in_buffer_in),
        .in_stall_in(GND_q),
        .in_valid_in(in_i_valid),
        .out_buffer_out(i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist4_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_1(DELAY,44)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist4_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_1_q <= $unsigned(i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out);
        end
    end

    // i_llvm_fpga_pipeline_keep_going_and_func5(BLACKBOX,28)@1
    // out out_exiting_stall_out@20000000
    // out out_exiting_valid_out@20000000
    // out out_not_exitcond_stall_out@20000000
    // out out_pipeline_dummy_out@20000000
    // out out_pipeline_forked_out@20000000
    // out out_pipeline_valid_out@20000000
    and_func_i_llvm_fpga_pipeline_keep_going_0 thei_llvm_fpga_pipeline_keep_going_and_func5 (
        .in_data_in(redist4_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_1_q),
        .in_dummy_in(redist6_i_llvm_fpga_dummy_thread_and_func_b1_start_dummy_and_func1_out_dummy_out_1_q),
        .in_forked_in(redist4_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_1_q),
        .in_not_exitcond_in(i_llvm_fpga_push_i1_notexitcond_and_func8_out_feedback_out_2),
        .in_not_exitcond_valid_in(i_llvm_fpga_push_i1_notexitcond_and_func8_out_feedback_valid_out_2),
        .in_pipeline_stall_in(GND_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg2_q),
        .out_data_out(i_llvm_fpga_pipeline_keep_going_and_func5_out_data_out),
        .out_exiting_stall_out(),
        .out_exiting_valid_out(i_llvm_fpga_pipeline_keep_going_and_func5_out_exiting_valid_out),
        .out_not_exitcond_stall_out(i_llvm_fpga_pipeline_keep_going_and_func5_out_not_exitcond_stall_out),
        .out_pipeline_dummy_out(i_llvm_fpga_pipeline_keep_going_and_func5_out_pipeline_dummy_out),
        .out_pipeline_forked_out(i_llvm_fpga_pipeline_keep_going_and_func5_out_pipeline_forked_out),
        .out_pipeline_valid_out(i_llvm_fpga_pipeline_keep_going_and_func5_out_pipeline_valid_out),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_regfree_osync_x(GPOUT,2)
    assign out_pipeline_dummy_out = i_llvm_fpga_pipeline_keep_going_and_func5_out_pipeline_dummy_out;

    // dupName_1_regfree_osync_x(GPOUT,3)
    assign out_pipeline_forked_out = i_llvm_fpga_pipeline_keep_going_and_func5_out_pipeline_forked_out;

    // dupName_2_regfree_osync_x(GPOUT,4)
    assign out_pipeline_valid_out = i_llvm_fpga_pipeline_keep_going_and_func5_out_pipeline_valid_out;

    // redist0_sync_together25_in_i_valid_2(DELAY,40)
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist0_sync_together25_in_i_valid_2_delay_0 <= '0;
        end
        else
        begin
            redist0_sync_together25_in_i_valid_2_delay_0 <= $unsigned(in_i_valid);
        end
    end
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_sync_together25_in_i_valid_2_q <= redist0_sync_together25_in_i_valid_2_delay_0;
        end
    end

    // redist1_sync_together25_in_i_valid_3(DELAY,41)
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist1_sync_together25_in_i_valid_3_q <= '0;
        end
        else
        begin
            redist1_sync_together25_in_i_valid_3_q <= $unsigned(redist0_sync_together25_in_i_valid_2_q);
        end
    end

    // valid_fanout_reg0(REG,33)@3 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg0_q <= $unsigned(redist1_sync_together25_in_i_valid_3_q);
        end
    end

    // redist2_i_llvm_fpga_push_i1_notexitcond_and_func8_out_data_out_3(DELAY,42)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist2_i_llvm_fpga_push_i1_notexitcond_and_func8_out_data_out_3_delay_0 <= $unsigned(i_llvm_fpga_push_i1_notexitcond_and_func8_out_data_out);
            redist2_i_llvm_fpga_push_i1_notexitcond_and_func8_out_data_out_3_delay_1 <= redist2_i_llvm_fpga_push_i1_notexitcond_and_func8_out_data_out_3_delay_0;
            redist2_i_llvm_fpga_push_i1_notexitcond_and_func8_out_data_out_3_q <= redist2_i_llvm_fpga_push_i1_notexitcond_and_func8_out_data_out_3_delay_1;
        end
    end

    // i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_c_i7_03_x(CONSTANT,8)
    assign i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_c_i7_03_x_q = $unsigned(7'b0000000);

    // redist3_i_llvm_fpga_pipeline_keep_going_and_func5_out_data_out_3(DELAY,43)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist3_i_llvm_fpga_pipeline_keep_going_and_func5_out_data_out_3_delay_0 <= $unsigned(i_llvm_fpga_pipeline_keep_going_and_func5_out_data_out);
            redist3_i_llvm_fpga_pipeline_keep_going_and_func5_out_data_out_3_delay_1 <= redist3_i_llvm_fpga_pipeline_keep_going_and_func5_out_data_out_3_delay_0;
            redist3_i_llvm_fpga_pipeline_keep_going_and_func5_out_data_out_3_q <= redist3_i_llvm_fpga_pipeline_keep_going_and_func5_out_data_out_3_delay_1;
        end
    end

    // i_and_func_b1_start_next_iter_isreal_and_func6(LOGICAL,25)@4
    assign i_and_func_b1_start_next_iter_isreal_and_func6_q = i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func0_i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func3_mux_x_q & redist3_i_llvm_fpga_pipeline_keep_going_and_func5_out_data_out_3_q;

    // i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_element_extension2_x(BITJOIN,9)@4
    assign i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_element_extension2_x_q = {i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_c_i7_03_x_q, i_and_func_b1_start_next_iter_isreal_and_func6_q};

    // i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_inv_pred_x(LOGICAL,11)@1
    assign i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_inv_pred_x_q = ~ (GND_q);

    // valid_fanout_reg4(REG,37)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg4_q <= $unsigned(in_i_valid);
        end
    end

    // redist7_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_inv_pred_x_q_2(DELAY,47)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist7_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_inv_pred_x_q_2_delay_0 <= $unsigned(i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_inv_pred_x_q);
            redist7_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_inv_pred_x_q_2_q <= redist7_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_inv_pred_x_q_2_delay_0;
        end
    end

    // valid_fanout_reg3(REG,36)@2 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg3_q <= $unsigned(redist0_sync_together25_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x(FIFODELAY,10)@1 + 1
    // in i_valid@3
    // in i_write_pred@3
    // in i_data@4
    // out o_data@4
    assign i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_stall = ~ (valid_fanout_reg4_q & i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_inv_pred_x_q);
    assign i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_valid = valid_fanout_reg3_q & redist7_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_data = i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_element_extension2_x_q;
    assign i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_valid[0];
    assign i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(8),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x (
        .i_valid(i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_i_stall_bitsignaltemp),
        .i_data(i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_element_extension2_x_q),
        .o_data(i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_adapt_scalar_trunc4_sel_x(BITSELECT,6)@4
    assign i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_adapt_scalar_trunc4_sel_x_b = i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func1_x_o_data[0:0];

    // redist5_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_4(DELAY,45)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist5_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_4_delay_0 <= $unsigned(redist4_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_1_q);
            redist5_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_4_delay_1 <= redist5_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_4_delay_0;
            redist5_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_4_q <= redist5_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_4_delay_1;
        end
    end

    // i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func0_i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func3_mux_x(MUX,5)@4
    assign i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func0_i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func3_mux_x_s = redist5_i_llvm_fpga_forked_and_func_b1_start_forked_and_func2_out_buffer_out_4_q;
    always @(i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func0_i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func3_mux_x_s or i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_adapt_scalar_trunc4_sel_x_b or VCC_q)
    begin
        unique case (i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func0_i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func3_mux_x_s)
            1'b0 : i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func0_i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func3_mux_x_q = i_llvm_fpga_push_i1_and_func_b1_start_next_iter_isreal_push_and_func0_adapt_scalar_trunc4_sel_x_b;
            1'b1 : i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func0_i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func3_mux_x_q = VCC_q;
            default : i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func0_i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func3_mux_x_q = 1'b0;
        endcase
    end

    // i_and_func_b1_start_current_iter_isspec_and_func4(LOGICAL,24)@4
    assign i_and_func_b1_start_current_iter_isspec_and_func4_q = i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func0_i_llvm_fpga_pop_coalesce_i1_and_func_b1_start_current_iter_isreal_and_func3_mux_x_q ^ VCC_q;

    // sync_out_aunroll_x(GPOUT,12)@4
    assign out_and_func_B1_start_current_iter_isspec = i_and_func_b1_start_current_iter_isspec_and_func4_q;
    assign out_c0_exi1_0_tpl = GND_q;
    assign out_c0_exi1_1_tpl = redist2_i_llvm_fpga_push_i1_notexitcond_and_func8_out_data_out_3_q;
    assign out_o_valid = valid_fanout_reg0_q;

    // regfree_osync(GPOUT,30)
    assign out_exiting_valid_out = i_llvm_fpga_pipeline_keep_going_and_func5_out_exiting_valid_out;

endmodule
