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// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from bb_and_func_B1_start
// Created for function/kernel and_func
// SystemVerilog created on Wed Oct 30 16:13:02 2024


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module and_func_bb_B1_start (
    input wire [15:0] in_iord_bl_call_and_func_i_fifodata,
    input wire [0:0] in_iord_bl_call_and_func_i_fifovalid,
    input wire [0:0] in_iowr_bl_return_and_func_i_fifoready,
    input wire [0:0] in_stall_in_0,
    input wire [0:0] in_valid_in_0,
    output wire [0:0] out_iord_bl_call_and_func_o_fifoalmost_full,
    output wire [0:0] out_iord_bl_call_and_func_o_fifoready,
    output wire [0:0] out_iowr_bl_return_and_func_o_fifodata,
    output wire [0:0] out_iowr_bl_return_and_func_o_fifovalid,
    output wire [0:0] out_profile_loop_o_valid,
    output wire [0:0] out_stall_in_0,
    output wire [0:0] out_stall_out_0,
    output wire [0:0] out_valid_in_0,
    output wire [0:0] out_valid_out_0,
    input wire clock,
    input wire resetn
    );

    wire [0:0] and_func_B1_start_branch_out_stall_out;
    wire [0:0] and_func_B1_start_branch_out_valid_out_0;
    wire [0:0] and_func_B1_start_merge_out_almost_empty_out;
    wire [0:0] and_func_B1_start_merge_out_empty_out;
    wire [0:0] and_func_B1_start_merge_out_stall_out_0;
    wire [0:0] and_func_B1_start_merge_out_valid_out;
    wire [0:0] bb_and_func_B1_start_stall_region_out_almost_empty_out;
    wire [0:0] bb_and_func_B1_start_stall_region_out_empty_out;
    wire [0:0] bb_and_func_B1_start_stall_region_out_iord_bl_call_and_func_o_fifoalmost_full;
    wire [0:0] bb_and_func_B1_start_stall_region_out_iord_bl_call_and_func_o_fifoready;
    wire [0:0] bb_and_func_B1_start_stall_region_out_iowr_bl_return_and_func_o_fifodata;
    wire [0:0] bb_and_func_B1_start_stall_region_out_iowr_bl_return_and_func_o_fifovalid;
    wire [0:0] bb_and_func_B1_start_stall_region_out_profile_loop_o_valid;
    wire [0:0] bb_and_func_B1_start_stall_region_out_stall_out;
    wire [0:0] bb_and_func_B1_start_stall_region_out_valid_out;
    reg [0:0] rst_sync_rst_sclrn;


    // and_func_B1_start_branch(BLACKBOX,2)
    and_func_B1_start_branch theand_func_B1_start_branch (
        .in_almost_empty_in(bb_and_func_B1_start_stall_region_out_almost_empty_out),
        .in_empty_in(bb_and_func_B1_start_stall_region_out_empty_out),
        .in_stall_in_0(in_stall_in_0),
        .in_valid_in(bb_and_func_B1_start_stall_region_out_valid_out),
        .out_stall_out(and_func_B1_start_branch_out_stall_out),
        .out_valid_out_0(and_func_B1_start_branch_out_valid_out_0),
        .clock(clock),
        .resetn(resetn)
    );

    // and_func_B1_start_merge(BLACKBOX,3)
    and_func_B1_start_merge theand_func_B1_start_merge (
        .in_stall_in(bb_and_func_B1_start_stall_region_out_stall_out),
        .in_valid_in_0(in_valid_in_0),
        .out_almost_empty_out(and_func_B1_start_merge_out_almost_empty_out),
        .out_empty_out(and_func_B1_start_merge_out_empty_out),
        .out_stall_out_0(and_func_B1_start_merge_out_stall_out_0),
        .out_valid_out(and_func_B1_start_merge_out_valid_out),
        .clock(clock),
        .resetn(resetn)
    );

    // bb_and_func_B1_start_stall_region(BLACKBOX,4)
    and_func_bb_B1_start_stall_region thebb_and_func_B1_start_stall_region (
        .in_almost_empty_in(and_func_B1_start_merge_out_almost_empty_out),
        .in_empty_in(and_func_B1_start_merge_out_empty_out),
        .in_iord_bl_call_and_func_i_fifodata(in_iord_bl_call_and_func_i_fifodata),
        .in_iord_bl_call_and_func_i_fifovalid(in_iord_bl_call_and_func_i_fifovalid),
        .in_iowr_bl_return_and_func_i_fifoready(in_iowr_bl_return_and_func_i_fifoready),
        .in_stall_in(and_func_B1_start_branch_out_stall_out),
        .in_valid_in(and_func_B1_start_merge_out_valid_out),
        .out_almost_empty_out(bb_and_func_B1_start_stall_region_out_almost_empty_out),
        .out_empty_out(bb_and_func_B1_start_stall_region_out_empty_out),
        .out_iord_bl_call_and_func_o_fifoalmost_full(bb_and_func_B1_start_stall_region_out_iord_bl_call_and_func_o_fifoalmost_full),
        .out_iord_bl_call_and_func_o_fifoready(bb_and_func_B1_start_stall_region_out_iord_bl_call_and_func_o_fifoready),
        .out_iowr_bl_return_and_func_o_fifodata(bb_and_func_B1_start_stall_region_out_iowr_bl_return_and_func_o_fifodata),
        .out_iowr_bl_return_and_func_o_fifovalid(bb_and_func_B1_start_stall_region_out_iowr_bl_return_and_func_o_fifovalid),
        .out_profile_loop_o_valid(bb_and_func_B1_start_stall_region_out_profile_loop_o_valid),
        .out_stall_out(bb_and_func_B1_start_stall_region_out_stall_out),
        .out_valid_out(bb_and_func_B1_start_stall_region_out_valid_out),
        .clock(clock),
        .resetn(resetn)
    );

    // out_iord_bl_call_and_func_o_fifoalmost_full(GPOUT,10)
    assign out_iord_bl_call_and_func_o_fifoalmost_full = bb_and_func_B1_start_stall_region_out_iord_bl_call_and_func_o_fifoalmost_full;

    // out_iord_bl_call_and_func_o_fifoready(GPOUT,11)
    assign out_iord_bl_call_and_func_o_fifoready = bb_and_func_B1_start_stall_region_out_iord_bl_call_and_func_o_fifoready;

    // out_iowr_bl_return_and_func_o_fifodata(GPOUT,12)
    assign out_iowr_bl_return_and_func_o_fifodata = bb_and_func_B1_start_stall_region_out_iowr_bl_return_and_func_o_fifodata;

    // out_iowr_bl_return_and_func_o_fifovalid(GPOUT,13)
    assign out_iowr_bl_return_and_func_o_fifovalid = bb_and_func_B1_start_stall_region_out_iowr_bl_return_and_func_o_fifovalid;

    // out_profile_loop_o_valid(GPOUT,14)
    assign out_profile_loop_o_valid = bb_and_func_B1_start_stall_region_out_profile_loop_o_valid;

    // out_stall_in_0(GPOUT,15)
    assign out_stall_in_0 = in_stall_in_0;

    // out_stall_out_0(GPOUT,16)
    assign out_stall_out_0 = and_func_B1_start_merge_out_stall_out_0;

    // out_valid_in_0(GPOUT,17)
    assign out_valid_in_0 = in_valid_in_0;

    // out_valid_out_0(GPOUT,18)
    assign out_valid_out_0 = and_func_B1_start_branch_out_valid_out_0;

    // rst_sync(RESETSYNC,19)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
