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// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
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// SystemVerilog created from i_sfc_s_c1_in_wt_entry_and_funcs_c1_enter_and_func3
// Created for function/kernel and_func
// SystemVerilog created on Wed Oct 30 16:13:02 2024


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module and_func_i_sfc_s_c1_in_wt_entry_s_c1_enter_and_func3 (
    output wire [0:0] out_almost_empty_out,
    output wire [0:0] out_c1_exit_0_tpl,
    output wire [0:0] out_c1_exit_1_tpl,
    output wire [0:0] out_empty_out,
    output wire [0:0] out_o_valid,
    input wire [0:0] in_almost_empty_in,
    input wire [0:0] in_c1_eni1_0_tpl,
    input wire [0:0] in_c1_eni1_1_tpl,
    input wire [0:0] in_c1_eni1_2_tpl,
    input wire [0:0] in_empty_in,
    input wire [0:0] in_i_valid,
    input wire [0:0] in_i_stall,
    output wire [0:0] out_o_stall,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_data_out_0_tpl;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_data_out_1_tpl;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_almost_empty_out;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_empty_out;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_stall_entry;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_valid_out;
    wire [0:0] i_sfc_logic_s_c1_in_wt_entry_and_funcs_c1_enter_and_func0_aunroll_x_out_c1_exi1_0_tpl;
    wire [0:0] i_sfc_logic_s_c1_in_wt_entry_and_funcs_c1_enter_and_func0_aunroll_x_out_c1_exi1_1_tpl;
    wire [0:0] i_sfc_logic_s_c1_in_wt_entry_and_funcs_c1_enter_and_func0_aunroll_x_out_o_valid;
    wire [0:0] input_accepted_and_q;
    reg [0:0] rst_sync_rst_sclrn;


    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // input_accepted_and(LOGICAL,8)
    assign input_accepted_and_q = in_i_valid & VCC_q;

    // i_sfc_logic_s_c1_in_wt_entry_and_funcs_c1_enter_and_func0_aunroll_x(BLACKBOX,4)@59
    and_func_i_sfc_logic_s_c1_in_wt_entry_s_c1_enter_and_func0 thei_sfc_logic_s_c1_in_wt_entry_and_funcs_c1_enter_and_func0_aunroll_x (
        .in_c1_eni1_0_tpl(in_c1_eni1_0_tpl),
        .in_c1_eni1_1_tpl(in_c1_eni1_1_tpl),
        .in_c1_eni1_2_tpl(in_c1_eni1_2_tpl),
        .in_i_valid(input_accepted_and_q),
        .out_c1_exi1_0_tpl(i_sfc_logic_s_c1_in_wt_entry_and_funcs_c1_enter_and_func0_aunroll_x_out_c1_exi1_0_tpl),
        .out_c1_exi1_1_tpl(i_sfc_logic_s_c1_in_wt_entry_and_funcs_c1_enter_and_func0_aunroll_x_out_c1_exi1_1_tpl),
        .out_o_valid(i_sfc_logic_s_c1_in_wt_entry_and_funcs_c1_enter_and_func0_aunroll_x_out_o_valid),
        .out_unnamed_and_func2(),
        .clock(clock),
        .resetn(rst_sync_rst_sclrn[0])
    );

    // i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x(BLACKBOX,3)@59
    // in in_mask_valid@20000000
    // in in_stall_in@20000000
    // out out_data_out_0_tpl@90
    // out out_data_out_1_tpl@90
    // out out_almost_empty_out@90
    // out out_empty_out@90
    // out out_stall_entry@20000000
    // out out_valid_out@90
    and_func_i_llvm_fpga_sfc_exit_s_c1_out_w0000_s_c1_exit_and_func0 thei_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x (
        .in_data_in_0_tpl(i_sfc_logic_s_c1_in_wt_entry_and_funcs_c1_enter_and_func0_aunroll_x_out_c1_exi1_0_tpl),
        .in_data_in_1_tpl(i_sfc_logic_s_c1_in_wt_entry_and_funcs_c1_enter_and_func0_aunroll_x_out_c1_exi1_1_tpl),
        .in_input_accepted(input_accepted_and_q),
        .in_mask_valid(GND_q),
        .in_stall_in(in_i_stall),
        .in_valid_in(i_sfc_logic_s_c1_in_wt_entry_and_funcs_c1_enter_and_func0_aunroll_x_out_o_valid),
        .out_data_out_0_tpl(i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_data_out_0_tpl),
        .out_data_out_1_tpl(i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_data_out_1_tpl),
        .out_almost_empty_out(i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_almost_empty_out),
        .out_empty_out(i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_empty_out),
        .out_stall_entry(i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_stall_entry),
        .out_valid_out(i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_valid_out),
        .clock(clock),
        .resetn(rst_sync_rst_sclrn[0])
    );

    // dupName_0_sync_out_aunroll_x(GPOUT,2)@90
    assign out_almost_empty_out = i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_almost_empty_out;
    assign out_c1_exit_0_tpl = i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_data_out_0_tpl;
    assign out_c1_exit_1_tpl = i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_data_out_1_tpl;
    assign out_empty_out = i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_empty_out;
    assign out_o_valid = i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_valid_out;

    // sync_out(GPOUT,10)@20000000
    assign out_o_stall = i_llvm_fpga_sfc_exit_s_c1_out_wt_entry_and_funcs_c1_exit_and_func1_aunroll_x_out_stall_entry;

    // rst_sync(RESETSYNC,11)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
