// (c) 1992-2024 Intel Corporation.                            
// Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words    
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// Your use of Intel Corporation's design tools, logic functions and other        
// software and tools, and its AMPP partner logic functions, and any output       
// files any of the foregoing (including device programming or simulation         
// files), and any associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License Subscription         
// Agreement, Intel MegaCore Function License Agreement, or other applicable      
// license agreement, including, without limitation, that your use is for the     
// sole purpose of programming logic devices manufactured by Intel and sold by    
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// Generated by Intel(R) HLS Compiler, Version 24.2.0 Build 99.1

/////////////////////////////////////////////////////////////////
// MODULE and_func_internal
/////////////////////////////////////////////////////////////////
module and_func_internal
(
   input logic clock,
   input logic resetn,
   input logic A,
   input logic B,
   input logic start,
   output logic busy,
   output logic done,
   input logic stall,
   output logic returndata
);
   logic resetn_extended;

   // INST and_func_internal of and_func_function_wrapper
   and_func_function_wrapper and_func_internal
   (
      .clock(clock),
      .resetn(resetn_extended),
      .A(A),
      .B(B),
      .start(start),
      .busy(busy),
      .done(done),
      .stall(stall),
      .returndata(returndata)
   );

   // INST global_reset_extender_inst of acl_reset_handler
   acl_reset_handler
   #(
      .ASYNC_RESET(0),
      .USE_SYNCHRONIZER(0),
      .PULSE_EXTENSION(70),
      .PIPE_DEPTH(0)
   )
   global_reset_extender_inst
   (
      .clk(clock),
      .i_resetn(resetn),
      .o_sclrn(resetn_extended)
   );

endmodule

