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`default_nettype none



module acl_shift_register_no_reset_dont_merge #(

    parameter int unsigned WIDTH,

    parameter int unsigned STAGES

) (

    input  wire              clock,

    input  wire  [WIDTH-1:0] D,

    output logic [WIDTH-1:0] Q

);

    genvar g;

    generate

    if (STAGES == 0) begin

        assign Q = D;

    end

    else begin

        logic [WIDTH-1:0] pipe [STAGES-1:0] /* synthesis dont_merge */;

        for (g=0; g<STAGES; g++) begin : GEN_PIPE

            always_ff @(posedge clock) begin

                pipe[g] <= (g==0) ? D : pipe[g-1];

            end

        end

        assign Q = pipe[STAGES-1];

    end

    endgenerate

    

endmodule



`default_nettype wire