module quartus_compile (
	  input logic resetn
	, input logic clock
	, input logic [0:0] and_func_start
	, output logic [0:0] and_func_busy
	, output logic [0:0] and_func_done
	, input logic [0:0] and_func_stall
	, output logic [0:0] and_func_returndata
	, input logic [0:0] and_func_A
	, input logic [0:0] and_func_B
	);

	logic [0:0] and_func_start_reg;
	logic [0:0] and_func_busy_reg;
	logic [0:0] and_func_done_reg;
	logic [0:0] and_func_stall_reg;
	logic [0:0] and_func_returndata_reg;
	logic [0:0] and_func_A_reg;
	logic [0:0] and_func_B_reg;


	always @(posedge clock) begin
		and_func_start_reg <= and_func_start;
		and_func_busy <= and_func_busy_reg;
		and_func_done <= and_func_done_reg;
		and_func_stall_reg <= and_func_stall;
		and_func_returndata <= and_func_returndata_reg;
		and_func_A_reg <= and_func_A;
		and_func_B_reg <= and_func_B;
	end


	reg [2:0] sync_resetn;
	always @(posedge clock or negedge resetn) begin
		if (!resetn) begin
			sync_resetn <= 3'b0;
		end else begin
			sync_resetn <= {sync_resetn[1:0], 1'b1};
		end
	end


	and_func and_func_inst (
		  .resetn(sync_resetn[2])
		, .clock(clock)
		, .start(and_func_start_reg)
		, .busy(and_func_busy_reg)
		, .done(and_func_done_reg)
		, .stall(and_func_stall_reg)
		, .returndata(and_func_returndata_reg)
		, .A(and_func_A_reg)
		, .B(and_func_B_reg)
	);



endmodule
