library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity M10 is
	port (
		
		P_I_RESET    : in std_logic;        -- global reset	
		
		P_I_CLK100   : in std_logic; 		   -- input 100MHz clock ** differential
		
		P_I_WR       : in std_logic; 		   -- enable pulse  
		
		P_O_DAC_CS   : out std_logic;       -- DAC communication pins CS/SYNC    
		P_O_DAC_DATA : out std_logic;       -- DAC data
		P_O_DAC_CLK  : out std_logic;       -- DAC CLK
		
		P_O_PULSE_2  : out std_logic;
		P_O_PULSE	 : out std_logic       	-- output pulse train
	);
	end M10;
	
architecture arch of M10 is


		component user_clks
		PORT(
		inclk0		: IN STD_LOGIC  := '0';
		c0		    : OUT STD_LOGIC ;          -------- 100MHz
		c1		    : OUT STD_LOGIC ;          -------- 10MHz
		locked		: OUT STD_LOGIC 
		);
		end component;
		
		
		component pulse_train
		port(
			I_RESET   : in std_logic;
			
			I_CLK100  : in std_logic;
			
			I_WR      : in std_logic;
			
			O_PULSE_2 : out std_logic;
			O_PULSE   : out std_logic
			);
		end component;
		
		component set_DAC
		port(
			I_RESET    : in std_logic;
			
			I_CLK100   : in std_logic;
			
			O_SYNC     : out std_logic;
			
			O_DAC_DATA : out std_logic;
			O_DAC_CLK  : out std_logic
			);
		end component;	
		
		component M_ADC is
		port (
			clock_clk              : in  std_logic                     := 'X';             -- clk
			reset_sink_reset_n     : in  std_logic                     := 'X';             -- reset_n
			adc_pll_clock_clk      : in  std_logic                     := 'X';             -- clk
			adc_pll_locked_export  : in  std_logic                     := 'X';             -- export
			command_valid          : in  std_logic                     := 'X';             -- valid
			command_channel        : in  std_logic_vector(4 downto 0)  := (others => 'X'); -- channel
			command_startofpacket  : in  std_logic                     := 'X';             -- startofpacket
			command_endofpacket    : in  std_logic                     := 'X';             -- endofpacket
			command_ready          : out std_logic;                                        -- ready
			response_valid         : out std_logic;                                        -- valid
			response_channel       : out std_logic_vector(4 downto 0);                     -- channel
			response_data          : out std_logic_vector(11 downto 0);                    -- data
			response_startofpacket : out std_logic;                                        -- startofpacket
			response_endofpacket   : out std_logic                                         -- endofpacket
		);
	end component M_ADC;
	-----------------------------------
	
	signal VCC : std_logic;
	signal GND : std_logic;
	
	--------------------------------
	
	signal global_reset  : std_logic;
	signal reset_buf     : std_logic;
	----------------------------------
	
	signal clk10  : std_logic;
	signal clk100 : std_logic;
	signal clk_locked : std_logic;
	
	-------------------------------------
	
	signal wr : std_logic;
	signal pulse : std_logic;
	signal pulse_2 : std_logic;
	
	--------------------------------------
	signal sync  : std_logic;
	signal serial_clk : std_logic;
	signal serial_data : std_logic;
	--------------------------------------
	
	signal command_valid           : std_logic;
	signal command_channel         : std_logic_vector(4 downto 0);
	signal command_start           : std_logic;
	signal command_end             : std_logic;
	signal command_ready           : std_logic;
	signal response_valid          : std_logic;
	signal response_channel        : std_logic_vector(4 downto 0);
	signal response_data           : std_logic_vector(11 downto 0);
	signal response_start          : std_logic;
	signal response_end            : std_logic;
	
	signal data_to_display         : std_logic_vector(11 downto 0);
	---------------------------------------
	begin
		VCC <= '1';
		GND <= '0';
	
	reset_buf   <= P_I_RESET;
	
	P_O_PULSE   <= pulse;
	P_O_PULSE_2 <= pulse_2;
	
	P_O_DAC_CLK  <= serial_clk;
	P_O_DAC_CS   <= sync;
	P_O_DAC_DATA <= serial_data;
	
	command_channel   <= "00010"; 
	command_valid <= '1';
	command_start <= '1';
	command_ready <= '1';

	
	
	clocks : user_clks port map(

	inclk0        => P_I_CLK100,
	
	c0            => clk100,
	c1            => clk10,
	
	locked      => clk_locked
	);
	
	
	
	--global reset system
	
	proc_reset: process (clk100, clk_locked)
	begin
		if(clk_locked ='0' or reset_buf='1') then
			global_reset <='1';
		elsif rising_edge (clk100) then
			global_reset <='0';
		end if;
	end process;	
-------------------------------------------------------
		
	
--------------------------------------------------------	--- ------------------------

	pulse_gen : pulse_train port map(

	I_RESET     => global_reset,

	I_CLK100    => clk100,
	
	I_WR        => P_I_WR,
	
	O_PULSE_2   => pulse_2,
	O_PULSE     => pulse
	
	);
	
	lets_DAC : set_DAC port map(
	
	I_RESET    => global_reset,
	
	I_CLK100   => clk100,
	
	O_SYNC     => sync,
	
	O_DAC_DATA => serial_data,
	O_DAC_CLK  => serial_clk
	
	);
	
	
	modular_adc_0 : component M_ADC port map(
	     clock_clk               => clk10,                                --          clock.clk
			reset_sink_reset_n     => global_reset,                        --     reset_sink.reset_n
			adc_pll_clock_clk      => clk10,                               --  adc_pll_clock.clk
			adc_pll_locked_export  => clk_locked,                              -- adc_pll_locked.export
			command_valid          => command_valid,          --        command.valid
			command_channel        => command_channel,        --               .channel
			command_startofpacket  => command_start,          --               .startofpacket
			command_endofpacket    => command_end,            --               .endofpacket
			command_ready          => command_ready,          --               .ready
			response_valid         => response_valid,         --       response.valid
			response_channel       => response_channel,       --               .channel
			response_data          => response_data,          --               .data
			response_startofpacket => response_start,         --               .startofpacket
			response_endofpacket   => response_end            --               .endofpacket
		);
	
	
	process (clk100,response_valid)

	begin

		if rising_edge(clk100) and response_valid = '1' then

			data_to_display <= response_data;

		end if;

	end process;	
	
		
	
end arch;