Hierarchy | Input | Constant Input | Unused Input | Floating Input | Output | Constant Output | Unused Output | Floating Output | Bidir | Constant Bidir | Unused Bidir | Input only Bidir | Output only Bidir
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u0|rst_controller|alt_rst_req_sync_uq1 | 2 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|rst_controller|alt_rst_sync_uq1 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|rst_controller | 33 | 31 | 0 | 31 | 2 | 31 | 31 | 31 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|avalon_st_adapter|error_adapter_0 | 38 | 1 | 2 | 1 | 37 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|avalon_st_adapter | 38 | 0 | 0 | 0 | 37 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|rsp_mux_001 | 120 | 0 | 2 | 0 | 118 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|rsp_mux | 120 | 0 | 2 | 0 | 118 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|rsp_demux | 121 | 4 | 2 | 4 | 235 | 4 | 4 | 4 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|cmd_mux|arb|adder | 8 | 2 | 0 | 2 | 4 | 2 | 2 | 2 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|cmd_mux|arb | 6 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|cmd_mux | 237 | 0 | 0 | 0 | 119 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|cmd_demux_001 | 120 | 1 | 2 | 1 | 118 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|cmd_demux | 120 | 1 | 2 | 1 | 118 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract | 17 | 1 | 0 | 1 | 8 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub | 16 | 2 | 0 | 2 | 8 | 2 | 2 | 2 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract | 17 | 1 | 0 | 1 | 8 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub | 16 | 2 | 0 | 2 | 8 | 2 | 2 | 2 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract | 17 | 1 | 0 | 1 | 8 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub | 16 | 2 | 0 | 2 | 8 | 2 | 2 | 2 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract | 17 | 1 | 0 | 1 | 8 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub | 16 | 2 | 0 | 2 | 8 | 2 | 2 | 2 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract | 17 | 1 | 0 | 1 | 8 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub | 16 | 2 | 0 | 2 | 8 | 2 | 2 | 2 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract | 17 | 1 | 0 | 1 | 8 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub | 16 | 2 | 0 | 2 | 8 | 2 | 2 | 2 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min | 31 | 0 | 2 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment | 7 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size | 29 | 5 | 0 | 5 | 23 | 5 | 5 | 5 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter | 120 | 0 | 0 | 0 | 118 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter | 120 | 0 | 0 | 0 | 118 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|router_002|the_default_decode | 0 | 4 | 0 | 4 | 4 | 4 | 4 | 4 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|router_002 | 118 | 0 | 2 | 0 | 118 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|router_001|the_default_decode | 0 | 3 | 0 | 3 | 3 | 3 | 3 | 3 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|router_001 | 118 | 3 | 3 | 3 | 118 | 3 | 3 | 3 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|router|the_default_decode | 0 | 3 | 0 | 3 | 3 | 3 | 3 | 3 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|router | 118 | 3 | 3 | 3 | 118 | 3 | 3 | 3 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_agent_rdata_fifo | 79 | 41 | 0 | 41 | 36 | 41 | 41 | 41 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_agent_rsp_fifo | 158 | 39 | 0 | 39 | 117 | 39 | 39 | 39 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_agent|uncompressor | 45 | 1 | 0 | 1 | 43 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_agent | 311 | 39 | 39 | 39 | 333 | 39 | 39 | 39 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|hps_0_h2f_lw_axi_master_agent|align_address_to_size | 38 | 0 | 1 | 0 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|hps_0_h2f_lw_axi_master_agent | 413 | 83 | 183 | 83 | 298 | 83 | 83 | 83 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0|onchip_memory2_0_s1_translator | 104 | 7 | 13 | 7 | 81 | 7 | 7 | 7 | 0 | 0 | 0 | 0 | 0
u0|mm_interconnect_0 | 190 | 0 | 0 | 0 | 113 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|onchip_memory2_0|the_altsyncram|auto_generated | 47 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|onchip_memory2_0 | 51 | 1 | 1 | 1 | 32 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|dll | 2 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|oct | 1 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|c0 | 228 | 173 | 8 | 173 | 280 | 173 | 173 | 173 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|seq | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst | 135 | 1 | 3 | 1 | 36 | 1 | 1 | 1 | 10 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs | 135 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].uclk_generator | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ureset_n_pad | 7 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ucmd_pad | 37 | 1 | 0 | 1 | 6 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ubank_pad | 19 | 1 | 0 | 1 | 3 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|uaddress_pad | 79 | 1 | 0 | 1 | 13 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[22].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[21].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[20].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[19].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[18].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[17].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[16].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[15].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[14].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[13].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[12].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[11].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[10].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[9].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[8].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[7].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[6].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[5].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[4].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[3].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[2].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[1].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[0].acv_ac_ldc | 10 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads | 110 | 0 | 5 | 0 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads | 600 | 157 | 340 | 157 | 212 | 157 | 157 | 157 | 10 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|memphy_ldc | 10 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy | 942 | 1 | 2 | 1 | 358 | 1 | 1 | 1 | 10 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0 | 878 | 545 | 0 | 545 | 125 | 545 | 545 | 545 | 10 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst|pll | 2 | 1 | 2 | 1 | 12 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border|hps_sdram_inst | 1 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0
u0|hps_0|hps_io|border | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0|hps_io | 2 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0
u0|hps_0|fpga_interfaces | 67 | 0 | 0 | 0 | 157 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
u0|hps_0 | 69 | 0 | 0 | 0 | 184 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0
u0 | 4 | 0 | 1 | 0 | 27 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0