Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition Info: Processing started: Tue Oct 06 15:15:26 2020 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MP-RX63N-FPGA-01 -c MP-RX63N-FPGA-01 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (12021): Found 1 design units, including 1 entities, in source file /pulser.v Info (12023): Found entity 1: pulser Info (12021): Found 1 design units, including 1 entities, in source file /ram_ctrl.v Info (12023): Found entity 1: ram_ctrl Info (12021): Found 1 design units, including 1 entities, in source file /pio_ctrl.v Info (12023): Found entity 1: pio_ctrl Info (12021): Found 1 design units, including 1 entities, in source file /main.v Info (12023): Found entity 1: main Info (12021): Found 1 design units, including 1 entities, in source file /io_ctrl.v Info (12023): Found entity 1: io_ctrl Info (12021): Found 1 design units, including 1 entities, in source file /db_swled.v Info (12023): Found entity 1: db_swled Info (12021): Found 1 design units, including 1 entities, in source file /altpll_adc.v Info (12023): Found entity 1: altpll_adc Info (12021): Found 1 design units, including 1 entities, in source file /ram2port2.v Info (12023): Found entity 1: ram2port2 Info (12021): Found 1 design units, including 1 entities, in source file /mw_altpll.v Info (12023): Found entity 1: mw_altpll Info (12021): Found 1 design units, including 1 entities, in source file /ram2port.v Info (12023): Found entity 1: ram2port Info (12127): Elaborating entity "main" for the top level hierarchy Info (12128): Elaborating entity "altpll_adc" for hierarchy "altpll_adc:altpll_adc_inst" Info (12128): Elaborating entity "altpll" for hierarchy "altpll_adc:altpll_adc_inst|altpll:altpll_component" Info (12130): Elaborated megafunction instantiation "altpll_adc:altpll_adc_inst|altpll:altpll_component" Info (12133): Instantiated megafunction "altpll_adc:altpll_adc_inst|altpll:altpll_component" with the following parameter: Info (12134): Parameter "bandwidth_type" = "AUTO" Info (12134): Parameter "clk0_divide_by" = "12" Info (12134): Parameter "clk0_duty_cycle" = "50" Info (12134): Parameter "clk0_multiply_by" = "5" Info (12134): Parameter "clk0_phase_shift" = "0" Info (12134): Parameter "compensate_clock" = "CLK0" Info (12134): Parameter "inclk0_input_frequency" = "20833" Info (12134): Parameter "intended_device_family" = "Cyclone 10 LP" Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=altpll_adc" Info (12134): Parameter "lpm_type" = "altpll" Info (12134): Parameter "operation_mode" = "NORMAL" Info (12134): Parameter "pll_type" = "AUTO" Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" Info (12134): Parameter "port_areset" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" Info (12134): Parameter "port_fbin" = "PORT_UNUSED" Info (12134): Parameter "port_inclk0" = "PORT_USED" Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" Info (12134): Parameter "port_locked" = "PORT_UNUSED" Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" Info (12134): Parameter "port_pllena" = "PORT_UNUSED" Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" Info (12134): Parameter "port_scandata" = "PORT_UNUSED" Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" Info (12134): Parameter "port_scandone" = "PORT_UNUSED" Info (12134): Parameter "port_scanread" = "PORT_UNUSED" Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" Info (12134): Parameter "port_clk0" = "PORT_USED" Info (12134): Parameter "port_clk1" = "PORT_UNUSED" Info (12134): Parameter "port_clk2" = "PORT_UNUSED" Info (12134): Parameter "port_clk3" = "PORT_UNUSED" Info (12134): Parameter "port_clk4" = "PORT_UNUSED" Info (12134): Parameter "port_clk5" = "PORT_UNUSED" Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" Info (12134): Parameter "width_clock" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_adc_altpll.v Info (12023): Found entity 1: altpll_adc_altpll Info (12128): Elaborating entity "altpll_adc_altpll" for hierarchy "altpll_adc:altpll_adc_inst|altpll:altpll_component|altpll_adc_altpll:auto_generated" Info (12128): Elaborating entity "pulser" for hierarchy "pulser:pulser" Info (12128): Elaborating entity "io_ctrl" for hierarchy "io_ctrl:io_ctrl" Warning (10240): Verilog HDL Always Construct warning at /io_ctrl.v(171): inferring latch(es) for variable "r_sfr", which holds its previous value in one or more paths through the always construct Info (10041): Inferred latch for "r_sfr[15]" at /io_ctrl.v(171) Info (10041): Inferred latch for "r_sfr[16]" at /io_ctrl.v(171) Info (10041): Inferred latch for "r_sfr[17]" at /io_ctrl.v(171) Info (10041): Inferred latch for "r_sfr[18]" at /io_ctrl.v(171) Info (10041): Inferred latch for "r_sfr[31]" at /io_ctrl.v(171) Info (10041): Inferred latch for "r_sfr[32]" at /io_ctrl.v(171) Info (10041): Inferred latch for "r_sfr[33]" at /io_ctrl.v(171) Info (10041): Inferred latch for "r_sfr[34]" at /io_ctrl.v(171) Info (12128): Elaborating entity "db_swled" for hierarchy "io_ctrl:io_ctrl|db_swled:swled" Info (12128): Elaborating entity "ram_ctrl" for hierarchy "ram_ctrl:ram_ctrl" Info (12128): Elaborating entity "mw_altpll" for hierarchy "ram_ctrl:ram_ctrl|mw_altpll:mw_altpll_inst" Info (12128): Elaborating entity "altpll" for hierarchy "ram_ctrl:ram_ctrl|mw_altpll:mw_altpll_inst|altpll:altpll_component" Info (12130): Elaborated megafunction instantiation "ram_ctrl:ram_ctrl|mw_altpll:mw_altpll_inst|altpll:altpll_component" Info (12133): Instantiated megafunction "ram_ctrl:ram_ctrl|mw_altpll:mw_altpll_inst|altpll:altpll_component" with the following parameter: Info (12134): Parameter "bandwidth_type" = "AUTO" Info (12134): Parameter "clk0_divide_by" = "12" Info (12134): Parameter "clk0_duty_cycle" = "50" Info (12134): Parameter "clk0_multiply_by" = "5" Info (12134): Parameter "clk0_phase_shift" = "0" Info (12134): Parameter "compensate_clock" = "CLK0" Info (12134): Parameter "inclk0_input_frequency" = "20833" Info (12134): Parameter "intended_device_family" = "Cyclone 10 LP" Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=mw_altpll" Info (12134): Parameter "lpm_type" = "altpll" Info (12134): Parameter "operation_mode" = "NORMAL" Info (12134): Parameter "pll_type" = "AUTO" Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" Info (12134): Parameter "port_areset" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" Info (12134): Parameter "port_fbin" = "PORT_UNUSED" Info (12134): Parameter "port_inclk0" = "PORT_USED" Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" Info (12134): Parameter "port_locked" = "PORT_UNUSED" Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" Info (12134): Parameter "port_pllena" = "PORT_UNUSED" Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" Info (12134): Parameter "port_scandata" = "PORT_UNUSED" Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" Info (12134): Parameter "port_scandone" = "PORT_UNUSED" Info (12134): Parameter "port_scanread" = "PORT_UNUSED" Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" Info (12134): Parameter "port_clk0" = "PORT_USED" Info (12134): Parameter "port_clk1" = "PORT_UNUSED" Info (12134): Parameter "port_clk2" = "PORT_UNUSED" Info (12134): Parameter "port_clk3" = "PORT_UNUSED" Info (12134): Parameter "port_clk4" = "PORT_UNUSED" Info (12134): Parameter "port_clk5" = "PORT_UNUSED" Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" Info (12134): Parameter "width_clock" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/mw_altpll_altpll.v Info (12023): Found entity 1: mw_altpll_altpll Info (12128): Elaborating entity "mw_altpll_altpll" for hierarchy "ram_ctrl:ram_ctrl|mw_altpll:mw_altpll_inst|altpll:altpll_component|mw_altpll_altpll:auto_generated" Info (12128): Elaborating entity "ram2port" for hierarchy "ram_ctrl:ram_ctrl|ram2port:ram2port_inst" Info (12128): Elaborating entity "altsyncram" for hierarchy "ram_ctrl:ram_ctrl|ram2port:ram2port_inst|altsyncram:altsyncram_component" Info (12130): Elaborated megafunction instantiation "ram_ctrl:ram_ctrl|ram2port:ram2port_inst|altsyncram:altsyncram_component" Info (12133): Instantiated megafunction "ram_ctrl:ram_ctrl|ram2port:ram2port_inst|altsyncram:altsyncram_component" with the following parameter: Info (12134): Parameter "address_reg_b" = "CLOCK0" Info (12134): Parameter "byte_size" = "8" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_b" = "BYPASS" Info (12134): Parameter "clock_enable_output_a" = "BYPASS" Info (12134): Parameter "clock_enable_output_b" = "BYPASS" Info (12134): Parameter "indata_reg_b" = "CLOCK0" Info (12134): Parameter "intended_device_family" = "Cyclone 10 LP" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "4096" Info (12134): Parameter "numwords_b" = "4096" Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT" Info (12134): Parameter "outdata_aclr_a" = "CLEAR0" Info (12134): Parameter "outdata_aclr_b" = "CLEAR0" Info (12134): Parameter "outdata_reg_a" = "CLOCK0" Info (12134): Parameter "outdata_reg_b" = "CLOCK0" Info (12134): Parameter "power_up_uninitialized" = "FALSE" Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_WITH_NBE_READ" Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_WITH_NBE_READ" Info (12134): Parameter "widthad_a" = "12" Info (12134): Parameter "widthad_b" = "12" Info (12134): Parameter "width_a" = "16" Info (12134): Parameter "width_b" = "16" Info (12134): Parameter "width_byteena_a" = "2" Info (12134): Parameter "width_byteena_b" = "1" Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ink2.tdf Info (12023): Found entity 1: altsyncram_ink2 Info (12128): Elaborating entity "altsyncram_ink2" for hierarchy "ram_ctrl:ram_ctrl|ram2port:ram2port_inst|altsyncram:altsyncram_component|altsyncram_ink2:auto_generated" Info (12128): Elaborating entity "ram2port2" for hierarchy "ram_ctrl:ram_ctrl|ram2port2:ram2port2_inst" Info (286030): Timing-Driven Synthesis is running Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL Info (21057): Implemented 326 device resources after synthesis - the final resource count might be different Info (21058): Implemented 49 input pins Info (21059): Implemented 7 output pins Info (21060): Implemented 16 bidirectional pins Info (21061): Implemented 220 logic cells Info (21064): Implemented 32 RAM segments Info (21065): Implemented 2 PLLs Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings Info: Peak virtual memory: 4790 megabytes Info: Processing ended: Tue Oct 06 15:15:44 2020 Info: Elapsed time: 00:00:18 Info: Total CPU time (on all processors): 00:00:24 Info: ******************************************************************* Info: Running Quartus Prime Fitter Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition Info: Processing started: Tue Oct 06 15:15:50 2020 Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off MP-RX63N-FPGA-01 -c MP-RX63N-FPGA-01 Info: qfit2_default_script.tcl version: #1 Info: Project = MP-RX63N-FPGA-01 Info: Revision = MP-RX63N-FPGA-01 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (119006): Selected device 10CL010YE144I7G for design "MP-RX63N-FPGA-01" Info (21077): Low junction temperature is -40 degrees C Info (21077): High junction temperature is 100 degrees C Info (15535): Implemented PLL "altpll_adc:altpll_adc_inst|altpll:altpll_component|altpll_adc_altpll:auto_generated|pll1" as Cyclone 10 LP PLL type Info (15099): Implementing clock multiplication of 5, clock division of 12, and phase shift of 0 degrees (0 ps) for altpll_adc:altpll_adc_inst|altpll:altpll_component|altpll_adc_altpll:auto_generated|wire_pll1_clk[0] port Info (15535): Implemented PLL "ram_ctrl:ram_ctrl|mw_altpll:mw_altpll_inst|altpll:altpll_component|mw_altpll_altpll:auto_generated|pll1" as Cyclone 10 LP PLL type Info (15099): Implementing clock multiplication of 5, clock division of 12, and phase shift of 0 degrees (0 ps) for ram_ctrl:ram_ctrl|mw_altpll:mw_altpll_inst|altpll:altpll_component|mw_altpll_altpll:auto_generated|wire_pll1_clk[0] port Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info (176445): Device 10CL006YE144A7G is compatible Info (176445): Device 10CL006YE144I7G is compatible Info (176445): Device 10CL010YE144A7G is compatible Info (176445): Device 10CL016YE144A7G is compatible Info (176445): Device 10CL016YE144I7G is compatible Info (176445): Device 10CL025YE144A7G is compatible Info (176445): Device 10CL025YE144I7G is compatible Info (169124): Fitter converted 5 user pins into dedicated programming pins Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6 Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8 Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12 Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13 Info (169125): Pin ~ALTERA_INIT_DONE~ is reserved at location 98 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info (176132): Successfully merged PLL ram_ctrl:ram_ctrl|mw_altpll:mw_altpll_inst|altpll:altpll_component|mw_altpll_altpll:auto_generated|pll1 and PLL altpll_adc:altpll_adc_inst|altpll:altpll_component|altpll_adc_altpll:auto_generated|pll1 Info (332104): Reading SDC File: '/main.sdc' Info (332110): Deriving PLL clocks Info (332110): create_generated_clock -source {ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 12 -multiply_by 5 -duty_cycle 50.00 -name {ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0]} {ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0]} Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332104): Reading SDC File: '/MP-RX63N-FPGA-01.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 2 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 20.833 CLK48MHz Info (332111): 49.999 ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0] Info (176353): Automatically promoted node CLK~input (placed in PIN 91 (CLK4, DIFFCLK_2p)) Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9 Info (176353): Automatically promoted node ram_ctrl:ram_ctrl|mw_altpll:mw_altpll_inst|altpll:altpll_component|mw_altpll_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_2) Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8 Info (176353): Automatically promoted node RSTL~input (placed in PIN 89 (CLK6, DIFFCLK_3p)) Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G6 Info (176356): Following destination nodes may be non-global or may not use global or regional clocks Info (176357): Destination node pulser:pulser|state_r Info (176357): Destination node pulser:pulser|pulse_r~0 Info (176357): Destination node pulser:pulser|PULSE_CYCLE_counter_r[11]~16 Info (176357): Destination node pulser:pulser|PULSE_CYCLE_counter_r[11]~17 Info (176233): Starting register packing Info (176235): Finished register packing Extra Info (176219): No registers were packed into other blocks Warning (15064): PLL "ram_ctrl:ram_ctrl|mw_altpll:mw_altpll_inst|altpll:altpll_component|mw_altpll_altpll:auto_generated|pll1" output port clk[0] feeds output pin "O_ADC2_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance Warning (15064): PLL "ram_ctrl:ram_ctrl|mw_altpll:mw_altpll_inst|altpll:altpll_component|mw_altpll_altpll:auto_generated|pll1" output port clk[0] feeds output pin "O_ADC1_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 2% of the available device resources Info (170196): Router estimated peak interconnect usage is 6% of the available device resources in the region that extends from location X11_Y0 to location X22_Y11 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 Info (11888): Total time spent on timing analysis during the Fitter is 0.37 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 Warning (169177): 65 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone 10 LP Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Info (169178): Pin PD[0] uses I/O standard 3.3-V LVTTL at 73 Info (169178): Pin PD[1] uses I/O standard 3.3-V LVTTL at 72 Info (169178): Pin PD[2] uses I/O standard 3.3-V LVTTL at 71 Info (169178): Pin PD[3] uses I/O standard 3.3-V LVTTL at 70 Info (169178): Pin PD[4] uses I/O standard 3.3-V LVTTL at 69 Info (169178): Pin PD[5] uses I/O standard 3.3-V LVTTL at 68 Info (169178): Pin PD[6] uses I/O standard 3.3-V LVTTL at 67 Info (169178): Pin PD[7] uses I/O standard 3.3-V LVTTL at 66 Info (169178): Pin PD[8] uses I/O standard 3.3-V LVTTL at 65 Info (169178): Pin PD[9] uses I/O standard 3.3-V LVTTL at 136 Info (169178): Pin PD[10] uses I/O standard 3.3-V LVTTL at 60 Info (169178): Pin PD[11] uses I/O standard 3.3-V LVTTL at 59 Info (169178): Pin PD[12] uses I/O standard 3.3-V LVTTL at 58 Info (169178): Pin PD[13] uses I/O standard 3.3-V LVTTL at 55 Info (169178): Pin PD[14] uses I/O standard 3.3-V LVTTL at 54 Info (169178): Pin PD[15] uses I/O standard 3.3-V LVTTL at 53 Info (169178): Pin CLK uses I/O standard 3.3-V LVTTL at 91 Info (169178): Pin RSTL uses I/O standard 3.3-V LVTTL at 89 Info (169178): Pin PA[1] uses I/O standard 3.3-V LVTTL at 85 Info (169178): Pin PA[4] uses I/O standard 3.3-V LVTTL at 100 Info (169178): Pin PA[5] uses I/O standard 3.3-V LVTTL at 103 Info (169178): Pin PA[6] uses I/O standard 3.3-V LVTTL at 138 Info (169178): Pin PCS1L uses I/O standard 3.3-V LVTTL at 80 Info (169178): Pin PA[3] uses I/O standard 3.3-V LVTTL at 87 Info (169178): Pin PA[0] uses I/O standard 3.3-V LVTTL at 84 Info (169178): Pin PA[2] uses I/O standard 3.3-V LVTTL at 86 Info (169178): Pin PBE0L uses I/O standard 3.3-V LVTTL at 83 Info (169178): Pin PBE1L uses I/O standard 3.3-V LVTTL at 77 Info (169178): Pin PWRL uses I/O standard 3.3-V LVTTL at 75 Info (169178): Pin PA[13] uses I/O standard 3.3-V LVTTL at 115 Info (169178): Pin PA[14] uses I/O standard 3.3-V LVTTL at 119 Info (169178): Pin PCS2L uses I/O standard 3.3-V LVTTL at 88 Info (169178): Pin PRDL uses I/O standard 3.3-V LVTTL at 76 Info (169178): Pin PA[12] uses I/O standard 3.3-V LVTTL at 114 Info (169178): Pin PA[7] uses I/O standard 3.3-V LVTTL at 105 Info (169178): Pin PA[8] uses I/O standard 3.3-V LVTTL at 135 Info (169178): Pin PA[9] uses I/O standard 3.3-V LVTTL at 111 Info (169178): Pin PA[10] uses I/O standard 3.3-V LVTTL at 112 Info (169178): Pin PA[11] uses I/O standard 3.3-V LVTTL at 113 Info (169178): Pin I_ADC1_D[0] uses I/O standard 3.3-V LVTTL at 51 Info (169178): Pin I_ADC2_D[0] uses I/O standard 3.3-V LVTTL at 28 Info (169178): Pin DSW[0] uses I/O standard 3.3-V LVTTL at 24 Info (169178): Pin I_ADC1_D[1] uses I/O standard 3.3-V LVTTL at 50 Info (169178): Pin I_ADC2_D[1] uses I/O standard 3.3-V LVTTL at 10 Info (169178): Pin DSW[1] uses I/O standard 3.3-V LVTTL at 25 Info (169178): Pin I_ADC1_D[2] uses I/O standard 3.3-V LVTTL at 49 Info (169178): Pin I_ADC2_D[2] uses I/O standard 3.3-V LVTTL at 11 Info (169178): Pin I_ADC1_D[3] uses I/O standard 3.3-V LVTTL at 46 Info (169178): Pin I_ADC2_D[3] uses I/O standard 3.3-V LVTTL at 3 Info (169178): Pin I_ADC1_D[4] uses I/O standard 3.3-V LVTTL at 44 Info (169178): Pin I_ADC2_D[4] uses I/O standard 3.3-V LVTTL at 7 Info (169178): Pin I_ADC1_D[5] uses I/O standard 3.3-V LVTTL at 43 Info (169178): Pin I_ADC2_D[5] uses I/O standard 3.3-V LVTTL at 1 Info (169178): Pin I_ADC1_D[6] uses I/O standard 3.3-V LVTTL at 42 Info (169178): Pin I_ADC2_D[6] uses I/O standard 3.3-V LVTTL at 2 Info (169178): Pin I_ADC1_D[7] uses I/O standard 3.3-V LVTTL at 39 Info (169178): Pin I_ADC2_D[7] uses I/O standard 3.3-V LVTTL at 143 Info (169178): Pin I_ADC1_D[8] uses I/O standard 3.3-V LVTTL at 38 Info (169178): Pin I_ADC2_D[8] uses I/O standard 3.3-V LVTTL at 144 Info (169178): Pin I_ADC1_D[9] uses I/O standard 3.3-V LVTTL at 34 Info (169178): Pin I_ADC2_D[9] uses I/O standard 3.3-V LVTTL at 141 Info (169178): Pin I_ADC1_D[10] uses I/O standard 3.3-V LVTTL at 33 Info (169178): Pin I_ADC2_D[10] uses I/O standard 3.3-V LVTTL at 142 Info (169178): Pin I_ADC1_D[11] uses I/O standard 3.3-V LVTTL at 32 Info (169178): Pin I_ADC2_D[11] uses I/O standard 3.3-V LVTTL at 137 Info (144001): Generated suppressed messages file Y:/output_files/MP-RX63N-FPGA-01.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings Info: Peak virtual memory: 5562 megabytes Info: Processing ended: Tue Oct 06 15:16:03 2020 Info: Elapsed time: 00:00:13 Info: Total CPU time (on all processors): 00:00:09 Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition Info: Processing started: Tue Oct 06 15:16:19 2020 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off MP-RX63N-FPGA-01 -c MP-RX63N-FPGA-01 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning Info: Peak virtual memory: 4708 megabytes Info: Processing ended: Tue Oct 06 15:16:22 2020 Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:01 Info (293026): Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition Info: Processing started: Tue Oct 06 15:16:25 2020 Info: Command: quartus_sta MP-RX63N-FPGA-01 -c MP-RX63N-FPGA-01 Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (21077): Low junction temperature is -40 degrees C Info (21077): High junction temperature is 100 degrees C Info (332104): Reading SDC File: '/main.sdc' Info (332110): Deriving PLL clocks Info (332110): create_generated_clock -source {ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 12 -multiply_by 5 -duty_cycle 50.00 -name {ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0]} {ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0]} Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332104): Reading SDC File: '/MP-RX63N-FPGA-01.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 100C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. Info (332146): Worst-case setup slack is -2.693 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -2.693 -5.200 CLK48MHz Info (332119): -1.279 -26.117 ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case hold slack is 0.305 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.305 0.000 ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.417 0.000 CLK48MHz Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 10.029 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 10.029 0.000 CLK48MHz Info (332119): 24.676 0.000 ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0] Warning (18330): Ignoring Synchronizer Identification setting Off, and using Auto instead. Info: Analyzing Slow 1200mV -40C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. Info (332146): Worst-case setup slack is -2.629 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -2.629 -5.116 CLK48MHz Info (332119): -0.493 -3.532 ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case hold slack is 0.279 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.279 0.000 ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.345 0.000 CLK48MHz Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 10.044 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 10.044 0.000 CLK48MHz Info (332119): 24.670 0.000 ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0] Warning (18330): Ignoring Synchronizer Identification setting Off, and using Auto instead. Info: Analyzing Fast 1200mV -40C Model Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. Info (332146): Worst-case setup slack is -1.366 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1.366 -2.649 CLK48MHz Info (332119): 1.534 0.000 ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case hold slack is 0.163 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.163 0.000 ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.180 0.000 CLK48MHz Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 9.647 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 9.647 0.000 CLK48MHz Info (332119): 24.700 0.000 ram_ctrl|mw_altpll_inst|altpll_component|auto_generated|pll1|clk[0] Warning (18330): Ignoring Synchronizer Identification setting Off, and using Auto instead. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 7 warnings Info: Peak virtual memory: 4799 megabytes Info: Processing ended: Tue Oct 06 15:16:34 2020 Info: Elapsed time: 00:00:09 Info: Total CPU time (on all processors): 00:00:02 Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition Info: Processing started: Tue Oct 06 15:16:41 2020 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off MP-RX63N-FPGA-01 -c MP-RX63N-FPGA-01 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Error (20268): Functional simulation is off but it is the only supported netlist type for this device. Info (204019): Generated file MP-RX63N-FPGA-01.vo in folder "Y:/simulation/modelsim/" for EDA simulation tool Error: Quartus Prime EDA Netlist Writer was unsuccessful. 1 error, 1 warning Error: Peak virtual memory: 4670 megabytes Error: Processing ended: Tue Oct 06 15:16:45 2020 Error: Elapsed time: 00:00:04 Error: Total CPU time (on all processors): 00:00:01 Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 17 warnings