/*
    Description :
    This block is to sync the reset signal so that it can be used in the system.

    User can set the parameters to get the desired reset signals
    Parameter signals:

    SYNC_DEPTH       : at least 3 FFs.
    ADDITIONAL_DEPTH : at least 2 FFs, add more of that if recovery errors occur from FFs hooked up to reset_out
    DISABLE_GLOBAL_NETWORK : set to 1 to prevent synchronized reset from getting promoted to global network, enable this if recovery errors occur from FFs hooked up to reset_out
    SYNC_BOTH_EDGE : set to 1 synchronize the reset_in to both edges, set to 0 to allow reset_out to deassert asynchronously and assert synchronously

*/




module reset_sync_block_v2(
    input wire clk_in,
    input wire reset_in,
    output wire clk_out,
    output wire reset_out
);

parameter SYNC_DEPTH                = 3;
parameter ADDITIONAL_DEPTH          = 2;
parameter DISABLE_GLOBAL_NETWORK    = 1;
parameter SYNC_BOTH_EDGES           = 0;

(* preserve *) reg [SYNC_DEPTH - 1 : 0] sync_reg;

// if use global network
generate

if(DISABLE_GLOBAL_NETWORK == 1)
begin
    (* altera_attribute = "-name GLOBAL_SIGNAL OFF" *) reg [ADDITIONAL_DEPTH - 1 : 0] output_pipeline_reg;
end 
else
begin
    reg [ADDITIONAL_DEPTH - 1 : 0] output_pipeline_reg;
end

endgenerate

// if sync on both edge

generate

if(SYNC_BOTH_EDGES == 0)
begin
    always@(posedge clk_in or posedge reset_in)
    begin
        if(reset_in == 1'b1)
        begin
            sync_reg <= {SYNC_DEPTH{1'b1}};
        end
        else
        begin
            sync_reg[SYNC_DEPTH - 1] <= 1'b0;
            sync_reg [SYNC_DEPTH - 2 : 0] <= sync_reg[SYNC_DEPTH - 1 : 1]; 
        end
    end

    always@(posedge clk_in or posedge reset_in)
    begin
        if(reset_in == 1'b1)
        begin
            output_pipeline_reg <= {ADDITIONAL_DEPTH {1'b1}};
        end
        else
        begin
            output_pipeline_reg[ADDITIONAL_DEPTH - 1] <= 1'b0;
            output_pipeline_reg[ADDITIONAL_DEPTH - 2 : 0] <= output_pipeline_reg[ADDITIONAL_DEPTH - 1 : 1];
        end
    end
end
else
begin
/*
    always@(posedge clk)
    begin
        sync_reg[SYNC_DEPTH - 1] <= reset_in;
        sync_reg[SYNC_DEPTH - 2 : 0] <= sync_reg[SYNC_DEPTH - 1 : 1];
    end    
    
*/

    always@(posedge clk_in or posedge reset_in)
    begin
        if(reset_in == 1'b1)
        begin
            sync_reg <={SYNC_DEPTH{1'b1}};
        end
    
        else
        begin
            sync_reg[SYNC_DEPTH - 1] <= 1'b0;
            sync_reg[SYNC_DEPTH - 2 : 0] <= sync_reg[SYNC_DEPTH - 1 : 1];
        end
    end

    always@(posedge clk_in)
    begin
        output_pipeline_reg[ADDITIONAL_DEPTH - 1] <= reset_in;
        output_pipeline_reg[ADDITIONAL_DEPTH - 2 : 0] <= output_pipeline_reg[ADDITIONAL_DEPTH - 1 : 1];
    end

end

endgenerate

assign clk_out = clk_in;

endmodule