library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
 use ieee.std_logic_unsigned.all;
   use ieee.std_logic_textio.all;
library std;
   use std.textio.all;

entity async_input_bram_player_tb is
end async_input_bram_player_tb;


architecture testbench of async_input_bram_player_tb is


 ----------------------------------------------------------------------
component async_input_bram_player
	port
	(
		clock		: in std_logic  := '1';
		data		: in std_logic_vector (127 downto 0);
		address		: in std_logic_vector (8 downto 0);
		wren		: in std_logic  := '0';
		q			: out std_logic_vector (127 downto 0)
	);
end component;

 ----------------------------------------------------------------------                                            
 signal  qam_number							: std_logic_vector(6 downto 0);
 signal  dpram_128x512_rdaddress			: std_logic_vector(8 downto 0);
 signal  dpram_128x512_data					: std_logic_vector(127 downto 0);
 signal  valid_for_async					: std_logic;
 signal  busy_from_async					: std_logic;
 type state_type is (idle,wait_1_clock,read_packet);
 signal current_state  : state_type;
 signal  counter							: integer range 0 to 127;
 signal  packet								: integer range 0 to 1023;
 signal  clock_counter						: integer;
 signal  sys_clk							: std_logic:='0';
 signal  reset_n							: std_logic;
 
begin
-----------------------------------------------
-- ** clocks and resets **
  sys_clk              <= not sys_clk  after 10 ns;
  reset_n <='0', '1' after 50 ns;
-----------------------------------------------
 inst_async_input_bram_player : async_input_bram_player
	PORT MAP
	(
		clock		=> sys_clk,
		data		=> (OTHERS => '0'),
		address	=> dpram_128x512_rdaddress,
		wren		=> '0',
		q			=> dpram_128x512_data
	);
	
	busy_from_async	<= '0';
------------------------------------------------------------------------------------------
	read_from_bram : PROCESS (sys_clk,reset_n) 
	BEGIN
		IF (reset_n = '0') THEN
			valid_for_async <= '0';
			counter <= 0;
			packet <= 0;
			clock_counter <= 0;
			QAM_number <= "0000001";
			dpram_128x512_rdaddress <= (OTHERS => '0');
		ELSIF sys_clk'event and sys_clk = '1' THEN
-----------------------------------------------------------------------------------------
			CASE (current_state) IS
----------------------------------------------------------------------------------			
				WHEN IDLE =>
					IF (busy_from_async = '0') THEN
						dpram_128x512_rdaddress <= dpram_128x512_rdaddress + 1;
						counter <= 0;
						current_state <= WAIT_1_CLOCK;
						valid_for_async <= '1';
					ELSE
						valid_for_async <= '0';
					END IF;
----------------------------------------------------------------------------------
				WHEN WAIT_1_CLOCK =>
					current_state <= READ_PACKET;
					dpram_128x512_rdaddress <= dpram_128x512_rdaddress + 1;
					counter <= counter + 1;
					valid_for_async <= '1';
----------------------------------------------------------------------------------
				WHEN READ_PACKET =>												-- 07 06 05 04 03 02 01
					IF (((packet = 0) AND (counter = 111)) OR					-- 81 69 57 45 34 22 10
					    ((packet > 0) AND (counter = 111))) THEN				-- 111
						current_state <= IDLE;
						packet <= packet + 1;
						IF QAM_number = "0000001" THEN
							QAM_number <= "0000010";
						ELSE
							QAM_number <= "0000001";
						END IF;
					ELSE
						counter <= counter + 1;
						valid_for_async <= '1';
					END IF;
					dpram_128x512_rdaddress <= dpram_128x512_rdaddress + 1;
----------------------------------------------------------------------------------
				WHEN OTHERS =>	
				   current_state <= IDLE;
			END CASE;
-----------------------------------------------------------------------------------------
			clock_counter <= clock_counter + 1;
		END IF;
	END PROCESS read_from_bram;

------------------------------------------------------------------------------------------


end architecture testbench;