Info: Generated by version: 21.3 build 170
Info: Starting: Create simulation model
Info: qsys-generate C:\svn\exo_r_c10gx\simulation_bad\async_input_bram_player\async_input_bram_player.ip --simulation=VERILOG --allow-mixed-language-simulation --simulator=MODELSIM --output-directory=C:\svn\exo_r_c10gx\simulation_bad\async_input_bram_player\async_input_bram_player --family="Cyclone 10 GX" --part=10CX105YU484I6G
: async_input_bram_player.ram_1port_0: Targeting device family: Cyclone 10 GX.
: async_input_bram_player.ram_1port_0: In 'Performance Optimization' tab, Cyclone 10 GX does not support 'Timing/Power Optimization' feature.
Info: async_input_bram_player: "Transforming system: async_input_bram_player"
Info: async_input_bram_player: "Naming system components in system: async_input_bram_player"
Info: async_input_bram_player: "Processing generation queue"
Info: async_input_bram_player: "Generating: async_input_bram_player"
Info: async_input_bram_player: "Generating: async_input_bram_player_ram_1port_2010_hohtliq"
Info: async_input_bram_player: Done "async_input_bram_player" with 2 modules, 2 files
Info: Generating the following file(s) for MODELSIM simulator in C:/svn/exo_r_c10gx/simulation_bad/async_input_bram_player/async_input_bram_player/sim/ directory:
Info: 	common/modelsim_files.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/svn/exo_r_c10gx/simulation_bad/async_input_bram_player/async_input_bram_player/sim/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: qsys-generate succeeded.
Info: Finished: Create simulation model
Info: Starting: Create simulation script
Info: sim-script-gen --system-file=C:\svn\exo_r_c10gx\simulation_bad\async_input_bram_player\async_input_bram_player.ip --simulator=MODELSIM --output-directory=C:/svn/exo_r_c10gx/simulation_bad/async_input_bram_player/async_input_bram_player/sim/ --use-relative-paths=true
Info: Generating the following file(s) for MODELSIM simulator in C:/svn/exo_r_c10gx/simulation_bad/async_input_bram_player/async_input_bram_player/sim/ directory:
Info: 	mentor/msim_setup.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/svn/exo_r_c10gx/simulation_bad/async_input_bram_player/async_input_bram_player/sim/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create simulation script
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\svn\exo_r_c10gx\simulation_bad\async_input_bram_player\async_input_bram_player.ip --block-symbol-file --output-directory=C:\svn\exo_r_c10gx\simulation_bad\async_input_bram_player\async_input_bram_player --family="Cyclone 10 GX" --part=10CX105YU484I6G
: async_input_bram_player.ram_1port_0: Targeting device family: Cyclone 10 GX.
: async_input_bram_player.ram_1port_0: In 'Performance Optimization' tab, Cyclone 10 GX does not support 'Timing/Power Optimization' feature.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\svn\exo_r_c10gx\simulation_bad\async_input_bram_player\async_input_bram_player.ip --synthesis=VERILOG --output-directory=C:\svn\exo_r_c10gx\simulation_bad\async_input_bram_player\async_input_bram_player --family="Cyclone 10 GX" --part=10CX105YU484I6G
: async_input_bram_player.ram_1port_0: Targeting device family: Cyclone 10 GX.
: async_input_bram_player.ram_1port_0: In 'Performance Optimization' tab, Cyclone 10 GX does not support 'Timing/Power Optimization' feature.
Info: async_input_bram_player: "Transforming system: async_input_bram_player"
Info: async_input_bram_player: "Naming system components in system: async_input_bram_player"
Info: async_input_bram_player: "Processing generation queue"
Info: async_input_bram_player: "Generating: async_input_bram_player"
Info: async_input_bram_player: "Generating: async_input_bram_player_ram_1port_2010_hohtliq"
Info: async_input_bram_player: Done "async_input_bram_player" with 2 modules, 2 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
Info: Starting: IP-XACT
Info: qsys-generate C:\svn\exo_r_c10gx\simulation_bad\async_input_bram_player\async_input_bram_player.ip --synthesis=VERILOG --ipxact --output-directory=C:\svn\exo_r_c10gx\simulation_bad\async_input_bram_player\async_input_bram_player --family="Cyclone 10 GX" --part=10CX105YU484I6G
Info: Finished: IP-XACT
Info: Starting: Generate IP Core Documentation
Info: No documentation filesets were found for components in async_input_bram_player. No files generated.
Info: Finished: Generate IP Core Documentation
