
proc get_design_libraries {} {
  set libraries [dict create]
  dict set libraries clock_in_0                            1
  dict set libraries ram_2port_2021                        1
  dict set libraries buf_level_cpu_bram                    1
  dict set libraries buf_level_bram                        1
  dict set libraries altera_xcvr_reset_control_1911        1
  dict set libraries reset_control                         1
  dict set libraries altera_common_sv_packages             1
  dict set libraries altera_xcvr_native_a10_191            1
  dict set libraries altera_eth_10gbaser_phy               1
  dict set libraries alt_em10g32_1931                      1
  dict set libraries altera_eth_10g_mac                    1
  dict set libraries altera_iopll_1931                     1
  dict set libraries docsis_pll                            1
  dict set libraries pcr_pll                               1
  dict set libraries altera_xcvr_atx_pll_a10_191           1
  dict set libraries atx_pll                               1
  dict set libraries eth_10base_r_pll                      1
  dict set libraries dpram_128x128                         1
  dict set libraries fifo_1910                             1
  dict set libraries fifo_128x8                            1
  dict set libraries true_dpram_16x128                     1
  dict set libraries true_dual_clock_dpram_16x128          1
  dict set libraries dpram_3x65536                         1
  dict set libraries true_dpram_32x128                     1
  dict set libraries async_i_next_time_del_t_req           1
  dict set libraries true_dpram_64x128                     1
  dict set libraries buffer_counter_min_max_bram           1
  dict set libraries async_i_tin_calc_buf_cnt_request_fifo 1
  dict set libraries fifo_12x128                           1
  dict set libraries lpm_mult_1920                         1
  dict set libraries mult_16_32                            1
  dict set libraries async_i_tin_calc_prev_time_fifo       1
  dict set libraries ddr_read_buffer_fifo                  1
  dict set libraries true_dual_clock_dpram_128x256         1
  dict set libraries packets_on_loan                       1
  dict set libraries lpm_divide_1910                       1
  dict set libraries pcr_divider                           1
  dict set libraries mult_4_32                             1
  dict set libraries fixed_pcr_bram                        1
  dict set libraries dpram_128x32                          1
  dict set libraries avalon_mm_ddr_reset_in                1
  dict set libraries altera_emif_arch_nf_191               1
  dict set libraries altera_avalon_mm_bridge_2001          1
  dict set libraries altera_avalon_onchip_memory2_1931     1
  dict set libraries altera_merlin_master_translator_191   1
  dict set libraries altera_merlin_slave_translator_191    1
  dict set libraries altera_mm_interconnect_1920           1
  dict set libraries altera_reset_controller_1921          1
  dict set libraries altera_emif_cal_slave_nf_191          1
  dict set libraries altera_emif_c10_1910                  1
  dict set libraries avalon_mm_ddr_emif_c10_0              1
  dict set libraries avalon_mm_ddr_mm_bridge_0             1
  dict set libraries avalon_mm_ddr_mm_bridge_2             1
  dict set libraries avalon_mm_ddr_mm_bridge_3             1
  dict set libraries depi_parser_descriptor_fifo           1
  dict set libraries depi_parser_input_bram                1
  dict set libraries depi_parser_ds_dpram                  1
  dict set libraries depi_parser_slot_aloc_dpram           1
  dict set libraries depi_parser_us_dpram                  1
  dict set libraries ram_1port_2010                        1
  dict set libraries per_pid_cc_counter_bram               1
  dict set libraries per_pid_cc_status_dpram               1
  dict set libraries rate_calc_bram                        1
  dict set libraries rate_calc_bram_2clocks                1
  dict set libraries ip_arrival_time_logger_dp_ram         1
  dict set libraries pckt_encap_descriptor                 1
  dict set libraries pckt_encap_header                     1
  dict set libraries pckt_encap_l2tp_udp                   1
  dict set libraries pckt_encap_seq_cnt                    1
  dict set libraries request_arbitter_random_jitter        1
  dict set libraries rx_arbiter_jitter_fifo                1
  dict set libraries request_arbiter_fifo                  1
  dict set libraries rx_arbiter_input_descriptors_fifo     1
  dict set libraries rx_arbiter_input_packets_bram         1
  dict set libraries rx_arbiter_vlan2qam_converter         1
  dict set libraries seq_error_counter_bram                1
  dict set libraries seq_value_bram                        1
  dict set libraries altera_emif_sim_checker_191           1
  dict set libraries ed_sim_sim_checker                    1
  dict set libraries altera_avalon_reset_source_191        1
  dict set libraries ed_sim_global_reset_n_source          1
  dict set libraries ed_sim_emif_c10_0                     1
  dict set libraries altera_emif_tg_avl_191                1
  dict set libraries ed_sim_tg                             1
  dict set libraries altera_emif_mem_model_core_ddr3_191   1
  dict set libraries altera_emif_mem_model_191             1
  dict set libraries ed_sim_mem                            1
  dict set libraries ed_sim_global_reset_n_splitter        1
  dict set libraries altera_avalon_clock_source_191        1
  dict set libraries ed_sim_pll_ref_clk_source             1
  dict set libraries async_input_bram_player               1
  dict set libraries altera_merlin_master_agent_191        1
  dict set libraries altera_merlin_slave_agent_191         1
  dict set libraries altera_avalon_sc_fifo_1930            1
  dict set libraries altera_merlin_router_1920             1
  dict set libraries altera_avalon_st_pipeline_stage_1920  1
  dict set libraries altera_merlin_burst_adapter_1921      1
  dict set libraries altera_merlin_demultiplexer_1921      1
  dict set libraries altera_merlin_multiplexer_1921        1
  dict set libraries altera_merlin_width_adapter_1920      1
  dict set libraries hs_clk_xer_1931                       1
  dict set libraries avalon_mm_ddr                         1
  return $libraries
}

proc get_memory_files {QSYS_SIMDIR} {
  set memory_files [list]
  lappend memory_files "[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/avalon_mm_ddr_emif_c10_0_altera_emif_arch_nf_191_oeywqni_seq_params_sim.hex"]"
  lappend memory_files "[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/avalon_mm_ddr_emif_c10_0_altera_emif_arch_nf_191_oeywqni_seq_params_synth.hex"]"
  lappend memory_files "[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/avalon_mm_ddr_emif_c10_0_altera_emif_arch_nf_191_oeywqni_seq_cal.hex"]"
  lappend memory_files "[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_avalon_onchip_memory2_1931/sim/seq_cal_soft_m20k.hex"]"
  lappend memory_files "[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/ed_sim_emif_c10_0_altera_emif_arch_nf_191_pgy4vhq_seq_params_sim.hex"]"
  lappend memory_files "[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/ed_sim_emif_c10_0_altera_emif_arch_nf_191_pgy4vhq_seq_params_synth.hex"]"
  lappend memory_files "[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/ed_sim_emif_c10_0_altera_emif_arch_nf_191_pgy4vhq_seq_cal.hex"]"
  lappend memory_files "[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_avalon_onchip_memory2_1931/sim/seq_cal_soft_m20k.hex"]"
  return $memory_files
}

proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
  set design_files [dict create]
  dict set design_files "altera_common_sv_packages::altera_xcvr_native_a10_functions_h" "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/altera_xcvr_native_a10_functions_h.sv"]\"  -work altera_common_sv_packages"                 
  dict set design_files "altera_common_sv_packages::avalon_vip_verbosity_pkg"           "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_global_reset_n_source/altera_avalon_reset_source_191/sim/verbosity_pkg.sv"]\"  -work altera_common_sv_packages"
  return $design_files
}

proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
  set design_files [list]
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/clock_in_0/sim/clock_in_0.v"]\"  -work clock_in_0"                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/buf_level_cpu_bram/buf_level_cpu_bram/ram_2port_2021/sim/buf_level_cpu_bram_ram_2port_2021_nsxuwxi.v"]\"  -work ram_2port_2021"                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/buf_level_cpu_bram/buf_level_cpu_bram/sim/buf_level_cpu_bram.v"]\"  -work buf_level_cpu_bram"                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/buf_level_bram/buf_level_bram/ram_2port_2021/sim/buf_level_bram_ram_2port_2021_hpwijwi.v"]\"  -work ram_2port_2021"                                                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/buf_level_bram/buf_level_bram/sim/buf_level_bram.v"]\"  -work buf_level_bram"                                                                                                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/xcvr_reset_controller/reset_control/altera_xcvr_reset_control_1911/sim/altera_xcvr_functions.sv"]\"  -work altera_xcvr_reset_control_1911"                                                                 
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/xcvr_reset_controller/reset_control/altera_xcvr_reset_control_1911/sim/alt_xcvr_resync.sv"]\"  -work altera_xcvr_reset_control_1911"                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/xcvr_reset_controller/reset_control/altera_xcvr_reset_control_1911/sim/altera_xcvr_reset_control.sv"]\"  -work altera_xcvr_reset_control_1911"                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/xcvr_reset_controller/reset_control/altera_xcvr_reset_control_1911/sim/alt_xcvr_reset_counter.sv"]\"  -work altera_xcvr_reset_control_1911"                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/xcvr_reset_controller/reset_control/sim/reset_control.v"]\"  -work reset_control"                                                                                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_resync.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_arbiter.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                          
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/twentynm_pcs.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/twentynm_pma.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/twentynm_xcvr_avmm.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/twentynm_xcvr_native.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/a10_avmm_h.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_pipe_retry.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_avmm_csr.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_prbs_accum.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_odi_accel.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                 
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_arb.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/altera_xcvr_native_pcie_dfe_params_h.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_commands_h.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_functions_h.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_program.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_cpu.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/pcie_mgmt_master.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                                          
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/altera_xcvr_native_pcie_dfe_ip.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                            
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/altera_eth_10gbaser_phy_altera_xcvr_native_a10_191_bvlalya.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_bvlalya.sv"]\" -l altera_common_sv_packages -work altera_xcvr_native_a10_191"                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/phy/altera_eth_10gbaser_phy/sim/altera_eth_10gbaser_phy.v"]\"  -work altera_eth_10gbaser_phy"                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/alt_em10g32.v"]\"  -work alt_em10g32_1931"                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/alt_em10g32unit.v"]\"  -work alt_em10g32_1931"                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_clk_rst.v"]\"  -work alt_em10g32_1931"                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_clock_crosser.v"]\"  -work alt_em10g32_1931"                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_crc32.v"]\"  -work alt_em10g32_1931"                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_crc32_gf_mult32_kc.v"]\"  -work alt_em10g32_1931"                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_creg_map.v"]\"  -work alt_em10g32_1931"                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_creg_top.v"]\"  -work alt_em10g32_1931"                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_frm_decoder.v"]\"  -work alt_em10g32_1931"                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v"]\"  -work alt_em10g32_1931"                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_pipeline_base.v"]\"  -work alt_em10g32_1931"                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_reset_synchronizer.v"]\"  -work alt_em10g32_1931"                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rr_clock_crosser.v"]\"  -work alt_em10g32_1931"                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rst_cnt.v"]\"  -work alt_em10g32_1931"                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v"]\"  -work alt_em10g32_1931"                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_fctl_overflow.v"]\"  -work alt_em10g32_1931"                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_fctl_preamble.v"]\"  -work alt_em10g32_1931"                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_frm_control.v"]\"  -work alt_em10g32_1931"                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_pfc_flow_control.v"]\"  -work alt_em10g32_1931"                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_pfc_pause_conversion.v"]\"  -work alt_em10g32_1931"                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_pkt_backpressure_control.v"]\"  -work alt_em10g32_1931"                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_rs_gmii16b.v"]\"  -work alt_em10g32_1931"                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_rs_gmii16b_top.v"]\"  -work alt_em10g32_1931"                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_rs_gmii_mii.v"]\"  -work alt_em10g32_1931"                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_rs_layer.v"]\"  -work alt_em10g32_1931"                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_rs_xgmii.v"]\"  -work alt_em10g32_1931"                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_status_aligner.v"]\"  -work alt_em10g32_1931"                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_top.v"]\"  -work alt_em10g32_1931"                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_stat_mem.v"]\"  -work alt_em10g32_1931"                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_stat_reg.v"]\"  -work alt_em10g32_1931"                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_data_frm_gen.v"]\"  -work alt_em10g32_1931"                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_srcaddr_inserter.v"]\"  -work alt_em10g32_1931"                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_err_aligner.v"]\"  -work alt_em10g32_1931"                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_flow_control.v"]\"  -work alt_em10g32_1931"                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_frm_arbiter.v"]\"  -work alt_em10g32_1931"                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_frm_muxer.v"]\"  -work alt_em10g32_1931"                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_pause_beat_conversion.v"]\"  -work alt_em10g32_1931"                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_pause_frm_gen.v"]\"  -work alt_em10g32_1931"                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_pause_req.v"]\"  -work alt_em10g32_1931"                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_pfc_frm_gen.v"]\"  -work alt_em10g32_1931"                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rr_buffer.v"]\"  -work alt_em10g32_1931"                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_rs_gmii16b.v"]\"  -work alt_em10g32_1931"                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_rs_gmii16b_top.v"]\"  -work alt_em10g32_1931"                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_rs_layer.v"]\"  -work alt_em10g32_1931"                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_rs_xgmii_layer.v"]\"  -work alt_em10g32_1931"                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_sc_fifo.v"]\"  -work alt_em10g32_1931"                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_top.v"]\"  -work alt_em10g32_1931"                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_gmii_decoder.v"]\"  -work alt_em10g32_1931"                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_gmii_decoder_dfa.v"]\"  -work alt_em10g32_1931"                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_gmii_encoder.v"]\"  -work alt_em10g32_1931"                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_gmii_encoder_dfa.v"]\"  -work alt_em10g32_1931"                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v"]\"  -work alt_em10g32_1931"                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v"]\"  -work alt_em10g32_1931"                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v"]\"  -work alt_em10g32_1931"                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v"]\"  -work alt_em10g32_1931"                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v"]\"  -work alt_em10g32_1931"                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v"]\"  -work alt_em10g32_1931"                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v"]\"  -work alt_em10g32_1931"                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_avalon_st_adapter/alt_em10g32_vldpkt_rddly.v"]\"  -work alt_em10g32_1931"                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v"]\"  -work alt_em10g32_1931"                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v"]\"  -work alt_em10g32_1931"                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v"]\"  -work alt_em10g32_1931"                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser.v"]\"  -work alt_em10g32_1931"                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_avalon_st_adapter/altera_eth_sideband_crosser_sync.v"]\"  -work alt_em10g32_1931"                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v"]\"  -work alt_em10g32_1931"                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v"]\"  -work alt_em10g32_1931"                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v"]\"  -work alt_em10g32_1931"                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_32_to_64_xgmii_conversion.v"]\"  -work alt_em10g32_1931"                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_dcfifo_64_to_32_xgmii_conversion.v"]\"  -work alt_em10g32_1931"                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_32_to_64_adapter.v"]\"  -work alt_em10g32_1931"                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_64_to_32_adapter.v"]\"  -work alt_em10g32_1931"                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/adapters/altera_eth_xgmii_data_format_adapter/alt_em10g32_xgmii_data_format_adapter.v"]\"  -work alt_em10g32_1931"                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_altsyncram_bundle.v"]\"  -work alt_em10g32_1931"                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_altsyncram.v"]\"  -work alt_em10g32_1931"                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_avalon_dc_fifo_lat_calc.v"]\"  -work alt_em10g32_1931"                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_avalon_dc_fifo_hecc.v"]\"  -work alt_em10g32_1931"                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_avalon_dc_fifo_secc.v"]\"  -work alt_em10g32_1931"                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_avalon_sc_fifo.v"]\"  -work alt_em10g32_1931"                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_avalon_sc_fifo_hecc.v"]\"  -work alt_em10g32_1931"                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_avalon_sc_fifo_secc.v"]\"  -work alt_em10g32_1931"                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_ecc_dec_18_12.v"]\"  -work alt_em10g32_1931"                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_ecc_dec_39_32.v"]\"  -work alt_em10g32_1931"                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_ecc_enc_12_18.v"]\"  -work alt_em10g32_1931"                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_ecc_enc_32_39.v"]\"  -work alt_em10g32_1931"                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_rs_xgmii_layer_ultra.v"]\"  -work alt_em10g32_1931"                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_rs_xgmii_ultra.v"]\"  -work alt_em10g32_1931"                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_avst_to_gmii_if.v"]\"  -work alt_em10g32_1931"                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_gmii_to_avst_if.v"]\"  -work alt_em10g32_1931"                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_gmii_tsu.v"]\"  -work alt_em10g32_1931"                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_gmii16b_tsu.v"]\"  -work alt_em10g32_1931"                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_lpm_mult.v"]\"  -work alt_em10g32_1931"                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_ptp_aligner.v"]\"  -work alt_em10g32_1931"                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_ptp_detector.v"]\"  -work alt_em10g32_1931"                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_rx_ptp_top.v"]\"  -work alt_em10g32_1931"                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_gmii_crc_inserter.v"]\"  -work alt_em10g32_1931"                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_gmii16b_crc_inserter.v"]\"  -work alt_em10g32_1931"                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_gmii_ptp_inserter.v"]\"  -work alt_em10g32_1931"                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_gmii16b_ptp_inserter.v"]\"  -work alt_em10g32_1931"                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_gmii16b_ptp_inserter_1g2p5g10g.v"]\"  -work alt_em10g32_1931"                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_ptp_processor.v"]\"  -work alt_em10g32_1931"                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_ptp_top.v"]\"  -work alt_em10g32_1931"                                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_xgmii_crc_inserter.v"]\"  -work alt_em10g32_1931"                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v"]\"  -work alt_em10g32_1931"                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_xgmii_tsu.v"]\"  -work alt_em10g32_1931"                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_crc328generator.v"]\"  -work alt_em10g32_1931"                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_crc32ctl8.v"]\"  -work alt_em10g32_1931"                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_crc32galois8.v"]\"  -work alt_em10g32_1931"                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_gmii_crc_inserter.v"]\"  -work alt_em10g32_1931"                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_gmii16b_crc_inserter.v"]\"  -work alt_em10g32_1931"                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/aldec/rtl/alt_em10g32_gmii16b_crc32.v"]\"  -work alt_em10g32_1931"                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/alt_em10g32_avalon_dc_fifo.v"]\"  -work alt_em10g32_1931"                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/alt_em10g32_dcfifo_synchronizer_bundle.v"]\"  -work alt_em10g32_1931"                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/alt_em10g32_std_synchronizer.v"]\"  -work alt_em10g32_1931"                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/alt_em10g32_1931/sim/altera_std_synchronizer_nocut.v"]\"  -work alt_em10g32_1931"                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/altera_eth_10g_mac_base_r_wrap/mac/altera_eth_10g_mac/sim/altera_eth_10g_mac.v"]\"  -work altera_eth_10g_mac"                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/docsis_pll/docsis_pll/altera_iopll_1931/sim/docsis_pll_altera_iopll_1931_c7g762y.vo"]\"  -work altera_iopll_1931"                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/docsis_pll/docsis_pll/sim/docsis_pll.v"]\"  -work docsis_pll"                                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/pcr_pll/pcr_pll/altera_iopll_1931/sim/pcr_pll_altera_iopll_1931_vxwntya.vo"]\"  -work altera_iopll_1931"                                                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/pcr_pll/pcr_pll/sim/pcr_pll.v"]\"  -work pcr_pll"                                                                                                                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/atx_pll/atx_pll/altera_xcvr_atx_pll_a10_191/sim/twentynm_xcvr_avmm.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191"                                                                                                 
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/atx_pll/atx_pll/altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_resync.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191"                                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/atx_pll/atx_pll/altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_arbiter.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191"                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/atx_pll/atx_pll/altera_xcvr_atx_pll_a10_191/sim/a10_avmm_h.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191"                                                                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/atx_pll/atx_pll/altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_atx_pll_rcfg_arb.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191"                                                                                          
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/atx_pll/atx_pll/altera_xcvr_atx_pll_a10_191/sim/a10_xcvr_atx_pll.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191"                                                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/atx_pll/atx_pll/altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_pll_embedded_debug.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191"                                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/atx_pll/atx_pll/altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_pll_avmm_csr.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191"                                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/atx_pll/atx_pll/altera_xcvr_atx_pll_a10_191/sim/atx_pll_altera_xcvr_atx_pll_a10_191_bhkzg4a.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191"                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/atx_pll/atx_pll/altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_atx_pll_rcfg_opt_logic_bhkzg4a.sv"]\" -l altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191"                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/atx_pll/atx_pll/sim/atx_pll.v"]\"  -work atx_pll"                                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/eth_10base_r_pll/eth_10base_r_pll/altera_iopll_1931/sim/eth_10base_r_pll_altera_iopll_1931_2a65c4i.vo"]\"  -work altera_iopll_1931"                                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/eth_10base_r_pll/eth_10base_r_pll/sim/eth_10base_r_pll.v"]\"  -work eth_10base_r_pll"                                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/dpram_128x128/dpram_128x128/ram_2port_2021/sim/dpram_128x128_ram_2port_2021_vp4jzdq.v"]\"  -work ram_2port_2021"                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/dpram_128x128/dpram_128x128/sim/dpram_128x128.v"]\"  -work dpram_128x128"                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/dc_fifo_128x8/fifo_128x8/fifo_1910/sim/fifo_128x8_fifo_1910_t4i6dna.v"]\"  -work fifo_1910"                                                                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/dc_fifo_128x8/fifo_128x8/sim/fifo_128x8.v"]\"  -work fifo_128x8"                                                                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/true_dpram_16x128/true_dpram_16x128/ram_2port_2021/sim/true_dpram_16x128_ram_2port_2021_3wuebta.v"]\"  -work ram_2port_2021"                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/true_dpram_16x128/true_dpram_16x128/sim/true_dpram_16x128.v"]\"  -work true_dpram_16x128"                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/true_dual_clock_dpram_16x128/true_dual_clock_dpram_16x128/ram_2port_2021/sim/true_dual_clock_dpram_16x128_ram_2port_2021_n3be4bi.v"]\"  -work ram_2port_2021"                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/true_dual_clock_dpram_16x128/true_dual_clock_dpram_16x128/sim/true_dual_clock_dpram_16x128.v"]\"  -work true_dual_clock_dpram_16x128"                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/dpram_3x65536/dpram_3x65536/ram_2port_2021/sim/dpram_3x65536_ram_2port_2021_imef7oq.v"]\"  -work ram_2port_2021"                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/dpram_3x65536/dpram_3x65536/sim/dpram_3x65536.v"]\"  -work dpram_3x65536"                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/true_dpram_32x128/true_dpram_32x128/ram_2port_2021/sim/true_dpram_32x128_ram_2port_2021_ddn2ijq.v"]\"  -work ram_2port_2021"                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/true_dpram_32x128/true_dpram_32x128/sim/true_dpram_32x128.v"]\"  -work true_dpram_32x128"                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/async_i_next_time_del_t_req/async_i_next_time_del_t_req/fifo_1910/sim/async_i_next_time_del_t_req_fifo_1910_cplc7xy.v"]\"  -work fifo_1910"                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/async_i_next_time_del_t_req/async_i_next_time_del_t_req/sim/async_i_next_time_del_t_req.v"]\"  -work async_i_next_time_del_t_req"                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/true_dpram_64x128/true_dpram_64x128/ram_2port_2021/sim/true_dpram_64x128_ram_2port_2021_q4exa5i.v"]\"  -work ram_2port_2021"                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/true_dpram_64x128/true_dpram_64x128/sim/true_dpram_64x128.v"]\"  -work true_dpram_64x128"                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/buffer_counter_min_max_bram/buffer_counter_min_max_bram/ram_2port_2021/sim/buffer_counter_min_max_bram_ram_2port_2021_yjtvuga.v"]\"  -work ram_2port_2021"                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/buffer_counter_min_max_bram/buffer_counter_min_max_bram/sim/buffer_counter_min_max_bram.v"]\"  -work buffer_counter_min_max_bram"                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/async_i_tin_calc_buf_cnt_request_fifo/async_i_tin_calc_buf_cnt_request_fifo/fifo_1910/sim/async_i_tin_calc_buf_cnt_request_fifo_fifo_1910_zqizpaa.v"]\"  -work fifo_1910"                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/async_i_tin_calc_buf_cnt_request_fifo/async_i_tin_calc_buf_cnt_request_fifo/sim/async_i_tin_calc_buf_cnt_request_fifo.v"]\"  -work async_i_tin_calc_buf_cnt_request_fifo"                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/dc_fifo_12x128/fifo_12x128/fifo_1910/sim/fifo_12x128_fifo_1910_zqizpaa.v"]\"  -work fifo_1910"                                                                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/dc_fifo_12x128/fifo_12x128/sim/fifo_12x128.v"]\"  -work fifo_12x128"                                                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/mult_16_32/mult_16_32/lpm_mult_1920/sim/mult_16_32_lpm_mult_1920_3y2e7iy.v"]\"  -work lpm_mult_1920"                                                                                                                                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/mult_16_32/mult_16_32/sim/mult_16_32.v"]\"  -work mult_16_32"                                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/async_i_tin_calc_prev_time_fifo/async_i_tin_calc_prev_time_fifo/fifo_1910/sim/async_i_tin_calc_prev_time_fifo_fifo_1910_bz66vki.v"]\"  -work fifo_1910"                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/async_i_tin_calc_prev_time_fifo/async_i_tin_calc_prev_time_fifo/sim/async_i_tin_calc_prev_time_fifo.v"]\"  -work async_i_tin_calc_prev_time_fifo"                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/ddr_read_buffer_fifo/ddr_read_buffer_fifo/fifo_1910/sim/ddr_read_buffer_fifo_fifo_1910_aqaycqa.v"]\"  -work fifo_1910"                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/ddr_read_buffer_fifo/ddr_read_buffer_fifo/sim/ddr_read_buffer_fifo.v"]\"  -work ddr_read_buffer_fifo"                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/true_dual_clock_dpram_128x256/true_dual_clock_dpram_128x256/ram_2port_2021/sim/true_dual_clock_dpram_128x256_ram_2port_2021_agz2ubq.v"]\"  -work ram_2port_2021"                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/true_dual_clock_dpram_128x256/true_dual_clock_dpram_128x256/sim/true_dual_clock_dpram_128x256.v"]\"  -work true_dual_clock_dpram_128x256"                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/packets_on_loan/packets_on_loan/ram_2port_2021/sim/packets_on_loan_ram_2port_2021_m7wvvzq.v"]\"  -work ram_2port_2021"                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/packets_on_loan/packets_on_loan/sim/packets_on_loan.v"]\"  -work packets_on_loan"                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/pcr_divider/pcr_divider/lpm_divide_1910/sim/pcr_divider_lpm_divide_1910_b6fmqia.v"]\"  -work lpm_divide_1910"                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/pcr_divider/pcr_divider/sim/pcr_divider.v"]\"  -work pcr_divider"                                                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/mult_4_32/mult_4_32/lpm_mult_1920/sim/mult_4_32_lpm_mult_1920_alq2vka.v"]\"  -work lpm_mult_1920"                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/mult_4_32/mult_4_32/sim/mult_4_32.v"]\"  -work mult_4_32"                                                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/fixed_pcr_bram/fixed_pcr_bram/ram_2port_2021/sim/fixed_pcr_bram_ram_2port_2021_4lhloma.v"]\"  -work ram_2port_2021"                                                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/fixed_pcr_bram/fixed_pcr_bram/sim/fixed_pcr_bram.v"]\"  -work fixed_pcr_bram"                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/dpram_128x32/dpram_128x32/ram_2port_2021/sim/dpram_128x32_ram_2port_2021_7jmv4yi.v"]\"  -work ram_2port_2021"                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/dpram_128x32/dpram_128x32/sim/dpram_128x32.v"]\"  -work dpram_128x32"                                                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_reset_in/sim/avalon_mm_ddr_reset_in.v"]\"  -work avalon_mm_ddr_reset_in"                                                                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/avalon_mm_ddr_emif_c10_0_altera_emif_arch_nf_191_oeywqni_top.sv"]\"  -work altera_emif_arch_nf_191"                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/avalon_mm_ddr_emif_c10_0_altera_emif_arch_nf_191_oeywqni_io_aux.sv"]\"  -work altera_emif_arch_nf_191"                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_oct.sv"]\"  -work altera_emif_arch_nf_191"                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_df_o.sv"]\"  -work altera_emif_arch_nf_191"                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_bdir_df.sv"]\"  -work altera_emif_arch_nf_191"                                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_bdir_se.sv"]\"  -work altera_emif_arch_nf_191"                                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_cp_i.sv"]\"  -work altera_emif_arch_nf_191"                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_df_i.sv"]\"  -work altera_emif_arch_nf_191"                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_se_i.sv"]\"  -work altera_emif_arch_nf_191"                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_se_o.sv"]\"  -work altera_emif_arch_nf_191"                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_core_clks_rsts.sv"]\"  -work altera_emif_arch_nf_191"                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_io_tiles.sv"]\"  -work altera_emif_arch_nf_191"                                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_io_tiles_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_pll.sv"]\"  -work altera_emif_arch_nf_191"                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/cyclone10gx_io_12_lane_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/cyclone10gx_io_12_lane_encrypted_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/cyclone10gx_io_12_lane_nf5es_encrypted_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_bufs.sv"]\"  -work altera_emif_arch_nf_191"                                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_unused.sv"]\"  -work altera_emif_arch_nf_191"                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_cal_counter.sv"]\"  -work altera_emif_arch_nf_191"                                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_pll_fast_sim.sv"]\"  -work altera_emif_arch_nf_191"                                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_pll_extra_clks.sv"]\"  -work altera_emif_arch_nf_191"                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hps_clks_rsts.sv"]\"  -work altera_emif_arch_nf_191"                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_io_tiles_wrap.sv"]\"  -work altera_emif_arch_nf_191"                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_abphy_mux.sv"]\"  -work altera_emif_arch_nf_191"                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_avl_if.sv"]\"  -work altera_emif_arch_nf_191"                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_sideband_if.sv"]\"  -work altera_emif_arch_nf_191"                                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_mmr_if.sv"]\"  -work altera_emif_arch_nf_191"                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_amm_data_if.sv"]\"  -work altera_emif_arch_nf_191"                                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_ast_data_if.sv"]\"  -work altera_emif_arch_nf_191"                                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_afi_if.sv"]\"  -work altera_emif_arch_nf_191"                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_seq_if.sv"]\"  -work altera_emif_arch_nf_191"                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_regs.sv"]\"  -work altera_emif_arch_nf_191"                                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_oct.sv"]\"  -work altera_emif_arch_nf_191"                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_oct_um_fsm.sv"]\"  -work altera_emif_arch_nf_191"                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/altera_std_synchronizer_nocut.v"]\"  -work altera_emif_arch_nf_191"                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/mem_array_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/io_12_lane_bcm__nf5es_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                                                          
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/io_12_lane__nf5es_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_arch_nf_191/sim/avalon_mm_ddr_emif_c10_0_altera_emif_arch_nf_191_oeywqni.sv"]\"  -work altera_emif_arch_nf_191"                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_avalon_mm_bridge_2001/sim/avalon_mm_ddr_emif_c10_0_altera_avalon_mm_bridge_2001_k2bg7dq.v"]\"  -work altera_avalon_mm_bridge_2001"                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_avalon_onchip_memory2_1931/sim/avalon_mm_ddr_emif_c10_0_altera_avalon_onchip_memory2_1931_ecie4wq.v"]\"  -work altera_avalon_onchip_memory2_1931"           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_merlin_master_translator_191/sim/avalon_mm_ddr_emif_c10_0_altera_merlin_master_translator_191_g7h47bq.sv"]\"  -work altera_merlin_master_translator_191"         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_merlin_slave_translator_191/sim/avalon_mm_ddr_emif_c10_0_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_mm_interconnect_1920/sim/avalon_mm_ddr_emif_c10_0_altera_mm_interconnect_1920_trcm3ta.v"]\"  -work altera_mm_interconnect_1920"                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_reset_controller_1921/sim/altera_reset_controller.v"]\"  -work altera_reset_controller_1921"                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_reset_controller_1921/sim/altera_reset_synchronizer.v"]\"  -work altera_reset_controller_1921"                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_cal_slave_nf_191/sim/avalon_mm_ddr_emif_c10_0_altera_emif_cal_slave_nf_191_rmzieji.v"]\"  -work altera_emif_cal_slave_nf_191"                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/altera_emif_c10_1910/sim/avalon_mm_ddr_emif_c10_0_altera_emif_c10_1910_ninihwi.v"]\"  -work altera_emif_c10_1910"                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_emif_c10_0/sim/avalon_mm_ddr_emif_c10_0.v"]\"  -work avalon_mm_ddr_emif_c10_0"                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_mm_bridge_0/altera_avalon_mm_bridge_2001/sim/avalon_mm_ddr_mm_bridge_0_altera_avalon_mm_bridge_2001_lkfzu4y.v"]\"  -work altera_avalon_mm_bridge_2001"                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_mm_bridge_0/sim/avalon_mm_ddr_mm_bridge_0.v"]\"  -work avalon_mm_ddr_mm_bridge_0"                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_mm_bridge_2/altera_avalon_mm_bridge_2001/sim/avalon_mm_ddr_mm_bridge_2_altera_avalon_mm_bridge_2001_lkfzu4y.v"]\"  -work altera_avalon_mm_bridge_2001"                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_mm_bridge_2/sim/avalon_mm_ddr_mm_bridge_2.v"]\"  -work avalon_mm_ddr_mm_bridge_2"                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_mm_bridge_3/altera_avalon_mm_bridge_2001/sim/avalon_mm_ddr_mm_bridge_3_altera_avalon_mm_bridge_2001_lkfzu4y.v"]\"  -work altera_avalon_mm_bridge_2001"                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/ip/avalon_mm_ddr/avalon_mm_ddr_mm_bridge_3/sim/avalon_mm_ddr_mm_bridge_3.v"]\"  -work avalon_mm_ddr_mm_bridge_3"                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/depi_parser_descriptor_fifo/depi_parser_descriptor_fifo/fifo_1910/sim/depi_parser_descriptor_fifo_fifo_1910_5w6e2wy.v"]\"  -work fifo_1910"                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/depi_parser_descriptor_fifo/depi_parser_descriptor_fifo/sim/depi_parser_descriptor_fifo.v"]\"  -work depi_parser_descriptor_fifo"                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/depi_parser_input_bram/depi_parser_input_bram/ram_2port_2021/sim/depi_parser_input_bram_ram_2port_2021_aytevnq.v"]\"  -work ram_2port_2021"                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/depi_parser_input_bram/depi_parser_input_bram/sim/depi_parser_input_bram.v"]\"  -work depi_parser_input_bram"                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/depi_parser_ds_dpram/depi_parser_ds_dpram/ram_2port_2021/sim/depi_parser_ds_dpram_ram_2port_2021_hmp54ry.v"]\"  -work ram_2port_2021"                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/depi_parser_ds_dpram/depi_parser_ds_dpram/sim/depi_parser_ds_dpram.v"]\"  -work depi_parser_ds_dpram"                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/depi_parser_slot_aloc_dpram/depi_parser_slot_aloc_dpram/ram_2port_2021/sim/depi_parser_slot_aloc_dpram_ram_2port_2021_4ahel7q.v"]\"  -work ram_2port_2021"                                                                           
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/depi_parser_slot_aloc_dpram/depi_parser_slot_aloc_dpram/sim/depi_parser_slot_aloc_dpram.v"]\"  -work depi_parser_slot_aloc_dpram"                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/depi_parser_us_dpram/depi_parser_us_dpram/ram_2port_2021/sim/depi_parser_us_dpram_ram_2port_2021_x3bchzy.v"]\"  -work ram_2port_2021"                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/depi_parser_us_dpram/depi_parser_us_dpram/sim/depi_parser_us_dpram.v"]\"  -work depi_parser_us_dpram"                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/per_pid_cc_counter_bram/per_pid_cc_counter_bram/ram_1port_2010/sim/per_pid_cc_counter_bram_ram_1port_2010_rsbllza.v"]\"  -work ram_1port_2010"                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/per_pid_cc_counter_bram/per_pid_cc_counter_bram/sim/per_pid_cc_counter_bram.v"]\"  -work per_pid_cc_counter_bram"                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/per_pid_cc_status_dpram/per_pid_cc_status_dpram/ram_2port_2021/sim/per_pid_cc_status_dpram_ram_2port_2021_5p6yj5q.v"]\"  -work ram_2port_2021"                                                                                       
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/per_pid_cc_status_dpram/per_pid_cc_status_dpram/sim/per_pid_cc_status_dpram.v"]\"  -work per_pid_cc_status_dpram"                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/rate_calc_bram/rate_calc_bram/ram_2port_2021/sim/rate_calc_bram_ram_2port_2021_6qio4qi.v"]\"  -work ram_2port_2021"                                                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/rate_calc_bram/rate_calc_bram/sim/rate_calc_bram.v"]\"  -work rate_calc_bram"                                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/rate_calc_bram_2clocks/rate_calc_bram_2clocks/ram_2port_2021/sim/rate_calc_bram_2clocks_ram_2port_2021_3t6q75y.v"]\"  -work ram_2port_2021"                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/rate_calc_bram_2clocks/rate_calc_bram_2clocks/sim/rate_calc_bram_2clocks.v"]\"  -work rate_calc_bram_2clocks"                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/ip_arrival_time_logger_dp_ram/ip_arrival_time_logger_dp_ram/ram_2port_2021/sim/ip_arrival_time_logger_dp_ram_ram_2port_2021_yllzqna.v"]\"  -work ram_2port_2021"                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/ip_arrival_time_logger_dp_ram/ip_arrival_time_logger_dp_ram/sim/ip_arrival_time_logger_dp_ram.v"]\"  -work ip_arrival_time_logger_dp_ram"                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/pckt_encap_descriptor/pckt_encap_descriptor/ram_2port_2021/sim/pckt_encap_descriptor_ram_2port_2021_omfz2ki.v"]\"  -work ram_2port_2021"                                                                                             
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/pckt_encap_descriptor/pckt_encap_descriptor/sim/pckt_encap_descriptor.v"]\"  -work pckt_encap_descriptor"                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/pckt_encap_header/pckt_encap_header/ram_2port_2021/sim/pckt_encap_header_ram_2port_2021_l3qcapa.v"]\"  -work ram_2port_2021"                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/pckt_encap_header/pckt_encap_header/sim/pckt_encap_header.v"]\"  -work pckt_encap_header"                                                                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/pckt_encap_l2tp_udp/pckt_encap_l2tp_udp/ram_2port_2021/sim/pckt_encap_l2tp_udp_ram_2port_2021_czmipza.v"]\"  -work ram_2port_2021"                                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/pckt_encap_l2tp_udp/pckt_encap_l2tp_udp/sim/pckt_encap_l2tp_udp.v"]\"  -work pckt_encap_l2tp_udp"                                                                                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/pckt_encap_seq_cnt/pckt_encap_seq_cnt/ram_1port_2010/sim/pckt_encap_seq_cnt_ram_1port_2010_xmnujia.v"]\"  -work ram_1port_2010"                                                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/pckt_encap_seq_cnt/pckt_encap_seq_cnt/sim/pckt_encap_seq_cnt.v"]\"  -work pckt_encap_seq_cnt"                                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/request_arbitter_random_jitter/request_arbitter_random_jitter/ram_2port_2021/sim/request_arbitter_random_jitter_ram_2port_2021_vy6stgq.v"]\"  -work ram_2port_2021"                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/request_arbitter_random_jitter/request_arbitter_random_jitter/sim/request_arbitter_random_jitter.v"]\"  -work request_arbitter_random_jitter"                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/rx_arbiter_jitter_fifo/rx_arbiter_jitter_fifo/fifo_1910/sim/rx_arbiter_jitter_fifo_fifo_1910_lyj6fbi.v"]\"  -work fifo_1910"                                                                                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/rx_arbiter_jitter_fifo/rx_arbiter_jitter_fifo/sim/rx_arbiter_jitter_fifo.v"]\"  -work rx_arbiter_jitter_fifo"                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/request_arbiter_fifo/request_arbiter_fifo/fifo_1910/sim/request_arbiter_fifo_fifo_1910_tirihci.v"]\"  -work fifo_1910"                                                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/request_arbiter_fifo/request_arbiter_fifo/sim/request_arbiter_fifo.v"]\"  -work request_arbiter_fifo"                                                                                                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/rx_arbiter_input_descriptors_fifo/rx_arbiter_input_descriptors_fifo/fifo_1910/sim/rx_arbiter_input_descriptors_fifo_fifo_1910_cngc3pi.v"]\"  -work fifo_1910"                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/rx_arbiter_input_descriptors_fifo/rx_arbiter_input_descriptors_fifo/sim/rx_arbiter_input_descriptors_fifo.v"]\"  -work rx_arbiter_input_descriptors_fifo"                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/rx_arbiter_input_packets_bram/rx_arbiter_input_packets_bram/ram_2port_2021/sim/rx_arbiter_input_packets_bram_ram_2port_2021_h5lfm5q.v"]\"  -work ram_2port_2021"                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/rx_arbiter_input_packets_bram/rx_arbiter_input_packets_bram/sim/rx_arbiter_input_packets_bram.v"]\"  -work rx_arbiter_input_packets_bram"                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/rx_arbiter_vlan2qam_converter/rx_arbiter_vlan2qam_converter/ram_2port_2021/sim/rx_arbiter_vlan2qam_converter_ram_2port_2021_ziwwtuq.v"]\"  -work ram_2port_2021"                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/rx_arbiter_vlan2qam_converter/rx_arbiter_vlan2qam_converter/sim/rx_arbiter_vlan2qam_converter.v"]\"  -work rx_arbiter_vlan2qam_converter"                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/seq_error_counter_bram/seq_error_counter_bram/ram_2port_2021/sim/seq_error_counter_bram_ram_2port_2021_34unmxi.v"]\"  -work ram_2port_2021"                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/seq_error_counter_bram/seq_error_counter_bram/sim/seq_error_counter_bram.v"]\"  -work seq_error_counter_bram"                                                                                                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/seq_value_bram/seq_value_bram/ram_2port_2021/sim/seq_value_bram_ram_2port_2021_5ehsryi.v"]\"  -work ram_2port_2021"                                                                                                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/seq_value_bram/seq_value_bram/sim/seq_value_bram.v"]\"  -work seq_value_bram"                                                                                                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_sim_checker/altera_emif_sim_checker_191/sim/altera_emif_sim_checker.sv"]\"  -work altera_emif_sim_checker_191"                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_sim_checker/sim/ed_sim_sim_checker.v"]\"  -work ed_sim_sim_checker"                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_global_reset_n_source/altera_avalon_reset_source_191/sim/altera_avalon_reset_source.sv"]\" -l altera_common_sv_packages -work altera_avalon_reset_source_191"      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_global_reset_n_source/sim/ed_sim_global_reset_n_source.v"]\"  -work ed_sim_global_reset_n_source"                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/ed_sim_emif_c10_0_altera_emif_arch_nf_191_pgy4vhq_top.sv"]\"  -work altera_emif_arch_nf_191"                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/ed_sim_emif_c10_0_altera_emif_arch_nf_191_pgy4vhq_io_aux.sv"]\"  -work altera_emif_arch_nf_191"                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_oct.sv"]\"  -work altera_emif_arch_nf_191"                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_df_o.sv"]\"  -work altera_emif_arch_nf_191"                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_bdir_df.sv"]\"  -work altera_emif_arch_nf_191"                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_bdir_se.sv"]\"  -work altera_emif_arch_nf_191"                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_cp_i.sv"]\"  -work altera_emif_arch_nf_191"                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_df_i.sv"]\"  -work altera_emif_arch_nf_191"                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_se_i.sv"]\"  -work altera_emif_arch_nf_191"                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_udir_se_o.sv"]\"  -work altera_emif_arch_nf_191"                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_core_clks_rsts.sv"]\"  -work altera_emif_arch_nf_191"                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_io_tiles.sv"]\"  -work altera_emif_arch_nf_191"                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_io_tiles_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_pll.sv"]\"  -work altera_emif_arch_nf_191"                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/cyclone10gx_io_12_lane_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/cyclone10gx_io_12_lane_encrypted_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/cyclone10gx_io_12_lane_nf5es_encrypted_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_bufs.sv"]\"  -work altera_emif_arch_nf_191"                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_buf_unused.sv"]\"  -work altera_emif_arch_nf_191"                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_cal_counter.sv"]\"  -work altera_emif_arch_nf_191"                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_pll_fast_sim.sv"]\"  -work altera_emif_arch_nf_191"                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_pll_extra_clks.sv"]\"  -work altera_emif_arch_nf_191"                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hps_clks_rsts.sv"]\"  -work altera_emif_arch_nf_191"                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_io_tiles_wrap.sv"]\"  -work altera_emif_arch_nf_191"                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_abphy_mux.sv"]\"  -work altera_emif_arch_nf_191"                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_avl_if.sv"]\"  -work altera_emif_arch_nf_191"                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_sideband_if.sv"]\"  -work altera_emif_arch_nf_191"                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_mmr_if.sv"]\"  -work altera_emif_arch_nf_191"                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_amm_data_if.sv"]\"  -work altera_emif_arch_nf_191"                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_hmc_ast_data_if.sv"]\"  -work altera_emif_arch_nf_191"                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_afi_if.sv"]\"  -work altera_emif_arch_nf_191"                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_seq_if.sv"]\"  -work altera_emif_arch_nf_191"                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_emif_arch_nf_regs.sv"]\"  -work altera_emif_arch_nf_191"                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_oct.sv"]\"  -work altera_emif_arch_nf_191"                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_oct_um_fsm.sv"]\"  -work altera_emif_arch_nf_191"                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/altera_std_synchronizer_nocut.v"]\"  -work altera_emif_arch_nf_191"                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/mem_array_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/io_12_lane_bcm__nf5es_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                                          
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/io_12_lane__nf5es_abphy.sv"]\"  -work altera_emif_arch_nf_191"                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_arch_nf_191/sim/ed_sim_emif_c10_0_altera_emif_arch_nf_191_pgy4vhq.sv"]\"  -work altera_emif_arch_nf_191"                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_avalon_mm_bridge_2001/sim/ed_sim_emif_c10_0_altera_avalon_mm_bridge_2001_k2bg7dq.v"]\"  -work altera_avalon_mm_bridge_2001"                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_avalon_onchip_memory2_1931/sim/ed_sim_emif_c10_0_altera_avalon_onchip_memory2_1931_ecie4wq.v"]\"  -work altera_avalon_onchip_memory2_1931"  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_merlin_master_translator_191/sim/ed_sim_emif_c10_0_altera_merlin_master_translator_191_g7h47bq.sv"]\"  -work altera_merlin_master_translator_191"
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_merlin_slave_translator_191/sim/ed_sim_emif_c10_0_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_mm_interconnect_1920/sim/ed_sim_emif_c10_0_altera_mm_interconnect_1920_trcm3ta.v"]\"  -work altera_mm_interconnect_1920"                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_reset_controller_1921/sim/altera_reset_controller.v"]\"  -work altera_reset_controller_1921"                                                
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_reset_controller_1921/sim/altera_reset_synchronizer.v"]\"  -work altera_reset_controller_1921"                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_cal_slave_nf_191/sim/ed_sim_emif_c10_0_altera_emif_cal_slave_nf_191_rmzieji.v"]\"  -work altera_emif_cal_slave_nf_191"                 
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/altera_emif_c10_1910/sim/ed_sim_emif_c10_0_altera_emif_c10_1910_vcl64oa.v"]\"  -work altera_emif_c10_1910"                                         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_emif_c10_0/sim/ed_sim_emif_c10_0.v"]\"  -work ed_sim_emif_c10_0"                                                                                              
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_std_synchronizer_nocut.v"]\"  -work altera_emif_tg_avl_191"                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_defs.sv"]\"  -work altera_emif_tg_avl_191"                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_top.sv"]\"  -work altera_emif_tg_avl_191"                                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_addr_gen.sv"]\"  -work altera_emif_tg_avl_191"                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_avl_mm_if.sv"]\"  -work altera_emif_tg_avl_191"                                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_avl_mm_srw_if.sv"]\"  -work altera_emif_tg_avl_191"                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_block_rw_stage.sv"]\"  -work altera_emif_tg_avl_191"                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_burst_boundary_addr_gen.sv"]\"  -work altera_emif_tg_avl_191"                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_byteenable_stage.sv"]\"  -work altera_emif_tg_avl_191"                                                            
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_driver_sim_mem_validate.sv"]\"  -work altera_emif_tg_avl_191"                                                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_driver_simple.sv"]\"  -work altera_emif_tg_avl_191"                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_driver.sv"]\"  -work altera_emif_tg_avl_191"                                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_driver_fsm.sv"]\"  -work altera_emif_tg_avl_191"                                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_lfsr.sv"]\"  -work altera_emif_tg_avl_191"                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_lfsr_wrapper.sv"]\"  -work altera_emif_tg_avl_191"                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_rand_addr_gen.sv"]\"  -work altera_emif_tg_avl_191"                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_rand_burstcount_gen.sv"]\"  -work altera_emif_tg_avl_191"                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_rand_num_gen.sv"]\"  -work altera_emif_tg_avl_191"                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_rand_seq_addr_gen.sv"]\"  -work altera_emif_tg_avl_191"                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_read_compare.sv"]\"  -work altera_emif_tg_avl_191"                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_scfifo_wrapper.sv"]\"  -work altera_emif_tg_avl_191"                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_seq_addr_gen.sv"]\"  -work altera_emif_tg_avl_191"                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_single_rw_stage.sv"]\"  -work altera_emif_tg_avl_191"                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_template_addr_gen.sv"]\"  -work altera_emif_tg_avl_191"                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_template_stage.sv"]\"  -work altera_emif_tg_avl_191"                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/altera_emif_tg_avl_191/sim/altera_emif_avl_tg_amm_1x_bridge.sv"]\"  -work altera_emif_tg_avl_191"                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_tg/sim/ed_sim_tg.v"]\"  -work ed_sim_tg"                                                                                                                      
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_mem/altera_emif_mem_model_core_ddr3_191/sim/altera_emif_ddrx_model.sv"]\"  -work altera_emif_mem_model_core_ddr3_191"                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_mem/altera_emif_mem_model_core_ddr3_191/sim/altera_emif_ddrx_model_per_ping_pong.sv"]\"  -work altera_emif_mem_model_core_ddr3_191"                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_mem/altera_emif_mem_model_core_ddr3_191/sim/altera_emif_ddrx_model_per_device.sv"]\"  -work altera_emif_mem_model_core_ddr3_191"                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_mem/altera_emif_mem_model_core_ddr3_191/sim/altera_emif_ddrx_model_rank.sv"]\"  -work altera_emif_mem_model_core_ddr3_191"                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_mem/altera_emif_mem_model_core_ddr3_191/sim/altera_emif_ddr3_model_rdimm_chip.sv"]\"  -work altera_emif_mem_model_core_ddr3_191"                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_mem/altera_emif_mem_model_core_ddr3_191/sim/altera_emif_ddr3_model_lrdimm_chip.sv"]\"  -work altera_emif_mem_model_core_ddr3_191"                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_mem/altera_emif_mem_model_core_ddr3_191/sim/altera_emif_ddrx_model_bidir_delay.sv"]\"  -work altera_emif_mem_model_core_ddr3_191"                                  
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_mem/altera_emif_mem_model_191/sim/ed_sim_mem_altera_emif_mem_model_191_2byhqwi.v"]\"  -work altera_emif_mem_model_191"                                        
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_mem/sim/ed_sim_mem.v"]\"  -work ed_sim_mem"                                                                                                                   
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_global_reset_n_splitter/sim/ed_sim_global_reset_n_splitter.v"]\"  -work ed_sim_global_reset_n_splitter"                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_pll_ref_clk_source/altera_avalon_clock_source_191/sim/altera_avalon_clock_source.sv"]\" -l altera_common_sv_packages -work altera_avalon_clock_source_191"         
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/emif_c10_0_example_design/sim/ip/ed_sim/ed_sim_pll_ref_clk_source/sim/ed_sim_pll_ref_clk_source.v"]\"  -work ed_sim_pll_ref_clk_source"                                                                      
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/async_input_bram_player/async_input_bram_player/ram_1port_2010/sim/async_input_bram_player_ram_1port_2010_bzyhfpa.v"]\"  -work ram_1port_2010"                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/async_input_bram_player/async_input_bram_player/sim/async_input_bram_player.v"]\"  -work async_input_bram_player"                                                                                                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_master_translator_191/sim/avalon_mm_ddr_altera_merlin_master_translator_191_g7h47bq.sv"]\"  -work altera_merlin_master_translator_191"                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_slave_translator_191/sim/avalon_mm_ddr_altera_merlin_slave_translator_191_x56fcki.sv"]\"  -work altera_merlin_slave_translator_191"                                                   
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_master_agent_191/sim/avalon_mm_ddr_altera_merlin_master_agent_191_mpbm6tq.sv"]\"  -work altera_merlin_master_agent_191"                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_slave_agent_191/sim/avalon_mm_ddr_altera_merlin_slave_agent_191_ncfkfri.sv"]\"  -work altera_merlin_slave_agent_191"                                                                  
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_slave_agent_191/sim/altera_merlin_burst_uncompressor.sv"]\"  -work altera_merlin_slave_agent_191"                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_avalon_sc_fifo_1930/sim/avalon_mm_ddr_altera_avalon_sc_fifo_1930_pqv24kq.v"]\"  -work altera_avalon_sc_fifo_1930"                                                                       
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_router_1920/sim/avalon_mm_ddr_altera_merlin_router_1920_u54nwdq.sv"]\"  -work altera_merlin_router_1920"                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_router_1920/sim/avalon_mm_ddr_altera_merlin_router_1920_ksgmbhi.sv"]\"  -work altera_merlin_router_1920"                                                                              
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_avalon_st_pipeline_stage_1920/sim/avalon_mm_ddr_altera_avalon_st_pipeline_stage_1920_zterisq.sv"]\"  -work altera_avalon_st_pipeline_stage_1920"                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_avalon_st_pipeline_stage_1920/sim/altera_avalon_st_pipeline_base.v"]\"  -work altera_avalon_st_pipeline_stage_1920"                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_burst_adapter_1921/sim/avalon_mm_ddr_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1921_szjdsxq.v"]\"  -work altera_merlin_burst_adapter_1921"                     
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_burst_adapter_1921/sim/avalon_mm_ddr_altera_merlin_burst_adapter_1921_mecymiq.sv"]\"  -work altera_merlin_burst_adapter_1921"                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_burst_adapter_1921/sim/altera_merlin_burst_adapter_uncmpr.sv"]\"  -work altera_merlin_burst_adapter_1921"                                                                             
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_burst_adapter_1921/sim/altera_merlin_burst_adapter_13_1.sv"]\"  -work altera_merlin_burst_adapter_1921"                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_burst_adapter_1921/sim/altera_merlin_burst_adapter_new.sv"]\"  -work altera_merlin_burst_adapter_1921"                                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_burst_adapter_1921/sim/altera_incr_burst_converter.sv"]\"  -work altera_merlin_burst_adapter_1921"                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_burst_adapter_1921/sim/altera_wrap_burst_converter.sv"]\"  -work altera_merlin_burst_adapter_1921"                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_burst_adapter_1921/sim/altera_default_burst_converter.sv"]\"  -work altera_merlin_burst_adapter_1921"                                                                                 
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_burst_adapter_1921/sim/altera_merlin_address_alignment.sv"]\"  -work altera_merlin_burst_adapter_1921"                                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_demultiplexer_1921/sim/avalon_mm_ddr_altera_merlin_demultiplexer_1921_xwx4vky.sv"]\"  -work altera_merlin_demultiplexer_1921"                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_multiplexer_1921/sim/avalon_mm_ddr_altera_merlin_multiplexer_1921_oangkgy.sv"]\"  -work altera_merlin_multiplexer_1921"                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_multiplexer_1921/sim/altera_merlin_arbitrator.sv"]\"  -work altera_merlin_multiplexer_1921"                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_demultiplexer_1921/sim/avalon_mm_ddr_altera_merlin_demultiplexer_1921_wuh3joy.sv"]\"  -work altera_merlin_demultiplexer_1921"                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_multiplexer_1921/sim/avalon_mm_ddr_altera_merlin_multiplexer_1921_o6dhfhi.sv"]\"  -work altera_merlin_multiplexer_1921"                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_multiplexer_1921/sim/altera_merlin_arbitrator.sv"]\"  -work altera_merlin_multiplexer_1921"                                                                                           
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_width_adapter_1920/sim/avalon_mm_ddr_altera_merlin_width_adapter_1920_w7djztq.sv"]\"  -work altera_merlin_width_adapter_1920"                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_width_adapter_1920/sim/altera_merlin_address_alignment.sv"]\"  -work altera_merlin_width_adapter_1920"                                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_width_adapter_1920/sim/altera_merlin_burst_uncompressor.sv"]\"  -work altera_merlin_width_adapter_1920"                                                                               
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_width_adapter_1920/sim/avalon_mm_ddr_altera_merlin_width_adapter_1920_yk6lb6q.sv"]\"  -work altera_merlin_width_adapter_1920"                                                         
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_width_adapter_1920/sim/altera_merlin_address_alignment.sv"]\"  -work altera_merlin_width_adapter_1920"                                                                                
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_merlin_width_adapter_1920/sim/altera_merlin_burst_uncompressor.sv"]\"  -work altera_merlin_width_adapter_1920"                                                                               
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/hs_clk_xer_1931/sim/avalon_mm_ddr_hs_clk_xer_1931_y4ocngi.v"]\"  -work hs_clk_xer_1931"                                                                                                        
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/hs_clk_xer_1931/sim/altera_avalon_st_clock_crosser.v"]\"  -work hs_clk_xer_1931"                                                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/hs_clk_xer_1931/sim/altera_avalon_st_pipeline_base.v"]\"  -work hs_clk_xer_1931"                                                                                                                    
  lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/hs_clk_xer_1931/sim/altera_std_synchronizer_nocut.v"]\"  -work hs_clk_xer_1931"                                                                                                                     
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_mm_interconnect_1920/sim/avalon_mm_ddr_altera_mm_interconnect_1920_p6j6cbi.v"]\"  -work altera_mm_interconnect_1920"                                                                    
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_reset_controller_1921/sim/altera_reset_controller.v"]\"  -work altera_reset_controller_1921"                                                                                            
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/altera_reset_controller_1921/sim/altera_reset_synchronizer.v"]\"  -work altera_reset_controller_1921"                                                                                          
  lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../src/altera/avalon_mm_ddr_16bit_ddr/avalon_mm_ddr/sim/avalon_mm_ddr.v"]\"  -work avalon_mm_ddr"                                                                                                                                                  
  return $design_files
}

proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
  set ELAB_OPTIONS ""
  if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
  } else {
  }
  return $ELAB_OPTIONS
}


proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
  set SIM_OPTIONS ""
  if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
  } else {
  }
  return $SIM_OPTIONS
}


proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
  set ENV_VARIABLES [dict create]
  set LD_LIBRARY_PATH [dict create]
  dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
  if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
  } else {
  }
  return $ENV_VARIABLES
}


proc normalize_path {FILEPATH} {
    if {[catch { package require fileutil } err]} { 
        return $FILEPATH 
    } 
    set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]  
    if {[file pathtype $FILEPATH] eq "relative"} { 
        set path [fileutil::relative [pwd] $path] 
    } 
    return $path 
} 
