<?xml version="1.0" encoding="UTF-8"?>
<preferences>
 <debug showDebugMenu="0" />
 <window width="1944" height="1034" x="-12" y="-12" />
 <generation
   path=""
   greybox="0"
   simulation="VERILOG"
   vcs="0"
   modelsim="1"
   ipxact="1"
   synthesis="VERILOG" />
</preferences>
