// async_input_bram_player.v

// Generated using ACDS version 21.3 170

`timescale 1 ps / 1 ps
module async_input_bram_player (
		input  wire [127:0] data,    //    data.datain
		output wire [127:0] q,       //       q.dataout
		input  wire [8:0]   address, // address.address
		input  wire         wren,    //    wren.wren
		input  wire         clock    //   clock.clk
	);

	async_input_bram_player_ram_1port_2010_bzyhfpa ram_1port_0 (
		.data    (data),    //   input,  width = 128,    data.datain
		.q       (q),       //  output,  width = 128,       q.dataout
		.address (address), //   input,    width = 9, address.address
		.wren    (wren),    //   input,    width = 1,    wren.wren
		.clock   (clock)    //   input,    width = 1,   clock.clk
	);

endmodule
