// (c) 1992-2020 Intel Corporation.                            
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// software and tools, and its AMPP partner logic functions, and any output       
// files any of the foregoing (including device programming or simulation         
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// Agreement, Intel MegaCore Function License Agreement, or other applicable      
// license agreement, including, without limitation, that your use is for the     
// sole purpose of programming logic devices manufactured by Intel and sold by    
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// agreement for further details.                                                 

module top(
  //////// CLOCK //////////
  input        pll_ref_clk,  		// reference clock for the DDR Memory PLL

  //////// PCIe //////////
  input        clk_pcie_clk, 		// 100MHz clock
  
  ////////Greset/////////
  input        reset_global_mem,
  
  input        reset_overall,

  //////// DDR4 //////////
  input         oct_rzqin,
  output [1:0]  mem_ba,
  output [0:0]  mem_bg,
  output [0:0]  mem_cke,
  output [0:0]  mem_ck,
  output [0:0]  mem_ck_n,
  output [0:0]  mem_cs_n,
  output [0:0]  mem_reset_n,
  output [0:0]  mem_odt,
  output [0:0]  mem_act_n,
  output [0:0]  mem_par,
  input  [0:0]  mem_alert_n,
  output [16:0] mem_a,
  inout  [63:0] mem_dq,
  inout  [7:0]  mem_dqs,
  inout  [7:0]  mem_dqs_n,
  inout  [7:0]  mem_dbi_n,
  
    //////// DDR4_2 //////////
  input         oct_rzqin_2,
  output [1:0]  mem_ba_2,
  output [0:0]  mem_bg_2,
  output [0:0]  mem_cke_2,
  output [0:0]  mem_ck_2,
  output [0:0]  mem_ck_n_2,
  output [0:0]  mem_cs_n_2,
  output [0:0]  mem_reset_n_2,
  output [0:0]  mem_odt_2,
  output [0:0]  mem_act_n_2,
  output [0:0]  mem_par_2,
  input  [0:0]  mem_alert_n_2,
  output [16:0] mem_a_2,
  inout  [63:0] mem_dq_2,
  inout  [7:0]  mem_dqs_2,
  inout  [7:0]  mem_dqs_n_2,
  inout  [7:0]  mem_dbi_n_2,
  
  //memory bank divider input///
  input [511:0] memory_bank_test_s_writedata_i,
  input memory_bank_test_s_read_i,
  input memory_bank_test_s_write_i,
  input [4:0] memory_bank_test_s_burstcount_i,
  input [63:0] memory_bank_test_s_byteenable_i,
  output memory_bank_test_s_waitrequest_o,
  output [511:0] memory_bank_test_s_readdata_o,
  output memory_bank_test_s_readdatavalid_o,
  input [25:0] memory_bank_test_s_address_i      
);

//=======================================================
//  REG/WIRE declarations
//=======================================================
wire 		local_cal_fail;
wire 		local_cal_success;

wire 		local_cal_fail_2;
wire 		local_cal_success_2;
//=======================================================
// board instantiation
//=======================================================
board board_inst
(
  .clk_pcie_clk(clk_pcie_clk),
  
  .global_reset_mem_reset(reset_global_mem),
  
  .reset_overall_reset(reset_overall),
  
  .clk_membankdiv_kern_clk(clk_kernel),      
  
  .reset_membankdiv_kern_reset_n(reset_kernel),
  
  // DDR4 pins
  .ddr4_pll_ref_clk_clk( pll_ref_clk ),
  .ddr4a_oct_oct_rzqin( oct_rzqin ),
  .ddr4a_mem_ba( mem_ba ),
  .ddr4a_mem_bg( mem_bg ),
  .ddr4a_mem_cke( mem_cke ),
  .ddr4a_mem_ck( mem_ck ),
  .ddr4a_mem_ck_n( mem_ck_n ),
  .ddr4a_mem_cs_n( mem_cs_n ),
  .ddr4a_mem_reset_n( mem_reset_n ),
  .ddr4a_mem_odt( mem_odt ),
  .ddr4a_mem_act_n( mem_act_n ),
  .ddr4a_mem_par( mem_par ),
  .ddr4a_mem_alert_n( mem_alert_n ),
  .ddr4a_mem_a( mem_a ),
  .ddr4a_mem_dq( mem_dq ),
  .ddr4a_mem_dqs( mem_dqs ),
  .ddr4a_mem_dqs_n( mem_dqs_n ),
  .ddr4a_mem_dbi_n( mem_dbi_n ),
  
    // DDR4_2 pins
  .ddr4a_oct_2_oct_rzqin( oct_rzqin_2),
  .ddr4a_2_mem_ba( mem_ba_2 ),
  .ddr4a_2_mem_bg( mem_bg_2 ),
  .ddr4a_2_mem_cke( mem_cke_2 ),
  .ddr4a_2_mem_ck( mem_ck_2 ),
  .ddr4a_2_mem_ck_n( mem_ck_n_2 ),
  .ddr4a_2_mem_cs_n( mem_cs_n_2 ),
  .ddr4a_2_mem_reset_n( mem_reset_n_2 ),
  .ddr4a_2_mem_odt( mem_odt_2 ),
  .ddr4a_2_mem_act_n( mem_act_n_2 ),
  .ddr4a_2_mem_par( mem_par_2 ),
  .ddr4a_2_mem_alert_n( mem_alert_n_2 ),
  .ddr4a_2_mem_a( mem_a_2 ),
  .ddr4a_2_mem_dq( mem_dq_2 ),
  .ddr4a_2_mem_dqs( mem_dqs_2 ),
  .ddr4a_2_mem_dqs_n( mem_dqs_n_2 ),
  .ddr4a_2_mem_dbi_n( mem_dbi_n_2 ),
  
  //mem bank divider///
  .memory_bank_test_s_writedata(memory_bank_test_s_writedata_i),           
  .memory_bank_test_s_read(memory_bank_test_s_read_i),
  .memory_bank_test_s_write(memory_bank_test_s_write_i),
  .memory_bank_test_s_burstcount(memory_bank_test_s_burstcount_i),
  .memory_bank_test_s_byteenable(memory_bank_test_s_byteenable_i),
  .memory_bank_test_s_waitrequest(memory_bank_test_s_waitrequest_o),
  .memory_bank_test_s_readdata(memory_bank_test_s_readdata_o),
  .memory_bank_test_s_readdatavalid(memory_bank_test_s_readdatavalid_o),
  .memory_bank_test_s_address(memory_bank_test_s_address_i)
);

endmodule