library ieee;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_1164.all;

entity NVM_top is 

port(
clock_20mhz_i  : in std_logic;
reset_ni 		: in std_logic;
en_read_i 		: in STD_LOGIC;
en_write_i 		: in STD_LOGIC;
data_write_i	: in STD_LOGIC_VECTOR(31 DOWNTO 0);
avmm_data_readdata_o : out std_logic_vector(31 downto 0)
);
end entity;


architecture arch of NVM_top is

component eLADEP_NVM 
	port (
		clock                   : in  std_logic                     := '0';             --    clk.clk
		avmm_csr_addr           : in  std_logic                     := '0';             --    csr.address
		avmm_csr_read           : in  std_logic                     := '0';             --       .read
		avmm_csr_writedata      : in  std_logic_vector(31 downto 0) := (others => '0'); --       .writedata
		avmm_csr_write          : in  std_logic                     := '0';             --       .write
		avmm_csr_readdata       : out std_logic_vector(31 downto 0);                    --       .readdata
		avmm_data_addr          : in  std_logic_vector(12 downto 0) := (others => '0'); --   data.address
		avmm_data_read          : in  std_logic                     := '0';             --       .read
		avmm_data_writedata     : in  std_logic_vector(31 downto 0) := (others => '0'); --       .writedata
		avmm_data_write         : in  std_logic                     := '0';             --       .write
		avmm_data_readdata      : out std_logic_vector(31 downto 0);                    --       .readdata
		avmm_data_waitrequest   : out std_logic;                                        --       .waitrequest
		avmm_data_readdatavalid : out std_logic;                                        --       .readdatavalid
		avmm_data_burstcount    : in  std_logic_vector(3 downto 0)  := (others => '0'); --       .burstcount
		reset_n                 : in  std_logic                     := '0'              -- nreset.reset_n
	);
end component;

component NVM_Read_write is
port(
		clock_20mhz_i 	:  in std_logic;
		reset_ni 		:  in std_logic;
		csr_readdata_i	: 	in STD_LOGIC_VECTOR(31 DOWNTO 0);
		waitrequest_i	: 	in STD_LOGIC;
		readvalid_i		: 	in STD_LOGIC;
		en_read_i		: 	in STD_LOGIC;
		en_write_i		: 	in STD_LOGIC;
		data_write_i	: 	in STD_LOGIC_VECTOR(31 DOWNTO 0);

		csr_addr_o				: OUT STD_LOGIC;
		csr_writedata_o		: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
		csr_write_o				: OUT STD_LOGIC;
		csr_read_o				: OUT STD_LOGIC;
		data_addr_o				: OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
		data_writedata_o		: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
		data_write_o			: OUT STD_LOGIC;
		data_read_o				: OUT STD_LOGIC;
		readvalid_counter_o	: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		burstcount_o			: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
end component;

signal avmm_csr_readdata_s       : std_logic_vector(31 downto 0);   --       .readdata
signal avmm_data_readdata_s      : std_logic_vector(31 downto 0);      --       .readdata
signal avmm_data_waitrequest_s   : std_logic;                         --       .waitrequest
signal avmm_data_readdatavalid_s : std_logic;                            --       .readdatavalid

SIGNAL csr_readdata_s 		: std_logic_vector (31 downto 0);
SIGNAL waitrequest_s 		: STD_LOGIC;
SIGNAL readvalid_s 			: STD_LOGIC;
--SIGNAL en_read_s 			: STD_LOGIC;
--SIGNAL en_write_s 			: STD_LOGIC;
SIGNAL csr_addr_s 			: STD_LOGIC;
SIGNAL csr_writedata_s 		: std_logic_vector (31 downto 0);
SIGNAL csr_write_s 			: STD_LOGIC;
SIGNAL csr_read_s 			: STD_LOGIC;
SIGNAL data_addr_s 			: std_logic_vector (12 downto 0);
SIGNAL data_writedata_s 	: std_logic_vector (31 downto 0);
SIGNAL data_write_s 			: STD_LOGIC;
SIGNAL data_read_s 			: STD_LOGIC;
SIGNAL readvalid_counter_s : std_logic_vector (3 downto 0);
SIGNAL burstcount_s 		   : std_logic_vector (3 downto 0);

begin

inst1: eLADEP_NVM 
PORT MAP(
		clock                   => clock_20mhz_i,            --    clk.clk
		avmm_csr_addr           => csr_addr_s,             --    csr.address
		avmm_csr_read           => csr_read_s,             --       .read
		avmm_csr_writedata      => csr_writedata_s, --       .writedata
		avmm_csr_write          => csr_write_s,             --       .write
		avmm_csr_readdata       => avmm_csr_readdata_s, --       .readdata
		avmm_data_addr          => data_addr_s, --   data.address
		avmm_data_read          => data_read_s,             --       .read
		avmm_data_writedata     => data_writedata_s, --       .writedata
		avmm_data_write         => data_write_s,             --       .write
		avmm_data_readdata      => avmm_data_readdata_s,--       .readdata
		avmm_data_waitrequest   => avmm_data_waitrequest_s, --       .waitrequest
		avmm_data_readdatavalid => avmm_data_readdatavalid_s, --       .readdatavalid
		avmm_data_burstcount    => burstcount_s,--       .burstcount
		reset_n                 => reset_ni              -- nreset.reset_n
	
);



inst2: NVM_Read_write 
PORT MAP(
		clock_20mhz_i 			=> clock_20mhz_i,    
		reset_ni 				=> reset_ni  ,
		csr_readdata_i			=> avmm_csr_readdata_s	,
		waitrequest_i			=> avmm_data_waitrequest_s	,
		readvalid_i				=> avmm_data_readdatavalid_s	,
		en_read_i				=> en_read_i	,
		en_write_i				=> en_write_i	,
		data_write_i			=> data_write_i  ,
		csr_addr_o				=> csr_addr_s,
		csr_writedata_o		=> csr_writedata_s,
		csr_write_o				=> csr_write_s,
		csr_read_o				=> csr_read_s,
		data_addr_o				=> data_addr_s,
		data_writedata_o		=> data_writedata_s,
		data_write_o			=> data_write_s,
		data_read_o				=> data_read_s,
		readvalid_counter_o	=> readvalid_counter_s,
		burstcount_o			=> burstcount_s
);

avmm_data_readdata_o <= avmm_data_readdata_s;

END ARCHITECTURE arch;