Info: *******************************************************************
Info: Running Quartus Prime Compiler Database Interface
    Info: Version 17.1.2 Build 304 01/31/2018 SJ Pro Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Mar 21 05:47:49 2018
Info: Command: quartus_cdb top -c base --import_design --file base.qdb --overwrite
Info: Quartus(args): --project top -c base --file base.qdb --overwrite
Info: Using INI file /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/quartus.ini
Info: Running design::import_design -file base.qdb -overwrite 
Critical Warning (18639): Skipping database version check for import of database files from  'Version 17.1.0 Internal Build 183 09/12/2017 TO Pro Edition'. The imported database might be incompatible with current version of the software.
Critical Warning (18639): Skipping database version check for import of database files from  'Version 17.1.0 Internal Build 183 09/12/2017 TO Pro Edition'. The imported database might be incompatible with current version of the software.
Critical Warning (18639): Skipping database version check for import of database files from  'Version 17.1.0 Internal Build 183 09/12/2017 TO Pro Edition'. The imported database might be incompatible with current version of the software.
Critical Warning (18639): Skipping database version check for import of database files from  'Version 17.1.0 Internal Build 183 09/12/2017 TO Pro Edition'. The imported database might be incompatible with current version of the software.
Info (16677): Loading final database
Info (16734): Loading "final" snapshot for partition "root_partition".
Info (16734): Loading "final" snapshot for partition "auto_fab_0".
Info (16734): Loading "final" snapshot for partition "kernel".
Info (16678): Successfully loaded final database: elapsed time is 00:16:41
Info (18230): Checking the imported netlist for invalid settings in the current version of the software.
Info (23030): Evaluation of Tcl script /home/shared/hdd/Quartus/17.1.0.240/quartus/common/tcl/internal/qatm_import_design.tcl was successful
Info: Quartus Prime Compiler Database Interface was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 3084 megabytes
    Info: Processing ended: Wed Mar 21 06:12:52 2018
    Info: Elapsed time: 00:25:03
    Info: Total CPU time (on all processors): 00:25:03
Info: *******************************************************************
Info: Running Quartus Prime Fitter
    Info: Version 17.1.2 Build 304 01/31/2018 SJ Pro Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Mar 21 06:12:53 2018
Info: Command: quartus_fit top -c base
Info: Using INI file /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/quartus.ini
Info: qfit2_default_script.tcl version: #1
Info: Project  = top
Info: Revision = base
Info (16677): Loading synthesized database
Info (16734): Loading "final" snapshot for partition "root_partition".
Info (16734): Loading "final" snapshot for partition "auto_fab_0".
Info (16734): Loading "final" snapshot for partition "kernel".
Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:11
Info (19078): Instance assignments in read-only partitions are ignored:
    Info (19079): Ignored assignment "LOCATION PIN_AU33 -to config_clk" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_BD24 -to kernel_pll_refclk" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AL37 -to pcie_refclk" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AL38 -to pcie_refclk(n)" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_BC30 -to perstl0_n" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AT40 -to hip_serial_rx_in[0]" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AP40 -to hip_serial_rx_in[1]" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AN42 -to hip_serial_rx_in[2]" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AM40 -to hip_serial_rx_in[3]" because target belongs to a read-only partition "|"
    Info (19079): Ignored assignment "LOCATION PIN_AL42 -to hip_serial_rx_in[4]" because target belongs to a read-only partition "|"
    Info (19080): Additional 190 ignored instance assignments are not displayed.
Warning (19182): The Entity SDC source file cannot be located: "board/altera_avalon_dc_fifo_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_stin_fifo/altera_avalon_dc_fifo_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_stout_fifo/altera_avalon_dc_fifo_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_clock_cross_kernel_to_ddr4a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_clock_cross_pcie_to_ddr4a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_clk_gen/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_interface/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "board/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ddr4/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_clk_gen/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_kernel_interface/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_memory_bank_divider_ddr4a/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_reset_controller_global/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/board/board_reset_controller_pcie/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/ddr4/ddr4_ddr4a/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr4a/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/mem/mem_reset_controller_ddr4a_pipe/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "mem/altera_reset_controller_171/synth/altera_reset_controller.sdc". Evaluation of this SDC file will be skipped.
Warning (19182): The Entity SDC source file cannot be located: "ip/ddr4/ddr4_ddr4a/altera_emif_arch_nf_171/synth/ddr4_ddr4a_altera_emif_arch_nf_171_ceotdni.sdc". Evaluation of this SDC file will be skipped.
Info (20030): Parallel compilation is enabled and will use 16 of the 44 processors detected
Info (119006): Selected device 10AX115S2F45I1SG for design "base"
Info (21077): Core supply voltage is 0.95V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 100 degrees C
Warning (18550): Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example.
    Info (119043): Atom "board_inst|mem|ddr4|ddr4a|ddr4a|cal_slave_component|ioaux_soft_ram|the_altsyncram|auto_generated|ram_block1a0" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled
Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info (12262): Starting Fitter periphery placement operations
Info (12290): Loading the periphery placement data.
Info (12291): Periphery placement data loaded: elapsed time is 00:00:28
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning (12789): Real-time CRC ERROR_CHECK_FREQUENCY_DIVISOR value (1) in design does not match value (256) in the Quartus Prime Settings File
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info (16210): Plan updated with currently enabled project assignments.
Info (12295): Periphery placement of all unplaced cells complete: elapsed time is 00:00:00
Warning (18708): ATX/FPLL < board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst > is not placed in the same bank as the reference clock.
Info (11178): Promoted 7 clocks (7 global)
    Info (13173): board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|outclk[0]~CLKENA0 (56257 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3A_G_I23
    Info (13173): board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|outclk[1]~CLKENA0 (7 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3A_G_I21
    Info (13173): freeze_wrapper_inst|kernel_system_clock_reset_reset_reset_n~CLKENA0 (13376 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2G_G_I12
    Info (13173): board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|clk_gen_hmc.hr_qr.clk_gen_master.emif_usr_clk_buf (6860 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2K_G_I6
    Info (13173): board_inst|kernel_interface|kernel_interface|reset_controller_sw|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 (2319 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1C_G_I5
    Info (13173): board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_c_counters[3]~CLKENA0 (185 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2K_G_I2
    Info (13173): board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys~CORE_CLK_OUTCLKENA0 (44427 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1D_G_I13
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176219): No registers were packed into other blocks
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity alt_xcvr_resync
        Info (332166): set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs}
    Info (332165): Entity altera_std_synchronizer
        Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
    Info (332165): Entity altpcie_reset_delay_sync
        Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]]
        Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]]
    Info (332165): Entity altpcie_sc_bitsync
        Info (332166): set_multicycle_path -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3
        Info (332166): set_false_path -hold -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]]
        Info (332166): set_multicycle_path -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3
        Info (332166): set_false_path -hold -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]]
    Info (332165): Entity dcfifo_2ei1
        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_3v8:dffpipe16|dffe17a* 
        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_2v8:dffpipe13|dffe14a* 
Warning (332174): Ignored filter at qfit2_default_fitter_flow.tcl(340): *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*] could not be matched with a keeper File: /home/shared/hdd/Quartus/17.1.0.240/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
Warning (332049): Ignored set_multicycle_path at qfit2_default_fitter_flow.tcl(340): Argument <to> is an empty collection File: /home/shared/hdd/Quartus/17.1.0.240/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
    Info (332050): eval "fit_plan $create_fitter_netlist_args" File: /home/shared/hdd/Quartus/17.1.0.240/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
Warning (332049): Ignored set_false_path at qfit2_default_fitter_flow.tcl(340): Argument <to> is an empty collection File: /home/shared/hdd/Quartus/17.1.0.240/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
    Info (332050): eval "fit_plan $create_fitter_netlist_args" File: /home/shared/hdd/Quartus/17.1.0.240/quartus/common/tcl/internal/qfit2_default_fitter_flow.tcl Line: 340
Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:02.
Info (332104): Reading SDC File: 'top.sdc'
Info (332104): Reading SDC File: 'kernel_system/altera_reset_controller_171/synth/altera_reset_controller.sdc'
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'board/altera_avalon_dc_fifo_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'board/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'mem/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_stout_fifo/altera_avalon_dc_fifo_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_reset_controller_global/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_stin_fifo/altera_avalon_dc_fifo_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_kernel_interface/mem_org_mode_100/synth/mem_org_mode.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_kernel_interface/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_kernel_interface/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_reset_controller_ddr4a_pipe/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_reset_controller_ddr4a/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/ddr4/ddr4_ddr4a/altera_emif_arch_nf_171/synth/ddr4_ddr4a_altera_emif_arch_nf_171_ceotdni.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/ddr4/ddr4_ddr4a/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_kernel_clk_gen/altera_avalon_st_handshake_clock_crosser_171/synth/altera_avalon_st_handshake_clock_crosser.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_kernel_clk_gen/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_pcie/altera_xcvr_native_a10_171/synth/altera_xcvr_native_a10_false_paths.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_pcie/altera_pcie_a10_hip_171/synth/altera_pci_express.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_alt_pr/alt_pr_171/synth/rtl/alt_pr.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/mem/mem_uniphy_status_20nm/uniphy_status_20nm_141/synth/uniphy_status_20nm.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'ip/board/board_temperature/acl_temperature_a10_151/synth/temp_sense_a10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_reset_controller_pcie/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/board/board_memory_bank_divider_ddr4a/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_clock_cross_pcie_to_ddr4a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ip/mem/mem_clock_cross_kernel_to_ddr4a/altera_avalon_mm_clock_crossing_bridge_171/synth/altera_avalon_dc_fifo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': 'ddr4/altera_reset_controller_171/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332104): Reading SDC File: 'top_post.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys|pll_fixed_clk_central} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|wys~CORE_CLK_OUT} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys|core_clk_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys~CORE_CLK_OUTCLKENA0|outclk} -duty_cycle 50.00 -name {board_inst|pcie|pld_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|wys|pld_clk}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -duty_cycle 50.00 -name {board_inst|pcie|hip_cmn_clk[0]} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pld_pcs_interface.inst_twentynm_hssi_common_pld_pcs_interface|hip_cmn_clk[0]}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|rx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|rx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[10]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[10]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|pma_hclk} -divide_by 2 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|pma_hclk_by2} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface|sta_pma_hclk_by2}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[10]} -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|rx_fref} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll|fref}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[0]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_refclk_select_inst|ref_iqclk[11]} -multiply_by 25 -duty_cycle 50.00 -name {board_inst|pcie|tx_serial_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_inst|clk0}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_refclk_select_inst|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|pll_pcie_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_inst|hclk_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_lc_refclk_select_mux_inst|ref_iqclk[11]} -invert -multiply_by 40 -duty_cycle 50.00 -name {board_inst|pcie|twentynm_atx_pll_inst~O_CLK0_8G} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst|clk0_8g}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[0]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[1]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[2]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pld_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|tx_clkout} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1_out}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[3]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[11]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[4]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[10]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[5]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[10]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[6]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux|ref_iqclk[10]} -multiply_by 5 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|rx_pma_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_deser.inst_twentynm_hssi_pma_rx_deser|clkdiv}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_4_reg} -divide_by 4 -duty_cycle 50.00 -name {board_inst|pcie|g_xcvr_native_insts[7]|tx_clk} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by4_1}
    Info (332110): create_generated_clock -source {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|clk_fpll_b} -divide_by 16 -duty_cycle 50.00 -name {board_inst|pcie|tx_bonding_clocks[0]} {board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|cpulse_out_bus[0]}
    Info (332110): create_generated_clock -source {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0]} -divide_by 10 -multiply_by 32 -duty_cycle 50.00 -name {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|outclk0} {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|iopll_inst|outclk[0]}
    Info (332110): create_generated_clock -source {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0]} -divide_by 5 -multiply_by 32 -duty_cycle 50.00 -name {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|outclk1} {board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_iopll_i|twentynm_pll|iopll_inst|outclk[1]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst|pll_cascade_in} -divide_by 2 -multiply_by 8 -phase 22.50 -duty_cycle 50.00 -name {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|phy_clk[0]} {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst|loaden[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst|pll_cascade_in} -divide_by 4 -multiply_by 8 -phase 11.25 -duty_cycle 50.00 -name {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|phy_clk[1]} {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst|lvds_clk[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst|pll_cascade_in} -divide_by 8 -multiply_by 8 -duty_cycle 50.00 -name {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_c_counters[3]} {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst|outclk[3]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate|pll_cascade_in} -divide_by 2 -multiply_by 8 -phase 22.50 -duty_cycle 50.00 -name {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_DuplicateLOADEN0} {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate|loaden[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate|pll_cascade_in} -divide_by 4 -multiply_by 8 -phase 11.25 -duty_cycle 50.00 -name {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_DuplicateLVDS_CLK0} {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate|lvds_clk[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|pll_cascade_in} -divide_by 2 -multiply_by 8 -phase 22.50 -duty_cycle 50.00 -name {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LOADEN0} {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|loaden[0]}
    Info (332110): create_generated_clock -source {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|pll_cascade_in} -divide_by 4 -multiply_by 8 -phase 11.25 -duty_cycle 50.00 -name {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LVDS_CLK0} {board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|lvds_clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at top_post.sdc(49): acl_hmcc_wrapper_inst|* could not be matched with a clock File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 49
Warning (332174): Ignored filter at top_post.sdc(53): mem_dqs[0]_IN could not be matched with a clock File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 53
Warning (332174): Ignored filter at top_post.sdc(53): mem_dqs[1]_IN could not be matched with a clock File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 53
Warning (332174): Ignored filter at top_post.sdc(53): mem_dqs[2]_IN could not be matched with a clock File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 53
Warning (332174): Ignored filter at top_post.sdc(53): mem_dqs[3]_IN could not be matched with a clock File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 53
Warning (332174): Ignored filter at top_post.sdc(53): mem_dqs[4]_IN could not be matched with a clock File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 53
Warning (332174): Ignored filter at top_post.sdc(53): mem_dqs[5]_IN could not be matched with a clock File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 53
Warning (332174): Ignored filter at top_post.sdc(53): mem_dqs[6]_IN could not be matched with a clock File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 53
Warning (332174): Ignored filter at top_post.sdc(53): mem_dqs[7]_IN could not be matched with a clock File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 53
Warning (332174): Ignored filter at top_post.sdc(33): a10_internal_oscillator_clock0 could not be matched with a clock File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 33
Warning (332174): Ignored filter at top_post.sdc(33): altera_ts_clk could not be matched with a clock File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 33
Warning (332054): Assignment set_clock_groups is accepted but has some problems at top_post.sdc(33): Argument -group with value   a10_internal_oscillator_clock0   could not match any element of the following types: ( clk ) File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 33
    Info (332050): set_clock_groups -asynchronous \
-group { \
   config_clk \
} -group { \
   a10_internal_oscillator_clock0 \
} -group { \
   altera_ts_clk \
} -group { \
   pll_ref_clk \
} -group { \
   kernel_pll_refclk \
} -group [get_clocks {
   pcie_refclk \
   board_inst|pcie|* \
}] -group [get_clocks { \
   board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|* \
}] -group [get_clocks { \
   acl_hmcc_wrapper_inst|* \
}] -group { \
   altera_reserved_tck \
} -group [get_clocks { \
    mem_dqs[0]_IN \
    mem_dqs[1]_IN \
    mem_dqs[2]_IN \
    mem_dqs[3]_IN \
    mem_dqs[4]_IN \
    mem_dqs[5]_IN \
    mem_dqs[6]_IN \
    mem_dqs[7]_IN \
    board_inst|mem|* \
}] File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 33
Warning (332054): Assignment set_clock_groups is accepted but has some problems at top_post.sdc(33): Argument -group with value   altera_ts_clk   could not match any element of the following types: ( clk ) File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 33
Warning (332054): Assignment set_clock_groups is accepted but has some problems at top_post.sdc(33): Argument -group with value [get_clocks {  acl_hmcc_wrapper_inst|*  }] contains zero elements File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 33
Warning (332174): Ignored filter at top_post.sdc(76): board_inst|mem|ddr4_calibrate|sw_reset_n_out could not be matched with a clock or keeper or register or port or pin or cell or partition File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 76
Warning (332049): Ignored set_false_path at top_post.sdc(76): Argument <from> is not an object ID File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 76
    Info (332050): set_false_path -from board_inst|mem|ddr4_calibrate|sw_reset_n_out -to * File: /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/top_post.sdc Line: 76
Critical Warning: Compiling with slowed OpenCL Kernel clock.  This is to help achieve timing closure for board bringup.
Info (332104): Reading SDC File: '/build/arc/cache/tools/acds/17.1/183/linux64/ip/altera/sld/jtag/altera_jtag_wys_atom/default_jtag.sdc'
Info (19449): Reading SDC files elapsed 00:00:01.
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~rx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg
Warning (332060): Node: mem_dqs[3] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[3].lane_inst~low_dff_a is being clocked by mem_dqs[3]
Warning (332060): Node: mem_dqs[4] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~low_dff_a is being clocked by mem_dqs[4]
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg is being clocked by board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~byte_serializer_pcs_clk_div_by_2_reg.reg
Warning (332060): Node: mem_dqs[2] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~low_dff_a is being clocked by mem_dqs[2]
Warning (332060): Node: mem_dqs[5] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst~low_dff_a is being clocked by mem_dqs[5]
Warning (332060): Node: mem_dqs[0] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~low_dff_a is being clocked by mem_dqs[0]
Warning (332060): Node: mem_dqs[1] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~low_dff_a is being clocked by mem_dqs[1]
Warning (332060): Node: mem_dqs[6] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[1].lane_inst~low_dff_a is being clocked by mem_dqs[6]
Warning (332060): Node: mem_dqs[7] was determined to be a clock but was found without an associated clock assignment.
    Info (13166): Register board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst~low_dff_a is being clocked by mem_dqs[7]
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
    Warning (332056): Clock: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|phy_clk[0] with master clock period: 6.666 found on PLL node: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst|loaden[0] does not match the master clock period requirement: 6.671
    Warning (332056): Clock: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|phy_clk[1] with master clock period: 6.666 found on PLL node: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst|lvds_clk[0] does not match the master clock period requirement: 6.671
    Warning (332056): Clock: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_c_counters[3] with master clock period: 6.666 found on PLL node: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst|outclk[3] does not match the master clock period requirement: 6.671
    Warning (332056): Clock: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_DuplicateLOADEN0 with master clock period: 6.666 found on PLL node: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate|loaden[0] does not match the master clock period requirement: 6.671
    Warning (332056): Clock: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_DuplicateLVDS_CLK0 with master clock period: 6.666 found on PLL node: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate|lvds_clk[0] does not match the master clock period requirement: 6.671
    Warning (332056): Clock: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LOADEN0 with master clock period: 6.666 found on PLL node: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|loaden[0] does not match the master clock period requirement: 6.671
    Warning (332056): Clock: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LVDS_CLK0 with master clock period: 6.666 found on PLL node: board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1|lvds_clk[0] does not match the master clock period requirement: 6.671
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 70 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):   50.000 altera_reserved_tck
    Info (332111):    2.500 board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|outclk0
    Info (332111):    1.250 board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|outclk1
    Info (332111):    1.666 board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|phy_clk[0]
    Info (332111):    3.333 board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|phy_clk[1]
    Info (332111):    6.666 board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_c_counters[3]
    Info (332111):    1.666 board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LOADEN0
    Info (332111):    3.333 board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_Duplicate_1LVDS_CLK0
    Info (332111):    1.666 board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_DuplicateLOADEN0
    Info (332111):    3.333 board_inst|mem|ddr4|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_inst~_DuplicateLVDS_CLK0
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[0]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[0]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[0]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[0]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[0]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[0]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[1]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[1]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[1]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[1]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[1]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[1]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[2]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[2]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[2]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[2]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[2]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[2]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[3]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[3]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[3]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[3]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[3]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[3]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[4]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[4]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[4]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[4]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[4]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[4]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[5]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[5]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[5]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[5]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[5]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[5]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[6]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[6]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[6]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[6]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[6]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[6]|tx_clk
    Info (332111):    4.000 board_inst|pcie|g_xcvr_native_insts[7]|pma_hclk_by2
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[7]|rx_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[7]|rx_clkout
    Info (332111):   10.000 board_inst|pcie|g_xcvr_native_insts[7]|rx_fref
    Info (332111):    2.000 board_inst|pcie|g_xcvr_native_insts[7]|rx_pma_clk
    Info (332111):   25.600 board_inst|pcie|g_xcvr_native_insts[7]|tx_clk
    Info (332111):    2.000 board_inst|pcie|hip_cmn_clk[0]
    Info (332111):    4.000 board_inst|pcie|pld_clk
    Info (332111):    2.000 board_inst|pcie|pll_pcie_clk
    Info (332111):    0.250 board_inst|pcie|twentynm_atx_pll_inst~O_CLK0_8G
    Info (332111):    6.400 board_inst|pcie|tx_bonding_clocks[0]
    Info (332111):   25.600 board_inst|pcie|tx_clkout
    Info (332111):    0.400 board_inst|pcie|tx_serial_clk
    Info (332111):    4.000 board_inst|pcie|wys~CORE_CLK_OUT
    Info (332111):   20.000   config_clk
    Info (332111):    8.000 kernel_pll_refclk
    Info (332111):   10.000  pcie_refclk
    Info (332111):    6.666  pll_ref_clk
Info (12263): Fitter periphery placement operations ending: elapsed time is 00:03:32
Info (11165): Fitter preparation operations ending: elapsed time is 00:03:17
Info (170189): Fitter placement preparation operations beginning
Critical Warning: Compiling with slowed OpenCL Kernel clock.  This is to help achieve timing closure for board bringup.
Info (14951): The Fitter is using Advanced Physical Optimization.
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:02:05
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:21
Critical Warning: Compiling with slowed OpenCL Kernel clock.  This is to help achieve timing closure for board bringup.
Info (11888): Total time spent on timing analysis during Placement is 49.58 seconds.
Info (170193): Fitter routing operations beginning
Info (170239): Router is attempting to preserve 100.00 percent of routes from an earlier compilation, a user specified Routing Constraints File, or internal routing requirements.
Info (170195): Router estimated average interconnect usage is 6% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 69% of the available device resources in the region that extends from location X11_Y71 to location X22_Y81
Critical Warning: Compiling with slowed OpenCL Kernel clock.  This is to help achieve timing closure for board bringup.
Info (11888): Total time spent on timing analysis during Routing is 7.60 seconds.
Info (16607): Fitter routing operations ending: elapsed time is 00:02:28
Info (11888): Total time spent on timing analysis during Post-Routing is 3.64 seconds.
Info (16557): Fitter post-fit operations ending: elapsed time is 00:02:36
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Info: Quartus Prime Fitter was successful. 0 errors, 104 warnings
    Info: Peak virtual memory: 12786 megabytes
    Info: Processing ended: Wed Mar 21 06:29:16 2018
    Info: Elapsed time: 00:16:23
    Info: Total CPU time (on all processors): 01:29:05
Info (19538): Reading SDC files took 00:00:04 cumulatively in this process.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
    Info: Version 17.1.2 Build 304 01/31/2018 SJ Pro Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Mar 21 06:29:21 2018
Info: Command: quartus_asm top -c base
Info: Using INI file /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/quartus.ini
Info (16677): Loading final database
Info (16734): Loading "final" snapshot for partition "root_partition".
Info (16734): Loading "final" snapshot for partition "auto_fab_0".
Info (16734): Loading "final" snapshot for partition "kernel".
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[0]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[1]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[2]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[3]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[4]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[5]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_debugaccess~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Info (16678): Successfully loaded final database: elapsed time is 00:00:11
Info: Quartus Prime Assembler was successful. 0 errors, 7 warnings
    Info: Peak virtual memory: 7791 megabytes
    Info: Processing ended: Wed Mar 21 06:30:45 2018
    Info: Elapsed time: 00:01:24
    Info: Total CPU time (on all processors): 00:01:25
Info: *******************************************************************
Info: Running Quartus Prime Compiler Database Interface
    Info: Version 17.1.2 Build 304 01/31/2018 SJ Pro Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Mar 21 06:30:47 2018
Info: Command: quartus_cdb top -c base --export_pr_static_block root_partition --snapshot final --file root_partition.qdb
Info: Quartus(args): --exclude_pr_subblocks --project top -c base --block_name root_partition --snapshot final --file root_partition.qdb
Info: Using INI file /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/quartus.ini
Info: Running design::export_block root_partition -snapshot final -file root_partition.qdb  -exclude_pr_subblocks   
Info (16677): Loading final database
Info (16734): Loading "final" snapshot for partition "root_partition".
Info (16734): Loading "final" snapshot for partition "auto_fab_0".
Info (16734): Loading "final" snapshot for partition "kernel".
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[0]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[1]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[2]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[3]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[4]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_address[5]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Warning (17912): Partition "freeze_wrapper_inst|kernel_system_inst" contains an output port, "kernel_mem0_debugaccess~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away.  Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
Info (16678): Successfully loaded final database: elapsed time is 00:00:11
Info (23030): Evaluation of Tcl script /home/shared/hdd/Quartus/17.1.0.240/quartus/common/tcl/internal/qatm_export_block.tcl was successful
Info: Quartus Prime Compiler Database Interface was successful. 0 errors, 7 warnings
    Info: Peak virtual memory: 2072 megabytes
    Info: Processing ended: Wed Mar 21 06:31:07 2018
    Info: Elapsed time: 00:00:20
    Info: Total CPU time (on all processors): 00:00:20
Info: *******************************************************************
Info: Running Quartus Prime Shell
    Info: Version 17.1.2 Build 304 01/31/2018 SJ Pro Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Mar 21 06:31:09 2018
Info: Command: quartus_sh --archive -input tmp_list_base_bak -output base_bak.qar
Info: Quartus(args): -qar -input tmp_list_base_bak -output base_bak.qar
Info: Using INI file /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/quartus.ini
Info: qar.tcl version #1
Info: Archive will store files relative to the closest common parent directory
Info (13213): Using common directory /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/
Info: ----------------------------------------------------------
Info: ----------------------------------------------------------
Info: Generated archive 'base_bak.qar'
Info: ----------------------------------------------------------
Info: ----------------------------------------------------------
Info (23030): Evaluation of Tcl script /home/shared/hdd/Quartus/17.1.0.240/quartus/common/tcl/apps/qpm/qar.tcl was successful
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 690 megabytes
    Info: Processing ended: Wed Mar 21 06:31:10 2018
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01
Info: *******************************************************************
Info: Running Quartus Prime Shell
    Info: Version 17.1.2 Build 304 01/31/2018 SJ Pro Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Mar 21 06:31:11 2018
Info: Command: quartus_sh --archive -input bak_list.txt -output qdb.qar
Info: Quartus(args): -qar -input bak_list.txt -output qdb.qar
Info: Using INI file /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/quartus.ini
Info: qar.tcl version #1
Info: Archive will store files relative to the closest common parent directory
Info (13213): Using common directory /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/qdb/
Info: ----------------------------------------------------------
Info: ----------------------------------------------------------
Info: Generated archive 'qdb.qar'
Info: ----------------------------------------------------------
Info: ----------------------------------------------------------
Info (23030): Evaluation of Tcl script /home/shared/hdd/Quartus/17.1.0.240/quartus/common/tcl/apps/qpm/qar.tcl was successful
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 690 megabytes
    Info: Processing ended: Wed Mar 21 06:31:16 2018
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:05
Info (125061): Changed top-level design entity name to "top"
Info (125061): Changed top-level design entity name to "kernel_system"
Info: *******************************************************************
Info: Running Quartus Prime Synthesis
    Info: Version 17.1.2 Build 304 01/31/2018 SJ Pro Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Mar 21 06:31:18 2018
Info: Command: quartus_syn top -c top_synth
Info: Using INI file /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/quartus.ini
Info: qis_default_flow_script.tcl version: #1
Info: Initializing Synthesis...
Info: Project = "top"
Info: Revision = "top_synth"
Info: Analyzing source files
Error (18185): Your design contains IP components that must be regenerated. To regenerate your IP, use the Upgrade IP Components dialog box, available on the Project menu in the Quartus Prime software
    Error (18186): You must upgrade the IP component instantiated in file ip/board/board_pcie.ip to the latest version of the IP component.
        Error (18187): <a href="https://documentation.altera.com/#/link/hco1421698042087/hco1421697756668">Release Notes</a>

Error: Flow failed: ERROR: Current design not found

Error: Quartus Prime Synthesis was unsuccessful. 4 errors, 0 warnings
    Error: Peak virtual memory: 834 megabytes
    Error: Processing ended: Wed Mar 21 06:31:36 2018
    Error: Elapsed time: 00:00:18
    Error: Total CPU time (on all processors): 00:00:37
Info: *******************************************************************
Info: Running Quartus Prime Compiler Database Interface
    Info: Version 17.1.2 Build 304 01/31/2018 SJ Pro Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Mar 21 05:47:47 2018
Info: Command: quartus_cdb -t import_compile.tcl
Info: Using INI file /home/team1/Documents/hardware_acceleration/test1/SimpleKernel/quartus.ini
Info: Checking for OpenCL SDK installation, environment should have INTELFPGAOCLSDKROOT defined
Info: INTELFPGAOCLSDKROOT=/home/shared/hdd/Quartus/17.1.0.240/hld
Info: Successfully completed BAK flow
Info: To reduce compile time on future compiles, you can generate a BAK cache by adding the arguments '--bsp-flow regenerate_cache' to aoc to skip BAK
Info: Retry strategy set to "retry-flat"
Info: Initial preservation set to "final"
Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful
Error: Quartus Prime Compiler Database Interface was unsuccessful. 1 error, 0 warnings
    Error: Peak virtual memory: 686 megabytes
    Error: Processing ended: Wed Mar 21 06:31:37 2018
    Error: Elapsed time: 00:43:50
    Error: Total CPU time (on all processors): 01:56:50