library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity MemoryMappedAvalonMasterForSDRAM is
		Port (
			-- clk-Interface
			clk_in : in std_logic;
			-- reset- Interface
			reset_n_in : in std_logic;
			--Avalon-MM Master Interface
			data_in : in std_logic_vector(15 downto 0);
			valid_in : in std_logic;
			waitrequest_in : in std_logic;
			
			address_out : out std_logic_vector(31 downto 0);
			byteenable_n_out : out std_logic_vector(1 downto 0);
			chipselect_out : out std_logic;
			data_out : out std_logic_vector(15 downto 0);
			read_n_out : out std_logic;
			write_n_out : out std_logic			
		);
end entity MemoryMappedAvalonMasterForSDRAM;

architecture MemoryMappedAvalonMasterForSDRAM of MemoryMappedAvalonMasterForSDRAM is

	-- Build an enumerated type for the state machine
	type state_type is (
	                      state_reset, state_ready, state_write
							  );
									
	-- Register to hold the current state
	signal state : state_type;
	
	-- Signals For Avalon MM Master Interface
	signal address : std_logic_vector(31 downto 0);
	signal address_old : std_logic_vector(31 downto 0);
	signal byteenable_n : std_logic_vector(1 downto 0);
	signal byteenable_n_old : std_logic_vector(1 downto 0);
	signal chipselect : std_logic;
	signal chipselect_old : std_logic;
	signal dataOut : std_logic_vector(15 downto 0);
	signal dataOut_old : std_logic_vector(15 downto 0);
	signal read_n : std_logic;
	signal read_n_old : std_logic;
	signal write_n : std_logic;			
	signal write_n_old : std_logic;			

	-- Counter for seconds
	signal counter : integer range 0 to 50000000;
	signal counter_old : integer range 0 to 50000000;
	
	
begin

	process (clk_in, reset_n_in)
	begin
		if ( reset_n_in = '0' ) then
			state <= state_reset;
		elsif ( rising_edge(clk_in) ) then
			-- Determine the next state synchronously, based on
			-- the current state and the input
			case state is
				when state_reset =>
					state <= state_ready;
				
				when state_ready =>
					if ( counter_old = 0 ) then
						state <= state_write;
					else
						state <= state_ready;
					end if;
					
				when state_write =>
					if (waitrequest_in = '1' ) then
						state <= state_write;
					else
						state <= state_ready;
					end if;
			end case;
			
		end if;	
	end process;

		
			
	-- Determine the output based only on the current state
	-- and the input (do not wait for a clock edge).
	process (state, address_old, byteenable_n_old, chipselect_old, dataOut_old,
				read_n_old, write_n_old, counter_old, waitrequest_in)
	begin
	
		address_out <= address_old;
		byteenable_n_out <= byteenable_n_old;
		chipselect_out <= chipselect_old;
		data_out <= dataOut_old;
		read_n_out <= read_n_old;
		write_n_out <= write_n_old;	
		dataOut <= dataOut_old;
		
		case state is
			when state_reset =>
				-- Signals For Avalon MM Master Interface
				address <= (others => '0');
				byteenable_n <= (others => '0');
				chipselect <= '0';
				dataOut <= (others => '0');
				read_n <= '1';
				write_n <= '1';
				counter <= 5000000;
			
			when state_ready =>
				address <= x"02000008";
				byteenable_n <= (others => '0');
				chipselect <= '0';
				--dataOut <= "1111111111111111";
				read_n <= '1';
				write_n <= '1';
				if ( counter_old = 0 ) then
					counter <= 5000000;
				else
					counter <= counter_old - 1;
				end if;

				
			when state_write =>
--				if ( waitrequest_in = '1' ) then
--					address <= address_old;
--				elsif (address_old = x"02000011" ) then
--					address <= x"02000008";
--				else
--					address <= std_logic_vector(unsigned(address_old) + 1);
--				end if;
				address <= x"02000000";--x"02000008";--std_logic_vector(unsigned(address_old) + 1);
				byteenable_n <= "01";--(others => '0');
				chipselect <= '1';
				--dataOut <= "1011111001111011";
				dataOut <= std_logic_vector(unsigned(dataOut_old) + 1);--(others => '1');
				read_n <= '1';
				write_n <= '0';
				counter <= counter_old;						
			end case;
			
	end process;
	

	--------------------------------------------------------------------------------------------
	-- uebernahme der aktuellen Werte in die Register
	--------------------------------------------------------------------------------------------
	process (
				clk_in
			) 
	begin
		if (rising_edge(clk_in)) then
			address_old <= address;
			byteenable_n_old <= byteenable_n;
			chipselect_old <= chipselect;
			dataOut_old <= dataOut;
			read_n_old <= read_n;
			write_n_old <= write_n;	
			counter_old <= counter;				
		end if;
	end process;

end architecture MemoryMappedAvalonMasterForSDRAM; -- of MemoryMappedAvalonMasterForSDRAM