module wave(clk, out);
input clk;
output out;
reg [7:0] duty_cycle;
wire en;
pwm u1(.duty_cycle(duty_cycle), .clk(clk), .out(out), .en(en));
reg[15:0] counter;
reg[15:0] next_counter;

always @(posedge clk)
      begin
counter = next_counter;
      end
      always @*
      begin
next_counter = counter+1;
case(counter[15:0])
0 : duty_cycle = 128;
1 : duty_cycle = 131;
2 : duty_cycle = 134;
3 : duty_cycle = 137;
4 : duty_cycle = 140;
5 : duty_cycle = 143;
6 : duty_cycle = 146;
7 : duty_cycle = 149;
8 : duty_cycle = 152;
9 : duty_cycle = 156;
10 : duty_cycle = 159;
11 : duty_cycle = 162;
12 : duty_cycle = 165;
13 : duty_cycle = 168;
14 : duty_cycle = 171;
15 : duty_cycle = 174;
16 : duty_cycle = 176;
17 : duty_cycle = 179;
18 : duty_cycle = 182;
19 : duty_cycle = 185;
20 : duty_cycle = 188;
21 : duty_cycle = 191;
22 : duty_cycle = 193;
23 : duty_cycle = 196;
24 : duty_cycle = 199;
25 : duty_cycle = 201;
26 : duty_cycle = 204;
27 : duty_cycle = 206;
28 : duty_cycle = 209;
29 : duty_cycle = 211;
30 : duty_cycle = 213;
31 : duty_cycle = 216;
32 : duty_cycle = 218;
33 : duty_cycle = 220;
34 : duty_cycle = 222;
35 : duty_cycle = 224;
36 : duty_cycle = 226;
37 : duty_cycle = 228;
38 : duty_cycle = 230;
39 : duty_cycle = 232;
40 : duty_cycle = 234;
41 : duty_cycle = 236;
42 : duty_cycle = 237;
43 : duty_cycle = 239;
44 : duty_cycle = 240;
45 : duty_cycle = 242;
46 : duty_cycle = 243;
47 : duty_cycle = 245;
48 : duty_cycle = 246;
49 : duty_cycle = 247;
50 : duty_cycle = 248;
51 : duty_cycle = 249;
52 : duty_cycle = 250;
53 : duty_cycle = 251;
54 : duty_cycle = 252;
55 : duty_cycle = 252;
56 : duty_cycle = 253;
57 : duty_cycle = 254;
58 : duty_cycle = 254;
59 : duty_cycle = 255;
60 : duty_cycle = 255;
61 : duty_cycle = 255;
62 : duty_cycle = 255;
63 : duty_cycle = 255;
64 : duty_cycle = 255;
65 : duty_cycle = 255;
66 : duty_cycle = 255;
67 : duty_cycle = 255;
68 : duty_cycle = 255;
69 : duty_cycle = 255;
70 : duty_cycle = 254;
71 : duty_cycle = 254;
72 : duty_cycle = 253;
73 : duty_cycle = 252;
74 : duty_cycle = 252;
75 : duty_cycle = 251;
76 : duty_cycle = 250;
77 : duty_cycle = 249;
78 : duty_cycle = 248;
79 : duty_cycle = 247;
80 : duty_cycle = 246;
81 : duty_cycle = 245;
82 : duty_cycle = 243;
83 : duty_cycle = 242;
84 : duty_cycle = 240;
85 : duty_cycle = 239;
86 : duty_cycle = 237;
87 : duty_cycle = 236;
88 : duty_cycle = 234;
89 : duty_cycle = 232;
90 : duty_cycle = 230;
91 : duty_cycle = 228;
92 : duty_cycle = 226;
93 : duty_cycle = 224;
94 : duty_cycle = 222;
95 : duty_cycle = 220;
96 : duty_cycle = 218;
97 : duty_cycle = 216; 
98 : duty_cycle = 213;
99 : duty_cycle = 211;
100 : duty_cycle = 209;
101 : duty_cycle = 206;
102 : duty_cycle = 204;
103 : duty_cycle = 201;
104 : duty_cycle = 199;
105 : duty_cycle = 196;
106 : duty_cycle = 193;
107 : duty_cycle = 191;
108 : duty_cycle = 188;
109 : duty_cycle = 185;
110 : duty_cycle = 182;
111 : duty_cycle = 179;
112 : duty_cycle = 176;
113 : duty_cycle = 174;
114 : duty_cycle = 171;
115 : duty_cycle = 168;
116 : duty_cycle = 165;
117 : duty_cycle = 162;
118 : duty_cycle = 159;
119 : duty_cycle = 156;
120 : duty_cycle = 152;
121 : duty_cycle = 149;
122 : duty_cycle = 146;
123 : duty_cycle = 143;
124 : duty_cycle = 140;
125 : duty_cycle = 137;
126 : duty_cycle = 134;
127 : duty_cycle = 131; /////
128 : duty_cycle = 128;
129 : duty_cycle = 124;
130 : duty_cycle = 121;
131 : duty_cycle = 118;
132 : duty_cycle = 115;
133 : duty_cycle = 112;
134 : duty_cycle = 109;
135 : duty_cycle = 106;
136 : duty_cycle = 103;
137 : duty_cycle = 99;
138 : duty_cycle = 96;
139 : duty_cycle = 93;
140 : duty_cycle = 90;
141 : duty_cycle = 87;
142 : duty_cycle = 84;
143 : duty_cycle = 81;
144 : duty_cycle = 79;
145 : duty_cycle = 76;
146 : duty_cycle = 73;
147 : duty_cycle = 70;
148 : duty_cycle = 67;
149 : duty_cycle = 64;
150 : duty_cycle = 62;
151 : duty_cycle = 59;
152 : duty_cycle = 56;
153 : duty_cycle = 54;
154 : duty_cycle = 51;
155 : duty_cycle = 49;
156 : duty_cycle = 46;
157 : duty_cycle = 44;
158 : duty_cycle = 42;
159 : duty_cycle = 39;
160 : duty_cycle = 37;
161 : duty_cycle = 35;
162 : duty_cycle = 33;
163 : duty_cycle = 31;
164 : duty_cycle = 29;
165 : duty_cycle = 27;
166 : duty_cycle = 25;
167 : duty_cycle = 23;
168 : duty_cycle = 21;
169 : duty_cycle = 19;
170 : duty_cycle = 18;
171 : duty_cycle = 16;
172 : duty_cycle = 15;
173 : duty_cycle = 13;
174 : duty_cycle = 12;
175 : duty_cycle = 10;
176 : duty_cycle = 9;
177 : duty_cycle = 8;
178 : duty_cycle = 7;
179 : duty_cycle = 6;
180 : duty_cycle = 5;
181 : duty_cycle = 4;
182 : duty_cycle = 3;
183 : duty_cycle = 3;
184 : duty_cycle = 2;
185 : duty_cycle = 1;
186 : duty_cycle = 1;
187 : duty_cycle = 0;
188 : duty_cycle = 0;
189 : duty_cycle = 0;
190 : duty_cycle = 0;
191 : duty_cycle = 0;
192 : duty_cycle = 0;
193 : duty_cycle = 0;
194 : duty_cycle = 0;
195 : duty_cycle = 0;
196 : duty_cycle = 0;
197 : duty_cycle = 0;
198 : duty_cycle = 1;
199 : duty_cycle = 1;
200 : duty_cycle = 2;
201 : duty_cycle = 3;
202 : duty_cycle = 3;
203 : duty_cycle = 4;
204 : duty_cycle = 5;
205 : duty_cycle = 6;
206 : duty_cycle = 7;
207 : duty_cycle = 8;
208 : duty_cycle = 9;
209 : duty_cycle = 10;
210 : duty_cycle = 12;
211 : duty_cycle = 13;
212 : duty_cycle = 15;
213 : duty_cycle = 16;
214 : duty_cycle = 18;
215 : duty_cycle = 19;
216 : duty_cycle = 21;
217 : duty_cycle = 23;
218 : duty_cycle = 25;
219 : duty_cycle = 27;
220 : duty_cycle = 29;
221 : duty_cycle = 31;
222 : duty_cycle = 33;
223 : duty_cycle = 35;
224 : duty_cycle = 37;
225 : duty_cycle = 39;
226 : duty_cycle = 42;
227 : duty_cycle = 44;
228 : duty_cycle = 46;
229 : duty_cycle = 49;
230 : duty_cycle = 51;
231 : duty_cycle = 54;
232 : duty_cycle = 56;
233 : duty_cycle = 59;
234 : duty_cycle = 62;
235 : duty_cycle = 64;
236 : duty_cycle = 67;
237 : duty_cycle = 70;
238 : duty_cycle = 73;
239 : duty_cycle = 76;
240 : duty_cycle = 79;
241 : duty_cycle = 81; 
242 : duty_cycle = 84;
243 : duty_cycle = 87;
244 : duty_cycle = 90;
245 : duty_cycle = 93;
246 : duty_cycle = 96;
247 : duty_cycle = 99;
248 : duty_cycle = 103;
249 : duty_cycle = 106;
250 : duty_cycle = 109;
251 : duty_cycle = 112;
252 : duty_cycle = 115;
253 : duty_cycle = 118;
254 : duty_cycle = 121;
255 : duty_cycle = 124;

     endcase
     end
assign en = 1;
     endmodule

module pwm(clk,en,duty_cycle,out);
input clk;
input en;
input[7:0] duty_cycle;
output reg out;
reg[7:0] counter;
reg[7:0] next_counter;
always @(posedge clk)
     begin
counter = next_counter;
    end
always @ *
    begin
if(en)
    begin
if(counter<duty_cycle)
    begin
out = 1;
    end
else
    begin
out = 0;
       end
next_counter = counter+1;
       end
else
   begin
next_counter = 0;
       end
     end
  endmodule