library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.standard;


entity read is
	port (clk	: in std_logic;
		  reset	: in std_logic;
		  adc_in1,adc_in2,adc_in3,adc_in4,adc_in5,adc_in6,adc_in7,adc_in8,adc_in9,adc_in10,adc_in11,adc_in12,adc_in13,adc_in14,adc_in15,adc_in16 : in std_logic_vector (7 downto 0);
	      adc_out1,adc_out2,adc_out3,adc_out4,adc_out5,adc_out6,adc_out7,adc_out8,adc_out9,adc_out10,adc_out11,adc_out12,adc_out13,adc_out14,adc_out15,adc_out16: out std_logic);

end read;

architecture a of read is 
	signal IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7 : std_logic; 

	begin
	p1: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out1 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;--8bit
		
	end process p1;
	
	p2: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out2 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;
	end process p2;
	
	p3: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out3 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;	
	end process p3;
	
	p4: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out4 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;	
	end process p4;
	
	p5: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out5 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;	
	end process p5;
	
	p6: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out6 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;	
	end process p6;
	
	p7: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out7 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;	
	end process p7;
	
	p8: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out8<= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;	
	end process p8;
	
	p9: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out9 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;	
	end process p9;
	
	p10: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out10 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;	
	end process p10;
	
	p11: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out11 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;	
	end process p11;
	
	p12: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out12 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;	
	end process p12;
	
	p13: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out13<= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;	
	end process p13;
	
	p14: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out14 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;	
	end process p14;
	
	p15: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out15 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;	
	end process p15;
	
	p16: process (IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
	begin
		adc_out16 <= IN7 and IN6 and IN5 and IN4 and IN3 and IN2 and IN1 and IN0;
	end process p16;
	

end a;