module freqs(clk,lwrfreq,dut,pwm,ton,uprfreq,stepsize,pwmop);
input clk;
input [7:0]dut;
output [5:0]ton;  
reg [15:0]ctr;
reg ton;
output pwm ;
reg pwm;
reg [15:0]counter=0;
reg[15:0]counter1=0;
           
input [32:0] lwrfreq;   
input[32:0]uprfreq;
input [32:0]stepsize;
output[2:0]pwmop;
reg[2:0]counter2=1;
reg [50:0]currentfreq=0;
assign pwmop= ((uprfreq-lwrfreq)/stepsize);	// total nof pwm op posible= (lower-uper/stepsize)

		
for(counter2=1;counter2<=pwmop;counter2=counter2+1;)
begin
		always @(posedge clk)
		begin 
		currentfreq =(currentfreq+stepsize);// for current pwm freq, determines required counter.
		ctr=(50000000/currentfreq);
		ton=((ctr*dut)/100);	
	
			counter=counter+1;
			if(counter<=ctr) 
				begin
				counter1=counter1+1;
				if(counter1<=ton)          // duty cycle variation
				pwm=1;
				else
				pwm=0;
				end
			else
				begin
				counter=0;
				counter1=0;
				end
		end	
end

	

endmodule