To Do:
1.	How do I simulate the ADC input data in Modelsim?  AUD_ADCDAT is a std_logic
	
FSM:
use two state machines
	* first: selects the 24 bits of address/data to send, and puts into a bit vector
	* second: sends one bit at a time from the input bit vector => 27 states (24 bits + 3 high impedance for ack)+ 3 more for start condition?.
	process(clock,reset,i2c_counter,i2c_data)
	i2cdata <= '1' when control = '1' else 'Z' -- ack states
	
	--clock trick.  after start condition invert the clock to prevent delay issues with the ack bits
	outputclock <= not clock when i2ccounter >= 3 else '0'; --does this mean first 3 states are for start condition
	--what each state sets: control,datavector, clock,done
	
	
	
ROM: rom width is 24bits: 8 for the constant slave address, 16 for the register + data
	rom depth is the 11 registers that can be set in the Wolfson
	
	MegaWizard, memory compiler, rom 1 port,  
		* 24 bit width, 32 words (min).  32 is a physical limit of the FPGA
		* Memory type block: Auto
		* Single clock
		* Use the 50MHz clock for the ROM component
		* Initialize using .mif file.
		* create separate module to change the ROM address used by the FSM
			* Simple increments the address when it gets the "increment" signal from the FSM
	.mif file:
		* Quartus > new file > .mif file
		* When creating the ROM in wizard, specify the mif/hex file to use with initial ROM data
	
	RAM is bigger and faster than ROM, but data is temporary.
	
	FPGA (MegaIP Wizard) Memory: 
		* SDRAM: difficult to intergace.  MegaIP includes interface "core". Synchronous
		* SRAM: Asynchronous, easy to interface.
		* Flash: ROM
		
Modelsim change wave colors: Tools > edit preferences > wave windows

Report:
	* Save screenshots

SIGNAL TAP:
	* signal congiguration clock: clock that signal tap samples at.  Clock must not be too fast, since memory is limited.

ADC/DAC:
	* what frequency should MCLK run at on the audio codec?  cannot use pll to get this with 27MHz,50MHz or 24MHz clocks
	* freq of DACLRC/ADCLRC are = fs = 48KHz?
	* using slave mode, left-justified mode
	* BitClock: 16-bits for left channel and 16-bits for right channel. Transfer on falling edge => 
	  negative_edge(bitClock).  sampling freq(fs) = 48KHz.
	  * countValue = 12. BitClock has period of 12 counts (countValue).
	* ADCLR/DACLR switch every 16 periods of bitCount
	* Loopback test: adcDat = dacDat.
	
Neuron:
	* Represent decimal(real) numbers in digital systems.
		* Fixed point: simpler. specify number of decimal places.
		* Floating point:
	* Euler's method: 
	* Cyclone 2 uses 9 bit multipliers => use 18 bit fixed point for exactly 2 multipliers
		* multiply 9 bit by 9 bit => need 18 bits to store the product
	* DAC/ADC voltage range -1 to 1 (rails)
	* codec can only accept 16 bits => chop off the 2 least significant bits
	* use left/right select clock to determine when each set of 16 bits has been sent
	* use bit clock (38kHz) to sent 16 bits one at a time
		* lower to 100 Hz 
		
Fixed point: 
	* can't use integers because quartus doesn't recognize the fixed point format => use std_logic
	* can just add std_logic_vectors, because overflow is not a problem with the numbers in the model
	* if multiplied numbers are not 18-bits, quartus will not use built-in multipliers, and synthesize in
		lookup tables instead.
		* use 9/52 multipliers => uses only 2% of the FPGA
	* can I just shift each number left by 16 bits, multiply as integers, then shift the product right 
	  by 32 bits? yes
	  
