WOW thanks for such a quick response !

This has, and still is, a very steep learning curve, but here's what i've found.

I set the constraints as you said, as follows

1) # the clock input to the device
  create_clock -name src_clk -period 125MHz [get_ports src_clk]

2) # the clock output (inversion of input)
  create_generated_clock -name inv_src_clk_out -invert -source [get_ports src_clk]

3) # set relationship between the clock going out and the data going out
   set_output_delay -min 0.0 -clock [get_clocks inv_src_clk_out] [get_ports data_out]
   set_output_delay -max 0.0 -clock [get_clocks inv_src_clk_out] [get_ports data_out]

which didn't meet timing and produced the following


               ______       
launch      __|      |_______
                        
                     :   
                      _______
latch       _________|    
                     :   
                     :     :
data arriv  _________:_____:_______
            _______________X________
                     :     :  
                     :     : 
                     :     : 
data reqd   _________:_____:__
            _________X_____:___
                     :     :  
                     :     :  
                        

Relationship 4ns
Clock Delay : 3.249
Data Delay : 3.229
Data Arrival : 6.478
Data Reqd : 4
some clock uncertainty
Slack : -2.498


One thing i'm not sure about is that this 'model' does not take into account the delay of the clock through 
the ALTDDIO cell which i've checked as being 5.075 ns (report -from src_clk -to inv_src_clk_out -through altddio cell)


Questions:


1) what happened to using virtual clocks ?

2) would i be correct in assuming that if this delay is added to the relationship somehow, this would then shift the
latch clock to the right by 5.075 ns giving me a new setup of 2.557 ns and meeting timing

3) do my set_output_delay commands need modifying as i'm not 100% sure i understand what they are doing.