Info: Saving generation log to D:/Project/Adv213_Motor/src/quartus19.1/bak/proj_Spi3_181223/proj_qsys/proj_qsys_generation.rpt
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate D:\Project\Adv213_Motor\src\quartus19.1\bak\proj_Spi3_181223\proj_qsys.qsys --block-symbol-file --output-directory=D:\Project\Adv213_Motor\src\quartus19.1\bak\proj_Spi3_181223\proj_qsys --family="MAX 10" --part=10M50DAF484C6GES
Progress: Loading proj_Spi3_181223/proj_qsys.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 19.1]
Progress: Parameterizing module clk_0
Progress: Adding jtag_uart_0 [altera_avalon_jtag_uart 19.1]
Progress: Parameterizing module jtag_uart_0
Progress: Adding nios2_gen2_0 [altera_nios2_gen2 19.1]
Progress: Parameterizing module nios2_gen2_0
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 19.1]
Progress: Parameterizing module onchip_memory2_0
Progress: Adding spi_0 [altera_avalon_spi 19.1]
Progress: Parameterizing module spi_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: proj_qsys.jtag_uart_0: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate D:\Project\Adv213_Motor\src\quartus19.1\bak\proj_Spi3_181223\proj_qsys.qsys --synthesis=VERILOG --output-directory=D:\Project\Adv213_Motor\src\quartus19.1\bak\proj_Spi3_181223\proj_qsys\synthesis --family="MAX 10" --part=10M50DAF484C6GES
Progress: Loading proj_Spi3_181223/proj_qsys.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 19.1]
Progress: Parameterizing module clk_0
Progress: Adding jtag_uart_0 [altera_avalon_jtag_uart 19.1]
Progress: Parameterizing module jtag_uart_0
Progress: Adding nios2_gen2_0 [altera_nios2_gen2 19.1]
Progress: Parameterizing module nios2_gen2_0
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 19.1]
Progress: Parameterizing module onchip_memory2_0
Progress: Adding spi_0 [altera_avalon_spi 19.1]
Progress: Parameterizing module spi_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: proj_qsys.jtag_uart_0: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: proj_qsys: Generating proj_qsys "proj_qsys" for QUARTUS_SYNTH
Info: jtag_uart_0: Starting RTL generation for module 'proj_qsys_jtag_uart_0'
Info: jtag_uart_0:   Generation command is [exec C:/intelfpga_lite/19.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=proj_qsys_jtag_uart_0 --dir=C:/Users/USER/AppData/Local/Temp/alt9732_1200839851885894760.dir/0002_jtag_uart_0_gen/ --quartus_dir=C:/intelfpga_lite/19.1/quartus --verilog --config=C:/Users/USER/AppData/Local/Temp/alt9732_1200839851885894760.dir/0002_jtag_uart_0_gen//proj_qsys_jtag_uart_0_component_configuration.pl  --do_build_sim=0  ]
Info: jtag_uart_0: Done RTL generation for module 'proj_qsys_jtag_uart_0'
Info: jtag_uart_0: "proj_qsys" instantiated altera_avalon_jtag_uart "jtag_uart_0"
Info: nios2_gen2_0: "proj_qsys" instantiated altera_nios2_gen2 "nios2_gen2_0"
Info: onchip_memory2_0: Starting RTL generation for module 'proj_qsys_onchip_memory2_0'
Info: onchip_memory2_0:   Generation command is [exec C:/intelfpga_lite/19.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=proj_qsys_onchip_memory2_0 --dir=C:/Users/USER/AppData/Local/Temp/alt9732_1200839851885894760.dir/0003_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/19.1/quartus --verilog --config=C:/Users/USER/AppData/Local/Temp/alt9732_1200839851885894760.dir/0003_onchip_memory2_0_gen//proj_qsys_onchip_memory2_0_component_configuration.pl  --do_build_sim=0  ]
Info: onchip_memory2_0: Done RTL generation for module 'proj_qsys_onchip_memory2_0'
Info: onchip_memory2_0: "proj_qsys" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"
Info: spi_0: Starting RTL generation for module 'proj_qsys_spi_0'
Info: spi_0:   Generation command is [exec C:/intelfpga_lite/19.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi -- C:/intelfpga_lite/19.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/generate_rtl.pl --name=proj_qsys_spi_0 --dir=C:/Users/USER/AppData/Local/Temp/alt9732_1200839851885894760.dir/0004_spi_0_gen/ --quartus_dir=C:/intelfpga_lite/19.1/quartus --verilog --config=C:/Users/USER/AppData/Local/Temp/alt9732_1200839851885894760.dir/0004_spi_0_gen//proj_qsys_spi_0_component_configuration.pl  --do_build_sim=0  ]
Info: spi_0: Done RTL generation for module 'proj_qsys_spi_0'
Info: spi_0: "proj_qsys" instantiated altera_avalon_spi "spi_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "proj_qsys" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: irq_mapper: "proj_qsys" instantiated altera_irq_mapper "irq_mapper"
Info: rst_controller: "proj_qsys" instantiated altera_reset_controller "rst_controller"
Info: cpu: Starting RTL generation for module 'proj_qsys_nios2_gen2_0_cpu'
Info: cpu:   Generation command is [exec C:/intelFPGA_lite/19.1/quartus/bin64//perl/bin/perl.exe -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/19.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/19.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=proj_qsys_nios2_gen2_0_cpu --dir=C:/Users/USER/AppData/Local/Temp/alt9732_1200839851885894760.dir/0007_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/19.1/quartus/bin64/ --verilog --config=C:/Users/USER/AppData/Local/Temp/alt9732_1200839851885894760.dir/0007_cpu_gen//proj_qsys_nios2_gen2_0_cpu_processor_configuration.pl  --do_build_sim=0  ]
Info: cpu: # 2024.01.10 09:19:42 (*) Starting Nios II generation
Info: cpu: # 2024.01.10 09:19:42 (*)   Elaborating CPU configuration settings
Info: cpu: # 2024.01.10 09:19:42 (*)   Creating all objects for CPU
Info: cpu: # 2024.01.10 09:19:43 (*)   Generating RTL from CPU objects
Info: cpu: # 2024.01.10 09:19:43 (*)   Creating plain-text RTL
Info: cpu: # 2024.01.10 09:19:43 (*) Done Nios II generation
Info: cpu: Done RTL generation for module 'proj_qsys_nios2_gen2_0_cpu'
Info: cpu: "nios2_gen2_0" instantiated altera_nios2_gen2_unit "cpu"
Info: nios2_gen2_0_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_0_data_master_translator"
Info: jtag_uart_0_avalon_jtag_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_0_avalon_jtag_slave_translator"
Info: nios2_gen2_0_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_0_data_master_agent"
Info: jtag_uart_0_avalon_jtag_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_0_avalon_jtag_slave_agent"
Info: jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: router_003: "mm_interconnect_0" instantiated altera_merlin_router "router_003"
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: cmd_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_001"
Info: Reusing file D:/Project/Adv213_Motor/src/quartus19.1/bak/proj_Spi3_181223/proj_qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_001"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file D:/Project/Adv213_Motor/src/quartus19.1/bak/proj_Spi3_181223/proj_qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"
Info: Reusing file D:/Project/Adv213_Motor/src/quartus19.1/bak/proj_Spi3_181223/proj_qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: proj_qsys: Done "proj_qsys" with 28 modules, 41 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis