//1152000 baud rate
module uart_tx	#(parameter n = 8)(
	input					clk,
	input					rst_n,
	input		[n-1:0]	data_in,
	
	output reg			data_out
);

	localparam			[3:0]
							idle		=	0,
							start		=	1,
							d0			=	2,
							d1			=	3,
							d2      	=	4,
							d3      	=	5,
							d4      	=	6,
							d5      	=	7,
							d6      	=	8,
							d7      	=	9,
							stop1   	=	10,
							stop2   	=	11;
						
	//wire			[n-1:0]	data_in	=	8'h41;
	
	reg			[3:0]	cur_st	;
	reg			[3:0]	nxt_st	;
	
	reg			[8:0]	cnt		;
	
	wire		cnt_clr;
	
	assign		cnt_clr	=	(cnt == 433) ? 1'b1 : 1'b0;
	
	//sequential logic for cur_st
	always @(posedge clk, negedge rst_n)	begin
		if(!rst_n == 1'b1)
			cur_st	<=	idle;
		else if(cnt_clr == 1'b1)
			cur_st	<=	nxt_st;
	end
	
	//sequential logic for cnt , timer
	always @(posedge clk, negedge rst_n)	begin
		if(!rst_n == 1'b1)
			cnt	<=	0;
		else if(cnt_clr == 1'b1)
			cnt	<=	0;
		else
			cnt	<=	cnt +	1'b1;
	end
	
	//combinational logic for nxt_st
	always @(cur_st,data_in) begin
		nxt_st	=	 idle;
		case(cur_st)
			idle	:	
				nxt_st	=	start;
			start	:
				nxt_st	=	d0;
			d0		:
				nxt_st	=	d1;
			d1		:
				nxt_st	=	d2;
			d2      :
				nxt_st	=	d3;
			d3      :
				nxt_st	=	d4;
			d4      :
				nxt_st	=	d5;
			d5      :
				nxt_st	=	d6;
			d6      :
				nxt_st	=	d7;
			d7      :
				nxt_st	=	stop1;
			stop1   :
				nxt_st	=	stop2;
			stop2   :
				nxt_st	=	idle;
		endcase
	end
	
	
	always @(cur_st,data_in) begin
		data_out	=	0;
		case(cur_st)
			idle	:	data_out	=	1;
			start	:	data_out	=	0;	
			d0		:	data_out	=	data_in[0];
			d1		:	data_out	=	data_in[1];
			d2    :	data_out	=	data_in[2];
			d3    :	data_out	=	data_in[3];
			d4    :	data_out	=	data_in[4];
			d5    :	data_out	=	data_in[5];
			d6    :	data_out	=	data_in[6];
			d7    :	data_out	=	data_in[7];
			stop1 :	data_out	=	1;
			stop2 :	data_out	=	1;
		endcase
	end
	
	

endmodule