gsfi_desg |

2022.06.27.15:59:42 | Datasheet

Overview

Processor
nios2_gen2_0 Nios II 19.1.0
All Components
intel_generic_serial_flash_interface_top_0 intel_generic_serial_flash_interface_top 20.1.1
jtag_uart_0 altera_avalon_jtag_uart 19.1.0
nios2_gen2_0 altera_nios2_gen2 19.1.0
onchip_memory2_0 altera_avalon_onchip_memory2 19.2.1
Memory Map

| nios2_gen2_0
data_master | instruction_master
intel_generic_serial_flash_interface_top_0 |  |
avl_csr | 0x02201100 | 0x02201100
avl_mem | 0x01000000 | 0x01000000
jtag_uart_0 |  |
avalon_jtag_slave | 0x02201208 | 0x02201208
nios2_gen2_0 |  |
debug_mem_slave | 0x02200800 | 0x02200800
onchip_memory2_0 |  |
s1 | 0x02100000 | 0x02100000

## clock_in

altera_clock_bridge v19.2.0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## intel_generic_serial_flash_interface_top_0

intel_generic_serial_flash_interface_top v20.1.1

nios2_gen2_0 | data_master | intel_generic_serial_flash_interface_top_0
avl_csr
data_master
avl_mem
instruction_master
avl_csr
instruction_master
avl_mem
debug_reset_request
reset
clock_in | out_clk
clk
reset_in | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments (none)

## jtag_uart_0

altera_avalon_jtag_uart v19.1.0

nios2_gen2_0 | data_master | jtag_uart_0
avalon_jtag_slave
instruction_master
avalon_jtag_slave
irq
irq
debug_reset_request
reset
clock_in | out_clk
clk
reset_in | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
READ_DEPTH | 64
READ_THRESHOLD | 8
WRITE_DEPTH | 64
WRITE_THRESHOLD | 8

## nios2_gen2_0

altera_nios2_gen2 v19.1.0

clock_in | out_clk | nios2_gen2_0
clk
reset_in | out_reset
reset
|  | data_master | jtag_uart_0
|  | avalon_jtag_slave
|  | instruction_master
|  | avalon_jtag_slave
|  | irq
|  | irq
|  | debug_reset_request
|  | reset
|  | data_master | intel_generic_serial_flash_interface_top_0
|  | avl_csr
|  | data_master
|  | avl_mem
|  | instruction_master
|  | avl_csr
|  | instruction_master
|  | avl_mem
|  | debug_reset_request
|  | reset
|  | data_master | onchip_memory2_0
|  | s1
|  | instruction_master
|  | s1
|  | debug_reset_request
|  | reset1

## Parameters
generateLegacySim | false

## Software Assignments
BIG_ENDIAN | 0
BREAK_ADDR | 0x02200820
CPU_ARCH_NIOS2_R1 |
CPU_FREQ | 50000000u
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x00000000
CPU_IMPLEMENTATION | "fast"
DATA_ADDR_WIDTH | 26
DCACHE_BYPASS_MASK | 0x80000000
DCACHE_LINE_SIZE | 32
DCACHE_LINE_SIZE_LOG2 | 5
DCACHE_SIZE | 2048
EXCEPTION_ADDR | 0x02100020
FLASH_ACCELERATOR_LINES | 0
FLASH_ACCELERATOR_LINE_SIZE | 0
FLUSHDA_SUPPORTED |
HARDWARE_DIVIDE_PRESENT | 0
HARDWARE_MULTIPLY_PRESENT | 1
HARDWARE_MULX_PRESENT | 0
HAS_DEBUG_CORE | 1
HAS_DEBUG_STUB |
HAS_EXTRA_EXCEPTION_INFO |
HAS_ILLEGAL_INSTRUCTION_EXCEPTION |
HAS_JMPI_INSTRUCTION |
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 2048
INITDA_SUPPORTED |
INST_ADDR_WIDTH | 26
NUM_OF_SHADOW_REG_SETS | 0
OCI_VERSION | 1
RESET_ADDR | 0x02100000

## onchip_memory2_0

altera_avalon_onchip_memory2 v19.2.1

nios2_gen2_0 | data_master | onchip_memory2_0
s1
instruction_master
s1
debug_reset_request
reset1
clock_in | out_clk
clk1
reset_in | out_reset
reset1

## Parameters
generateLegacySim | false

## Software Assignments
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE | 0
CONTENTS_INFO | ""
DUAL_PORT | 0
GUI_RAM_BLOCK_TYPE | AUTO
INIT_CONTENTS_FILE | gsfi_desg_onchip_memory2_0_onchip_memory2_0
INIT_MEM_CONTENT | 1
INSTANCE_ID | NONE
NON_DEFAULT_INIT_FILE_ENABLED | 0
RAM_BLOCK_TYPE | AUTO
READ_DURING_WRITE_MODE | DONT_CARE
SINGLE_CLOCK_OP | 0
SIZE_MULTIPLE | 1
SIZE_VALUE | 655356
WRITABLE | 1

## reset_in

altera_reset_bridge v19.2.0

clock_in | out_clk | reset_in
clk
|  | out_reset | nios2_gen2_0
|  | reset
|  | out_reset | jtag_uart_0
|  | reset
|  | out_reset | intel_generic_serial_flash_interface_top_0
|  | reset
|  | out_reset | onchip_memory2_0
|  | reset1

## Parameters
generateLegacySim | false

## Software Assignments (none)

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