cycloneIII_3c25_niosII_standard_sopc |

2010.05.17.23:15:34 | Datasheet

Overview

clk | cycloneIII_3c25_niosII_standard_sopc
| button_pio
| in_port
| out_port

Processor
cpu Nios II 9.1
Peripherals
pll altera_avalon_pll 9.1
cpu altera_nios2 9.1
flash_ssram_pipeline_bridge altera_avalon_pipeline_bridge 9.1
pipeline_bridge_before_tristate_bridge altera_avalon_pipeline_bridge 9.1
flash_ssram_tristate_bridge altera_avalon_tri_state_bridge 9.1
ddr_sdram altmemddr 9.1
cpu_ddr_clock_bridge altera_avalon_clock_crossing 9.1
slow_peripheral_bridge altera_avalon_clock_crossing 9.1
sys_clk_timer altera_avalon_timer 9.1
high_res_timer altera_avalon_timer 9.1
sysid altera_avalon_sysid 9.1
performance_counter altera_avalon_performance_counter 9.1
jtag_uart altera_avalon_jtag_uart 9.1
button_pio altera_avalon_pio 9.1
led_pio altera_avalon_pio 9.1
remote_update altera_avalon_remote_update_cycloneiii 9.1
alt_vip_vfr_0 alt_vip_vfr 9.1
alt_vip_itc_0 alt_vip_itc 9.1
Memory Map

| cpu | alt_vip_vfr_0
instruction_master | data_master | avalon_master
pll |  |  |
s1 |  | 0x08000140 |
cpu |  |  |
jtag_debug_module | 0x02000800 | 0x02000800 |
ssram |  |  |
s1 | 0x05000000 | 0x05000000 |
ext_flash |  |  |
s1 | 0x04000000 | 0x04000000 |
ddr_sdram |  |  |
s1 | 0x00000000 | 0x00000000 | 0x00000000
sys_clk_timer |  |  |
s1 |  | 0x08000160 |
high_res_timer |  |  |
s1 |  | 0x08000100 |
sysid |  |  |
control_slave |  | 0x080001a8 |
performance_counter |  |  |
control_slave |  | 0x08000120 |
jtag_uart |  |  |
avalon_jtag_slave |  | 0x080001a0 |
button_pio |  |  |
s1 |  | 0x08000180 |
led_pio |  |  |
s1 |  | 0x08000190 |
remote_update |  |  |
s1 |  | 0x08000000 |
alt_vip_vfr_0 |  |  |
avalon_slave |  | 0x02001400 |
alt_vip_itc_0 |  |  |
control |  | 0x02001000 |

## clk

clock_source v9.1

## Parameters
clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## pll

altera_avalon_pll v9.1

clk | clk | pll
inclk0
slow_peripheral_bridge | m1
s1
|  | c0 | cpu_ddr_clock_bridge
|  | clk_s1
|  | c0 | cpu
|  | clk
|  | c0 | ext_flash
|  | clk
|  | c0 | ssram
|  | clk
|  | c0 | flash_ssram_pipeline_bridge
|  | clk
|  | c0 | flash_ssram_tristate_bridge
|  | clk
|  | c0 | pipeline_bridge_before_tristate_bridge
|  | clk
|  | c0 | slow_peripheral_bridge
|  | clk_s1
|  | c2
|  | clk_m1
|  | c2 | button_pio
|  | clk
|  | c2 | high_res_timer
|  | clk
|  | c2 | jtag_uart
|  | clk
|  | c2 | led_pio
|  | clk
|  | c2 | performance_counter
|  | clk
|  | c2 | sys_clk_timer
|  | clk
|  | c2 | sysid
|  | clk
|  | c3 | remote_update
|  | global_signals_clock
|  | c0 | alt_vip_itc_0
|  | is_clk_rst
|  | c0 | alt_vip_vfr_0
|  | clock_reset
|  | c0 | alt_vip_cpr_0
|  | clock

## Parameters
c0 |
c1 |
c2 |
c3 |
c4 |
c5 |
c6 |
c7 |
c8 |
c9 |
deviceFamily | CYCLONEIII
e0 |
e1 |
e2 |
e3 |
inputClockFrequency | 50000000
inputClockRate | 50000000
lockedOutputPortOption | Export
pfdenaInputPortOption | Register
pllHdl |
resetInputPortOption | Register
generateLegacySim | false

## Software Assignments
ARESET | "None"
PFDENA | "None"
LOCKED | "None"
PLLENA | "None"
SCANCLK | "None"
SCANDATA | "None"
SCANREAD | "None"
SCANWRITE | "None"
SCANCLKENA | "None"
SCANACLR | "None"
SCANDATAOUT | "None"
SCANDONE | "None"
CONFIGUPDATE | "None"
PHASECOUNTERSELECT | "None"
PHASEDONE | "None"
PHASEUPDOWN | "None"
PHASESTEP | "None"

## cpu

altera_nios2 v9.1

pll | c0 | cpu
clk
|  | d_irq | button_pio
|  | irq
|  | d_irq | high_res_timer
|  | irq
|  | d_irq | jtag_uart
|  | irq
|  | d_irq | sys_clk_timer
|  | irq
|  | data_master | cpu_ddr_clock_bridge
|  | s1
|  | instruction_master
|  | s1
|  | data_master | flash_ssram_pipeline_bridge
|  | s1
|  | instruction_master
|  | s1
|  | data_master | slow_peripheral_bridge
|  | s1
|  | d_irq | alt_vip_vfr_0
|  | interrupt_sender
|  | data_master
|  | avalon_slave
|  | d_irq | alt_vip_itc_0
|  | status_update_irq
|  | data_master
|  | control

## Parameters
userDefinedSettings |
setting_showUnpublishedSettings | false
setting_showInternalSettings | false
setting_shadowRegisterSets | 0
setting_preciseSlaveAccessErrorException | false
setting_preciseIllegalMemAccessException | false
setting_preciseDivisionErrorException | false
setting_performanceCounter | false
setting_perfCounterWidth | _32
setting_interruptControllerType | Internal
setting_illegalMemAccessDetection | false
setting_illegalInstructionsTrap | false
setting_fullWaveformSignals | false
setting_extraExceptionInfo | false
setting_exportPCB | false
setting_debugSimGen | false
setting_clearXBitsLDNonBypass | true
setting_branchPredictionType | Automatic
setting_bit31BypassDCache | true
setting_bigEndian | false
setting_bhtPtrSz | _8
setting_bhtIndexPcOnly | false
setting_avalonDebugPortPresent | false
setting_alwaysEncrypt | true
setting_allowFullAddressRange | false
setting_activateTrace | true
setting_activateTestEndChecker | false
setting_activateMonitors | true
setting_activateModelChecker | false
setting_HDLSimCachesCleared | true
setting_HBreakTest | false
resetSlave | ext_flash.s1
resetOffset | 0
muldiv_multiplierType | EmbeddedMulFast
muldiv_divider | false
mpu_useLimit | false
mpu_numOfInstRegion | 8
mpu_numOfDataRegion | 8
mpu_minInstRegionSize | _12
mpu_minDataRegionSize | _12
mpu_enabled | false
mmu_uitlbNumEntries | _4
mmu_udtlbNumEntries | _6
mmu_tlbPtrSz | _7
mmu_tlbNumWays | _16
mmu_processIDNumBits | _8
mmu_enabled | false
mmu_autoAssignTlbPtrSz | true
mmu_TLBMissExcSlave |
mmu_TLBMissExcOffset | 0
manuallyAssignCpuID | false
impl | Fast
icache_size | _4096
icache_ramBlockType | Automatic
icache_numTCIM | _0
icache_burstType | None
exceptionSlave | ssram.s1
exceptionOffset | 32
debug_triggerArming | true
debug_level | Level1
debug_jtagInstanceID | 0
debug_embeddedPLL | true
debug_debugReqSignals | false
debug_assignJtagInstanceID | false
debug_OCIOnchipTrace | _128
dcache_size | _2048
dcache_ramBlockType | Automatic
dcache_omitDataMaster | false
dcache_numTCDM | _0
dcache_lineSize | _32
dcache_bursts | false
cpuReset | false
cpuID | 0
clockFrequency | 100000000
breakSlave | cpu.jtag_debug_module
breakOffset | 32
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
CPU_IMPLEMENTATION | "fast"
BIG_ENDIAN | 0
CPU_FREQ | 100000000u
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 4096
DCACHE_LINE_SIZE | 32
DCACHE_LINE_SIZE_LOG2 | 5
DCACHE_SIZE | 2048
INITDA_SUPPORTED |
FLUSHDA_SUPPORTED |
HAS_JMPI_INSTRUCTION |
EXCEPTION_ADDR | 0x5000020
RESET_ADDR | 0x4000000
BREAK_ADDR | 0x2000820
HAS_DEBUG_STUB |
HAS_DEBUG_CORE | 1
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x0
HARDWARE_DIVIDE_PRESENT | 0
HARDWARE_MULTIPLY_PRESENT | 1
HARDWARE_MULX_PRESENT | 0
INST_ADDR_WIDTH | 27
DATA_ADDR_WIDTH | 28
NUM_OF_SHADOW_REG_SETS | 0

## flash_ssram_pipeline_bridge

altera_avalon_pipeline_bridge v9.1

cpu | data_master | flash_ssram_pipeline_bridge
s1
instruction_master
s1
pll | c0
clk
|  | m1 | pipeline_bridge_before_tristate_bridge
|  | s1

## Parameters
burstEnable | false
dataWidth | 32
downstreamPipeline | true
enableArbiterlock | false
maxBurstSize | 2
maximumPendingReadTransactions | 10
slaveAddressWidth | 23
upstreamPipeline | true
waitrequestPipeline | true
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## pipeline_bridge_before_tristate_bridge

altera_avalon_pipeline_bridge v9.1

flash_ssram_pipeline_bridge | m1 | pipeline_bridge_before_tristate_bridge
s1
pll | c0
clk
|  | m1 | flash_ssram_tristate_bridge
|  | avalon_slave

## Parameters
burstEnable | false
dataWidth | 32
downstreamPipeline | true
enableArbiterlock | false
maxBurstSize | 2
maximumPendingReadTransactions | 7
slaveAddressWidth | 23
upstreamPipeline | true
waitrequestPipeline | true
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## flash_ssram_tristate_bridge

altera_avalon_tri_state_bridge v9.1

pipeline_bridge_before_tristate_bridge | m1 | flash_ssram_tristate_bridge
avalon_slave
pll | c0
clk
|  | tristate_master | ext_flash
|  | s1
|  | tristate_master | ssram
|  | s1

## Parameters
registerIncomingSignals | true
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## ssram

altera_avalon_cy7c1380_ssram v9.1

flash_ssram_tristate_bridge | tristate_master | ssram
s1
pll | c0
clk

## Parameters
readLatency | 2
sharedPorts | s1/address,s1/data
simMakeModel | true
size | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
SRAM_MEMORY_SIZE | 1
SRAM_MEMORY_UNITS | 1048576
SSRAM_DATA_WIDTH | 32
SSRAM_READ_LATENCY | 2

## ext_flash

altera_avalon_cfi_flash v9.1

flash_ssram_tristate_bridge | tristate_master | ext_flash
s1
pll | c0
clk

## Parameters
actualHoldTime | 20.0
actualSetupTime | 30.0
actualWaitTime | 100.0
addressWidth | 23
clockRate | 100000000
corePreset | INTEL128P30
dataWidth | 16
holdTime | 20
setupTime | 25
sharedPorts | s1/address,s1/data
timingUnits | NS
waitTime | 100
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
SETUP_VALUE | 25
WAIT_VALUE | 100
HOLD_VALUE | 20
TIMING_UNITS | "ns"
SIZE | 16777216u

## ddr_sdram

altmemddr v9.1

clk | clk | ddr_sdram
refclk
cpu_ddr_clock_bridge | m1
s1
alt_vip_vfr_0 | avalon_master
s1
|  | sysclk | cpu_ddr_clock_bridge
|  | clk_m1
|  | sysclk | alt_vip_vfr_0
|  | clock_master

## Parameters
pipeline_commands | false
debug_en | false
export_debug_port | false
use_generated_memory_model | true
dedicated_memory_clk_phase_label | Dedicated memory clock phase:
mem_if_clk_mhz | 133.0
quartus_project_exists | false
local_if_drate | Half
enable_v72_rsu | false
local_if_clk_mhz_label | 66,5
new_variant | true
mem_if_memtype | DDR SDRAM
pll_ref_clk_mhz | 50.0
mem_if_clk_ps_label | (7519 ps)
family | Cyclone III
project_family | Cyclone III
speed_grade | 8
dedicated_memory_clk_phase | 0
pll_ref_clk_ps_label | (20000 ps)
avalon_burst_length | 1
mem_if_clk_pair_count | 1
mem_if_cs_per_dimm | 1
pre_latency_label | Fix read latency at:
dedicated_memory_clk_en | false
mirror_addressing | 0
mem_if_bankaddr_width | 2
register_control_word_9 | 0000
mem_if_rowaddr_width | 13
mem_dyn_deskew_en | false
post_latency_label | cycles (0 cycles=minimum latency, non-deterministic)
mem_if_dm_pins_en | Yes
local_if_dwidth_label | 64
register_control_word_7 | 0000
register_control_word_8 | 0000
mem_if_preset | PSC A2S56D40CTP-G5
mem_if_pchaddr_bit | 10
WIDTH_RATIO | 4
vendor | Other
register_control_word_3 | 0000
register_control_word_4 | 0000
chip_or_dimm | Discrete Device
register_control_word_5 | 0000
register_control_word_6 | 0000
mem_fmax | 200.0
register_control_word_0 | 0000
register_control_word_size | 4
register_control_word_1 | 0000
register_control_word_2 | 0000
register_control_word_11 | 0000
register_control_word_10 | 0000
mem_if_cs_width | 1
mem_if_preset_rlat | 0
mem_if_cs_per_rank | 1
fast_simulation_en | FAST
register_control_word_15 | 0000
register_control_word_14 | 0000
mem_if_dwidth | 16
mem_if_dq_per_dqs | 8
mem_if_coladdr_width | 9
register_control_word_13 | 0000
register_control_word_12 | 0000
mem_tiha_ps | 600
mem_tdsh_ck | 0.2
mem_if_trfc_ns | 70.0
mem_tqh_ck | 0.36
mem_tisa_ps | 600
mem_tdss_ck | 0.2
mem_trtp_ns | 0.0
mem_if_tinit_us | 200.0
mem_if_trcd_ns | 15.0
mem_if_twtr_ck | 2
mem_trrd_ns | 0.0
mem_tdqss_ck | 0.28
mem_tqhs_ps | 500
mem_tdsa_ps | 400
mem_tac_ps | 700
mem_tdha_ps | 400
mem_if_tras_ns | 40.0
mem_if_twr_ns | 15.0
mem_tdqsck_ps | 550
mem_if_trp_ns | 15.0
mem_tdqsq_ps | 400
mem_if_tmrd_ns | 10.0
mem_tfaw_ns | 0.0
mem_if_trefi_us | 7.0
mem_tcl_40_fmax | 533.0
mem_odt | Disabled
mp_WLH_percent | 0.6
mem_drv_str | Normal
mp_DH_percent | 0.5
input_period | 0
mp_QH_percent | 0.5
mp_QHS_percent | 0.5
mem_tcl_30_fmax | 200.0
ac_clk_select | 90
mp_DQSQ_percent | 0.65
mp_DS_percent | 0.6
pll_reconfig_ports_en | false
mem_btype | Sequential
mp_IS_percent | 0.7
mem_tcl | 3.0
mp_DQSS_percent | 0.5
export_bank_info | false
mp_DSS_percent | 0.6
mem_dll_en | Yes
ac_phase | 90
mem_if_oct_en | false
mem_tcl_60_fmax | 533.0
mp_DSH_percent | 0.6
mem_if_dqsn_en | false
enable_mp_calibration | true
mp_IH_percent | 0.6
mem_tcl_15_fmax | 533.0
dll_external | false
mem_bl | 4
mp_WLS_percent | 0.7
mem_tcl_50_fmax | 533.0
mp_DQSCK_percent | 0.5
mem_tcl_25_fmax | 200.0
mem_tcl_20_fmax | 133.333
mem_addr_mapping | CHIP_ROW_BANK_COL
ctl_ecc_en | false
user_refresh_en | false
ctl_hrb_en | false
clk_source_sharing_en | false
ctl_lookahead_depth | 4
ref_clk_source | clk
ctl_autopch_en | false
multicast_wr_en | false
ctl_powerdn_en | false
auto_powerdn_cycles | 0
csr_en | false
local_if_type_avalon | true
auto_powerdn_en | false
ctl_auto_correct_en | false
ctl_self_refresh_en | false
phy_if_type_afi | true
shared_sys_clk_source |
controller_type | hp_ctl
max_local_size | 4
tool_context | SOPC_BUILDER
mem_srtr | Normal
mem_mpr_loc | Predefined Pattern
dss_tinit_rst_us | 200.0
mem_tcl_90_fmax | 400.0
mem_rtt_wr | Dynamic ODT off
mem_tcl_100_fmax | 400.0
mem_pasr | Full Array
mem_asrm | Manual SR Reference (SRT)
mem_mpr_oper | Predefined Pattern
mem_tcl_80_fmax | 400.0
mem_drv_impedance | RZQ/7
mem_rtt_nom | ODT Disabled
mem_tcl_70_fmax | 400.0
mem_wtcl | 5.0
mem_dll_pch | Fast Exit
mem_atcl | Disabled
board_settings_valid | true
t_IH | 0.6
board_intra_DQS_group_skew | 0.02
isi_DQS | 0.0
addr_cmd_slew_rate | 1.0
board_tpd_inter_DIMM | 0.05
board_addresscmd_CK_skew | 0.0
t_DS_calculated | 0,400
isi_addresscmd_hold | 0.0
t_IS | 0.6
restore_default_toggle | false
dqs_dqsn_slew_rate | 2.0
dq_slew_rate | 1.0
board_inter_DQS_group_skew | 0.02
isi_addresscmd_setup | 0.0
board_minCK_DQS_skew | -0.01
t_IS_calculated | 0,600
num_slots_or_devices | 1
board_maxCK_DQS_skew | 0.01
board_skew_ps | 20
t_DH | 0.4
ck_ckn_slew_rate | 2.0
isi_DQ | 0.0
t_IH_calculated | 0,600
t_DH_calculated | 0,400
t_DS | 0.4
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## cpu_ddr_clock_bridge

altera_avalon_clock_crossing v9.1

cpu | data_master | cpu_ddr_clock_bridge
s1
instruction_master
s1
ddr_sdram | sysclk
clk_m1
pll | c0
clk_s1
|  | m1 | ddr_sdram
|  | s1

## Parameters
dataWidth | 32
downstreamFIFODepth | 8
downstreamUseRegister | false
masterSyncDepth | 3
maxBurstSize | 8
slaveAddressWidth | 23
slaveSyncDepth | 3
upstreamFIFODepth | 64
upstreamUseRegister | false
useBurstCount | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## slow_peripheral_bridge

altera_avalon_clock_crossing v9.1

cpu | data_master | slow_peripheral_bridge
s1
pll | c0
clk_s1
c2
clk_m1
|  | m1 | button_pio
|  | s1
|  | m1 | high_res_timer
|  | s1
|  | m1 | jtag_uart
|  | avalon_jtag_slave
|  | m1 | led_pio
|  | s1
|  | m1 | performance_counter
|  | control_slave
|  | m1 | pll
|  | s1
|  | m1 | remote_update
|  | s1
|  | m1 | sys_clk_timer
|  | s1
|  | m1 | sysid
|  | control_slave

## Parameters
dataWidth | 32
downstreamFIFODepth | 16
downstreamUseRegister | false
masterSyncDepth | 3
maxBurstSize | 8
slaveAddressWidth | 7
slaveSyncDepth | 3
upstreamFIFODepth | 64
upstreamUseRegister | false
useBurstCount | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## sys_clk_timer

altera_avalon_timer v9.1

cpu | d_irq | sys_clk_timer
irq
pll | c2
clk
slow_peripheral_bridge | m1
s1

## Parameters
alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 10.0
periodUnits | MSEC
resetOutput | false
snapshot | true
systemFrequency | 60000000
timeoutPulseOutput | false
timerPreset | FULL_FEATURED
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
ALWAYS_RUN | 0
FIXED_PERIOD | 0
SNAPSHOT | 1
PERIOD | 10.0
PERIOD_UNITS | "ms"
RESET_OUTPUT | 0
TIMEOUT_PULSE_OUTPUT | 0
FREQ | 60000000u
LOAD_VALUE | 599999ULL
COUNTER_SIZE | 32
MULT | 0.0010
TICKS_PER_SEC | 100u

## high_res_timer

altera_avalon_timer v9.1

cpu | d_irq | high_res_timer
irq
pll | c2
clk
slow_peripheral_bridge | m1
s1

## Parameters
alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 10.0
periodUnits | USEC
resetOutput | false
snapshot | true
systemFrequency | 60000000
timeoutPulseOutput | false
timerPreset | FULL_FEATURED
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
ALWAYS_RUN | 0
FIXED_PERIOD | 0
SNAPSHOT | 1
PERIOD | 10.0
PERIOD_UNITS | "us"
RESET_OUTPUT | 0
TIMEOUT_PULSE_OUTPUT | 0
FREQ | 60000000u
LOAD_VALUE | 599ULL
COUNTER_SIZE | 32
MULT | 1.0E-6
TICKS_PER_SEC | 100000u

## sysid

altera_avalon_sysid v9.1

pll | c2 | sysid
clk
slow_peripheral_bridge | m1
control_slave

## Parameters
id | 895408991
timestamp | 1274130913
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
ID | 895408991u
TIMESTAMP | 1274130913u

## performance_counter

altera_avalon_performance_counter v9.1

pll | c2 | performance_counter
clk
slow_peripheral_bridge | m1
control_slave

## Parameters
numberOfSections | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
HOW_MANY_SECTIONS | 1

## jtag_uart

altera_avalon_jtag_uart v9.1

cpu | d_irq | jtag_uart
irq
pll | c2
clk
slow_peripheral_bridge | m1
avalon_jtag_slave

## Parameters
allowMultipleConnections | false
hubInstanceID | 0
readBufferDepth | 8
readIRQThreshold | 4
simInputCharacterStream |
simInteractiveOptions | INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer | true
useRegistersForWriteBuffer | true
useRelativePathForSimFile | false
writeBufferDepth | 8
writeIRQThreshold | 4
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
WRITE_DEPTH | 8
READ_DEPTH | 8
WRITE_THRESHOLD | 4
READ_THRESHOLD | 4

## button_pio

altera_avalon_pio v9.1

cpu | d_irq | button_pio
irq
pll | c2
clk
slow_peripheral_bridge | m1
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | true
clockRate | 60000000
direction | Input
edgeType | RISING
generateIRQ | true
irqType | EDGE
resetValue | 0
simDoTestBenchWiring | true
simDrivenValue | 15
width | 4
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 1
DRIVEN_SIM_VALUE | 0xf
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 1
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 4
RESET_VALUE | 0x0
EDGE_TYPE | "RISING"
IRQ_TYPE | "EDGE"
FREQ | 60000000u

## led_pio

altera_avalon_pio v9.1

pll | c2 | led_pio
clk
slow_peripheral_bridge | m1
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 60000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 2
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 2
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 60000000u

## remote_update

altera_avalon_remote_update_cycloneiii v9.1

pll | c3 | remote_update
global_signals_clock
slow_peripheral_bridge | m1
s1

## Parameters
AUTO_GLOBAL_SIGNALS_CLOCK_CLOCK_RATE | 40000000
AUTO_DEVICE_FAMILY | Cyclone III
deviceFamily | Cyclone III
generateLegacySim | false

## Software Assignments (none)

## alt_vip_vfr_0

alt_vip_vfr v9.1

cpu | d_irq | alt_vip_vfr_0
interrupt_sender
data_master
avalon_slave
pll | c0
clock_reset
ddr_sdram | sysclk
clock_master
|  | avalon_master | ddr_sdram
|  | s1
|  | avalon_streaming_source | alt_vip_cpr_0
|  | din0

## Parameters
BITS_PER_PIXEL_PER_COLOR_PLANE | 8
NUMBER_OF_CHANNELS_IN_PARALLEL | 3
NUMBER_OF_CHANNELS_IN_SEQUENCE | 1
MAX_IMAGE_WIDTH | 800
MAX_IMAGE_HEIGHT | 480
MEM_PORT_WIDTH | 32
RMASTER_FIFO_DEPTH | 64
RMASTER_BURST_TARGET | 32
CLOCKS_ARE_SEPARATE | 1
AUTO_CLOCK_RESET_CLOCK_RATE | 100000000
AUTO_CLOCK_MASTER_CLOCK_RATE | 66500000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## alt_vip_itc_0

alt_vip_itc v9.1

pll | c0 | alt_vip_itc_0
is_clk_rst
alt_vip_cpr_0 | dout0
din
cpu | d_irq
status_update_irq
data_master
control

## Parameters
USE_EMBEDDED_SYNCS | 0
H_BACK_PORCH | 216
F_FALLING_EDGE | 0
H_SYNC_LENGTH | 1
V_ACTIVE_LINES | 480
CLOCKS_ARE_SAME | 0
FIELD0_V_SYNC_LENGTH | 0
BPS | 8
GENERATE_SYNC | 0
STD_WIDTH | 1
AP_LINE | 0
FIELD0_V_BLANK | 0
V_SYNC_LENGTH | 1
INTERLACED | 0
V_BLANK | 0
USE_CONTROL | 1
NUMBER_OF_COLOUR_PLANES | 3
V_FRONT_PORCH | 10
THRESHOLD | 700
H_FRONT_PORCH | 40
FIELD0_V_RISING_EDGE | 0
FIELD0_V_FRONT_PORCH | 0
NO_OF_MODES | 1
FIELD0_V_BACK_PORCH | 0
H_ACTIVE_PIXELS | 800
ACCEPT_COLOURS_IN_SEQ | 0
H_BLANK | 0
COLOUR_PLANES_ARE_IN_PARALLEL | 0
F_RISING_EDGE | 0
V_BACK_PORCH | 35
FIFO_DEPTH | 800
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## alt_vip_cpr_0

alt_vip_cpr v9.1

alt_vip_vfr_0 | avalon_streaming_source | alt_vip_cpr_0
din0
pll | c0
clock
|  | dout0 | alt_vip_itc_0
|  | din

## Parameters
DIN1_ENABLED | 0
DOUT1_SYMBOLS_PER_BEAT | 0
DOUT0_SYMBOLS_PER_BEAT | 1
DOUT1_ENABLED | 0
PARAMETERISATION |
DIN0_SYMBOLS_PER_BEAT | 3
DIN1_SYMBOLS_PER_BEAT | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

generation took 0,00 seconds | rendering took 7,34 seconds