# Reading C:/intelFPGA/18.0/modelsim_ase/tcl/vsim/pref.tcl
cd C:/Users/anandr1x/Desktop/lvdstxQ18lite/lvdsTX_sim/mentor
do msim_setup.tcl
# lvdsTX
# ./../
# C:/intelfpga_lite/18.0/quartus/
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work ./libraries/work/ 
# Copying C:/intelFPGA/18.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work_lib ./libraries/work/ 
# Modifying modelsim.ini
# [exec] file_copy
# List Of Command Line Aliases
# 
# file_copy                                         -- Copy ROM/RAM files to simulation directory
# 
# dev_com                                           -- Compile device library files
# 
# com                                               -- Compile the design files in correct order
# 
# elab                                              -- Elaborate top level design
# 
# elab_debug                                        -- Elaborate the top level design with novopt option
# 
# ld                                                -- Compile all the design files and elaborate the top level design
# 
# ld_debug                                          -- Compile all the design files and elaborate the top level design with -novopt
# 
# 
# 
# List Of Variables
# 
# TOP_LEVEL_NAME                                    -- Top level module name.
#                                                      For most designs, this should be overridden
#                                                      to enable the elab/elab_debug aliases.
# 
# SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
# 
# QSYS_SIMDIR                                       -- Platform Designer base simulation directory.
# 
# QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
# 
# USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
# 
# USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.
com
# [exec] com
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 09:21:20 on Sep 27,2018
# vlog -reportprogress 300 ./../lvdsTX.v 
# -- Compiling module lvdsTX_ddio_out_vpd
# -- Compiling module lvdsTX_cmpr_hqb
# -- Compiling module lvdsTX_cntr_7jd
# -- Compiling module lvdsTX_shift_reg_c6e
# -- Compiling module lvdsTX_shift_reg_a6e
# -- Compiling module lvdsTX
# 
# Top level modules:
# 	lvdsTX
# End time: 09:21:20 on Sep 27,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
elab
# [exec] elab
# vsim -t ps -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver lvdsTX 
# Start time: 09:21:25 on Sep 27,2018
# Loading work.lvdsTX
# Loading work.lvdsTX_ddio_out_vpd
# Loading fiftyfivenm_ver.fiftyfivenm_ddio_out
# Loading altera_ver.dffeas
# Loading fiftyfivenm_ver.fiftyfivenm_routing_wire
# Loading fiftyfivenm_ver.fiftyfivenm_mux21
# Loading work.lvdsTX_cmpr_hqb
# Loading work.lvdsTX_cntr_7jd
# Loading fiftyfivenm_ver.fiftyfivenm_lcell_comb
# Loading work.lvdsTX_shift_reg_c6e
# Loading work.lvdsTX_shift_reg_a6e
# Loading fiftyfivenm_ver.fiftyfivenm_pll
# Loading fiftyfivenm_ver.fiftyfivenm_m_cntr
# Loading fiftyfivenm_ver.fiftyfivenm_n_cntr
# Loading fiftyfivenm_ver.fiftyfivenm_scale_cntr
# ** Warning: (vsim-3017) ./../lvdsTX.v(55): [TFMPC] - Too few port connections. Expected 15, found 14.
#    Time: 0 ps  Iteration: 0  Instance: /lvdsTX/ddio_out/ddio_outa_0 File: /build/swbuild/SJ/nightly/18.0std/614/l64/work/modelsim/eda/sim_lib/fiftyfivenm_atoms.v
# ** Warning: (vsim-3722) ./../lvdsTX.v(55): [TFMPC] - Missing connection for port 'phymemclock'.
# Loading altera_ver.PRIM_GDFF_LOW
# ** Warning: (vsim-3017) ./../lvdsTX.v(55): [TFMPC] - Too few port connections. Expected 15, found 14.
#    Time: 0 ps  Iteration: 0  Instance: /lvdsTX/outclock_ddio/ddio_outa_0 File: /build/swbuild/SJ/nightly/18.0std/614/l64/work/modelsim/eda/sim_lib/fiftyfivenm_atoms.v
# ** Warning: (vsim-3722) ./../lvdsTX.v(55): [TFMPC] - Missing connection for port 'phymemclock'.