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## Legal Notice: Copyright (C) 1991-2008 Altera Corporation
## Any megafunction design, and related net list (encrypted or decrypted),
## support information, device programming or simulation file, and any other
## associated documentation or information provided by Altera or a partner
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# Testbench simulation files
catch {set testbench_files [glob fft*.hex]} error_msg
puts $error_msg
catch {set input_files [glob fft*input.txt]} error_msg
puts $error_msg
     
# The top-level in HDL type "Verilog"
set ipfs_ext vo
set hdl_ext v
if {[file exists fft.$ipfs_ext]} {
        puts "Info: Found fft.$ipfs_ext."
} else {
	puts "Warning: Could not find fft.$ipfs_ext!"
}

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT Verilog -section_id eda_simulation

# Set test bench name
set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation


# test bench settings
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME fft_inst -section_id tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME work.fft_tb -section_id tb

# IPFS file
set_global_assignment -name EDA_IPFS_FILE fft.$ipfs_ext -section_id eda_simulation -library work

# Add Testbench files
foreach i $testbench_files {
  set_global_assignment -name EDA_TEST_BENCH_FILE $i -section_id tb -library work
}
foreach i $input_files {
  set_global_assignment -name EDA_TEST_BENCH_FILE $i -section_id tb -library work
}
set_global_assignment -name EDA_TEST_BENCH_FILE fft_tb.$hdl_ext -section_id tb -library work

# Specify testbench mode for nativelink
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation

# Specify active testbench for nativelink
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation




