couldn't open "transcript": permission denied # // Questa Intel Starter FPGA Edition-64 # // Version 2022.1 win64 Jan 29 2022 # // # // Copyright 1991-2022 Mentor Graphics Corporation # // All Rights Reserved. # // # // QuestaSim and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // cd c:/quartus_projects/test_fft_speed/fft2_tb dir # Volume in drive C has no label. # Volume Serial Number is 3EBD-04D2 # # Directory of c:\quartus_projects\test_fft_speed\fft2_tb # # 20/04/2023 16:46 . # 20/04/2023 16:46 .. # 20/04/2023 16:45 343 fft2.ipx # 20/04/2023 16:46 34,811 fft2_generation.rpt # 20/04/2023 16:45 424 fft2_generation.rpt.1 # 20/04/2023 16:46 fft2_tb # 20/04/2023 16:45 124,668 fft2_tb.qsys # 20/04/2023 16:45 86,463 fft2_tb.qsys.legacy # 20/04/2023 16:45 ip # 5 File(s) 246,709 bytes # 4 Dir(s) 71,702,540,288 bytes free dir # Volume in drive C has no label. # Volume Serial Number is 3EBD-04D2 # # Directory of c:\quartus_projects\test_fft_speed\fft2_tb # # 20/04/2023 16:46 . # 20/04/2023 16:46 .. # 20/04/2023 16:45 343 fft2.ipx # 20/04/2023 16:46 34,811 fft2_generation.rpt # 20/04/2023 16:45 424 fft2_generation.rpt.1 # 20/04/2023 16:46 fft2_tb # 20/04/2023 16:45 124,668 fft2_tb.qsys # 20/04/2023 16:45 86,463 fft2_tb.qsys.legacy # 20/04/2023 16:45 ip # 5 File(s) 246,709 bytes # 4 Dir(s) 71,702,540,288 bytes free cd C:/quartus_projects/test_fft_speed/fft2_tb/fft2_tb/sim/mentor do msim_setup.tcl # fft2_tb.fft2_tb # ./../ # C:/intelfpga_pro/22.4/quartus/ # false # false # bit_64 # -t fs # work work_lib altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip # Questa Intel Starter FPGA Edition-64 vmap 2022.1 Lib Mapping Utility 2022.01 Jan 29 2022 # vmap work ./libraries/work/ # Copying C:/intelFPGA_pro/22.4/questa_fse/win64/../modelsim.ini to modelsim.ini # Modifying modelsim.ini # Questa Intel Starter FPGA Edition-64 vmap 2022.1 Lib Mapping Utility 2022.01 Jan 29 2022 # vmap work_lib ./libraries/work/ # Modifying modelsim.ini # altera_common_sv_packages 1 altera_avalon_st_sink_bfm_2000 1 fft2_inst_source_bfm_ip 1 intel_FPGA_unified_fft_104 1 fft2 1 altera_avalon_clock_source_191 1 fft2_inst_clk_bfm_ip 1 altera_avalon_st_source_bfm_2000 1 fft2_inst_sink_bfm_ip 1 altera_avalon_reset_source_191 1 fft2_inst_rst_bfm_ip 1 fft2_tb 1 # altera_common_sv_packages altera_avalon_st_sink_bfm_2000 fft2_inst_source_bfm_ip intel_FPGA_unified_fft_104 fft2 altera_avalon_clock_source_191 fft2_inst_clk_bfm_ip altera_avalon_st_source_bfm_2000 fft2_inst_sink_bfm_ip altera_avalon_reset_source_191 fft2_inst_rst_bfm_ip fft2_tb # [exec] file_copy # List Of Command Line Aliases # # file_copy -- Copy ROM/RAM files to simulation directory # # dev_com -- Compile device library files # # com -- Compile the design files in correct order # # elab -- Elaborate top level design # # elab_debug -- Elaborate the top level design with -voptargs=+acc option # # ld -- Compile all the design files and elaborate the top level design # # ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc # # # # List Of Variables # # TOP_LEVEL_NAME -- Top level module name. # For most designs, this should be overridden # to enable the elab/elab_debug aliases. # # SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module. # # QSYS_SIMDIR -- Qsys base simulation directory. # # QUARTUS_INSTALL_DIR -- Quartus installation directory. # # USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases. # # USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases. # # USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases. # # USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases. # # SILENCE -- Set to true to suppress all informational and/or warning messages in the generated simulation script. # # FORCE_MODELSIM_AE_SELECTION -- Set to true to force to select Modelsim AE always. set TOP_LEVEL_NAME "fft2_tb.fft2_tb" # fft2_tb.fft2_tb com # [exec] com # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:30 on Apr 20,2023 # vlog -reportprogress 300 -sv ../../../ip/fft2_tb/fft2_inst_rst_bfm_ip/altera_avalon_reset_source_191/sim/verbosity_pkg.sv -work altera_common_sv_packages # -- Compiling package verbosity_pkg # # Top level modules: # --none-- # End time: 16:48:30 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:30 on Apr 20,2023 # vlog -reportprogress 300 -sv ../../../ip/fft2_tb/fft2_inst_sink_bfm_ip/altera_avalon_st_source_bfm_2000/sim/avalon_utilities_pkg.sv -work altera_common_sv_packages # -- Compiling package avalon_utilities_pkg # # Top level modules: # --none-- # End time: 16:48:30 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:31 on Apr 20,2023 # vlog -reportprogress 300 -sv ../../../ip/fft2_tb/fft2_inst_source_bfm_ip/altera_avalon_st_sink_bfm_2000/sim/altera_avalon_st_sink_bfm.sv -L altera_common_sv_packages -work altera_avalon_st_sink_bfm_2000 # -- Compiling module altera_avalon_st_sink_bfm # -- Importing package altera_common_sv_packages.verbosity_pkg # # Top level modules: # altera_avalon_st_sink_bfm # End time: 16:48:31 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:31 on Apr 20,2023 # vlog -reportprogress 300 ../../../ip/fft2_tb/fft2_inst_source_bfm_ip/sim/fft2_inst_source_bfm_ip.v -work fft2_inst_source_bfm_ip # -- Compiling module fft2_inst_source_bfm_ip # # Top level modules: # fft2_inst_source_bfm_ip # End time: 16:48:31 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:31 on Apr 20,2023 # vlog -reportprogress 300 -sv ../../../../fft2/intel_FPGA_unified_fft_104/sim/dspba_library_ver.sv -work intel_FPGA_unified_fft_104 # -- Compiling module dspba_delay_ver # -- Compiling module dspba_sync_reg_ver # -- Compiling module dspba_pipe # -- Compiling module dspba_dcfifo_mixed_widths # # Top level modules: # dspba_delay_ver # dspba_sync_reg_ver # dspba_pipe # dspba_dcfifo_mixed_widths # End time: 16:48:31 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vcom 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:31 on Apr 20,2023 # vcom -reportprogress 300 ../../../../fft2/intel_FPGA_unified_fft_104/sim/dspba_sim_library_package.vhd -work intel_FPGA_unified_fft_104 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Compiling package dspba_sim_library_package # -- Compiling package body dspba_sim_library_package # -- Loading package dspba_sim_library_package # End time: 16:48:31 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vcom 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:31 on Apr 20,2023 # vcom -reportprogress 300 ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y_atb.vhd -work intel_FPGA_unified_fft_104 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Loading package MATH_REAL # -- Loading package dspba_sim_library_package # -- Compiling entity fft2_intel_FPGA_unified_fft_104_3ngyi6y_atb # -- Compiling architecture normal of fft2_intel_FPGA_unified_fft_104_3ngyi6y_atb # End time: 16:48:31 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vcom 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:31 on Apr 20,2023 # vcom -reportprogress 300 ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y_stm.vhd -work intel_FPGA_unified_fft_104 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity fft2_intel_FPGA_unified_fft_104_3ngyi6y_stm # -- Compiling architecture normal of fft2_intel_FPGA_unified_fft_104_3ngyi6y_stm # End time: 16:48:31 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:31 on Apr 20,2023 # vlog -reportprogress 300 -sv ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv -work intel_FPGA_unified_fft_104 # -- Compiling module fft2_intel_FPGA_unified_fft_104_3ngyi6y # # Top level modules: # fft2_intel_FPGA_unified_fft_104_3ngyi6y # End time: 16:48:31 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:31 on Apr 20,2023 # vlog -reportprogress 300 ../../../../fft2/sim/fft2.v -work fft2 # -- Compiling module fft2 # # Top level modules: # fft2 # End time: 16:48:31 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:31 on Apr 20,2023 # vlog -reportprogress 300 -sv ../../../ip/fft2_tb/fft2_inst_clk_bfm_ip/altera_avalon_clock_source_191/sim/altera_avalon_clock_source.sv -L altera_common_sv_packages -work altera_avalon_clock_source_191 # -- Compiling module altera_avalon_clock_source # -- Importing package altera_common_sv_packages.verbosity_pkg # # Top level modules: # altera_avalon_clock_source # End time: 16:48:31 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:32 on Apr 20,2023 # vlog -reportprogress 300 ../../../ip/fft2_tb/fft2_inst_clk_bfm_ip/sim/fft2_inst_clk_bfm_ip.v -work fft2_inst_clk_bfm_ip # -- Compiling module fft2_inst_clk_bfm_ip # # Top level modules: # fft2_inst_clk_bfm_ip # End time: 16:48:32 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:32 on Apr 20,2023 # vlog -reportprogress 300 -sv ../../../ip/fft2_tb/fft2_inst_sink_bfm_ip/altera_avalon_st_source_bfm_2000/sim/altera_avalon_st_source_bfm.sv -L altera_common_sv_packages -work altera_avalon_st_source_bfm_2000 # -- Compiling module altera_avalon_st_source_bfm # -- Importing package altera_common_sv_packages.verbosity_pkg # -- Importing package altera_common_sv_packages.avalon_utilities_pkg # # Top level modules: # altera_avalon_st_source_bfm # End time: 16:48:32 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:32 on Apr 20,2023 # vlog -reportprogress 300 ../../../ip/fft2_tb/fft2_inst_sink_bfm_ip/sim/fft2_inst_sink_bfm_ip.v -work fft2_inst_sink_bfm_ip # -- Compiling module fft2_inst_sink_bfm_ip # # Top level modules: # fft2_inst_sink_bfm_ip # End time: 16:48:32 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:32 on Apr 20,2023 # vlog -reportprogress 300 -sv ../../../ip/fft2_tb/fft2_inst_rst_bfm_ip/altera_avalon_reset_source_191/sim/altera_avalon_reset_source.sv -L altera_common_sv_packages -work altera_avalon_reset_source_191 # -- Compiling module altera_avalon_reset_source # -- Importing package altera_common_sv_packages.verbosity_pkg # # Top level modules: # altera_avalon_reset_source # End time: 16:48:32 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:32 on Apr 20,2023 # vlog -reportprogress 300 ../../../ip/fft2_tb/fft2_inst_rst_bfm_ip/sim/fft2_inst_rst_bfm_ip.v -work fft2_inst_rst_bfm_ip # -- Compiling module fft2_inst_rst_bfm_ip # # Top level modules: # fft2_inst_rst_bfm_ip # End time: 16:48:32 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Questa Intel Starter FPGA Edition-64 vlog 2022.1 Compiler 2022.01 Jan 29 2022 # Start time: 16:48:32 on Apr 20,2023 # vlog -reportprogress 300 ../fft2_tb.v -work fft2_tb # -- Compiling module fft2_tb # # Top level modules: # fft2_tb # End time: 16:48:32 on Apr 20,2023, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 elab # [exec] elab # vsim -t fs -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L twentynm_ver -L twentynm_hssi_ver -L twentynm_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L twentynm -L twentynm_hssi -L twentynm_hip -L altera_common_sv_packages -L altera_avalon_st_sink_bfm_2000 -L fft2_inst_source_bfm_ip -L intel_FPGA_unified_fft_104 -L fft2 -L altera_avalon_clock_source_191 -L fft2_inst_clk_bfm_ip -L altera_avalon_st_source_bfm_2000 -L fft2_inst_sink_bfm_ip -L altera_avalon_reset_source_191 -L fft2_inst_rst_bfm_ip -L fft2_tb fft2_tb.fft2_tb # Start time: 16:48:48 on Apr 20,2023 # ** Note: (vsim-3812) Design is being optimized... # Loading work.fft2_tb(fast) # Loading sv_std.std # Loading intel_FPGA_unified_fft_104.fft2_intel_FPGA_unified_fft_104_3ngyi6y(fast) # Loading altera_lnsim_ver.altera_syncram(fast) # Loading altera_lnsim_ver.altera_syncram(fast__1) # Loading altera_lnsim_ver.altera_syncram(fast__2) # Loading twentynm_ver.twentynm_mac(fast) # Loading altera_lnsim_ver.altera_syncram(fast__3) # Loading altera_lnsim_ver.altera_syncram(fast__4) # Loading twentynm_ver.twentynm_mac(fast__1) # Loading altera_lnsim_ver.altera_syncram(fast__5) # Loading altera_lnsim_ver.altera_syncram(fast__6) # Loading altera_lnsim_ver.altera_syncram(fast__7) # Loading altera_lnsim_ver.altera_syncram(fast__8) # Loading twentynm_ver.twentynm_mac(fast__2) # Loading altera_lnsim_ver.altera_syncram(fast__9) # Loading altera_lnsim_ver.altera_syncram(fast__10) # Loading twentynm_ver.twentynm_mac(fast__3) # Loading altera_lnsim_ver.altera_syncram(fast__11) # Loading twentynm_ver.twentynm_mac(fast__4) # Loading altera_lnsim_ver.altera_syncram(fast__12) # Loading altera_common_sv_packages.verbosity_pkg(fast) # Loading altera_avalon_clock_source_191.altera_avalon_clock_source(fast) # Loading altera_avalon_reset_source_191.altera_avalon_reset_source(fast) # Loading altera_common_sv_packages.avalon_utilities_pkg(fast) # Loading altera_avalon_st_source_bfm_2000.altera_avalon_st_source_bfm(fast) # Loading altera_avalon_st_sink_bfm_2000.altera_avalon_st_sink_bfm(fast) # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clocken0'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/redist15_fft_fftLight_FFTPipe_FFT4Block_0_fft2Block_BFUBlock_BFUImpl_FBmux_imag_x_q_2048_mem_dmem File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 2744 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clocken0'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/redist14_fft_fftLight_FFTPipe_FFT4Block_0_fft2Block_BFUBlock_BFUImpl_FBmux_real_x_q_2048_mem_dmem File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 2988 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clocken0'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/redist34_fft_fftLight_FFTPipe_FFT4Block_0_BFUBlock_BFUImpl_FBmux_real_x_q_1024_mem_dmem File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 3225 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clocken0'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/redist35_fft_fftLight_FFTPipe_FFT4Block_0_BFUBlock_BFUImpl_FBmux_imag_x_q_1024_mem_dmem File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 3550 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_0_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_0_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_0_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 3636 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_0_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_0_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_0_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 3636 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_0_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_0_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_0_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 3636 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clocken0'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/redist12_fft_fftLight_FFTPipe_FFT4Block_1_fft2Block_BFUBlock_BFUImpl_FBmux_real_x_q_512_mem_dmem File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 3822 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_0_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_0_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_0_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 3957 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_0_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_0_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_0_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 3957 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_0_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_0_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_0_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 3957 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clocken0'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/redist13_fft_fftLight_FFTPipe_FFT4Block_1_fft2Block_BFUBlock_BFUImpl_FBmux_imag_x_q_512_mem_dmem File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 4143 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clocken0'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/redist31_fft_fftLight_FFTPipe_FFT4Block_1_BFUBlock_BFUImpl_FBmux_imag_x_q_256_mem_dmem File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 4393 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clocken0'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/redist30_fft_fftLight_FFTPipe_FFT4Block_1_BFUBlock_BFUImpl_FBmux_real_x_q_256_mem_dmem File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 4661 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_1_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_1_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_1_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 4746 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_1_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_1_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_1_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 4746 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_1_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_1_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_1_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 4746 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clocken0'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/redist11_fft_fftLight_FFTPipe_FFT4Block_2_fft2Block_BFUBlock_BFUImpl_FBmux_imag_x_q_128_mem_dmem File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 4945 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_1_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_1_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_1_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 5095 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_1_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_1_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_1_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 5095 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_1_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_1_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_1_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 5095 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clocken0'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/redist10_fft_fftLight_FFTPipe_FFT4Block_2_fft2Block_BFUBlock_BFUImpl_FBmux_real_x_q_128_mem_dmem File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 5281 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_2_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_2_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_2_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 6223 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_2_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_2_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_2_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 6223 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_2_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_2_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_2_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 6223 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_2_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_2_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_2_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 6542 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_2_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_2_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_2_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 6542 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_2_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_2_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_2_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 6542 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_3_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_3_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_3_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 7399 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_3_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_3_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_3_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 7399 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_3_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_3_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_3_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 7399 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_3_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_3_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_3_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 7697 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_3_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_3_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_3_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 7697 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_3_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_3_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_3_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 7697 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_4_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_4_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_4_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 8222 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_4_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_4_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_4_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 8222 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_4_mult_realMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_4_mult_realSub_x_fft_fftLight_FFTPipe_TwiddleBlock_4_mult_realMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 8222 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_4_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_4_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_4_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 8384 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_4_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_4_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_4_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 8384 # ** Warning: (vsim-3016) Port type is incompatible with connection (port 'clk'). # Time: 0 fs Iteration: 0 Instance: /fft2_tb/fft2_inst/intel_fpga_unified_fft_0/fft_fftLight_FFTPipe_TwiddleBlock_4_mult_imagMult1_x_fft_fftLight_FFTPipe_TwiddleBlock_4_mult_imagAdd_x_fft_fftLight_FFTPipe_TwiddleBlock_4_mult_imagMult2_x_merged_cma_DSP0 File: ../../../../fft2/intel_FPGA_unified_fft_104/sim/fft2_intel_FPGA_unified_fft_104_3ngyi6y.sv Line: 8384 dir # Volume in drive C has no label. # Volume Serial Number is 3EBD-04D2 # # Directory of C:\quartus_projects\test_fft_speed\fft2_tb\fft2_tb\sim\mentor # # 20/04/2023 16:47 . # 20/04/2023 16:47 .. # 20/04/2023 16:45 137,984 fft2_intel_FPGA_unified_fft_104_3ngyi6y_chanIn_cunroll_x.stm # 20/04/2023 16:45 19,486 fft2_intel_FPGA_unified_fft_104_3ngyi6y_fft_fftLight_FFTPipe_TwiddleBlock_2_twiddleRom_dualMem_x.hex # 20/04/2023 16:47 libraries # 20/04/2023 16:47 100,976 modelsim.ini # 20/04/2023 16:46 20,651 msim_setup.tcl # 4 File(s) 279,097 bytes # 3 Dir(s) 71,677,063,168 bytes free