// megafunction wizard: %ALTACCUMULATE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altaccumulate 

// ============================================================
// File Name: acc_fir_a.v
// Megafunction Name(s):
// 			altaccumulate
//
// Simulation Library Files(s):
// 			altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 203 02/05/2008 SP 2 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acc_fir_a (
	cin,
	clken,
	clock,
	data,
	sload,
	overflow,
	result);

	input	  cin;
	input	  clken;
	input	  clock;
	input	[30:0]  data;
	input	  sload;
	output	  overflow;
	output	[30:0]  result;

	wire  sub_wire0;
	wire [30:0] sub_wire1;
	wire  overflow = sub_wire0;
	wire [30:0] result = sub_wire1[30:0];

	altaccumulate	altaccumulate_component (
				.cin (cin),
				.sload (sload),
				.clken (clken),
				.clock (clock),
				.data (data),
				.overflow (sub_wire0),
				.result (sub_wire1)
				// synopsys translate_off
				,
				.aclr (),
				.add_sub (),
				.cout (),
				.sign_data ()
				// synopsys translate_on
				);
	defparam
		altaccumulate_component.extra_latency = 1,
		altaccumulate_component.lpm_representation = "SIGNED",
		altaccumulate_component.lpm_type = "altaccumulate",
		altaccumulate_component.width_in = 31,
		altaccumulate_component.width_out = 31;


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
// Retrieval info: PRIVATE: CIN NUMERIC "1"
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: COUT NUMERIC "0"
// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LATENCY NUMERIC "1"
// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW NUMERIC "1"
// Retrieval info: PRIVATE: SLOAD NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "31"
// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "31"
// Retrieval info: CONSTANT: EXTRA_LATENCY NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "31"
// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "31"
// Retrieval info: USED_PORT: cin 0 0 0 0 INPUT GND cin
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
// Retrieval info: USED_PORT: data 0 0 31 0 INPUT NODEFVAL data[30..0]
// Retrieval info: USED_PORT: overflow 0 0 0 0 OUTPUT NODEFVAL overflow
// Retrieval info: USED_PORT: result 0 0 31 0 OUTPUT NODEFVAL result[30..0]
// Retrieval info: USED_PORT: sload 0 0 0 0 INPUT GND sload
// Retrieval info: CONNECT: @data 0 0 31 0 data 0 0 31 0
// Retrieval info: CONNECT: result 0 0 31 0 @result 0 0 31 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @sload 0 0 0 0 sload 0 0 0 0
// Retrieval info: CONNECT: @cin 0 0 0 0 cin 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: overflow 0 0 0 0 @overflow 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL acc_fir_a.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acc_fir_a.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acc_fir_a.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acc_fir_a.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acc_fir_a_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acc_fir_a_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acc_fir_a_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acc_fir_a_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf