ÿ U-Boot SPL 2023.10-31848-g0b3e82ca6e-dirty (Jun 07 2024 - 13:09:53 -0600) fpga_init HD MRPS spl_board_init: FPGA is in user mode fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x HD MRPS spl_board_init: FIRST config_pins return value is 0 fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x HD MRPS spl_board_init: SECOND config_pins return value is 0 HD MRPS spl_board_init: Entered section that begins DDRCAL HD MRPS spl_board_init: Resetting Cadence flash... 0 - 0 'spi@ff809000' - found fdtdec_get_addr_size_auto_parent: na=1, ns=1, fdtdec_get_addr_size_fixed: reg: addr=00000000x fdtdec_get_addr_size_auto_noparent: fdtdec_get_addr_size_auto_parent: na=1, ns=1, fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x fdtdec_get_addr_size_auto_parent: na=1, ns=1, fdtdec_get_addr_size_fixed: reg: addr=00000000x ofnode_read_bool: cdns,is-decoded-cs: false ofnode_read_u32_index: cdns,fifo-depth: x (128) ofnode_read_u32_index: cdns,fifo-width: x (4) ofnode_read_u32_index: cdns,trigger-address: x (0) ofnode_read_bool: cdns,is-dma: false ofnode_read_u32_index: spi-max-frequency: x (100000000) ofnode_read_u32_index: page-size: x (256) ofnode_read_u32_index: block-size: x (16) ofnode_read_u32_index: cdns,tshsl-ns: x (50) ofnode_read_u32_index: cdns,tsd2d-ns: x (50) ofnode_read_u32_index: cdns,tchsh-ns: x (4) ofnode_read_u32_index: cdns,tslch-ns: x (4) ofnode_read_u32_index: cdns,read-delay: (not found) cadence_spi_of_to_plat: regbase=ff809000 ahbbase=ffa00000 max-frequency=100000000 page-size=256 clk_set_defaults(spi@ff809000) clk_set_default_parents: could not read assigned-clock-parents for ffe29834 ofnode_read_prop: assigned-clock-rates: fdtdec_get_int: #clock-cells: x (0) Looking for qspi_clk Looking for qspi_clk - result for qspi_clk: qspi_clk (ret=0) - result for qspi_clk: qspi_clk (ret=0) ofnode_read_u32_index: fixed-divider: (not found) ofnode_read_u32_array: div-reg: fdtdec_get_int_array: div-reg get_prop_check_min_len: div-reg ofnode_read_u32_array: clk-gate: fdtdec_get_int_array: clk-gate get_prop_check_min_len: clk-gate clk_set_defaults(qspi_clk) clk_set_default_parents: could not read assigned-clock-parents for ffe29748 ofnode_read_prop: assigned-clock-rates: fdtdec_get_int: #clock-cells: x (0) fdtdec_get_int: #clock-cells: x (0) Looking for l4_main_clk Looking for l4_main_clk - result for l4_main_clk: l4_main_clk (ret=0) - result for l4_main_clk: l4_main_clk (ret=0) ofnode_read_u32_index: fixed-divider: (not found) ofnode_read_u32_array: div-reg: fdtdec_get_int_array: div-reg get_prop_check_min_len: div-reg ofnode_read_u32_array: clk-gate: fdtdec_get_int_array: clk-gate get_prop_check_min_len: clk-gate clk_set_defaults(l4_main_clk) clk_set_default_parents: could not read assigned-clock-parents for ffe29604 ofnode_read_prop: assigned-clock-rates: fdtdec_get_int: #clock-cells: x (0) fdtdec_get_int: #clock-cells: x (0) Looking for noc_free_clk@64 Looking for noc_free_clk@64 - result for noc_free_clk@64: noc_free_clk@64 (ret=0) - result for noc_free_clk@64: noc_free_clk@64 (ret=0) clk_of_xlate_default(clk=ffe2b8c0) clk_request(dev=ffe2952c, clk=ffe2b8c0) ofnode_read_u32_index: reg: (not found) clk_set_defaults(l4_main_clk) clk_set_default_parents: could not read assigned-clock-parents for ffe29604 ofnode_read_prop: assigned-clock-rates: clk_of_xlate_default(clk=ffe2b840) clk_request(dev=ffe29604, clk=ffe2b840) ofnode_read_u32_index: reg: (not found) clk_set_defaults(qspi_clk) clk_set_default_parents: could not read assigned-clock-parents for ffe29748 ofnode_read_prop: assigned-clock-rates: clk_of_xlate_default(clk=ffe24db0) clk_request(dev=ffe29748, clk=ffe24db0) clk_get_rate(clk=ffe24db0) clk_get_rate(clk=ffe2b840) clk_get_rate(clk=ffe2b8c0) clk_get_rate(clk=ffe2b0c0) clk_get_rate(clk=ffe2b400) clk_get_rate(clk=ffe2b1c0) clk_get_rate(clk=ffe2b280) clk_free(clk=ffe24db0) fdtdec_get_int: #reset-cells: x (1) fdtdec_get_int: #reset-cells: x (1) fdtdec_get_int: #reset-cells: x (1) Looking for rstmgr@ffd05000 Looking for rstmgr@ffd05000 - result for rstmgr@ffd05000: rstmgr@ffd05000 (ret=0) - result for rstmgr@ffd05000: rstmgr@ffd05000 (ret=0) reset_of_xlate_default(reset_ctl=ffe2b9c0) fdtdec_get_int: #reset-cells: x (1) fdtdec_get_int: #reset-cells: x (1) Looking for rstmgr@ffd05000 Looking for rstmgr@ffd05000 - result for rstmgr@ffd05000: rstmgr@ffd05000 (ret=0) - result for rstmgr@ffd05000: rstmgr@ffd05000 (ret=0) reset_of_xlate_default(reset_ctl=ffe2b9d0) reset_deassert(reset_ctl=ffe2b9c0) reset_deassert(reset_ctl=ffe2b9d0) ofnode_read_u32_index: spi-max-frequency: (not found) cadence_spi spi@ff809000: spi_find_chip_select: plat=ffe29934, cs=0 clk_set_defaults(n25q00a@0) clk_set_default_parents: could not read assigned-clock-parents for ffe298e4 ofnode_read_prop: assigned-clock-rates: cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 1000000Hz Div 0xf, actual 6250000Hz cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 100000000Hz Div 0x0, actual 100000000Hz SF: Read data capture delay calibrated to 7 (0 - 15) cadence_spi_set_speed: speed=100000000 cadence_qspi_apb_chipselect : chipselect 0 decode 0 jedec_spi_nor n25q00a@0: unrecognized JEDEC id bytes: ff, ff, ff spi_get_bus_and_cs: Error path, device 'n25q00a@0' Failed to initialize SPI flash at 0:0 (error -124) HD MRPS spl_board_init: Masking 2f & FPGA manager module reset from warm reset... HD MRPS spl_board_init: Setting up BootROM to configure both IO and pin mux after a warm reset... HD MRPS spl_board_init: Setting FSBL image as valid... HD MRPS spl_board_init: Calling set_regular_boot(true)... HD MRPS spl_board_init: Calling schedule()... HD MRPS spl_board_init: Calling reset_cpu()... clk_set_defaults(rstmgr@ffd05000) clk_set_default_parents: could not read assigned-clock-parents for ffe299c0 ofnode_read_prop: assigned-clock-rates: fdtdec_get_addr_size_auto_parent: na=1, ns=1, fdtdec_get_addr_size_fixed: reg: addr=00000000xÿ U-Boot SPL 2023.10-31848-g0b3e82ca6e-dirty (Jun 07 2024 - 13:09:53 -0600) fpga_init HD MRPS spl_board_init: FPGA is in user mode fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x HD MRPS spl_board_init: FIRST config_pins return value is 0 fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x HD MRPS spl_board_init: SECOND config_pins return value is 0 HD MRPS spl_board_init: Calling set_regular_boot(false)... HD MRPS spl_board_init: Unmasking 2f & FPGA manager module reset from warm reset... HD MRPS spl_board_init: Setting FSBL image as invalid... HD MRPS spl_board_init: BEGINNING DDRCAL DDRCAL: Success HD MRPS sdram_mmr_init: niosreserve1 is 19520 HD MRPS sdram_mmr_init: niosreserve0 is 1568 HD MRPS sdram_mmr_init: ddrioctl (initial) is 0 HD MRPS sdram_mmr_init: update_value is 1568 HD MRPS sdram_mmr_init: ddrioctl (final) is 1 HD MRPS sdram_mmr_init: io48_value (initial) is 199183 HD MRPS sdram_mmr_init: update_value (or ddr config match) is 3 HD MRPS sdram_mmr_init: ctrlcfg0_cfg_ctrl_burst_len is 8 HD MRPS sdram_mmr_init: caltim0_cfg_act_to_rdwr is 6 HD MRPS sdram_mmr_init: caltim0_cfg_act_to_act is 22 HD MRPS sdram_mmr_init: caltim0_cfg_act_to_act_db is 4 HD MRPS sdram_mmr_init: caltim1_cfg_rd_to_wr is 7 HD MRPS sdram_mmr_init: caltim1_cfg_rd_to_rd_dc is 4 HD MRPS sdram_mmr_init: caltim1_cfg_rd_to_wr_dc is 7 HD MRPS sdram_mmr_init: caltim2_cfg_rd_to_pch is 4 HD MRPS sdram_mmr_init: caltim3_cfg_wr_to_rd is 17 HD MRPS sdram_mmr_init: caltim3_cfg_wr_to_rd_dc is 5 HD MRPS sdram_mmr_init: caltim4_cfg_pch_to_valid is 7 HD MRPS sdram_mmr_init: caltim9_cfg_4_act_to_act is 13 HD MRPS sdram_mmr_init: update_value is 15 HD MRPS sdram_mmr_init: io48_value (final)is 24 HD MRPS sdram_mmr_init: ECC is NOT enabled! SDRAM size=1073741824 HD MRPS ddr_calibration_sequence: Size returned from sdram_size_cal is 1073741824 HD MRPS ddr_calibration_sequence: else statement: gd->ram_size is 1073741824 fdtdec_setup_memory_banksize: DRAM Bank #0: start = 0xx, size = 0xx HD MRPS ddr_calibration_sequence: gd->bd->bi_dram[0].size is 1073741824 fdtdec_get_int_array: mpu0 get_prop_check_min_len: mpu0 fdtdec_get_int_array: mpu1 get_prop_check_min_len: mpu1 fdtdec_get_int_array: altr,mpu1 get_prop_check_min_len: altr,mpu1 fdtdec_get_int_array: mpu2 get_prop_check_min_len: mpu2 fdtdec_get_int_array: altr,mpu2 get_prop_check_min_len: altr,mpu2 fdtdec_get_int_array: mpu3 get_prop_check_min_len: mpu3 fdtdec_get_int_array: altr,mpu3 get_prop_check_min_len: altr,mpu3 fdtdec_get_int_array: l3-0 get_prop_check_min_len: l3-0 fdtdec_get_int_array: l3-1 get_prop_check_min_len: l3-1 fdtdec_get_int_array: altr,l3-1 get_prop_check_min_len: altr,l3-1 fdtdec_get_int_array: l3-2 get_prop_check_min_len: l3-2 fdtdec_get_int_array: altr,l3-2 get_prop_check_min_len: altr,l3-2 fdtdec_get_int_array: l3-3 get_prop_check_min_len: l3-3 fdtdec_get_int_array: altr,l3-3 get_prop_check_min_len: altr,l3-3 fdtdec_get_int_array: l3-4 get_prop_check_min_len: l3-4 fdtdec_get_int_array: altr,l3-4 get_prop_check_min_len: altr,l3-4 fdtdec_get_int_array: l3-5 get_prop_check_min_len: l3-5 fdtdec_get_int_array: altr,l3-5 get_prop_check_min_len: altr,l3-5 fdtdec_get_int_array: l3-6 get_prop_check_min_len: l3-6 fdtdec_get_int_array: altr,l3-6 get_prop_check_min_len: altr,l3-6 fdtdec_get_int_array: l3-7 get_prop_check_min_len: l3-7 fdtdec_get_int_array: altr,l3-7 get_prop_check_min_len: altr,l3-7 fdtdec_get_int_array: fpga2sdram0-0 get_prop_check_min_len: fpga2sdram0-0 fdtdec_get_int_array: fpga2sdram0-1 get_prop_check_min_len: fpga2sdram0-1 fdtdec_get_int_array: altr,fpga2sdram0-1 get_prop_check_min_len: altr,fpga2sdram0-1 fdtdec_get_int_array: fpga2sdram0-2 get_prop_check_min_len: fpga2sdram0-2 fdtdec_get_int_array: altr,fpga2sdram0-2 get_prop_check_min_len: altr,fpga2sdram0-2 fdtdec_get_int_array: fpga2sdram0-3 get_prop_check_min_len: fpga2sdram0-3 fdtdec_get_int_array: altr,fpga2sdram0-3 get_prop_check_min_len: altr,fpga2sdram0-3 fdtdec_get_int_array: fpga2sdram1-0 get_prop_check_min_len: fpga2sdram1-0 fdtdec_get_int_array: fpga2sdram1-1 get_prop_check_min_len: fpga2sdram1-1 fdtdec_get_int_array: altr,fpga2sdram1-1 get_prop_check_min_len: altr,fpga2sdram1-1 fdtdec_get_int_array: fpga2sdram1-2 get_prop_check_min_len: fpga2sdram1-2 fdtdec_get_int_array: altr,fpga2sdram1-2 get_prop_check_min_len: altr,fpga2sdram1-2 fdtdec_get_int_array: fpga2sdram1-3 get_prop_check_min_len: fpga2sdram1-3 fdtdec_get_int_array: altr,fpga2sdram1-3 get_prop_check_min_len: altr,fpga2sdram1-3 fdtdec_get_int_array: fpga2sdram2-0 get_prop_check_min_len: fpga2sdram2-0 fdtdec_get_int_array: fpga2sdram2-1 get_prop_check_min_len: fpga2sdram2-1 fdtdec_get_int_array: altr,fpga2sdram2-1 get_prop_check_min_len: altr,fpga2sdram2-1 fdtdec_get_int_array: fpga2sdram2-2 get_prop_check_min_len: fpga2sdram2-2 fdtdec_get_int_array: altr,fpga2sdram2-2 get_prop_check_min_len: altr,fpga2sdram2-2 fdtdec_get_int_array: fpga2sdram2-3 get_prop_check_min_len: fpga2sdram2-3 fdtdec_get_int_array: altr,fpga2sdram2-3 get_prop_check_min_len: altr,fpga2sdram2-3 HD MRPS ddr_calibration_sequence: gd->bd->bi_dram[0].size is 1073741824 (right before sdram_size_check) DDR: Running SDRAM size sanity check HD MRPS sdram_size_check: sizeof(unsigned long) == 4 HD MRPS sdram_size_check: sizeof(long) == 4 HD MRPS sdram_size_check: sizeof(phys_size_t) == 4 HD MRPS sdram_size_check: gd->bd->bi_dram[0].start == 0 HD MRPS sdram_size_check: gd->bd->bi_dram[0].size == 1073741824 HD MRPS get_ram_size_hdmrps: BITS_PER_LONG == 32 HD MRPS get_ram_size_hdmrps: bits_per_ulong == 32 HD MRPS get_ram_size_hdmrps: size is 256 HD MRPS sdram_size_check: ram_check == 256 DDR: SDRAM size check failed! HD MRPS spl_board_init: ENDING DDRCAL ofnode_read_u32_index: timeout-sec: (not found) ofnode_read_u32_index: hw_margin_ms: (not found) ofnode_read_bool: u-boot,noautostart: false ofnode_read_bool: u-boot,autostart: false clk_set_defaults(watchdog@ffd00300) clk_set_default_parents: could not read assigned-clock-parents for ffe29b7c ofnode_read_prop: assigned-clock-rates: fdtdec_get_addr_size_auto_parent: na=1, ns=1, fdtdec_get_addr_size_fixed: reg: addr=00000000x fdtdec_get_int: #clock-cells: x (0) Looking for l4_sys_free_clk Looking for l4_sys_free_clk - result for l4_sys_free_clk: l4_sys_free_clk (ret=0) - result for l4_sys_free_clk: l4_sys_free_clk (ret=0) clk_of_xlate_default(clk=ffe28e48) clk_request(dev=ffe29598, clk=ffe28e48) clk_enable(clk=ffe28e48) clk_enable(clk=ffe2b6c0) clk_enable(clk=ffe2b0c0) clk_enable(clk=ffe2b400) clk_enable(clk=ffe2b1c0) clk_enable(clk=ffe2b280) clk_get_rate(clk=ffe28e48) clk_get_rate(clk=ffe2b6c0) clk_get_rate(clk=ffe2b0c0) clk_get_rate(clk=ffe2b400) clk_get_rate(clk=ffe2b1c0) clk_get_rate(clk=ffe2b280) ofnode_read_prop: resets: fdtdec_get_int: #reset-cells: x (1) fdtdec_get_int: #reset-cells: x (1) Looking for rstmgr@ffd05000 Looking for rstmgr@ffd05000 - result for rstmgr@ffd05000: rstmgr@ffd05000 (ret=0) - result for rstmgr@ffd05000: rstmgr@ffd05000 (ret=0) reset_of_xlate_default(reset_ctl=ffe2b7c0) reset_deassert(reset_ctl=ffe2b7c0) ofnode_read_prop: resets: reset_assert(reset_ctl=ffe2b7c0) reset_deassert(reset_ctl=ffe2b7c0) ofnode_read_prop: resets: reset_assert(reset_ctl=ffe2b7c0) reset_deassert(reset_ctl=ffe2b7c0) WDT: Started watchdog@ffd00300 with servicing every 1000ms (10s timeout)