|project_top
rst_n => rst_n.IN6
clk_in => clk_in.IN1
mii_rx_clk => mii_rx_clk.IN1
mii_rx_er => mii_rx_er.IN1
mii_rx_dv => mii_rx_dv.IN1
mii_rxd[0] => mii_rxd[0].IN1
mii_rxd[1] => mii_rxd[1].IN1
mii_rxd[2] => mii_rxd[2].IN1
mii_rxd[3] => mii_rxd[3].IN1
mii_tx_clk => mii_tx_clk.IN1
mii_tx_en <= mac_ip_0002:mac_ip_inst.m_tx_en
mii_txd[0] <= mac_ip_0002:mac_ip_inst.m_tx_d
mii_txd[1] <= mac_ip_0002:mac_ip_inst.m_tx_d
mii_txd[2] <= mac_ip_0002:mac_ip_inst.m_tx_d
mii_txd[3] <= mac_ip_0002:mac_ip_inst.m_tx_d
crs => ~NO_FANOUT~
col => ~NO_FANOUT~
eth_mdc <= mac_ip_0002:mac_ip_inst.mdc
eth_mdio <> eth_mdio
phy_rst <= dp83848_rst:dp83848_rst_ins.phy_rst
led_test <= led:led_ins.led_out


|project_top|mac_reg:mac_reg_ins
clk => reg_addr[0]~reg0.CLK
clk => reg_addr[1]~reg0.CLK
clk => reg_addr[2]~reg0.CLK
clk => reg_addr[3]~reg0.CLK
clk => reg_addr[4]~reg0.CLK
clk => reg_addr[5]~reg0.CLK
clk => reg_addr[6]~reg0.CLK
clk => reg_addr[7]~reg0.CLK
clk => reg_wdata[0]~reg0.CLK
clk => reg_wdata[1]~reg0.CLK
clk => reg_wdata[2]~reg0.CLK
clk => reg_wdata[3]~reg0.CLK
clk => reg_wdata[4]~reg0.CLK
clk => reg_wdata[5]~reg0.CLK
clk => reg_wdata[6]~reg0.CLK
clk => reg_wdata[7]~reg0.CLK
clk => reg_wdata[8]~reg0.CLK
clk => reg_wdata[9]~reg0.CLK
clk => reg_wdata[10]~reg0.CLK
clk => reg_wdata[11]~reg0.CLK
clk => reg_wdata[12]~reg0.CLK
clk => reg_wdata[13]~reg0.CLK
clk => reg_wdata[14]~reg0.CLK
clk => reg_wdata[15]~reg0.CLK
clk => reg_wdata[16]~reg0.CLK
clk => reg_wdata[17]~reg0.CLK
clk => reg_wdata[18]~reg0.CLK
clk => reg_wdata[19]~reg0.CLK
clk => reg_wdata[20]~reg0.CLK
clk => reg_wdata[21]~reg0.CLK
clk => reg_wdata[22]~reg0.CLK
clk => reg_wdata[23]~reg0.CLK
clk => reg_wdata[24]~reg0.CLK
clk => reg_wdata[25]~reg0.CLK
clk => reg_wdata[26]~reg0.CLK
clk => reg_wdata[27]~reg0.CLK
clk => reg_wdata[28]~reg0.CLK
clk => reg_wdata[29]~reg0.CLK
clk => reg_wdata[30]~reg0.CLK
clk => reg_wdata[31]~reg0.CLK
clk => reg_read~reg0.CLK
clk => time_wait[0].CLK
clk => time_wait[1].CLK
clk => time_wait[2].CLK
clk => time_wait[3].CLK
clk => time_wait[4].CLK
clk => time_wait[5].CLK
clk => time_wait[6].CLK
clk => time_wait[7].CLK
clk => wait_flag.CLK
clk => reg_write~reg0.CLK
clk => flag_en.CLK
clk => cnt_wait[0].CLK
clk => cnt_wait[1].CLK
clk => cnt_wait[2].CLK
clk => cnt_wait[3].CLK
clk => cnt_wait[4].CLK
clk => cnt_wait[5].CLK
clk => cnt_wait[6].CLK
clk => cnt_wait[7].CLK
clk => cnt_reg[0].CLK
clk => cnt_reg[1].CLK
clk => cnt_reg[2].CLK
clk => cnt_reg[3].CLK
clk => cnt_reg[4].CLK
clk => cnt_wridle[0].CLK
clk => cnt_wridle[1].CLK
rst_n => reg_wdata[0]~reg0.ACLR
rst_n => reg_wdata[1]~reg0.ACLR
rst_n => reg_wdata[2]~reg0.ACLR
rst_n => reg_wdata[3]~reg0.ACLR
rst_n => reg_wdata[4]~reg0.ACLR
rst_n => reg_wdata[5]~reg0.ACLR
rst_n => reg_wdata[6]~reg0.ACLR
rst_n => reg_wdata[7]~reg0.ACLR
rst_n => reg_wdata[8]~reg0.ACLR
rst_n => reg_wdata[9]~reg0.ACLR
rst_n => reg_wdata[10]~reg0.ACLR
rst_n => reg_wdata[11]~reg0.ACLR
rst_n => reg_wdata[12]~reg0.ACLR
rst_n => reg_wdata[13]~reg0.ACLR
rst_n => reg_wdata[14]~reg0.ACLR
rst_n => reg_wdata[15]~reg0.ACLR
rst_n => reg_wdata[16]~reg0.ACLR
rst_n => reg_wdata[17]~reg0.ACLR
rst_n => reg_wdata[18]~reg0.ACLR
rst_n => reg_wdata[19]~reg0.ACLR
rst_n => reg_wdata[20]~reg0.ACLR
rst_n => reg_wdata[21]~reg0.ACLR
rst_n => reg_wdata[22]~reg0.ACLR
rst_n => reg_wdata[23]~reg0.ACLR
rst_n => reg_wdata[24]~reg0.ACLR
rst_n => reg_wdata[25]~reg0.ACLR
rst_n => reg_wdata[26]~reg0.ACLR
rst_n => reg_wdata[27]~reg0.ACLR
rst_n => reg_wdata[28]~reg0.ACLR
rst_n => reg_wdata[29]~reg0.ACLR
rst_n => reg_wdata[30]~reg0.ACLR
rst_n => reg_wdata[31]~reg0.ACLR
rst_n => reg_addr[0]~reg0.ACLR
rst_n => reg_addr[1]~reg0.ACLR
rst_n => reg_addr[2]~reg0.ACLR
rst_n => reg_addr[3]~reg0.ACLR
rst_n => reg_addr[4]~reg0.ACLR
rst_n => reg_addr[5]~reg0.ACLR
rst_n => reg_addr[6]~reg0.ACLR
rst_n => reg_addr[7]~reg0.ACLR
rst_n => reg_read~reg0.ACLR
rst_n => reg_write~reg0.ACLR
rst_n => cnt_wridle[0].ACLR
rst_n => cnt_wridle[1].ACLR
rst_n => cnt_reg[0].ACLR
rst_n => cnt_reg[1].ACLR
rst_n => cnt_reg[2].ACLR
rst_n => cnt_reg[3].ACLR
rst_n => cnt_reg[4].ACLR
rst_n => cnt_wait[0].ACLR
rst_n => cnt_wait[1].ACLR
rst_n => cnt_wait[2].ACLR
rst_n => cnt_wait[3].ACLR
rst_n => cnt_wait[4].ACLR
rst_n => cnt_wait[5].ACLR
rst_n => cnt_wait[6].ACLR
rst_n => cnt_wait[7].ACLR
rst_n => flag_en.ACLR
rst_n => wait_flag.ACLR
rst_n => time_wait[0].ACLR
rst_n => time_wait[1].ACLR
rst_n => time_wait[2].ACLR
rst_n => time_wait[3].ACLR
rst_n => time_wait[4].ACLR
rst_n => time_wait[5].ACLR
rst_n => time_wait[6].ACLR
rst_n => time_wait[7].ACLR
config_en => flag_en.OUTPUTSELECT
mac_self[0] => Mux10.IN31
mac_self[1] => Mux9.IN31
mac_self[2] => Mux8.IN31
mac_self[3] => Mux7.IN31
mac_self[4] => Mux6.IN31
mac_self[5] => Mux5.IN31
mac_self[6] => Mux4.IN31
mac_self[7] => Mux3.IN31
mac_self[8] => Mux18.IN31
mac_self[9] => Mux17.IN31
mac_self[10] => Mux16.IN31
mac_self[11] => Mux15.IN31
mac_self[12] => Mux14.IN31
mac_self[13] => Mux13.IN31
mac_self[14] => Mux12.IN31
mac_self[15] => Mux11.IN31
mac_self[16] => data_reg[24].DATAB
mac_self[17] => Mux0.IN31
mac_self[18] => data_reg[26].DATAB
mac_self[19] => data_reg[27].DATAB
mac_self[20] => data_reg[28].DATAB
mac_self[21] => data_reg[29].DATAB
mac_self[22] => data_reg[30].DATAB
mac_self[23] => data_reg[31].DATAB
mac_self[24] => data_reg[16].DATAB
mac_self[25] => data_reg[17].DATAB
mac_self[26] => Mux2.IN31
mac_self[27] => data_reg[19].DATAB
mac_self[28] => data_reg[20].DATAB
mac_self[29] => data_reg[21].DATAB
mac_self[30] => data_reg[22].DATAB
mac_self[31] => Mux1.IN31
mac_self[32] => Mux10.IN30
mac_self[33] => Mux9.IN30
mac_self[34] => Mux8.IN30
mac_self[35] => Mux7.IN30
mac_self[36] => Mux6.IN30
mac_self[37] => Mux5.IN30
mac_self[38] => Mux4.IN30
mac_self[39] => Mux3.IN30
mac_self[40] => Mux18.IN30
mac_self[41] => Mux17.IN30
mac_self[42] => Mux16.IN30
mac_self[43] => Mux15.IN30
mac_self[44] => Mux14.IN30
mac_self[45] => Mux13.IN30
mac_self[46] => Mux12.IN30
mac_self[47] => Mux11.IN30
reg_addr[0] <= reg_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_addr[1] <= reg_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_addr[2] <= reg_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_addr[3] <= reg_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_addr[4] <= reg_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_addr[5] <= reg_addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_addr[6] <= reg_addr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_addr[7] <= reg_addr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_read <= reg_read~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[0] => ~NO_FANOUT~
reg_rdata[1] => ~NO_FANOUT~
reg_rdata[2] => ~NO_FANOUT~
reg_rdata[3] => ~NO_FANOUT~
reg_rdata[4] => ~NO_FANOUT~
reg_rdata[5] => ~NO_FANOUT~
reg_rdata[6] => ~NO_FANOUT~
reg_rdata[7] => ~NO_FANOUT~
reg_rdata[8] => ~NO_FANOUT~
reg_rdata[9] => ~NO_FANOUT~
reg_rdata[10] => ~NO_FANOUT~
reg_rdata[11] => ~NO_FANOUT~
reg_rdata[12] => ~NO_FANOUT~
reg_rdata[13] => ~NO_FANOUT~
reg_rdata[14] => ~NO_FANOUT~
reg_rdata[15] => ~NO_FANOUT~
reg_rdata[16] => ~NO_FANOUT~
reg_rdata[17] => ~NO_FANOUT~
reg_rdata[18] => ~NO_FANOUT~
reg_rdata[19] => ~NO_FANOUT~
reg_rdata[20] => ~NO_FANOUT~
reg_rdata[21] => ~NO_FANOUT~
reg_rdata[22] => ~NO_FANOUT~
reg_rdata[23] => ~NO_FANOUT~
reg_rdata[24] => ~NO_FANOUT~
reg_rdata[25] => ~NO_FANOUT~
reg_rdata[26] => ~NO_FANOUT~
reg_rdata[27] => ~NO_FANOUT~
reg_rdata[28] => ~NO_FANOUT~
reg_rdata[29] => ~NO_FANOUT~
reg_rdata[30] => ~NO_FANOUT~
reg_rdata[31] => ~NO_FANOUT~
reg_rvld => ~NO_FANOUT~
reg_write <= reg_write~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[0] <= reg_wdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[1] <= reg_wdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[2] <= reg_wdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[3] <= reg_wdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[4] <= reg_wdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[5] <= reg_wdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[6] <= reg_wdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[7] <= reg_wdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[8] <= reg_wdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[9] <= reg_wdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[10] <= reg_wdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[11] <= reg_wdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[12] <= reg_wdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[13] <= reg_wdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[14] <= reg_wdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[15] <= reg_wdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[16] <= reg_wdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[17] <= reg_wdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[18] <= reg_wdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[19] <= reg_wdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[20] <= reg_wdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[21] <= reg_wdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[22] <= reg_wdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[23] <= reg_wdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[24] <= reg_wdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[25] <= reg_wdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[26] <= reg_wdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[27] <= reg_wdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[28] <= reg_wdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[29] <= reg_wdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[30] <= reg_wdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_wdata[31] <= reg_wdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdy => add_cnt_wridle.IN1


|project_top|mac_reg_config:mac_reg_config_ins
clk => reg_rvld~reg0.CLK
clk => reg_rdata[0]~reg0.CLK
clk => reg_rdata[1]~reg0.CLK
clk => reg_rdata[2]~reg0.CLK
clk => reg_rdata[3]~reg0.CLK
clk => reg_rdata[4]~reg0.CLK
clk => reg_rdata[5]~reg0.CLK
clk => reg_rdata[6]~reg0.CLK
clk => reg_rdata[7]~reg0.CLK
clk => reg_rdata[8]~reg0.CLK
clk => reg_rdata[9]~reg0.CLK
clk => reg_rdata[10]~reg0.CLK
clk => reg_rdata[11]~reg0.CLK
clk => reg_rdata[12]~reg0.CLK
clk => reg_rdata[13]~reg0.CLK
clk => reg_rdata[14]~reg0.CLK
clk => reg_rdata[15]~reg0.CLK
clk => reg_rdata[16]~reg0.CLK
clk => reg_rdata[17]~reg0.CLK
clk => reg_rdata[18]~reg0.CLK
clk => reg_rdata[19]~reg0.CLK
clk => reg_rdata[20]~reg0.CLK
clk => reg_rdata[21]~reg0.CLK
clk => reg_rdata[22]~reg0.CLK
clk => reg_rdata[23]~reg0.CLK
clk => reg_rdata[24]~reg0.CLK
clk => reg_rdata[25]~reg0.CLK
clk => reg_rdata[26]~reg0.CLK
clk => reg_rdata[27]~reg0.CLK
clk => reg_rdata[28]~reg0.CLK
clk => reg_rdata[29]~reg0.CLK
clk => reg_rdata[30]~reg0.CLK
clk => reg_rdata[31]~reg0.CLK
clk => mac_addr[0]~reg0.CLK
clk => mac_addr[1]~reg0.CLK
clk => mac_addr[2]~reg0.CLK
clk => mac_addr[3]~reg0.CLK
clk => mac_addr[4]~reg0.CLK
clk => mac_addr[5]~reg0.CLK
clk => mac_addr[6]~reg0.CLK
clk => mac_addr[7]~reg0.CLK
clk => mac_wdata[0]~reg0.CLK
clk => mac_wdata[1]~reg0.CLK
clk => mac_wdata[2]~reg0.CLK
clk => mac_wdata[3]~reg0.CLK
clk => mac_wdata[4]~reg0.CLK
clk => mac_wdata[5]~reg0.CLK
clk => mac_wdata[6]~reg0.CLK
clk => mac_wdata[7]~reg0.CLK
clk => mac_wdata[8]~reg0.CLK
clk => mac_wdata[9]~reg0.CLK
clk => mac_wdata[10]~reg0.CLK
clk => mac_wdata[11]~reg0.CLK
clk => mac_wdata[12]~reg0.CLK
clk => mac_wdata[13]~reg0.CLK
clk => mac_wdata[14]~reg0.CLK
clk => mac_wdata[15]~reg0.CLK
clk => mac_wdata[16]~reg0.CLK
clk => mac_wdata[17]~reg0.CLK
clk => mac_wdata[18]~reg0.CLK
clk => mac_wdata[19]~reg0.CLK
clk => mac_wdata[20]~reg0.CLK
clk => mac_wdata[21]~reg0.CLK
clk => mac_wdata[22]~reg0.CLK
clk => mac_wdata[23]~reg0.CLK
clk => mac_wdata[24]~reg0.CLK
clk => mac_wdata[25]~reg0.CLK
clk => mac_wdata[26]~reg0.CLK
clk => mac_wdata[27]~reg0.CLK
clk => mac_wdata[28]~reg0.CLK
clk => mac_wdata[29]~reg0.CLK
clk => mac_wdata[30]~reg0.CLK
clk => mac_wdata[31]~reg0.CLK
clk => mac_read~reg0.CLK
clk => mac_write~reg0.CLK
clk => mac_wait_ff0.CLK
rst_n => reg_rdata[0]~reg0.ACLR
rst_n => reg_rdata[1]~reg0.ACLR
rst_n => reg_rdata[2]~reg0.ACLR
rst_n => reg_rdata[3]~reg0.ACLR
rst_n => reg_rdata[4]~reg0.ACLR
rst_n => reg_rdata[5]~reg0.ACLR
rst_n => reg_rdata[6]~reg0.ACLR
rst_n => reg_rdata[7]~reg0.ACLR
rst_n => reg_rdata[8]~reg0.ACLR
rst_n => reg_rdata[9]~reg0.ACLR
rst_n => reg_rdata[10]~reg0.ACLR
rst_n => reg_rdata[11]~reg0.ACLR
rst_n => reg_rdata[12]~reg0.ACLR
rst_n => reg_rdata[13]~reg0.ACLR
rst_n => reg_rdata[14]~reg0.ACLR
rst_n => reg_rdata[15]~reg0.ACLR
rst_n => reg_rdata[16]~reg0.ACLR
rst_n => reg_rdata[17]~reg0.ACLR
rst_n => reg_rdata[18]~reg0.ACLR
rst_n => reg_rdata[19]~reg0.ACLR
rst_n => reg_rdata[20]~reg0.ACLR
rst_n => reg_rdata[21]~reg0.ACLR
rst_n => reg_rdata[22]~reg0.ACLR
rst_n => reg_rdata[23]~reg0.ACLR
rst_n => reg_rdata[24]~reg0.ACLR
rst_n => reg_rdata[25]~reg0.ACLR
rst_n => reg_rdata[26]~reg0.ACLR
rst_n => reg_rdata[27]~reg0.ACLR
rst_n => reg_rdata[28]~reg0.ACLR
rst_n => reg_rdata[29]~reg0.ACLR
rst_n => reg_rdata[30]~reg0.ACLR
rst_n => reg_rdata[31]~reg0.ACLR
rst_n => reg_rvld~reg0.ACLR
rst_n => mac_addr[0]~reg0.ACLR
rst_n => mac_addr[1]~reg0.ACLR
rst_n => mac_addr[2]~reg0.ACLR
rst_n => mac_addr[3]~reg0.ACLR
rst_n => mac_addr[4]~reg0.ACLR
rst_n => mac_addr[5]~reg0.ACLR
rst_n => mac_addr[6]~reg0.ACLR
rst_n => mac_addr[7]~reg0.ACLR
rst_n => mac_read~reg0.ACLR
rst_n => mac_write~reg0.ACLR
rst_n => mac_wdata[0]~reg0.ACLR
rst_n => mac_wdata[1]~reg0.ACLR
rst_n => mac_wdata[2]~reg0.ACLR
rst_n => mac_wdata[3]~reg0.ACLR
rst_n => mac_wdata[4]~reg0.ACLR
rst_n => mac_wdata[5]~reg0.ACLR
rst_n => mac_wdata[6]~reg0.ACLR
rst_n => mac_wdata[7]~reg0.ACLR
rst_n => mac_wdata[8]~reg0.ACLR
rst_n => mac_wdata[9]~reg0.ACLR
rst_n => mac_wdata[10]~reg0.ACLR
rst_n => mac_wdata[11]~reg0.ACLR
rst_n => mac_wdata[12]~reg0.ACLR
rst_n => mac_wdata[13]~reg0.ACLR
rst_n => mac_wdata[14]~reg0.ACLR
rst_n => mac_wdata[15]~reg0.ACLR
rst_n => mac_wdata[16]~reg0.ACLR
rst_n => mac_wdata[17]~reg0.ACLR
rst_n => mac_wdata[18]~reg0.ACLR
rst_n => mac_wdata[19]~reg0.ACLR
rst_n => mac_wdata[20]~reg0.ACLR
rst_n => mac_wdata[21]~reg0.ACLR
rst_n => mac_wdata[22]~reg0.ACLR
rst_n => mac_wdata[23]~reg0.ACLR
rst_n => mac_wdata[24]~reg0.ACLR
rst_n => mac_wdata[25]~reg0.ACLR
rst_n => mac_wdata[26]~reg0.ACLR
rst_n => mac_wdata[27]~reg0.ACLR
rst_n => mac_wdata[28]~reg0.ACLR
rst_n => mac_wdata[29]~reg0.ACLR
rst_n => mac_wdata[30]~reg0.ACLR
rst_n => mac_wdata[31]~reg0.ACLR
rst_n => mac_wait_ff0.PRESET
reg_write => mac_write.OUTPUTSELECT
reg_write => always7.IN0
reg_write => mac_wdata[31]~reg0.ENA
reg_write => mac_wdata[30]~reg0.ENA
reg_write => mac_wdata[29]~reg0.ENA
reg_write => mac_wdata[28]~reg0.ENA
reg_write => mac_wdata[27]~reg0.ENA
reg_write => mac_wdata[26]~reg0.ENA
reg_write => mac_wdata[25]~reg0.ENA
reg_write => mac_wdata[24]~reg0.ENA
reg_write => mac_wdata[23]~reg0.ENA
reg_write => mac_wdata[22]~reg0.ENA
reg_write => mac_wdata[21]~reg0.ENA
reg_write => mac_wdata[20]~reg0.ENA
reg_write => mac_wdata[19]~reg0.ENA
reg_write => mac_wdata[18]~reg0.ENA
reg_write => mac_wdata[17]~reg0.ENA
reg_write => mac_wdata[16]~reg0.ENA
reg_write => mac_wdata[15]~reg0.ENA
reg_write => mac_wdata[14]~reg0.ENA
reg_write => mac_wdata[13]~reg0.ENA
reg_write => mac_wdata[12]~reg0.ENA
reg_write => mac_wdata[11]~reg0.ENA
reg_write => mac_wdata[10]~reg0.ENA
reg_write => mac_wdata[9]~reg0.ENA
reg_write => mac_wdata[8]~reg0.ENA
reg_write => mac_wdata[7]~reg0.ENA
reg_write => mac_wdata[6]~reg0.ENA
reg_write => mac_wdata[5]~reg0.ENA
reg_write => mac_wdata[4]~reg0.ENA
reg_write => mac_wdata[3]~reg0.ENA
reg_write => mac_wdata[2]~reg0.ENA
reg_write => mac_wdata[1]~reg0.ENA
reg_write => mac_wdata[0]~reg0.ENA
reg_read => mac_read.OUTPUTSELECT
reg_read => always7.IN1
reg_rdy <= always7.DB_MAX_OUTPUT_PORT_TYPE
reg_addr[0] => mac_addr[0]~reg0.DATAIN
reg_addr[1] => mac_addr[1]~reg0.DATAIN
reg_addr[2] => mac_addr[2]~reg0.DATAIN
reg_addr[3] => mac_addr[3]~reg0.DATAIN
reg_addr[4] => mac_addr[4]~reg0.DATAIN
reg_addr[5] => mac_addr[5]~reg0.DATAIN
reg_addr[6] => mac_addr[6]~reg0.DATAIN
reg_addr[7] => mac_addr[7]~reg0.DATAIN
reg_wdata[0] => mac_wdata[0]~reg0.DATAIN
reg_wdata[1] => mac_wdata[1]~reg0.DATAIN
reg_wdata[2] => mac_wdata[2]~reg0.DATAIN
reg_wdata[3] => mac_wdata[3]~reg0.DATAIN
reg_wdata[4] => mac_wdata[4]~reg0.DATAIN
reg_wdata[5] => mac_wdata[5]~reg0.DATAIN
reg_wdata[6] => mac_wdata[6]~reg0.DATAIN
reg_wdata[7] => mac_wdata[7]~reg0.DATAIN
reg_wdata[8] => mac_wdata[8]~reg0.DATAIN
reg_wdata[9] => mac_wdata[9]~reg0.DATAIN
reg_wdata[10] => mac_wdata[10]~reg0.DATAIN
reg_wdata[11] => mac_wdata[11]~reg0.DATAIN
reg_wdata[12] => mac_wdata[12]~reg0.DATAIN
reg_wdata[13] => mac_wdata[13]~reg0.DATAIN
reg_wdata[14] => mac_wdata[14]~reg0.DATAIN
reg_wdata[15] => mac_wdata[15]~reg0.DATAIN
reg_wdata[16] => mac_wdata[16]~reg0.DATAIN
reg_wdata[17] => mac_wdata[17]~reg0.DATAIN
reg_wdata[18] => mac_wdata[18]~reg0.DATAIN
reg_wdata[19] => mac_wdata[19]~reg0.DATAIN
reg_wdata[20] => mac_wdata[20]~reg0.DATAIN
reg_wdata[21] => mac_wdata[21]~reg0.DATAIN
reg_wdata[22] => mac_wdata[22]~reg0.DATAIN
reg_wdata[23] => mac_wdata[23]~reg0.DATAIN
reg_wdata[24] => mac_wdata[24]~reg0.DATAIN
reg_wdata[25] => mac_wdata[25]~reg0.DATAIN
reg_wdata[26] => mac_wdata[26]~reg0.DATAIN
reg_wdata[27] => mac_wdata[27]~reg0.DATAIN
reg_wdata[28] => mac_wdata[28]~reg0.DATAIN
reg_wdata[29] => mac_wdata[29]~reg0.DATAIN
reg_wdata[30] => mac_wdata[30]~reg0.DATAIN
reg_wdata[31] => mac_wdata[31]~reg0.DATAIN
reg_rdata[0] <= reg_rdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[1] <= reg_rdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[2] <= reg_rdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[3] <= reg_rdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[4] <= reg_rdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[5] <= reg_rdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[6] <= reg_rdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[7] <= reg_rdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[8] <= reg_rdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[9] <= reg_rdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[10] <= reg_rdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[11] <= reg_rdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[12] <= reg_rdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[13] <= reg_rdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[14] <= reg_rdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[15] <= reg_rdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[16] <= reg_rdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[17] <= reg_rdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[18] <= reg_rdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[19] <= reg_rdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[20] <= reg_rdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[21] <= reg_rdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[22] <= reg_rdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[23] <= reg_rdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[24] <= reg_rdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[25] <= reg_rdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[26] <= reg_rdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[27] <= reg_rdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[28] <= reg_rdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[29] <= reg_rdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[30] <= reg_rdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rdata[31] <= reg_rdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_rvld <= reg_rvld~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_addr[0] <= mac_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_addr[1] <= mac_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_addr[2] <= mac_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_addr[3] <= mac_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_addr[4] <= mac_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_addr[5] <= mac_addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_addr[6] <= mac_addr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_addr[7] <= mac_addr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_read <= mac_read~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_write <= mac_write~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[0] <= mac_wdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[1] <= mac_wdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[2] <= mac_wdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[3] <= mac_wdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[4] <= mac_wdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[5] <= mac_wdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[6] <= mac_wdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[7] <= mac_wdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[8] <= mac_wdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[9] <= mac_wdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[10] <= mac_wdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[11] <= mac_wdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[12] <= mac_wdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[13] <= mac_wdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[14] <= mac_wdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[15] <= mac_wdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[16] <= mac_wdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[17] <= mac_wdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[18] <= mac_wdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[19] <= mac_wdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[20] <= mac_wdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[21] <= mac_wdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[22] <= mac_wdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[23] <= mac_wdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[24] <= mac_wdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[25] <= mac_wdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[26] <= mac_wdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[27] <= mac_wdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[28] <= mac_wdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[29] <= mac_wdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[30] <= mac_wdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_wdata[31] <= mac_wdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mac_rdata[0] => reg_rdata[0]~reg0.DATAIN
mac_rdata[1] => reg_rdata[1]~reg0.DATAIN
mac_rdata[2] => reg_rdata[2]~reg0.DATAIN
mac_rdata[3] => reg_rdata[3]~reg0.DATAIN
mac_rdata[4] => reg_rdata[4]~reg0.DATAIN
mac_rdata[5] => reg_rdata[5]~reg0.DATAIN
mac_rdata[6] => reg_rdata[6]~reg0.DATAIN
mac_rdata[7] => reg_rdata[7]~reg0.DATAIN
mac_rdata[8] => reg_rdata[8]~reg0.DATAIN
mac_rdata[9] => reg_rdata[9]~reg0.DATAIN
mac_rdata[10] => reg_rdata[10]~reg0.DATAIN
mac_rdata[11] => reg_rdata[11]~reg0.DATAIN
mac_rdata[12] => reg_rdata[12]~reg0.DATAIN
mac_rdata[13] => reg_rdata[13]~reg0.DATAIN
mac_rdata[14] => reg_rdata[14]~reg0.DATAIN
mac_rdata[15] => reg_rdata[15]~reg0.DATAIN
mac_rdata[16] => reg_rdata[16]~reg0.DATAIN
mac_rdata[17] => reg_rdata[17]~reg0.DATAIN
mac_rdata[18] => reg_rdata[18]~reg0.DATAIN
mac_rdata[19] => reg_rdata[19]~reg0.DATAIN
mac_rdata[20] => reg_rdata[20]~reg0.DATAIN
mac_rdata[21] => reg_rdata[21]~reg0.DATAIN
mac_rdata[22] => reg_rdata[22]~reg0.DATAIN
mac_rdata[23] => reg_rdata[23]~reg0.DATAIN
mac_rdata[24] => reg_rdata[24]~reg0.DATAIN
mac_rdata[25] => reg_rdata[25]~reg0.DATAIN
mac_rdata[26] => reg_rdata[26]~reg0.DATAIN
mac_rdata[27] => reg_rdata[27]~reg0.DATAIN
mac_rdata[28] => reg_rdata[28]~reg0.DATAIN
mac_rdata[29] => reg_rdata[29]~reg0.DATAIN
mac_rdata[30] => reg_rdata[30]~reg0.DATAIN
mac_rdata[31] => reg_rdata[31]~reg0.DATAIN
mac_wait => mac_wait_ff0.DATAIN
mac_wait => mac_wait_finish.IN1


|project_top|mac_ip_0002:mac_ip_inst
clk => clk.IN1
reset => reset.IN1
address[0] => address[0].IN1
address[1] => address[1].IN1
address[2] => address[2].IN1
address[3] => address[3].IN1
address[4] => address[4].IN1
address[5] => address[5].IN1
address[6] => address[6].IN1
address[7] => address[7].IN1
readdata[0] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[1] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[2] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[3] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[4] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[5] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[6] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[7] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[8] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[9] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[10] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[11] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[12] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[13] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[14] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[15] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[16] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[17] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[18] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[19] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[20] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[21] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[22] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[23] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[24] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[25] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[26] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[27] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[28] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[29] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[30] <= altera_eth_tse_mac:i_tse_mac.readdata
readdata[31] <= altera_eth_tse_mac:i_tse_mac.readdata
read => read.IN1
writedata[0] => writedata[0].IN1
writedata[1] => writedata[1].IN1
writedata[2] => writedata[2].IN1
writedata[3] => writedata[3].IN1
writedata[4] => writedata[4].IN1
writedata[5] => writedata[5].IN1
writedata[6] => writedata[6].IN1
writedata[7] => writedata[7].IN1
writedata[8] => writedata[8].IN1
writedata[9] => writedata[9].IN1
writedata[10] => writedata[10].IN1
writedata[11] => writedata[11].IN1
writedata[12] => writedata[12].IN1
writedata[13] => writedata[13].IN1
writedata[14] => writedata[14].IN1
writedata[15] => writedata[15].IN1
writedata[16] => writedata[16].IN1
writedata[17] => writedata[17].IN1
writedata[18] => writedata[18].IN1
writedata[19] => writedata[19].IN1
writedata[20] => writedata[20].IN1
writedata[21] => writedata[21].IN1
writedata[22] => writedata[22].IN1
writedata[23] => writedata[23].IN1
writedata[24] => writedata[24].IN1
writedata[25] => writedata[25].IN1
writedata[26] => writedata[26].IN1
writedata[27] => writedata[27].IN1
writedata[28] => writedata[28].IN1
writedata[29] => writedata[29].IN1
writedata[30] => writedata[30].IN1
writedata[31] => writedata[31].IN1
write => write.IN1
waitrequest <= altera_eth_tse_mac:i_tse_mac.waitrequest
tx_clk => tx_clk.IN1
rx_clk => rx_clk.IN1
set_10 => set_10.IN1
set_1000 => set_1000.IN1
eth_mode <= altera_eth_tse_mac:i_tse_mac.eth_mode
ena_10 <= altera_eth_tse_mac:i_tse_mac.ena_10
gm_rx_d[0] => gm_rx_d[0].IN1
gm_rx_d[1] => gm_rx_d[1].IN1
gm_rx_d[2] => gm_rx_d[2].IN1
gm_rx_d[3] => gm_rx_d[3].IN1
gm_rx_d[4] => gm_rx_d[4].IN1
gm_rx_d[5] => gm_rx_d[5].IN1
gm_rx_d[6] => gm_rx_d[6].IN1
gm_rx_d[7] => gm_rx_d[7].IN1
gm_rx_dv => gm_rx_dv.IN1
gm_rx_err => gm_rx_err.IN1
gm_tx_d[0] <= altera_eth_tse_mac:i_tse_mac.gm_tx_d
gm_tx_d[1] <= altera_eth_tse_mac:i_tse_mac.gm_tx_d
gm_tx_d[2] <= altera_eth_tse_mac:i_tse_mac.gm_tx_d
gm_tx_d[3] <= altera_eth_tse_mac:i_tse_mac.gm_tx_d
gm_tx_d[4] <= altera_eth_tse_mac:i_tse_mac.gm_tx_d
gm_tx_d[5] <= altera_eth_tse_mac:i_tse_mac.gm_tx_d
gm_tx_d[6] <= altera_eth_tse_mac:i_tse_mac.gm_tx_d
gm_tx_d[7] <= altera_eth_tse_mac:i_tse_mac.gm_tx_d
gm_tx_en <= altera_eth_tse_mac:i_tse_mac.gm_tx_en
gm_tx_err <= altera_eth_tse_mac:i_tse_mac.gm_tx_err
m_rx_d[0] => m_rx_d[0].IN1
m_rx_d[1] => m_rx_d[1].IN1
m_rx_d[2] => m_rx_d[2].IN1
m_rx_d[3] => m_rx_d[3].IN1
m_rx_en => m_rx_en.IN1
m_rx_err => m_rx_err.IN1
m_tx_d[0] <= altera_eth_tse_mac:i_tse_mac.m_tx_d
m_tx_d[1] <= altera_eth_tse_mac:i_tse_mac.m_tx_d
m_tx_d[2] <= altera_eth_tse_mac:i_tse_mac.m_tx_d
m_tx_d[3] <= altera_eth_tse_mac:i_tse_mac.m_tx_d
m_tx_en <= altera_eth_tse_mac:i_tse_mac.m_tx_en
m_tx_err <= altera_eth_tse_mac:i_tse_mac.m_tx_err
ff_rx_clk => ff_rx_clk.IN1
ff_tx_clk => ff_tx_clk.IN1
ff_rx_data[0] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[1] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[2] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[3] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[4] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[5] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[6] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[7] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[8] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[9] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[10] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[11] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[12] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[13] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[14] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[15] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[16] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[17] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[18] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[19] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[20] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[21] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[22] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[23] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[24] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[25] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[26] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[27] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[28] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[29] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[30] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_data[31] <= altera_eth_tse_mac:i_tse_mac.ff_rx_data
ff_rx_eop <= altera_eth_tse_mac:i_tse_mac.ff_rx_eop
rx_err[0] <= altera_eth_tse_mac:i_tse_mac.rx_err
rx_err[1] <= altera_eth_tse_mac:i_tse_mac.rx_err
rx_err[2] <= altera_eth_tse_mac:i_tse_mac.rx_err
rx_err[3] <= altera_eth_tse_mac:i_tse_mac.rx_err
rx_err[4] <= altera_eth_tse_mac:i_tse_mac.rx_err
rx_err[5] <= altera_eth_tse_mac:i_tse_mac.rx_err
ff_rx_mod[0] <= altera_eth_tse_mac:i_tse_mac.ff_rx_mod
ff_rx_mod[1] <= altera_eth_tse_mac:i_tse_mac.ff_rx_mod
ff_rx_rdy => ff_rx_rdy.IN1
ff_rx_sop <= altera_eth_tse_mac:i_tse_mac.ff_rx_sop
ff_rx_dval <= altera_eth_tse_mac:i_tse_mac.ff_rx_dval
ff_tx_data[0] => ff_tx_data[0].IN1
ff_tx_data[1] => ff_tx_data[1].IN1
ff_tx_data[2] => ff_tx_data[2].IN1
ff_tx_data[3] => ff_tx_data[3].IN1
ff_tx_data[4] => ff_tx_data[4].IN1
ff_tx_data[5] => ff_tx_data[5].IN1
ff_tx_data[6] => ff_tx_data[6].IN1
ff_tx_data[7] => ff_tx_data[7].IN1
ff_tx_data[8] => ff_tx_data[8].IN1
ff_tx_data[9] => ff_tx_data[9].IN1
ff_tx_data[10] => ff_tx_data[10].IN1
ff_tx_data[11] => ff_tx_data[11].IN1
ff_tx_data[12] => ff_tx_data[12].IN1
ff_tx_data[13] => ff_tx_data[13].IN1
ff_tx_data[14] => ff_tx_data[14].IN1
ff_tx_data[15] => ff_tx_data[15].IN1
ff_tx_data[16] => ff_tx_data[16].IN1
ff_tx_data[17] => ff_tx_data[17].IN1
ff_tx_data[18] => ff_tx_data[18].IN1
ff_tx_data[19] => ff_tx_data[19].IN1
ff_tx_data[20] => ff_tx_data[20].IN1
ff_tx_data[21] => ff_tx_data[21].IN1
ff_tx_data[22] => ff_tx_data[22].IN1
ff_tx_data[23] => ff_tx_data[23].IN1
ff_tx_data[24] => ff_tx_data[24].IN1
ff_tx_data[25] => ff_tx_data[25].IN1
ff_tx_data[26] => ff_tx_data[26].IN1
ff_tx_data[27] => ff_tx_data[27].IN1
ff_tx_data[28] => ff_tx_data[28].IN1
ff_tx_data[29] => ff_tx_data[29].IN1
ff_tx_data[30] => ff_tx_data[30].IN1
ff_tx_data[31] => ff_tx_data[31].IN1
ff_tx_eop => ff_tx_eop.IN1
ff_tx_err => ff_tx_err.IN1
ff_tx_mod[0] => ff_tx_mod[0].IN1
ff_tx_mod[1] => ff_tx_mod[1].IN1
ff_tx_rdy <= altera_eth_tse_mac:i_tse_mac.ff_tx_rdy
ff_tx_sop => ff_tx_sop.IN1
ff_tx_wren => ff_tx_wren.IN1
mdc <= altera_eth_tse_mac:i_tse_mac.mdc
mdio_in => mdio_in.IN1
mdio_out <= altera_eth_tse_mac:i_tse_mac.mdio_out
mdio_oen <= altera_eth_tse_mac:i_tse_mac.mdio_oen
xon_gen => xon_gen.IN1
xoff_gen => xoff_gen.IN1
magic_wakeup <= altera_eth_tse_mac:i_tse_mac.magic_wakeup
magic_sleep_n => magic_sleep_n.IN1
ff_tx_crc_fwd => ff_tx_crc_fwd.IN1
ff_tx_septy <= altera_eth_tse_mac:i_tse_mac.ff_tx_septy
tx_ff_uflow <= altera_eth_tse_mac:i_tse_mac.tx_ff_uflow
ff_tx_a_full <= altera_eth_tse_mac:i_tse_mac.ff_tx_a_full
ff_tx_a_empty <= altera_eth_tse_mac:i_tse_mac.ff_tx_a_empty
rx_err_stat[0] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[1] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[2] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[3] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[4] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[5] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[6] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[7] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[8] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[9] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[10] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[11] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[12] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[13] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[14] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[15] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[16] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_err_stat[17] <= altera_eth_tse_mac:i_tse_mac.rx_err_stat
rx_frm_type[0] <= altera_eth_tse_mac:i_tse_mac.rx_frm_type
rx_frm_type[1] <= altera_eth_tse_mac:i_tse_mac.rx_frm_type
rx_frm_type[2] <= altera_eth_tse_mac:i_tse_mac.rx_frm_type
rx_frm_type[3] <= altera_eth_tse_mac:i_tse_mac.rx_frm_type
ff_rx_dsav <= altera_eth_tse_mac:i_tse_mac.ff_rx_dsav
ff_rx_a_full <= altera_eth_tse_mac:i_tse_mac.ff_rx_a_full
ff_rx_a_empty <= altera_eth_tse_mac:i_tse_mac.ff_rx_a_empty


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac
reset => reset.IN5
rx_clk => rx_clk.IN3
tx_clk => tx_clk.IN3
rx_clkena => rx_clkena.IN1
tx_clkena => tx_clkena.IN1
gm_rx_d[0] => gm_rx_d[0].IN1
gm_rx_d[1] => gm_rx_d[1].IN1
gm_rx_d[2] => gm_rx_d[2].IN1
gm_rx_d[3] => gm_rx_d[3].IN1
gm_rx_d[4] => gm_rx_d[4].IN1
gm_rx_d[5] => gm_rx_d[5].IN1
gm_rx_d[6] => gm_rx_d[6].IN1
gm_rx_d[7] => gm_rx_d[7].IN1
gm_rx_dv => gm_rx_dv.IN1
gm_rx_err => gm_rx_err.IN1
gm_tx_d[0] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.gm_tx_d
gm_tx_d[1] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.gm_tx_d
gm_tx_d[2] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.gm_tx_d
gm_tx_d[3] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.gm_tx_d
gm_tx_d[4] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.gm_tx_d
gm_tx_d[5] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.gm_tx_d
gm_tx_d[6] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.gm_tx_d
gm_tx_d[7] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.gm_tx_d
gm_tx_en <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.gm_tx_en
gm_tx_err <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.gm_tx_err
m_rx_crs => m_rx_crs.IN1
m_rx_col => m_rx_col.IN1
m_rx_d[0] => m_rx_d[0].IN1
m_rx_d[1] => m_rx_d[1].IN1
m_rx_d[2] => m_rx_d[2].IN1
m_rx_d[3] => m_rx_d[3].IN1
m_rx_en => m_rx_en.IN1
m_rx_err => m_rx_err.IN1
m_tx_d[0] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.m_tx_d
m_tx_d[1] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.m_tx_d
m_tx_d[2] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.m_tx_d
m_tx_d[3] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.m_tx_d
m_tx_en <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.m_tx_en
m_tx_err <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.m_tx_err
rx_control => ~NO_FANOUT~
rgmii_in[0] => ~NO_FANOUT~
rgmii_in[1] => ~NO_FANOUT~
rgmii_in[2] => ~NO_FANOUT~
rgmii_in[3] => ~NO_FANOUT~
tx_control <= <GND>
rgmii_out[0] <= <GND>
rgmii_out[1] <= <GND>
rgmii_out[2] <= <GND>
rgmii_out[3] <= <GND>
eth_mode <= altera_tse_mac_control:U_MAC_CONTROL.eth_mode
ena_10 <= altera_tse_mac_control:U_MAC_CONTROL.ena_10
set_10 => set_10.IN1
set_1000 => set_1000.IN1
ff_rx_clk => ff_rx_clk.IN2
ff_rx_data[0] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[1] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[2] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[3] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[4] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[5] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[6] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[7] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[8] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[9] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[10] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[11] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[12] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[13] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[14] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[15] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[16] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[17] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[18] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[19] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[20] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[21] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[22] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[23] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[24] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[25] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[26] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[27] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[28] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[29] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[30] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_data[31] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_data
ff_rx_mod[0] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_mod
ff_rx_mod[1] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_mod
ff_rx_sop <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_sop
ff_rx_eop <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_eop
rx_err[0] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err
rx_err[1] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err[2] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err[3] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err[4] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err[5] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[0] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[1] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[2] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[3] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[4] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[5] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[6] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[7] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[8] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[9] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[10] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[11] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[12] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[13] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[14] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[15] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[16] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_err_stat[17] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_err_stat
rx_frm_type[0] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_ucast
rx_frm_type[1] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_mcast
rx_frm_type[2] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_bcast
rx_frm_type[3] <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_vlan
ff_rx_rdy => ff_rx_rdy_int.IN1
ff_rx_dval <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_dval
ff_rx_dsav <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_rx_dsav
ff_rx_a_full <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.rx_a_full
ff_rx_a_empty <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.rx_a_empty
ff_tx_clk => ff_tx_clk.IN2
ff_tx_data[0] => ff_tx_data[0].IN1
ff_tx_data[1] => ff_tx_data[1].IN1
ff_tx_data[2] => ff_tx_data[2].IN1
ff_tx_data[3] => ff_tx_data[3].IN1
ff_tx_data[4] => ff_tx_data[4].IN1
ff_tx_data[5] => ff_tx_data[5].IN1
ff_tx_data[6] => ff_tx_data[6].IN1
ff_tx_data[7] => ff_tx_data[7].IN1
ff_tx_data[8] => ff_tx_data[8].IN1
ff_tx_data[9] => ff_tx_data[9].IN1
ff_tx_data[10] => ff_tx_data[10].IN1
ff_tx_data[11] => ff_tx_data[11].IN1
ff_tx_data[12] => ff_tx_data[12].IN1
ff_tx_data[13] => ff_tx_data[13].IN1
ff_tx_data[14] => ff_tx_data[14].IN1
ff_tx_data[15] => ff_tx_data[15].IN1
ff_tx_data[16] => ff_tx_data[16].IN1
ff_tx_data[17] => ff_tx_data[17].IN1
ff_tx_data[18] => ff_tx_data[18].IN1
ff_tx_data[19] => ff_tx_data[19].IN1
ff_tx_data[20] => ff_tx_data[20].IN1
ff_tx_data[21] => ff_tx_data[21].IN1
ff_tx_data[22] => ff_tx_data[22].IN1
ff_tx_data[23] => ff_tx_data[23].IN1
ff_tx_data[24] => ff_tx_data[24].IN1
ff_tx_data[25] => ff_tx_data[25].IN1
ff_tx_data[26] => ff_tx_data[26].IN1
ff_tx_data[27] => ff_tx_data[27].IN1
ff_tx_data[28] => ff_tx_data[28].IN1
ff_tx_data[29] => ff_tx_data[29].IN1
ff_tx_data[30] => ff_tx_data[30].IN1
ff_tx_data[31] => ff_tx_data[31].IN1
ff_tx_mod[0] => ff_tx_mod_int[0].IN1
ff_tx_mod[1] => ff_tx_mod_int[1].IN1
ff_tx_sop => ff_tx_sop.IN1
ff_tx_eop => ff_tx_eop.IN1
ff_tx_err => ff_tx_err.IN1
ff_tx_wren => ff_tx_wren.IN1
ff_tx_crc_fwd => ff_tx_crc_fwd.IN1
ff_tx_rdy <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_tx_rdy
ff_tx_septy <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.ff_tx_septy
tx_ff_uflow <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.tx_ff_uflow
ff_tx_a_full <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.tx_a_full
ff_tx_a_empty <= altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP.tx_a_empty
xoff_gen => ~NO_FANOUT~
xon_gen => ~NO_FANOUT~
mdc <= altera_tse_top_mdio:U_MDIO.mdc
mdio_in => mdio_in.IN1
mdio_out <= altera_tse_top_mdio:U_MDIO.mdio_out
mdio_oen <= altera_tse_top_mdio:U_MDIO.mdio_oen
clk => reg_clk.IN4
read => reg_rd.IN1
write => reg_wr.IN1
address[0] => reg_addr[2].IN1
address[1] => reg_addr[3].IN1
address[2] => reg_addr[4].IN1
address[3] => reg_addr[5].IN1
address[4] => reg_addr[6].IN1
address[5] => reg_addr[7].IN1
address[6] => reg_addr[8].IN1
address[7] => reg_addr[9].IN1
writedata[0] => reg_data_in[0].IN1
writedata[1] => reg_data_in[1].IN1
writedata[2] => reg_data_in[2].IN1
writedata[3] => reg_data_in[3].IN1
writedata[4] => reg_data_in[4].IN1
writedata[5] => reg_data_in[5].IN1
writedata[6] => reg_data_in[6].IN1
writedata[7] => reg_data_in[7].IN1
writedata[8] => reg_data_in[8].IN1
writedata[9] => reg_data_in[9].IN1
writedata[10] => reg_data_in[10].IN1
writedata[11] => reg_data_in[11].IN1
writedata[12] => reg_data_in[12].IN1
writedata[13] => reg_data_in[13].IN1
writedata[14] => reg_data_in[14].IN1
writedata[15] => reg_data_in[15].IN1
writedata[16] => reg_data_in[16].IN1
writedata[17] => reg_data_in[17].IN1
writedata[18] => reg_data_in[18].IN1
writedata[19] => reg_data_in[19].IN1
writedata[20] => reg_data_in[20].IN1
writedata[21] => reg_data_in[21].IN1
writedata[22] => reg_data_in[22].IN1
writedata[23] => reg_data_in[23].IN1
writedata[24] => reg_data_in[24].IN1
writedata[25] => reg_data_in[25].IN1
writedata[26] => reg_data_in[26].IN1
writedata[27] => reg_data_in[27].IN1
writedata[28] => reg_data_in[28].IN1
writedata[29] => reg_data_in[29].IN1
writedata[30] => reg_data_in[30].IN1
writedata[31] => reg_data_in[31].IN1
readdata[0] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[1] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[2] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[3] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[4] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[5] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[6] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[7] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[8] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[9] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[10] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[11] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[12] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[13] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[14] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[15] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[16] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[17] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[18] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[19] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[20] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[21] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[22] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[23] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[24] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[25] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[26] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[27] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[28] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[29] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[30] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
readdata[31] <= altera_tse_mac_control:U_MAC_CONTROL.data_out
waitrequest <= altera_tse_mac_control:U_MAC_CONTROL.busy
magic_sleep_n => magic_sleep_n.IN1
magic_wakeup <= altera_tse_mac_control:U_MAC_CONTROL.reg_wakeup


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_0
reset_in => altera_tse_reset_synchronizer_chain_out.PRESET
reset_in => altera_tse_reset_synchronizer_chain[0].PRESET
reset_in => altera_tse_reset_synchronizer_chain[1].PRESET
clk => altera_tse_reset_synchronizer_chain_out.CLK
clk => altera_tse_reset_synchronizer_chain[0].CLK
clk => altera_tse_reset_synchronizer_chain[1].CLK
reset_out <= altera_tse_reset_synchronizer_chain_out.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_1
reset_in => altera_tse_reset_synchronizer_chain_out.PRESET
reset_in => altera_tse_reset_synchronizer_chain[0].PRESET
reset_in => altera_tse_reset_synchronizer_chain[1].PRESET
clk => altera_tse_reset_synchronizer_chain_out.CLK
clk => altera_tse_reset_synchronizer_chain[0].CLK
clk => altera_tse_reset_synchronizer_chain[1].CLK
reset_out <= altera_tse_reset_synchronizer_chain_out.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_2
reset_in => altera_tse_reset_synchronizer_chain_out.PRESET
reset_in => altera_tse_reset_synchronizer_chain[0].PRESET
reset_in => altera_tse_reset_synchronizer_chain[1].PRESET
clk => altera_tse_reset_synchronizer_chain_out.CLK
clk => altera_tse_reset_synchronizer_chain[0].CLK
clk => altera_tse_reset_synchronizer_chain[1].CLK
reset_out <= altera_tse_reset_synchronizer_chain_out.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_3
reset_in => altera_tse_reset_synchronizer_chain_out.PRESET
reset_in => altera_tse_reset_synchronizer_chain[0].PRESET
reset_in => altera_tse_reset_synchronizer_chain[1].PRESET
clk => altera_tse_reset_synchronizer_chain_out.CLK
clk => altera_tse_reset_synchronizer_chain[0].CLK
clk => altera_tse_reset_synchronizer_chain[1].CLK
reset_out <= altera_tse_reset_synchronizer_chain_out.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_4
reset_in => altera_tse_reset_synchronizer_chain_out.PRESET
reset_in => altera_tse_reset_synchronizer_chain[0].PRESET
reset_in => altera_tse_reset_synchronizer_chain[1].PRESET
clk => altera_tse_reset_synchronizer_chain_out.CLK
clk => altera_tse_reset_synchronizer_chain[0].CLK
clk => altera_tse_reset_synchronizer_chain[1].CLK
reset_out <= altera_tse_reset_synchronizer_chain_out.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL
rx_clk => rx_clk.IN2
tx_clk => tx_clk.IN1
reset_rx_clk => reset_rx_clk.IN2
reset_tx_clk => reset_tx_clk.IN1
reset_reg_clk => reset_reg_clk.IN2
reg_clk => reg_clk.IN2
cs => cs.IN1
rd => rd.IN1
wr => wr.IN1
sel[0] => sel[0].IN1
sel[1] => sel[1].IN1
sel[2] => sel[2].IN1
sel[3] => sel[3].IN1
sel[4] => sel[4].IN1
sel[5] => sel[5].IN1
sel[6] => sel[6].IN1
sel[7] => sel[7].IN1
data_in[0] => data_in[0].IN1
data_in[1] => data_in[1].IN1
data_in[2] => data_in[2].IN1
data_in[3] => data_in[3].IN1
data_in[4] => data_in[4].IN1
data_in[5] => data_in[5].IN1
data_in[6] => data_in[6].IN1
data_in[7] => data_in[7].IN1
data_in[8] => data_in[8].IN1
data_in[9] => data_in[9].IN1
data_in[10] => data_in[10].IN1
data_in[11] => data_in[11].IN1
data_in[12] => data_in[12].IN1
data_in[13] => data_in[13].IN1
data_in[14] => data_in[14].IN1
data_in[15] => data_in[15].IN1
data_in[16] => data_in[16].IN1
data_in[17] => data_in[17].IN1
data_in[18] => data_in[18].IN1
data_in[19] => data_in[19].IN1
data_in[20] => data_in[20].IN1
data_in[21] => data_in[21].IN1
data_in[22] => data_in[22].IN1
data_in[23] => data_in[23].IN1
data_in[24] => data_in[24].IN1
data_in[25] => data_in[25].IN1
data_in[26] => data_in[26].IN1
data_in[27] => data_in[27].IN1
data_in[28] => data_in[28].IN1
data_in[29] => data_in[29].IN1
data_in[30] => data_in[30].IN1
data_in[31] => data_in[31].IN1
data_out[0] <= altera_tse_host_control:U_CTRL.data_out
data_out[1] <= altera_tse_host_control:U_CTRL.data_out
data_out[2] <= altera_tse_host_control:U_CTRL.data_out
data_out[3] <= altera_tse_host_control:U_CTRL.data_out
data_out[4] <= altera_tse_host_control:U_CTRL.data_out
data_out[5] <= altera_tse_host_control:U_CTRL.data_out
data_out[6] <= altera_tse_host_control:U_CTRL.data_out
data_out[7] <= altera_tse_host_control:U_CTRL.data_out
data_out[8] <= altera_tse_host_control:U_CTRL.data_out
data_out[9] <= altera_tse_host_control:U_CTRL.data_out
data_out[10] <= altera_tse_host_control:U_CTRL.data_out
data_out[11] <= altera_tse_host_control:U_CTRL.data_out
data_out[12] <= altera_tse_host_control:U_CTRL.data_out
data_out[13] <= altera_tse_host_control:U_CTRL.data_out
data_out[14] <= altera_tse_host_control:U_CTRL.data_out
data_out[15] <= altera_tse_host_control:U_CTRL.data_out
data_out[16] <= altera_tse_host_control:U_CTRL.data_out
data_out[17] <= altera_tse_host_control:U_CTRL.data_out
data_out[18] <= altera_tse_host_control:U_CTRL.data_out
data_out[19] <= altera_tse_host_control:U_CTRL.data_out
data_out[20] <= altera_tse_host_control:U_CTRL.data_out
data_out[21] <= altera_tse_host_control:U_CTRL.data_out
data_out[22] <= altera_tse_host_control:U_CTRL.data_out
data_out[23] <= altera_tse_host_control:U_CTRL.data_out
data_out[24] <= altera_tse_host_control:U_CTRL.data_out
data_out[25] <= altera_tse_host_control:U_CTRL.data_out
data_out[26] <= altera_tse_host_control:U_CTRL.data_out
data_out[27] <= altera_tse_host_control:U_CTRL.data_out
data_out[28] <= altera_tse_host_control:U_CTRL.data_out
data_out[29] <= altera_tse_host_control:U_CTRL.data_out
data_out[30] <= altera_tse_host_control:U_CTRL.data_out
data_out[31] <= altera_tse_host_control:U_CTRL.data_out
busy <= altera_tse_host_control:U_CTRL.busy
rx_section_empty[0] <= altera_tse_register_map:U_REG.rx_section_empty
rx_section_empty[1] <= altera_tse_register_map:U_REG.rx_section_empty
rx_section_empty[2] <= altera_tse_register_map:U_REG.rx_section_empty
rx_section_empty[3] <= altera_tse_register_map:U_REG.rx_section_empty
rx_section_empty[4] <= altera_tse_register_map:U_REG.rx_section_empty
rx_section_empty[5] <= altera_tse_register_map:U_REG.rx_section_empty
rx_section_empty[6] <= altera_tse_register_map:U_REG.rx_section_empty
rx_section_empty[7] <= altera_tse_register_map:U_REG.rx_section_empty
rx_section_empty[8] <= altera_tse_register_map:U_REG.rx_section_empty
rx_section_empty[9] <= altera_tse_register_map:U_REG.rx_section_empty
rx_section_empty[10] <= altera_tse_register_map:U_REG.rx_section_empty
rx_section_full[0] <= altera_tse_register_map:U_REG.rx_section_full
rx_section_full[1] <= altera_tse_register_map:U_REG.rx_section_full
rx_section_full[2] <= altera_tse_register_map:U_REG.rx_section_full
rx_section_full[3] <= altera_tse_register_map:U_REG.rx_section_full
rx_section_full[4] <= altera_tse_register_map:U_REG.rx_section_full
rx_section_full[5] <= altera_tse_register_map:U_REG.rx_section_full
rx_section_full[6] <= altera_tse_register_map:U_REG.rx_section_full
rx_section_full[7] <= altera_tse_register_map:U_REG.rx_section_full
rx_section_full[8] <= altera_tse_register_map:U_REG.rx_section_full
rx_section_full[9] <= altera_tse_register_map:U_REG.rx_section_full
rx_section_full[10] <= altera_tse_register_map:U_REG.rx_section_full
tx_section_empty[0] <= altera_tse_register_map:U_REG.tx_section_empty
tx_section_empty[1] <= altera_tse_register_map:U_REG.tx_section_empty
tx_section_empty[2] <= altera_tse_register_map:U_REG.tx_section_empty
tx_section_empty[3] <= altera_tse_register_map:U_REG.tx_section_empty
tx_section_empty[4] <= altera_tse_register_map:U_REG.tx_section_empty
tx_section_empty[5] <= altera_tse_register_map:U_REG.tx_section_empty
tx_section_empty[6] <= altera_tse_register_map:U_REG.tx_section_empty
tx_section_empty[7] <= altera_tse_register_map:U_REG.tx_section_empty
tx_section_empty[8] <= altera_tse_register_map:U_REG.tx_section_empty
tx_section_empty[9] <= altera_tse_register_map:U_REG.tx_section_empty
tx_section_empty[10] <= altera_tse_register_map:U_REG.tx_section_empty
tx_section_full[0] <= altera_tse_register_map:U_REG.tx_section_full
tx_section_full[1] <= altera_tse_register_map:U_REG.tx_section_full
tx_section_full[2] <= altera_tse_register_map:U_REG.tx_section_full
tx_section_full[3] <= altera_tse_register_map:U_REG.tx_section_full
tx_section_full[4] <= altera_tse_register_map:U_REG.tx_section_full
tx_section_full[5] <= altera_tse_register_map:U_REG.tx_section_full
tx_section_full[6] <= altera_tse_register_map:U_REG.tx_section_full
tx_section_full[7] <= altera_tse_register_map:U_REG.tx_section_full
tx_section_full[8] <= altera_tse_register_map:U_REG.tx_section_full
tx_section_full[9] <= altera_tse_register_map:U_REG.tx_section_full
tx_section_full[10] <= altera_tse_register_map:U_REG.tx_section_full
rx_ae_level[0] <= altera_tse_register_map:U_REG.rx_ae_level
rx_ae_level[1] <= altera_tse_register_map:U_REG.rx_ae_level
rx_ae_level[2] <= altera_tse_register_map:U_REG.rx_ae_level
rx_ae_level[3] <= altera_tse_register_map:U_REG.rx_ae_level
rx_ae_level[4] <= altera_tse_register_map:U_REG.rx_ae_level
rx_ae_level[5] <= altera_tse_register_map:U_REG.rx_ae_level
rx_ae_level[6] <= altera_tse_register_map:U_REG.rx_ae_level
rx_ae_level[7] <= altera_tse_register_map:U_REG.rx_ae_level
rx_ae_level[8] <= altera_tse_register_map:U_REG.rx_ae_level
rx_ae_level[9] <= altera_tse_register_map:U_REG.rx_ae_level
rx_ae_level[10] <= altera_tse_register_map:U_REG.rx_ae_level
rx_af_level[0] <= altera_tse_register_map:U_REG.rx_af_level
rx_af_level[1] <= altera_tse_register_map:U_REG.rx_af_level
rx_af_level[2] <= altera_tse_register_map:U_REG.rx_af_level
rx_af_level[3] <= altera_tse_register_map:U_REG.rx_af_level
rx_af_level[4] <= altera_tse_register_map:U_REG.rx_af_level
rx_af_level[5] <= altera_tse_register_map:U_REG.rx_af_level
rx_af_level[6] <= altera_tse_register_map:U_REG.rx_af_level
rx_af_level[7] <= altera_tse_register_map:U_REG.rx_af_level
rx_af_level[8] <= altera_tse_register_map:U_REG.rx_af_level
rx_af_level[9] <= altera_tse_register_map:U_REG.rx_af_level
rx_af_level[10] <= altera_tse_register_map:U_REG.rx_af_level
tx_ae_level[0] <= altera_tse_register_map:U_REG.tx_ae_level
tx_ae_level[1] <= altera_tse_register_map:U_REG.tx_ae_level
tx_ae_level[2] <= altera_tse_register_map:U_REG.tx_ae_level
tx_ae_level[3] <= altera_tse_register_map:U_REG.tx_ae_level
tx_ae_level[4] <= altera_tse_register_map:U_REG.tx_ae_level
tx_ae_level[5] <= altera_tse_register_map:U_REG.tx_ae_level
tx_ae_level[6] <= altera_tse_register_map:U_REG.tx_ae_level
tx_ae_level[7] <= altera_tse_register_map:U_REG.tx_ae_level
tx_ae_level[8] <= altera_tse_register_map:U_REG.tx_ae_level
tx_ae_level[9] <= altera_tse_register_map:U_REG.tx_ae_level
tx_ae_level[10] <= altera_tse_register_map:U_REG.tx_ae_level
tx_af_level[0] <= altera_tse_register_map:U_REG.tx_af_level
tx_af_level[1] <= altera_tse_register_map:U_REG.tx_af_level
tx_af_level[2] <= altera_tse_register_map:U_REG.tx_af_level
tx_af_level[3] <= altera_tse_register_map:U_REG.tx_af_level
tx_af_level[4] <= altera_tse_register_map:U_REG.tx_af_level
tx_af_level[5] <= altera_tse_register_map:U_REG.tx_af_level
tx_af_level[6] <= altera_tse_register_map:U_REG.tx_af_level
tx_af_level[7] <= altera_tse_register_map:U_REG.tx_af_level
tx_af_level[8] <= altera_tse_register_map:U_REG.tx_af_level
tx_af_level[9] <= altera_tse_register_map:U_REG.tx_af_level
tx_af_level[10] <= altera_tse_register_map:U_REG.tx_af_level
excess_col => excess_col.IN1
late_col => late_col.IN1
mac_addr[0] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[1] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[2] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[3] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[4] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[5] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[6] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[7] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[8] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[9] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[10] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[11] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[12] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[13] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[14] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[15] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[16] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[17] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[18] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[19] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[20] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[21] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[22] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[23] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[24] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[25] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[26] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[27] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[28] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[29] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[30] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[31] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[32] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[33] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[34] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[35] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[36] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[37] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[38] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[39] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[40] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[41] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[42] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[43] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[44] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[45] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[46] <= altera_tse_register_map:U_REG.mac_addr
mac_addr[47] <= altera_tse_register_map:U_REG.mac_addr
pause_quant[0] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[1] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[2] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[3] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[4] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[5] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[6] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[7] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[8] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[9] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[10] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[11] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[12] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[13] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[14] <= altera_tse_register_map:U_REG.pause_quant
pause_quant[15] <= altera_tse_register_map:U_REG.pause_quant
holdoff_quant[0] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[1] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[2] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[3] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[4] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[5] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[6] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[7] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[8] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[9] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[10] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[11] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[12] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[13] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[14] <= altera_tse_register_map:U_REG.holdoff_quant
holdoff_quant[15] <= altera_tse_register_map:U_REG.holdoff_quant
promis_en <= altera_tse_register_map:U_REG.promis_en
frm_length_max[0] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[1] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[2] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[3] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[4] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[5] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[6] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[7] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[8] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[9] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[10] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[11] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[12] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[13] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[14] <= altera_tse_register_map:U_REG.frm_length_max
frm_length_max[15] <= altera_tse_register_map:U_REG.frm_length_max
pause_fwd <= altera_tse_register_map:U_REG.pause_fwd
pause_ignore <= altera_tse_register_map:U_REG.pause_ignore
pad_ena <= altera_tse_register_map:U_REG.pad_ena
ethernet_mode <= altera_tse_register_map:U_REG.ethernet_mode
eth_mode <= altera_tse_register_map:U_REG.eth_mode
set_1000 => set_1000.IN1
set_10 => set_10.IN1
enable_tx <= altera_tse_register_map:U_REG.enable_tx
enable_rx <= altera_tse_register_map:U_REG.enable_rx
hd_ena <= altera_tse_register_map:U_REG.hd_ena
tx_addr_ins <= altera_tse_register_map:U_REG.tx_addr_ins
crc_fwd <= altera_tse_register_map:U_REG.crc_fwd
sw_reset <= altera_tse_register_map:U_REG.sw_reset
tx_done => tx_done.IN1
mhash_sel <= altera_tse_register_map:U_REG.mhash_sel
cmd_frm_ena <= altera_tse_register_map:U_REG.cmd_frm_ena
no_lgth_check <= altera_tse_register_map:U_REG.no_lgth_check
ena_10 <= altera_tse_register_map:U_REG.ena_10
rx_err_frm_disc <= altera_tse_register_map:U_REG.rx_err_frm_disc
tx_ipg_len[0] <= altera_tse_register_map:U_REG.tx_ipg_len
tx_ipg_len[1] <= altera_tse_register_map:U_REG.tx_ipg_len
tx_ipg_len[2] <= altera_tse_register_map:U_REG.tx_ipg_len
tx_ipg_len[3] <= altera_tse_register_map:U_REG.tx_ipg_len
tx_ipg_len[4] <= altera_tse_register_map:U_REG.tx_ipg_len
rx_reset_done => rx_reset_done.IN1
magic_ena <= altera_tse_register_map:U_REG.magic_ena
magic_detect => magic_detect.IN1
sleep_ena <= altera_tse_register_map:U_REG.sleep_ena
reg_sleepn => reg_sleepn.IN1
reg_wakeup <= altera_tse_register_map:U_REG.reg_wakeup
xoff_gen <= altera_tse_register_map:U_REG.xoff_gen
xon_gen <= altera_tse_register_map:U_REG.xon_gen
tx_crc_fwd_out <= altera_tse_register_map:U_REG.tx_crc_fwd_out
tx_shift16 <= altera_tse_register_map:U_REG.tx_shift16
rx_shift16 <= altera_tse_register_map:U_REG.rx_shift16
lut_wren <= altera_tse_register_map:U_REG.lut_wren
lut_wdata <= altera_tse_register_map:U_REG.lut_wdata
lut_waddr[0] <= altera_tse_register_map:U_REG.lut_waddr
lut_waddr[1] <= altera_tse_register_map:U_REG.lut_waddr
lut_waddr[2] <= altera_tse_register_map:U_REG.lut_waddr
lut_waddr[3] <= altera_tse_register_map:U_REG.lut_waddr
lut_waddr[4] <= altera_tse_register_map:U_REG.lut_waddr
lut_waddr[5] <= altera_tse_register_map:U_REG.lut_waddr
mdio_data_in[0] => mdio_data_in[0].IN1
mdio_data_in[1] => mdio_data_in[1].IN1
mdio_data_in[2] => mdio_data_in[2].IN1
mdio_data_in[3] => mdio_data_in[3].IN1
mdio_data_in[4] => mdio_data_in[4].IN1
mdio_data_in[5] => mdio_data_in[5].IN1
mdio_data_in[6] => mdio_data_in[6].IN1
mdio_data_in[7] => mdio_data_in[7].IN1
mdio_data_in[8] => mdio_data_in[8].IN1
mdio_data_in[9] => mdio_data_in[9].IN1
mdio_data_in[10] => mdio_data_in[10].IN1
mdio_data_in[11] => mdio_data_in[11].IN1
mdio_data_in[12] => mdio_data_in[12].IN1
mdio_data_in[13] => mdio_data_in[13].IN1
mdio_data_in[14] => mdio_data_in[14].IN1
mdio_data_in[15] => mdio_data_in[15].IN1
mdio_data_out[0] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[1] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[2] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[3] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[4] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[5] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[6] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[7] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[8] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[9] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[10] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[11] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[12] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[13] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[14] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_data_out[15] <= altera_tse_register_map:U_REG.mdio_data_out
mdio_dev_addr[0] <= altera_tse_register_map:U_REG.mdio_dev_addr
mdio_dev_addr[1] <= altera_tse_register_map:U_REG.mdio_dev_addr
mdio_dev_addr[2] <= altera_tse_register_map:U_REG.mdio_dev_addr
mdio_dev_addr[3] <= altera_tse_register_map:U_REG.mdio_dev_addr
mdio_dev_addr[4] <= altera_tse_register_map:U_REG.mdio_dev_addr
mdio_addr[0] <= altera_tse_register_map:U_REG.mdio_addr
mdio_addr[1] <= altera_tse_register_map:U_REG.mdio_addr
mdio_addr[2] <= altera_tse_register_map:U_REG.mdio_addr
mdio_addr[3] <= altera_tse_register_map:U_REG.mdio_addr
mdio_addr[4] <= altera_tse_register_map:U_REG.mdio_addr
mdio_cs <= altera_tse_register_map:U_REG.mdio_cs
mdio_rd <= altera_tse_register_map:U_REG.mdio_rd
mdio_wr <= altera_tse_register_map:U_REG.mdio_wr
mdio_busy => mdio_busy.IN1
pause_rcv => pause_rcv.IN1
pause_tx => pause_tx.IN1
frm_align_err => frm_align_err.IN1
frm_crc_err => frm_crc_err.IN1
long_crc_err => long_crc_err.IN1
short_crc_err => short_crc_err.IN1
frm_discard => frm_discard.IN1
rx_total_lgth[0] => rx_total_lgth[0].IN1
rx_total_lgth[1] => rx_total_lgth[1].IN1
rx_total_lgth[2] => rx_total_lgth[2].IN1
rx_total_lgth[3] => rx_total_lgth[3].IN1
rx_total_lgth[4] => rx_total_lgth[4].IN1
rx_total_lgth[5] => rx_total_lgth[5].IN1
rx_total_lgth[6] => rx_total_lgth[6].IN1
rx_total_lgth[7] => rx_total_lgth[7].IN1
rx_total_lgth[8] => rx_total_lgth[8].IN1
rx_total_lgth[9] => rx_total_lgth[9].IN1
rx_total_lgth[10] => rx_total_lgth[10].IN1
rx_total_lgth[11] => rx_total_lgth[11].IN1
rx_total_lgth[12] => rx_total_lgth[12].IN1
rx_total_lgth[13] => rx_total_lgth[13].IN1
rx_total_lgth[14] => rx_total_lgth[14].IN1
rx_total_lgth[15] => rx_total_lgth[15].IN1
rx_total_val => rx_total_val.IN1
rx_frm_stat_ena => rx_frm_stat_ena.IN1
rx_frm_stat_val => rx_frm_stat_val.IN1
rx_frm_err => rx_frm_err.IN1
rx_frm_crc_err => rx_frm_crc_err.IN1
rx_frm_length[0] => rx_frm_length[0].IN1
rx_frm_length[1] => rx_frm_length[1].IN1
rx_frm_length[2] => rx_frm_length[2].IN1
rx_frm_length[3] => rx_frm_length[3].IN1
rx_frm_length[4] => rx_frm_length[4].IN1
rx_frm_length[5] => rx_frm_length[5].IN1
rx_frm_length[6] => rx_frm_length[6].IN1
rx_frm_length[7] => rx_frm_length[7].IN1
rx_frm_length[8] => rx_frm_length[8].IN1
rx_frm_length[9] => rx_frm_length[9].IN1
rx_frm_length[10] => rx_frm_length[10].IN1
rx_frm_length[11] => rx_frm_length[11].IN1
rx_frm_length[12] => rx_frm_length[12].IN1
rx_frm_length[13] => rx_frm_length[13].IN1
rx_frm_length[14] => rx_frm_length[14].IN1
rx_frm_length[15] => rx_frm_length[15].IN1
rx_frm_vlan => rx_frm_vlan.IN1
rx_frm_stack_vlan => rx_frm_stack_vlan.IN1
rx_frm_unicast => rx_frm_unicast.IN1
rx_frm_broadcast => rx_frm_broadcast.IN1
rx_frm_mltcast => rx_frm_mltcast.IN1
tx_frm_stat_val => tx_frm_stat_val.IN1
tx_frm_err => tx_frm_err.IN1
tx_frm_length[0] => tx_frm_length[0].IN1
tx_frm_length[1] => tx_frm_length[1].IN1
tx_frm_length[2] => tx_frm_length[2].IN1
tx_frm_length[3] => tx_frm_length[3].IN1
tx_frm_length[4] => tx_frm_length[4].IN1
tx_frm_length[5] => tx_frm_length[5].IN1
tx_frm_length[6] => tx_frm_length[6].IN1
tx_frm_length[7] => tx_frm_length[7].IN1
tx_frm_length[8] => tx_frm_length[8].IN1
tx_frm_length[9] => tx_frm_length[9].IN1
tx_frm_length[10] => tx_frm_length[10].IN1
tx_frm_length[11] => tx_frm_length[11].IN1
tx_frm_length[12] => tx_frm_length[12].IN1
tx_frm_length[13] => tx_frm_length[13].IN1
tx_frm_length[14] => tx_frm_length[14].IN1
tx_frm_length[15] => tx_frm_length[15].IN1
tx_frm_unicast => tx_frm_unicast.IN1
tx_frm_broadcast => tx_frm_broadcast.IN1
tx_frm_mltcast => tx_frm_mltcast.IN1
gmii_loopback <= altera_tse_register_map:U_REG.gmii_loopback
smac_0[0] <= altera_tse_register_map:U_REG.smac_0
smac_0[1] <= altera_tse_register_map:U_REG.smac_0
smac_0[2] <= altera_tse_register_map:U_REG.smac_0
smac_0[3] <= altera_tse_register_map:U_REG.smac_0
smac_0[4] <= altera_tse_register_map:U_REG.smac_0
smac_0[5] <= altera_tse_register_map:U_REG.smac_0
smac_0[6] <= altera_tse_register_map:U_REG.smac_0
smac_0[7] <= altera_tse_register_map:U_REG.smac_0
smac_0[8] <= altera_tse_register_map:U_REG.smac_0
smac_0[9] <= altera_tse_register_map:U_REG.smac_0
smac_0[10] <= altera_tse_register_map:U_REG.smac_0
smac_0[11] <= altera_tse_register_map:U_REG.smac_0
smac_0[12] <= altera_tse_register_map:U_REG.smac_0
smac_0[13] <= altera_tse_register_map:U_REG.smac_0
smac_0[14] <= altera_tse_register_map:U_REG.smac_0
smac_0[15] <= altera_tse_register_map:U_REG.smac_0
smac_0[16] <= altera_tse_register_map:U_REG.smac_0
smac_0[17] <= altera_tse_register_map:U_REG.smac_0
smac_0[18] <= altera_tse_register_map:U_REG.smac_0
smac_0[19] <= altera_tse_register_map:U_REG.smac_0
smac_0[20] <= altera_tse_register_map:U_REG.smac_0
smac_0[21] <= altera_tse_register_map:U_REG.smac_0
smac_0[22] <= altera_tse_register_map:U_REG.smac_0
smac_0[23] <= altera_tse_register_map:U_REG.smac_0
smac_0[24] <= altera_tse_register_map:U_REG.smac_0
smac_0[25] <= altera_tse_register_map:U_REG.smac_0
smac_0[26] <= altera_tse_register_map:U_REG.smac_0
smac_0[27] <= altera_tse_register_map:U_REG.smac_0
smac_0[28] <= altera_tse_register_map:U_REG.smac_0
smac_0[29] <= altera_tse_register_map:U_REG.smac_0
smac_0[30] <= altera_tse_register_map:U_REG.smac_0
smac_0[31] <= altera_tse_register_map:U_REG.smac_0
smac_0[32] <= altera_tse_register_map:U_REG.smac_0
smac_0[33] <= altera_tse_register_map:U_REG.smac_0
smac_0[34] <= altera_tse_register_map:U_REG.smac_0
smac_0[35] <= altera_tse_register_map:U_REG.smac_0
smac_0[36] <= altera_tse_register_map:U_REG.smac_0
smac_0[37] <= altera_tse_register_map:U_REG.smac_0
smac_0[38] <= altera_tse_register_map:U_REG.smac_0
smac_0[39] <= altera_tse_register_map:U_REG.smac_0
smac_0[40] <= altera_tse_register_map:U_REG.smac_0
smac_0[41] <= altera_tse_register_map:U_REG.smac_0
smac_0[42] <= altera_tse_register_map:U_REG.smac_0
smac_0[43] <= altera_tse_register_map:U_REG.smac_0
smac_0[44] <= altera_tse_register_map:U_REG.smac_0
smac_0[45] <= altera_tse_register_map:U_REG.smac_0
smac_0[46] <= altera_tse_register_map:U_REG.smac_0
smac_0[47] <= altera_tse_register_map:U_REG.smac_0
smac_1[0] <= altera_tse_register_map:U_REG.smac_1
smac_1[1] <= altera_tse_register_map:U_REG.smac_1
smac_1[2] <= altera_tse_register_map:U_REG.smac_1
smac_1[3] <= altera_tse_register_map:U_REG.smac_1
smac_1[4] <= altera_tse_register_map:U_REG.smac_1
smac_1[5] <= altera_tse_register_map:U_REG.smac_1
smac_1[6] <= altera_tse_register_map:U_REG.smac_1
smac_1[7] <= altera_tse_register_map:U_REG.smac_1
smac_1[8] <= altera_tse_register_map:U_REG.smac_1
smac_1[9] <= altera_tse_register_map:U_REG.smac_1
smac_1[10] <= altera_tse_register_map:U_REG.smac_1
smac_1[11] <= altera_tse_register_map:U_REG.smac_1
smac_1[12] <= altera_tse_register_map:U_REG.smac_1
smac_1[13] <= altera_tse_register_map:U_REG.smac_1
smac_1[14] <= altera_tse_register_map:U_REG.smac_1
smac_1[15] <= altera_tse_register_map:U_REG.smac_1
smac_1[16] <= altera_tse_register_map:U_REG.smac_1
smac_1[17] <= altera_tse_register_map:U_REG.smac_1
smac_1[18] <= altera_tse_register_map:U_REG.smac_1
smac_1[19] <= altera_tse_register_map:U_REG.smac_1
smac_1[20] <= altera_tse_register_map:U_REG.smac_1
smac_1[21] <= altera_tse_register_map:U_REG.smac_1
smac_1[22] <= altera_tse_register_map:U_REG.smac_1
smac_1[23] <= altera_tse_register_map:U_REG.smac_1
smac_1[24] <= altera_tse_register_map:U_REG.smac_1
smac_1[25] <= altera_tse_register_map:U_REG.smac_1
smac_1[26] <= altera_tse_register_map:U_REG.smac_1
smac_1[27] <= altera_tse_register_map:U_REG.smac_1
smac_1[28] <= altera_tse_register_map:U_REG.smac_1
smac_1[29] <= altera_tse_register_map:U_REG.smac_1
smac_1[30] <= altera_tse_register_map:U_REG.smac_1
smac_1[31] <= altera_tse_register_map:U_REG.smac_1
smac_1[32] <= altera_tse_register_map:U_REG.smac_1
smac_1[33] <= altera_tse_register_map:U_REG.smac_1
smac_1[34] <= altera_tse_register_map:U_REG.smac_1
smac_1[35] <= altera_tse_register_map:U_REG.smac_1
smac_1[36] <= altera_tse_register_map:U_REG.smac_1
smac_1[37] <= altera_tse_register_map:U_REG.smac_1
smac_1[38] <= altera_tse_register_map:U_REG.smac_1
smac_1[39] <= altera_tse_register_map:U_REG.smac_1
smac_1[40] <= altera_tse_register_map:U_REG.smac_1
smac_1[41] <= altera_tse_register_map:U_REG.smac_1
smac_1[42] <= altera_tse_register_map:U_REG.smac_1
smac_1[43] <= altera_tse_register_map:U_REG.smac_1
smac_1[44] <= altera_tse_register_map:U_REG.smac_1
smac_1[45] <= altera_tse_register_map:U_REG.smac_1
smac_1[46] <= altera_tse_register_map:U_REG.smac_1
smac_1[47] <= altera_tse_register_map:U_REG.smac_1
smac_2[0] <= altera_tse_register_map:U_REG.smac_2
smac_2[1] <= altera_tse_register_map:U_REG.smac_2
smac_2[2] <= altera_tse_register_map:U_REG.smac_2
smac_2[3] <= altera_tse_register_map:U_REG.smac_2
smac_2[4] <= altera_tse_register_map:U_REG.smac_2
smac_2[5] <= altera_tse_register_map:U_REG.smac_2
smac_2[6] <= altera_tse_register_map:U_REG.smac_2
smac_2[7] <= altera_tse_register_map:U_REG.smac_2
smac_2[8] <= altera_tse_register_map:U_REG.smac_2
smac_2[9] <= altera_tse_register_map:U_REG.smac_2
smac_2[10] <= altera_tse_register_map:U_REG.smac_2
smac_2[11] <= altera_tse_register_map:U_REG.smac_2
smac_2[12] <= altera_tse_register_map:U_REG.smac_2
smac_2[13] <= altera_tse_register_map:U_REG.smac_2
smac_2[14] <= altera_tse_register_map:U_REG.smac_2
smac_2[15] <= altera_tse_register_map:U_REG.smac_2
smac_2[16] <= altera_tse_register_map:U_REG.smac_2
smac_2[17] <= altera_tse_register_map:U_REG.smac_2
smac_2[18] <= altera_tse_register_map:U_REG.smac_2
smac_2[19] <= altera_tse_register_map:U_REG.smac_2
smac_2[20] <= altera_tse_register_map:U_REG.smac_2
smac_2[21] <= altera_tse_register_map:U_REG.smac_2
smac_2[22] <= altera_tse_register_map:U_REG.smac_2
smac_2[23] <= altera_tse_register_map:U_REG.smac_2
smac_2[24] <= altera_tse_register_map:U_REG.smac_2
smac_2[25] <= altera_tse_register_map:U_REG.smac_2
smac_2[26] <= altera_tse_register_map:U_REG.smac_2
smac_2[27] <= altera_tse_register_map:U_REG.smac_2
smac_2[28] <= altera_tse_register_map:U_REG.smac_2
smac_2[29] <= altera_tse_register_map:U_REG.smac_2
smac_2[30] <= altera_tse_register_map:U_REG.smac_2
smac_2[31] <= altera_tse_register_map:U_REG.smac_2
smac_2[32] <= altera_tse_register_map:U_REG.smac_2
smac_2[33] <= altera_tse_register_map:U_REG.smac_2
smac_2[34] <= altera_tse_register_map:U_REG.smac_2
smac_2[35] <= altera_tse_register_map:U_REG.smac_2
smac_2[36] <= altera_tse_register_map:U_REG.smac_2
smac_2[37] <= altera_tse_register_map:U_REG.smac_2
smac_2[38] <= altera_tse_register_map:U_REG.smac_2
smac_2[39] <= altera_tse_register_map:U_REG.smac_2
smac_2[40] <= altera_tse_register_map:U_REG.smac_2
smac_2[41] <= altera_tse_register_map:U_REG.smac_2
smac_2[42] <= altera_tse_register_map:U_REG.smac_2
smac_2[43] <= altera_tse_register_map:U_REG.smac_2
smac_2[44] <= altera_tse_register_map:U_REG.smac_2
smac_2[45] <= altera_tse_register_map:U_REG.smac_2
smac_2[46] <= altera_tse_register_map:U_REG.smac_2
smac_2[47] <= altera_tse_register_map:U_REG.smac_2
smac_3[0] <= altera_tse_register_map:U_REG.smac_3
smac_3[1] <= altera_tse_register_map:U_REG.smac_3
smac_3[2] <= altera_tse_register_map:U_REG.smac_3
smac_3[3] <= altera_tse_register_map:U_REG.smac_3
smac_3[4] <= altera_tse_register_map:U_REG.smac_3
smac_3[5] <= altera_tse_register_map:U_REG.smac_3
smac_3[6] <= altera_tse_register_map:U_REG.smac_3
smac_3[7] <= altera_tse_register_map:U_REG.smac_3
smac_3[8] <= altera_tse_register_map:U_REG.smac_3
smac_3[9] <= altera_tse_register_map:U_REG.smac_3
smac_3[10] <= altera_tse_register_map:U_REG.smac_3
smac_3[11] <= altera_tse_register_map:U_REG.smac_3
smac_3[12] <= altera_tse_register_map:U_REG.smac_3
smac_3[13] <= altera_tse_register_map:U_REG.smac_3
smac_3[14] <= altera_tse_register_map:U_REG.smac_3
smac_3[15] <= altera_tse_register_map:U_REG.smac_3
smac_3[16] <= altera_tse_register_map:U_REG.smac_3
smac_3[17] <= altera_tse_register_map:U_REG.smac_3
smac_3[18] <= altera_tse_register_map:U_REG.smac_3
smac_3[19] <= altera_tse_register_map:U_REG.smac_3
smac_3[20] <= altera_tse_register_map:U_REG.smac_3
smac_3[21] <= altera_tse_register_map:U_REG.smac_3
smac_3[22] <= altera_tse_register_map:U_REG.smac_3
smac_3[23] <= altera_tse_register_map:U_REG.smac_3
smac_3[24] <= altera_tse_register_map:U_REG.smac_3
smac_3[25] <= altera_tse_register_map:U_REG.smac_3
smac_3[26] <= altera_tse_register_map:U_REG.smac_3
smac_3[27] <= altera_tse_register_map:U_REG.smac_3
smac_3[28] <= altera_tse_register_map:U_REG.smac_3
smac_3[29] <= altera_tse_register_map:U_REG.smac_3
smac_3[30] <= altera_tse_register_map:U_REG.smac_3
smac_3[31] <= altera_tse_register_map:U_REG.smac_3
smac_3[32] <= altera_tse_register_map:U_REG.smac_3
smac_3[33] <= altera_tse_register_map:U_REG.smac_3
smac_3[34] <= altera_tse_register_map:U_REG.smac_3
smac_3[35] <= altera_tse_register_map:U_REG.smac_3
smac_3[36] <= altera_tse_register_map:U_REG.smac_3
smac_3[37] <= altera_tse_register_map:U_REG.smac_3
smac_3[38] <= altera_tse_register_map:U_REG.smac_3
smac_3[39] <= altera_tse_register_map:U_REG.smac_3
smac_3[40] <= altera_tse_register_map:U_REG.smac_3
smac_3[41] <= altera_tse_register_map:U_REG.smac_3
smac_3[42] <= altera_tse_register_map:U_REG.smac_3
smac_3[43] <= altera_tse_register_map:U_REG.smac_3
smac_3[44] <= altera_tse_register_map:U_REG.smac_3
smac_3[45] <= altera_tse_register_map:U_REG.smac_3
smac_3[46] <= altera_tse_register_map:U_REG.smac_3
smac_3[47] <= altera_tse_register_map:U_REG.smac_3
tx_addr_sel[0] <= altera_tse_register_map:U_REG.tx_addr_sel
tx_addr_sel[1] <= altera_tse_register_map:U_REG.tx_addr_sel
tx_addr_sel[2] <= altera_tse_register_map:U_REG.tx_addr_sel


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG
rx_clk => rx_clk.IN1
tx_clk => tx_clk.IN1
reg_clk => reg_clk.IN6
reset_rx_clk => _.IN1
reset_tx_clk => _.IN1
reset_reg_clk => reg_data_out[0]~reg0.ACLR
reset_reg_clk => reg_data_out[1]~reg0.ACLR
reset_reg_clk => reg_data_out[2]~reg0.ACLR
reset_reg_clk => reg_data_out[3]~reg0.ACLR
reset_reg_clk => reg_data_out[4]~reg0.ACLR
reset_reg_clk => reg_data_out[5]~reg0.ACLR
reset_reg_clk => reg_data_out[6]~reg0.ACLR
reset_reg_clk => reg_data_out[7]~reg0.ACLR
reset_reg_clk => reg_data_out[8]~reg0.ACLR
reset_reg_clk => reg_data_out[9]~reg0.ACLR
reset_reg_clk => reg_data_out[10]~reg0.ACLR
reset_reg_clk => reg_data_out[11]~reg0.ACLR
reset_reg_clk => reg_data_out[12]~reg0.ACLR
reset_reg_clk => reg_data_out[13]~reg0.ACLR
reset_reg_clk => reg_data_out[14]~reg0.ACLR
reset_reg_clk => reg_data_out[15]~reg0.ACLR
reset_reg_clk => reg_data_out[16]~reg0.ACLR
reset_reg_clk => reg_data_out[17]~reg0.ACLR
reset_reg_clk => reg_data_out[18]~reg0.ACLR
reset_reg_clk => reg_data_out[19]~reg0.ACLR
reset_reg_clk => reg_data_out[20]~reg0.ACLR
reset_reg_clk => reg_data_out[21]~reg0.ACLR
reset_reg_clk => reg_data_out[22]~reg0.ACLR
reset_reg_clk => reg_data_out[23]~reg0.ACLR
reset_reg_clk => reg_data_out[24]~reg0.ACLR
reset_reg_clk => reg_data_out[25]~reg0.ACLR
reset_reg_clk => reg_data_out[26]~reg0.ACLR
reset_reg_clk => reg_data_out[27]~reg0.ACLR
reset_reg_clk => reg_data_out[28]~reg0.ACLR
reset_reg_clk => reg_data_out[29]~reg0.ACLR
reset_reg_clk => reg_data_out[30]~reg0.ACLR
reset_reg_clk => reg_data_out[31]~reg0.ACLR
reset_reg_clk => mdio_dev_addr_reg[0].ACLR
reset_reg_clk => mdio_dev_addr_reg[1].ACLR
reset_reg_clk => mdio_dev_addr_reg[2].ACLR
reset_reg_clk => mdio_dev_addr_reg[3].ACLR
reset_reg_clk => mdio_dev_addr_reg[4].ACLR
reset_reg_clk => mdio_data_out_reg[0].ACLR
reset_reg_clk => mdio_data_out_reg[1].ACLR
reset_reg_clk => mdio_data_out_reg[2].ACLR
reset_reg_clk => mdio_data_out_reg[3].ACLR
reset_reg_clk => mdio_data_out_reg[4].ACLR
reset_reg_clk => mdio_data_out_reg[5].ACLR
reset_reg_clk => mdio_data_out_reg[6].ACLR
reset_reg_clk => mdio_data_out_reg[7].ACLR
reset_reg_clk => mdio_data_out_reg[8].ACLR
reset_reg_clk => mdio_data_out_reg[9].ACLR
reset_reg_clk => mdio_data_out_reg[10].ACLR
reset_reg_clk => mdio_data_out_reg[11].ACLR
reset_reg_clk => mdio_data_out_reg[12].ACLR
reset_reg_clk => mdio_data_out_reg[13].ACLR
reset_reg_clk => mdio_data_out_reg[14].ACLR
reset_reg_clk => mdio_data_out_reg[15].ACLR
reset_reg_clk => mdio_addr_reg[0].ACLR
reset_reg_clk => mdio_addr_reg[1].ACLR
reset_reg_clk => mdio_addr_reg[2].ACLR
reset_reg_clk => mdio_addr_reg[3].ACLR
reset_reg_clk => mdio_addr_reg[4].ACLR
reset_reg_clk => mdio_rd_reg.ACLR
reset_reg_clk => mdio_wr_reg.ACLR
reset_reg_clk => mdio_cs_int_reg.ACLR
reset_reg_clk => mdio_cs_reg.ACLR
reset_reg_clk => rx_command_status[25].PRESET
reset_reg_clk => tx_command_status[17].ACLR
reset_reg_clk => tx_command_status[18].PRESET
reset_reg_clk => msb_etherstatsoctets[0].ACLR
reset_reg_clk => msb_etherstatsoctets[1].ACLR
reset_reg_clk => msb_etherstatsoctets[2].ACLR
reset_reg_clk => msb_etherstatsoctets[3].ACLR
reset_reg_clk => msb_etherstatsoctets[4].ACLR
reset_reg_clk => msb_etherstatsoctets[5].ACLR
reset_reg_clk => msb_etherstatsoctets[6].ACLR
reset_reg_clk => msb_etherstatsoctets[7].ACLR
reset_reg_clk => msb_etherstatsoctets[8].ACLR
reset_reg_clk => msb_etherstatsoctets[9].ACLR
reset_reg_clk => msb_etherstatsoctets[10].ACLR
reset_reg_clk => msb_etherstatsoctets[11].ACLR
reset_reg_clk => msb_etherstatsoctets[12].ACLR
reset_reg_clk => msb_etherstatsoctets[13].ACLR
reset_reg_clk => msb_etherstatsoctets[14].ACLR
reset_reg_clk => msb_etherstatsoctets[15].ACLR
reset_reg_clk => msb_etherstatsoctets[16].ACLR
reset_reg_clk => msb_etherstatsoctets[17].ACLR
reset_reg_clk => msb_etherstatsoctets[18].ACLR
reset_reg_clk => msb_etherstatsoctets[19].ACLR
reset_reg_clk => msb_etherstatsoctets[20].ACLR
reset_reg_clk => msb_etherstatsoctets[21].ACLR
reset_reg_clk => msb_etherstatsoctets[22].ACLR
reset_reg_clk => msb_etherstatsoctets[23].ACLR
reset_reg_clk => msb_etherstatsoctets[24].ACLR
reset_reg_clk => msb_etherstatsoctets[25].ACLR
reset_reg_clk => msb_etherstatsoctets[26].ACLR
reset_reg_clk => msb_etherstatsoctets[27].ACLR
reset_reg_clk => msb_etherstatsoctets[28].ACLR
reset_reg_clk => msb_etherstatsoctets[29].ACLR
reset_reg_clk => msb_etherstatsoctets[30].ACLR
reset_reg_clk => msb_etherstatsoctets[31].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[0].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[1].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[2].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[3].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[4].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[5].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[6].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[7].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[8].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[9].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[10].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[11].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[12].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[13].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[14].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[15].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[16].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[17].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[18].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[19].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[20].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[21].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[22].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[23].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[24].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[25].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[26].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[27].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[28].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[29].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[30].ACLR
reset_reg_clk => msb_aOctetsReceivedOK[31].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[0].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[1].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[2].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[3].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[4].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[5].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[6].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[7].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[8].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[9].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[10].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[11].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[12].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[13].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[14].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[15].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[16].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[17].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[18].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[19].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[20].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[21].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[22].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[23].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[24].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[25].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[26].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[27].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[28].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[29].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[30].ACLR
reset_reg_clk => msb_aOctetsTransmittedOK[31].ACLR
reset_reg_clk => aframesreceivedok[0].ACLR
reset_reg_clk => aframesreceivedok[1].ACLR
reset_reg_clk => aframesreceivedok[2].ACLR
reset_reg_clk => aframesreceivedok[3].ACLR
reset_reg_clk => aframesreceivedok[4].ACLR
reset_reg_clk => aframesreceivedok[5].ACLR
reset_reg_clk => aframesreceivedok[6].ACLR
reset_reg_clk => aframesreceivedok[7].ACLR
reset_reg_clk => aframesreceivedok[8].ACLR
reset_reg_clk => aframesreceivedok[9].ACLR
reset_reg_clk => aframesreceivedok[10].ACLR
reset_reg_clk => aframesreceivedok[11].ACLR
reset_reg_clk => aframesreceivedok[12].ACLR
reset_reg_clk => aframesreceivedok[13].ACLR
reset_reg_clk => aframesreceivedok[14].ACLR
reset_reg_clk => aframesreceivedok[15].ACLR
reset_reg_clk => aframesreceivedok[16].ACLR
reset_reg_clk => aframesreceivedok[17].ACLR
reset_reg_clk => aframesreceivedok[18].ACLR
reset_reg_clk => aframesreceivedok[19].ACLR
reset_reg_clk => aframesreceivedok[20].ACLR
reset_reg_clk => aframesreceivedok[21].ACLR
reset_reg_clk => aframesreceivedok[22].ACLR
reset_reg_clk => aframesreceivedok[23].ACLR
reset_reg_clk => aframesreceivedok[24].ACLR
reset_reg_clk => aframesreceivedok[25].ACLR
reset_reg_clk => aframesreceivedok[26].ACLR
reset_reg_clk => aframesreceivedok[27].ACLR
reset_reg_clk => aframesreceivedok[28].ACLR
reset_reg_clk => aframesreceivedok[29].ACLR
reset_reg_clk => aframesreceivedok[30].ACLR
reset_reg_clk => aframesreceivedok[31].ACLR
reset_reg_clk => aframechecksequenceerrors[0].ACLR
reset_reg_clk => aframechecksequenceerrors[1].ACLR
reset_reg_clk => aframechecksequenceerrors[2].ACLR
reset_reg_clk => aframechecksequenceerrors[3].ACLR
reset_reg_clk => aframechecksequenceerrors[4].ACLR
reset_reg_clk => aframechecksequenceerrors[5].ACLR
reset_reg_clk => aframechecksequenceerrors[6].ACLR
reset_reg_clk => aframechecksequenceerrors[7].ACLR
reset_reg_clk => aframechecksequenceerrors[8].ACLR
reset_reg_clk => aframechecksequenceerrors[9].ACLR
reset_reg_clk => aframechecksequenceerrors[10].ACLR
reset_reg_clk => aframechecksequenceerrors[11].ACLR
reset_reg_clk => aframechecksequenceerrors[12].ACLR
reset_reg_clk => aframechecksequenceerrors[13].ACLR
reset_reg_clk => aframechecksequenceerrors[14].ACLR
reset_reg_clk => aframechecksequenceerrors[15].ACLR
reset_reg_clk => aframechecksequenceerrors[16].ACLR
reset_reg_clk => aframechecksequenceerrors[17].ACLR
reset_reg_clk => aframechecksequenceerrors[18].ACLR
reset_reg_clk => aframechecksequenceerrors[19].ACLR
reset_reg_clk => aframechecksequenceerrors[20].ACLR
reset_reg_clk => aframechecksequenceerrors[21].ACLR
reset_reg_clk => aframechecksequenceerrors[22].ACLR
reset_reg_clk => aframechecksequenceerrors[23].ACLR
reset_reg_clk => aframechecksequenceerrors[24].ACLR
reset_reg_clk => aframechecksequenceerrors[25].ACLR
reset_reg_clk => aframechecksequenceerrors[26].ACLR
reset_reg_clk => aframechecksequenceerrors[27].ACLR
reset_reg_clk => aframechecksequenceerrors[28].ACLR
reset_reg_clk => aframechecksequenceerrors[29].ACLR
reset_reg_clk => aframechecksequenceerrors[30].ACLR
reset_reg_clk => aframechecksequenceerrors[31].ACLR
reset_reg_clk => aalignmenterrors[0].ACLR
reset_reg_clk => aalignmenterrors[1].ACLR
reset_reg_clk => aalignmenterrors[2].ACLR
reset_reg_clk => aalignmenterrors[3].ACLR
reset_reg_clk => aalignmenterrors[4].ACLR
reset_reg_clk => aalignmenterrors[5].ACLR
reset_reg_clk => aalignmenterrors[6].ACLR
reset_reg_clk => aalignmenterrors[7].ACLR
reset_reg_clk => aalignmenterrors[8].ACLR
reset_reg_clk => aalignmenterrors[9].ACLR
reset_reg_clk => aalignmenterrors[10].ACLR
reset_reg_clk => aalignmenterrors[11].ACLR
reset_reg_clk => aalignmenterrors[12].ACLR
reset_reg_clk => aalignmenterrors[13].ACLR
reset_reg_clk => aalignmenterrors[14].ACLR
reset_reg_clk => aalignmenterrors[15].ACLR
reset_reg_clk => aalignmenterrors[16].ACLR
reset_reg_clk => aalignmenterrors[17].ACLR
reset_reg_clk => aalignmenterrors[18].ACLR
reset_reg_clk => aalignmenterrors[19].ACLR
reset_reg_clk => aalignmenterrors[20].ACLR
reset_reg_clk => aalignmenterrors[21].ACLR
reset_reg_clk => aalignmenterrors[22].ACLR
reset_reg_clk => aalignmenterrors[23].ACLR
reset_reg_clk => aalignmenterrors[24].ACLR
reset_reg_clk => aalignmenterrors[25].ACLR
reset_reg_clk => aalignmenterrors[26].ACLR
reset_reg_clk => aalignmenterrors[27].ACLR
reset_reg_clk => aalignmenterrors[28].ACLR
reset_reg_clk => aalignmenterrors[29].ACLR
reset_reg_clk => aalignmenterrors[30].ACLR
reset_reg_clk => aalignmenterrors[31].ACLR
reset_reg_clk => apausemacctrlframesreceived[0].ACLR
reset_reg_clk => apausemacctrlframesreceived[1].ACLR
reset_reg_clk => apausemacctrlframesreceived[2].ACLR
reset_reg_clk => apausemacctrlframesreceived[3].ACLR
reset_reg_clk => apausemacctrlframesreceived[4].ACLR
reset_reg_clk => apausemacctrlframesreceived[5].ACLR
reset_reg_clk => apausemacctrlframesreceived[6].ACLR
reset_reg_clk => apausemacctrlframesreceived[7].ACLR
reset_reg_clk => apausemacctrlframesreceived[8].ACLR
reset_reg_clk => apausemacctrlframesreceived[9].ACLR
reset_reg_clk => apausemacctrlframesreceived[10].ACLR
reset_reg_clk => apausemacctrlframesreceived[11].ACLR
reset_reg_clk => apausemacctrlframesreceived[12].ACLR
reset_reg_clk => apausemacctrlframesreceived[13].ACLR
reset_reg_clk => apausemacctrlframesreceived[14].ACLR
reset_reg_clk => apausemacctrlframesreceived[15].ACLR
reset_reg_clk => apausemacctrlframesreceived[16].ACLR
reset_reg_clk => apausemacctrlframesreceived[17].ACLR
reset_reg_clk => apausemacctrlframesreceived[18].ACLR
reset_reg_clk => apausemacctrlframesreceived[19].ACLR
reset_reg_clk => apausemacctrlframesreceived[20].ACLR
reset_reg_clk => apausemacctrlframesreceived[21].ACLR
reset_reg_clk => apausemacctrlframesreceived[22].ACLR
reset_reg_clk => apausemacctrlframesreceived[23].ACLR
reset_reg_clk => apausemacctrlframesreceived[24].ACLR
reset_reg_clk => apausemacctrlframesreceived[25].ACLR
reset_reg_clk => apausemacctrlframesreceived[26].ACLR
reset_reg_clk => apausemacctrlframesreceived[27].ACLR
reset_reg_clk => apausemacctrlframesreceived[28].ACLR
reset_reg_clk => apausemacctrlframesreceived[29].ACLR
reset_reg_clk => apausemacctrlframesreceived[30].ACLR
reset_reg_clk => apausemacctrlframesreceived[31].ACLR
reset_reg_clk => etherStatsJabbers[0].ACLR
reset_reg_clk => etherStatsJabbers[1].ACLR
reset_reg_clk => etherStatsJabbers[2].ACLR
reset_reg_clk => etherStatsJabbers[3].ACLR
reset_reg_clk => etherStatsJabbers[4].ACLR
reset_reg_clk => etherStatsJabbers[5].ACLR
reset_reg_clk => etherStatsJabbers[6].ACLR
reset_reg_clk => etherStatsJabbers[7].ACLR
reset_reg_clk => etherStatsJabbers[8].ACLR
reset_reg_clk => etherStatsJabbers[9].ACLR
reset_reg_clk => etherStatsJabbers[10].ACLR
reset_reg_clk => etherStatsJabbers[11].ACLR
reset_reg_clk => etherStatsJabbers[12].ACLR
reset_reg_clk => etherStatsJabbers[13].ACLR
reset_reg_clk => etherStatsJabbers[14].ACLR
reset_reg_clk => etherStatsJabbers[15].ACLR
reset_reg_clk => etherStatsJabbers[16].ACLR
reset_reg_clk => etherStatsJabbers[17].ACLR
reset_reg_clk => etherStatsJabbers[18].ACLR
reset_reg_clk => etherStatsJabbers[19].ACLR
reset_reg_clk => etherStatsJabbers[20].ACLR
reset_reg_clk => etherStatsJabbers[21].ACLR
reset_reg_clk => etherStatsJabbers[22].ACLR
reset_reg_clk => etherStatsJabbers[23].ACLR
reset_reg_clk => etherStatsJabbers[24].ACLR
reset_reg_clk => etherStatsJabbers[25].ACLR
reset_reg_clk => etherStatsJabbers[26].ACLR
reset_reg_clk => etherStatsJabbers[27].ACLR
reset_reg_clk => etherStatsJabbers[28].ACLR
reset_reg_clk => etherStatsJabbers[29].ACLR
reset_reg_clk => etherStatsJabbers[30].ACLR
reset_reg_clk => etherStatsJabbers[31].ACLR
reset_reg_clk => etherStatsFragments[0].ACLR
reset_reg_clk => etherStatsFragments[1].ACLR
reset_reg_clk => etherStatsFragments[2].ACLR
reset_reg_clk => etherStatsFragments[3].ACLR
reset_reg_clk => etherStatsFragments[4].ACLR
reset_reg_clk => etherStatsFragments[5].ACLR
reset_reg_clk => etherStatsFragments[6].ACLR
reset_reg_clk => etherStatsFragments[7].ACLR
reset_reg_clk => etherStatsFragments[8].ACLR
reset_reg_clk => etherStatsFragments[9].ACLR
reset_reg_clk => etherStatsFragments[10].ACLR
reset_reg_clk => etherStatsFragments[11].ACLR
reset_reg_clk => etherStatsFragments[12].ACLR
reset_reg_clk => etherStatsFragments[13].ACLR
reset_reg_clk => etherStatsFragments[14].ACLR
reset_reg_clk => etherStatsFragments[15].ACLR
reset_reg_clk => etherStatsFragments[16].ACLR
reset_reg_clk => etherStatsFragments[17].ACLR
reset_reg_clk => etherStatsFragments[18].ACLR
reset_reg_clk => etherStatsFragments[19].ACLR
reset_reg_clk => etherStatsFragments[20].ACLR
reset_reg_clk => etherStatsFragments[21].ACLR
reset_reg_clk => etherStatsFragments[22].ACLR
reset_reg_clk => etherStatsFragments[23].ACLR
reset_reg_clk => etherStatsFragments[24].ACLR
reset_reg_clk => etherStatsFragments[25].ACLR
reset_reg_clk => etherStatsFragments[26].ACLR
reset_reg_clk => etherStatsFragments[27].ACLR
reset_reg_clk => etherStatsFragments[28].ACLR
reset_reg_clk => etherStatsFragments[29].ACLR
reset_reg_clk => etherStatsFragments[30].ACLR
reset_reg_clk => etherStatsFragments[31].ACLR
reset_reg_clk => reg_status.ACLR
reset_reg_clk => tx_ipg_len_reg[0].ACLR
reset_reg_clk => tx_ipg_len_reg[1].ACLR
reset_reg_clk => tx_ipg_len_reg[2].ACLR
reset_reg_clk => tx_ipg_len_reg[3].ACLR
reset_reg_clk => tx_ipg_len_reg[4].ACLR
reset_reg_clk => holdoff_quant[0]~reg0.PRESET
reset_reg_clk => holdoff_quant[1]~reg0.PRESET
reset_reg_clk => holdoff_quant[2]~reg0.PRESET
reset_reg_clk => holdoff_quant[3]~reg0.PRESET
reset_reg_clk => holdoff_quant[4]~reg0.PRESET
reset_reg_clk => holdoff_quant[5]~reg0.PRESET
reset_reg_clk => holdoff_quant[6]~reg0.PRESET
reset_reg_clk => holdoff_quant[7]~reg0.PRESET
reset_reg_clk => holdoff_quant[8]~reg0.PRESET
reset_reg_clk => holdoff_quant[9]~reg0.PRESET
reset_reg_clk => holdoff_quant[10]~reg0.PRESET
reset_reg_clk => holdoff_quant[11]~reg0.PRESET
reset_reg_clk => holdoff_quant[12]~reg0.PRESET
reset_reg_clk => holdoff_quant[13]~reg0.PRESET
reset_reg_clk => holdoff_quant[14]~reg0.PRESET
reset_reg_clk => holdoff_quant[15]~reg0.PRESET
reset_reg_clk => mdio_addr1[0].PRESET
reset_reg_clk => mdio_addr1[1].ACLR
reset_reg_clk => mdio_addr1[2].ACLR
reset_reg_clk => mdio_addr1[3].ACLR
reset_reg_clk => mdio_addr1[4].ACLR
reset_reg_clk => mdio_addr0[0].ACLR
reset_reg_clk => mdio_addr0[1].ACLR
reset_reg_clk => mdio_addr0[2].ACLR
reset_reg_clk => mdio_addr0[3].ACLR
reset_reg_clk => mdio_addr0[4].ACLR
reset_reg_clk => tx_af_level_reg[0].ACLR
reset_reg_clk => tx_af_level_reg[1].ACLR
reset_reg_clk => tx_af_level_reg[2].ACLR
reset_reg_clk => tx_af_level_reg[3].ACLR
reset_reg_clk => tx_af_level_reg[4].ACLR
reset_reg_clk => tx_af_level_reg[5].ACLR
reset_reg_clk => tx_af_level_reg[6].ACLR
reset_reg_clk => tx_af_level_reg[7].ACLR
reset_reg_clk => tx_af_level_reg[8].ACLR
reset_reg_clk => tx_af_level_reg[9].ACLR
reset_reg_clk => tx_af_level_reg[10].ACLR
reset_reg_clk => tx_ae_level_reg[0].ACLR
reset_reg_clk => tx_ae_level_reg[1].ACLR
reset_reg_clk => tx_ae_level_reg[2].ACLR
reset_reg_clk => tx_ae_level_reg[3].ACLR
reset_reg_clk => tx_ae_level_reg[4].ACLR
reset_reg_clk => tx_ae_level_reg[5].ACLR
reset_reg_clk => tx_ae_level_reg[6].ACLR
reset_reg_clk => tx_ae_level_reg[7].ACLR
reset_reg_clk => tx_ae_level_reg[8].ACLR
reset_reg_clk => tx_ae_level_reg[9].ACLR
reset_reg_clk => tx_ae_level_reg[10].ACLR
reset_reg_clk => rx_af_level_reg[0].ACLR
reset_reg_clk => rx_af_level_reg[1].ACLR
reset_reg_clk => rx_af_level_reg[2].ACLR
reset_reg_clk => rx_af_level_reg[3].ACLR
reset_reg_clk => rx_af_level_reg[4].ACLR
reset_reg_clk => rx_af_level_reg[5].ACLR
reset_reg_clk => rx_af_level_reg[6].ACLR
reset_reg_clk => rx_af_level_reg[7].ACLR
reset_reg_clk => rx_af_level_reg[8].ACLR
reset_reg_clk => rx_af_level_reg[9].ACLR
reset_reg_clk => rx_af_level_reg[10].ACLR
reset_reg_clk => rx_ae_level_reg[0].ACLR
reset_reg_clk => rx_ae_level_reg[1].ACLR
reset_reg_clk => rx_ae_level_reg[2].ACLR
reset_reg_clk => rx_ae_level_reg[3].ACLR
reset_reg_clk => rx_ae_level_reg[4].ACLR
reset_reg_clk => rx_ae_level_reg[5].ACLR
reset_reg_clk => rx_ae_level_reg[6].ACLR
reset_reg_clk => rx_ae_level_reg[7].ACLR
reset_reg_clk => rx_ae_level_reg[8].ACLR
reset_reg_clk => rx_ae_level_reg[9].ACLR
reset_reg_clk => rx_ae_level_reg[10].ACLR
reset_reg_clk => tx_section_full_reg[0].ACLR
reset_reg_clk => tx_section_full_reg[1].ACLR
reset_reg_clk => tx_section_full_reg[2].ACLR
reset_reg_clk => tx_section_full_reg[3].ACLR
reset_reg_clk => tx_section_full_reg[4].ACLR
reset_reg_clk => tx_section_full_reg[5].ACLR
reset_reg_clk => tx_section_full_reg[6].ACLR
reset_reg_clk => tx_section_full_reg[7].ACLR
reset_reg_clk => tx_section_full_reg[8].ACLR
reset_reg_clk => tx_section_full_reg[9].ACLR
reset_reg_clk => tx_section_full_reg[10].ACLR
reset_reg_clk => tx_section_empty_reg[0].ACLR
reset_reg_clk => tx_section_empty_reg[1].ACLR
reset_reg_clk => tx_section_empty_reg[2].ACLR
reset_reg_clk => tx_section_empty_reg[3].ACLR
reset_reg_clk => tx_section_empty_reg[4].ACLR
reset_reg_clk => tx_section_empty_reg[5].ACLR
reset_reg_clk => tx_section_empty_reg[6].ACLR
reset_reg_clk => tx_section_empty_reg[7].ACLR
reset_reg_clk => tx_section_empty_reg[8].ACLR
reset_reg_clk => tx_section_empty_reg[9].ACLR
reset_reg_clk => tx_section_empty_reg[10].ACLR
reset_reg_clk => rx_section_full_reg[0].ACLR
reset_reg_clk => rx_section_full_reg[1].ACLR
reset_reg_clk => rx_section_full_reg[2].ACLR
reset_reg_clk => rx_section_full_reg[3].ACLR
reset_reg_clk => rx_section_full_reg[4].ACLR
reset_reg_clk => rx_section_full_reg[5].ACLR
reset_reg_clk => rx_section_full_reg[6].ACLR
reset_reg_clk => rx_section_full_reg[7].ACLR
reset_reg_clk => rx_section_full_reg[8].ACLR
reset_reg_clk => rx_section_full_reg[9].ACLR
reset_reg_clk => rx_section_full_reg[10].ACLR
reset_reg_clk => rx_section_empty_reg[0].ACLR
reset_reg_clk => rx_section_empty_reg[1].ACLR
reset_reg_clk => rx_section_empty_reg[2].ACLR
reset_reg_clk => rx_section_empty_reg[3].ACLR
reset_reg_clk => rx_section_empty_reg[4].ACLR
reset_reg_clk => rx_section_empty_reg[5].ACLR
reset_reg_clk => rx_section_empty_reg[6].ACLR
reset_reg_clk => rx_section_empty_reg[7].ACLR
reset_reg_clk => rx_section_empty_reg[8].ACLR
reset_reg_clk => rx_section_empty_reg[9].ACLR
reset_reg_clk => rx_section_empty_reg[10].ACLR
reset_reg_clk => pause_quant_reg[0].ACLR
reset_reg_clk => pause_quant_reg[1].ACLR
reset_reg_clk => pause_quant_reg[2].ACLR
reset_reg_clk => pause_quant_reg[3].ACLR
reset_reg_clk => pause_quant_reg[4].ACLR
reset_reg_clk => pause_quant_reg[5].ACLR
reset_reg_clk => pause_quant_reg[6].ACLR
reset_reg_clk => pause_quant_reg[7].ACLR
reset_reg_clk => pause_quant_reg[8].ACLR
reset_reg_clk => pause_quant_reg[9].ACLR
reset_reg_clk => pause_quant_reg[10].ACLR
reset_reg_clk => pause_quant_reg[11].ACLR
reset_reg_clk => pause_quant_reg[12].ACLR
reset_reg_clk => pause_quant_reg[13].ACLR
reset_reg_clk => pause_quant_reg[14].ACLR
reset_reg_clk => pause_quant_reg[15].ACLR
reset_reg_clk => pause_quant_reg[16].ACLR
reset_reg_clk => pause_quant_reg[17].ACLR
reset_reg_clk => pause_quant_reg[18].ACLR
reset_reg_clk => pause_quant_reg[19].ACLR
reset_reg_clk => pause_quant_reg[20].ACLR
reset_reg_clk => pause_quant_reg[21].ACLR
reset_reg_clk => pause_quant_reg[22].ACLR
reset_reg_clk => pause_quant_reg[23].ACLR
reset_reg_clk => pause_quant_reg[24].ACLR
reset_reg_clk => pause_quant_reg[25].ACLR
reset_reg_clk => pause_quant_reg[26].ACLR
reset_reg_clk => pause_quant_reg[27].ACLR
reset_reg_clk => pause_quant_reg[28].ACLR
reset_reg_clk => pause_quant_reg[29].ACLR
reset_reg_clk => pause_quant_reg[30].ACLR
reset_reg_clk => pause_quant_reg[31].ACLR
reset_reg_clk => frm_length[0].ACLR
reset_reg_clk => frm_length[1].PRESET
reset_reg_clk => frm_length[2].PRESET
reset_reg_clk => frm_length[3].PRESET
reset_reg_clk => frm_length[4].ACLR
reset_reg_clk => frm_length[5].PRESET
reset_reg_clk => frm_length[6].PRESET
reset_reg_clk => frm_length[7].PRESET
reset_reg_clk => frm_length[8].PRESET
reset_reg_clk => frm_length[9].ACLR
reset_reg_clk => frm_length[10].PRESET
reset_reg_clk => frm_length[11].ACLR
reset_reg_clk => frm_length[12].ACLR
reset_reg_clk => frm_length[13].ACLR
reset_reg_clk => frm_length[14].ACLR
reset_reg_clk => frm_length[15].ACLR
reset_reg_clk => mac_1[0].ACLR
reset_reg_clk => mac_1[1].ACLR
reset_reg_clk => mac_1[2].ACLR
reset_reg_clk => mac_1[3].ACLR
reset_reg_clk => mac_1[4].ACLR
reset_reg_clk => mac_1[5].ACLR
reset_reg_clk => mac_1[6].ACLR
reset_reg_clk => mac_1[7].ACLR
reset_reg_clk => mac_1[8].ACLR
reset_reg_clk => mac_1[9].ACLR
reset_reg_clk => mac_1[10].ACLR
reset_reg_clk => mac_1[11].ACLR
reset_reg_clk => mac_1[12].ACLR
reset_reg_clk => mac_1[13].ACLR
reset_reg_clk => mac_1[14].ACLR
reset_reg_clk => mac_1[15].ACLR
reset_reg_clk => mac_0[0].ACLR
reset_reg_clk => mac_0[1].ACLR
reset_reg_clk => mac_0[2].ACLR
reset_reg_clk => mac_0[3].ACLR
reset_reg_clk => mac_0[4].ACLR
reset_reg_clk => mac_0[5].ACLR
reset_reg_clk => mac_0[6].ACLR
reset_reg_clk => mac_0[7].ACLR
reset_reg_clk => mac_0[8].ACLR
reset_reg_clk => mac_0[9].ACLR
reset_reg_clk => mac_0[10].ACLR
reset_reg_clk => mac_0[11].ACLR
reset_reg_clk => mac_0[12].ACLR
reset_reg_clk => mac_0[13].ACLR
reset_reg_clk => mac_0[14].ACLR
reset_reg_clk => mac_0[15].ACLR
reset_reg_clk => mac_0[16].ACLR
reset_reg_clk => mac_0[17].ACLR
reset_reg_clk => mac_0[18].ACLR
reset_reg_clk => mac_0[19].ACLR
reset_reg_clk => mac_0[20].ACLR
reset_reg_clk => mac_0[21].ACLR
reset_reg_clk => mac_0[22].ACLR
reset_reg_clk => mac_0[23].ACLR
reset_reg_clk => mac_0[24].ACLR
reset_reg_clk => mac_0[25].ACLR
reset_reg_clk => mac_0[26].ACLR
reset_reg_clk => mac_0[27].ACLR
reset_reg_clk => mac_0[28].ACLR
reset_reg_clk => mac_0[29].ACLR
reset_reg_clk => mac_0[30].ACLR
reset_reg_clk => mac_0[31].ACLR
reset_reg_clk => sleep_ena~reg0.ACLR
reset_reg_clk => enable_rx~reg0.ACLR
reset_reg_clk => enable_tx~reg0.ACLR
reset_reg_clk => ena_10~reg0.ACLR
reset_reg_clk => eth_mode~reg0.ACLR
reset_reg_clk => ethernet_mode~reg0.ACLR
reset_reg_clk => command_config[21].ACLR
reset_reg_clk => command_config[0].ACLR
reset_reg_clk => command_config[1].ACLR
reset_reg_clk => command_config[2].ACLR
reset_reg_clk => command_config[3].ACLR
reset_reg_clk => command_config[4].ACLR
reset_reg_clk => command_config[5].ACLR
reset_reg_clk => command_config[6].ACLR
reset_reg_clk => command_config[7].ACLR
reset_reg_clk => command_config[8].ACLR
reset_reg_clk => command_config[9].ACLR
reset_reg_clk => command_config[13].ACLR
reset_reg_clk => command_config[14].ACLR
reset_reg_clk => command_config[15].ACLR
reset_reg_clk => command_config[16].ACLR
reset_reg_clk => command_config[17].ACLR
reset_reg_clk => command_config[18].ACLR
reset_reg_clk => command_config[19].ACLR
reset_reg_clk => command_config[20].ACLR
reset_reg_clk => command_config[22].ACLR
reset_reg_clk => command_config[23].ACLR
reset_reg_clk => command_config[24].ACLR
reset_reg_clk => command_config[25].ACLR
reset_reg_clk => command_config[26].ACLR
reset_reg_clk => command_config[27].ACLR
reset_reg_clk => command_config[31].ACLR
reset_reg_clk => scratch[0].ACLR
reset_reg_clk => scratch[1].ACLR
reset_reg_clk => scratch[2].ACLR
reset_reg_clk => scratch[3].ACLR
reset_reg_clk => scratch[4].ACLR
reset_reg_clk => scratch[5].ACLR
reset_reg_clk => scratch[6].ACLR
reset_reg_clk => scratch[7].ACLR
reset_reg_clk => scratch[8].ACLR
reset_reg_clk => scratch[9].ACLR
reset_reg_clk => scratch[10].ACLR
reset_reg_clk => scratch[11].ACLR
reset_reg_clk => scratch[12].ACLR
reset_reg_clk => scratch[13].ACLR
reset_reg_clk => scratch[14].ACLR
reset_reg_clk => scratch[15].ACLR
reset_reg_clk => scratch[16].ACLR
reset_reg_clk => scratch[17].ACLR
reset_reg_clk => scratch[18].ACLR
reset_reg_clk => scratch[19].ACLR
reset_reg_clk => scratch[20].ACLR
reset_reg_clk => scratch[21].ACLR
reset_reg_clk => scratch[22].ACLR
reset_reg_clk => scratch[23].ACLR
reset_reg_clk => scratch[24].ACLR
reset_reg_clk => scratch[25].ACLR
reset_reg_clk => scratch[26].ACLR
reset_reg_clk => scratch[27].ACLR
reset_reg_clk => scratch[28].ACLR
reset_reg_clk => scratch[29].ACLR
reset_reg_clk => scratch[30].ACLR
reset_reg_clk => scratch[31].ACLR
reset_reg_clk => _.IN1
reset_reg_clk => _.IN1
reset_reg_clk => _.IN1
reset_reg_clk => _.IN1
reset_reg_clk => _.IN1
reset_reg_clk => _.IN1
reg_rd => always38.IN1
reg_rd => always48.IN0
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => reg_data_out.OUTPUTSELECT
reg_rd => mdio_rd_reg.DATAIN
reg_wr => always0.IN1
reg_wr => always2.IN1
reg_wr => always10.IN1
reg_wr => always12.IN1
reg_wr => always14.IN1
reg_wr => always17.IN1
reg_wr => always19.IN1
reg_wr => always21.IN1
reg_wr => always23.IN1
reg_wr => always25.IN1
reg_wr => always27.IN1
reg_wr => always29.IN1
reg_wr => always31.IN1
reg_wr => always33.IN1
reg_wr => always35.IN1
reg_wr => always37.IN1
reg_wr => always44.IN1
reg_wr => always47.IN1
reg_wr => always48.IN1
reg_wr => mdio_wr_reg.DATAIN
reg_timout => command_config.OUTPUTSELECT
reg_timout => command_config.OUTPUTSELECT
reg_timout => reg_status.OUTPUTSELECT
reg_sel[0] => LessThan0.IN16
reg_sel[0] => LessThan1.IN16
reg_sel[0] => LessThan2.IN16
reg_sel[0] => Decoder0.IN7
reg_sel[0] => mdio_addr_reg[0].DATAIN
reg_sel[0] => Equal0.IN0
reg_sel[0] => Equal1.IN7
reg_sel[0] => Equal2.IN1
reg_sel[0] => Equal3.IN7
reg_sel[0] => Equal4.IN1
reg_sel[0] => Equal5.IN2
reg_sel[0] => Equal6.IN7
reg_sel[0] => Equal7.IN1
reg_sel[0] => Equal8.IN7
reg_sel[0] => Equal9.IN2
reg_sel[0] => Equal10.IN7
reg_sel[0] => Equal11.IN2
reg_sel[0] => Equal12.IN7
reg_sel[0] => Equal13.IN3
reg_sel[0] => Equal14.IN7
reg_sel[0] => Equal15.IN3
reg_sel[0] => Equal16.IN7
reg_sel[0] => Equal17.IN7
reg_sel[0] => Equal18.IN4
reg_sel[1] => LessThan0.IN15
reg_sel[1] => LessThan1.IN15
reg_sel[1] => LessThan2.IN15
reg_sel[1] => Decoder0.IN6
reg_sel[1] => mdio_addr_reg[1].DATAIN
reg_sel[1] => Equal0.IN7
reg_sel[1] => Equal1.IN0
reg_sel[1] => Equal2.IN0
reg_sel[1] => Equal3.IN6
reg_sel[1] => Equal4.IN7
reg_sel[1] => Equal5.IN1
reg_sel[1] => Equal6.IN6
reg_sel[1] => Equal7.IN7
reg_sel[1] => Equal8.IN1
reg_sel[1] => Equal9.IN1
reg_sel[1] => Equal10.IN6
reg_sel[1] => Equal11.IN7
reg_sel[1] => Equal12.IN2
reg_sel[1] => Equal13.IN2
reg_sel[1] => Equal14.IN6
reg_sel[1] => Equal15.IN2
reg_sel[1] => Equal16.IN2
reg_sel[1] => Equal17.IN3
reg_sel[1] => Equal18.IN3
reg_sel[2] => LessThan0.IN14
reg_sel[2] => LessThan1.IN14
reg_sel[2] => LessThan2.IN14
reg_sel[2] => Decoder0.IN5
reg_sel[2] => mdio_addr_reg[2].DATAIN
reg_sel[2] => Equal0.IN6
reg_sel[2] => Equal1.IN6
reg_sel[2] => Equal2.IN7
reg_sel[2] => Equal3.IN0
reg_sel[2] => Equal4.IN0
reg_sel[2] => Equal5.IN0
reg_sel[2] => Equal6.IN5
reg_sel[2] => Equal7.IN6
reg_sel[2] => Equal8.IN6
reg_sel[2] => Equal9.IN7
reg_sel[2] => Equal10.IN1
reg_sel[2] => Equal11.IN1
reg_sel[2] => Equal12.IN1
reg_sel[2] => Equal13.IN1
reg_sel[2] => Equal14.IN5
reg_sel[2] => Equal15.IN1
reg_sel[2] => Equal16.IN1
reg_sel[2] => Equal17.IN6
reg_sel[2] => Equal18.IN7
reg_sel[3] => LessThan0.IN13
reg_sel[3] => LessThan1.IN13
reg_sel[3] => LessThan2.IN13
reg_sel[3] => Decoder0.IN4
reg_sel[3] => mdio_addr_reg[3].DATAIN
reg_sel[3] => Equal0.IN5
reg_sel[3] => Equal1.IN5
reg_sel[3] => Equal2.IN6
reg_sel[3] => Equal3.IN5
reg_sel[3] => Equal4.IN6
reg_sel[3] => Equal5.IN7
reg_sel[3] => Equal6.IN0
reg_sel[3] => Equal7.IN0
reg_sel[3] => Equal8.IN0
reg_sel[3] => Equal9.IN0
reg_sel[3] => Equal10.IN0
reg_sel[3] => Equal11.IN0
reg_sel[3] => Equal12.IN0
reg_sel[3] => Equal13.IN0
reg_sel[3] => Equal14.IN4
reg_sel[3] => Equal15.IN7
reg_sel[3] => Equal16.IN6
reg_sel[3] => Equal17.IN2
reg_sel[3] => Equal18.IN2
reg_sel[4] => LessThan0.IN12
reg_sel[4] => LessThan1.IN12
reg_sel[4] => LessThan2.IN12
reg_sel[4] => Decoder0.IN3
reg_sel[4] => mdio_addr_reg[4].DATAIN
reg_sel[4] => Equal0.IN4
reg_sel[4] => Equal1.IN4
reg_sel[4] => Equal2.IN5
reg_sel[4] => Equal3.IN4
reg_sel[4] => Equal4.IN5
reg_sel[4] => Equal5.IN6
reg_sel[4] => Equal6.IN4
reg_sel[4] => Equal7.IN5
reg_sel[4] => Equal8.IN5
reg_sel[4] => Equal9.IN6
reg_sel[4] => Equal10.IN5
reg_sel[4] => Equal11.IN6
reg_sel[4] => Equal12.IN6
reg_sel[4] => Equal13.IN7
reg_sel[4] => Equal14.IN0
reg_sel[4] => Equal15.IN0
reg_sel[4] => Equal16.IN0
reg_sel[4] => Equal17.IN1
reg_sel[4] => Equal18.IN1
reg_sel[5] => LessThan0.IN11
reg_sel[5] => LessThan1.IN11
reg_sel[5] => LessThan2.IN11
reg_sel[5] => Decoder0.IN2
reg_sel[5] => Equal0.IN3
reg_sel[5] => Equal1.IN3
reg_sel[5] => Equal2.IN4
reg_sel[5] => Equal3.IN3
reg_sel[5] => Equal4.IN4
reg_sel[5] => Equal5.IN5
reg_sel[5] => Equal6.IN3
reg_sel[5] => Equal7.IN4
reg_sel[5] => Equal8.IN4
reg_sel[5] => Equal9.IN5
reg_sel[5] => Equal10.IN4
reg_sel[5] => Equal11.IN5
reg_sel[5] => Equal12.IN5
reg_sel[5] => Equal13.IN6
reg_sel[5] => Equal14.IN3
reg_sel[5] => Equal15.IN6
reg_sel[5] => Equal16.IN5
reg_sel[5] => Equal17.IN0
reg_sel[5] => Equal18.IN0
reg_sel[6] => LessThan0.IN10
reg_sel[6] => LessThan1.IN10
reg_sel[6] => LessThan2.IN10
reg_sel[6] => Decoder0.IN1
reg_sel[6] => Equal0.IN2
reg_sel[6] => Equal1.IN2
reg_sel[6] => Equal2.IN3
reg_sel[6] => Equal3.IN2
reg_sel[6] => Equal4.IN3
reg_sel[6] => Equal5.IN4
reg_sel[6] => Equal6.IN2
reg_sel[6] => Equal7.IN3
reg_sel[6] => Equal8.IN3
reg_sel[6] => Equal9.IN4
reg_sel[6] => Equal10.IN3
reg_sel[6] => Equal11.IN4
reg_sel[6] => Equal12.IN4
reg_sel[6] => Equal13.IN5
reg_sel[6] => Equal14.IN2
reg_sel[6] => Equal15.IN5
reg_sel[6] => Equal16.IN4
reg_sel[6] => Equal17.IN5
reg_sel[6] => Equal18.IN6
reg_sel[7] => LessThan0.IN9
reg_sel[7] => LessThan1.IN9
reg_sel[7] => LessThan2.IN9
reg_sel[7] => Decoder0.IN0
reg_sel[7] => Equal0.IN1
reg_sel[7] => Equal1.IN1
reg_sel[7] => Equal2.IN2
reg_sel[7] => Equal3.IN1
reg_sel[7] => Equal4.IN2
reg_sel[7] => Equal5.IN3
reg_sel[7] => Equal6.IN1
reg_sel[7] => Equal7.IN2
reg_sel[7] => Equal8.IN2
reg_sel[7] => Equal9.IN3
reg_sel[7] => Equal10.IN2
reg_sel[7] => Equal11.IN3
reg_sel[7] => Equal12.IN3
reg_sel[7] => Equal13.IN4
reg_sel[7] => Equal14.IN1
reg_sel[7] => Equal15.IN4
reg_sel[7] => Equal16.IN3
reg_sel[7] => Equal17.IN4
reg_sel[7] => Equal18.IN5
reg_data_in[0] => command_config.DATAB
reg_data_in[0] => mdio_data_out_reg[0].DATAIN
reg_data_in[0] => scratch[0].DATAIN
reg_data_in[0] => mac_0[0].DATAIN
reg_data_in[0] => mac_1[0].DATAIN
reg_data_in[0] => frm_length[0].DATAIN
reg_data_in[0] => rx_section_empty_reg[0].DATAIN
reg_data_in[0] => rx_section_full_reg[0].DATAIN
reg_data_in[0] => tx_section_empty_reg[0].DATAIN
reg_data_in[0] => tx_section_full_reg[0].DATAIN
reg_data_in[0] => rx_ae_level_reg[0].DATAIN
reg_data_in[0] => rx_af_level_reg[0].DATAIN
reg_data_in[0] => tx_ae_level_reg[0].DATAIN
reg_data_in[0] => tx_af_level_reg[0].DATAIN
reg_data_in[0] => mdio_addr0[0].DATAIN
reg_data_in[0] => mdio_addr1[0].DATAIN
reg_data_in[0] => tx_ipg_len_reg[0].DATAIN
reg_data_in[1] => command_config.DATAB
reg_data_in[1] => mdio_data_out_reg[1].DATAIN
reg_data_in[1] => scratch[1].DATAIN
reg_data_in[1] => mac_0[1].DATAIN
reg_data_in[1] => mac_1[1].DATAIN
reg_data_in[1] => frm_length[1].DATAIN
reg_data_in[1] => rx_section_empty_reg[1].DATAIN
reg_data_in[1] => rx_section_full_reg[1].DATAIN
reg_data_in[1] => tx_section_empty_reg[1].DATAIN
reg_data_in[1] => tx_section_full_reg[1].DATAIN
reg_data_in[1] => rx_ae_level_reg[1].DATAIN
reg_data_in[1] => rx_af_level_reg[1].DATAIN
reg_data_in[1] => tx_ae_level_reg[1].DATAIN
reg_data_in[1] => tx_af_level_reg[1].DATAIN
reg_data_in[1] => mdio_addr0[1].DATAIN
reg_data_in[1] => mdio_addr1[1].DATAIN
reg_data_in[1] => tx_ipg_len_reg[1].DATAIN
reg_data_in[2] => mdio_data_out_reg[2].DATAIN
reg_data_in[2] => scratch[2].DATAIN
reg_data_in[2] => command_config[2].DATAIN
reg_data_in[2] => mac_0[2].DATAIN
reg_data_in[2] => mac_1[2].DATAIN
reg_data_in[2] => frm_length[2].DATAIN
reg_data_in[2] => rx_section_empty_reg[2].DATAIN
reg_data_in[2] => rx_section_full_reg[2].DATAIN
reg_data_in[2] => tx_section_empty_reg[2].DATAIN
reg_data_in[2] => tx_section_full_reg[2].DATAIN
reg_data_in[2] => rx_ae_level_reg[2].DATAIN
reg_data_in[2] => rx_af_level_reg[2].DATAIN
reg_data_in[2] => tx_ae_level_reg[2].DATAIN
reg_data_in[2] => tx_af_level_reg[2].DATAIN
reg_data_in[2] => mdio_addr0[2].DATAIN
reg_data_in[2] => mdio_addr1[2].DATAIN
reg_data_in[2] => tx_ipg_len_reg[2].DATAIN
reg_data_in[3] => mdio_data_out_reg[3].DATAIN
reg_data_in[3] => scratch[3].DATAIN
reg_data_in[3] => command_config[3].DATAIN
reg_data_in[3] => mac_0[3].DATAIN
reg_data_in[3] => mac_1[3].DATAIN
reg_data_in[3] => frm_length[3].DATAIN
reg_data_in[3] => rx_section_empty_reg[3].DATAIN
reg_data_in[3] => rx_section_full_reg[3].DATAIN
reg_data_in[3] => tx_section_empty_reg[3].DATAIN
reg_data_in[3] => tx_section_full_reg[3].DATAIN
reg_data_in[3] => rx_ae_level_reg[3].DATAIN
reg_data_in[3] => rx_af_level_reg[3].DATAIN
reg_data_in[3] => tx_ae_level_reg[3].DATAIN
reg_data_in[3] => tx_af_level_reg[3].DATAIN
reg_data_in[3] => mdio_addr0[3].DATAIN
reg_data_in[3] => mdio_addr1[3].DATAIN
reg_data_in[3] => tx_ipg_len_reg[3].DATAIN
reg_data_in[4] => mdio_data_out_reg[4].DATAIN
reg_data_in[4] => scratch[4].DATAIN
reg_data_in[4] => command_config[4].DATAIN
reg_data_in[4] => mac_0[4].DATAIN
reg_data_in[4] => mac_1[4].DATAIN
reg_data_in[4] => frm_length[4].DATAIN
reg_data_in[4] => rx_section_empty_reg[4].DATAIN
reg_data_in[4] => rx_section_full_reg[4].DATAIN
reg_data_in[4] => tx_section_empty_reg[4].DATAIN
reg_data_in[4] => tx_section_full_reg[4].DATAIN
reg_data_in[4] => rx_ae_level_reg[4].DATAIN
reg_data_in[4] => rx_af_level_reg[4].DATAIN
reg_data_in[4] => tx_ae_level_reg[4].DATAIN
reg_data_in[4] => tx_af_level_reg[4].DATAIN
reg_data_in[4] => mdio_addr0[4].DATAIN
reg_data_in[4] => mdio_addr1[4].DATAIN
reg_data_in[4] => tx_ipg_len_reg[4].DATAIN
reg_data_in[5] => mdio_data_out_reg[5].DATAIN
reg_data_in[5] => scratch[5].DATAIN
reg_data_in[5] => command_config[5].DATAIN
reg_data_in[5] => mac_0[5].DATAIN
reg_data_in[5] => mac_1[5].DATAIN
reg_data_in[5] => frm_length[5].DATAIN
reg_data_in[5] => rx_section_empty_reg[5].DATAIN
reg_data_in[5] => rx_section_full_reg[5].DATAIN
reg_data_in[5] => tx_section_empty_reg[5].DATAIN
reg_data_in[5] => tx_section_full_reg[5].DATAIN
reg_data_in[5] => rx_ae_level_reg[5].DATAIN
reg_data_in[5] => rx_af_level_reg[5].DATAIN
reg_data_in[5] => tx_ae_level_reg[5].DATAIN
reg_data_in[5] => tx_af_level_reg[5].DATAIN
reg_data_in[6] => mdio_data_out_reg[6].DATAIN
reg_data_in[6] => scratch[6].DATAIN
reg_data_in[6] => command_config[6].DATAIN
reg_data_in[6] => mac_0[6].DATAIN
reg_data_in[6] => mac_1[6].DATAIN
reg_data_in[6] => frm_length[6].DATAIN
reg_data_in[6] => rx_section_empty_reg[6].DATAIN
reg_data_in[6] => rx_section_full_reg[6].DATAIN
reg_data_in[6] => tx_section_empty_reg[6].DATAIN
reg_data_in[6] => tx_section_full_reg[6].DATAIN
reg_data_in[6] => rx_ae_level_reg[6].DATAIN
reg_data_in[6] => rx_af_level_reg[6].DATAIN
reg_data_in[6] => tx_ae_level_reg[6].DATAIN
reg_data_in[6] => tx_af_level_reg[6].DATAIN
reg_data_in[7] => mdio_data_out_reg[7].DATAIN
reg_data_in[7] => scratch[7].DATAIN
reg_data_in[7] => command_config[7].DATAIN
reg_data_in[7] => mac_0[7].DATAIN
reg_data_in[7] => mac_1[7].DATAIN
reg_data_in[7] => frm_length[7].DATAIN
reg_data_in[7] => rx_section_empty_reg[7].DATAIN
reg_data_in[7] => rx_section_full_reg[7].DATAIN
reg_data_in[7] => tx_section_empty_reg[7].DATAIN
reg_data_in[7] => tx_section_full_reg[7].DATAIN
reg_data_in[7] => rx_ae_level_reg[7].DATAIN
reg_data_in[7] => rx_af_level_reg[7].DATAIN
reg_data_in[7] => tx_ae_level_reg[7].DATAIN
reg_data_in[7] => tx_af_level_reg[7].DATAIN
reg_data_in[8] => mdio_data_out_reg[8].DATAIN
reg_data_in[8] => scratch[8].DATAIN
reg_data_in[8] => command_config[8].DATAIN
reg_data_in[8] => mac_0[8].DATAIN
reg_data_in[8] => mac_1[8].DATAIN
reg_data_in[8] => frm_length[8].DATAIN
reg_data_in[8] => rx_section_empty_reg[8].DATAIN
reg_data_in[8] => rx_section_full_reg[8].DATAIN
reg_data_in[8] => tx_section_empty_reg[8].DATAIN
reg_data_in[8] => tx_section_full_reg[8].DATAIN
reg_data_in[8] => rx_ae_level_reg[8].DATAIN
reg_data_in[8] => rx_af_level_reg[8].DATAIN
reg_data_in[8] => tx_ae_level_reg[8].DATAIN
reg_data_in[8] => tx_af_level_reg[8].DATAIN
reg_data_in[9] => mdio_data_out_reg[9].DATAIN
reg_data_in[9] => scratch[9].DATAIN
reg_data_in[9] => command_config[9].DATAIN
reg_data_in[9] => mac_0[9].DATAIN
reg_data_in[9] => mac_1[9].DATAIN
reg_data_in[9] => frm_length[9].DATAIN
reg_data_in[9] => rx_section_empty_reg[9].DATAIN
reg_data_in[9] => rx_section_full_reg[9].DATAIN
reg_data_in[9] => tx_section_empty_reg[9].DATAIN
reg_data_in[9] => tx_section_full_reg[9].DATAIN
reg_data_in[9] => rx_ae_level_reg[9].DATAIN
reg_data_in[9] => rx_af_level_reg[9].DATAIN
reg_data_in[9] => tx_ae_level_reg[9].DATAIN
reg_data_in[9] => tx_af_level_reg[9].DATAIN
reg_data_in[10] => mdio_data_out_reg[10].DATAIN
reg_data_in[10] => scratch[10].DATAIN
reg_data_in[10] => mac_0[10].DATAIN
reg_data_in[10] => mac_1[10].DATAIN
reg_data_in[10] => frm_length[10].DATAIN
reg_data_in[10] => rx_section_empty_reg[10].DATAIN
reg_data_in[10] => rx_section_full_reg[10].DATAIN
reg_data_in[10] => tx_section_empty_reg[10].DATAIN
reg_data_in[10] => tx_section_full_reg[10].DATAIN
reg_data_in[10] => rx_ae_level_reg[10].DATAIN
reg_data_in[10] => rx_af_level_reg[10].DATAIN
reg_data_in[10] => tx_ae_level_reg[10].DATAIN
reg_data_in[10] => tx_af_level_reg[10].DATAIN
reg_data_in[11] => mdio_data_out_reg[11].DATAIN
reg_data_in[11] => scratch[11].DATAIN
reg_data_in[11] => mac_0[11].DATAIN
reg_data_in[11] => mac_1[11].DATAIN
reg_data_in[11] => frm_length[11].DATAIN
reg_data_in[12] => mdio_data_out_reg[12].DATAIN
reg_data_in[12] => scratch[12].DATAIN
reg_data_in[12] => mac_0[12].DATAIN
reg_data_in[12] => mac_1[12].DATAIN
reg_data_in[12] => frm_length[12].DATAIN
reg_data_in[13] => command_config.DATAB
reg_data_in[13] => mdio_data_out_reg[13].DATAIN
reg_data_in[13] => scratch[13].DATAIN
reg_data_in[13] => mac_0[13].DATAIN
reg_data_in[13] => mac_1[13].DATAIN
reg_data_in[13] => frm_length[13].DATAIN
reg_data_in[14] => mdio_data_out_reg[14].DATAIN
reg_data_in[14] => scratch[14].DATAIN
reg_data_in[14] => command_config[14].DATAIN
reg_data_in[14] => mac_0[14].DATAIN
reg_data_in[14] => mac_1[14].DATAIN
reg_data_in[14] => frm_length[14].DATAIN
reg_data_in[15] => mdio_data_out_reg[15].DATAIN
reg_data_in[15] => scratch[15].DATAIN
reg_data_in[15] => command_config[15].DATAIN
reg_data_in[15] => mac_0[15].DATAIN
reg_data_in[15] => mac_1[15].DATAIN
reg_data_in[15] => frm_length[15].DATAIN
reg_data_in[16] => scratch[16].DATAIN
reg_data_in[16] => command_config[16].DATAIN
reg_data_in[16] => mac_0[16].DATAIN
reg_data_in[17] => scratch[17].DATAIN
reg_data_in[17] => command_config[17].DATAIN
reg_data_in[17] => mac_0[17].DATAIN
reg_data_in[17] => tx_command_status[17].DATAIN
reg_data_in[18] => scratch[18].DATAIN
reg_data_in[18] => command_config[18].DATAIN
reg_data_in[18] => mac_0[18].DATAIN
reg_data_in[18] => tx_command_status[18].DATAIN
reg_data_in[19] => scratch[19].DATAIN
reg_data_in[19] => command_config[19].DATAIN
reg_data_in[19] => mac_0[19].DATAIN
reg_data_in[20] => scratch[20].DATAIN
reg_data_in[20] => command_config[20].DATAIN
reg_data_in[20] => mac_0[20].DATAIN
reg_data_in[21] => scratch[21].DATAIN
reg_data_in[21] => mac_0[21].DATAIN
reg_data_in[22] => scratch[22].DATAIN
reg_data_in[22] => command_config[22].DATAIN
reg_data_in[22] => mac_0[22].DATAIN
reg_data_in[23] => scratch[23].DATAIN
reg_data_in[23] => command_config[23].DATAIN
reg_data_in[23] => mac_0[23].DATAIN
reg_data_in[24] => scratch[24].DATAIN
reg_data_in[24] => command_config[24].DATAIN
reg_data_in[24] => mac_0[24].DATAIN
reg_data_in[25] => scratch[25].DATAIN
reg_data_in[25] => command_config[25].DATAIN
reg_data_in[25] => mac_0[25].DATAIN
reg_data_in[25] => rx_command_status[25].DATAIN
reg_data_in[26] => scratch[26].DATAIN
reg_data_in[26] => command_config[26].DATAIN
reg_data_in[26] => mac_0[26].DATAIN
reg_data_in[27] => scratch[27].DATAIN
reg_data_in[27] => command_config[27].DATAIN
reg_data_in[27] => mac_0[27].DATAIN
reg_data_in[28] => scratch[28].DATAIN
reg_data_in[28] => mac_0[28].DATAIN
reg_data_in[29] => scratch[29].DATAIN
reg_data_in[29] => mac_0[29].DATAIN
reg_data_in[30] => scratch[30].DATAIN
reg_data_in[30] => mac_0[30].DATAIN
reg_data_in[31] => command_config.DATAB
reg_data_in[31] => scratch[31].DATAIN
reg_data_in[31] => mac_0[31].DATAIN
reg_data_out[0] <= reg_data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[1] <= reg_data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[2] <= reg_data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[3] <= reg_data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[4] <= reg_data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[5] <= reg_data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[6] <= reg_data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[7] <= reg_data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[8] <= reg_data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[9] <= reg_data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[10] <= reg_data_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[11] <= reg_data_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[12] <= reg_data_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[13] <= reg_data_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[14] <= reg_data_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[15] <= reg_data_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[16] <= reg_data_out[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[17] <= reg_data_out[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[18] <= reg_data_out[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[19] <= reg_data_out[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[20] <= reg_data_out[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[21] <= reg_data_out[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[22] <= reg_data_out[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[23] <= reg_data_out[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[24] <= reg_data_out[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[25] <= reg_data_out[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[26] <= reg_data_out[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[27] <= reg_data_out[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[28] <= reg_data_out[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[29] <= reg_data_out[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[30] <= reg_data_out[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[31] <= reg_data_out[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
busy <= mdio_busy.DB_MAX_OUTPUT_PORT_TYPE
rx_section_empty[0] <= rx_section_empty_reg[0].DB_MAX_OUTPUT_PORT_TYPE
rx_section_empty[1] <= rx_section_empty_reg[1].DB_MAX_OUTPUT_PORT_TYPE
rx_section_empty[2] <= rx_section_empty_reg[2].DB_MAX_OUTPUT_PORT_TYPE
rx_section_empty[3] <= rx_section_empty_reg[3].DB_MAX_OUTPUT_PORT_TYPE
rx_section_empty[4] <= rx_section_empty_reg[4].DB_MAX_OUTPUT_PORT_TYPE
rx_section_empty[5] <= rx_section_empty_reg[5].DB_MAX_OUTPUT_PORT_TYPE
rx_section_empty[6] <= rx_section_empty_reg[6].DB_MAX_OUTPUT_PORT_TYPE
rx_section_empty[7] <= rx_section_empty_reg[7].DB_MAX_OUTPUT_PORT_TYPE
rx_section_empty[8] <= rx_section_empty_reg[8].DB_MAX_OUTPUT_PORT_TYPE
rx_section_empty[9] <= rx_section_empty_reg[9].DB_MAX_OUTPUT_PORT_TYPE
rx_section_empty[10] <= rx_section_empty_reg[10].DB_MAX_OUTPUT_PORT_TYPE
rx_section_full[0] <= rx_section_full_reg[0].DB_MAX_OUTPUT_PORT_TYPE
rx_section_full[1] <= rx_section_full_reg[1].DB_MAX_OUTPUT_PORT_TYPE
rx_section_full[2] <= rx_section_full_reg[2].DB_MAX_OUTPUT_PORT_TYPE
rx_section_full[3] <= rx_section_full_reg[3].DB_MAX_OUTPUT_PORT_TYPE
rx_section_full[4] <= rx_section_full_reg[4].DB_MAX_OUTPUT_PORT_TYPE
rx_section_full[5] <= rx_section_full_reg[5].DB_MAX_OUTPUT_PORT_TYPE
rx_section_full[6] <= rx_section_full_reg[6].DB_MAX_OUTPUT_PORT_TYPE
rx_section_full[7] <= rx_section_full_reg[7].DB_MAX_OUTPUT_PORT_TYPE
rx_section_full[8] <= rx_section_full_reg[8].DB_MAX_OUTPUT_PORT_TYPE
rx_section_full[9] <= rx_section_full_reg[9].DB_MAX_OUTPUT_PORT_TYPE
rx_section_full[10] <= rx_section_full_reg[10].DB_MAX_OUTPUT_PORT_TYPE
tx_section_empty[0] <= tx_section_empty_reg[0].DB_MAX_OUTPUT_PORT_TYPE
tx_section_empty[1] <= tx_section_empty_reg[1].DB_MAX_OUTPUT_PORT_TYPE
tx_section_empty[2] <= tx_section_empty_reg[2].DB_MAX_OUTPUT_PORT_TYPE
tx_section_empty[3] <= tx_section_empty_reg[3].DB_MAX_OUTPUT_PORT_TYPE
tx_section_empty[4] <= tx_section_empty_reg[4].DB_MAX_OUTPUT_PORT_TYPE
tx_section_empty[5] <= tx_section_empty_reg[5].DB_MAX_OUTPUT_PORT_TYPE
tx_section_empty[6] <= tx_section_empty_reg[6].DB_MAX_OUTPUT_PORT_TYPE
tx_section_empty[7] <= tx_section_empty_reg[7].DB_MAX_OUTPUT_PORT_TYPE
tx_section_empty[8] <= tx_section_empty_reg[8].DB_MAX_OUTPUT_PORT_TYPE
tx_section_empty[9] <= tx_section_empty_reg[9].DB_MAX_OUTPUT_PORT_TYPE
tx_section_empty[10] <= tx_section_empty_reg[10].DB_MAX_OUTPUT_PORT_TYPE
tx_section_full[0] <= tx_section_full_reg[0].DB_MAX_OUTPUT_PORT_TYPE
tx_section_full[1] <= tx_section_full_reg[1].DB_MAX_OUTPUT_PORT_TYPE
tx_section_full[2] <= tx_section_full_reg[2].DB_MAX_OUTPUT_PORT_TYPE
tx_section_full[3] <= tx_section_full_reg[3].DB_MAX_OUTPUT_PORT_TYPE
tx_section_full[4] <= tx_section_full_reg[4].DB_MAX_OUTPUT_PORT_TYPE
tx_section_full[5] <= tx_section_full_reg[5].DB_MAX_OUTPUT_PORT_TYPE
tx_section_full[6] <= tx_section_full_reg[6].DB_MAX_OUTPUT_PORT_TYPE
tx_section_full[7] <= tx_section_full_reg[7].DB_MAX_OUTPUT_PORT_TYPE
tx_section_full[8] <= tx_section_full_reg[8].DB_MAX_OUTPUT_PORT_TYPE
tx_section_full[9] <= tx_section_full_reg[9].DB_MAX_OUTPUT_PORT_TYPE
tx_section_full[10] <= tx_section_full_reg[10].DB_MAX_OUTPUT_PORT_TYPE
rx_ae_level[0] <= rx_ae_level_reg[0].DB_MAX_OUTPUT_PORT_TYPE
rx_ae_level[1] <= rx_ae_level_reg[1].DB_MAX_OUTPUT_PORT_TYPE
rx_ae_level[2] <= rx_ae_level_reg[2].DB_MAX_OUTPUT_PORT_TYPE
rx_ae_level[3] <= rx_ae_level_reg[3].DB_MAX_OUTPUT_PORT_TYPE
rx_ae_level[4] <= rx_ae_level_reg[4].DB_MAX_OUTPUT_PORT_TYPE
rx_ae_level[5] <= rx_ae_level_reg[5].DB_MAX_OUTPUT_PORT_TYPE
rx_ae_level[6] <= rx_ae_level_reg[6].DB_MAX_OUTPUT_PORT_TYPE
rx_ae_level[7] <= rx_ae_level_reg[7].DB_MAX_OUTPUT_PORT_TYPE
rx_ae_level[8] <= rx_ae_level_reg[8].DB_MAX_OUTPUT_PORT_TYPE
rx_ae_level[9] <= rx_ae_level_reg[9].DB_MAX_OUTPUT_PORT_TYPE
rx_ae_level[10] <= rx_ae_level_reg[10].DB_MAX_OUTPUT_PORT_TYPE
rx_af_level[0] <= rx_af_level_reg[0].DB_MAX_OUTPUT_PORT_TYPE
rx_af_level[1] <= rx_af_level_reg[1].DB_MAX_OUTPUT_PORT_TYPE
rx_af_level[2] <= rx_af_level_reg[2].DB_MAX_OUTPUT_PORT_TYPE
rx_af_level[3] <= rx_af_level_reg[3].DB_MAX_OUTPUT_PORT_TYPE
rx_af_level[4] <= rx_af_level_reg[4].DB_MAX_OUTPUT_PORT_TYPE
rx_af_level[5] <= rx_af_level_reg[5].DB_MAX_OUTPUT_PORT_TYPE
rx_af_level[6] <= rx_af_level_reg[6].DB_MAX_OUTPUT_PORT_TYPE
rx_af_level[7] <= rx_af_level_reg[7].DB_MAX_OUTPUT_PORT_TYPE
rx_af_level[8] <= rx_af_level_reg[8].DB_MAX_OUTPUT_PORT_TYPE
rx_af_level[9] <= rx_af_level_reg[9].DB_MAX_OUTPUT_PORT_TYPE
rx_af_level[10] <= rx_af_level_reg[10].DB_MAX_OUTPUT_PORT_TYPE
tx_ae_level[0] <= tx_ae_level_reg[0].DB_MAX_OUTPUT_PORT_TYPE
tx_ae_level[1] <= tx_ae_level_reg[1].DB_MAX_OUTPUT_PORT_TYPE
tx_ae_level[2] <= tx_ae_level_reg[2].DB_MAX_OUTPUT_PORT_TYPE
tx_ae_level[3] <= tx_ae_level_reg[3].DB_MAX_OUTPUT_PORT_TYPE
tx_ae_level[4] <= tx_ae_level_reg[4].DB_MAX_OUTPUT_PORT_TYPE
tx_ae_level[5] <= tx_ae_level_reg[5].DB_MAX_OUTPUT_PORT_TYPE
tx_ae_level[6] <= tx_ae_level_reg[6].DB_MAX_OUTPUT_PORT_TYPE
tx_ae_level[7] <= tx_ae_level_reg[7].DB_MAX_OUTPUT_PORT_TYPE
tx_ae_level[8] <= tx_ae_level_reg[8].DB_MAX_OUTPUT_PORT_TYPE
tx_ae_level[9] <= tx_ae_level_reg[9].DB_MAX_OUTPUT_PORT_TYPE
tx_ae_level[10] <= tx_ae_level_reg[10].DB_MAX_OUTPUT_PORT_TYPE
tx_af_level[0] <= tx_af_level_reg[0].DB_MAX_OUTPUT_PORT_TYPE
tx_af_level[1] <= tx_af_level_reg[1].DB_MAX_OUTPUT_PORT_TYPE
tx_af_level[2] <= tx_af_level_reg[2].DB_MAX_OUTPUT_PORT_TYPE
tx_af_level[3] <= tx_af_level_reg[3].DB_MAX_OUTPUT_PORT_TYPE
tx_af_level[4] <= tx_af_level_reg[4].DB_MAX_OUTPUT_PORT_TYPE
tx_af_level[5] <= tx_af_level_reg[5].DB_MAX_OUTPUT_PORT_TYPE
tx_af_level[6] <= tx_af_level_reg[6].DB_MAX_OUTPUT_PORT_TYPE
tx_af_level[7] <= tx_af_level_reg[7].DB_MAX_OUTPUT_PORT_TYPE
tx_af_level[8] <= tx_af_level_reg[8].DB_MAX_OUTPUT_PORT_TYPE
tx_af_level[9] <= tx_af_level_reg[9].DB_MAX_OUTPUT_PORT_TYPE
tx_af_level[10] <= tx_af_level_reg[10].DB_MAX_OUTPUT_PORT_TYPE
excess_col => excess_col.IN1
late_col => late_col.IN1
mac_addr[0] <= mac_0[0].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[1] <= mac_0[1].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[2] <= mac_0[2].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[3] <= mac_0[3].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[4] <= mac_0[4].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[5] <= mac_0[5].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[6] <= mac_0[6].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[7] <= mac_0[7].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[8] <= mac_0[8].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[9] <= mac_0[9].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[10] <= mac_0[10].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[11] <= mac_0[11].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[12] <= mac_0[12].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[13] <= mac_0[13].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[14] <= mac_0[14].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[15] <= mac_0[15].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[16] <= mac_0[16].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[17] <= mac_0[17].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[18] <= mac_0[18].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[19] <= mac_0[19].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[20] <= mac_0[20].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[21] <= mac_0[21].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[22] <= mac_0[22].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[23] <= mac_0[23].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[24] <= mac_0[24].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[25] <= mac_0[25].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[26] <= mac_0[26].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[27] <= mac_0[27].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[28] <= mac_0[28].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[29] <= mac_0[29].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[30] <= mac_0[30].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[31] <= mac_0[31].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[32] <= mac_1[0].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[33] <= mac_1[1].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[34] <= mac_1[2].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[35] <= mac_1[3].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[36] <= mac_1[4].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[37] <= mac_1[5].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[38] <= mac_1[6].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[39] <= mac_1[7].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[40] <= mac_1[8].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[41] <= mac_1[9].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[42] <= mac_1[10].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[43] <= mac_1[11].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[44] <= mac_1[12].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[45] <= mac_1[13].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[46] <= mac_1[14].DB_MAX_OUTPUT_PORT_TYPE
mac_addr[47] <= mac_1[15].DB_MAX_OUTPUT_PORT_TYPE
pause_quant[0] <= <GND>
pause_quant[1] <= <GND>
pause_quant[2] <= <GND>
pause_quant[3] <= <GND>
pause_quant[4] <= <GND>
pause_quant[5] <= <GND>
pause_quant[6] <= <GND>
pause_quant[7] <= <GND>
pause_quant[8] <= <GND>
pause_quant[9] <= <GND>
pause_quant[10] <= <GND>
pause_quant[11] <= <GND>
pause_quant[12] <= <GND>
pause_quant[13] <= <GND>
pause_quant[14] <= <GND>
pause_quant[15] <= <GND>
holdoff_quant[0] <= holdoff_quant[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[1] <= holdoff_quant[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[2] <= holdoff_quant[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[3] <= holdoff_quant[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[4] <= holdoff_quant[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[5] <= holdoff_quant[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[6] <= holdoff_quant[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[7] <= holdoff_quant[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[8] <= holdoff_quant[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[9] <= holdoff_quant[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[10] <= holdoff_quant[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[11] <= holdoff_quant[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[12] <= holdoff_quant[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[13] <= holdoff_quant[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[14] <= holdoff_quant[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
holdoff_quant[15] <= holdoff_quant[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
promis_en <= command_config[4].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[0] <= frm_length[0].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[1] <= frm_length[1].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[2] <= frm_length[2].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[3] <= frm_length[3].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[4] <= frm_length[4].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[5] <= frm_length[5].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[6] <= frm_length[6].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[7] <= frm_length[7].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[8] <= frm_length[8].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[9] <= frm_length[9].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[10] <= frm_length[10].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[11] <= frm_length[11].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[12] <= frm_length[12].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[13] <= frm_length[13].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[14] <= frm_length[14].DB_MAX_OUTPUT_PORT_TYPE
frm_length_max[15] <= frm_length[15].DB_MAX_OUTPUT_PORT_TYPE
pause_fwd <= <GND>
pause_ignore <= <GND>
crc_fwd <= command_config[6].DB_MAX_OUTPUT_PORT_TYPE
pad_ena <= command_config[5].DB_MAX_OUTPUT_PORT_TYPE
ethernet_mode <= ethernet_mode~reg0.DB_MAX_OUTPUT_PORT_TYPE
eth_mode <= eth_mode~reg0.DB_MAX_OUTPUT_PORT_TYPE
enable_tx <= enable_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
enable_rx <= enable_rx~reg0.DB_MAX_OUTPUT_PORT_TYPE
hd_ena <= <GND>
tx_addr_ins <= command_config[9].DB_MAX_OUTPUT_PORT_TYPE
sw_reset <= command_config[13].DB_MAX_OUTPUT_PORT_TYPE
tx_done => tx_done.IN1
mhash_sel <= command_config[14].DB_MAX_OUTPUT_PORT_TYPE
cmd_frm_ena <= command_config[23].DB_MAX_OUTPUT_PORT_TYPE
no_lgth_check <= command_config[24].DB_MAX_OUTPUT_PORT_TYPE
ena_10 <= ena_10~reg0.DB_MAX_OUTPUT_PORT_TYPE
set_1000 => ethernet_mode.DATAA
set_10 => ena_10.DATAA
rx_err_frm_disc <= command_config[26].DB_MAX_OUTPUT_PORT_TYPE
disable_rd_timeout <= command_config[27].DB_MAX_OUTPUT_PORT_TYPE
tx_ipg_len[0] <= tx_ipg_len_reg[0].DB_MAX_OUTPUT_PORT_TYPE
tx_ipg_len[1] <= tx_ipg_len_reg[1].DB_MAX_OUTPUT_PORT_TYPE
tx_ipg_len[2] <= tx_ipg_len_reg[2].DB_MAX_OUTPUT_PORT_TYPE
tx_ipg_len[3] <= tx_ipg_len_reg[3].DB_MAX_OUTPUT_PORT_TYPE
tx_ipg_len[4] <= tx_ipg_len_reg[4].DB_MAX_OUTPUT_PORT_TYPE
rx_reset_done => sw_reset_int.IN1
magic_ena <= command_config[19].DB_MAX_OUTPUT_PORT_TYPE
magic_detect => magic_detect.IN1
sleep_ena <= sleep_ena~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_sleepn => reg_sleepn.IN1
reg_wakeup <= command_config[21].DB_MAX_OUTPUT_PORT_TYPE
xoff_gen <= <GND>
xon_gen <= <GND>
tx_crc_fwd_out <= tx_command_status[17].DB_MAX_OUTPUT_PORT_TYPE
tx_shift16 <= tx_command_status[18].DB_MAX_OUTPUT_PORT_TYPE
rx_shift16 <= rx_command_status[25].DB_MAX_OUTPUT_PORT_TYPE
lut_wren <= <GND>
lut_wdata <= <GND>
lut_waddr[0] <= <GND>
lut_waddr[1] <= <GND>
lut_waddr[2] <= <GND>
lut_waddr[3] <= <GND>
lut_waddr[4] <= <GND>
lut_waddr[5] <= <GND>
mdio_data_in[0] => Selector31.IN63
mdio_data_in[1] => Selector30.IN62
mdio_data_in[2] => Selector29.IN62
mdio_data_in[3] => Selector28.IN62
mdio_data_in[4] => Selector27.IN62
mdio_data_in[5] => Selector26.IN63
mdio_data_in[6] => Selector25.IN63
mdio_data_in[7] => Selector24.IN63
mdio_data_in[8] => Selector23.IN65
mdio_data_in[9] => Selector22.IN63
mdio_data_in[10] => Selector21.IN66
mdio_data_in[11] => Selector20.IN73
mdio_data_in[12] => Selector19.IN71
mdio_data_in[13] => Selector18.IN71
mdio_data_in[14] => Selector17.IN71
mdio_data_in[15] => Selector16.IN71
mdio_data_out[0] <= mdio_data_out_reg[0].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[1] <= mdio_data_out_reg[1].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[2] <= mdio_data_out_reg[2].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[3] <= mdio_data_out_reg[3].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[4] <= mdio_data_out_reg[4].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[5] <= mdio_data_out_reg[5].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[6] <= mdio_data_out_reg[6].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[7] <= mdio_data_out_reg[7].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[8] <= mdio_data_out_reg[8].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[9] <= mdio_data_out_reg[9].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[10] <= mdio_data_out_reg[10].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[11] <= mdio_data_out_reg[11].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[12] <= mdio_data_out_reg[12].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[13] <= mdio_data_out_reg[13].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[14] <= mdio_data_out_reg[14].DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[15] <= mdio_data_out_reg[15].DB_MAX_OUTPUT_PORT_TYPE
mdio_dev_addr[0] <= mdio_dev_addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE
mdio_dev_addr[1] <= mdio_dev_addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE
mdio_dev_addr[2] <= mdio_dev_addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE
mdio_dev_addr[3] <= mdio_dev_addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE
mdio_dev_addr[4] <= mdio_dev_addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE
mdio_addr[0] <= mdio_addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE
mdio_addr[1] <= mdio_addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE
mdio_addr[2] <= mdio_addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE
mdio_addr[3] <= mdio_addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE
mdio_addr[4] <= mdio_addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE
mdio_cs <= mdio_cs_reg.DB_MAX_OUTPUT_PORT_TYPE
mdio_rd <= mdio_rd_reg.DB_MAX_OUTPUT_PORT_TYPE
mdio_wr <= mdio_wr_reg.DB_MAX_OUTPUT_PORT_TYPE
mdio_busy => busy.DATAIN
rx_total_lgth[0] => ~NO_FANOUT~
rx_total_lgth[1] => ~NO_FANOUT~
rx_total_lgth[2] => ~NO_FANOUT~
rx_total_lgth[3] => ~NO_FANOUT~
rx_total_lgth[4] => ~NO_FANOUT~
rx_total_lgth[5] => ~NO_FANOUT~
rx_total_lgth[6] => ~NO_FANOUT~
rx_total_lgth[7] => ~NO_FANOUT~
rx_total_lgth[8] => ~NO_FANOUT~
rx_total_lgth[9] => ~NO_FANOUT~
rx_total_lgth[10] => ~NO_FANOUT~
rx_total_lgth[11] => ~NO_FANOUT~
rx_total_lgth[12] => ~NO_FANOUT~
rx_total_lgth[13] => ~NO_FANOUT~
rx_total_lgth[14] => ~NO_FANOUT~
rx_total_lgth[15] => ~NO_FANOUT~
rx_total_val => ~NO_FANOUT~
rx_frm_stat_ena => ~NO_FANOUT~
rx_frm_stat_val => ~NO_FANOUT~
rx_frm_err => ~NO_FANOUT~
rx_frm_crc_err => ~NO_FANOUT~
rx_frm_length[0] => ~NO_FANOUT~
rx_frm_length[1] => ~NO_FANOUT~
rx_frm_length[2] => ~NO_FANOUT~
rx_frm_length[3] => ~NO_FANOUT~
rx_frm_length[4] => ~NO_FANOUT~
rx_frm_length[5] => ~NO_FANOUT~
rx_frm_length[6] => ~NO_FANOUT~
rx_frm_length[7] => ~NO_FANOUT~
rx_frm_length[8] => ~NO_FANOUT~
rx_frm_length[9] => ~NO_FANOUT~
rx_frm_length[10] => ~NO_FANOUT~
rx_frm_length[11] => ~NO_FANOUT~
rx_frm_length[12] => ~NO_FANOUT~
rx_frm_length[13] => ~NO_FANOUT~
rx_frm_length[14] => ~NO_FANOUT~
rx_frm_length[15] => ~NO_FANOUT~
rx_frm_vlan => ~NO_FANOUT~
rx_frm_stack_vlan => ~NO_FANOUT~
rx_frm_unicast => ~NO_FANOUT~
rx_frm_broadcast => ~NO_FANOUT~
rx_frm_mltcast => ~NO_FANOUT~
tx_frm_stat_val => ~NO_FANOUT~
tx_frm_err => ~NO_FANOUT~
tx_frm_length[0] => ~NO_FANOUT~
tx_frm_length[1] => ~NO_FANOUT~
tx_frm_length[2] => ~NO_FANOUT~
tx_frm_length[3] => ~NO_FANOUT~
tx_frm_length[4] => ~NO_FANOUT~
tx_frm_length[5] => ~NO_FANOUT~
tx_frm_length[6] => ~NO_FANOUT~
tx_frm_length[7] => ~NO_FANOUT~
tx_frm_length[8] => ~NO_FANOUT~
tx_frm_length[9] => ~NO_FANOUT~
tx_frm_length[10] => ~NO_FANOUT~
tx_frm_length[11] => ~NO_FANOUT~
tx_frm_length[12] => ~NO_FANOUT~
tx_frm_length[13] => ~NO_FANOUT~
tx_frm_length[14] => ~NO_FANOUT~
tx_frm_length[15] => ~NO_FANOUT~
tx_frm_unicast => ~NO_FANOUT~
tx_frm_broadcast => ~NO_FANOUT~
tx_frm_mltcast => ~NO_FANOUT~
pause_rcv => ~NO_FANOUT~
pause_tx => ~NO_FANOUT~
frm_align_err => ~NO_FANOUT~
frm_crc_err => ~NO_FANOUT~
long_crc_err => ~NO_FANOUT~
short_crc_err => ~NO_FANOUT~
frm_discard => ~NO_FANOUT~
gmii_loopback <= <GND>
smac_0[0] <= <GND>
smac_0[1] <= <GND>
smac_0[2] <= <GND>
smac_0[3] <= <GND>
smac_0[4] <= <GND>
smac_0[5] <= <GND>
smac_0[6] <= <GND>
smac_0[7] <= <GND>
smac_0[8] <= <GND>
smac_0[9] <= <GND>
smac_0[10] <= <GND>
smac_0[11] <= <GND>
smac_0[12] <= <GND>
smac_0[13] <= <GND>
smac_0[14] <= <GND>
smac_0[15] <= <GND>
smac_0[16] <= <GND>
smac_0[17] <= <GND>
smac_0[18] <= <GND>
smac_0[19] <= <GND>
smac_0[20] <= <GND>
smac_0[21] <= <GND>
smac_0[22] <= <GND>
smac_0[23] <= <GND>
smac_0[24] <= <GND>
smac_0[25] <= <GND>
smac_0[26] <= <GND>
smac_0[27] <= <GND>
smac_0[28] <= <GND>
smac_0[29] <= <GND>
smac_0[30] <= <GND>
smac_0[31] <= <GND>
smac_0[32] <= <GND>
smac_0[33] <= <GND>
smac_0[34] <= <GND>
smac_0[35] <= <GND>
smac_0[36] <= <GND>
smac_0[37] <= <GND>
smac_0[38] <= <GND>
smac_0[39] <= <GND>
smac_0[40] <= <GND>
smac_0[41] <= <GND>
smac_0[42] <= <GND>
smac_0[43] <= <GND>
smac_0[44] <= <GND>
smac_0[45] <= <GND>
smac_0[46] <= <GND>
smac_0[47] <= <GND>
smac_1[0] <= <GND>
smac_1[1] <= <GND>
smac_1[2] <= <GND>
smac_1[3] <= <GND>
smac_1[4] <= <GND>
smac_1[5] <= <GND>
smac_1[6] <= <GND>
smac_1[7] <= <GND>
smac_1[8] <= <GND>
smac_1[9] <= <GND>
smac_1[10] <= <GND>
smac_1[11] <= <GND>
smac_1[12] <= <GND>
smac_1[13] <= <GND>
smac_1[14] <= <GND>
smac_1[15] <= <GND>
smac_1[16] <= <GND>
smac_1[17] <= <GND>
smac_1[18] <= <GND>
smac_1[19] <= <GND>
smac_1[20] <= <GND>
smac_1[21] <= <GND>
smac_1[22] <= <GND>
smac_1[23] <= <GND>
smac_1[24] <= <GND>
smac_1[25] <= <GND>
smac_1[26] <= <GND>
smac_1[27] <= <GND>
smac_1[28] <= <GND>
smac_1[29] <= <GND>
smac_1[30] <= <GND>
smac_1[31] <= <GND>
smac_1[32] <= <GND>
smac_1[33] <= <GND>
smac_1[34] <= <GND>
smac_1[35] <= <GND>
smac_1[36] <= <GND>
smac_1[37] <= <GND>
smac_1[38] <= <GND>
smac_1[39] <= <GND>
smac_1[40] <= <GND>
smac_1[41] <= <GND>
smac_1[42] <= <GND>
smac_1[43] <= <GND>
smac_1[44] <= <GND>
smac_1[45] <= <GND>
smac_1[46] <= <GND>
smac_1[47] <= <GND>
smac_2[0] <= <GND>
smac_2[1] <= <GND>
smac_2[2] <= <GND>
smac_2[3] <= <GND>
smac_2[4] <= <GND>
smac_2[5] <= <GND>
smac_2[6] <= <GND>
smac_2[7] <= <GND>
smac_2[8] <= <GND>
smac_2[9] <= <GND>
smac_2[10] <= <GND>
smac_2[11] <= <GND>
smac_2[12] <= <GND>
smac_2[13] <= <GND>
smac_2[14] <= <GND>
smac_2[15] <= <GND>
smac_2[16] <= <GND>
smac_2[17] <= <GND>
smac_2[18] <= <GND>
smac_2[19] <= <GND>
smac_2[20] <= <GND>
smac_2[21] <= <GND>
smac_2[22] <= <GND>
smac_2[23] <= <GND>
smac_2[24] <= <GND>
smac_2[25] <= <GND>
smac_2[26] <= <GND>
smac_2[27] <= <GND>
smac_2[28] <= <GND>
smac_2[29] <= <GND>
smac_2[30] <= <GND>
smac_2[31] <= <GND>
smac_2[32] <= <GND>
smac_2[33] <= <GND>
smac_2[34] <= <GND>
smac_2[35] <= <GND>
smac_2[36] <= <GND>
smac_2[37] <= <GND>
smac_2[38] <= <GND>
smac_2[39] <= <GND>
smac_2[40] <= <GND>
smac_2[41] <= <GND>
smac_2[42] <= <GND>
smac_2[43] <= <GND>
smac_2[44] <= <GND>
smac_2[45] <= <GND>
smac_2[46] <= <GND>
smac_2[47] <= <GND>
smac_3[0] <= <GND>
smac_3[1] <= <GND>
smac_3[2] <= <GND>
smac_3[3] <= <GND>
smac_3[4] <= <GND>
smac_3[5] <= <GND>
smac_3[6] <= <GND>
smac_3[7] <= <GND>
smac_3[8] <= <GND>
smac_3[9] <= <GND>
smac_3[10] <= <GND>
smac_3[11] <= <GND>
smac_3[12] <= <GND>
smac_3[13] <= <GND>
smac_3[14] <= <GND>
smac_3[15] <= <GND>
smac_3[16] <= <GND>
smac_3[17] <= <GND>
smac_3[18] <= <GND>
smac_3[19] <= <GND>
smac_3[20] <= <GND>
smac_3[21] <= <GND>
smac_3[22] <= <GND>
smac_3[23] <= <GND>
smac_3[24] <= <GND>
smac_3[25] <= <GND>
smac_3[26] <= <GND>
smac_3[27] <= <GND>
smac_3[28] <= <GND>
smac_3[29] <= <GND>
smac_3[30] <= <GND>
smac_3[31] <= <GND>
smac_3[32] <= <GND>
smac_3[33] <= <GND>
smac_3[34] <= <GND>
smac_3[35] <= <GND>
smac_3[36] <= <GND>
smac_3[37] <= <GND>
smac_3[38] <= <GND>
smac_3[39] <= <GND>
smac_3[40] <= <GND>
smac_3[41] <= <GND>
smac_3[42] <= <GND>
smac_3[43] <= <GND>
smac_3[44] <= <GND>
smac_3[45] <= <GND>
smac_3[46] <= <GND>
smac_3[47] <= <GND>
tx_addr_sel[0] <= command_config[16].DB_MAX_OUTPUT_PORT_TYPE
tx_addr_sel[1] <= command_config[17].DB_MAX_OUTPUT_PORT_TYPE
tx_addr_sel[2] <= command_config[18].DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_std_synchronizer:U_SYNC_1
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_std_synchronizer:U_SYNC_2
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_std_synchronizer:U_SYNC_3
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_std_synchronizer:U_SYNC_4
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_std_synchronizer:U_SYNC_5
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_std_synchronizer:U_EXCESS_COL
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_std_synchronizer:U_LATE_COL
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_register_map:U_REG|altera_std_synchronizer:U_MAGIC_DETECT
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL
reset => reg_rd_ack_reg1.ACLR
reset => reg_rd_ack.ACLR
reset => reg_rd_req.ACLR
reset => rd_timout_done.ACLR
reset => rd_timout[0].ACLR
reset => rd_timout[1].ACLR
reset => rd_timout[2].ACLR
reset => rd_timout[3].ACLR
reset => rd_timout[4].ACLR
reset => rd_timout[5].ACLR
reset => rd_timout[6].ACLR
reset => rd_timout[7].ACLR
reset => state~3.DATAIN
reset => _.IN1
reset_phy_clk => phy_rd_ack0.ACLR
reset_phy_clk => _.IN1
clk => clk.IN1
phy_clk => phy_clk.IN1
cs => always1.IN0
cs => always1.IN0
rd => always1.IN1
rd => reg_rd.DATAB
rd => always1.IN1
wr => always1.IN1
wr => reg_wr.DATAB
wr => always1.IN1
sel[0] => LessThan0.IN16
sel[0] => LessThan1.IN16
sel[0] => LessThan2.IN16
sel[0] => LessThan3.IN16
sel[0] => reg_sel[0].DATAIN
sel[1] => LessThan0.IN15
sel[1] => LessThan1.IN15
sel[1] => LessThan2.IN15
sel[1] => LessThan3.IN15
sel[1] => reg_sel[1].DATAIN
sel[2] => LessThan0.IN14
sel[2] => LessThan1.IN14
sel[2] => LessThan2.IN14
sel[2] => LessThan3.IN14
sel[2] => reg_sel[2].DATAIN
sel[3] => LessThan0.IN13
sel[3] => LessThan1.IN13
sel[3] => LessThan2.IN13
sel[3] => LessThan3.IN13
sel[3] => reg_sel[3].DATAIN
sel[4] => LessThan0.IN12
sel[4] => LessThan1.IN12
sel[4] => LessThan2.IN12
sel[4] => LessThan3.IN12
sel[4] => reg_sel[4].DATAIN
sel[5] => LessThan0.IN11
sel[5] => LessThan1.IN11
sel[5] => LessThan2.IN11
sel[5] => LessThan3.IN11
sel[5] => reg_sel[5].DATAIN
sel[6] => LessThan0.IN10
sel[6] => LessThan1.IN10
sel[6] => LessThan2.IN10
sel[6] => LessThan3.IN10
sel[6] => reg_sel[6].DATAIN
sel[7] => LessThan0.IN9
sel[7] => LessThan1.IN9
sel[7] => LessThan2.IN9
sel[7] => LessThan3.IN9
sel[7] => reg_sel[7].DATAIN
data_in[0] => reg_data_out[0].DATAIN
data_in[1] => reg_data_out[1].DATAIN
data_in[2] => reg_data_out[2].DATAIN
data_in[3] => reg_data_out[3].DATAIN
data_in[4] => reg_data_out[4].DATAIN
data_in[5] => reg_data_out[5].DATAIN
data_in[6] => reg_data_out[6].DATAIN
data_in[7] => reg_data_out[7].DATAIN
data_in[8] => reg_data_out[8].DATAIN
data_in[9] => reg_data_out[9].DATAIN
data_in[10] => reg_data_out[10].DATAIN
data_in[11] => reg_data_out[11].DATAIN
data_in[12] => reg_data_out[12].DATAIN
data_in[13] => reg_data_out[13].DATAIN
data_in[14] => reg_data_out[14].DATAIN
data_in[15] => reg_data_out[15].DATAIN
data_in[16] => reg_data_out[16].DATAIN
data_in[17] => reg_data_out[17].DATAIN
data_in[18] => reg_data_out[18].DATAIN
data_in[19] => reg_data_out[19].DATAIN
data_in[20] => reg_data_out[20].DATAIN
data_in[21] => reg_data_out[21].DATAIN
data_in[22] => reg_data_out[22].DATAIN
data_in[23] => reg_data_out[23].DATAIN
data_in[24] => reg_data_out[24].DATAIN
data_in[25] => reg_data_out[25].DATAIN
data_in[26] => reg_data_out[26].DATAIN
data_in[27] => reg_data_out[27].DATAIN
data_in[28] => reg_data_out[28].DATAIN
data_in[29] => reg_data_out[29].DATAIN
data_in[30] => reg_data_out[30].DATAIN
data_in[31] => reg_data_out[31].DATAIN
data_out[0] <= reg_data_in[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= reg_data_in[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= reg_data_in[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= reg_data_in[3].DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= reg_data_in[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= reg_data_in[5].DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= reg_data_in[6].DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= reg_data_in[7].DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= reg_data_in[8].DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= reg_data_in[9].DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= reg_data_in[10].DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= reg_data_in[11].DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= reg_data_in[12].DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= reg_data_in[13].DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= reg_data_in[14].DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= reg_data_in[15].DB_MAX_OUTPUT_PORT_TYPE
data_out[16] <= reg_data_in[16].DB_MAX_OUTPUT_PORT_TYPE
data_out[17] <= reg_data_in[17].DB_MAX_OUTPUT_PORT_TYPE
data_out[18] <= reg_data_in[18].DB_MAX_OUTPUT_PORT_TYPE
data_out[19] <= reg_data_in[19].DB_MAX_OUTPUT_PORT_TYPE
data_out[20] <= reg_data_in[20].DB_MAX_OUTPUT_PORT_TYPE
data_out[21] <= reg_data_in[21].DB_MAX_OUTPUT_PORT_TYPE
data_out[22] <= reg_data_in[22].DB_MAX_OUTPUT_PORT_TYPE
data_out[23] <= reg_data_in[23].DB_MAX_OUTPUT_PORT_TYPE
data_out[24] <= reg_data_in[24].DB_MAX_OUTPUT_PORT_TYPE
data_out[25] <= reg_data_in[25].DB_MAX_OUTPUT_PORT_TYPE
data_out[26] <= reg_data_in[26].DB_MAX_OUTPUT_PORT_TYPE
data_out[27] <= reg_data_in[27].DB_MAX_OUTPUT_PORT_TYPE
data_out[28] <= reg_data_in[28].DB_MAX_OUTPUT_PORT_TYPE
data_out[29] <= reg_data_in[29].DB_MAX_OUTPUT_PORT_TYPE
data_out[30] <= reg_data_in[30].DB_MAX_OUTPUT_PORT_TYPE
data_out[31] <= reg_data_in[31].DB_MAX_OUTPUT_PORT_TYPE
busy <= busy.DB_MAX_OUTPUT_PORT_TYPE
reg_timout <= rd_timout_done.DB_MAX_OUTPUT_PORT_TYPE
reg_rd <= reg_rd.DB_MAX_OUTPUT_PORT_TYPE
reg_wr <= reg_wr.DB_MAX_OUTPUT_PORT_TYPE
reg_sel[0] <= sel[0].DB_MAX_OUTPUT_PORT_TYPE
reg_sel[1] <= sel[1].DB_MAX_OUTPUT_PORT_TYPE
reg_sel[2] <= sel[2].DB_MAX_OUTPUT_PORT_TYPE
reg_sel[3] <= sel[3].DB_MAX_OUTPUT_PORT_TYPE
reg_sel[4] <= sel[4].DB_MAX_OUTPUT_PORT_TYPE
reg_sel[5] <= sel[5].DB_MAX_OUTPUT_PORT_TYPE
reg_sel[6] <= sel[6].DB_MAX_OUTPUT_PORT_TYPE
reg_sel[7] <= sel[7].DB_MAX_OUTPUT_PORT_TYPE
reg_data_in[0] => data_out[0].DATAIN
reg_data_in[1] => data_out[1].DATAIN
reg_data_in[2] => data_out[2].DATAIN
reg_data_in[3] => data_out[3].DATAIN
reg_data_in[4] => data_out[4].DATAIN
reg_data_in[5] => data_out[5].DATAIN
reg_data_in[6] => data_out[6].DATAIN
reg_data_in[7] => data_out[7].DATAIN
reg_data_in[8] => data_out[8].DATAIN
reg_data_in[9] => data_out[9].DATAIN
reg_data_in[10] => data_out[10].DATAIN
reg_data_in[11] => data_out[11].DATAIN
reg_data_in[12] => data_out[12].DATAIN
reg_data_in[13] => data_out[13].DATAIN
reg_data_in[14] => data_out[14].DATAIN
reg_data_in[15] => data_out[15].DATAIN
reg_data_in[16] => data_out[16].DATAIN
reg_data_in[17] => data_out[17].DATAIN
reg_data_in[18] => data_out[18].DATAIN
reg_data_in[19] => data_out[19].DATAIN
reg_data_in[20] => data_out[20].DATAIN
reg_data_in[21] => data_out[21].DATAIN
reg_data_in[22] => data_out[22].DATAIN
reg_data_in[23] => data_out[23].DATAIN
reg_data_in[24] => data_out[24].DATAIN
reg_data_in[25] => data_out[25].DATAIN
reg_data_in[26] => data_out[26].DATAIN
reg_data_in[27] => data_out[27].DATAIN
reg_data_in[28] => data_out[28].DATAIN
reg_data_in[29] => data_out[29].DATAIN
reg_data_in[30] => data_out[30].DATAIN
reg_data_in[31] => data_out[31].DATAIN
reg_data_out[0] <= data_in[0].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[1] <= data_in[1].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[2] <= data_in[2].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[3] <= data_in[3].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[4] <= data_in[4].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[5] <= data_in[5].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[6] <= data_in[6].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[7] <= data_in[7].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[8] <= data_in[8].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[9] <= data_in[9].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[10] <= data_in[10].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[11] <= data_in[11].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[12] <= data_in[12].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[13] <= data_in[13].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[14] <= data_in[14].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[15] <= data_in[15].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[16] <= data_in[16].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[17] <= data_in[17].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[18] <= data_in[18].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[19] <= data_in[19].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[20] <= data_in[20].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[21] <= data_in[21].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[22] <= data_in[22].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[23] <= data_in[23].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[24] <= data_in[24].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[25] <= data_in[25].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[26] <= data_in[26].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[27] <= data_in[27].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[28] <= data_in[28].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[29] <= data_in[29].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[30] <= data_in[30].DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[31] <= data_in[31].DB_MAX_OUTPUT_PORT_TYPE
disable_rd_timeout => always4.IN1
mdio_busy => Selector1.IN3
mdio_busy => Selector2.IN3
mdio_busy => Selector3.IN4
mdio_busy => Selector5.IN1


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|altera_std_synchronizer:U_SYNC_1
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_mac_control:U_MAC_CONTROL|altera_tse_host_control:U_CTRL|altera_std_synchronizer:U_SYNC_2
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO
reset => reset.IN3
reg_clk => reg_clk.IN3
mdc <= altera_tse_mdio_clk_gen:U_CLKGEN.mdio_clk
mdio_in => mdio_in.IN1
mdio_out <= mdio_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_oen <= mdio_oen~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_in[0] => host_data_in[0].IN1
host_data_in[1] => host_data_in[1].IN1
host_data_in[2] => host_data_in[2].IN1
host_data_in[3] => host_data_in[3].IN1
host_data_in[4] => host_data_in[4].IN1
host_data_in[5] => host_data_in[5].IN1
host_data_in[6] => host_data_in[6].IN1
host_data_in[7] => host_data_in[7].IN1
host_data_in[8] => host_data_in[8].IN1
host_data_in[9] => host_data_in[9].IN1
host_data_in[10] => host_data_in[10].IN1
host_data_in[11] => host_data_in[11].IN1
host_data_in[12] => host_data_in[12].IN1
host_data_in[13] => host_data_in[13].IN1
host_data_in[14] => host_data_in[14].IN1
host_data_in[15] => host_data_in[15].IN1
host_data_out[0] <= host_data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[1] <= host_data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[2] <= host_data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[3] <= host_data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[4] <= host_data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[5] <= host_data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[6] <= host_data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[7] <= host_data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[8] <= host_data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[9] <= host_data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[10] <= host_data_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[11] <= host_data_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[12] <= host_data_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[13] <= host_data_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[14] <= host_data_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_data_out[15] <= host_data_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
host_addr[0] => host_addr[0].IN1
host_addr[1] => host_addr[1].IN1
host_addr[2] => host_addr[2].IN1
host_addr[3] => host_addr[3].IN1
host_addr[4] => host_addr[4].IN1
host_dev_addr[0] => host_dev_addr[0].IN1
host_dev_addr[1] => host_dev_addr[1].IN1
host_dev_addr[2] => host_dev_addr[2].IN1
host_dev_addr[3] => host_dev_addr[3].IN1
host_dev_addr[4] => host_dev_addr[4].IN1
host_cs => host_cs.IN1
host_rd => host_rd.IN1
host_wr => host_wr.IN1
host_busy <= altera_tse_mdio_cntl:U_CNTL.host_busy


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_clk_gen:U_CLKGEN
reset => clk_ena~reg0.ACLR
reset => mdio_clk~reg0.ACLR
reset => cnt[0].ACLR
reset => cnt[1].ACLR
reset => cnt[2].ACLR
reset => cnt[3].ACLR
reset => cnt[4].ACLR
reset => cnt[5].ACLR
reset => cnt[6].ACLR
reset => cnt[7].ACLR
reg_clk => clk_ena~reg0.CLK
reg_clk => mdio_clk~reg0.CLK
reg_clk => cnt[0].CLK
reg_clk => cnt[1].CLK
reg_clk => cnt[2].CLK
reg_clk => cnt[3].CLK
reg_clk => cnt[4].CLK
reg_clk => cnt[5].CLK
reg_clk => cnt[6].CLK
reg_clk => cnt[7].CLK
clk_ena <= clk_ena~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_clk <= mdio_clk~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio_cntl:U_CNTL
reset => host_busy_int.PRESET
reset => mdio_data_out[0]~reg0.ACLR
reset => mdio_data_out[1]~reg0.ACLR
reset => mdio_data_out[2]~reg0.ACLR
reset => mdio_data_out[3]~reg0.ACLR
reset => mdio_data_out[4]~reg0.ACLR
reset => mdio_data_out[5]~reg0.ACLR
reset => mdio_data_out[6]~reg0.ACLR
reset => mdio_data_out[7]~reg0.ACLR
reset => mdio_data_out[8]~reg0.ACLR
reset => mdio_data_out[9]~reg0.ACLR
reset => mdio_data_out[10]~reg0.ACLR
reset => mdio_data_out[11]~reg0.ACLR
reset => mdio_data_out[12]~reg0.ACLR
reset => mdio_data_out[13]~reg0.ACLR
reset => mdio_data_out[14]~reg0.ACLR
reset => mdio_data_out[15]~reg0.ACLR
reset => mdio_wr~reg0.ACLR
reset => mdio_sel[0]~reg0.ACLR
reset => mdio_sel[1]~reg0.ACLR
reset => mdio_csn~reg0.PRESET
reset => state~17.DATAIN
reg_clk => host_busy_int.CLK
reg_clk => mdio_data_out[0]~reg0.CLK
reg_clk => mdio_data_out[1]~reg0.CLK
reg_clk => mdio_data_out[2]~reg0.CLK
reg_clk => mdio_data_out[3]~reg0.CLK
reg_clk => mdio_data_out[4]~reg0.CLK
reg_clk => mdio_data_out[5]~reg0.CLK
reg_clk => mdio_data_out[6]~reg0.CLK
reg_clk => mdio_data_out[7]~reg0.CLK
reg_clk => mdio_data_out[8]~reg0.CLK
reg_clk => mdio_data_out[9]~reg0.CLK
reg_clk => mdio_data_out[10]~reg0.CLK
reg_clk => mdio_data_out[11]~reg0.CLK
reg_clk => mdio_data_out[12]~reg0.CLK
reg_clk => mdio_data_out[13]~reg0.CLK
reg_clk => mdio_data_out[14]~reg0.CLK
reg_clk => mdio_data_out[15]~reg0.CLK
reg_clk => mdio_wr~reg0.CLK
reg_clk => mdio_sel[0]~reg0.CLK
reg_clk => mdio_sel[1]~reg0.CLK
reg_clk => mdio_csn~reg0.CLK
reg_clk => state~15.DATAIN
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => host_busy_int.ENA
mdio_data_out[0] <= mdio_data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[1] <= mdio_data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[2] <= mdio_data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[3] <= mdio_data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[4] <= mdio_data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[5] <= mdio_data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[6] <= mdio_data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[7] <= mdio_data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[8] <= mdio_data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[9] <= mdio_data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[10] <= mdio_data_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[11] <= mdio_data_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[12] <= mdio_data_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[13] <= mdio_data_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[14] <= mdio_data_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_data_out[15] <= mdio_data_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_csn <= mdio_csn~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_sel[0] <= mdio_sel[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_sel[1] <= mdio_sel[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_wr <= mdio_wr~reg0.DB_MAX_OUTPUT_PORT_TYPE
mdio_busy => Selector2.IN3
mdio_busy => Selector1.IN3
mdio_busy => nextstate.STM_TYP_HOST_RD_REG.DATAB
mdio_busy => nextstate.STM_TYP_HOST_WR_END.DATAB
host_data_in[0] => mdio_data_out.DATAB
host_data_in[1] => mdio_data_out.DATAB
host_data_in[2] => mdio_data_out.DATAB
host_data_in[3] => mdio_data_out.DATAB
host_data_in[4] => mdio_data_out.DATAB
host_data_in[5] => mdio_data_out.DATAB
host_data_in[6] => mdio_data_out.DATAB
host_data_in[7] => mdio_data_out.DATAB
host_data_in[8] => mdio_data_out.DATAB
host_data_in[9] => mdio_data_out.DATAB
host_data_in[10] => mdio_data_out.DATAB
host_data_in[11] => mdio_data_out.DATAB
host_data_in[12] => mdio_data_out.DATAB
host_data_in[13] => mdio_data_out.DATAB
host_data_in[14] => mdio_data_out.DATAB
host_data_in[15] => mdio_data_out.DATAB
host_addr[0] => mdio_data_out.DATAB
host_addr[0] => mdio_data_out.DATAB
host_addr[1] => mdio_data_out.DATAB
host_addr[1] => mdio_data_out.DATAB
host_addr[2] => mdio_data_out.DATAB
host_addr[2] => mdio_data_out.DATAB
host_addr[3] => mdio_data_out.DATAB
host_addr[3] => mdio_data_out.DATAB
host_addr[4] => mdio_data_out.DATAB
host_addr[4] => mdio_data_out.DATAB
host_dev_addr[0] => mdio_data_out.DATAB
host_dev_addr[0] => mdio_data_out.DATAB
host_dev_addr[1] => mdio_data_out.DATAB
host_dev_addr[1] => mdio_data_out.DATAB
host_dev_addr[2] => mdio_data_out.DATAB
host_dev_addr[2] => mdio_data_out.DATAB
host_dev_addr[3] => mdio_data_out.DATAB
host_dev_addr[3] => mdio_data_out.DATAB
host_dev_addr[4] => mdio_data_out.DATAB
host_dev_addr[4] => mdio_data_out.DATAB
host_cs => always1.IN0
host_cs => always1.IN0
host_rd => always1.IN1
host_wr => always1.IN1
host_busy <= host_busy_int.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_mdio:U_MDIO|altera_tse_mdio:U_MDIO
reset => read_error.ACLR
reset => mux_out.PRESET
reset => cd_oe.PRESET
reset => mdio_run[0].ACLR
reset => mdio_run[1].ACLR
reset => mdio_run[2].ACLR
reset => mdio_run[3].ACLR
reset => mdio_run[4].ACLR
reset => mdio_run[5].ACLR
reset => mdio_run[6].ACLR
reset => mdio_run[7].ACLR
reset => mdio_run[8].ACLR
reset => mdio_run[9].ACLR
reset => mdio_run[10].ACLR
reset => mdio_run[11].ACLR
reset => mdio_run[12].ACLR
reset => mdio_run[13].ACLR
reset => mdio_run[14].ACLR
reset => mdio_run[15].ACLR
reset => mdio_run[16].ACLR
reset => mdio_run[17].ACLR
reset => mdio_run[18].ACLR
reset => mdio_run[19].ACLR
reset => mdio_wait.PRESET
reset => cnt_32[0].ACLR
reset => cnt_32[1].ACLR
reset => cnt_32[2].ACLR
reset => cnt_32[3].ACLR
reset => cnt_32[4].ACLR
reset => run_write.ACLR
reset => run_read.ACLR
reset => reg_data_rd[0].ACLR
reset => reg_data_rd[1].ACLR
reset => reg_data_rd[2].ACLR
reset => reg_data_rd[3].ACLR
reset => reg_data_rd[4].ACLR
reset => reg_data_rd[5].ACLR
reset => reg_data_rd[6].ACLR
reset => reg_data_rd[7].ACLR
reset => reg_data_rd[8].ACLR
reset => reg_data_rd[9].ACLR
reset => reg_data_rd[10].ACLR
reset => reg_data_rd[11].ACLR
reset => reg_data_rd[12].ACLR
reset => reg_data_rd[13].ACLR
reset => reg_data_rd[14].ACLR
reset => reg_data_rd[15].ACLR
reset => reg_data[0].ACLR
reset => reg_data[1].ACLR
reset => reg_data[2].ACLR
reset => reg_data[3].ACLR
reset => reg_data[4].ACLR
reset => reg_data[5].ACLR
reset => reg_data[6].ACLR
reset => reg_data[7].ACLR
reset => reg_data[8].ACLR
reset => reg_data[9].ACLR
reset => reg_data[10].ACLR
reset => reg_data[11].ACLR
reset => reg_data[12].ACLR
reset => reg_data[13].ACLR
reset => reg_data[14].ACLR
reset => reg_data[15].ACLR
reset => reg_phy_reg_add[0].ACLR
reset => reg_phy_reg_add[1].ACLR
reset => reg_phy_reg_add[2].ACLR
reset => reg_phy_reg_add[3].ACLR
reset => reg_phy_reg_add[4].ACLR
reset => reg_phy_reg_add[5].PRESET
reset => reg_phy_reg_add[6].ACLR
reset => reg_phy_reg_add[7].ACLR
reset => reg_phy_reg_add[8].ACLR
reset => reg_phy_reg_add[9].ACLR
mdc => read_error.CLK
mdc => mux_out.CLK
mdc => cd_oe.CLK
mdc => mdio_run[0].CLK
mdc => mdio_run[1].CLK
mdc => mdio_run[2].CLK
mdc => mdio_run[3].CLK
mdc => mdio_run[4].CLK
mdc => mdio_run[5].CLK
mdc => mdio_run[6].CLK
mdc => mdio_run[7].CLK
mdc => mdio_run[8].CLK
mdc => mdio_run[9].CLK
mdc => mdio_run[10].CLK
mdc => mdio_run[11].CLK
mdc => mdio_run[12].CLK
mdc => mdio_run[13].CLK
mdc => mdio_run[14].CLK
mdc => mdio_run[15].CLK
mdc => mdio_run[16].CLK
mdc => mdio_run[17].CLK
mdc => mdio_run[18].CLK
mdc => mdio_run[19].CLK
mdc => mdio_wait.CLK
mdc => cnt_32[0].CLK
mdc => cnt_32[1].CLK
mdc => cnt_32[2].CLK
mdc => cnt_32[3].CLK
mdc => cnt_32[4].CLK
mdc => run_write.CLK
mdc => run_read.CLK
mdc => reg_data_rd[0].CLK
mdc => reg_data_rd[1].CLK
mdc => reg_data_rd[2].CLK
mdc => reg_data_rd[3].CLK
mdc => reg_data_rd[4].CLK
mdc => reg_data_rd[5].CLK
mdc => reg_data_rd[6].CLK
mdc => reg_data_rd[7].CLK
mdc => reg_data_rd[8].CLK
mdc => reg_data_rd[9].CLK
mdc => reg_data_rd[10].CLK
mdc => reg_data_rd[11].CLK
mdc => reg_data_rd[12].CLK
mdc => reg_data_rd[13].CLK
mdc => reg_data_rd[14].CLK
mdc => reg_data_rd[15].CLK
mdc => reg_data[0].CLK
mdc => reg_data[1].CLK
mdc => reg_data[2].CLK
mdc => reg_data[3].CLK
mdc => reg_data[4].CLK
mdc => reg_data[5].CLK
mdc => reg_data[6].CLK
mdc => reg_data[7].CLK
mdc => reg_data[8].CLK
mdc => reg_data[9].CLK
mdc => reg_data[10].CLK
mdc => reg_data[11].CLK
mdc => reg_data[12].CLK
mdc => reg_data[13].CLK
mdc => reg_data[14].CLK
mdc => reg_data[15].CLK
mdc => reg_phy_reg_add[0].CLK
mdc => reg_phy_reg_add[1].CLK
mdc => reg_phy_reg_add[2].CLK
mdc => reg_phy_reg_add[3].CLK
mdc => reg_phy_reg_add[4].CLK
mdc => reg_phy_reg_add[5].CLK
mdc => reg_phy_reg_add[6].CLK
mdc => reg_phy_reg_add[7].CLK
mdc => reg_phy_reg_add[8].CLK
mdc => reg_phy_reg_add[9].CLK
mdc_ena => reg_phy_reg_add[9].ENA
mdc_ena => reg_phy_reg_add[8].ENA
mdc_ena => reg_phy_reg_add[7].ENA
mdc_ena => reg_phy_reg_add[6].ENA
mdc_ena => reg_phy_reg_add[5].ENA
mdc_ena => reg_phy_reg_add[4].ENA
mdc_ena => reg_phy_reg_add[3].ENA
mdc_ena => reg_phy_reg_add[2].ENA
mdc_ena => reg_phy_reg_add[1].ENA
mdc_ena => reg_phy_reg_add[0].ENA
mdc_ena => reg_data[15].ENA
mdc_ena => reg_data[14].ENA
mdc_ena => reg_data[13].ENA
mdc_ena => reg_data[12].ENA
mdc_ena => reg_data[11].ENA
mdc_ena => reg_data[10].ENA
mdc_ena => reg_data[9].ENA
mdc_ena => reg_data[8].ENA
mdc_ena => reg_data[7].ENA
mdc_ena => reg_data[6].ENA
mdc_ena => reg_data[5].ENA
mdc_ena => reg_data[4].ENA
mdc_ena => reg_data[3].ENA
mdc_ena => reg_data[2].ENA
mdc_ena => reg_data[1].ENA
mdc_ena => reg_data[0].ENA
mdc_ena => reg_data_rd[15].ENA
mdc_ena => reg_data_rd[14].ENA
mdc_ena => reg_data_rd[13].ENA
mdc_ena => reg_data_rd[12].ENA
mdc_ena => reg_data_rd[11].ENA
mdc_ena => reg_data_rd[10].ENA
mdc_ena => reg_data_rd[9].ENA
mdc_ena => reg_data_rd[8].ENA
mdc_ena => reg_data_rd[7].ENA
mdc_ena => reg_data_rd[6].ENA
mdc_ena => reg_data_rd[5].ENA
mdc_ena => reg_data_rd[4].ENA
mdc_ena => reg_data_rd[3].ENA
mdc_ena => reg_data_rd[2].ENA
mdc_ena => reg_data_rd[1].ENA
mdc_ena => reg_data_rd[0].ENA
mdc_ena => run_read.ENA
mdc_ena => run_write.ENA
mdc_ena => cnt_32[4].ENA
mdc_ena => cnt_32[3].ENA
mdc_ena => cnt_32[2].ENA
mdc_ena => cnt_32[1].ENA
mdc_ena => cnt_32[0].ENA
mdc_ena => mdio_wait.ENA
mdc_ena => mdio_run[19].ENA
mdc_ena => mdio_run[18].ENA
mdc_ena => mdio_run[17].ENA
mdc_ena => mdio_run[16].ENA
mdc_ena => mdio_run[15].ENA
mdc_ena => mdio_run[14].ENA
mdc_ena => mdio_run[13].ENA
mdc_ena => mdio_run[12].ENA
mdc_ena => mdio_run[11].ENA
mdc_ena => mdio_run[10].ENA
mdc_ena => mdio_run[9].ENA
mdc_ena => mdio_run[8].ENA
mdc_ena => mdio_run[7].ENA
mdc_ena => mdio_run[6].ENA
mdc_ena => mdio_run[5].ENA
mdc_ena => mdio_run[4].ENA
mdc_ena => mdio_run[3].ENA
mdc_ena => mdio_run[2].ENA
mdc_ena => mdio_run[1].ENA
mdc_ena => mdio_run[0].ENA
mdc_ena => cd_oe.ENA
mdc_ena => mux_out.ENA
mdc_ena => read_error.ENA
mdio_in => reg_data_rd.DATAB
mdio_out <= mux_out.DB_MAX_OUTPUT_PORT_TYPE
mdio_oen <= cd_oe.DB_MAX_OUTPUT_PORT_TYPE
reg_data_in[0] => reg_phy_reg_add.DATAB
reg_data_in[0] => reg_data.DATAB
reg_data_in[1] => reg_phy_reg_add.DATAB
reg_data_in[1] => reg_data.DATAB
reg_data_in[2] => reg_phy_reg_add.DATAB
reg_data_in[2] => reg_data.DATAB
reg_data_in[3] => reg_phy_reg_add.DATAB
reg_data_in[3] => reg_data.DATAB
reg_data_in[4] => reg_phy_reg_add.DATAB
reg_data_in[4] => reg_data.DATAB
reg_data_in[5] => reg_phy_reg_add.DATAB
reg_data_in[5] => reg_data.DATAB
reg_data_in[6] => reg_phy_reg_add.DATAB
reg_data_in[6] => reg_data.DATAB
reg_data_in[7] => reg_phy_reg_add.DATAB
reg_data_in[7] => reg_data.DATAB
reg_data_in[8] => reg_phy_reg_add.DATAB
reg_data_in[8] => reg_data.DATAB
reg_data_in[9] => reg_phy_reg_add.DATAB
reg_data_in[9] => reg_data.DATAB
reg_data_in[10] => reg_data.DATAB
reg_data_in[11] => reg_data.DATAB
reg_data_in[12] => reg_data.DATAB
reg_data_in[13] => reg_data.DATAB
reg_data_in[14] => reg_data.DATAB
reg_data_in[15] => reg_data.DATAB
reg_data_in[15] => always0.IN1
reg_data_out[0] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[1] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[2] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[3] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[4] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[5] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[6] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[7] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[8] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[9] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[10] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[11] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[12] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[13] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[14] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_data_out[15] <= reg_data_out.DB_MAX_OUTPUT_PORT_TYPE
reg_csn => always0.IN0
reg_wr => always0.IN1
reg_sel[0] => always0.IN1
reg_sel[0] => reg_data_out.IN0
reg_sel[0] => always0.IN1
reg_sel[1] => always0.IN1
reg_sel[1] => reg_data_out.IN1
reg_sel[1] => always0.IN1
busy <= mdio_wait.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP
reset_rx_clk => reset_rx_clk.IN4
reset_tx_clk => reset_tx_clk.IN4
reset_ff_rx_clk => reset_ff_rx_clk.IN1
reset_ff_tx_clk => reset_ff_tx_clk.IN1
rx_clk => rx_clk.IN5
tx_clk => tx_clk.IN4
rx_clkena => rx_clkena.IN2
tx_clkena => tx_clkena.IN2
reg_clk => reg_clk.IN1
gm_rx_d[0] => gm_rx_d[0].IN1
gm_rx_d[1] => gm_rx_d[1].IN1
gm_rx_d[2] => gm_rx_d[2].IN1
gm_rx_d[3] => gm_rx_d[3].IN1
gm_rx_d[4] => gm_rx_d[4].IN1
gm_rx_d[5] => gm_rx_d[5].IN1
gm_rx_d[6] => gm_rx_d[6].IN1
gm_rx_d[7] => gm_rx_d[7].IN1
gm_rx_dv => gm_rx_dv.IN1
gm_rx_err => gm_rx_err.IN1
gm_tx_d[0] <= altera_tse_gmii_io:U_GMIF.gm_tx_d
gm_tx_d[1] <= altera_tse_gmii_io:U_GMIF.gm_tx_d
gm_tx_d[2] <= altera_tse_gmii_io:U_GMIF.gm_tx_d
gm_tx_d[3] <= altera_tse_gmii_io:U_GMIF.gm_tx_d
gm_tx_d[4] <= altera_tse_gmii_io:U_GMIF.gm_tx_d
gm_tx_d[5] <= altera_tse_gmii_io:U_GMIF.gm_tx_d
gm_tx_d[6] <= altera_tse_gmii_io:U_GMIF.gm_tx_d
gm_tx_d[7] <= altera_tse_gmii_io:U_GMIF.gm_tx_d
gm_tx_en <= altera_tse_gmii_io:U_GMIF.gm_tx_en
gm_tx_err <= altera_tse_gmii_io:U_GMIF.gm_tx_err
m_rx_crs => m_rx_crs.IN1
m_rx_col => m_rx_col.IN1
m_rx_d[0] => m_rx_d[0].IN1
m_rx_d[1] => m_rx_d[1].IN1
m_rx_d[2] => m_rx_d[2].IN1
m_rx_d[3] => m_rx_d[3].IN1
m_rx_en => m_rx_en.IN1
m_rx_err => m_rx_err.IN1
m_tx_d[0] <= altera_tse_mii_tx_if:U_MTX.mii_txd
m_tx_d[1] <= altera_tse_mii_tx_if:U_MTX.mii_txd
m_tx_d[2] <= altera_tse_mii_tx_if:U_MTX.mii_txd
m_tx_d[3] <= altera_tse_mii_tx_if:U_MTX.mii_txd
m_tx_en <= altera_tse_mii_tx_if:U_MTX.mii_txdv
m_tx_err <= altera_tse_mii_tx_if:U_MTX.mii_txerr
rx_sav_section[0] => rx_sav_section[0].IN1
rx_sav_section[1] => rx_sav_section[1].IN1
rx_sav_section[2] => rx_sav_section[2].IN1
rx_sav_section[3] => rx_sav_section[3].IN1
rx_sav_section[4] => rx_sav_section[4].IN1
rx_sav_section[5] => rx_sav_section[5].IN1
rx_sav_section[6] => rx_sav_section[6].IN1
rx_sav_section[7] => rx_sav_section[7].IN1
rx_sav_section[8] => rx_sav_section[8].IN1
rx_sav_section[9] => rx_sav_section[9].IN1
rx_sav_section[10] => rx_sav_section[10].IN1
rx_septy_section[0] => rx_septy_section[0].IN1
rx_septy_section[1] => rx_septy_section[1].IN1
rx_septy_section[2] => rx_septy_section[2].IN1
rx_septy_section[3] => rx_septy_section[3].IN1
rx_septy_section[4] => rx_septy_section[4].IN1
rx_septy_section[5] => rx_septy_section[5].IN1
rx_septy_section[6] => rx_septy_section[6].IN1
rx_septy_section[7] => rx_septy_section[7].IN1
rx_septy_section[8] => rx_septy_section[8].IN1
rx_septy_section[9] => rx_septy_section[9].IN1
rx_septy_section[10] => rx_septy_section[10].IN1
rx_af_level[0] => rx_af_level[0].IN1
rx_af_level[1] => rx_af_level[1].IN1
rx_af_level[2] => rx_af_level[2].IN1
rx_af_level[3] => rx_af_level[3].IN1
rx_af_level[4] => rx_af_level[4].IN1
rx_af_level[5] => rx_af_level[5].IN1
rx_af_level[6] => rx_af_level[6].IN1
rx_af_level[7] => rx_af_level[7].IN1
rx_af_level[8] => rx_af_level[8].IN1
rx_af_level[9] => rx_af_level[9].IN1
rx_af_level[10] => rx_af_level[10].IN1
rx_ae_level[0] => rx_ae_level[0].IN1
rx_ae_level[1] => rx_ae_level[1].IN1
rx_ae_level[2] => rx_ae_level[2].IN1
rx_ae_level[3] => rx_ae_level[3].IN1
rx_ae_level[4] => rx_ae_level[4].IN1
rx_ae_level[5] => rx_ae_level[5].IN1
rx_ae_level[6] => rx_ae_level[6].IN1
rx_ae_level[7] => rx_ae_level[7].IN1
rx_ae_level[8] => rx_ae_level[8].IN1
rx_ae_level[9] => rx_ae_level[9].IN1
rx_ae_level[10] => rx_ae_level[10].IN1
rx_a_full <= altera_tse_top_w_fifo:U_MAC.rx_a_full
rx_a_empty <= altera_tse_top_w_fifo:U_MAC.rx_a_empty
ff_rx_clk => ff_rx_clk.IN1
ff_rx_data[0] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[1] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[2] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[3] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[4] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[5] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[6] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[7] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[8] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[9] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[10] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[11] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[12] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[13] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[14] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[15] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[16] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[17] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[18] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[19] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[20] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[21] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[22] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[23] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[24] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[25] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[26] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[27] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[28] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[29] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[30] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_data[31] <= altera_tse_top_w_fifo:U_MAC.ff_rx_data
ff_rx_mod[0] <= altera_tse_top_w_fifo:U_MAC.ff_rx_mod
ff_rx_mod[1] <= altera_tse_top_w_fifo:U_MAC.ff_rx_mod
ff_rx_sop <= altera_tse_top_w_fifo:U_MAC.ff_rx_sop
ff_rx_eop <= altera_tse_top_w_fifo:U_MAC.ff_rx_eop
ff_rx_err <= altera_tse_top_w_fifo:U_MAC.ff_rx_err
ff_rx_err_stat[0] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[1] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[2] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[3] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[4] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[5] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[6] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[7] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[8] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[9] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[10] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[11] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[12] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[13] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[14] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[15] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[16] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[17] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[18] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[19] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[20] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[21] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_err_stat[22] <= altera_tse_top_w_fifo:U_MAC.ff_rx_err_stat
ff_rx_ucast <= altera_tse_top_w_fifo:U_MAC.ff_rx_ucast
ff_rx_bcast <= altera_tse_top_w_fifo:U_MAC.ff_rx_bcast
ff_rx_mcast <= altera_tse_top_w_fifo:U_MAC.ff_rx_mcast
ff_rx_vlan <= altera_tse_top_w_fifo:U_MAC.ff_rx_vlan
ff_rx_rdy => ff_rx_rdy.IN1
ff_rx_dval <= altera_tse_top_w_fifo:U_MAC.ff_rx_dval
ff_rx_dsav <= altera_tse_top_w_fifo:U_MAC.ff_rx_dsav
tx_sav_section[0] => tx_sav_section[0].IN1
tx_sav_section[1] => tx_sav_section[1].IN1
tx_sav_section[2] => tx_sav_section[2].IN1
tx_sav_section[3] => tx_sav_section[3].IN1
tx_sav_section[4] => tx_sav_section[4].IN1
tx_sav_section[5] => tx_sav_section[5].IN1
tx_sav_section[6] => tx_sav_section[6].IN1
tx_sav_section[7] => tx_sav_section[7].IN1
tx_sav_section[8] => tx_sav_section[8].IN1
tx_sav_section[9] => tx_sav_section[9].IN1
tx_sav_section[10] => tx_sav_section[10].IN1
tx_septy_section[0] => tx_septy_section[0].IN1
tx_septy_section[1] => tx_septy_section[1].IN1
tx_septy_section[2] => tx_septy_section[2].IN1
tx_septy_section[3] => tx_septy_section[3].IN1
tx_septy_section[4] => tx_septy_section[4].IN1
tx_septy_section[5] => tx_septy_section[5].IN1
tx_septy_section[6] => tx_septy_section[6].IN1
tx_septy_section[7] => tx_septy_section[7].IN1
tx_septy_section[8] => tx_septy_section[8].IN1
tx_septy_section[9] => tx_septy_section[9].IN1
tx_septy_section[10] => tx_septy_section[10].IN1
tx_af_level[0] => tx_af_level[0].IN1
tx_af_level[1] => tx_af_level[1].IN1
tx_af_level[2] => tx_af_level[2].IN1
tx_af_level[3] => tx_af_level[3].IN1
tx_af_level[4] => tx_af_level[4].IN1
tx_af_level[5] => tx_af_level[5].IN1
tx_af_level[6] => tx_af_level[6].IN1
tx_af_level[7] => tx_af_level[7].IN1
tx_af_level[8] => tx_af_level[8].IN1
tx_af_level[9] => tx_af_level[9].IN1
tx_af_level[10] => tx_af_level[10].IN1
tx_ae_level[0] => tx_ae_level[0].IN1
tx_ae_level[1] => tx_ae_level[1].IN1
tx_ae_level[2] => tx_ae_level[2].IN1
tx_ae_level[3] => tx_ae_level[3].IN1
tx_ae_level[4] => tx_ae_level[4].IN1
tx_ae_level[5] => tx_ae_level[5].IN1
tx_ae_level[6] => tx_ae_level[6].IN1
tx_ae_level[7] => tx_ae_level[7].IN1
tx_ae_level[8] => tx_ae_level[8].IN1
tx_ae_level[9] => tx_ae_level[9].IN1
tx_ae_level[10] => tx_ae_level[10].IN1
tx_a_full <= altera_tse_top_w_fifo:U_MAC.tx_a_full
tx_a_empty <= altera_tse_top_w_fifo:U_MAC.tx_a_empty
ff_tx_clk => ff_tx_clk.IN2
ff_tx_data[0] => ff_tx_data[0].IN1
ff_tx_data[1] => ff_tx_data[1].IN1
ff_tx_data[2] => ff_tx_data[2].IN1
ff_tx_data[3] => ff_tx_data[3].IN1
ff_tx_data[4] => ff_tx_data[4].IN1
ff_tx_data[5] => ff_tx_data[5].IN1
ff_tx_data[6] => ff_tx_data[6].IN1
ff_tx_data[7] => ff_tx_data[7].IN1
ff_tx_data[8] => ff_tx_data[8].IN1
ff_tx_data[9] => ff_tx_data[9].IN1
ff_tx_data[10] => ff_tx_data[10].IN1
ff_tx_data[11] => ff_tx_data[11].IN1
ff_tx_data[12] => ff_tx_data[12].IN1
ff_tx_data[13] => ff_tx_data[13].IN1
ff_tx_data[14] => ff_tx_data[14].IN1
ff_tx_data[15] => ff_tx_data[15].IN1
ff_tx_data[16] => ff_tx_data[16].IN1
ff_tx_data[17] => ff_tx_data[17].IN1
ff_tx_data[18] => ff_tx_data[18].IN1
ff_tx_data[19] => ff_tx_data[19].IN1
ff_tx_data[20] => ff_tx_data[20].IN1
ff_tx_data[21] => ff_tx_data[21].IN1
ff_tx_data[22] => ff_tx_data[22].IN1
ff_tx_data[23] => ff_tx_data[23].IN1
ff_tx_data[24] => ff_tx_data[24].IN1
ff_tx_data[25] => ff_tx_data[25].IN1
ff_tx_data[26] => ff_tx_data[26].IN1
ff_tx_data[27] => ff_tx_data[27].IN1
ff_tx_data[28] => ff_tx_data[28].IN1
ff_tx_data[29] => ff_tx_data[29].IN1
ff_tx_data[30] => ff_tx_data[30].IN1
ff_tx_data[31] => ff_tx_data[31].IN1
ff_tx_mod[0] => ff_tx_mod[0].IN1
ff_tx_mod[1] => ff_tx_mod[1].IN1
ff_tx_sop => ff_tx_sop.IN1
ff_tx_eop => ff_tx_eop.IN1
ff_tx_err => ff_tx_err.IN1
ff_tx_wren => ff_tx_wren.IN1
ff_tx_rdy <= altera_tse_top_w_fifo:U_MAC.ff_tx_rdy
ff_tx_septy <= altera_tse_top_w_fifo:U_MAC.ff_tx_septy
tx_ff_uflow <= altera_tse_top_w_fifo:U_MAC.tx_ff_uflow
xoff_gen => xoff_gen.IN1
xon_gen => xon_gen.IN1
mac_addr[0] => mac_addr[0].IN1
mac_addr[1] => mac_addr[1].IN1
mac_addr[2] => mac_addr[2].IN1
mac_addr[3] => mac_addr[3].IN1
mac_addr[4] => mac_addr[4].IN1
mac_addr[5] => mac_addr[5].IN1
mac_addr[6] => mac_addr[6].IN1
mac_addr[7] => mac_addr[7].IN1
mac_addr[8] => mac_addr[8].IN1
mac_addr[9] => mac_addr[9].IN1
mac_addr[10] => mac_addr[10].IN1
mac_addr[11] => mac_addr[11].IN1
mac_addr[12] => mac_addr[12].IN1
mac_addr[13] => mac_addr[13].IN1
mac_addr[14] => mac_addr[14].IN1
mac_addr[15] => mac_addr[15].IN1
mac_addr[16] => mac_addr[16].IN1
mac_addr[17] => mac_addr[17].IN1
mac_addr[18] => mac_addr[18].IN1
mac_addr[19] => mac_addr[19].IN1
mac_addr[20] => mac_addr[20].IN1
mac_addr[21] => mac_addr[21].IN1
mac_addr[22] => mac_addr[22].IN1
mac_addr[23] => mac_addr[23].IN1
mac_addr[24] => mac_addr[24].IN1
mac_addr[25] => mac_addr[25].IN1
mac_addr[26] => mac_addr[26].IN1
mac_addr[27] => mac_addr[27].IN1
mac_addr[28] => mac_addr[28].IN1
mac_addr[29] => mac_addr[29].IN1
mac_addr[30] => mac_addr[30].IN1
mac_addr[31] => mac_addr[31].IN1
mac_addr[32] => mac_addr[32].IN1
mac_addr[33] => mac_addr[33].IN1
mac_addr[34] => mac_addr[34].IN1
mac_addr[35] => mac_addr[35].IN1
mac_addr[36] => mac_addr[36].IN1
mac_addr[37] => mac_addr[37].IN1
mac_addr[38] => mac_addr[38].IN1
mac_addr[39] => mac_addr[39].IN1
mac_addr[40] => mac_addr[40].IN1
mac_addr[41] => mac_addr[41].IN1
mac_addr[42] => mac_addr[42].IN1
mac_addr[43] => mac_addr[43].IN1
mac_addr[44] => mac_addr[44].IN1
mac_addr[45] => mac_addr[45].IN1
mac_addr[46] => mac_addr[46].IN1
mac_addr[47] => mac_addr[47].IN1
smac_0[0] => smac_0[0].IN1
smac_0[1] => smac_0[1].IN1
smac_0[2] => smac_0[2].IN1
smac_0[3] => smac_0[3].IN1
smac_0[4] => smac_0[4].IN1
smac_0[5] => smac_0[5].IN1
smac_0[6] => smac_0[6].IN1
smac_0[7] => smac_0[7].IN1
smac_0[8] => smac_0[8].IN1
smac_0[9] => smac_0[9].IN1
smac_0[10] => smac_0[10].IN1
smac_0[11] => smac_0[11].IN1
smac_0[12] => smac_0[12].IN1
smac_0[13] => smac_0[13].IN1
smac_0[14] => smac_0[14].IN1
smac_0[15] => smac_0[15].IN1
smac_0[16] => smac_0[16].IN1
smac_0[17] => smac_0[17].IN1
smac_0[18] => smac_0[18].IN1
smac_0[19] => smac_0[19].IN1
smac_0[20] => smac_0[20].IN1
smac_0[21] => smac_0[21].IN1
smac_0[22] => smac_0[22].IN1
smac_0[23] => smac_0[23].IN1
smac_0[24] => smac_0[24].IN1
smac_0[25] => smac_0[25].IN1
smac_0[26] => smac_0[26].IN1
smac_0[27] => smac_0[27].IN1
smac_0[28] => smac_0[28].IN1
smac_0[29] => smac_0[29].IN1
smac_0[30] => smac_0[30].IN1
smac_0[31] => smac_0[31].IN1
smac_0[32] => smac_0[32].IN1
smac_0[33] => smac_0[33].IN1
smac_0[34] => smac_0[34].IN1
smac_0[35] => smac_0[35].IN1
smac_0[36] => smac_0[36].IN1
smac_0[37] => smac_0[37].IN1
smac_0[38] => smac_0[38].IN1
smac_0[39] => smac_0[39].IN1
smac_0[40] => smac_0[40].IN1
smac_0[41] => smac_0[41].IN1
smac_0[42] => smac_0[42].IN1
smac_0[43] => smac_0[43].IN1
smac_0[44] => smac_0[44].IN1
smac_0[45] => smac_0[45].IN1
smac_0[46] => smac_0[46].IN1
smac_0[47] => smac_0[47].IN1
smac_1[0] => smac_1[0].IN1
smac_1[1] => smac_1[1].IN1
smac_1[2] => smac_1[2].IN1
smac_1[3] => smac_1[3].IN1
smac_1[4] => smac_1[4].IN1
smac_1[5] => smac_1[5].IN1
smac_1[6] => smac_1[6].IN1
smac_1[7] => smac_1[7].IN1
smac_1[8] => smac_1[8].IN1
smac_1[9] => smac_1[9].IN1
smac_1[10] => smac_1[10].IN1
smac_1[11] => smac_1[11].IN1
smac_1[12] => smac_1[12].IN1
smac_1[13] => smac_1[13].IN1
smac_1[14] => smac_1[14].IN1
smac_1[15] => smac_1[15].IN1
smac_1[16] => smac_1[16].IN1
smac_1[17] => smac_1[17].IN1
smac_1[18] => smac_1[18].IN1
smac_1[19] => smac_1[19].IN1
smac_1[20] => smac_1[20].IN1
smac_1[21] => smac_1[21].IN1
smac_1[22] => smac_1[22].IN1
smac_1[23] => smac_1[23].IN1
smac_1[24] => smac_1[24].IN1
smac_1[25] => smac_1[25].IN1
smac_1[26] => smac_1[26].IN1
smac_1[27] => smac_1[27].IN1
smac_1[28] => smac_1[28].IN1
smac_1[29] => smac_1[29].IN1
smac_1[30] => smac_1[30].IN1
smac_1[31] => smac_1[31].IN1
smac_1[32] => smac_1[32].IN1
smac_1[33] => smac_1[33].IN1
smac_1[34] => smac_1[34].IN1
smac_1[35] => smac_1[35].IN1
smac_1[36] => smac_1[36].IN1
smac_1[37] => smac_1[37].IN1
smac_1[38] => smac_1[38].IN1
smac_1[39] => smac_1[39].IN1
smac_1[40] => smac_1[40].IN1
smac_1[41] => smac_1[41].IN1
smac_1[42] => smac_1[42].IN1
smac_1[43] => smac_1[43].IN1
smac_1[44] => smac_1[44].IN1
smac_1[45] => smac_1[45].IN1
smac_1[46] => smac_1[46].IN1
smac_1[47] => smac_1[47].IN1
smac_2[0] => smac_2[0].IN1
smac_2[1] => smac_2[1].IN1
smac_2[2] => smac_2[2].IN1
smac_2[3] => smac_2[3].IN1
smac_2[4] => smac_2[4].IN1
smac_2[5] => smac_2[5].IN1
smac_2[6] => smac_2[6].IN1
smac_2[7] => smac_2[7].IN1
smac_2[8] => smac_2[8].IN1
smac_2[9] => smac_2[9].IN1
smac_2[10] => smac_2[10].IN1
smac_2[11] => smac_2[11].IN1
smac_2[12] => smac_2[12].IN1
smac_2[13] => smac_2[13].IN1
smac_2[14] => smac_2[14].IN1
smac_2[15] => smac_2[15].IN1
smac_2[16] => smac_2[16].IN1
smac_2[17] => smac_2[17].IN1
smac_2[18] => smac_2[18].IN1
smac_2[19] => smac_2[19].IN1
smac_2[20] => smac_2[20].IN1
smac_2[21] => smac_2[21].IN1
smac_2[22] => smac_2[22].IN1
smac_2[23] => smac_2[23].IN1
smac_2[24] => smac_2[24].IN1
smac_2[25] => smac_2[25].IN1
smac_2[26] => smac_2[26].IN1
smac_2[27] => smac_2[27].IN1
smac_2[28] => smac_2[28].IN1
smac_2[29] => smac_2[29].IN1
smac_2[30] => smac_2[30].IN1
smac_2[31] => smac_2[31].IN1
smac_2[32] => smac_2[32].IN1
smac_2[33] => smac_2[33].IN1
smac_2[34] => smac_2[34].IN1
smac_2[35] => smac_2[35].IN1
smac_2[36] => smac_2[36].IN1
smac_2[37] => smac_2[37].IN1
smac_2[38] => smac_2[38].IN1
smac_2[39] => smac_2[39].IN1
smac_2[40] => smac_2[40].IN1
smac_2[41] => smac_2[41].IN1
smac_2[42] => smac_2[42].IN1
smac_2[43] => smac_2[43].IN1
smac_2[44] => smac_2[44].IN1
smac_2[45] => smac_2[45].IN1
smac_2[46] => smac_2[46].IN1
smac_2[47] => smac_2[47].IN1
smac_3[0] => smac_3[0].IN1
smac_3[1] => smac_3[1].IN1
smac_3[2] => smac_3[2].IN1
smac_3[3] => smac_3[3].IN1
smac_3[4] => smac_3[4].IN1
smac_3[5] => smac_3[5].IN1
smac_3[6] => smac_3[6].IN1
smac_3[7] => smac_3[7].IN1
smac_3[8] => smac_3[8].IN1
smac_3[9] => smac_3[9].IN1
smac_3[10] => smac_3[10].IN1
smac_3[11] => smac_3[11].IN1
smac_3[12] => smac_3[12].IN1
smac_3[13] => smac_3[13].IN1
smac_3[14] => smac_3[14].IN1
smac_3[15] => smac_3[15].IN1
smac_3[16] => smac_3[16].IN1
smac_3[17] => smac_3[17].IN1
smac_3[18] => smac_3[18].IN1
smac_3[19] => smac_3[19].IN1
smac_3[20] => smac_3[20].IN1
smac_3[21] => smac_3[21].IN1
smac_3[22] => smac_3[22].IN1
smac_3[23] => smac_3[23].IN1
smac_3[24] => smac_3[24].IN1
smac_3[25] => smac_3[25].IN1
smac_3[26] => smac_3[26].IN1
smac_3[27] => smac_3[27].IN1
smac_3[28] => smac_3[28].IN1
smac_3[29] => smac_3[29].IN1
smac_3[30] => smac_3[30].IN1
smac_3[31] => smac_3[31].IN1
smac_3[32] => smac_3[32].IN1
smac_3[33] => smac_3[33].IN1
smac_3[34] => smac_3[34].IN1
smac_3[35] => smac_3[35].IN1
smac_3[36] => smac_3[36].IN1
smac_3[37] => smac_3[37].IN1
smac_3[38] => smac_3[38].IN1
smac_3[39] => smac_3[39].IN1
smac_3[40] => smac_3[40].IN1
smac_3[41] => smac_3[41].IN1
smac_3[42] => smac_3[42].IN1
smac_3[43] => smac_3[43].IN1
smac_3[44] => smac_3[44].IN1
smac_3[45] => smac_3[45].IN1
smac_3[46] => smac_3[46].IN1
smac_3[47] => smac_3[47].IN1
tx_shift16 => tx_shift16.IN1
rx_shift16 => rx_shift16.IN1
sw_reset => sw_reset.IN1
rx_reset_done <= altera_tse_top_w_fifo:U_MAC.rx_reset_done
rx_total_lgth[0] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[1] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[2] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[3] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[4] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[5] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[6] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[7] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[8] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[9] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[10] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[11] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[12] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[13] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[14] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_lgth[15] <= altera_tse_top_w_fifo:U_MAC.rx_total_lgth
rx_total_val <= altera_tse_top_w_fifo:U_MAC.rx_total_val
rx_frm_stat_ena <= altera_tse_top_w_fifo:U_MAC.rx_frm_stat_ena
rx_frm_stat_val <= altera_tse_top_w_fifo:U_MAC.rx_frm_stat_val
rx_frm_err <= altera_tse_top_w_fifo:U_MAC.rx_frm_err
rx_frm_crc_err <= altera_tse_top_w_fifo:U_MAC.rx_frm_crc_err
rx_frm_length[0] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[1] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[2] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[3] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[4] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[5] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[6] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[7] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[8] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[9] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[10] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[11] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[12] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[13] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[14] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_length[15] <= altera_tse_top_w_fifo:U_MAC.rx_frm_length
rx_frm_vlan <= altera_tse_top_w_fifo:U_MAC.rx_frm_vlan
rx_frm_stack_vlan <= altera_tse_top_w_fifo:U_MAC.rx_frm_stack_vlan
rx_frm_unicast <= altera_tse_top_w_fifo:U_MAC.rx_frm_unicast
rx_frm_broadcast <= altera_tse_top_w_fifo:U_MAC.rx_frm_broadcast
rx_frm_mltcast <= altera_tse_top_w_fifo:U_MAC.rx_frm_mltcast
pause_rcv <= altera_tse_top_w_fifo:U_MAC.pause_rcv
frm_align_err <= altera_tse_top_w_fifo:U_MAC.frm_align_err
frm_crc_err <= altera_tse_top_w_fifo:U_MAC.frm_crc_err
long_crc_err <= altera_tse_top_w_fifo:U_MAC.long_crc_err
short_crc_err <= altera_tse_top_w_fifo:U_MAC.short_crc_err
frm_discard <= altera_tse_top_w_fifo:U_MAC.frm_discard
tx_frm_stat_val <= altera_tse_top_w_fifo:U_MAC.tx_frm_stat_val
tx_frm_err <= altera_tse_top_w_fifo:U_MAC.tx_frm_err
tx_frm_length[0] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[1] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[2] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[3] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[4] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[5] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[6] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[7] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[8] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[9] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[10] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[11] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[12] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[13] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[14] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_length[15] <= altera_tse_top_w_fifo:U_MAC.tx_frm_length
tx_frm_unicast <= altera_tse_top_w_fifo:U_MAC.tx_frm_unicast
tx_frm_broadcast <= altera_tse_top_w_fifo:U_MAC.tx_frm_broadcast
tx_frm_mltcast <= altera_tse_top_w_fifo:U_MAC.tx_frm_mltcast
excess_col <= altera_tse_top_w_fifo:U_MAC.excess_col
late_col <= altera_tse_top_w_fifo:U_MAC.late_col
pause_tx <= altera_tse_top_w_fifo:U_MAC.pause_tx
tx_addr_ins => tx_addr_ins.IN1
tx_addr_sel[0] => tx_addr_sel[0].IN1
tx_addr_sel[1] => tx_addr_sel[1].IN1
tx_addr_sel[2] => tx_addr_sel[2].IN1
enable_tx => enable_tx.IN1
tx_ipg_len[0] => tx_ipg_len[0].IN1
tx_ipg_len[1] => tx_ipg_len[1].IN1
tx_ipg_len[2] => tx_ipg_len[2].IN1
tx_ipg_len[3] => tx_ipg_len[3].IN1
tx_ipg_len[4] => tx_ipg_len[4].IN1
tx_crc_fwd => tx_crc_fwd.IN1
tx_crc_fwd_in => tx_crc_fwd_sig.DATAA
gmii_loopback => ~NO_FANOUT~
enable_rx => enable_rx.IN1
no_lgth_check => no_lgth_check.IN1
rx_err_frm_disc => rx_err_frm_disc.IN1
frm_length_max[0] => frm_length_max[0].IN1
frm_length_max[1] => frm_length_max[1].IN1
frm_length_max[2] => frm_length_max[2].IN1
frm_length_max[3] => frm_length_max[3].IN1
frm_length_max[4] => frm_length_max[4].IN1
frm_length_max[5] => frm_length_max[5].IN1
frm_length_max[6] => frm_length_max[6].IN1
frm_length_max[7] => frm_length_max[7].IN1
frm_length_max[8] => frm_length_max[8].IN1
frm_length_max[9] => frm_length_max[9].IN1
frm_length_max[10] => frm_length_max[10].IN1
frm_length_max[11] => frm_length_max[11].IN1
frm_length_max[12] => frm_length_max[12].IN1
frm_length_max[13] => frm_length_max[13].IN1
frm_length_max[14] => frm_length_max[14].IN1
frm_length_max[15] => frm_length_max[15].IN1
promis_en => promis_en.IN1
crc_fwd => crc_fwd.IN1
pad_ena => pad_ena.IN1
half_duplex_ena => half_duplex_ena.IN1
ethernet_mode => ethernet_mode_sig.IN5
magic_ena => magic_ena.IN1
sleep_ena => sleep_ena.IN1
magic_detect <= altera_tse_top_w_fifo:U_MAC.magic_detect
cmd_frm_ena => cmd_frm_ena.IN1
pause_quant[0] => pause_quant[0].IN1
pause_quant[1] => pause_quant[1].IN1
pause_quant[2] => pause_quant[2].IN1
pause_quant[3] => pause_quant[3].IN1
pause_quant[4] => pause_quant[4].IN1
pause_quant[5] => pause_quant[5].IN1
pause_quant[6] => pause_quant[6].IN1
pause_quant[7] => pause_quant[7].IN1
pause_quant[8] => pause_quant[8].IN1
pause_quant[9] => pause_quant[9].IN1
pause_quant[10] => pause_quant[10].IN1
pause_quant[11] => pause_quant[11].IN1
pause_quant[12] => pause_quant[12].IN1
pause_quant[13] => pause_quant[13].IN1
pause_quant[14] => pause_quant[14].IN1
pause_quant[15] => pause_quant[15].IN1
pause_fwd => pause_fwd.IN1
pause_ignore => pause_ignore.IN1
holdoff_quant[0] => holdoff_quant[0].IN1
holdoff_quant[1] => holdoff_quant[1].IN1
holdoff_quant[2] => holdoff_quant[2].IN1
holdoff_quant[3] => holdoff_quant[3].IN1
holdoff_quant[4] => holdoff_quant[4].IN1
holdoff_quant[5] => holdoff_quant[5].IN1
holdoff_quant[6] => holdoff_quant[6].IN1
holdoff_quant[7] => holdoff_quant[7].IN1
holdoff_quant[8] => holdoff_quant[8].IN1
holdoff_quant[9] => holdoff_quant[9].IN1
holdoff_quant[10] => holdoff_quant[10].IN1
holdoff_quant[11] => holdoff_quant[11].IN1
holdoff_quant[12] => holdoff_quant[12].IN1
holdoff_quant[13] => holdoff_quant[13].IN1
holdoff_quant[14] => holdoff_quant[14].IN1
holdoff_quant[15] => holdoff_quant[15].IN1
mhash_sel => mhash_sel.IN1
hash_wren => hash_wren.IN1
hash_wdata => hash_wdata.IN1
hash_waddr[0] => hash_waddr[0].IN1
hash_waddr[1] => hash_waddr[1].IN1
hash_waddr[2] => hash_waddr[2].IN1
hash_waddr[3] => hash_waddr[3].IN1
hash_waddr[4] => hash_waddr[4].IN1
hash_waddr[5] => hash_waddr[5].IN1


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT
reset_rx_clk => rxclk_ena~reg0.ACLR
reset_rx_clk => rxclk_ena_i.ACLR
reset_rx_clk => _.IN1
reset_tx_clk => txclk_ena~reg0.ACLR
reset_tx_clk => txclk_ena_i.ACLR
reset_tx_clk => _.IN1
ethernet_mode => ethernet_mode.IN2
rx_clk => rx_clk.IN1
tx_clk => tx_clk.IN1
rx_clkena => rxclk_ena.IN1
rx_clkena => rxclk_ena.DATAB
rx_clkena => rxclk_ena_i.ENA
tx_clkena => txclk_ena.IN1
tx_clkena => txclk_ena.DATAB
tx_clkena => txclk_ena_i.ENA
rxclk_ena <= rxclk_ena~reg0.DB_MAX_OUTPUT_PORT_TYPE
txclk_ena <= txclk_ena~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT|altera_std_synchronizer:U_SYNC_RX_ETH_MODE
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_clk_cntl:U_CLKCT|altera_std_synchronizer:U_SYNC_TX_ETH_MODE
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_rx_if:U_MRX
reset => mii_rxerr_o~reg0.ACLR
reset => mii_rxdv_o~reg0.ACLR
reset => mii_rxd_o[0]~reg0.ACLR
reset => mii_rxd_o[1]~reg0.ACLR
reset => mii_rxd_o[2]~reg0.ACLR
reset => mii_rxd_o[3]~reg0.ACLR
reset => mii_rxd_o[4]~reg0.ACLR
reset => mii_rxd_o[5]~reg0.ACLR
reset => mii_rxd_o[6]~reg0.ACLR
reset => mii_rxd_o[7]~reg0.ACLR
reset => alignment_error.ACLR
reset => align_pipeline_1_2.ACLR
reset => packet_in_progress.ACLR
reset => mii_rxerr_reg_2.ACLR
reset => mii_rxdv_reg_2.ACLR
reset => mii_rxd_reg_2[0].ACLR
reset => mii_rxd_reg_2[1].ACLR
reset => mii_rxd_reg_2[2].ACLR
reset => mii_rxd_reg_2[3].ACLR
reset => mii_rxerr_reg_1.ACLR
reset => mii_rxdv_reg_1.ACLR
reset => mii_rxd_reg_1[0].ACLR
reset => mii_rxd_reg_1[1].ACLR
reset => mii_rxd_reg_1[2].ACLR
reset => mii_rxd_reg_1[3].ACLR
reset => mii_rxerr_reg_0.ACLR
reset => mii_rxdv_reg_0.ACLR
reset => mii_rxd_reg_0[0].ACLR
reset => mii_rxd_reg_0[1].ACLR
reset => mii_rxd_reg_0[2].ACLR
reset => mii_rxd_reg_0[3].ACLR
reset => mii_clk_ena.ACLR
rx_clk => mii_rxerr_o~reg0.CLK
rx_clk => mii_rxdv_o~reg0.CLK
rx_clk => mii_rxd_o[0]~reg0.CLK
rx_clk => mii_rxd_o[1]~reg0.CLK
rx_clk => mii_rxd_o[2]~reg0.CLK
rx_clk => mii_rxd_o[3]~reg0.CLK
rx_clk => mii_rxd_o[4]~reg0.CLK
rx_clk => mii_rxd_o[5]~reg0.CLK
rx_clk => mii_rxd_o[6]~reg0.CLK
rx_clk => mii_rxd_o[7]~reg0.CLK
rx_clk => alignment_error.CLK
rx_clk => align_pipeline_1_2.CLK
rx_clk => packet_in_progress.CLK
rx_clk => mii_rxerr_reg_2.CLK
rx_clk => mii_rxdv_reg_2.CLK
rx_clk => mii_rxd_reg_2[0].CLK
rx_clk => mii_rxd_reg_2[1].CLK
rx_clk => mii_rxd_reg_2[2].CLK
rx_clk => mii_rxd_reg_2[3].CLK
rx_clk => mii_rxerr_reg_1.CLK
rx_clk => mii_rxdv_reg_1.CLK
rx_clk => mii_rxd_reg_1[0].CLK
rx_clk => mii_rxd_reg_1[1].CLK
rx_clk => mii_rxd_reg_1[2].CLK
rx_clk => mii_rxd_reg_1[3].CLK
rx_clk => mii_rxerr_reg_0.CLK
rx_clk => mii_rxdv_reg_0.CLK
rx_clk => mii_rxd_reg_0[0].CLK
rx_clk => mii_rxd_reg_0[1].CLK
rx_clk => mii_rxd_reg_0[2].CLK
rx_clk => mii_rxd_reg_0[3].CLK
rx_clk => mii_clk_ena.CLK
clk_ena => always2.IN1
clk_ena => mii_clk_ena.ENA
clk_ena => mii_rxd_reg_0[3].ENA
clk_ena => mii_rxd_reg_0[2].ENA
clk_ena => mii_rxd_reg_0[1].ENA
clk_ena => mii_rxd_reg_0[0].ENA
clk_ena => mii_rxdv_reg_0.ENA
clk_ena => mii_rxerr_reg_0.ENA
clk_ena => mii_rxd_reg_1[3].ENA
clk_ena => mii_rxd_reg_1[2].ENA
clk_ena => mii_rxd_reg_1[1].ENA
clk_ena => mii_rxd_reg_1[0].ENA
clk_ena => mii_rxdv_reg_1.ENA
clk_ena => mii_rxerr_reg_1.ENA
clk_ena => mii_rxd_reg_2[3].ENA
clk_ena => mii_rxd_reg_2[2].ENA
clk_ena => mii_rxd_reg_2[1].ENA
clk_ena => mii_rxd_reg_2[0].ENA
clk_ena => mii_rxdv_reg_2.ENA
clk_ena => mii_rxerr_reg_2.ENA
mii_rxd[0] => mii_rxd_reg_0[0].DATAIN
mii_rxd[1] => mii_rxd_reg_0[1].DATAIN
mii_rxd[2] => mii_rxd_reg_0[2].DATAIN
mii_rxd[3] => mii_rxd_reg_0[3].DATAIN
mii_rxdv => mii_rxdv_reg_0.DATAIN
mii_rxerr => mii_rxerr_reg_0.DATAIN
mii_rxd_o[0] <= mii_rxd_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mii_rxd_o[1] <= mii_rxd_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mii_rxd_o[2] <= mii_rxd_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mii_rxd_o[3] <= mii_rxd_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mii_rxd_o[4] <= mii_rxd_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mii_rxd_o[5] <= mii_rxd_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mii_rxd_o[6] <= mii_rxd_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mii_rxd_o[7] <= mii_rxd_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mii_rxdv_o <= mii_rxdv_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
mii_rxerr_o <= mii_rxerr_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
mii_align_err <= alignment_error.DB_MAX_OUTPUT_PORT_TYPE
mii_alignment_status <= align_pipeline_1_2.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_tx_if:U_MTX
reset => mii_txerr_int.ACLR
reset => mii_txdv_int.ACLR
reset => mii_txd_int[0].ACLR
reset => mii_txd_int[1].ACLR
reset => mii_txd_int[2].ACLR
reset => mii_txd_int[3].ACLR
reset => mii_pos.ACLR
reset => _.IN1
tx_clk => tx_clk.IN1
tx_clkena => mii_txerr_int.ENA
tx_clkena => mii_pos.ENA
tx_clkena => mii_txd_int[3].ENA
tx_clkena => mii_txd_int[2].ENA
tx_clkena => mii_txd_int[1].ENA
tx_clkena => mii_txd_int[0].ENA
tx_clkena => mii_txdv_int.ENA
enan => enan.IN1
mii_txd[0] <= mii_txd_int[0].DB_MAX_OUTPUT_PORT_TYPE
mii_txd[1] <= mii_txd_int[1].DB_MAX_OUTPUT_PORT_TYPE
mii_txd[2] <= mii_txd_int[2].DB_MAX_OUTPUT_PORT_TYPE
mii_txd[3] <= mii_txd_int[3].DB_MAX_OUTPUT_PORT_TYPE
mii_txdv <= mii_txdv_int.DB_MAX_OUTPUT_PORT_TYPE
mii_txerr <= mii_txerr_int.DB_MAX_OUTPUT_PORT_TYPE
mii_txd_i[0] => mii_txd_int.DATAA
mii_txd_i[1] => mii_txd_int.DATAA
mii_txd_i[2] => mii_txd_int.DATAA
mii_txd_i[3] => mii_txd_int.DATAA
mii_txd_i[4] => mii_txd_int.DATAB
mii_txd_i[5] => mii_txd_int.DATAB
mii_txd_i[6] => mii_txd_int.DATAB
mii_txd_i[7] => mii_txd_int.DATAB
mii_txdv_i => mii_pos.OUTPUTSELECT
mii_txdv_i => mii_txdv_int.DATAB
mii_txerr_i => mii_txerr_int.DATAB


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_mii_tx_if:U_MTX|altera_std_synchronizer:U_SYNC_1
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF
reset_rx_clk => gm_rx_d_i_reg[0].ACLR
reset_rx_clk => gm_rx_d_i_reg[1].ACLR
reset_rx_clk => gm_rx_d_i_reg[2].ACLR
reset_rx_clk => gm_rx_d_i_reg[3].ACLR
reset_rx_clk => gm_rx_d_i_reg[4].ACLR
reset_rx_clk => gm_rx_d_i_reg[5].ACLR
reset_rx_clk => gm_rx_d_i_reg[6].ACLR
reset_rx_clk => gm_rx_d_i_reg[7].ACLR
reset_rx_clk => gm_rx_err_i_reg.ACLR
reset_rx_clk => gm_rx_en_i_reg.ACLR
reset_tx_clk => gm_tx_d_reg[0].ACLR
reset_tx_clk => gm_tx_d_reg[1].ACLR
reset_tx_clk => gm_tx_d_reg[2].ACLR
reset_tx_clk => gm_tx_d_reg[3].ACLR
reset_tx_clk => gm_tx_d_reg[4].ACLR
reset_tx_clk => gm_tx_d_reg[5].ACLR
reset_tx_clk => gm_tx_d_reg[6].ACLR
reset_tx_clk => gm_tx_d_reg[7].ACLR
reset_tx_clk => gm_tx_err_reg.ACLR
reset_tx_clk => gm_tx_en_reg.ACLR
reset_tx_clk => _.IN1
ena => ena.IN1
rx_clk => gm_rx_d_i_reg[0].CLK
rx_clk => gm_rx_d_i_reg[1].CLK
rx_clk => gm_rx_d_i_reg[2].CLK
rx_clk => gm_rx_d_i_reg[3].CLK
rx_clk => gm_rx_d_i_reg[4].CLK
rx_clk => gm_rx_d_i_reg[5].CLK
rx_clk => gm_rx_d_i_reg[6].CLK
rx_clk => gm_rx_d_i_reg[7].CLK
rx_clk => gm_rx_err_i_reg.CLK
rx_clk => gm_rx_en_i_reg.CLK
gm_rx_d[0] => gm_rx_d_i_reg[0].DATAIN
gm_rx_d[1] => gm_rx_d_i_reg[1].DATAIN
gm_rx_d[2] => gm_rx_d_i_reg[2].DATAIN
gm_rx_d[3] => gm_rx_d_i_reg[3].DATAIN
gm_rx_d[4] => gm_rx_d_i_reg[4].DATAIN
gm_rx_d[5] => gm_rx_d_i_reg[5].DATAIN
gm_rx_d[6] => gm_rx_d_i_reg[6].DATAIN
gm_rx_d[7] => gm_rx_d_i_reg[7].DATAIN
gm_rx_en => gm_rx_en_i_reg.DATAIN
gm_rx_err => gm_rx_err_i_reg.DATAIN
gm_rx_d_i[0] <= gm_rx_d_i_reg[0].DB_MAX_OUTPUT_PORT_TYPE
gm_rx_d_i[1] <= gm_rx_d_i_reg[1].DB_MAX_OUTPUT_PORT_TYPE
gm_rx_d_i[2] <= gm_rx_d_i_reg[2].DB_MAX_OUTPUT_PORT_TYPE
gm_rx_d_i[3] <= gm_rx_d_i_reg[3].DB_MAX_OUTPUT_PORT_TYPE
gm_rx_d_i[4] <= gm_rx_d_i_reg[4].DB_MAX_OUTPUT_PORT_TYPE
gm_rx_d_i[5] <= gm_rx_d_i_reg[5].DB_MAX_OUTPUT_PORT_TYPE
gm_rx_d_i[6] <= gm_rx_d_i_reg[6].DB_MAX_OUTPUT_PORT_TYPE
gm_rx_d_i[7] <= gm_rx_d_i_reg[7].DB_MAX_OUTPUT_PORT_TYPE
gm_rx_en_i <= gm_rx_en_i_reg.DB_MAX_OUTPUT_PORT_TYPE
gm_rx_err_i <= gm_rx_err_i_reg.DB_MAX_OUTPUT_PORT_TYPE
tx_clk => tx_clk.IN1
gm_tx_d[0] <= gm_tx_d_reg[0].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[1] <= gm_tx_d_reg[1].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[2] <= gm_tx_d_reg[2].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[3] <= gm_tx_d_reg[3].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[4] <= gm_tx_d_reg[4].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[5] <= gm_tx_d_reg[5].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[6] <= gm_tx_d_reg[6].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[7] <= gm_tx_d_reg[7].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_en <= gm_tx_en_reg.DB_MAX_OUTPUT_PORT_TYPE
gm_tx_err <= gm_tx_err_reg.DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d_o[0] => gm_tx_d_reg.DATAB
gm_tx_d_o[1] => gm_tx_d_reg.DATAB
gm_tx_d_o[2] => gm_tx_d_reg.DATAB
gm_tx_d_o[3] => gm_tx_d_reg.DATAB
gm_tx_d_o[4] => gm_tx_d_reg.DATAB
gm_tx_d_o[5] => gm_tx_d_reg.DATAB
gm_tx_d_o[6] => gm_tx_d_reg.DATAB
gm_tx_d_o[7] => gm_tx_d_reg.DATAB
gm_tx_en_o => gm_tx_en_reg.DATAB
gm_tx_err_o => gm_tx_err_reg.DATAB


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_gmii_io:U_GMIF|altera_std_synchronizer:U_SYNC_1
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_std_synchronizer:U_SYNC_1
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_std_synchronizer:U_SYNC_2
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC
reset_rx_clk => reset_rx_clk.IN2
reset_tx_clk => reset_tx_clk.IN2
reset_ff_rx_clk => reset_ff_rx_clk.IN1
reset_ff_tx_clk => reset_ff_tx_clk.IN1
rx_clk => rx_clk.IN2
rxclk_ena => rxclk_ena.IN1
tx_clk => tx_clk.IN2
txclk_ena => txclk_ena.IN2
reg_clk => reg_clk.IN1
gm_rx_crs => gm_rx_crs.IN1
gm_rx_col => gm_rx_col.IN1
gm_rx_d[0] => gm_rx_d[0].IN1
gm_rx_d[1] => gm_rx_d[1].IN1
gm_rx_d[2] => gm_rx_d[2].IN1
gm_rx_d[3] => gm_rx_d[3].IN1
gm_rx_d[4] => gm_rx_d[4].IN1
gm_rx_d[5] => gm_rx_d[5].IN1
gm_rx_d[6] => gm_rx_d[6].IN1
gm_rx_d[7] => gm_rx_d[7].IN1
gm_rx_en => gm_rx_en.IN1
gm_rx_err => gm_rx_err.IN1
mii_align_err => mii_align_err.IN1
gm_tx_d[0] <= altera_tse_top_1geth:U_GETH.gm_tx_d
gm_tx_d[1] <= altera_tse_top_1geth:U_GETH.gm_tx_d
gm_tx_d[2] <= altera_tse_top_1geth:U_GETH.gm_tx_d
gm_tx_d[3] <= altera_tse_top_1geth:U_GETH.gm_tx_d
gm_tx_d[4] <= altera_tse_top_1geth:U_GETH.gm_tx_d
gm_tx_d[5] <= altera_tse_top_1geth:U_GETH.gm_tx_d
gm_tx_d[6] <= altera_tse_top_1geth:U_GETH.gm_tx_d
gm_tx_d[7] <= altera_tse_top_1geth:U_GETH.gm_tx_d
gm_tx_en <= altera_tse_top_1geth:U_GETH.gm_tx_en
gm_tx_err <= altera_tse_top_1geth:U_GETH.gm_tx_err
rx_sav_section[0] => rx_sav_section[0].IN1
rx_sav_section[1] => rx_sav_section[1].IN1
rx_sav_section[2] => rx_sav_section[2].IN1
rx_sav_section[3] => rx_sav_section[3].IN1
rx_sav_section[4] => rx_sav_section[4].IN1
rx_sav_section[5] => rx_sav_section[5].IN1
rx_sav_section[6] => rx_sav_section[6].IN1
rx_sav_section[7] => rx_sav_section[7].IN1
rx_sav_section[8] => rx_sav_section[8].IN1
rx_sav_section[9] => rx_sav_section[9].IN1
rx_sav_section[10] => rx_sav_section[10].IN1
rx_septy_section[0] => rx_septy_section[0].IN1
rx_septy_section[1] => rx_septy_section[1].IN1
rx_septy_section[2] => rx_septy_section[2].IN1
rx_septy_section[3] => rx_septy_section[3].IN1
rx_septy_section[4] => rx_septy_section[4].IN1
rx_septy_section[5] => rx_septy_section[5].IN1
rx_septy_section[6] => rx_septy_section[6].IN1
rx_septy_section[7] => rx_septy_section[7].IN1
rx_septy_section[8] => rx_septy_section[8].IN1
rx_septy_section[9] => rx_septy_section[9].IN1
rx_septy_section[10] => rx_septy_section[10].IN1
rx_af_level[0] => rx_af_level[0].IN1
rx_af_level[1] => rx_af_level[1].IN1
rx_af_level[2] => rx_af_level[2].IN1
rx_af_level[3] => rx_af_level[3].IN1
rx_af_level[4] => rx_af_level[4].IN1
rx_af_level[5] => rx_af_level[5].IN1
rx_af_level[6] => rx_af_level[6].IN1
rx_af_level[7] => rx_af_level[7].IN1
rx_af_level[8] => rx_af_level[8].IN1
rx_af_level[9] => rx_af_level[9].IN1
rx_af_level[10] => rx_af_level[10].IN1
rx_ae_level[0] => rx_ae_level[0].IN1
rx_ae_level[1] => rx_ae_level[1].IN1
rx_ae_level[2] => rx_ae_level[2].IN1
rx_ae_level[3] => rx_ae_level[3].IN1
rx_ae_level[4] => rx_ae_level[4].IN1
rx_ae_level[5] => rx_ae_level[5].IN1
rx_ae_level[6] => rx_ae_level[6].IN1
rx_ae_level[7] => rx_ae_level[7].IN1
rx_ae_level[8] => rx_ae_level[8].IN1
rx_ae_level[9] => rx_ae_level[9].IN1
rx_ae_level[10] => rx_ae_level[10].IN1
rx_a_full <= rx_afull.DB_MAX_OUTPUT_PORT_TYPE
rx_a_empty <= altera_tse_rx_min_ff:U_RXFF.rx_a_empty
ff_rx_clk => ff_rx_clk.IN1
ff_rx_data[0] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[1] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[2] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[3] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[4] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[5] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[6] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[7] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[8] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[9] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[10] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[11] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[12] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[13] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[14] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[15] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[16] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[17] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[18] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[19] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[20] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[21] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[22] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[23] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[24] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[25] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[26] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[27] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[28] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[29] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[30] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_data[31] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_data
ff_rx_mod[0] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_mod
ff_rx_mod[1] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_mod
ff_rx_sop <= altera_tse_rx_min_ff:U_RXFF.ff_rx_sop
ff_rx_eop <= altera_tse_rx_min_ff:U_RXFF.ff_rx_eop
ff_rx_err <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err
ff_rx_err_stat[0] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[1] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[2] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[3] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[4] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[5] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[6] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[7] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[8] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[9] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[10] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[11] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[12] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[13] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[14] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[15] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[16] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[17] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[18] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[19] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[20] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[21] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_err_stat[22] <= altera_tse_rx_min_ff:U_RXFF.ff_rx_err_stat
ff_rx_rdy => ff_rx_rdy.IN1
ff_rx_ucast <= altera_tse_rx_min_ff:U_RXFF.ff_rx_ucast
ff_rx_bcast <= altera_tse_rx_min_ff:U_RXFF.ff_rx_bcast
ff_rx_mcast <= altera_tse_rx_min_ff:U_RXFF.ff_rx_mcast
ff_rx_vlan <= altera_tse_rx_min_ff:U_RXFF.ff_rx_vlan
ff_rx_dval <= altera_tse_rx_min_ff:U_RXFF.ff_rx_dval
ff_rx_dsav <= altera_tse_rx_min_ff:U_RXFF.ff_rx_dsav
tx_sav_section[0] => tx_sav_section[0].IN1
tx_sav_section[1] => tx_sav_section[1].IN1
tx_sav_section[2] => tx_sav_section[2].IN1
tx_sav_section[3] => tx_sav_section[3].IN1
tx_sav_section[4] => tx_sav_section[4].IN1
tx_sav_section[5] => tx_sav_section[5].IN1
tx_sav_section[6] => tx_sav_section[6].IN1
tx_sav_section[7] => tx_sav_section[7].IN1
tx_sav_section[8] => tx_sav_section[8].IN1
tx_sav_section[9] => tx_sav_section[9].IN1
tx_sav_section[10] => tx_sav_section[10].IN1
tx_septy_section[0] => tx_septy_section[0].IN1
tx_septy_section[1] => tx_septy_section[1].IN1
tx_septy_section[2] => tx_septy_section[2].IN1
tx_septy_section[3] => tx_septy_section[3].IN1
tx_septy_section[4] => tx_septy_section[4].IN1
tx_septy_section[5] => tx_septy_section[5].IN1
tx_septy_section[6] => tx_septy_section[6].IN1
tx_septy_section[7] => tx_septy_section[7].IN1
tx_septy_section[8] => tx_septy_section[8].IN1
tx_septy_section[9] => tx_septy_section[9].IN1
tx_septy_section[10] => tx_septy_section[10].IN1
tx_af_level[0] => tx_af_level[0].IN1
tx_af_level[1] => tx_af_level[1].IN1
tx_af_level[2] => tx_af_level[2].IN1
tx_af_level[3] => tx_af_level[3].IN1
tx_af_level[4] => tx_af_level[4].IN1
tx_af_level[5] => tx_af_level[5].IN1
tx_af_level[6] => tx_af_level[6].IN1
tx_af_level[7] => tx_af_level[7].IN1
tx_af_level[8] => tx_af_level[8].IN1
tx_af_level[9] => tx_af_level[9].IN1
tx_af_level[10] => tx_af_level[10].IN1
tx_ae_level[0] => tx_ae_level[0].IN1
tx_ae_level[1] => tx_ae_level[1].IN1
tx_ae_level[2] => tx_ae_level[2].IN1
tx_ae_level[3] => tx_ae_level[3].IN1
tx_ae_level[4] => tx_ae_level[4].IN1
tx_ae_level[5] => tx_ae_level[5].IN1
tx_ae_level[6] => tx_ae_level[6].IN1
tx_ae_level[7] => tx_ae_level[7].IN1
tx_ae_level[8] => tx_ae_level[8].IN1
tx_ae_level[9] => tx_ae_level[9].IN1
tx_ae_level[10] => tx_ae_level[10].IN1
tx_a_full <= altera_tse_tx_min_ff:U_TXFF.tx_a_full
tx_a_empty <= altera_tse_tx_min_ff:U_TXFF.tx_a_empty
ff_tx_clk => ff_tx_clk.IN1
ff_tx_data[0] => ff_tx_data[0].IN1
ff_tx_data[1] => ff_tx_data[1].IN1
ff_tx_data[2] => ff_tx_data[2].IN1
ff_tx_data[3] => ff_tx_data[3].IN1
ff_tx_data[4] => ff_tx_data[4].IN1
ff_tx_data[5] => ff_tx_data[5].IN1
ff_tx_data[6] => ff_tx_data[6].IN1
ff_tx_data[7] => ff_tx_data[7].IN1
ff_tx_data[8] => ff_tx_data[8].IN1
ff_tx_data[9] => ff_tx_data[9].IN1
ff_tx_data[10] => ff_tx_data[10].IN1
ff_tx_data[11] => ff_tx_data[11].IN1
ff_tx_data[12] => ff_tx_data[12].IN1
ff_tx_data[13] => ff_tx_data[13].IN1
ff_tx_data[14] => ff_tx_data[14].IN1
ff_tx_data[15] => ff_tx_data[15].IN1
ff_tx_data[16] => ff_tx_data[16].IN1
ff_tx_data[17] => ff_tx_data[17].IN1
ff_tx_data[18] => ff_tx_data[18].IN1
ff_tx_data[19] => ff_tx_data[19].IN1
ff_tx_data[20] => ff_tx_data[20].IN1
ff_tx_data[21] => ff_tx_data[21].IN1
ff_tx_data[22] => ff_tx_data[22].IN1
ff_tx_data[23] => ff_tx_data[23].IN1
ff_tx_data[24] => ff_tx_data[24].IN1
ff_tx_data[25] => ff_tx_data[25].IN1
ff_tx_data[26] => ff_tx_data[26].IN1
ff_tx_data[27] => ff_tx_data[27].IN1
ff_tx_data[28] => ff_tx_data[28].IN1
ff_tx_data[29] => ff_tx_data[29].IN1
ff_tx_data[30] => ff_tx_data[30].IN1
ff_tx_data[31] => ff_tx_data[31].IN1
ff_tx_mod[0] => ff_tx_mod[0].IN1
ff_tx_mod[1] => ff_tx_mod[1].IN1
ff_tx_sop => ff_tx_sop.IN1
ff_tx_eop => ff_tx_eop.IN1
ff_tx_err => ff_tx_err.IN1
ff_tx_wren => ff_tx_wren.IN1
ff_tx_rdy <= altera_tse_tx_min_ff:U_TXFF.ff_tx_rdy
ff_tx_septy <= altera_tse_tx_min_ff:U_TXFF.ff_tx_septy
tx_ff_uflow <= altera_tse_top_1geth:U_GETH.tx_ff_uflow
xoff_gen => xoff_gen.IN1
xon_gen => xon_gen.IN1
mac_addr[0] => mac_addr[0].IN1
mac_addr[1] => mac_addr[1].IN1
mac_addr[2] => mac_addr[2].IN1
mac_addr[3] => mac_addr[3].IN1
mac_addr[4] => mac_addr[4].IN1
mac_addr[5] => mac_addr[5].IN1
mac_addr[6] => mac_addr[6].IN1
mac_addr[7] => mac_addr[7].IN1
mac_addr[8] => mac_addr[8].IN1
mac_addr[9] => mac_addr[9].IN1
mac_addr[10] => mac_addr[10].IN1
mac_addr[11] => mac_addr[11].IN1
mac_addr[12] => mac_addr[12].IN1
mac_addr[13] => mac_addr[13].IN1
mac_addr[14] => mac_addr[14].IN1
mac_addr[15] => mac_addr[15].IN1
mac_addr[16] => mac_addr[16].IN1
mac_addr[17] => mac_addr[17].IN1
mac_addr[18] => mac_addr[18].IN1
mac_addr[19] => mac_addr[19].IN1
mac_addr[20] => mac_addr[20].IN1
mac_addr[21] => mac_addr[21].IN1
mac_addr[22] => mac_addr[22].IN1
mac_addr[23] => mac_addr[23].IN1
mac_addr[24] => mac_addr[24].IN1
mac_addr[25] => mac_addr[25].IN1
mac_addr[26] => mac_addr[26].IN1
mac_addr[27] => mac_addr[27].IN1
mac_addr[28] => mac_addr[28].IN1
mac_addr[29] => mac_addr[29].IN1
mac_addr[30] => mac_addr[30].IN1
mac_addr[31] => mac_addr[31].IN1
mac_addr[32] => mac_addr[32].IN1
mac_addr[33] => mac_addr[33].IN1
mac_addr[34] => mac_addr[34].IN1
mac_addr[35] => mac_addr[35].IN1
mac_addr[36] => mac_addr[36].IN1
mac_addr[37] => mac_addr[37].IN1
mac_addr[38] => mac_addr[38].IN1
mac_addr[39] => mac_addr[39].IN1
mac_addr[40] => mac_addr[40].IN1
mac_addr[41] => mac_addr[41].IN1
mac_addr[42] => mac_addr[42].IN1
mac_addr[43] => mac_addr[43].IN1
mac_addr[44] => mac_addr[44].IN1
mac_addr[45] => mac_addr[45].IN1
mac_addr[46] => mac_addr[46].IN1
mac_addr[47] => mac_addr[47].IN1
smac_0[0] => smac_0[0].IN1
smac_0[1] => smac_0[1].IN1
smac_0[2] => smac_0[2].IN1
smac_0[3] => smac_0[3].IN1
smac_0[4] => smac_0[4].IN1
smac_0[5] => smac_0[5].IN1
smac_0[6] => smac_0[6].IN1
smac_0[7] => smac_0[7].IN1
smac_0[8] => smac_0[8].IN1
smac_0[9] => smac_0[9].IN1
smac_0[10] => smac_0[10].IN1
smac_0[11] => smac_0[11].IN1
smac_0[12] => smac_0[12].IN1
smac_0[13] => smac_0[13].IN1
smac_0[14] => smac_0[14].IN1
smac_0[15] => smac_0[15].IN1
smac_0[16] => smac_0[16].IN1
smac_0[17] => smac_0[17].IN1
smac_0[18] => smac_0[18].IN1
smac_0[19] => smac_0[19].IN1
smac_0[20] => smac_0[20].IN1
smac_0[21] => smac_0[21].IN1
smac_0[22] => smac_0[22].IN1
smac_0[23] => smac_0[23].IN1
smac_0[24] => smac_0[24].IN1
smac_0[25] => smac_0[25].IN1
smac_0[26] => smac_0[26].IN1
smac_0[27] => smac_0[27].IN1
smac_0[28] => smac_0[28].IN1
smac_0[29] => smac_0[29].IN1
smac_0[30] => smac_0[30].IN1
smac_0[31] => smac_0[31].IN1
smac_0[32] => smac_0[32].IN1
smac_0[33] => smac_0[33].IN1
smac_0[34] => smac_0[34].IN1
smac_0[35] => smac_0[35].IN1
smac_0[36] => smac_0[36].IN1
smac_0[37] => smac_0[37].IN1
smac_0[38] => smac_0[38].IN1
smac_0[39] => smac_0[39].IN1
smac_0[40] => smac_0[40].IN1
smac_0[41] => smac_0[41].IN1
smac_0[42] => smac_0[42].IN1
smac_0[43] => smac_0[43].IN1
smac_0[44] => smac_0[44].IN1
smac_0[45] => smac_0[45].IN1
smac_0[46] => smac_0[46].IN1
smac_0[47] => smac_0[47].IN1
smac_1[0] => smac_1[0].IN1
smac_1[1] => smac_1[1].IN1
smac_1[2] => smac_1[2].IN1
smac_1[3] => smac_1[3].IN1
smac_1[4] => smac_1[4].IN1
smac_1[5] => smac_1[5].IN1
smac_1[6] => smac_1[6].IN1
smac_1[7] => smac_1[7].IN1
smac_1[8] => smac_1[8].IN1
smac_1[9] => smac_1[9].IN1
smac_1[10] => smac_1[10].IN1
smac_1[11] => smac_1[11].IN1
smac_1[12] => smac_1[12].IN1
smac_1[13] => smac_1[13].IN1
smac_1[14] => smac_1[14].IN1
smac_1[15] => smac_1[15].IN1
smac_1[16] => smac_1[16].IN1
smac_1[17] => smac_1[17].IN1
smac_1[18] => smac_1[18].IN1
smac_1[19] => smac_1[19].IN1
smac_1[20] => smac_1[20].IN1
smac_1[21] => smac_1[21].IN1
smac_1[22] => smac_1[22].IN1
smac_1[23] => smac_1[23].IN1
smac_1[24] => smac_1[24].IN1
smac_1[25] => smac_1[25].IN1
smac_1[26] => smac_1[26].IN1
smac_1[27] => smac_1[27].IN1
smac_1[28] => smac_1[28].IN1
smac_1[29] => smac_1[29].IN1
smac_1[30] => smac_1[30].IN1
smac_1[31] => smac_1[31].IN1
smac_1[32] => smac_1[32].IN1
smac_1[33] => smac_1[33].IN1
smac_1[34] => smac_1[34].IN1
smac_1[35] => smac_1[35].IN1
smac_1[36] => smac_1[36].IN1
smac_1[37] => smac_1[37].IN1
smac_1[38] => smac_1[38].IN1
smac_1[39] => smac_1[39].IN1
smac_1[40] => smac_1[40].IN1
smac_1[41] => smac_1[41].IN1
smac_1[42] => smac_1[42].IN1
smac_1[43] => smac_1[43].IN1
smac_1[44] => smac_1[44].IN1
smac_1[45] => smac_1[45].IN1
smac_1[46] => smac_1[46].IN1
smac_1[47] => smac_1[47].IN1
smac_2[0] => smac_2[0].IN1
smac_2[1] => smac_2[1].IN1
smac_2[2] => smac_2[2].IN1
smac_2[3] => smac_2[3].IN1
smac_2[4] => smac_2[4].IN1
smac_2[5] => smac_2[5].IN1
smac_2[6] => smac_2[6].IN1
smac_2[7] => smac_2[7].IN1
smac_2[8] => smac_2[8].IN1
smac_2[9] => smac_2[9].IN1
smac_2[10] => smac_2[10].IN1
smac_2[11] => smac_2[11].IN1
smac_2[12] => smac_2[12].IN1
smac_2[13] => smac_2[13].IN1
smac_2[14] => smac_2[14].IN1
smac_2[15] => smac_2[15].IN1
smac_2[16] => smac_2[16].IN1
smac_2[17] => smac_2[17].IN1
smac_2[18] => smac_2[18].IN1
smac_2[19] => smac_2[19].IN1
smac_2[20] => smac_2[20].IN1
smac_2[21] => smac_2[21].IN1
smac_2[22] => smac_2[22].IN1
smac_2[23] => smac_2[23].IN1
smac_2[24] => smac_2[24].IN1
smac_2[25] => smac_2[25].IN1
smac_2[26] => smac_2[26].IN1
smac_2[27] => smac_2[27].IN1
smac_2[28] => smac_2[28].IN1
smac_2[29] => smac_2[29].IN1
smac_2[30] => smac_2[30].IN1
smac_2[31] => smac_2[31].IN1
smac_2[32] => smac_2[32].IN1
smac_2[33] => smac_2[33].IN1
smac_2[34] => smac_2[34].IN1
smac_2[35] => smac_2[35].IN1
smac_2[36] => smac_2[36].IN1
smac_2[37] => smac_2[37].IN1
smac_2[38] => smac_2[38].IN1
smac_2[39] => smac_2[39].IN1
smac_2[40] => smac_2[40].IN1
smac_2[41] => smac_2[41].IN1
smac_2[42] => smac_2[42].IN1
smac_2[43] => smac_2[43].IN1
smac_2[44] => smac_2[44].IN1
smac_2[45] => smac_2[45].IN1
smac_2[46] => smac_2[46].IN1
smac_2[47] => smac_2[47].IN1
smac_3[0] => smac_3[0].IN1
smac_3[1] => smac_3[1].IN1
smac_3[2] => smac_3[2].IN1
smac_3[3] => smac_3[3].IN1
smac_3[4] => smac_3[4].IN1
smac_3[5] => smac_3[5].IN1
smac_3[6] => smac_3[6].IN1
smac_3[7] => smac_3[7].IN1
smac_3[8] => smac_3[8].IN1
smac_3[9] => smac_3[9].IN1
smac_3[10] => smac_3[10].IN1
smac_3[11] => smac_3[11].IN1
smac_3[12] => smac_3[12].IN1
smac_3[13] => smac_3[13].IN1
smac_3[14] => smac_3[14].IN1
smac_3[15] => smac_3[15].IN1
smac_3[16] => smac_3[16].IN1
smac_3[17] => smac_3[17].IN1
smac_3[18] => smac_3[18].IN1
smac_3[19] => smac_3[19].IN1
smac_3[20] => smac_3[20].IN1
smac_3[21] => smac_3[21].IN1
smac_3[22] => smac_3[22].IN1
smac_3[23] => smac_3[23].IN1
smac_3[24] => smac_3[24].IN1
smac_3[25] => smac_3[25].IN1
smac_3[26] => smac_3[26].IN1
smac_3[27] => smac_3[27].IN1
smac_3[28] => smac_3[28].IN1
smac_3[29] => smac_3[29].IN1
smac_3[30] => smac_3[30].IN1
smac_3[31] => smac_3[31].IN1
smac_3[32] => smac_3[32].IN1
smac_3[33] => smac_3[33].IN1
smac_3[34] => smac_3[34].IN1
smac_3[35] => smac_3[35].IN1
smac_3[36] => smac_3[36].IN1
smac_3[37] => smac_3[37].IN1
smac_3[38] => smac_3[38].IN1
smac_3[39] => smac_3[39].IN1
smac_3[40] => smac_3[40].IN1
smac_3[41] => smac_3[41].IN1
smac_3[42] => smac_3[42].IN1
smac_3[43] => smac_3[43].IN1
smac_3[44] => smac_3[44].IN1
smac_3[45] => smac_3[45].IN1
smac_3[46] => smac_3[46].IN1
smac_3[47] => smac_3[47].IN1
tx_shift16 => tx_shift16.IN1
rx_shift16 => rx_shift16.IN1
sw_reset => sw_reset.IN2
rx_reset_done <= altera_tse_rx_min_ff:U_RXFF.sw_reset_done
rx_total_lgth[0] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[1] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[2] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[3] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[4] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[5] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[6] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[7] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[8] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[9] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[10] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[11] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[12] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[13] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[14] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_lgth[15] <= altera_tse_top_1geth:U_GETH.rx_total_lgth
rx_total_val <= altera_tse_top_1geth:U_GETH.rx_total_val
rx_frm_stat_ena <= altera_tse_top_1geth:U_GETH.rx_frm_stat_ena
rx_frm_stat_val <= altera_tse_top_1geth:U_GETH.rx_frm_stat_val
rx_frm_err <= altera_tse_top_1geth:U_GETH.rx_frm_err
rx_frm_crc_err <= altera_tse_top_1geth:U_GETH.rx_frm_crc_err
rx_frm_length[0] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[1] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[2] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[3] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[4] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[5] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[6] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[7] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[8] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[9] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[10] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[11] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[12] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[13] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[14] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_length[15] <= altera_tse_top_1geth:U_GETH.rx_frm_length
rx_frm_vlan <= altera_tse_top_1geth:U_GETH.rx_frm_vlan
rx_frm_stack_vlan <= altera_tse_top_1geth:U_GETH.rx_frm_stack_vlan
rx_frm_unicast <= altera_tse_top_1geth:U_GETH.rx_frm_unicast
rx_frm_broadcast <= altera_tse_top_1geth:U_GETH.rx_frm_broadcast
rx_frm_mltcast <= altera_tse_top_1geth:U_GETH.rx_frm_mltcast
pause_rcv <= altera_tse_top_1geth:U_GETH.pause_rcv
frm_align_err <= altera_tse_top_1geth:U_GETH.frm_align_err
frm_crc_err <= altera_tse_top_1geth:U_GETH.frm_crc_err
long_crc_err <= altera_tse_top_1geth:U_GETH.long_crc_err
short_crc_err <= altera_tse_top_1geth:U_GETH.short_crc_err
frm_discard <= altera_tse_top_1geth:U_GETH.frm_discard
tx_frm_stat_val <= altera_tse_top_1geth:U_GETH.tx_frm_stat_val
tx_frm_err <= altera_tse_top_1geth:U_GETH.tx_frm_err
tx_frm_length[0] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[1] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[2] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[3] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[4] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[5] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[6] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[7] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[8] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[9] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[10] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[11] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[12] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[13] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[14] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_length[15] <= altera_tse_top_1geth:U_GETH.tx_frm_length
tx_frm_unicast <= altera_tse_top_1geth:U_GETH.tx_frm_unicast
tx_frm_broadcast <= altera_tse_top_1geth:U_GETH.tx_frm_broadcast
tx_frm_mltcast <= altera_tse_top_1geth:U_GETH.tx_frm_mltcast
excess_col <= excess_col.DB_MAX_OUTPUT_PORT_TYPE
late_col <= late_col.DB_MAX_OUTPUT_PORT_TYPE
pause_tx <= altera_tse_top_1geth:U_GETH.pause_tx
tx_addr_sel[0] => tx_addr_sel[0].IN1
tx_addr_sel[1] => tx_addr_sel[1].IN1
tx_addr_sel[2] => tx_addr_sel[2].IN1
src_mac_insert => src_mac_insert.IN1
enable_tx => enable_tx.IN1
tx_ipg_len[0] => tx_ipg_len[0].IN1
tx_ipg_len[1] => tx_ipg_len[1].IN1
tx_ipg_len[2] => tx_ipg_len[2].IN1
tx_ipg_len[3] => tx_ipg_len[3].IN1
tx_ipg_len[4] => tx_ipg_len[4].IN1
tx_crc_fwd => tx_crc_fwd.IN1
enable_rx => enable_rx.IN1
no_lgth_check => no_lgth_check.IN1
rx_err_frm_disc => rx_err_frm_disc.IN1
frm_length_max[0] => frm_length_max[0].IN1
frm_length_max[1] => frm_length_max[1].IN1
frm_length_max[2] => frm_length_max[2].IN1
frm_length_max[3] => frm_length_max[3].IN1
frm_length_max[4] => frm_length_max[4].IN1
frm_length_max[5] => frm_length_max[5].IN1
frm_length_max[6] => frm_length_max[6].IN1
frm_length_max[7] => frm_length_max[7].IN1
frm_length_max[8] => frm_length_max[8].IN1
frm_length_max[9] => frm_length_max[9].IN1
frm_length_max[10] => frm_length_max[10].IN1
frm_length_max[11] => frm_length_max[11].IN1
frm_length_max[12] => frm_length_max[12].IN1
frm_length_max[13] => frm_length_max[13].IN1
frm_length_max[14] => frm_length_max[14].IN1
frm_length_max[15] => frm_length_max[15].IN1
promis_en => promis_en.IN1
crc_fwd => crc_fwd.IN1
pad_ena => pad_ena.IN1
half_duplex_ena => half_duplex_ena.IN2
ethernet_mode => ethernet_mode.IN2
magic_ena => magic_ena.IN1
sleep_ena => sleep_ena.IN1
magic_detect <= <GND>
cmd_frm_ena => cmd_frm_ena.IN1
pause_quant[0] => pause_quant[0].IN1
pause_quant[1] => pause_quant[1].IN1
pause_quant[2] => pause_quant[2].IN1
pause_quant[3] => pause_quant[3].IN1
pause_quant[4] => pause_quant[4].IN1
pause_quant[5] => pause_quant[5].IN1
pause_quant[6] => pause_quant[6].IN1
pause_quant[7] => pause_quant[7].IN1
pause_quant[8] => pause_quant[8].IN1
pause_quant[9] => pause_quant[9].IN1
pause_quant[10] => pause_quant[10].IN1
pause_quant[11] => pause_quant[11].IN1
pause_quant[12] => pause_quant[12].IN1
pause_quant[13] => pause_quant[13].IN1
pause_quant[14] => pause_quant[14].IN1
pause_quant[15] => pause_quant[15].IN1
pause_fwd => pause_fwd.IN1
pause_ignore => pause_ignore.IN1
holdoff_quant[0] => holdoff_quant[0].IN1
holdoff_quant[1] => holdoff_quant[1].IN1
holdoff_quant[2] => holdoff_quant[2].IN1
holdoff_quant[3] => holdoff_quant[3].IN1
holdoff_quant[4] => holdoff_quant[4].IN1
holdoff_quant[5] => holdoff_quant[5].IN1
holdoff_quant[6] => holdoff_quant[6].IN1
holdoff_quant[7] => holdoff_quant[7].IN1
holdoff_quant[8] => holdoff_quant[8].IN1
holdoff_quant[9] => holdoff_quant[9].IN1
holdoff_quant[10] => holdoff_quant[10].IN1
holdoff_quant[11] => holdoff_quant[11].IN1
holdoff_quant[12] => holdoff_quant[12].IN1
holdoff_quant[13] => holdoff_quant[13].IN1
holdoff_quant[14] => holdoff_quant[14].IN1
holdoff_quant[15] => holdoff_quant[15].IN1
mhash_sel => mhash_sel.IN1
hash_wren => hash_wren.IN1
hash_wdata => hash_wdata.IN1
hash_waddr[0] => hash_waddr[0].IN1
hash_waddr[1] => hash_waddr[1].IN1
hash_waddr[2] => hash_waddr[2].IN1
hash_waddr[3] => hash_waddr[3].IN1
hash_waddr[4] => hash_waddr[4].IN1
hash_waddr[5] => hash_waddr[5].IN1


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH
reset_rx_clk => reset_rx_clk.IN2
reset_tx_clk => reset_tx_clk.IN3
rx_clk => rx_clk.IN2
rxclk_ena => rxclk_ena.IN2
tx_clk => tx_clk.IN3
txclk_ena => txclk_ena.IN2
reg_clk => reg_clk.IN1
mii_align_err => mii_align_err.IN1
gm_rx_crs => gm_rx_crs.IN1
gm_rx_col => gm_rx_col.IN2
col <= col.DB_MAX_OUTPUT_PORT_TYPE
late_col => late_col.IN1
excess_col => excess_col.IN1
crs <= altera_tse_mac_tx:U_TX.crs
gm_rx_d[0] => gm_rx_d[0].IN2
gm_rx_d[1] => gm_rx_d[1].IN2
gm_rx_d[2] => gm_rx_d[2].IN2
gm_rx_d[3] => gm_rx_d[3].IN2
gm_rx_d[4] => gm_rx_d[4].IN2
gm_rx_d[5] => gm_rx_d[5].IN2
gm_rx_d[6] => gm_rx_d[6].IN2
gm_rx_d[7] => gm_rx_d[7].IN2
gm_rx_en => gm_rx_en.IN2
gm_rx_err => gm_rx_err.IN1
gm_tx_d[0] <= gm_tx_d_i[0].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[1] <= gm_tx_d_i[1].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[2] <= gm_tx_d_i[2].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[3] <= gm_tx_d_i[3].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[4] <= gm_tx_d_i[4].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[5] <= gm_tx_d_i[5].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[6] <= gm_tx_d_i[6].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_d[7] <= gm_tx_d_i[7].DB_MAX_OUTPUT_PORT_TYPE
gm_tx_en <= gm_tx_en_i.DB_MAX_OUTPUT_PORT_TYPE
gm_tx_err <= gm_tx_err_i.DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[0] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[1] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[2] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[3] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[4] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[5] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[6] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[7] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[8] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[9] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[10] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[11] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[12] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[13] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[14] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[15] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[16] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[17] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[18] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[19] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[20] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[21] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_data[22] <= altera_tse_mac_rx:U_RX.rx_stat_data
rx_stat_wren <= altera_tse_mac_rx:U_RX.rx_stat_wren
rx_data_int[0] <= altera_tse_mac_rx:U_RX.rx_data_int
rx_data_int[1] <= altera_tse_mac_rx:U_RX.rx_data_int
rx_data_int[2] <= altera_tse_mac_rx:U_RX.rx_data_int
rx_data_int[3] <= altera_tse_mac_rx:U_RX.rx_data_int
rx_data_int[4] <= altera_tse_mac_rx:U_RX.rx_data_int
rx_data_int[5] <= altera_tse_mac_rx:U_RX.rx_data_int
rx_data_int[6] <= altera_tse_mac_rx:U_RX.rx_data_int
rx_data_int[7] <= altera_tse_mac_rx:U_RX.rx_data_int
rx_a_full => rx_a_full.IN1
rx_sop_int <= altera_tse_mac_rx:U_RX.rx_sop_int
rx_eop_int <= altera_tse_mac_rx:U_RX.rx_eop_int
rx_wren_int <= altera_tse_mac_rx:U_RX.rx_wren_int
rx_data_val <= altera_tse_mac_rx:U_RX.rx_data_val
rx_ucast <= altera_tse_mac_rx:U_RX.rx_ucast
rx_bcast <= altera_tse_mac_rx:U_RX.rx_bcast
rx_mcast <= altera_tse_mac_rx:U_RX.rx_mcast
rx_vlan <= altera_tse_mac_rx:U_RX.rx_vlan
tx_stat_empty => tx_stat_empty.IN1
tx_stat => tx_stat.IN1
tx_stat_rden <= altera_tse_mac_tx:U_TX.tx_stat_rden
rx_septy => rx_septy.IN1
tx_data_int[0] => tx_data_int[0].IN1
tx_data_int[1] => tx_data_int[1].IN1
tx_data_int[2] => tx_data_int[2].IN1
tx_data_int[3] => tx_data_int[3].IN1
tx_data_int[4] => tx_data_int[4].IN1
tx_data_int[5] => tx_data_int[5].IN1
tx_data_int[6] => tx_data_int[6].IN1
tx_data_int[7] => tx_data_int[7].IN1
tx_sav_int => tx_sav_int.IN1
tx_empty => tx_empty.IN1
tx_sop_int => tx_sop_int.IN1
tx_eop_int => tx_eop_int.IN1
tx_rden_int <= altera_tse_mac_tx:U_TX.tx_rden_int
tx_ff_uflow <= altera_tse_mac_tx:U_TX.tx_ff_uflow
xoff_gen => xoff_gen.IN1
xon_gen => xon_gen.IN1
mac_addr[0] => mac_addr[0].IN2
mac_addr[1] => mac_addr[1].IN2
mac_addr[2] => mac_addr[2].IN2
mac_addr[3] => mac_addr[3].IN2
mac_addr[4] => mac_addr[4].IN2
mac_addr[5] => mac_addr[5].IN2
mac_addr[6] => mac_addr[6].IN2
mac_addr[7] => mac_addr[7].IN2
mac_addr[8] => mac_addr[8].IN2
mac_addr[9] => mac_addr[9].IN2
mac_addr[10] => mac_addr[10].IN2
mac_addr[11] => mac_addr[11].IN2
mac_addr[12] => mac_addr[12].IN2
mac_addr[13] => mac_addr[13].IN2
mac_addr[14] => mac_addr[14].IN2
mac_addr[15] => mac_addr[15].IN2
mac_addr[16] => mac_addr[16].IN2
mac_addr[17] => mac_addr[17].IN2
mac_addr[18] => mac_addr[18].IN2
mac_addr[19] => mac_addr[19].IN2
mac_addr[20] => mac_addr[20].IN2
mac_addr[21] => mac_addr[21].IN2
mac_addr[22] => mac_addr[22].IN2
mac_addr[23] => mac_addr[23].IN2
mac_addr[24] => mac_addr[24].IN2
mac_addr[25] => mac_addr[25].IN2
mac_addr[26] => mac_addr[26].IN2
mac_addr[27] => mac_addr[27].IN2
mac_addr[28] => mac_addr[28].IN2
mac_addr[29] => mac_addr[29].IN2
mac_addr[30] => mac_addr[30].IN2
mac_addr[31] => mac_addr[31].IN2
mac_addr[32] => mac_addr[32].IN2
mac_addr[33] => mac_addr[33].IN2
mac_addr[34] => mac_addr[34].IN2
mac_addr[35] => mac_addr[35].IN2
mac_addr[36] => mac_addr[36].IN2
mac_addr[37] => mac_addr[37].IN2
mac_addr[38] => mac_addr[38].IN2
mac_addr[39] => mac_addr[39].IN2
mac_addr[40] => mac_addr[40].IN2
mac_addr[41] => mac_addr[41].IN2
mac_addr[42] => mac_addr[42].IN2
mac_addr[43] => mac_addr[43].IN2
mac_addr[44] => mac_addr[44].IN2
mac_addr[45] => mac_addr[45].IN2
mac_addr[46] => mac_addr[46].IN2
mac_addr[47] => mac_addr[47].IN2
smac_0[0] => smac_0[0].IN2
smac_0[1] => smac_0[1].IN2
smac_0[2] => smac_0[2].IN2
smac_0[3] => smac_0[3].IN2
smac_0[4] => smac_0[4].IN2
smac_0[5] => smac_0[5].IN2
smac_0[6] => smac_0[6].IN2
smac_0[7] => smac_0[7].IN2
smac_0[8] => smac_0[8].IN2
smac_0[9] => smac_0[9].IN2
smac_0[10] => smac_0[10].IN2
smac_0[11] => smac_0[11].IN2
smac_0[12] => smac_0[12].IN2
smac_0[13] => smac_0[13].IN2
smac_0[14] => smac_0[14].IN2
smac_0[15] => smac_0[15].IN2
smac_0[16] => smac_0[16].IN2
smac_0[17] => smac_0[17].IN2
smac_0[18] => smac_0[18].IN2
smac_0[19] => smac_0[19].IN2
smac_0[20] => smac_0[20].IN2
smac_0[21] => smac_0[21].IN2
smac_0[22] => smac_0[22].IN2
smac_0[23] => smac_0[23].IN2
smac_0[24] => smac_0[24].IN2
smac_0[25] => smac_0[25].IN2
smac_0[26] => smac_0[26].IN2
smac_0[27] => smac_0[27].IN2
smac_0[28] => smac_0[28].IN2
smac_0[29] => smac_0[29].IN2
smac_0[30] => smac_0[30].IN2
smac_0[31] => smac_0[31].IN2
smac_0[32] => smac_0[32].IN2
smac_0[33] => smac_0[33].IN2
smac_0[34] => smac_0[34].IN2
smac_0[35] => smac_0[35].IN2
smac_0[36] => smac_0[36].IN2
smac_0[37] => smac_0[37].IN2
smac_0[38] => smac_0[38].IN2
smac_0[39] => smac_0[39].IN2
smac_0[40] => smac_0[40].IN2
smac_0[41] => smac_0[41].IN2
smac_0[42] => smac_0[42].IN2
smac_0[43] => smac_0[43].IN2
smac_0[44] => smac_0[44].IN2
smac_0[45] => smac_0[45].IN2
smac_0[46] => smac_0[46].IN2
smac_0[47] => smac_0[47].IN2
smac_1[0] => smac_1[0].IN2
smac_1[1] => smac_1[1].IN2
smac_1[2] => smac_1[2].IN2
smac_1[3] => smac_1[3].IN2
smac_1[4] => smac_1[4].IN2
smac_1[5] => smac_1[5].IN2
smac_1[6] => smac_1[6].IN2
smac_1[7] => smac_1[7].IN2
smac_1[8] => smac_1[8].IN2
smac_1[9] => smac_1[9].IN2
smac_1[10] => smac_1[10].IN2
smac_1[11] => smac_1[11].IN2
smac_1[12] => smac_1[12].IN2
smac_1[13] => smac_1[13].IN2
smac_1[14] => smac_1[14].IN2
smac_1[15] => smac_1[15].IN2
smac_1[16] => smac_1[16].IN2
smac_1[17] => smac_1[17].IN2
smac_1[18] => smac_1[18].IN2
smac_1[19] => smac_1[19].IN2
smac_1[20] => smac_1[20].IN2
smac_1[21] => smac_1[21].IN2
smac_1[22] => smac_1[22].IN2
smac_1[23] => smac_1[23].IN2
smac_1[24] => smac_1[24].IN2
smac_1[25] => smac_1[25].IN2
smac_1[26] => smac_1[26].IN2
smac_1[27] => smac_1[27].IN2
smac_1[28] => smac_1[28].IN2
smac_1[29] => smac_1[29].IN2
smac_1[30] => smac_1[30].IN2
smac_1[31] => smac_1[31].IN2
smac_1[32] => smac_1[32].IN2
smac_1[33] => smac_1[33].IN2
smac_1[34] => smac_1[34].IN2
smac_1[35] => smac_1[35].IN2
smac_1[36] => smac_1[36].IN2
smac_1[37] => smac_1[37].IN2
smac_1[38] => smac_1[38].IN2
smac_1[39] => smac_1[39].IN2
smac_1[40] => smac_1[40].IN2
smac_1[41] => smac_1[41].IN2
smac_1[42] => smac_1[42].IN2
smac_1[43] => smac_1[43].IN2
smac_1[44] => smac_1[44].IN2
smac_1[45] => smac_1[45].IN2
smac_1[46] => smac_1[46].IN2
smac_1[47] => smac_1[47].IN2
smac_2[0] => smac_2[0].IN2
smac_2[1] => smac_2[1].IN2
smac_2[2] => smac_2[2].IN2
smac_2[3] => smac_2[3].IN2
smac_2[4] => smac_2[4].IN2
smac_2[5] => smac_2[5].IN2
smac_2[6] => smac_2[6].IN2
smac_2[7] => smac_2[7].IN2
smac_2[8] => smac_2[8].IN2
smac_2[9] => smac_2[9].IN2
smac_2[10] => smac_2[10].IN2
smac_2[11] => smac_2[11].IN2
smac_2[12] => smac_2[12].IN2
smac_2[13] => smac_2[13].IN2
smac_2[14] => smac_2[14].IN2
smac_2[15] => smac_2[15].IN2
smac_2[16] => smac_2[16].IN2
smac_2[17] => smac_2[17].IN2
smac_2[18] => smac_2[18].IN2
smac_2[19] => smac_2[19].IN2
smac_2[20] => smac_2[20].IN2
smac_2[21] => smac_2[21].IN2
smac_2[22] => smac_2[22].IN2
smac_2[23] => smac_2[23].IN2
smac_2[24] => smac_2[24].IN2
smac_2[25] => smac_2[25].IN2
smac_2[26] => smac_2[26].IN2
smac_2[27] => smac_2[27].IN2
smac_2[28] => smac_2[28].IN2
smac_2[29] => smac_2[29].IN2
smac_2[30] => smac_2[30].IN2
smac_2[31] => smac_2[31].IN2
smac_2[32] => smac_2[32].IN2
smac_2[33] => smac_2[33].IN2
smac_2[34] => smac_2[34].IN2
smac_2[35] => smac_2[35].IN2
smac_2[36] => smac_2[36].IN2
smac_2[37] => smac_2[37].IN2
smac_2[38] => smac_2[38].IN2
smac_2[39] => smac_2[39].IN2
smac_2[40] => smac_2[40].IN2
smac_2[41] => smac_2[41].IN2
smac_2[42] => smac_2[42].IN2
smac_2[43] => smac_2[43].IN2
smac_2[44] => smac_2[44].IN2
smac_2[45] => smac_2[45].IN2
smac_2[46] => smac_2[46].IN2
smac_2[47] => smac_2[47].IN2
smac_3[0] => smac_3[0].IN2
smac_3[1] => smac_3[1].IN2
smac_3[2] => smac_3[2].IN2
smac_3[3] => smac_3[3].IN2
smac_3[4] => smac_3[4].IN2
smac_3[5] => smac_3[5].IN2
smac_3[6] => smac_3[6].IN2
smac_3[7] => smac_3[7].IN2
smac_3[8] => smac_3[8].IN2
smac_3[9] => smac_3[9].IN2
smac_3[10] => smac_3[10].IN2
smac_3[11] => smac_3[11].IN2
smac_3[12] => smac_3[12].IN2
smac_3[13] => smac_3[13].IN2
smac_3[14] => smac_3[14].IN2
smac_3[15] => smac_3[15].IN2
smac_3[16] => smac_3[16].IN2
smac_3[17] => smac_3[17].IN2
smac_3[18] => smac_3[18].IN2
smac_3[19] => smac_3[19].IN2
smac_3[20] => smac_3[20].IN2
smac_3[21] => smac_3[21].IN2
smac_3[22] => smac_3[22].IN2
smac_3[23] => smac_3[23].IN2
smac_3[24] => smac_3[24].IN2
smac_3[25] => smac_3[25].IN2
smac_3[26] => smac_3[26].IN2
smac_3[27] => smac_3[27].IN2
smac_3[28] => smac_3[28].IN2
smac_3[29] => smac_3[29].IN2
smac_3[30] => smac_3[30].IN2
smac_3[31] => smac_3[31].IN2
smac_3[32] => smac_3[32].IN2
smac_3[33] => smac_3[33].IN2
smac_3[34] => smac_3[34].IN2
smac_3[35] => smac_3[35].IN2
smac_3[36] => smac_3[36].IN2
smac_3[37] => smac_3[37].IN2
smac_3[38] => smac_3[38].IN2
smac_3[39] => smac_3[39].IN2
smac_3[40] => smac_3[40].IN2
smac_3[41] => smac_3[41].IN2
smac_3[42] => smac_3[42].IN2
smac_3[43] => smac_3[43].IN2
smac_3[44] => smac_3[44].IN2
smac_3[45] => smac_3[45].IN2
smac_3[46] => smac_3[46].IN2
smac_3[47] => smac_3[47].IN2
rx_frm_stat_ena <= altera_tse_mac_rx:U_RX.rx_frm_stat_ena
rx_frm_stat_val <= altera_tse_rx_stat_extract:U_RXSTAT.frm_stat_val
rx_total_lgth[0] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[1] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[2] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[3] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[4] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[5] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[6] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[7] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[8] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[9] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[10] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[11] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[12] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[13] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[14] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_lgth[15] <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth
rx_total_val <= altera_tse_rx_stat_extract:U_RXSTAT.total_lgth_val
rx_frm_err <= altera_tse_rx_stat_extract:U_RXSTAT.frm_err
rx_frm_crc_err <= altera_tse_rx_stat_extract:U_RXSTAT.frm_crc_err
rx_frm_length[0] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[1] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[2] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[3] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[4] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[5] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[6] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[7] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[8] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[9] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[10] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[11] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[12] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[13] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[14] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_length[15] <= altera_tse_rx_stat_extract:U_RXSTAT.frm_length
rx_frm_vlan <= altera_tse_rx_stat_extract:U_RXSTAT.frm_vlan
rx_frm_stack_vlan <= altera_tse_rx_stat_extract:U_RXSTAT.frm_stack_vlan
rx_frm_unicast <= altera_tse_rx_stat_extract:U_RXSTAT.frm_unicast
rx_frm_broadcast <= altera_tse_rx_stat_extract:U_RXSTAT.frm_broadcast
rx_frm_mltcast <= altera_tse_rx_stat_extract:U_RXSTAT.frm_mltcast
pause_rcv <= pause_rcv_i.DB_MAX_OUTPUT_PORT_TYPE
frm_align_err <= altera_tse_mac_rx:U_RX.frm_align_err
frm_crc_err <= altera_tse_mac_rx:U_RX.frm_crc_err
long_crc_err <= altera_tse_mac_rx:U_RX.long_crc_err
short_crc_err <= altera_tse_mac_rx:U_RX.short_crc_err
frm_discard <= altera_tse_mac_rx:U_RX.frm_discard
tx_frm_stat_val <= altera_tse_tx_stat_extract:U_TXSTAT.frm_stat_val
tx_frm_err <= altera_tse_tx_stat_extract:U_TXSTAT.frm_err
tx_frm_length[0] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[1] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[2] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[3] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[4] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[5] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[6] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[7] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[8] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[9] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[10] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[11] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[12] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[13] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[14] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_length[15] <= altera_tse_tx_stat_extract:U_TXSTAT.frm_length
tx_frm_unicast <= altera_tse_tx_stat_extract:U_TXSTAT.frm_unicast
tx_frm_broadcast <= altera_tse_tx_stat_extract:U_TXSTAT.frm_broadcast
tx_frm_mltcast <= altera_tse_tx_stat_extract:U_TXSTAT.frm_mltcast
pause_tx <= altera_tse_mac_tx:U_TX.pause_tx
enable_tx => enable_tx.IN1
tx_addr_sel[0] => tx_addr_sel[0].IN1
tx_addr_sel[1] => tx_addr_sel[1].IN1
tx_addr_sel[2] => tx_addr_sel[2].IN1
src_mac_insert => src_mac_insert.IN1
mac_ena_int => mac_ena_int.IN1
tx_ipg_len[0] => tx_ipg_len[0].IN1
tx_ipg_len[1] => tx_ipg_len[1].IN1
tx_ipg_len[2] => tx_ipg_len[2].IN1
tx_ipg_len[3] => tx_ipg_len[3].IN1
tx_ipg_len[4] => tx_ipg_len[4].IN1
tx_crc_fwd => tx_crc_fwd.IN1
enable_rx => enable_rx.IN2
promis_en => promis_en.IN1
frm_length_max[0] => frm_length_max[0].IN1
frm_length_max[1] => frm_length_max[1].IN1
frm_length_max[2] => frm_length_max[2].IN1
frm_length_max[3] => frm_length_max[3].IN1
frm_length_max[4] => frm_length_max[4].IN1
frm_length_max[5] => frm_length_max[5].IN1
frm_length_max[6] => frm_length_max[6].IN1
frm_length_max[7] => frm_length_max[7].IN1
frm_length_max[8] => frm_length_max[8].IN1
frm_length_max[9] => frm_length_max[9].IN1
frm_length_max[10] => frm_length_max[10].IN1
frm_length_max[11] => frm_length_max[11].IN1
frm_length_max[12] => frm_length_max[12].IN1
frm_length_max[13] => frm_length_max[13].IN1
frm_length_max[14] => frm_length_max[14].IN1
frm_length_max[15] => frm_length_max[15].IN1
no_lgth_check => no_lgth_check.IN1
crc_fwd => crc_fwd.IN1
pad_ena => pad_ena.IN1
half_duplex_ena => half_duplex_ena.IN2
ethernet_mode => ethernet_mode.IN2
sw_reset => sw_reset.IN1
cmd_frm_ena => cmd_frm_ena.IN1
pause_quant[0] => pause_quant[0].IN1
pause_quant[1] => pause_quant[1].IN1
pause_quant[2] => pause_quant[2].IN1
pause_quant[3] => pause_quant[3].IN1
pause_quant[4] => pause_quant[4].IN1
pause_quant[5] => pause_quant[5].IN1
pause_quant[6] => pause_quant[6].IN1
pause_quant[7] => pause_quant[7].IN1
pause_quant[8] => pause_quant[8].IN1
pause_quant[9] => pause_quant[9].IN1
pause_quant[10] => pause_quant[10].IN1
pause_quant[11] => pause_quant[11].IN1
pause_quant[12] => pause_quant[12].IN1
pause_quant[13] => pause_quant[13].IN1
pause_quant[14] => pause_quant[14].IN1
pause_quant[15] => pause_quant[15].IN1
holdoff_quant[0] => holdoff_quant[0].IN1
holdoff_quant[1] => holdoff_quant[1].IN1
holdoff_quant[2] => holdoff_quant[2].IN1
holdoff_quant[3] => holdoff_quant[3].IN1
holdoff_quant[4] => holdoff_quant[4].IN1
holdoff_quant[5] => holdoff_quant[5].IN1
holdoff_quant[6] => holdoff_quant[6].IN1
holdoff_quant[7] => holdoff_quant[7].IN1
holdoff_quant[8] => holdoff_quant[8].IN1
holdoff_quant[9] => holdoff_quant[9].IN1
holdoff_quant[10] => holdoff_quant[10].IN1
holdoff_quant[11] => holdoff_quant[11].IN1
holdoff_quant[12] => holdoff_quant[12].IN1
holdoff_quant[13] => holdoff_quant[13].IN1
holdoff_quant[14] => holdoff_quant[14].IN1
holdoff_quant[15] => holdoff_quant[15].IN1
pause_fwd => pause_fwd.IN1
pause_ignore => pause_ignore.IN1
magic_ena => magic_ena.IN2
sleep_ena => sleep_ena.IN2
magic_pkt_ena <= altera_tse_mac_rx:U_RX.magic_pkt_ena
mhash_sel => mhash_sel.IN1
hash_wren => hash_wren.IN1
hash_wdata => hash_wdata.IN1
hash_waddr[0] => hash_waddr[0].IN1
hash_waddr[1] => hash_waddr[1].IN1
hash_waddr[2] => hash_waddr[2].IN1
hash_waddr[3] => hash_waddr[3].IN1
hash_waddr[4] => hash_waddr[4].IN1
hash_waddr[5] => hash_waddr[5].IN1


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT
reset => frm_crc_err_r.ACLR
reset => frm_err_r.ACLR
reset => frm_stat_val_r.ACLR
reset => frm_mltcast~reg0.ACLR
reset => frm_broadcast~reg0.ACLR
reset => frm_unicast~reg0.ACLR
reset => frm_stack_vlan~reg0.ACLR
reset => frm_vlan~reg0.ACLR
reset => frm_length[0]~reg0.ACLR
reset => frm_length[1]~reg0.ACLR
reset => frm_length[2]~reg0.ACLR
reset => frm_length[3]~reg0.ACLR
reset => frm_length[4]~reg0.ACLR
reset => frm_length[5]~reg0.ACLR
reset => frm_length[6]~reg0.ACLR
reset => frm_length[7]~reg0.ACLR
reset => frm_length[8]~reg0.ACLR
reset => frm_length[9]~reg0.ACLR
reset => frm_length[10]~reg0.ACLR
reset => frm_length[11]~reg0.ACLR
reset => frm_length[12]~reg0.ACLR
reset => frm_length[13]~reg0.ACLR
reset => frm_length[14]~reg0.ACLR
reset => frm_length[15]~reg0.ACLR
reset => total_lgth_val_d.ACLR
reset => frm_stack_vlan_int.ACLR
reset => frm_vlan_int.ACLR
reset => frm_mltcast_int.ACLR
reset => frm_unicast_int.ACLR
reset => frm_broadcast_int.ACLR
reset => dest_addr[0].ACLR
reset => dest_addr[1].ACLR
reset => dest_addr[2].ACLR
reset => dest_addr[3].ACLR
reset => dest_addr[4].ACLR
reset => dest_addr[5].ACLR
reset => dest_addr[6].ACLR
reset => dest_addr[7].ACLR
reset => dest_addr[8].ACLR
reset => dest_addr[9].ACLR
reset => dest_addr[10].ACLR
reset => dest_addr[11].ACLR
reset => dest_addr[12].ACLR
reset => dest_addr[13].ACLR
reset => dest_addr[14].ACLR
reset => dest_addr[15].ACLR
reset => dest_addr[16].ACLR
reset => dest_addr[17].ACLR
reset => dest_addr[18].ACLR
reset => dest_addr[19].ACLR
reset => dest_addr[20].ACLR
reset => dest_addr[21].ACLR
reset => dest_addr[22].ACLR
reset => dest_addr[23].ACLR
reset => dest_addr[24].ACLR
reset => dest_addr[25].ACLR
reset => dest_addr[26].ACLR
reset => dest_addr[27].ACLR
reset => dest_addr[28].ACLR
reset => dest_addr[29].ACLR
reset => dest_addr[30].ACLR
reset => dest_addr[31].ACLR
reset => dest_addr[32].ACLR
reset => dest_addr[33].ACLR
reset => dest_addr[34].ACLR
reset => dest_addr[35].ACLR
reset => dest_addr[36].ACLR
reset => dest_addr[37].ACLR
reset => dest_addr[38].ACLR
reset => dest_addr[39].ACLR
reset => dest_addr[40].ACLR
reset => dest_addr[41].ACLR
reset => dest_addr[42].ACLR
reset => dest_addr[43].ACLR
reset => dest_addr[44].ACLR
reset => dest_addr[45].ACLR
reset => dest_addr[46].ACLR
reset => dest_addr[47].ACLR
reset => frm_length_int[0].ACLR
reset => frm_length_int[1].ACLR
reset => frm_length_int[2].ACLR
reset => frm_length_int[3].ACLR
reset => frm_length_int[4].ACLR
reset => frm_length_int[5].ACLR
reset => frm_length_int[6].ACLR
reset => frm_length_int[7].ACLR
reset => frm_length_int[8].ACLR
reset => frm_length_int[9].ACLR
reset => frm_length_int[10].ACLR
reset => frm_length_int[11].ACLR
reset => frm_length_int[12].ACLR
reset => frm_length_int[13].ACLR
reset => frm_length_int[14].ACLR
reset => frm_length_int[15].ACLR
reset => sop_reg[0].ACLR
reset => sop_reg[1].ACLR
reset => sop_reg[2].ACLR
reset => sop_reg[3].ACLR
reset => sop_reg[4].ACLR
reset => sop_reg[5].ACLR
reset => sop_reg[6].ACLR
reset => sop_reg[7].ACLR
reset => total_lgth_val~reg0.ACLR
reset => total_frm_cnt[0].ACLR
reset => total_frm_cnt[1].ACLR
reset => total_frm_cnt[2].ACLR
reset => total_frm_cnt[3].ACLR
reset => total_frm_cnt[4].ACLR
reset => total_frm_cnt[5].ACLR
reset => total_frm_cnt[6].ACLR
reset => total_frm_cnt[7].ACLR
reset => total_frm_cnt[8].ACLR
reset => total_frm_cnt[9].ACLR
reset => total_frm_cnt[10].ACLR
reset => total_frm_cnt[11].ACLR
reset => total_frm_cnt[12].ACLR
reset => total_frm_cnt[13].ACLR
reset => total_frm_cnt[14].ACLR
reset => total_frm_cnt[15].ACLR
reset => state~7.DATAIN
reset => _.IN1
rx_clk => rx_clk.IN1
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => state.OUTPUTSELECT
clk_ena => total_lgth_val.DATAB
clk_ena => total_lgth_val_d.OUTPUTSELECT
clk_ena => frm_stat_val.IN1
clk_ena => frm_err.IN1
clk_ena => frm_crc_err.IN1
clk_ena => total_frm_cnt[15].ENA
clk_ena => total_frm_cnt[14].ENA
clk_ena => total_frm_cnt[13].ENA
clk_ena => total_frm_cnt[12].ENA
clk_ena => total_frm_cnt[11].ENA
clk_ena => total_frm_cnt[10].ENA
clk_ena => total_frm_cnt[9].ENA
clk_ena => total_frm_cnt[8].ENA
clk_ena => total_frm_cnt[7].ENA
clk_ena => total_frm_cnt[6].ENA
clk_ena => total_frm_cnt[5].ENA
clk_ena => total_frm_cnt[4].ENA
clk_ena => total_frm_cnt[3].ENA
clk_ena => total_frm_cnt[2].ENA
clk_ena => total_frm_cnt[1].ENA
clk_ena => total_frm_cnt[0].ENA
clk_ena => sop_reg[7].ENA
clk_ena => sop_reg[6].ENA
clk_ena => sop_reg[5].ENA
clk_ena => sop_reg[4].ENA
clk_ena => sop_reg[3].ENA
clk_ena => sop_reg[2].ENA
clk_ena => sop_reg[1].ENA
clk_ena => sop_reg[0].ENA
clk_ena => dest_addr[47].ENA
clk_ena => dest_addr[46].ENA
clk_ena => dest_addr[45].ENA
clk_ena => dest_addr[44].ENA
clk_ena => dest_addr[43].ENA
clk_ena => dest_addr[42].ENA
clk_ena => dest_addr[41].ENA
clk_ena => dest_addr[40].ENA
clk_ena => dest_addr[39].ENA
clk_ena => dest_addr[38].ENA
clk_ena => dest_addr[37].ENA
clk_ena => dest_addr[36].ENA
clk_ena => dest_addr[35].ENA
clk_ena => dest_addr[34].ENA
clk_ena => dest_addr[33].ENA
clk_ena => dest_addr[32].ENA
clk_ena => dest_addr[31].ENA
clk_ena => dest_addr[30].ENA
clk_ena => dest_addr[29].ENA
clk_ena => dest_addr[28].ENA
clk_ena => dest_addr[27].ENA
clk_ena => dest_addr[26].ENA
clk_ena => dest_addr[25].ENA
clk_ena => dest_addr[24].ENA
clk_ena => dest_addr[23].ENA
clk_ena => dest_addr[22].ENA
clk_ena => dest_addr[21].ENA
clk_ena => dest_addr[20].ENA
clk_ena => dest_addr[19].ENA
clk_ena => dest_addr[18].ENA
clk_ena => dest_addr[17].ENA
clk_ena => dest_addr[16].ENA
clk_ena => dest_addr[15].ENA
clk_ena => dest_addr[14].ENA
clk_ena => dest_addr[13].ENA
clk_ena => dest_addr[12].ENA
clk_ena => dest_addr[11].ENA
clk_ena => dest_addr[10].ENA
clk_ena => dest_addr[9].ENA
clk_ena => dest_addr[8].ENA
clk_ena => dest_addr[7].ENA
clk_ena => dest_addr[6].ENA
clk_ena => dest_addr[5].ENA
clk_ena => dest_addr[4].ENA
clk_ena => dest_addr[3].ENA
clk_ena => dest_addr[2].ENA
clk_ena => dest_addr[1].ENA
clk_ena => dest_addr[0].ENA
clk_ena => frm_length[15]~reg0.ENA
clk_ena => frm_length[14]~reg0.ENA
clk_ena => frm_length[13]~reg0.ENA
clk_ena => frm_length[12]~reg0.ENA
clk_ena => frm_length[11]~reg0.ENA
clk_ena => frm_length[10]~reg0.ENA
clk_ena => frm_length[9]~reg0.ENA
clk_ena => frm_length[8]~reg0.ENA
clk_ena => frm_length[7]~reg0.ENA
clk_ena => frm_length[6]~reg0.ENA
clk_ena => frm_length[5]~reg0.ENA
clk_ena => frm_length[4]~reg0.ENA
clk_ena => frm_length[3]~reg0.ENA
clk_ena => frm_length[2]~reg0.ENA
clk_ena => frm_length[1]~reg0.ENA
clk_ena => frm_length[0]~reg0.ENA
clk_ena => frm_vlan~reg0.ENA
clk_ena => frm_stack_vlan~reg0.ENA
clk_ena => frm_unicast~reg0.ENA
clk_ena => frm_broadcast~reg0.ENA
clk_ena => frm_crc_err_r.ENA
clk_ena => frm_mltcast~reg0.ENA
clk_ena => frm_stat_val_r.ENA
clk_ena => frm_err_r.ENA
enable_rx => enable_rx.IN1
gmii_en => always1.IN1
gmii_en => sop_reg.IN1
gmii_en => always5.IN1
gmii_en => Selector1.IN3
gmii_en => always1.IN1
gmii_en => nextstate.stm_typ_end_frm.DATAB
gmii_data[0] => dest_addr.DATAB
gmii_data[0] => dest_addr.DATAB
gmii_data[0] => dest_addr.DATAB
gmii_data[0] => dest_addr.DATAB
gmii_data[0] => dest_addr.DATAB
gmii_data[0] => dest_addr.DATAB
gmii_data[0] => Equal0.IN4
gmii_data[1] => dest_addr.DATAB
gmii_data[1] => dest_addr.DATAB
gmii_data[1] => dest_addr.DATAB
gmii_data[1] => dest_addr.DATAB
gmii_data[1] => dest_addr.DATAB
gmii_data[1] => dest_addr.DATAB
gmii_data[1] => Equal0.IN7
gmii_data[2] => dest_addr.DATAB
gmii_data[2] => dest_addr.DATAB
gmii_data[2] => dest_addr.DATAB
gmii_data[2] => dest_addr.DATAB
gmii_data[2] => dest_addr.DATAB
gmii_data[2] => dest_addr.DATAB
gmii_data[2] => Equal0.IN3
gmii_data[3] => dest_addr.DATAB
gmii_data[3] => dest_addr.DATAB
gmii_data[3] => dest_addr.DATAB
gmii_data[3] => dest_addr.DATAB
gmii_data[3] => dest_addr.DATAB
gmii_data[3] => dest_addr.DATAB
gmii_data[3] => Equal0.IN6
gmii_data[4] => dest_addr.DATAB
gmii_data[4] => dest_addr.DATAB
gmii_data[4] => dest_addr.DATAB
gmii_data[4] => dest_addr.DATAB
gmii_data[4] => dest_addr.DATAB
gmii_data[4] => dest_addr.DATAB
gmii_data[4] => Equal0.IN2
gmii_data[5] => dest_addr.DATAB
gmii_data[5] => dest_addr.DATAB
gmii_data[5] => dest_addr.DATAB
gmii_data[5] => dest_addr.DATAB
gmii_data[5] => dest_addr.DATAB
gmii_data[5] => dest_addr.DATAB
gmii_data[5] => Equal0.IN5
gmii_data[6] => dest_addr.DATAB
gmii_data[6] => dest_addr.DATAB
gmii_data[6] => dest_addr.DATAB
gmii_data[6] => dest_addr.DATAB
gmii_data[6] => dest_addr.DATAB
gmii_data[6] => dest_addr.DATAB
gmii_data[6] => Equal0.IN1
gmii_data[7] => dest_addr.DATAB
gmii_data[7] => dest_addr.DATAB
gmii_data[7] => dest_addr.DATAB
gmii_data[7] => dest_addr.DATAB
gmii_data[7] => dest_addr.DATAB
gmii_data[7] => dest_addr.DATAB
gmii_data[7] => Equal0.IN0
data_err => frm_err_r.DATAB
data_crc_err => frm_crc_err_r.DATAB
pause_rcv => always11.IN0
cmd_rcv => always11.IN1
data_err_ena => frm_err_r.OUTPUTSELECT
data_err_ena => frm_crc_err_r.OUTPUTSELECT
data_err_ena => frm_stat_val_r.DATAIN
total_lgth[0] <= total_frm_cnt[0].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[1] <= total_frm_cnt[1].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[2] <= total_frm_cnt[2].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[3] <= total_frm_cnt[3].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[4] <= total_frm_cnt[4].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[5] <= total_frm_cnt[5].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[6] <= total_frm_cnt[6].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[7] <= total_frm_cnt[7].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[8] <= total_frm_cnt[8].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[9] <= total_frm_cnt[9].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[10] <= total_frm_cnt[10].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[11] <= total_frm_cnt[11].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[12] <= total_frm_cnt[12].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[13] <= total_frm_cnt[13].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[14] <= total_frm_cnt[14].DB_MAX_OUTPUT_PORT_TYPE
total_lgth[15] <= total_frm_cnt[15].DB_MAX_OUTPUT_PORT_TYPE
total_lgth_val <= total_lgth_val~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_stat_val <= frm_stat_val.DB_MAX_OUTPUT_PORT_TYPE
frm_err <= frm_err.DB_MAX_OUTPUT_PORT_TYPE
frm_crc_err <= frm_crc_err.DB_MAX_OUTPUT_PORT_TYPE
frm_length[0] <= frm_length[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[1] <= frm_length[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[2] <= frm_length[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[3] <= frm_length[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[4] <= frm_length[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[5] <= frm_length[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[6] <= frm_length[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[7] <= frm_length[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[8] <= frm_length[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[9] <= frm_length[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[10] <= frm_length[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[11] <= frm_length[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[12] <= frm_length[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[13] <= frm_length[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[14] <= frm_length[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[15] <= frm_length[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_vlan <= frm_vlan~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_stack_vlan <= frm_stack_vlan~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_unicast <= frm_unicast~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_broadcast <= frm_broadcast~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_mltcast <= frm_mltcast~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_rx_stat_extract:U_RXSTAT|altera_std_synchronizer:U_SYNC_1
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX
rx_col => ~NO_FANOUT~
smac_0[0] => ~NO_FANOUT~
smac_0[1] => ~NO_FANOUT~
smac_0[2] => ~NO_FANOUT~
smac_0[3] => ~NO_FANOUT~
smac_0[4] => ~NO_FANOUT~
smac_0[5] => ~NO_FANOUT~
smac_0[6] => ~NO_FANOUT~
smac_0[7] => ~NO_FANOUT~
smac_0[8] => ~NO_FANOUT~
smac_0[9] => ~NO_FANOUT~
smac_0[10] => ~NO_FANOUT~
smac_0[11] => ~NO_FANOUT~
smac_0[12] => ~NO_FANOUT~
smac_0[13] => ~NO_FANOUT~
smac_0[14] => ~NO_FANOUT~
smac_0[15] => ~NO_FANOUT~
smac_0[16] => ~NO_FANOUT~
smac_0[17] => ~NO_FANOUT~
smac_0[18] => ~NO_FANOUT~
smac_0[19] => ~NO_FANOUT~
smac_0[20] => ~NO_FANOUT~
smac_0[21] => ~NO_FANOUT~
smac_0[22] => ~NO_FANOUT~
smac_0[23] => ~NO_FANOUT~
smac_0[24] => ~NO_FANOUT~
smac_0[25] => ~NO_FANOUT~
smac_0[26] => ~NO_FANOUT~
smac_0[27] => ~NO_FANOUT~
smac_0[28] => ~NO_FANOUT~
smac_0[29] => ~NO_FANOUT~
smac_0[30] => ~NO_FANOUT~
smac_0[31] => ~NO_FANOUT~
smac_0[32] => ~NO_FANOUT~
smac_0[33] => ~NO_FANOUT~
smac_0[34] => ~NO_FANOUT~
smac_0[35] => ~NO_FANOUT~
smac_0[36] => ~NO_FANOUT~
smac_0[37] => ~NO_FANOUT~
smac_0[38] => ~NO_FANOUT~
smac_0[39] => ~NO_FANOUT~
smac_0[40] => ~NO_FANOUT~
smac_0[41] => ~NO_FANOUT~
smac_0[42] => ~NO_FANOUT~
smac_0[43] => ~NO_FANOUT~
smac_0[44] => ~NO_FANOUT~
smac_0[45] => ~NO_FANOUT~
smac_0[46] => ~NO_FANOUT~
smac_0[47] => ~NO_FANOUT~
smac_1[0] => ~NO_FANOUT~
smac_1[1] => ~NO_FANOUT~
smac_1[2] => ~NO_FANOUT~
smac_1[3] => ~NO_FANOUT~
smac_1[4] => ~NO_FANOUT~
smac_1[5] => ~NO_FANOUT~
smac_1[6] => ~NO_FANOUT~
smac_1[7] => ~NO_FANOUT~
smac_1[8] => ~NO_FANOUT~
smac_1[9] => ~NO_FANOUT~
smac_1[10] => ~NO_FANOUT~
smac_1[11] => ~NO_FANOUT~
smac_1[12] => ~NO_FANOUT~
smac_1[13] => ~NO_FANOUT~
smac_1[14] => ~NO_FANOUT~
smac_1[15] => ~NO_FANOUT~
smac_1[16] => ~NO_FANOUT~
smac_1[17] => ~NO_FANOUT~
smac_1[18] => ~NO_FANOUT~
smac_1[19] => ~NO_FANOUT~
smac_1[20] => ~NO_FANOUT~
smac_1[21] => ~NO_FANOUT~
smac_1[22] => ~NO_FANOUT~
smac_1[23] => ~NO_FANOUT~
smac_1[24] => ~NO_FANOUT~
smac_1[25] => ~NO_FANOUT~
smac_1[26] => ~NO_FANOUT~
smac_1[27] => ~NO_FANOUT~
smac_1[28] => ~NO_FANOUT~
smac_1[29] => ~NO_FANOUT~
smac_1[30] => ~NO_FANOUT~
smac_1[31] => ~NO_FANOUT~
smac_1[32] => ~NO_FANOUT~
smac_1[33] => ~NO_FANOUT~
smac_1[34] => ~NO_FANOUT~
smac_1[35] => ~NO_FANOUT~
smac_1[36] => ~NO_FANOUT~
smac_1[37] => ~NO_FANOUT~
smac_1[38] => ~NO_FANOUT~
smac_1[39] => ~NO_FANOUT~
smac_1[40] => ~NO_FANOUT~
smac_1[41] => ~NO_FANOUT~
smac_1[42] => ~NO_FANOUT~
smac_1[43] => ~NO_FANOUT~
smac_1[44] => ~NO_FANOUT~
smac_1[45] => ~NO_FANOUT~
smac_1[46] => ~NO_FANOUT~
smac_1[47] => ~NO_FANOUT~
smac_2[0] => ~NO_FANOUT~
smac_2[1] => ~NO_FANOUT~
smac_2[2] => ~NO_FANOUT~
smac_2[3] => ~NO_FANOUT~
smac_2[4] => ~NO_FANOUT~
smac_2[5] => ~NO_FANOUT~
smac_2[6] => ~NO_FANOUT~
smac_2[7] => ~NO_FANOUT~
smac_2[8] => ~NO_FANOUT~
smac_2[9] => ~NO_FANOUT~
smac_2[10] => ~NO_FANOUT~
smac_2[11] => ~NO_FANOUT~
smac_2[12] => ~NO_FANOUT~
smac_2[13] => ~NO_FANOUT~
smac_2[14] => ~NO_FANOUT~
smac_2[15] => ~NO_FANOUT~
smac_2[16] => ~NO_FANOUT~
smac_2[17] => ~NO_FANOUT~
smac_2[18] => ~NO_FANOUT~
smac_2[19] => ~NO_FANOUT~
smac_2[20] => ~NO_FANOUT~
smac_2[21] => ~NO_FANOUT~
smac_2[22] => ~NO_FANOUT~
smac_2[23] => ~NO_FANOUT~
smac_2[24] => ~NO_FANOUT~
smac_2[25] => ~NO_FANOUT~
smac_2[26] => ~NO_FANOUT~
smac_2[27] => ~NO_FANOUT~
smac_2[28] => ~NO_FANOUT~
smac_2[29] => ~NO_FANOUT~
smac_2[30] => ~NO_FANOUT~
smac_2[31] => ~NO_FANOUT~
smac_2[32] => ~NO_FANOUT~
smac_2[33] => ~NO_FANOUT~
smac_2[34] => ~NO_FANOUT~
smac_2[35] => ~NO_FANOUT~
smac_2[36] => ~NO_FANOUT~
smac_2[37] => ~NO_FANOUT~
smac_2[38] => ~NO_FANOUT~
smac_2[39] => ~NO_FANOUT~
smac_2[40] => ~NO_FANOUT~
smac_2[41] => ~NO_FANOUT~
smac_2[42] => ~NO_FANOUT~
smac_2[43] => ~NO_FANOUT~
smac_2[44] => ~NO_FANOUT~
smac_2[45] => ~NO_FANOUT~
smac_2[46] => ~NO_FANOUT~
smac_2[47] => ~NO_FANOUT~
smac_3[0] => ~NO_FANOUT~
smac_3[1] => ~NO_FANOUT~
smac_3[2] => ~NO_FANOUT~
smac_3[3] => ~NO_FANOUT~
smac_3[4] => ~NO_FANOUT~
smac_3[5] => ~NO_FANOUT~
smac_3[6] => ~NO_FANOUT~
smac_3[7] => ~NO_FANOUT~
smac_3[8] => ~NO_FANOUT~
smac_3[9] => ~NO_FANOUT~
smac_3[10] => ~NO_FANOUT~
smac_3[11] => ~NO_FANOUT~
smac_3[12] => ~NO_FANOUT~
smac_3[13] => ~NO_FANOUT~
smac_3[14] => ~NO_FANOUT~
smac_3[15] => ~NO_FANOUT~
smac_3[16] => ~NO_FANOUT~
smac_3[17] => ~NO_FANOUT~
smac_3[18] => ~NO_FANOUT~
smac_3[19] => ~NO_FANOUT~
smac_3[20] => ~NO_FANOUT~
smac_3[21] => ~NO_FANOUT~
smac_3[22] => ~NO_FANOUT~
smac_3[23] => ~NO_FANOUT~
smac_3[24] => ~NO_FANOUT~
smac_3[25] => ~NO_FANOUT~
smac_3[26] => ~NO_FANOUT~
smac_3[27] => ~NO_FANOUT~
smac_3[28] => ~NO_FANOUT~
smac_3[29] => ~NO_FANOUT~
smac_3[30] => ~NO_FANOUT~
smac_3[31] => ~NO_FANOUT~
smac_3[32] => ~NO_FANOUT~
smac_3[33] => ~NO_FANOUT~
smac_3[34] => ~NO_FANOUT~
smac_3[35] => ~NO_FANOUT~
smac_3[36] => ~NO_FANOUT~
smac_3[37] => ~NO_FANOUT~
smac_3[38] => ~NO_FANOUT~
smac_3[39] => ~NO_FANOUT~
smac_3[40] => ~NO_FANOUT~
smac_3[41] => ~NO_FANOUT~
smac_3[42] => ~NO_FANOUT~
smac_3[43] => ~NO_FANOUT~
smac_3[44] => ~NO_FANOUT~
smac_3[45] => ~NO_FANOUT~
smac_3[46] => ~NO_FANOUT~
smac_3[47] => ~NO_FANOUT~
reset_rx_clk => reset_rx_clk.IN1
reset_tx_clk => pause_quant_val[0]~reg0.ACLR
reset_tx_clk => pause_quant_val[1]~reg0.ACLR
reset_tx_clk => pause_quant_val[2]~reg0.ACLR
reset_tx_clk => pause_quant_val[3]~reg0.ACLR
reset_tx_clk => pause_quant_val[4]~reg0.ACLR
reset_tx_clk => pause_quant_val[5]~reg0.ACLR
reset_tx_clk => pause_quant_val[6]~reg0.ACLR
reset_tx_clk => pause_quant_val[7]~reg0.ACLR
reset_tx_clk => pause_quant_val[8]~reg0.ACLR
reset_tx_clk => pause_quant_val[9]~reg0.ACLR
reset_tx_clk => pause_quant_val[10]~reg0.ACLR
reset_tx_clk => pause_quant_val[11]~reg0.ACLR
reset_tx_clk => pause_quant_val[12]~reg0.ACLR
reset_tx_clk => pause_quant_val[13]~reg0.ACLR
reset_tx_clk => pause_quant_val[14]~reg0.ACLR
reset_tx_clk => pause_quant_val[15]~reg0.ACLR
sw_reset => sw_reset.IN1
ethernet_mode => ethernet_mode.IN1
rx_clk => rx_clk.IN12
rxclk_ena => rxclk_ena.IN2
tx_clk => pause_quant_val[0]~reg0.CLK
tx_clk => pause_quant_val[1]~reg0.CLK
tx_clk => pause_quant_val[2]~reg0.CLK
tx_clk => pause_quant_val[3]~reg0.CLK
tx_clk => pause_quant_val[4]~reg0.CLK
tx_clk => pause_quant_val[5]~reg0.CLK
tx_clk => pause_quant_val[6]~reg0.CLK
tx_clk => pause_quant_val[7]~reg0.CLK
tx_clk => pause_quant_val[8]~reg0.CLK
tx_clk => pause_quant_val[9]~reg0.CLK
tx_clk => pause_quant_val[10]~reg0.CLK
tx_clk => pause_quant_val[11]~reg0.CLK
tx_clk => pause_quant_val[12]~reg0.CLK
tx_clk => pause_quant_val[13]~reg0.CLK
tx_clk => pause_quant_val[14]~reg0.CLK
tx_clk => pause_quant_val[15]~reg0.CLK
half_duplex_ena => ~NO_FANOUT~
no_lgth_check => no_lgth_check.IN1
mii_align_err => always5.IN0
rx_d[0] => rxd_0[0].DATAIN
rx_d[1] => rxd_0[1].DATAIN
rx_d[2] => rxd_0[2].DATAIN
rx_d[3] => rxd_0[3].DATAIN
rx_d[4] => rxd_0[4].DATAIN
rx_d[5] => rxd_0[5].DATAIN
rx_d[6] => rxd_0[6].DATAIN
rx_d[7] => rxd_0[7].DATAIN
rx_en => rx_err_s.IN0
rx_en => always20.IN1
rx_en => rx_en_reg.DATAIN
rx_en => always20.IN1
rx_en => enable_rx_reg3.ENA
rx_en => rx_en_s[0].DATAIN
rx_err => rx_err_s.IN1
mac_addr[0] => Equal1.IN15
mac_addr[1] => Equal1.IN14
mac_addr[2] => Equal1.IN13
mac_addr[3] => Equal1.IN12
mac_addr[4] => Equal1.IN11
mac_addr[5] => Equal1.IN10
mac_addr[6] => Equal1.IN9
mac_addr[7] => Equal1.IN8
mac_addr[8] => Equal2.IN15
mac_addr[9] => Equal2.IN14
mac_addr[10] => Equal2.IN13
mac_addr[11] => Equal2.IN12
mac_addr[12] => Equal2.IN11
mac_addr[13] => Equal2.IN10
mac_addr[14] => Equal2.IN9
mac_addr[15] => Equal2.IN8
mac_addr[16] => Equal3.IN15
mac_addr[17] => Equal3.IN14
mac_addr[18] => Equal3.IN13
mac_addr[19] => Equal3.IN12
mac_addr[20] => Equal3.IN11
mac_addr[21] => Equal3.IN10
mac_addr[22] => Equal3.IN9
mac_addr[23] => Equal3.IN8
mac_addr[24] => Equal4.IN15
mac_addr[25] => Equal4.IN14
mac_addr[26] => Equal4.IN13
mac_addr[27] => Equal4.IN12
mac_addr[28] => Equal4.IN11
mac_addr[29] => Equal4.IN10
mac_addr[30] => Equal4.IN9
mac_addr[31] => Equal4.IN8
mac_addr[32] => Equal5.IN15
mac_addr[33] => Equal5.IN14
mac_addr[34] => Equal5.IN13
mac_addr[35] => Equal5.IN12
mac_addr[36] => Equal5.IN11
mac_addr[37] => Equal5.IN10
mac_addr[38] => Equal5.IN9
mac_addr[39] => Equal5.IN8
mac_addr[40] => Equal6.IN15
mac_addr[41] => Equal6.IN14
mac_addr[42] => Equal6.IN13
mac_addr[43] => Equal6.IN12
mac_addr[44] => Equal6.IN11
mac_addr[45] => Equal6.IN10
mac_addr[46] => Equal6.IN9
mac_addr[47] => Equal6.IN8
promis_en => promis_en.IN1
frm_length_max[0] => Equal12.IN3
frm_length_max[1] => Equal12.IN2
frm_length_max[2] => Equal12.IN1
frm_length_max[3] => Equal12.IN0
frm_length_max[4] => Equal13.IN3
frm_length_max[5] => Equal13.IN2
frm_length_max[6] => Equal13.IN1
frm_length_max[7] => Equal13.IN0
frm_length_max[8] => Equal14.IN3
frm_length_max[9] => Equal14.IN2
frm_length_max[10] => Equal14.IN1
frm_length_max[11] => Equal14.IN0
frm_length_max[12] => Equal15.IN3
frm_length_max[13] => Equal15.IN2
frm_length_max[14] => Equal15.IN1
frm_length_max[15] => Equal15.IN0
crc_fwd => crc_fwd.IN1
pause_fwd => pause_fwd.IN1
pause_ignore => pause_ignore.IN1
pad_ena => pad_ena.IN1
enable_rx => enable_rx.IN1
mhash_sel => ~NO_FANOUT~
cmd_frm_ena => cmd_frm_ena.IN1
magic_ena => ~NO_FANOUT~
sleep_ena => ~NO_FANOUT~
magic_pkt_ena <= magic_pkt_ena~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_rcv <= <GND>
cmd_rcv <= cmd_rcv.DB_MAX_OUTPUT_PORT_TYPE
frm_align_err <= frm_align_err~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_crc_err <= frm_crc_err~reg0.DB_MAX_OUTPUT_PORT_TYPE
long_crc_err <= long_crc_err~reg0.DB_MAX_OUTPUT_PORT_TYPE
short_crc_err <= short_crc_err~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_discard <= frm_discard~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[0] <= pause_quant_val[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[1] <= pause_quant_val[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[2] <= pause_quant_val[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[3] <= pause_quant_val[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[4] <= pause_quant_val[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[5] <= pause_quant_val[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[6] <= pause_quant_val[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[7] <= pause_quant_val[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[8] <= pause_quant_val[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[9] <= pause_quant_val[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[10] <= pause_quant_val[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[11] <= pause_quant_val[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[12] <= pause_quant_val[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[13] <= pause_quant_val[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[14] <= pause_quant_val[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_val[15] <= pause_quant_val[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pause_quant_avb <= <GND>
reg_clk => ~NO_FANOUT~
hash_wren => ~NO_FANOUT~
hash_wdata => ~NO_FANOUT~
hash_waddr[0] => ~NO_FANOUT~
hash_waddr[1] => ~NO_FANOUT~
hash_waddr[2] => ~NO_FANOUT~
hash_waddr[3] => ~NO_FANOUT~
hash_waddr[4] => ~NO_FANOUT~
hash_waddr[5] => ~NO_FANOUT~
rx_stat_data[0] <= rx_stat_data_s[0].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[1] <= rx_stat_data_s[1].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[2] <= rx_stat_data_s[2].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[3] <= rx_stat_data_s[3].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[4] <= rx_stat_data_s[4].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[5] <= payload_length[0].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[6] <= payload_length[1].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[7] <= payload_length[2].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[8] <= payload_length[3].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[9] <= payload_length[4].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[10] <= payload_length[5].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[11] <= payload_length[6].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[12] <= payload_length[7].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[13] <= payload_length[8].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[14] <= payload_length[9].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[15] <= payload_length[10].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[16] <= payload_length[11].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[17] <= payload_length[12].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[18] <= payload_length[13].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[19] <= payload_length[14].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[20] <= payload_length[15].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[21] <= rx_stat_data_s[5].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_data[22] <= rx_stat_data_s[6].DB_MAX_OUTPUT_PORT_TYPE
rx_stat_wren <= rx_stat_wren~reg0.DB_MAX_OUTPUT_PORT_TYPE
stat_err_ena <= stat_err_ena~reg0.DB_MAX_OUTPUT_PORT_TYPE
stat_en <= stat_en~reg0.DB_MAX_OUTPUT_PORT_TYPE
stat_err <= stat_err~reg0.DB_MAX_OUTPUT_PORT_TYPE
stat_crc_err <= stat_crc_err~reg0.DB_MAX_OUTPUT_PORT_TYPE
stat_data[0] <= stat_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stat_data[1] <= stat_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stat_data[2] <= stat_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stat_data[3] <= stat_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stat_data[4] <= stat_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stat_data[5] <= stat_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stat_data[6] <= stat_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
stat_data[7] <= stat_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data_int[0] <= rx_data_int[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data_int[1] <= rx_data_int[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data_int[2] <= rx_data_int[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data_int[3] <= rx_data_int[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data_int[4] <= rx_data_int[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data_int[5] <= rx_data_int[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data_int[6] <= rx_data_int[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data_int[7] <= rx_data_int[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_a_full => ok_sfd_discard.IN1
rx_a_full => always16.IN1
rx_a_full => always16.IN1
rx_a_full => always16.IN1
rx_sop_int <= rx_sop_int~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_eop_int <= rx_eop_int~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_ucast <= rx_ucast~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_bcast <= rx_bcast~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_mcast <= rx_mcast~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_vlan <= rx_vlan~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data_val <= rx_data_val~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_wren_int <= rx_wren_int~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_frm_stat_ena <= rx_frm_stat_ena~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_std_synchronizer:U_SYNC_4
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_std_synchronizer:U_SYNC_5
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_std_synchronizer:U_SYNC_6
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_std_synchronizer:U_SYNC_7
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_std_synchronizer:U_SYNC_8
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_std_synchronizer:U_SYNC_9
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_std_synchronizer:U_SYNC_10
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_std_synchronizer:U_SYNC_11
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_std_synchronizer:U_SYNC_12
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_std_synchronizer:U_SYNC_PAD_ENA
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC
clk => clk.IN1
clk_ena => clk_ena.IN1
rst => rst.IN1
sof => sof.IN1
data[0] => data_i.DATAB
data[1] => data_i.DATAB
data[2] => data_i.DATAB
data[3] => data_i.DATAB
data[4] => data_i.DATAB
data[5] => data_i.DATAB
data[6] => data_i.DATAB
data[7] => data_i.DATAB
eof => eof_dly[0].DATAIN
check_vld <= eof_dly[2].DB_MAX_OUTPUT_PORT_TYPE
crc_ok <= crc_ok~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_crc328checker:U_CRC|altera_tse_crc32galois8:U_GALS
clk => reg_out[0].CLK
clk => reg_out[1].CLK
clk => reg_out[2].CLK
clk => reg_out[3].CLK
clk => reg_out[4].CLK
clk => reg_out[5].CLK
clk => reg_out[6].CLK
clk => reg_out[7].CLK
clk => reg_out[8].CLK
clk => reg_out[9].CLK
clk => reg_out[10].CLK
clk => reg_out[11].CLK
clk => reg_out[12].CLK
clk => reg_out[13].CLK
clk => reg_out[14].CLK
clk => reg_out[15].CLK
clk => reg_out[16].CLK
clk => reg_out[17].CLK
clk => reg_out[18].CLK
clk => reg_out[19].CLK
clk => reg_out[20].CLK
clk => reg_out[21].CLK
clk => reg_out[22].CLK
clk => reg_out[23].CLK
clk => reg_out[24].CLK
clk => reg_out[25].CLK
clk => reg_out[26].CLK
clk => reg_out[27].CLK
clk => reg_out[28].CLK
clk => reg_out[29].CLK
clk => reg_out[30].CLK
clk => reg_out[31].CLK
clk_ena => reg_out[0].ENA
clk_ena => reg_out[31].ENA
clk_ena => reg_out[30].ENA
clk_ena => reg_out[29].ENA
clk_ena => reg_out[28].ENA
clk_ena => reg_out[27].ENA
clk_ena => reg_out[26].ENA
clk_ena => reg_out[25].ENA
clk_ena => reg_out[24].ENA
clk_ena => reg_out[23].ENA
clk_ena => reg_out[22].ENA
clk_ena => reg_out[21].ENA
clk_ena => reg_out[20].ENA
clk_ena => reg_out[19].ENA
clk_ena => reg_out[18].ENA
clk_ena => reg_out[17].ENA
clk_ena => reg_out[16].ENA
clk_ena => reg_out[15].ENA
clk_ena => reg_out[14].ENA
clk_ena => reg_out[13].ENA
clk_ena => reg_out[12].ENA
clk_ena => reg_out[11].ENA
clk_ena => reg_out[10].ENA
clk_ena => reg_out[9].ENA
clk_ena => reg_out[8].ENA
clk_ena => reg_out[7].ENA
clk_ena => reg_out[6].ENA
clk_ena => reg_out[5].ENA
clk_ena => reg_out[4].ENA
clk_ena => reg_out[3].ENA
clk_ena => reg_out[2].ENA
clk_ena => reg_out[1].ENA
rst => reg_out[0].ACLR
rst => reg_out[1].ACLR
rst => reg_out[2].ACLR
rst => reg_out[3].ACLR
rst => reg_out[4].ACLR
rst => reg_out[5].ACLR
rst => reg_out[6].ACLR
rst => reg_out[7].ACLR
rst => reg_out[8].ACLR
rst => reg_out[9].ACLR
rst => reg_out[10].ACLR
rst => reg_out[11].ACLR
rst => reg_out[12].ACLR
rst => reg_out[13].ACLR
rst => reg_out[14].ACLR
rst => reg_out[15].ACLR
rst => reg_out[16].ACLR
rst => reg_out[17].ACLR
rst => reg_out[18].ACLR
rst => reg_out[19].ACLR
rst => reg_out[20].ACLR
rst => reg_out[21].ACLR
rst => reg_out[22].ACLR
rst => reg_out[23].ACLR
rst => reg_out[24].ACLR
rst => reg_out[25].ACLR
rst => reg_out[26].ACLR
rst => reg_out[27].ACLR
rst => reg_out[28].ACLR
rst => reg_out[29].ACLR
rst => reg_out[30].ACLR
rst => reg_out[31].ACLR
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
data[0] => o1[27].IN1
data[1] => o1[22].IN1
data[2] => o1[9].IN1
data[3] => o1[28].IN1
data[4] => o[28].IN1
data[5] => o1[29].IN1
data[6] => o[30].IN1
data[7] => o[31].IN1
outp[0] <= reg_out[31].DB_MAX_OUTPUT_PORT_TYPE
outp[1] <= reg_out[30].DB_MAX_OUTPUT_PORT_TYPE
outp[2] <= reg_out[29].DB_MAX_OUTPUT_PORT_TYPE
outp[3] <= reg_out[28].DB_MAX_OUTPUT_PORT_TYPE
outp[4] <= reg_out[27].DB_MAX_OUTPUT_PORT_TYPE
outp[5] <= reg_out[26].DB_MAX_OUTPUT_PORT_TYPE
outp[6] <= reg_out[25].DB_MAX_OUTPUT_PORT_TYPE
outp[7] <= reg_out[24].DB_MAX_OUTPUT_PORT_TYPE
outp[8] <= reg_out[23].DB_MAX_OUTPUT_PORT_TYPE
outp[9] <= reg_out[22].DB_MAX_OUTPUT_PORT_TYPE
outp[10] <= reg_out[21].DB_MAX_OUTPUT_PORT_TYPE
outp[11] <= reg_out[20].DB_MAX_OUTPUT_PORT_TYPE
outp[12] <= reg_out[19].DB_MAX_OUTPUT_PORT_TYPE
outp[13] <= reg_out[18].DB_MAX_OUTPUT_PORT_TYPE
outp[14] <= reg_out[17].DB_MAX_OUTPUT_PORT_TYPE
outp[15] <= reg_out[16].DB_MAX_OUTPUT_PORT_TYPE
outp[16] <= reg_out[15].DB_MAX_OUTPUT_PORT_TYPE
outp[17] <= reg_out[14].DB_MAX_OUTPUT_PORT_TYPE
outp[18] <= reg_out[13].DB_MAX_OUTPUT_PORT_TYPE
outp[19] <= reg_out[12].DB_MAX_OUTPUT_PORT_TYPE
outp[20] <= reg_out[11].DB_MAX_OUTPUT_PORT_TYPE
outp[21] <= reg_out[10].DB_MAX_OUTPUT_PORT_TYPE
outp[22] <= reg_out[9].DB_MAX_OUTPUT_PORT_TYPE
outp[23] <= reg_out[8].DB_MAX_OUTPUT_PORT_TYPE
outp[24] <= reg_out[7].DB_MAX_OUTPUT_PORT_TYPE
outp[25] <= reg_out[6].DB_MAX_OUTPUT_PORT_TYPE
outp[26] <= reg_out[5].DB_MAX_OUTPUT_PORT_TYPE
outp[27] <= reg_out[4].DB_MAX_OUTPUT_PORT_TYPE
outp[28] <= reg_out[3].DB_MAX_OUTPUT_PORT_TYPE
outp[29] <= reg_out[2].DB_MAX_OUTPUT_PORT_TYPE
outp[30] <= reg_out[1].DB_MAX_OUTPUT_PORT_TYPE
outp[31] <= reg_out[0].DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_rx:U_RX|altera_tse_altshifttaps:U_SHIFTTAPS
clken => shift_reg[4][0].ENA
clken => shift_reg[3][7].ENA
clken => shift_reg[3][6].ENA
clken => shift_reg[3][5].ENA
clken => shift_reg[3][4].ENA
clken => shift_reg[3][3].ENA
clken => shift_reg[3][2].ENA
clken => shift_reg[3][1].ENA
clken => shift_reg[3][0].ENA
clken => shift_reg[2][7].ENA
clken => shift_reg[2][6].ENA
clken => shift_reg[2][5].ENA
clken => shift_reg[2][4].ENA
clken => shift_reg[2][3].ENA
clken => shift_reg[2][2].ENA
clken => shift_reg[2][1].ENA
clken => shift_reg[2][0].ENA
clken => shift_reg[1][7].ENA
clken => shift_reg[1][6].ENA
clken => shift_reg[1][5].ENA
clken => shift_reg[1][4].ENA
clken => shift_reg[1][3].ENA
clken => shift_reg[1][2].ENA
clken => shift_reg[1][1].ENA
clken => shift_reg[1][0].ENA
clken => shift_reg[0][7].ENA
clken => shift_reg[0][6].ENA
clken => shift_reg[0][5].ENA
clken => shift_reg[0][4].ENA
clken => shift_reg[0][3].ENA
clken => shift_reg[0][2].ENA
clken => shift_reg[0][1].ENA
clken => shift_reg[0][0].ENA
clken => shift_reg[4][1].ENA
clken => shift_reg[4][2].ENA
clken => shift_reg[4][3].ENA
clken => shift_reg[4][4].ENA
clken => shift_reg[4][5].ENA
clken => shift_reg[4][6].ENA
clken => shift_reg[4][7].ENA
clken => shift_reg[5][0].ENA
clken => shift_reg[5][1].ENA
clken => shift_reg[5][2].ENA
clken => shift_reg[5][3].ENA
clken => shift_reg[5][4].ENA
clken => shift_reg[5][5].ENA
clken => shift_reg[5][6].ENA
clken => shift_reg[5][7].ENA
clken => shift_reg[6][0].ENA
clken => shift_reg[6][1].ENA
clken => shift_reg[6][2].ENA
clken => shift_reg[6][3].ENA
clken => shift_reg[6][4].ENA
clken => shift_reg[6][5].ENA
clken => shift_reg[6][6].ENA
clken => shift_reg[6][7].ENA
clken => shift_reg[7][0].ENA
clken => shift_reg[7][1].ENA
clken => shift_reg[7][2].ENA
clken => shift_reg[7][3].ENA
clken => shift_reg[7][4].ENA
clken => shift_reg[7][5].ENA
clken => shift_reg[7][6].ENA
clken => shift_reg[7][7].ENA
clken => shift_reg[8][0].ENA
clken => shift_reg[8][1].ENA
clken => shift_reg[8][2].ENA
clken => shift_reg[8][3].ENA
clken => shift_reg[8][4].ENA
clken => shift_reg[8][5].ENA
clken => shift_reg[8][6].ENA
clken => shift_reg[8][7].ENA
clken => shift_reg[9][0].ENA
clken => shift_reg[9][1].ENA
clken => shift_reg[9][2].ENA
clken => shift_reg[9][3].ENA
clken => shift_reg[9][4].ENA
clken => shift_reg[9][5].ENA
clken => shift_reg[9][6].ENA
clken => shift_reg[9][7].ENA
clken => shift_reg[10][0].ENA
clken => shift_reg[10][1].ENA
clken => shift_reg[10][2].ENA
clken => shift_reg[10][3].ENA
clken => shift_reg[10][4].ENA
clken => shift_reg[10][5].ENA
clken => shift_reg[10][6].ENA
clken => shift_reg[10][7].ENA
clken => shift_reg[11][0].ENA
clken => shift_reg[11][1].ENA
clken => shift_reg[11][2].ENA
clken => shift_reg[11][3].ENA
clken => shift_reg[11][4].ENA
clken => shift_reg[11][5].ENA
clken => shift_reg[11][6].ENA
clken => shift_reg[11][7].ENA
clken => shift_reg[12][0].ENA
clken => shift_reg[12][1].ENA
clken => shift_reg[12][2].ENA
clken => shift_reg[12][3].ENA
clken => shift_reg[12][4].ENA
clken => shift_reg[12][5].ENA
clken => shift_reg[12][6].ENA
clken => shift_reg[12][7].ENA
clken => shift_reg[13][0].ENA
clken => shift_reg[13][1].ENA
clken => shift_reg[13][2].ENA
clken => shift_reg[13][3].ENA
clken => shift_reg[13][4].ENA
clken => shift_reg[13][5].ENA
clken => shift_reg[13][6].ENA
clken => shift_reg[13][7].ENA
clken => shift_reg[14][0].ENA
clken => shift_reg[14][1].ENA
clken => shift_reg[14][2].ENA
clken => shift_reg[14][3].ENA
clken => shift_reg[14][4].ENA
clken => shift_reg[14][5].ENA
clken => shift_reg[14][6].ENA
clken => shift_reg[14][7].ENA
clken => shift_reg[15][0].ENA
clken => shift_reg[15][1].ENA
clken => shift_reg[15][2].ENA
clken => shift_reg[15][3].ENA
clken => shift_reg[15][4].ENA
clken => shift_reg[15][5].ENA
clken => shift_reg[15][6].ENA
clken => shift_reg[15][7].ENA
clock => shift_reg[0][0].CLK
clock => shift_reg[0][1].CLK
clock => shift_reg[0][2].CLK
clock => shift_reg[0][3].CLK
clock => shift_reg[0][4].CLK
clock => shift_reg[0][5].CLK
clock => shift_reg[0][6].CLK
clock => shift_reg[0][7].CLK
clock => shift_reg[1][0].CLK
clock => shift_reg[1][1].CLK
clock => shift_reg[1][2].CLK
clock => shift_reg[1][3].CLK
clock => shift_reg[1][4].CLK
clock => shift_reg[1][5].CLK
clock => shift_reg[1][6].CLK
clock => shift_reg[1][7].CLK
clock => shift_reg[2][0].CLK
clock => shift_reg[2][1].CLK
clock => shift_reg[2][2].CLK
clock => shift_reg[2][3].CLK
clock => shift_reg[2][4].CLK
clock => shift_reg[2][5].CLK
clock => shift_reg[2][6].CLK
clock => shift_reg[2][7].CLK
clock => shift_reg[3][0].CLK
clock => shift_reg[3][1].CLK
clock => shift_reg[3][2].CLK
clock => shift_reg[3][3].CLK
clock => shift_reg[3][4].CLK
clock => shift_reg[3][5].CLK
clock => shift_reg[3][6].CLK
clock => shift_reg[3][7].CLK
clock => shift_reg[4][0].CLK
clock => shift_reg[4][1].CLK
clock => shift_reg[4][2].CLK
clock => shift_reg[4][3].CLK
clock => shift_reg[4][4].CLK
clock => shift_reg[4][5].CLK
clock => shift_reg[4][6].CLK
clock => shift_reg[4][7].CLK
clock => shift_reg[5][0].CLK
clock => shift_reg[5][1].CLK
clock => shift_reg[5][2].CLK
clock => shift_reg[5][3].CLK
clock => shift_reg[5][4].CLK
clock => shift_reg[5][5].CLK
clock => shift_reg[5][6].CLK
clock => shift_reg[5][7].CLK
clock => shift_reg[6][0].CLK
clock => shift_reg[6][1].CLK
clock => shift_reg[6][2].CLK
clock => shift_reg[6][3].CLK
clock => shift_reg[6][4].CLK
clock => shift_reg[6][5].CLK
clock => shift_reg[6][6].CLK
clock => shift_reg[6][7].CLK
clock => shift_reg[7][0].CLK
clock => shift_reg[7][1].CLK
clock => shift_reg[7][2].CLK
clock => shift_reg[7][3].CLK
clock => shift_reg[7][4].CLK
clock => shift_reg[7][5].CLK
clock => shift_reg[7][6].CLK
clock => shift_reg[7][7].CLK
clock => shift_reg[8][0].CLK
clock => shift_reg[8][1].CLK
clock => shift_reg[8][2].CLK
clock => shift_reg[8][3].CLK
clock => shift_reg[8][4].CLK
clock => shift_reg[8][5].CLK
clock => shift_reg[8][6].CLK
clock => shift_reg[8][7].CLK
clock => shift_reg[9][0].CLK
clock => shift_reg[9][1].CLK
clock => shift_reg[9][2].CLK
clock => shift_reg[9][3].CLK
clock => shift_reg[9][4].CLK
clock => shift_reg[9][5].CLK
clock => shift_reg[9][6].CLK
clock => shift_reg[9][7].CLK
clock => shift_reg[10][0].CLK
clock => shift_reg[10][1].CLK
clock => shift_reg[10][2].CLK
clock => shift_reg[10][3].CLK
clock => shift_reg[10][4].CLK
clock => shift_reg[10][5].CLK
clock => shift_reg[10][6].CLK
clock => shift_reg[10][7].CLK
clock => shift_reg[11][0].CLK
clock => shift_reg[11][1].CLK
clock => shift_reg[11][2].CLK
clock => shift_reg[11][3].CLK
clock => shift_reg[11][4].CLK
clock => shift_reg[11][5].CLK
clock => shift_reg[11][6].CLK
clock => shift_reg[11][7].CLK
clock => shift_reg[12][0].CLK
clock => shift_reg[12][1].CLK
clock => shift_reg[12][2].CLK
clock => shift_reg[12][3].CLK
clock => shift_reg[12][4].CLK
clock => shift_reg[12][5].CLK
clock => shift_reg[12][6].CLK
clock => shift_reg[12][7].CLK
clock => shift_reg[13][0].CLK
clock => shift_reg[13][1].CLK
clock => shift_reg[13][2].CLK
clock => shift_reg[13][3].CLK
clock => shift_reg[13][4].CLK
clock => shift_reg[13][5].CLK
clock => shift_reg[13][6].CLK
clock => shift_reg[13][7].CLK
clock => shift_reg[14][0].CLK
clock => shift_reg[14][1].CLK
clock => shift_reg[14][2].CLK
clock => shift_reg[14][3].CLK
clock => shift_reg[14][4].CLK
clock => shift_reg[14][5].CLK
clock => shift_reg[14][6].CLK
clock => shift_reg[14][7].CLK
clock => shift_reg[15][0].CLK
clock => shift_reg[15][1].CLK
clock => shift_reg[15][2].CLK
clock => shift_reg[15][3].CLK
clock => shift_reg[15][4].CLK
clock => shift_reg[15][5].CLK
clock => shift_reg[15][6].CLK
clock => shift_reg[15][7].CLK
shiftin[0] => shift_reg[0][0].DATAIN
shiftin[1] => shift_reg[0][1].DATAIN
shiftin[2] => shift_reg[0][2].DATAIN
shiftin[3] => shift_reg[0][3].DATAIN
shiftin[4] => shift_reg[0][4].DATAIN
shiftin[5] => shift_reg[0][5].DATAIN
shiftin[6] => shift_reg[0][6].DATAIN
shiftin[7] => shift_reg[0][7].DATAIN
taps[0] <= shift_reg[15][0].DB_MAX_OUTPUT_PORT_TYPE
taps[1] <= shift_reg[15][1].DB_MAX_OUTPUT_PORT_TYPE
taps[2] <= shift_reg[15][2].DB_MAX_OUTPUT_PORT_TYPE
taps[3] <= shift_reg[15][3].DB_MAX_OUTPUT_PORT_TYPE
taps[4] <= shift_reg[15][4].DB_MAX_OUTPUT_PORT_TYPE
taps[5] <= shift_reg[15][5].DB_MAX_OUTPUT_PORT_TYPE
taps[6] <= shift_reg[15][6].DB_MAX_OUTPUT_PORT_TYPE
taps[7] <= shift_reg[15][7].DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_tx_stat_extract:U_TXSTAT
col => always2.IN1
col => late_excess_col_reg.OUTPUTSELECT
late_col => always2.IN0
excess_col => always2.IN1
reset => frm_err~reg0.ACLR
reset => frm_stat_val~reg0.ACLR
reset => frm_mltcast~reg0.ACLR
reset => frm_unicast~reg0.ACLR
reset => frm_broadcast~reg0.ACLR
reset => type_length[0].ACLR
reset => type_length[1].ACLR
reset => type_length[2].ACLR
reset => type_length[3].ACLR
reset => type_length[4].ACLR
reset => type_length[5].ACLR
reset => type_length[6].ACLR
reset => type_length[7].ACLR
reset => type_length[8].ACLR
reset => type_length[9].ACLR
reset => type_length[10].ACLR
reset => type_length[11].ACLR
reset => type_length[12].ACLR
reset => type_length[13].ACLR
reset => type_length[14].ACLR
reset => type_length[15].ACLR
reset => dest_addr[0].ACLR
reset => dest_addr[1].ACLR
reset => dest_addr[2].ACLR
reset => dest_addr[3].ACLR
reset => dest_addr[4].ACLR
reset => dest_addr[5].ACLR
reset => dest_addr[6].ACLR
reset => dest_addr[7].ACLR
reset => dest_addr[8].ACLR
reset => dest_addr[9].ACLR
reset => dest_addr[10].ACLR
reset => dest_addr[11].ACLR
reset => dest_addr[12].ACLR
reset => dest_addr[13].ACLR
reset => dest_addr[14].ACLR
reset => dest_addr[15].ACLR
reset => dest_addr[16].ACLR
reset => dest_addr[17].ACLR
reset => dest_addr[18].ACLR
reset => dest_addr[19].ACLR
reset => dest_addr[20].ACLR
reset => dest_addr[21].ACLR
reset => dest_addr[22].ACLR
reset => dest_addr[23].ACLR
reset => dest_addr[24].ACLR
reset => dest_addr[25].ACLR
reset => dest_addr[26].ACLR
reset => dest_addr[27].ACLR
reset => dest_addr[28].ACLR
reset => dest_addr[29].ACLR
reset => dest_addr[30].ACLR
reset => dest_addr[31].ACLR
reset => dest_addr[32].ACLR
reset => dest_addr[33].ACLR
reset => dest_addr[34].ACLR
reset => dest_addr[35].ACLR
reset => dest_addr[36].ACLR
reset => dest_addr[37].ACLR
reset => dest_addr[38].ACLR
reset => dest_addr[39].ACLR
reset => dest_addr[40].ACLR
reset => dest_addr[41].ACLR
reset => dest_addr[42].ACLR
reset => dest_addr[43].ACLR
reset => dest_addr[44].ACLR
reset => dest_addr[45].ACLR
reset => dest_addr[46].ACLR
reset => dest_addr[47].ACLR
reset => frm_cnt[0].ACLR
reset => frm_cnt[1].ACLR
reset => frm_cnt[2].ACLR
reset => frm_cnt[3].ACLR
reset => frm_cnt[4].ACLR
reset => frm_cnt[5].ACLR
reset => frm_cnt[6].ACLR
reset => frm_cnt[7].ACLR
reset => frm_cnt[8].ACLR
reset => frm_cnt[9].ACLR
reset => frm_cnt[10].ACLR
reset => frm_cnt[11].ACLR
reset => frm_cnt[12].ACLR
reset => frm_cnt[13].ACLR
reset => frm_cnt[14].ACLR
reset => frm_cnt[15].ACLR
reset => frm_stack_vlan.ACLR
reset => frm_vlan.ACLR
reset => sop_reg[0].ACLR
reset => sop_reg[1].ACLR
reset => sop_reg[2].ACLR
reset => sop_reg[3].ACLR
reset => sop_reg[4].ACLR
reset => sop_reg[5].ACLR
reset => sop_reg[6].ACLR
reset => sop_reg[7].ACLR
reset => sop_reg[8].ACLR
reset => sop_reg[9].ACLR
reset => sop_reg[10].ACLR
reset => sop_reg[11].ACLR
reset => sop_reg[12].ACLR
reset => sop_reg[13].ACLR
reset => sop_reg[14].ACLR
reset => sop_reg[15].ACLR
reset => sop_reg[16].ACLR
reset => sop_reg[17].ACLR
reset => sop_reg[18].ACLR
reset => sop_reg[19].ACLR
reset => sop_reg[20].ACLR
reset => sop_reg[21].ACLR
reset => sop_reg[22].ACLR
reset => sop_reg[23].ACLR
reset => sop_reg[24].ACLR
reset => sop_reg[25].ACLR
reset => late_excess_col_reg.ACLR
reset => frm_err_reg.ACLR
reset => col_reg.ACLR
tx_clk => frm_err~reg0.CLK
tx_clk => frm_stat_val~reg0.CLK
tx_clk => frm_mltcast~reg0.CLK
tx_clk => frm_unicast~reg0.CLK
tx_clk => frm_broadcast~reg0.CLK
tx_clk => type_length[0].CLK
tx_clk => type_length[1].CLK
tx_clk => type_length[2].CLK
tx_clk => type_length[3].CLK
tx_clk => type_length[4].CLK
tx_clk => type_length[5].CLK
tx_clk => type_length[6].CLK
tx_clk => type_length[7].CLK
tx_clk => type_length[8].CLK
tx_clk => type_length[9].CLK
tx_clk => type_length[10].CLK
tx_clk => type_length[11].CLK
tx_clk => type_length[12].CLK
tx_clk => type_length[13].CLK
tx_clk => type_length[14].CLK
tx_clk => type_length[15].CLK
tx_clk => dest_addr[0].CLK
tx_clk => dest_addr[1].CLK
tx_clk => dest_addr[2].CLK
tx_clk => dest_addr[3].CLK
tx_clk => dest_addr[4].CLK
tx_clk => dest_addr[5].CLK
tx_clk => dest_addr[6].CLK
tx_clk => dest_addr[7].CLK
tx_clk => dest_addr[8].CLK
tx_clk => dest_addr[9].CLK
tx_clk => dest_addr[10].CLK
tx_clk => dest_addr[11].CLK
tx_clk => dest_addr[12].CLK
tx_clk => dest_addr[13].CLK
tx_clk => dest_addr[14].CLK
tx_clk => dest_addr[15].CLK
tx_clk => dest_addr[16].CLK
tx_clk => dest_addr[17].CLK
tx_clk => dest_addr[18].CLK
tx_clk => dest_addr[19].CLK
tx_clk => dest_addr[20].CLK
tx_clk => dest_addr[21].CLK
tx_clk => dest_addr[22].CLK
tx_clk => dest_addr[23].CLK
tx_clk => dest_addr[24].CLK
tx_clk => dest_addr[25].CLK
tx_clk => dest_addr[26].CLK
tx_clk => dest_addr[27].CLK
tx_clk => dest_addr[28].CLK
tx_clk => dest_addr[29].CLK
tx_clk => dest_addr[30].CLK
tx_clk => dest_addr[31].CLK
tx_clk => dest_addr[32].CLK
tx_clk => dest_addr[33].CLK
tx_clk => dest_addr[34].CLK
tx_clk => dest_addr[35].CLK
tx_clk => dest_addr[36].CLK
tx_clk => dest_addr[37].CLK
tx_clk => dest_addr[38].CLK
tx_clk => dest_addr[39].CLK
tx_clk => dest_addr[40].CLK
tx_clk => dest_addr[41].CLK
tx_clk => dest_addr[42].CLK
tx_clk => dest_addr[43].CLK
tx_clk => dest_addr[44].CLK
tx_clk => dest_addr[45].CLK
tx_clk => dest_addr[46].CLK
tx_clk => dest_addr[47].CLK
tx_clk => frm_cnt[0].CLK
tx_clk => frm_cnt[1].CLK
tx_clk => frm_cnt[2].CLK
tx_clk => frm_cnt[3].CLK
tx_clk => frm_cnt[4].CLK
tx_clk => frm_cnt[5].CLK
tx_clk => frm_cnt[6].CLK
tx_clk => frm_cnt[7].CLK
tx_clk => frm_cnt[8].CLK
tx_clk => frm_cnt[9].CLK
tx_clk => frm_cnt[10].CLK
tx_clk => frm_cnt[11].CLK
tx_clk => frm_cnt[12].CLK
tx_clk => frm_cnt[13].CLK
tx_clk => frm_cnt[14].CLK
tx_clk => frm_cnt[15].CLK
tx_clk => frm_stack_vlan.CLK
tx_clk => frm_vlan.CLK
tx_clk => sop_reg[0].CLK
tx_clk => sop_reg[1].CLK
tx_clk => sop_reg[2].CLK
tx_clk => sop_reg[3].CLK
tx_clk => sop_reg[4].CLK
tx_clk => sop_reg[5].CLK
tx_clk => sop_reg[6].CLK
tx_clk => sop_reg[7].CLK
tx_clk => sop_reg[8].CLK
tx_clk => sop_reg[9].CLK
tx_clk => sop_reg[10].CLK
tx_clk => sop_reg[11].CLK
tx_clk => sop_reg[12].CLK
tx_clk => sop_reg[13].CLK
tx_clk => sop_reg[14].CLK
tx_clk => sop_reg[15].CLK
tx_clk => sop_reg[16].CLK
tx_clk => sop_reg[17].CLK
tx_clk => sop_reg[18].CLK
tx_clk => sop_reg[19].CLK
tx_clk => sop_reg[20].CLK
tx_clk => sop_reg[21].CLK
tx_clk => sop_reg[22].CLK
tx_clk => sop_reg[23].CLK
tx_clk => sop_reg[24].CLK
tx_clk => sop_reg[25].CLK
tx_clk => late_excess_col_reg.CLK
tx_clk => frm_err_reg.CLK
tx_clk => col_reg.CLK
clk_ena => frm_err.IN1
clk_ena => frm_stat_val.DATAB
clk_ena => frm_err_reg.ENA
clk_ena => sop_reg[25].ENA
clk_ena => sop_reg[24].ENA
clk_ena => sop_reg[23].ENA
clk_ena => sop_reg[22].ENA
clk_ena => sop_reg[21].ENA
clk_ena => sop_reg[20].ENA
clk_ena => sop_reg[19].ENA
clk_ena => sop_reg[18].ENA
clk_ena => sop_reg[17].ENA
clk_ena => sop_reg[16].ENA
clk_ena => sop_reg[15].ENA
clk_ena => sop_reg[14].ENA
clk_ena => sop_reg[13].ENA
clk_ena => sop_reg[12].ENA
clk_ena => sop_reg[11].ENA
clk_ena => sop_reg[10].ENA
clk_ena => sop_reg[9].ENA
clk_ena => sop_reg[8].ENA
clk_ena => sop_reg[7].ENA
clk_ena => sop_reg[6].ENA
clk_ena => sop_reg[5].ENA
clk_ena => sop_reg[4].ENA
clk_ena => sop_reg[3].ENA
clk_ena => sop_reg[2].ENA
clk_ena => sop_reg[1].ENA
clk_ena => sop_reg[0].ENA
clk_ena => frm_cnt[15].ENA
clk_ena => frm_cnt[14].ENA
clk_ena => frm_cnt[13].ENA
clk_ena => frm_cnt[12].ENA
clk_ena => frm_cnt[11].ENA
clk_ena => frm_cnt[10].ENA
clk_ena => frm_cnt[9].ENA
clk_ena => frm_cnt[8].ENA
clk_ena => frm_cnt[7].ENA
clk_ena => frm_cnt[6].ENA
clk_ena => frm_cnt[5].ENA
clk_ena => frm_cnt[4].ENA
clk_ena => frm_cnt[3].ENA
clk_ena => frm_cnt[2].ENA
clk_ena => frm_cnt[1].ENA
clk_ena => frm_cnt[0].ENA
clk_ena => dest_addr[47].ENA
clk_ena => dest_addr[46].ENA
clk_ena => dest_addr[45].ENA
clk_ena => dest_addr[44].ENA
clk_ena => dest_addr[43].ENA
clk_ena => dest_addr[42].ENA
clk_ena => dest_addr[41].ENA
clk_ena => dest_addr[40].ENA
clk_ena => dest_addr[39].ENA
clk_ena => dest_addr[38].ENA
clk_ena => dest_addr[37].ENA
clk_ena => dest_addr[36].ENA
clk_ena => dest_addr[35].ENA
clk_ena => dest_addr[34].ENA
clk_ena => dest_addr[33].ENA
clk_ena => dest_addr[32].ENA
clk_ena => dest_addr[31].ENA
clk_ena => dest_addr[30].ENA
clk_ena => dest_addr[29].ENA
clk_ena => dest_addr[28].ENA
clk_ena => dest_addr[27].ENA
clk_ena => dest_addr[26].ENA
clk_ena => dest_addr[25].ENA
clk_ena => dest_addr[24].ENA
clk_ena => dest_addr[23].ENA
clk_ena => dest_addr[22].ENA
clk_ena => dest_addr[21].ENA
clk_ena => dest_addr[20].ENA
clk_ena => dest_addr[19].ENA
clk_ena => dest_addr[18].ENA
clk_ena => dest_addr[17].ENA
clk_ena => dest_addr[16].ENA
clk_ena => dest_addr[15].ENA
clk_ena => dest_addr[14].ENA
clk_ena => dest_addr[13].ENA
clk_ena => dest_addr[12].ENA
clk_ena => dest_addr[11].ENA
clk_ena => dest_addr[10].ENA
clk_ena => dest_addr[9].ENA
clk_ena => dest_addr[8].ENA
clk_ena => dest_addr[7].ENA
clk_ena => dest_addr[6].ENA
clk_ena => dest_addr[5].ENA
clk_ena => dest_addr[4].ENA
clk_ena => dest_addr[3].ENA
clk_ena => dest_addr[2].ENA
clk_ena => dest_addr[1].ENA
clk_ena => dest_addr[0].ENA
clk_ena => type_length[15].ENA
clk_ena => type_length[14].ENA
clk_ena => type_length[13].ENA
clk_ena => type_length[12].ENA
clk_ena => type_length[11].ENA
clk_ena => type_length[10].ENA
clk_ena => type_length[9].ENA
clk_ena => type_length[8].ENA
clk_ena => type_length[7].ENA
clk_ena => type_length[6].ENA
clk_ena => type_length[5].ENA
clk_ena => type_length[4].ENA
clk_ena => type_length[3].ENA
clk_ena => type_length[2].ENA
clk_ena => type_length[1].ENA
clk_ena => type_length[0].ENA
data_en => always1.IN1
data_en => sop_reg.DATAA
data_en => always5.IN1
data_en => always1.IN1
data_err => data_err_temp.IN1
data[0] => dest_addr.DATAB
data[0] => dest_addr.DATAB
data[0] => dest_addr.DATAB
data[0] => dest_addr.DATAB
data[0] => dest_addr.DATAB
data[0] => dest_addr.DATAB
data[0] => type_length.DATAB
data[0] => type_length.DATAB
data[1] => dest_addr.DATAB
data[1] => dest_addr.DATAB
data[1] => dest_addr.DATAB
data[1] => dest_addr.DATAB
data[1] => dest_addr.DATAB
data[1] => dest_addr.DATAB
data[1] => type_length.DATAB
data[1] => type_length.DATAB
data[2] => dest_addr.DATAB
data[2] => dest_addr.DATAB
data[2] => dest_addr.DATAB
data[2] => dest_addr.DATAB
data[2] => dest_addr.DATAB
data[2] => dest_addr.DATAB
data[2] => type_length.DATAB
data[2] => type_length.DATAB
data[3] => dest_addr.DATAB
data[3] => dest_addr.DATAB
data[3] => dest_addr.DATAB
data[3] => dest_addr.DATAB
data[3] => dest_addr.DATAB
data[3] => dest_addr.DATAB
data[3] => type_length.DATAB
data[3] => type_length.DATAB
data[4] => dest_addr.DATAB
data[4] => dest_addr.DATAB
data[4] => dest_addr.DATAB
data[4] => dest_addr.DATAB
data[4] => dest_addr.DATAB
data[4] => dest_addr.DATAB
data[4] => type_length.DATAB
data[4] => type_length.DATAB
data[5] => dest_addr.DATAB
data[5] => dest_addr.DATAB
data[5] => dest_addr.DATAB
data[5] => dest_addr.DATAB
data[5] => dest_addr.DATAB
data[5] => dest_addr.DATAB
data[5] => type_length.DATAB
data[5] => type_length.DATAB
data[6] => dest_addr.DATAB
data[6] => dest_addr.DATAB
data[6] => dest_addr.DATAB
data[6] => dest_addr.DATAB
data[6] => dest_addr.DATAB
data[6] => dest_addr.DATAB
data[6] => type_length.DATAB
data[6] => type_length.DATAB
data[7] => dest_addr.DATAB
data[7] => dest_addr.DATAB
data[7] => dest_addr.DATAB
data[7] => dest_addr.DATAB
data[7] => dest_addr.DATAB
data[7] => dest_addr.DATAB
data[7] => type_length.DATAB
data[7] => type_length.DATAB
frm_stat_val <= frm_stat_val~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_err <= frm_err~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_length[0] <= frm_cnt[0].DB_MAX_OUTPUT_PORT_TYPE
frm_length[1] <= frm_cnt[1].DB_MAX_OUTPUT_PORT_TYPE
frm_length[2] <= frm_cnt[2].DB_MAX_OUTPUT_PORT_TYPE
frm_length[3] <= frm_cnt[3].DB_MAX_OUTPUT_PORT_TYPE
frm_length[4] <= frm_cnt[4].DB_MAX_OUTPUT_PORT_TYPE
frm_length[5] <= frm_cnt[5].DB_MAX_OUTPUT_PORT_TYPE
frm_length[6] <= frm_cnt[6].DB_MAX_OUTPUT_PORT_TYPE
frm_length[7] <= frm_cnt[7].DB_MAX_OUTPUT_PORT_TYPE
frm_length[8] <= frm_cnt[8].DB_MAX_OUTPUT_PORT_TYPE
frm_length[9] <= frm_cnt[9].DB_MAX_OUTPUT_PORT_TYPE
frm_length[10] <= frm_cnt[10].DB_MAX_OUTPUT_PORT_TYPE
frm_length[11] <= frm_cnt[11].DB_MAX_OUTPUT_PORT_TYPE
frm_length[12] <= frm_cnt[12].DB_MAX_OUTPUT_PORT_TYPE
frm_length[13] <= frm_cnt[13].DB_MAX_OUTPUT_PORT_TYPE
frm_length[14] <= frm_cnt[14].DB_MAX_OUTPUT_PORT_TYPE
frm_length[15] <= frm_cnt[15].DB_MAX_OUTPUT_PORT_TYPE
frm_unicast <= frm_unicast~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_broadcast <= frm_broadcast~reg0.DB_MAX_OUTPUT_PORT_TYPE
frm_mltcast <= frm_mltcast~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX
gm_rx_col => ~NO_FANOUT~
gm_rx_crs => ~NO_FANOUT~
col <= <GND>
crs <= <GND>
smac_0[0] => ~NO_FANOUT~
smac_0[1] => ~NO_FANOUT~
smac_0[2] => ~NO_FANOUT~
smac_0[3] => ~NO_FANOUT~
smac_0[4] => ~NO_FANOUT~
smac_0[5] => ~NO_FANOUT~
smac_0[6] => ~NO_FANOUT~
smac_0[7] => ~NO_FANOUT~
smac_0[8] => ~NO_FANOUT~
smac_0[9] => ~NO_FANOUT~
smac_0[10] => ~NO_FANOUT~
smac_0[11] => ~NO_FANOUT~
smac_0[12] => ~NO_FANOUT~
smac_0[13] => ~NO_FANOUT~
smac_0[14] => ~NO_FANOUT~
smac_0[15] => ~NO_FANOUT~
smac_0[16] => ~NO_FANOUT~
smac_0[17] => ~NO_FANOUT~
smac_0[18] => ~NO_FANOUT~
smac_0[19] => ~NO_FANOUT~
smac_0[20] => ~NO_FANOUT~
smac_0[21] => ~NO_FANOUT~
smac_0[22] => ~NO_FANOUT~
smac_0[23] => ~NO_FANOUT~
smac_0[24] => ~NO_FANOUT~
smac_0[25] => ~NO_FANOUT~
smac_0[26] => ~NO_FANOUT~
smac_0[27] => ~NO_FANOUT~
smac_0[28] => ~NO_FANOUT~
smac_0[29] => ~NO_FANOUT~
smac_0[30] => ~NO_FANOUT~
smac_0[31] => ~NO_FANOUT~
smac_0[32] => ~NO_FANOUT~
smac_0[33] => ~NO_FANOUT~
smac_0[34] => ~NO_FANOUT~
smac_0[35] => ~NO_FANOUT~
smac_0[36] => ~NO_FANOUT~
smac_0[37] => ~NO_FANOUT~
smac_0[38] => ~NO_FANOUT~
smac_0[39] => ~NO_FANOUT~
smac_0[40] => ~NO_FANOUT~
smac_0[41] => ~NO_FANOUT~
smac_0[42] => ~NO_FANOUT~
smac_0[43] => ~NO_FANOUT~
smac_0[44] => ~NO_FANOUT~
smac_0[45] => ~NO_FANOUT~
smac_0[46] => ~NO_FANOUT~
smac_0[47] => ~NO_FANOUT~
smac_1[0] => ~NO_FANOUT~
smac_1[1] => ~NO_FANOUT~
smac_1[2] => ~NO_FANOUT~
smac_1[3] => ~NO_FANOUT~
smac_1[4] => ~NO_FANOUT~
smac_1[5] => ~NO_FANOUT~
smac_1[6] => ~NO_FANOUT~
smac_1[7] => ~NO_FANOUT~
smac_1[8] => ~NO_FANOUT~
smac_1[9] => ~NO_FANOUT~
smac_1[10] => ~NO_FANOUT~
smac_1[11] => ~NO_FANOUT~
smac_1[12] => ~NO_FANOUT~
smac_1[13] => ~NO_FANOUT~
smac_1[14] => ~NO_FANOUT~
smac_1[15] => ~NO_FANOUT~
smac_1[16] => ~NO_FANOUT~
smac_1[17] => ~NO_FANOUT~
smac_1[18] => ~NO_FANOUT~
smac_1[19] => ~NO_FANOUT~
smac_1[20] => ~NO_FANOUT~
smac_1[21] => ~NO_FANOUT~
smac_1[22] => ~NO_FANOUT~
smac_1[23] => ~NO_FANOUT~
smac_1[24] => ~NO_FANOUT~
smac_1[25] => ~NO_FANOUT~
smac_1[26] => ~NO_FANOUT~
smac_1[27] => ~NO_FANOUT~
smac_1[28] => ~NO_FANOUT~
smac_1[29] => ~NO_FANOUT~
smac_1[30] => ~NO_FANOUT~
smac_1[31] => ~NO_FANOUT~
smac_1[32] => ~NO_FANOUT~
smac_1[33] => ~NO_FANOUT~
smac_1[34] => ~NO_FANOUT~
smac_1[35] => ~NO_FANOUT~
smac_1[36] => ~NO_FANOUT~
smac_1[37] => ~NO_FANOUT~
smac_1[38] => ~NO_FANOUT~
smac_1[39] => ~NO_FANOUT~
smac_1[40] => ~NO_FANOUT~
smac_1[41] => ~NO_FANOUT~
smac_1[42] => ~NO_FANOUT~
smac_1[43] => ~NO_FANOUT~
smac_1[44] => ~NO_FANOUT~
smac_1[45] => ~NO_FANOUT~
smac_1[46] => ~NO_FANOUT~
smac_1[47] => ~NO_FANOUT~
smac_2[0] => ~NO_FANOUT~
smac_2[1] => ~NO_FANOUT~
smac_2[2] => ~NO_FANOUT~
smac_2[3] => ~NO_FANOUT~
smac_2[4] => ~NO_FANOUT~
smac_2[5] => ~NO_FANOUT~
smac_2[6] => ~NO_FANOUT~
smac_2[7] => ~NO_FANOUT~
smac_2[8] => ~NO_FANOUT~
smac_2[9] => ~NO_FANOUT~
smac_2[10] => ~NO_FANOUT~
smac_2[11] => ~NO_FANOUT~
smac_2[12] => ~NO_FANOUT~
smac_2[13] => ~NO_FANOUT~
smac_2[14] => ~NO_FANOUT~
smac_2[15] => ~NO_FANOUT~
smac_2[16] => ~NO_FANOUT~
smac_2[17] => ~NO_FANOUT~
smac_2[18] => ~NO_FANOUT~
smac_2[19] => ~NO_FANOUT~
smac_2[20] => ~NO_FANOUT~
smac_2[21] => ~NO_FANOUT~
smac_2[22] => ~NO_FANOUT~
smac_2[23] => ~NO_FANOUT~
smac_2[24] => ~NO_FANOUT~
smac_2[25] => ~NO_FANOUT~
smac_2[26] => ~NO_FANOUT~
smac_2[27] => ~NO_FANOUT~
smac_2[28] => ~NO_FANOUT~
smac_2[29] => ~NO_FANOUT~
smac_2[30] => ~NO_FANOUT~
smac_2[31] => ~NO_FANOUT~
smac_2[32] => ~NO_FANOUT~
smac_2[33] => ~NO_FANOUT~
smac_2[34] => ~NO_FANOUT~
smac_2[35] => ~NO_FANOUT~
smac_2[36] => ~NO_FANOUT~
smac_2[37] => ~NO_FANOUT~
smac_2[38] => ~NO_FANOUT~
smac_2[39] => ~NO_FANOUT~
smac_2[40] => ~NO_FANOUT~
smac_2[41] => ~NO_FANOUT~
smac_2[42] => ~NO_FANOUT~
smac_2[43] => ~NO_FANOUT~
smac_2[44] => ~NO_FANOUT~
smac_2[45] => ~NO_FANOUT~
smac_2[46] => ~NO_FANOUT~
smac_2[47] => ~NO_FANOUT~
smac_3[0] => ~NO_FANOUT~
smac_3[1] => ~NO_FANOUT~
smac_3[2] => ~NO_FANOUT~
smac_3[3] => ~NO_FANOUT~
smac_3[4] => ~NO_FANOUT~
smac_3[5] => ~NO_FANOUT~
smac_3[6] => ~NO_FANOUT~
smac_3[7] => ~NO_FANOUT~
smac_3[8] => ~NO_FANOUT~
smac_3[9] => ~NO_FANOUT~
smac_3[10] => ~NO_FANOUT~
smac_3[11] => ~NO_FANOUT~
smac_3[12] => ~NO_FANOUT~
smac_3[13] => ~NO_FANOUT~
smac_3[14] => ~NO_FANOUT~
smac_3[15] => ~NO_FANOUT~
smac_3[16] => ~NO_FANOUT~
smac_3[17] => ~NO_FANOUT~
smac_3[18] => ~NO_FANOUT~
smac_3[19] => ~NO_FANOUT~
smac_3[20] => ~NO_FANOUT~
smac_3[21] => ~NO_FANOUT~
smac_3[22] => ~NO_FANOUT~
smac_3[23] => ~NO_FANOUT~
smac_3[24] => ~NO_FANOUT~
smac_3[25] => ~NO_FANOUT~
smac_3[26] => ~NO_FANOUT~
smac_3[27] => ~NO_FANOUT~
smac_3[28] => ~NO_FANOUT~
smac_3[29] => ~NO_FANOUT~
smac_3[30] => ~NO_FANOUT~
smac_3[31] => ~NO_FANOUT~
smac_3[32] => ~NO_FANOUT~
smac_3[33] => ~NO_FANOUT~
smac_3[34] => ~NO_FANOUT~
smac_3[35] => ~NO_FANOUT~
smac_3[36] => ~NO_FANOUT~
smac_3[37] => ~NO_FANOUT~
smac_3[38] => ~NO_FANOUT~
smac_3[39] => ~NO_FANOUT~
smac_3[40] => ~NO_FANOUT~
smac_3[41] => ~NO_FANOUT~
smac_3[42] => ~NO_FANOUT~
smac_3[43] => ~NO_FANOUT~
smac_3[44] => ~NO_FANOUT~
smac_3[45] => ~NO_FANOUT~
smac_3[46] => ~NO_FANOUT~
smac_3[47] => ~NO_FANOUT~
tx_addr_sel[0] => ~NO_FANOUT~
tx_addr_sel[1] => ~NO_FANOUT~
tx_addr_sel[2] => ~NO_FANOUT~
reset_tx_clk => reset_tx_clk.IN1
tx_clk => tx_clk.IN4
txclk_ena => txclk_ena.IN1
ethernet_mode => ethernet_mode.IN1
half_duplex_ena => ~NO_FANOUT~
tx_en <= tx_en_s[1].DB_MAX_OUTPUT_PORT_TYPE
tx_d[0] <= rd_14[0].DB_MAX_OUTPUT_PORT_TYPE
tx_d[1] <= rd_14[1].DB_MAX_OUTPUT_PORT_TYPE
tx_d[2] <= rd_14[2].DB_MAX_OUTPUT_PORT_TYPE
tx_d[3] <= rd_14[3].DB_MAX_OUTPUT_PORT_TYPE
tx_d[4] <= rd_14[4].DB_MAX_OUTPUT_PORT_TYPE
tx_d[5] <= rd_14[5].DB_MAX_OUTPUT_PORT_TYPE
tx_d[6] <= rd_14[6].DB_MAX_OUTPUT_PORT_TYPE
tx_d[7] <= rd_14[7].DB_MAX_OUTPUT_PORT_TYPE
tx_err <= tx_err~reg0.DB_MAX_OUTPUT_PORT_TYPE
xoff_gen => ~NO_FANOUT~
xon_gen => ~NO_FANOUT~
tx_crc_fwd => crc_fwd.DATAB
src_mac_insert => always11.IN1
src_mac_insert => always11.IN1
src_mac_insert => always11.IN1
src_mac_insert => always11.IN1
src_mac_insert => always11.IN1
src_mac_insert => always11.IN1
enable_tx => enable_tx.IN1
mac_ena_int => mac_ena.IN1
mac_addr[0] => rd_3.DATAB
mac_addr[1] => rd_3.DATAB
mac_addr[2] => rd_3.DATAB
mac_addr[3] => rd_3.DATAB
mac_addr[4] => rd_3.DATAB
mac_addr[5] => rd_3.DATAB
mac_addr[6] => rd_3.DATAB
mac_addr[7] => rd_3.DATAB
mac_addr[8] => rd_3.DATAB
mac_addr[9] => rd_3.DATAB
mac_addr[10] => rd_3.DATAB
mac_addr[11] => rd_3.DATAB
mac_addr[12] => rd_3.DATAB
mac_addr[13] => rd_3.DATAB
mac_addr[14] => rd_3.DATAB
mac_addr[15] => rd_3.DATAB
mac_addr[16] => rd_3.DATAB
mac_addr[17] => rd_3.DATAB
mac_addr[18] => rd_3.DATAB
mac_addr[19] => rd_3.DATAB
mac_addr[20] => rd_3.DATAB
mac_addr[21] => rd_3.DATAB
mac_addr[22] => rd_3.DATAB
mac_addr[23] => rd_3.DATAB
mac_addr[24] => rd_3.DATAB
mac_addr[25] => rd_3.DATAB
mac_addr[26] => rd_3.DATAB
mac_addr[27] => rd_3.DATAB
mac_addr[28] => rd_3.DATAB
mac_addr[29] => rd_3.DATAB
mac_addr[30] => rd_3.DATAB
mac_addr[31] => rd_3.DATAB
mac_addr[32] => rd_3.DATAB
mac_addr[33] => rd_3.DATAB
mac_addr[34] => rd_3.DATAB
mac_addr[35] => rd_3.DATAB
mac_addr[36] => rd_3.DATAB
mac_addr[37] => rd_3.DATAB
mac_addr[38] => rd_3.DATAB
mac_addr[39] => rd_3.DATAB
mac_addr[40] => rd_3.DATAB
mac_addr[41] => rd_3.DATAB
mac_addr[42] => rd_3.DATAB
mac_addr[43] => rd_3.DATAB
mac_addr[44] => rd_3.DATAB
mac_addr[45] => rd_3.DATAB
mac_addr[46] => rd_3.DATAB
mac_addr[47] => rd_3.DATAB
pause_quant_val[0] => ~NO_FANOUT~
pause_quant_val[1] => ~NO_FANOUT~
pause_quant_val[2] => ~NO_FANOUT~
pause_quant_val[3] => ~NO_FANOUT~
pause_quant_val[4] => ~NO_FANOUT~
pause_quant_val[5] => ~NO_FANOUT~
pause_quant_val[6] => ~NO_FANOUT~
pause_quant_val[7] => ~NO_FANOUT~
pause_quant_val[8] => ~NO_FANOUT~
pause_quant_val[9] => ~NO_FANOUT~
pause_quant_val[10] => ~NO_FANOUT~
pause_quant_val[11] => ~NO_FANOUT~
pause_quant_val[12] => ~NO_FANOUT~
pause_quant_val[13] => ~NO_FANOUT~
pause_quant_val[14] => ~NO_FANOUT~
pause_quant_val[15] => ~NO_FANOUT~
pause_quant_avb => ~NO_FANOUT~
pause_quant[0] => ~NO_FANOUT~
pause_quant[1] => ~NO_FANOUT~
pause_quant[2] => ~NO_FANOUT~
pause_quant[3] => ~NO_FANOUT~
pause_quant[4] => ~NO_FANOUT~
pause_quant[5] => ~NO_FANOUT~
pause_quant[6] => ~NO_FANOUT~
pause_quant[7] => ~NO_FANOUT~
pause_quant[8] => ~NO_FANOUT~
pause_quant[9] => ~NO_FANOUT~
pause_quant[10] => ~NO_FANOUT~
pause_quant[11] => ~NO_FANOUT~
pause_quant[12] => ~NO_FANOUT~
pause_quant[13] => ~NO_FANOUT~
pause_quant[14] => ~NO_FANOUT~
pause_quant[15] => ~NO_FANOUT~
holdoff_quant[0] => ~NO_FANOUT~
holdoff_quant[1] => ~NO_FANOUT~
holdoff_quant[2] => ~NO_FANOUT~
holdoff_quant[3] => ~NO_FANOUT~
holdoff_quant[4] => ~NO_FANOUT~
holdoff_quant[5] => ~NO_FANOUT~
holdoff_quant[6] => ~NO_FANOUT~
holdoff_quant[7] => ~NO_FANOUT~
holdoff_quant[8] => ~NO_FANOUT~
holdoff_quant[9] => ~NO_FANOUT~
holdoff_quant[10] => ~NO_FANOUT~
holdoff_quant[11] => ~NO_FANOUT~
holdoff_quant[12] => ~NO_FANOUT~
holdoff_quant[13] => ~NO_FANOUT~
holdoff_quant[14] => ~NO_FANOUT~
holdoff_quant[15] => ~NO_FANOUT~
magic_ena => ~NO_FANOUT~
sleep_ena => ~NO_FANOUT~
tx_ipg_len[0] => tx_ipg_len[0].IN1
tx_ipg_len[1] => tx_ipg_len[1].IN1
tx_ipg_len[2] => tx_ipg_len[2].IN1
tx_ipg_len[3] => tx_ipg_len[3].IN1
tx_ipg_len[4] => tx_ipg_len[4].IN1
pause_tx <= pause_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_ff_uflow <= tx_ff_uflow~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_stat_empty => always3.IN1
tx_stat_empty => always6.IN1
tx_stat_empty => always8.IN1
tx_stat => always11.IN1
tx_stat_rden <= tx_stat_rden~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_septy => ~NO_FANOUT~
tx_data_int[0] => rd_1.DATAB
tx_data_int[1] => rd_1.DATAB
tx_data_int[2] => rd_1.DATAB
tx_data_int[3] => rd_1.DATAB
tx_data_int[4] => rd_1.DATAB
tx_data_int[5] => rd_1.DATAB
tx_data_int[6] => rd_1.DATAB
tx_data_int[7] => rd_1.DATAB
tx_sav_int => tx_sav_int_reg.DATAIN
tx_empty => always3.IN1
tx_empty => always6.IN1
tx_empty => always3.IN1
tx_sop_int => sop.DATAB
tx_eop_int => eop_0.IN1
tx_rden_int <= tx_rden_int.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_std_synchronizer:U_SYNC_1
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_std_synchronizer:U_SYNC_2
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_std_synchronizer_bundle:U_SYNC_3
clk => clk.IN5
reset_n => reset_n.IN5
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC
clk => clk.IN2
clk_ena => clk_ena.IN2
rst => rst.IN2
sof => sof.IN1
data[0] => data_i.DATAB
data[1] => data_i.DATAB
data[2] => data_i.DATAB
data[3] => data_i.DATAB
data[4] => data_i.DATAB
data[5] => data_i.DATAB
data[6] => data_i.DATAB
data[7] => data_i.DATAB
eof => eof.IN1
crc_vld <= altera_tse_crc32ctl8:U_CTL.crc_vld
crc[0] <= altera_tse_crc32galois8:U_GALS.outp
crc[1] <= altera_tse_crc32galois8:U_GALS.outp
crc[2] <= altera_tse_crc32galois8:U_GALS.outp
crc[3] <= altera_tse_crc32galois8:U_GALS.outp
crc[4] <= altera_tse_crc32galois8:U_GALS.outp
crc[5] <= altera_tse_crc32galois8:U_GALS.outp
crc[6] <= altera_tse_crc32galois8:U_GALS.outp
crc[7] <= altera_tse_crc32galois8:U_GALS.outp
crc[8] <= altera_tse_crc32galois8:U_GALS.outp
crc[9] <= altera_tse_crc32galois8:U_GALS.outp
crc[10] <= altera_tse_crc32galois8:U_GALS.outp
crc[11] <= altera_tse_crc32galois8:U_GALS.outp
crc[12] <= altera_tse_crc32galois8:U_GALS.outp
crc[13] <= altera_tse_crc32galois8:U_GALS.outp
crc[14] <= altera_tse_crc32galois8:U_GALS.outp
crc[15] <= altera_tse_crc32galois8:U_GALS.outp
crc[16] <= altera_tse_crc32galois8:U_GALS.outp
crc[17] <= altera_tse_crc32galois8:U_GALS.outp
crc[18] <= altera_tse_crc32galois8:U_GALS.outp
crc[19] <= altera_tse_crc32galois8:U_GALS.outp
crc[20] <= altera_tse_crc32galois8:U_GALS.outp
crc[21] <= altera_tse_crc32galois8:U_GALS.outp
crc[22] <= altera_tse_crc32galois8:U_GALS.outp
crc[23] <= altera_tse_crc32galois8:U_GALS.outp
crc[24] <= altera_tse_crc32galois8:U_GALS.outp
crc[25] <= altera_tse_crc32galois8:U_GALS.outp
crc[26] <= altera_tse_crc32galois8:U_GALS.outp
crc[27] <= altera_tse_crc32galois8:U_GALS.outp
crc[28] <= altera_tse_crc32galois8:U_GALS.outp
crc[29] <= altera_tse_crc32galois8:U_GALS.outp
crc[30] <= altera_tse_crc32galois8:U_GALS.outp
crc[31] <= altera_tse_crc32galois8:U_GALS.outp


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|altera_tse_crc32galois8:U_GALS
clk => reg_out[0].CLK
clk => reg_out[1].CLK
clk => reg_out[2].CLK
clk => reg_out[3].CLK
clk => reg_out[4].CLK
clk => reg_out[5].CLK
clk => reg_out[6].CLK
clk => reg_out[7].CLK
clk => reg_out[8].CLK
clk => reg_out[9].CLK
clk => reg_out[10].CLK
clk => reg_out[11].CLK
clk => reg_out[12].CLK
clk => reg_out[13].CLK
clk => reg_out[14].CLK
clk => reg_out[15].CLK
clk => reg_out[16].CLK
clk => reg_out[17].CLK
clk => reg_out[18].CLK
clk => reg_out[19].CLK
clk => reg_out[20].CLK
clk => reg_out[21].CLK
clk => reg_out[22].CLK
clk => reg_out[23].CLK
clk => reg_out[24].CLK
clk => reg_out[25].CLK
clk => reg_out[26].CLK
clk => reg_out[27].CLK
clk => reg_out[28].CLK
clk => reg_out[29].CLK
clk => reg_out[30].CLK
clk => reg_out[31].CLK
clk_ena => reg_out[0].ENA
clk_ena => reg_out[31].ENA
clk_ena => reg_out[30].ENA
clk_ena => reg_out[29].ENA
clk_ena => reg_out[28].ENA
clk_ena => reg_out[27].ENA
clk_ena => reg_out[26].ENA
clk_ena => reg_out[25].ENA
clk_ena => reg_out[24].ENA
clk_ena => reg_out[23].ENA
clk_ena => reg_out[22].ENA
clk_ena => reg_out[21].ENA
clk_ena => reg_out[20].ENA
clk_ena => reg_out[19].ENA
clk_ena => reg_out[18].ENA
clk_ena => reg_out[17].ENA
clk_ena => reg_out[16].ENA
clk_ena => reg_out[15].ENA
clk_ena => reg_out[14].ENA
clk_ena => reg_out[13].ENA
clk_ena => reg_out[12].ENA
clk_ena => reg_out[11].ENA
clk_ena => reg_out[10].ENA
clk_ena => reg_out[9].ENA
clk_ena => reg_out[8].ENA
clk_ena => reg_out[7].ENA
clk_ena => reg_out[6].ENA
clk_ena => reg_out[5].ENA
clk_ena => reg_out[4].ENA
clk_ena => reg_out[3].ENA
clk_ena => reg_out[2].ENA
clk_ena => reg_out[1].ENA
rst => reg_out[0].ACLR
rst => reg_out[1].ACLR
rst => reg_out[2].ACLR
rst => reg_out[3].ACLR
rst => reg_out[4].ACLR
rst => reg_out[5].ACLR
rst => reg_out[6].ACLR
rst => reg_out[7].ACLR
rst => reg_out[8].ACLR
rst => reg_out[9].ACLR
rst => reg_out[10].ACLR
rst => reg_out[11].ACLR
rst => reg_out[12].ACLR
rst => reg_out[13].ACLR
rst => reg_out[14].ACLR
rst => reg_out[15].ACLR
rst => reg_out[16].ACLR
rst => reg_out[17].ACLR
rst => reg_out[18].ACLR
rst => reg_out[19].ACLR
rst => reg_out[20].ACLR
rst => reg_out[21].ACLR
rst => reg_out[22].ACLR
rst => reg_out[23].ACLR
rst => reg_out[24].ACLR
rst => reg_out[25].ACLR
rst => reg_out[26].ACLR
rst => reg_out[27].ACLR
rst => reg_out[28].ACLR
rst => reg_out[29].ACLR
rst => reg_out[30].ACLR
rst => reg_out[31].ACLR
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
clr => reg_out.OUTPUTSELECT
data[0] => o1[27].IN1
data[1] => o1[22].IN1
data[2] => o1[9].IN1
data[3] => o1[28].IN1
data[4] => o[28].IN1
data[5] => o1[29].IN1
data[6] => o[30].IN1
data[7] => o[31].IN1
outp[0] <= reg_out[31].DB_MAX_OUTPUT_PORT_TYPE
outp[1] <= reg_out[30].DB_MAX_OUTPUT_PORT_TYPE
outp[2] <= reg_out[29].DB_MAX_OUTPUT_PORT_TYPE
outp[3] <= reg_out[28].DB_MAX_OUTPUT_PORT_TYPE
outp[4] <= reg_out[27].DB_MAX_OUTPUT_PORT_TYPE
outp[5] <= reg_out[26].DB_MAX_OUTPUT_PORT_TYPE
outp[6] <= reg_out[25].DB_MAX_OUTPUT_PORT_TYPE
outp[7] <= reg_out[24].DB_MAX_OUTPUT_PORT_TYPE
outp[8] <= reg_out[23].DB_MAX_OUTPUT_PORT_TYPE
outp[9] <= reg_out[22].DB_MAX_OUTPUT_PORT_TYPE
outp[10] <= reg_out[21].DB_MAX_OUTPUT_PORT_TYPE
outp[11] <= reg_out[20].DB_MAX_OUTPUT_PORT_TYPE
outp[12] <= reg_out[19].DB_MAX_OUTPUT_PORT_TYPE
outp[13] <= reg_out[18].DB_MAX_OUTPUT_PORT_TYPE
outp[14] <= reg_out[17].DB_MAX_OUTPUT_PORT_TYPE
outp[15] <= reg_out[16].DB_MAX_OUTPUT_PORT_TYPE
outp[16] <= reg_out[15].DB_MAX_OUTPUT_PORT_TYPE
outp[17] <= reg_out[14].DB_MAX_OUTPUT_PORT_TYPE
outp[18] <= reg_out[13].DB_MAX_OUTPUT_PORT_TYPE
outp[19] <= reg_out[12].DB_MAX_OUTPUT_PORT_TYPE
outp[20] <= reg_out[11].DB_MAX_OUTPUT_PORT_TYPE
outp[21] <= reg_out[10].DB_MAX_OUTPUT_PORT_TYPE
outp[22] <= reg_out[9].DB_MAX_OUTPUT_PORT_TYPE
outp[23] <= reg_out[8].DB_MAX_OUTPUT_PORT_TYPE
outp[24] <= reg_out[7].DB_MAX_OUTPUT_PORT_TYPE
outp[25] <= reg_out[6].DB_MAX_OUTPUT_PORT_TYPE
outp[26] <= reg_out[5].DB_MAX_OUTPUT_PORT_TYPE
outp[27] <= reg_out[4].DB_MAX_OUTPUT_PORT_TYPE
outp[28] <= reg_out[3].DB_MAX_OUTPUT_PORT_TYPE
outp[29] <= reg_out[2].DB_MAX_OUTPUT_PORT_TYPE
outp[30] <= reg_out[1].DB_MAX_OUTPUT_PORT_TYPE
outp[31] <= reg_out[0].DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|altera_tse_crc328generator:U_CRC|altera_tse_crc32ctl8:U_CTL
clk => eof_dly[0].CLK
clk => eof_dly[1].CLK
clk => eof_dly[2].CLK
clk => eof_dly[3].CLK
clk => eof_dly[4].CLK
clk => eof_dly[5].CLK
clk_ena => eof_dly[0].ENA
clk_ena => eof_dly[5].ENA
clk_ena => eof_dly[4].ENA
clk_ena => eof_dly[3].ENA
clk_ena => eof_dly[2].ENA
clk_ena => eof_dly[1].ENA
rst => eof_dly[0].ACLR
rst => eof_dly[1].ACLR
rst => eof_dly[2].ACLR
rst => eof_dly[3].ACLR
rst => eof_dly[4].ACLR
rst => eof_dly[5].ACLR
eof => eof_dly[0].DATAIN
crc_vld <= eof_dly[5].DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF
reset_rx_clk => reset_rx_clk.IN2
reset_ff_rx_clk => reset_ff_rx_clk.IN2
sw_reset => sw_reset.IN1
sw_reset_done <= Selector8.DB_MAX_OUTPUT_PORT_TYPE
rx_err_frm_disc => rx_err_frm_disc.IN1
rx_shift16 => rx_shift16.IN1
rx_clk => rx_clk.IN3
rx_stat_data[0] => err_stat_sig[0].IN1
rx_stat_data[1] => err_stat_sig[1].IN1
rx_stat_data[2] => err_stat_sig[2].IN1
rx_stat_data[3] => err_stat_sig[3].IN1
rx_stat_data[4] => err_stat_sig[4].IN1
rx_stat_data[5] => err_stat_sig[5].IN1
rx_stat_data[6] => err_stat_sig[6].IN1
rx_stat_data[7] => err_stat_sig[7].IN1
rx_stat_data[8] => err_stat_sig[8].IN1
rx_stat_data[9] => err_stat_sig[9].IN1
rx_stat_data[10] => err_stat_sig[10].IN1
rx_stat_data[11] => err_stat_sig[11].IN1
rx_stat_data[12] => err_stat_sig[12].IN1
rx_stat_data[13] => err_stat_sig[13].IN1
rx_stat_data[14] => err_stat_sig[14].IN1
rx_stat_data[15] => err_stat_sig[15].IN1
rx_stat_data[16] => err_stat_sig[16].IN1
rx_stat_data[17] => err_stat_sig[17].IN1
rx_stat_data[18] => err_stat_sig[18].IN1
rx_stat_data[19] => err_stat_sig[19].IN1
rx_stat_data[20] => err_stat_sig[20].IN1
rx_stat_data[21] => err_stat_sig[21].IN1
rx_stat_data[22] => err_stat_sig[22].IN1
rx_stat_wren => rx_stat_wren.IN1
rx_a_full <= altera_tse_a_fifo_opt_1246:RX_DATA.afull
rx_a_empty <= altera_tse_a_fifo_opt_1246:RX_DATA.aempty
rx_septy <= altera_tse_a_fifo_opt_1246:RX_DATA.septy
rx_data_int[0] => rx_data32.DATAB
rx_data_int[0] => rx_data32.DATAA
rx_data_int[0] => rx_data32.DATAB
rx_data_int[0] => rx_data32.DATAB
rx_data_int[1] => rx_data32.DATAB
rx_data_int[1] => rx_data32.DATAA
rx_data_int[1] => rx_data32.DATAB
rx_data_int[1] => rx_data32.DATAB
rx_data_int[2] => rx_data32.DATAB
rx_data_int[2] => rx_data32.DATAA
rx_data_int[2] => rx_data32.DATAB
rx_data_int[2] => rx_data32.DATAB
rx_data_int[3] => rx_data32.DATAB
rx_data_int[3] => rx_data32.DATAA
rx_data_int[3] => rx_data32.DATAB
rx_data_int[3] => rx_data32.DATAB
rx_data_int[4] => rx_data32.DATAB
rx_data_int[4] => rx_data32.DATAA
rx_data_int[4] => rx_data32.DATAB
rx_data_int[4] => rx_data32.DATAB
rx_data_int[5] => rx_data32.DATAB
rx_data_int[5] => rx_data32.DATAA
rx_data_int[5] => rx_data32.DATAB
rx_data_int[5] => rx_data32.DATAB
rx_data_int[6] => rx_data32.DATAB
rx_data_int[6] => rx_data32.DATAA
rx_data_int[6] => rx_data32.DATAB
rx_data_int[6] => rx_data32.DATAB
rx_data_int[7] => rx_data32.DATAB
rx_data_int[7] => rx_data32.DATAA
rx_data_int[7] => rx_data32.DATAB
rx_data_int[7] => rx_data32.DATAB
rx_sop_int => always0.IN0
rx_eop_int => always2.IN0
rx_eop_int => always4.IN1
rx_ucast_int => frm_type32.DATAB
rx_bcast_int => frm_type32.DATAB
rx_mcast_int => frm_type32.DATAB
rx_vlan_int => frm_type32.DATAB
rx_wren_int => always0.IN1
rx_wren_int => byte_empty.OUTPUTSELECT
rx_wren_int => byte_empty.OUTPUTSELECT
rx_wren_int => always2.IN1
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => rx_data32.OUTPUTSELECT
rx_wren_int => always4.IN1
sav_section[0] => sav_section[0].IN1
sav_section[1] => sav_section[1].IN1
sav_section[2] => sav_section[2].IN1
sav_section[3] => sav_section[3].IN1
sav_section[4] => sav_section[4].IN1
sav_section[5] => sav_section[5].IN1
sav_section[6] => sav_section[6].IN1
sav_section[7] => sav_section[7].IN1
sav_section[8] => sav_section[8].IN1
sav_section[9] => sav_section[9].IN1
sav_section[10] => sav_section[10].IN1
septy_section[0] => septy_section[0].IN1
septy_section[1] => septy_section[1].IN1
septy_section[2] => septy_section[2].IN1
septy_section[3] => septy_section[3].IN1
septy_section[4] => septy_section[4].IN1
septy_section[5] => septy_section[5].IN1
septy_section[6] => septy_section[6].IN1
septy_section[7] => septy_section[7].IN1
septy_section[8] => septy_section[8].IN1
septy_section[9] => septy_section[9].IN1
septy_section[10] => septy_section[10].IN1
af_level[0] => af_level[0].IN1
af_level[1] => af_level[1].IN1
af_level[2] => af_level[2].IN1
af_level[3] => af_level[3].IN1
af_level[4] => af_level[4].IN1
af_level[5] => af_level[5].IN1
af_level[6] => af_level[6].IN1
af_level[7] => af_level[7].IN1
af_level[8] => af_level[8].IN1
af_level[9] => af_level[9].IN1
af_level[10] => af_level[10].IN1
ae_level[0] => ae_level[0].IN1
ae_level[1] => ae_level[1].IN1
ae_level[2] => ae_level[2].IN1
ae_level[3] => ae_level[3].IN1
ae_level[4] => ae_level[4].IN1
ae_level[5] => ae_level[5].IN1
ae_level[6] => ae_level[6].IN1
ae_level[7] => ae_level[7].IN1
ae_level[8] => ae_level[8].IN1
ae_level[9] => ae_level[9].IN1
ae_level[10] => ae_level[10].IN1
ff_rx_clk => ff_rx_clk.IN6
ff_rx_data[0] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[1] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[2] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[3] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[4] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[5] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[6] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[7] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[8] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[9] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[10] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[11] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[12] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[13] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[14] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[15] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[16] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[17] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[18] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[19] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[20] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[21] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[22] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[23] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[24] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[25] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[26] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[27] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[28] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[29] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[30] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_data[31] <= ff_rx_data.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_mod[0] <= ff_rx_mod.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_mod[1] <= ff_rx_mod.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_sop <= ff_rx_sop_sig.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_eop <= Selector4.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err <= ff_rx_err.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[0] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[1] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[2] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[3] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[4] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[5] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[6] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[7] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[8] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[9] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[10] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[11] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[12] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[13] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[14] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[15] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[16] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[17] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[18] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[19] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[20] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[21] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_err_stat[22] <= ff_rx_err_stat.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_ucast <= ff_rx_frm_type_sig.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_bcast <= ff_rx_frm_type_sig.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_mcast <= ff_rx_frm_type_sig.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_vlan <= ff_rx_frm_type_sig.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_rdy => rx_rdy_reg.DATAIN
ff_rx_dval <= dval_sig.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_dsav <= altera_tse_a_fifo_opt_1246:RX_DATA.sav


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer:U_SYNC_1
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_2
clk => clk.IN11
reset_n => reset_n.IN11
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
din[9] => din[9].IN1
din[10] => din[10].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout
dout[9] <= altera_std_synchronizer:sync[9].u.dout
dout[10] <= altera_std_synchronizer:sync[10].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[9].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[10].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_3
clk => clk.IN11
reset_n => reset_n.IN11
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
din[9] => din[9].IN1
din[10] => din[10].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout
dout[9] <= altera_std_synchronizer:sync[9].u.dout
dout[10] <= altera_std_synchronizer:sync[10].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[9].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[10].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer:U_SYNC_4
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_std_synchronizer:U_SYNC_5
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA
reset_wclk => reset_wclk.IN1
reset_rclk => reset_rclk.IN1
wclk => wclk.IN4
wclk_ena => wclk_ena.IN1
wren => write_reg.IN2
din[0] => din_reg[0].IN1
din[1] => din_reg[1].IN1
din[2] => din_reg[2].IN1
din[3] => din_reg[3].IN1
din[4] => din_reg[4].IN1
din[5] => din_reg[5].IN1
din[6] => din_reg[6].IN1
din[7] => din_reg[7].IN1
din[8] => din_reg[8].IN1
din[9] => din_reg[9].IN1
din[10] => din_reg[10].IN1
din[11] => din_reg[11].IN1
din[12] => din_reg[12].IN1
din[13] => din_reg[13].IN1
din[14] => din_reg[14].IN1
din[15] => din_reg[15].IN1
din[16] => din_reg[16].IN1
din[17] => din_reg[17].IN1
din[18] => din_reg[18].IN1
din[19] => din_reg[19].IN1
din[20] => din_reg[20].IN1
din[21] => din_reg[21].IN1
din[22] => din_reg[22].IN1
din[23] => din_reg[23].IN1
din[24] => din_reg[24].IN1
din[25] => din_reg[25].IN1
din[26] => din_reg[26].IN1
din[27] => din_reg[27].IN1
din[28] => din_reg[28].IN1
din[29] => din_reg[29].IN1
din[30] => din_reg[30].IN1
din[31] => din_reg[31].IN1
din[32] => din_reg[32].IN1
din[33] => din_reg[33].IN1
din[34] => din_reg[34].IN1
din[35] => din_reg[35].IN1
din[36] => din_reg[36].IN1
din[37] => din_reg[37].IN1
din[38] => din_reg[38].IN1
din[39] => din_reg[39].IN1
rclk => rclk.IN4
rclk_ena => rclk_ena.IN1
rden => rden.IN1
dout[0] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[1] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[2] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[3] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[4] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[5] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[6] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[7] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[8] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[9] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[10] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[11] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[12] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[13] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[14] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[15] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[16] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[17] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[18] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[19] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[20] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[21] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[22] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[23] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[24] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[25] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[26] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[27] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[28] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[29] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[30] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[31] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[32] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[33] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[34] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[35] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[36] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[37] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[38] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[39] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
section[0] => LessThan4.IN11
section[0] => Equal5.IN10
section[1] => LessThan4.IN10
section[1] => Equal5.IN9
section[2] => LessThan4.IN9
section[2] => Equal5.IN8
section[3] => LessThan4.IN8
section[3] => Equal5.IN7
section[4] => LessThan4.IN7
section[4] => Equal5.IN6
section[5] => LessThan4.IN6
section[5] => Equal5.IN5
section[6] => LessThan4.IN5
section[6] => Equal5.IN4
section[7] => LessThan4.IN4
section[7] => Equal5.IN3
section[8] => LessThan4.IN3
section[8] => Equal5.IN2
section[9] => LessThan4.IN2
section[9] => Equal5.IN1
section[10] => LessThan4.IN1
section[10] => Equal5.IN0
sect_e[0] => LessThan2.IN11
sect_e[0] => Equal1.IN10
sect_e[1] => LessThan2.IN10
sect_e[1] => Equal1.IN9
sect_e[2] => LessThan2.IN9
sect_e[2] => Equal1.IN8
sect_e[3] => LessThan2.IN8
sect_e[3] => Equal1.IN7
sect_e[4] => LessThan2.IN7
sect_e[4] => Equal1.IN6
sect_e[5] => LessThan2.IN6
sect_e[5] => Equal1.IN5
sect_e[6] => LessThan2.IN5
sect_e[6] => Equal1.IN4
sect_e[7] => LessThan2.IN4
sect_e[7] => Equal1.IN3
sect_e[8] => LessThan2.IN3
sect_e[8] => Equal1.IN2
sect_e[9] => LessThan2.IN2
sect_e[9] => Equal1.IN1
sect_e[10] => LessThan2.IN1
sect_e[10] => Equal1.IN0
af_level[0] => af_level[0].IN1
af_level[1] => af_level[1].IN1
af_level[2] => af_level[2].IN1
af_level[3] => af_level[3].IN1
af_level[4] => af_level[4].IN1
af_level[5] => af_level[5].IN1
af_level[6] => af_level[6].IN1
af_level[7] => af_level[7].IN1
af_level[8] => af_level[8].IN1
af_level[9] => af_level[9].IN1
af_level[10] => af_level[10].IN1
ae_level[0] => ae_level[0].IN1
ae_level[1] => ae_level[1].IN1
ae_level[2] => ae_level[2].IN1
ae_level[3] => ae_level[3].IN1
ae_level[4] => ae_level[4].IN1
ae_level[5] => ae_level[5].IN1
ae_level[6] => ae_level[6].IN1
ae_level[7] => ae_level[7].IN1
ae_level[8] => ae_level[8].IN1
ae_level[9] => ae_level[9].IN1
ae_level[10] => ae_level[10].IN1
sav <= sav_flag.DB_MAX_OUTPUT_PORT_TYPE
septy <= septy_flag.DB_MAX_OUTPUT_PORT_TYPE
afull <= afull_flag.DB_MAX_OUTPUT_PORT_TYPE
full <= full_flag.DB_MAX_OUTPUT_PORT_TYPE
aempty <= aempty_flag.DB_MAX_OUTPUT_PORT_TYPE
empty <= empty_flag.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM
data[0] => data[0].IN1
data[1] => data[1].IN1
data[2] => data[2].IN1
data[3] => data[3].IN1
data[4] => data[4].IN1
data[5] => data[5].IN1
data[6] => data[6].IN1
data[7] => data[7].IN1
data[8] => data[8].IN1
data[9] => data[9].IN1
data[10] => data[10].IN1
data[11] => data[11].IN1
data[12] => data[12].IN1
data[13] => data[13].IN1
data[14] => data[14].IN1
data[15] => data[15].IN1
data[16] => data[16].IN1
data[17] => data[17].IN1
data[18] => data[18].IN1
data[19] => data[19].IN1
data[20] => data[20].IN1
data[21] => data[21].IN1
data[22] => data[22].IN1
data[23] => data[23].IN1
data[24] => data[24].IN1
data[25] => data[25].IN1
data[26] => data[26].IN1
data[27] => data[27].IN1
data[28] => data[28].IN1
data[29] => data[29].IN1
data[30] => data[30].IN1
data[31] => data[31].IN1
data[32] => data[32].IN1
data[33] => data[33].IN1
data[34] => data[34].IN1
data[35] => data[35].IN1
data[36] => data[36].IN1
data[37] => data[37].IN1
data[38] => data[38].IN1
data[39] => data[39].IN1
rdaddress[0] => rdaddress[0].IN1
rdaddress[1] => rdaddress[1].IN1
rdaddress[2] => rdaddress[2].IN1
rdaddress[3] => rdaddress[3].IN1
rdaddress[4] => rdaddress[4].IN1
rdaddress[5] => rdaddress[5].IN1
rdaddress[6] => rdaddress[6].IN1
rdaddress[7] => rdaddress[7].IN1
rdaddress[8] => rdaddress[8].IN1
rdaddress[9] => rdaddress[9].IN1
rdaddress[10] => rdaddress[10].IN1
rdclock => rdclock.IN1
wraddress[0] => wraddress[0].IN1
wraddress[1] => wraddress[1].IN1
wraddress[2] => wraddress[2].IN1
wraddress[3] => wraddress[3].IN1
wraddress[4] => wraddress[4].IN1
wraddress[5] => wraddress[5].IN1
wraddress[6] => wraddress[6].IN1
wraddress[7] => wraddress[7].IN1
wraddress[8] => wraddress[8].IN1
wraddress[9] => wraddress[9].IN1
wraddress[10] => wraddress[10].IN1
wrclock => wrclock.IN1
wren => wren.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b
q[4] <= altsyncram:altsyncram_component.q_b
q[5] <= altsyncram:altsyncram_component.q_b
q[6] <= altsyncram:altsyncram_component.q_b
q[7] <= altsyncram:altsyncram_component.q_b
q[8] <= altsyncram:altsyncram_component.q_b
q[9] <= altsyncram:altsyncram_component.q_b
q[10] <= altsyncram:altsyncram_component.q_b
q[11] <= altsyncram:altsyncram_component.q_b
q[12] <= altsyncram:altsyncram_component.q_b
q[13] <= altsyncram:altsyncram_component.q_b
q[14] <= altsyncram:altsyncram_component.q_b
q[15] <= altsyncram:altsyncram_component.q_b
q[16] <= altsyncram:altsyncram_component.q_b
q[17] <= altsyncram:altsyncram_component.q_b
q[18] <= altsyncram:altsyncram_component.q_b
q[19] <= altsyncram:altsyncram_component.q_b
q[20] <= altsyncram:altsyncram_component.q_b
q[21] <= altsyncram:altsyncram_component.q_b
q[22] <= altsyncram:altsyncram_component.q_b
q[23] <= altsyncram:altsyncram_component.q_b
q[24] <= altsyncram:altsyncram_component.q_b
q[25] <= altsyncram:altsyncram_component.q_b
q[26] <= altsyncram:altsyncram_component.q_b
q[27] <= altsyncram:altsyncram_component.q_b
q[28] <= altsyncram:altsyncram_component.q_b
q[29] <= altsyncram:altsyncram_component.q_b
q[30] <= altsyncram:altsyncram_component.q_b
q[31] <= altsyncram:altsyncram_component.q_b
q[32] <= altsyncram:altsyncram_component.q_b
q[33] <= altsyncram:altsyncram_component.q_b
q[34] <= altsyncram:altsyncram_component.q_b
q[35] <= altsyncram:altsyncram_component.q_b
q[36] <= altsyncram:altsyncram_component.q_b
q[37] <= altsyncram:altsyncram_component.q_b
q[38] <= altsyncram:altsyncram_component.q_b
q[39] <= altsyncram:altsyncram_component.q_b


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component
wren_a => altsyncram_cfg1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_cfg1:auto_generated.data_a[0]
data_a[1] => altsyncram_cfg1:auto_generated.data_a[1]
data_a[2] => altsyncram_cfg1:auto_generated.data_a[2]
data_a[3] => altsyncram_cfg1:auto_generated.data_a[3]
data_a[4] => altsyncram_cfg1:auto_generated.data_a[4]
data_a[5] => altsyncram_cfg1:auto_generated.data_a[5]
data_a[6] => altsyncram_cfg1:auto_generated.data_a[6]
data_a[7] => altsyncram_cfg1:auto_generated.data_a[7]
data_a[8] => altsyncram_cfg1:auto_generated.data_a[8]
data_a[9] => altsyncram_cfg1:auto_generated.data_a[9]
data_a[10] => altsyncram_cfg1:auto_generated.data_a[10]
data_a[11] => altsyncram_cfg1:auto_generated.data_a[11]
data_a[12] => altsyncram_cfg1:auto_generated.data_a[12]
data_a[13] => altsyncram_cfg1:auto_generated.data_a[13]
data_a[14] => altsyncram_cfg1:auto_generated.data_a[14]
data_a[15] => altsyncram_cfg1:auto_generated.data_a[15]
data_a[16] => altsyncram_cfg1:auto_generated.data_a[16]
data_a[17] => altsyncram_cfg1:auto_generated.data_a[17]
data_a[18] => altsyncram_cfg1:auto_generated.data_a[18]
data_a[19] => altsyncram_cfg1:auto_generated.data_a[19]
data_a[20] => altsyncram_cfg1:auto_generated.data_a[20]
data_a[21] => altsyncram_cfg1:auto_generated.data_a[21]
data_a[22] => altsyncram_cfg1:auto_generated.data_a[22]
data_a[23] => altsyncram_cfg1:auto_generated.data_a[23]
data_a[24] => altsyncram_cfg1:auto_generated.data_a[24]
data_a[25] => altsyncram_cfg1:auto_generated.data_a[25]
data_a[26] => altsyncram_cfg1:auto_generated.data_a[26]
data_a[27] => altsyncram_cfg1:auto_generated.data_a[27]
data_a[28] => altsyncram_cfg1:auto_generated.data_a[28]
data_a[29] => altsyncram_cfg1:auto_generated.data_a[29]
data_a[30] => altsyncram_cfg1:auto_generated.data_a[30]
data_a[31] => altsyncram_cfg1:auto_generated.data_a[31]
data_a[32] => altsyncram_cfg1:auto_generated.data_a[32]
data_a[33] => altsyncram_cfg1:auto_generated.data_a[33]
data_a[34] => altsyncram_cfg1:auto_generated.data_a[34]
data_a[35] => altsyncram_cfg1:auto_generated.data_a[35]
data_a[36] => altsyncram_cfg1:auto_generated.data_a[36]
data_a[37] => altsyncram_cfg1:auto_generated.data_a[37]
data_a[38] => altsyncram_cfg1:auto_generated.data_a[38]
data_a[39] => altsyncram_cfg1:auto_generated.data_a[39]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
data_b[8] => ~NO_FANOUT~
data_b[9] => ~NO_FANOUT~
data_b[10] => ~NO_FANOUT~
data_b[11] => ~NO_FANOUT~
data_b[12] => ~NO_FANOUT~
data_b[13] => ~NO_FANOUT~
data_b[14] => ~NO_FANOUT~
data_b[15] => ~NO_FANOUT~
data_b[16] => ~NO_FANOUT~
data_b[17] => ~NO_FANOUT~
data_b[18] => ~NO_FANOUT~
data_b[19] => ~NO_FANOUT~
data_b[20] => ~NO_FANOUT~
data_b[21] => ~NO_FANOUT~
data_b[22] => ~NO_FANOUT~
data_b[23] => ~NO_FANOUT~
data_b[24] => ~NO_FANOUT~
data_b[25] => ~NO_FANOUT~
data_b[26] => ~NO_FANOUT~
data_b[27] => ~NO_FANOUT~
data_b[28] => ~NO_FANOUT~
data_b[29] => ~NO_FANOUT~
data_b[30] => ~NO_FANOUT~
data_b[31] => ~NO_FANOUT~
data_b[32] => ~NO_FANOUT~
data_b[33] => ~NO_FANOUT~
data_b[34] => ~NO_FANOUT~
data_b[35] => ~NO_FANOUT~
data_b[36] => ~NO_FANOUT~
data_b[37] => ~NO_FANOUT~
data_b[38] => ~NO_FANOUT~
data_b[39] => ~NO_FANOUT~
address_a[0] => altsyncram_cfg1:auto_generated.address_a[0]
address_a[1] => altsyncram_cfg1:auto_generated.address_a[1]
address_a[2] => altsyncram_cfg1:auto_generated.address_a[2]
address_a[3] => altsyncram_cfg1:auto_generated.address_a[3]
address_a[4] => altsyncram_cfg1:auto_generated.address_a[4]
address_a[5] => altsyncram_cfg1:auto_generated.address_a[5]
address_a[6] => altsyncram_cfg1:auto_generated.address_a[6]
address_a[7] => altsyncram_cfg1:auto_generated.address_a[7]
address_a[8] => altsyncram_cfg1:auto_generated.address_a[8]
address_a[9] => altsyncram_cfg1:auto_generated.address_a[9]
address_a[10] => altsyncram_cfg1:auto_generated.address_a[10]
address_b[0] => altsyncram_cfg1:auto_generated.address_b[0]
address_b[1] => altsyncram_cfg1:auto_generated.address_b[1]
address_b[2] => altsyncram_cfg1:auto_generated.address_b[2]
address_b[3] => altsyncram_cfg1:auto_generated.address_b[3]
address_b[4] => altsyncram_cfg1:auto_generated.address_b[4]
address_b[5] => altsyncram_cfg1:auto_generated.address_b[5]
address_b[6] => altsyncram_cfg1:auto_generated.address_b[6]
address_b[7] => altsyncram_cfg1:auto_generated.address_b[7]
address_b[8] => altsyncram_cfg1:auto_generated.address_b[8]
address_b[9] => altsyncram_cfg1:auto_generated.address_b[9]
address_b[10] => altsyncram_cfg1:auto_generated.address_b[10]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_cfg1:auto_generated.clock0
clock1 => altsyncram_cfg1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_a[8] <= <GND>
q_a[9] <= <GND>
q_a[10] <= <GND>
q_a[11] <= <GND>
q_a[12] <= <GND>
q_a[13] <= <GND>
q_a[14] <= <GND>
q_a[15] <= <GND>
q_a[16] <= <GND>
q_a[17] <= <GND>
q_a[18] <= <GND>
q_a[19] <= <GND>
q_a[20] <= <GND>
q_a[21] <= <GND>
q_a[22] <= <GND>
q_a[23] <= <GND>
q_a[24] <= <GND>
q_a[25] <= <GND>
q_a[26] <= <GND>
q_a[27] <= <GND>
q_a[28] <= <GND>
q_a[29] <= <GND>
q_a[30] <= <GND>
q_a[31] <= <GND>
q_a[32] <= <GND>
q_a[33] <= <GND>
q_a[34] <= <GND>
q_a[35] <= <GND>
q_a[36] <= <GND>
q_a[37] <= <GND>
q_a[38] <= <GND>
q_a[39] <= <GND>
q_b[0] <= altsyncram_cfg1:auto_generated.q_b[0]
q_b[1] <= altsyncram_cfg1:auto_generated.q_b[1]
q_b[2] <= altsyncram_cfg1:auto_generated.q_b[2]
q_b[3] <= altsyncram_cfg1:auto_generated.q_b[3]
q_b[4] <= altsyncram_cfg1:auto_generated.q_b[4]
q_b[5] <= altsyncram_cfg1:auto_generated.q_b[5]
q_b[6] <= altsyncram_cfg1:auto_generated.q_b[6]
q_b[7] <= altsyncram_cfg1:auto_generated.q_b[7]
q_b[8] <= altsyncram_cfg1:auto_generated.q_b[8]
q_b[9] <= altsyncram_cfg1:auto_generated.q_b[9]
q_b[10] <= altsyncram_cfg1:auto_generated.q_b[10]
q_b[11] <= altsyncram_cfg1:auto_generated.q_b[11]
q_b[12] <= altsyncram_cfg1:auto_generated.q_b[12]
q_b[13] <= altsyncram_cfg1:auto_generated.q_b[13]
q_b[14] <= altsyncram_cfg1:auto_generated.q_b[14]
q_b[15] <= altsyncram_cfg1:auto_generated.q_b[15]
q_b[16] <= altsyncram_cfg1:auto_generated.q_b[16]
q_b[17] <= altsyncram_cfg1:auto_generated.q_b[17]
q_b[18] <= altsyncram_cfg1:auto_generated.q_b[18]
q_b[19] <= altsyncram_cfg1:auto_generated.q_b[19]
q_b[20] <= altsyncram_cfg1:auto_generated.q_b[20]
q_b[21] <= altsyncram_cfg1:auto_generated.q_b[21]
q_b[22] <= altsyncram_cfg1:auto_generated.q_b[22]
q_b[23] <= altsyncram_cfg1:auto_generated.q_b[23]
q_b[24] <= altsyncram_cfg1:auto_generated.q_b[24]
q_b[25] <= altsyncram_cfg1:auto_generated.q_b[25]
q_b[26] <= altsyncram_cfg1:auto_generated.q_b[26]
q_b[27] <= altsyncram_cfg1:auto_generated.q_b[27]
q_b[28] <= altsyncram_cfg1:auto_generated.q_b[28]
q_b[29] <= altsyncram_cfg1:auto_generated.q_b[29]
q_b[30] <= altsyncram_cfg1:auto_generated.q_b[30]
q_b[31] <= altsyncram_cfg1:auto_generated.q_b[31]
q_b[32] <= altsyncram_cfg1:auto_generated.q_b[32]
q_b[33] <= altsyncram_cfg1:auto_generated.q_b[33]
q_b[34] <= altsyncram_cfg1:auto_generated.q_b[34]
q_b[35] <= altsyncram_cfg1:auto_generated.q_b[35]
q_b[36] <= altsyncram_cfg1:auto_generated.q_b[36]
q_b[37] <= altsyncram_cfg1:auto_generated.q_b[37]
q_b[38] <= altsyncram_cfg1:auto_generated.q_b[38]
q_b[39] <= altsyncram_cfg1:auto_generated.q_b[39]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[0] => ram_block1a32.PORTAADDR
address_a[0] => ram_block1a33.PORTAADDR
address_a[0] => ram_block1a34.PORTAADDR
address_a[0] => ram_block1a35.PORTAADDR
address_a[0] => ram_block1a36.PORTAADDR
address_a[0] => ram_block1a37.PORTAADDR
address_a[0] => ram_block1a38.PORTAADDR
address_a[0] => ram_block1a39.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[1] => ram_block1a32.PORTAADDR1
address_a[1] => ram_block1a33.PORTAADDR1
address_a[1] => ram_block1a34.PORTAADDR1
address_a[1] => ram_block1a35.PORTAADDR1
address_a[1] => ram_block1a36.PORTAADDR1
address_a[1] => ram_block1a37.PORTAADDR1
address_a[1] => ram_block1a38.PORTAADDR1
address_a[1] => ram_block1a39.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[2] => ram_block1a32.PORTAADDR2
address_a[2] => ram_block1a33.PORTAADDR2
address_a[2] => ram_block1a34.PORTAADDR2
address_a[2] => ram_block1a35.PORTAADDR2
address_a[2] => ram_block1a36.PORTAADDR2
address_a[2] => ram_block1a37.PORTAADDR2
address_a[2] => ram_block1a38.PORTAADDR2
address_a[2] => ram_block1a39.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[3] => ram_block1a32.PORTAADDR3
address_a[3] => ram_block1a33.PORTAADDR3
address_a[3] => ram_block1a34.PORTAADDR3
address_a[3] => ram_block1a35.PORTAADDR3
address_a[3] => ram_block1a36.PORTAADDR3
address_a[3] => ram_block1a37.PORTAADDR3
address_a[3] => ram_block1a38.PORTAADDR3
address_a[3] => ram_block1a39.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_a[4] => ram_block1a32.PORTAADDR4
address_a[4] => ram_block1a33.PORTAADDR4
address_a[4] => ram_block1a34.PORTAADDR4
address_a[4] => ram_block1a35.PORTAADDR4
address_a[4] => ram_block1a36.PORTAADDR4
address_a[4] => ram_block1a37.PORTAADDR4
address_a[4] => ram_block1a38.PORTAADDR4
address_a[4] => ram_block1a39.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_a[5] => ram_block1a24.PORTAADDR5
address_a[5] => ram_block1a25.PORTAADDR5
address_a[5] => ram_block1a26.PORTAADDR5
address_a[5] => ram_block1a27.PORTAADDR5
address_a[5] => ram_block1a28.PORTAADDR5
address_a[5] => ram_block1a29.PORTAADDR5
address_a[5] => ram_block1a30.PORTAADDR5
address_a[5] => ram_block1a31.PORTAADDR5
address_a[5] => ram_block1a32.PORTAADDR5
address_a[5] => ram_block1a33.PORTAADDR5
address_a[5] => ram_block1a34.PORTAADDR5
address_a[5] => ram_block1a35.PORTAADDR5
address_a[5] => ram_block1a36.PORTAADDR5
address_a[5] => ram_block1a37.PORTAADDR5
address_a[5] => ram_block1a38.PORTAADDR5
address_a[5] => ram_block1a39.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[6] => ram_block1a26.PORTAADDR6
address_a[6] => ram_block1a27.PORTAADDR6
address_a[6] => ram_block1a28.PORTAADDR6
address_a[6] => ram_block1a29.PORTAADDR6
address_a[6] => ram_block1a30.PORTAADDR6
address_a[6] => ram_block1a31.PORTAADDR6
address_a[6] => ram_block1a32.PORTAADDR6
address_a[6] => ram_block1a33.PORTAADDR6
address_a[6] => ram_block1a34.PORTAADDR6
address_a[6] => ram_block1a35.PORTAADDR6
address_a[6] => ram_block1a36.PORTAADDR6
address_a[6] => ram_block1a37.PORTAADDR6
address_a[6] => ram_block1a38.PORTAADDR6
address_a[6] => ram_block1a39.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[7] => ram_block1a16.PORTAADDR7
address_a[7] => ram_block1a17.PORTAADDR7
address_a[7] => ram_block1a18.PORTAADDR7
address_a[7] => ram_block1a19.PORTAADDR7
address_a[7] => ram_block1a20.PORTAADDR7
address_a[7] => ram_block1a21.PORTAADDR7
address_a[7] => ram_block1a22.PORTAADDR7
address_a[7] => ram_block1a23.PORTAADDR7
address_a[7] => ram_block1a24.PORTAADDR7
address_a[7] => ram_block1a25.PORTAADDR7
address_a[7] => ram_block1a26.PORTAADDR7
address_a[7] => ram_block1a27.PORTAADDR7
address_a[7] => ram_block1a28.PORTAADDR7
address_a[7] => ram_block1a29.PORTAADDR7
address_a[7] => ram_block1a30.PORTAADDR7
address_a[7] => ram_block1a31.PORTAADDR7
address_a[7] => ram_block1a32.PORTAADDR7
address_a[7] => ram_block1a33.PORTAADDR7
address_a[7] => ram_block1a34.PORTAADDR7
address_a[7] => ram_block1a35.PORTAADDR7
address_a[7] => ram_block1a36.PORTAADDR7
address_a[7] => ram_block1a37.PORTAADDR7
address_a[7] => ram_block1a38.PORTAADDR7
address_a[7] => ram_block1a39.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[8] => ram_block1a16.PORTAADDR8
address_a[8] => ram_block1a17.PORTAADDR8
address_a[8] => ram_block1a18.PORTAADDR8
address_a[8] => ram_block1a19.PORTAADDR8
address_a[8] => ram_block1a20.PORTAADDR8
address_a[8] => ram_block1a21.PORTAADDR8
address_a[8] => ram_block1a22.PORTAADDR8
address_a[8] => ram_block1a23.PORTAADDR8
address_a[8] => ram_block1a24.PORTAADDR8
address_a[8] => ram_block1a25.PORTAADDR8
address_a[8] => ram_block1a26.PORTAADDR8
address_a[8] => ram_block1a27.PORTAADDR8
address_a[8] => ram_block1a28.PORTAADDR8
address_a[8] => ram_block1a29.PORTAADDR8
address_a[8] => ram_block1a30.PORTAADDR8
address_a[8] => ram_block1a31.PORTAADDR8
address_a[8] => ram_block1a32.PORTAADDR8
address_a[8] => ram_block1a33.PORTAADDR8
address_a[8] => ram_block1a34.PORTAADDR8
address_a[8] => ram_block1a35.PORTAADDR8
address_a[8] => ram_block1a36.PORTAADDR8
address_a[8] => ram_block1a37.PORTAADDR8
address_a[8] => ram_block1a38.PORTAADDR8
address_a[8] => ram_block1a39.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[9] => ram_block1a16.PORTAADDR9
address_a[9] => ram_block1a17.PORTAADDR9
address_a[9] => ram_block1a18.PORTAADDR9
address_a[9] => ram_block1a19.PORTAADDR9
address_a[9] => ram_block1a20.PORTAADDR9
address_a[9] => ram_block1a21.PORTAADDR9
address_a[9] => ram_block1a22.PORTAADDR9
address_a[9] => ram_block1a23.PORTAADDR9
address_a[9] => ram_block1a24.PORTAADDR9
address_a[9] => ram_block1a25.PORTAADDR9
address_a[9] => ram_block1a26.PORTAADDR9
address_a[9] => ram_block1a27.PORTAADDR9
address_a[9] => ram_block1a28.PORTAADDR9
address_a[9] => ram_block1a29.PORTAADDR9
address_a[9] => ram_block1a30.PORTAADDR9
address_a[9] => ram_block1a31.PORTAADDR9
address_a[9] => ram_block1a32.PORTAADDR9
address_a[9] => ram_block1a33.PORTAADDR9
address_a[9] => ram_block1a34.PORTAADDR9
address_a[9] => ram_block1a35.PORTAADDR9
address_a[9] => ram_block1a36.PORTAADDR9
address_a[9] => ram_block1a37.PORTAADDR9
address_a[9] => ram_block1a38.PORTAADDR9
address_a[9] => ram_block1a39.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[10] => ram_block1a16.PORTAADDR10
address_a[10] => ram_block1a17.PORTAADDR10
address_a[10] => ram_block1a18.PORTAADDR10
address_a[10] => ram_block1a19.PORTAADDR10
address_a[10] => ram_block1a20.PORTAADDR10
address_a[10] => ram_block1a21.PORTAADDR10
address_a[10] => ram_block1a22.PORTAADDR10
address_a[10] => ram_block1a23.PORTAADDR10
address_a[10] => ram_block1a24.PORTAADDR10
address_a[10] => ram_block1a25.PORTAADDR10
address_a[10] => ram_block1a26.PORTAADDR10
address_a[10] => ram_block1a27.PORTAADDR10
address_a[10] => ram_block1a28.PORTAADDR10
address_a[10] => ram_block1a29.PORTAADDR10
address_a[10] => ram_block1a30.PORTAADDR10
address_a[10] => ram_block1a31.PORTAADDR10
address_a[10] => ram_block1a32.PORTAADDR10
address_a[10] => ram_block1a33.PORTAADDR10
address_a[10] => ram_block1a34.PORTAADDR10
address_a[10] => ram_block1a35.PORTAADDR10
address_a[10] => ram_block1a36.PORTAADDR10
address_a[10] => ram_block1a37.PORTAADDR10
address_a[10] => ram_block1a38.PORTAADDR10
address_a[10] => ram_block1a39.PORTAADDR10
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[0] => ram_block1a16.PORTBADDR
address_b[0] => ram_block1a17.PORTBADDR
address_b[0] => ram_block1a18.PORTBADDR
address_b[0] => ram_block1a19.PORTBADDR
address_b[0] => ram_block1a20.PORTBADDR
address_b[0] => ram_block1a21.PORTBADDR
address_b[0] => ram_block1a22.PORTBADDR
address_b[0] => ram_block1a23.PORTBADDR
address_b[0] => ram_block1a24.PORTBADDR
address_b[0] => ram_block1a25.PORTBADDR
address_b[0] => ram_block1a26.PORTBADDR
address_b[0] => ram_block1a27.PORTBADDR
address_b[0] => ram_block1a28.PORTBADDR
address_b[0] => ram_block1a29.PORTBADDR
address_b[0] => ram_block1a30.PORTBADDR
address_b[0] => ram_block1a31.PORTBADDR
address_b[0] => ram_block1a32.PORTBADDR
address_b[0] => ram_block1a33.PORTBADDR
address_b[0] => ram_block1a34.PORTBADDR
address_b[0] => ram_block1a35.PORTBADDR
address_b[0] => ram_block1a36.PORTBADDR
address_b[0] => ram_block1a37.PORTBADDR
address_b[0] => ram_block1a38.PORTBADDR
address_b[0] => ram_block1a39.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[1] => ram_block1a16.PORTBADDR1
address_b[1] => ram_block1a17.PORTBADDR1
address_b[1] => ram_block1a18.PORTBADDR1
address_b[1] => ram_block1a19.PORTBADDR1
address_b[1] => ram_block1a20.PORTBADDR1
address_b[1] => ram_block1a21.PORTBADDR1
address_b[1] => ram_block1a22.PORTBADDR1
address_b[1] => ram_block1a23.PORTBADDR1
address_b[1] => ram_block1a24.PORTBADDR1
address_b[1] => ram_block1a25.PORTBADDR1
address_b[1] => ram_block1a26.PORTBADDR1
address_b[1] => ram_block1a27.PORTBADDR1
address_b[1] => ram_block1a28.PORTBADDR1
address_b[1] => ram_block1a29.PORTBADDR1
address_b[1] => ram_block1a30.PORTBADDR1
address_b[1] => ram_block1a31.PORTBADDR1
address_b[1] => ram_block1a32.PORTBADDR1
address_b[1] => ram_block1a33.PORTBADDR1
address_b[1] => ram_block1a34.PORTBADDR1
address_b[1] => ram_block1a35.PORTBADDR1
address_b[1] => ram_block1a36.PORTBADDR1
address_b[1] => ram_block1a37.PORTBADDR1
address_b[1] => ram_block1a38.PORTBADDR1
address_b[1] => ram_block1a39.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
address_b[2] => ram_block1a16.PORTBADDR2
address_b[2] => ram_block1a17.PORTBADDR2
address_b[2] => ram_block1a18.PORTBADDR2
address_b[2] => ram_block1a19.PORTBADDR2
address_b[2] => ram_block1a20.PORTBADDR2
address_b[2] => ram_block1a21.PORTBADDR2
address_b[2] => ram_block1a22.PORTBADDR2
address_b[2] => ram_block1a23.PORTBADDR2
address_b[2] => ram_block1a24.PORTBADDR2
address_b[2] => ram_block1a25.PORTBADDR2
address_b[2] => ram_block1a26.PORTBADDR2
address_b[2] => ram_block1a27.PORTBADDR2
address_b[2] => ram_block1a28.PORTBADDR2
address_b[2] => ram_block1a29.PORTBADDR2
address_b[2] => ram_block1a30.PORTBADDR2
address_b[2] => ram_block1a31.PORTBADDR2
address_b[2] => ram_block1a32.PORTBADDR2
address_b[2] => ram_block1a33.PORTBADDR2
address_b[2] => ram_block1a34.PORTBADDR2
address_b[2] => ram_block1a35.PORTBADDR2
address_b[2] => ram_block1a36.PORTBADDR2
address_b[2] => ram_block1a37.PORTBADDR2
address_b[2] => ram_block1a38.PORTBADDR2
address_b[2] => ram_block1a39.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[3] => ram_block1a8.PORTBADDR3
address_b[3] => ram_block1a9.PORTBADDR3
address_b[3] => ram_block1a10.PORTBADDR3
address_b[3] => ram_block1a11.PORTBADDR3
address_b[3] => ram_block1a12.PORTBADDR3
address_b[3] => ram_block1a13.PORTBADDR3
address_b[3] => ram_block1a14.PORTBADDR3
address_b[3] => ram_block1a15.PORTBADDR3
address_b[3] => ram_block1a16.PORTBADDR3
address_b[3] => ram_block1a17.PORTBADDR3
address_b[3] => ram_block1a18.PORTBADDR3
address_b[3] => ram_block1a19.PORTBADDR3
address_b[3] => ram_block1a20.PORTBADDR3
address_b[3] => ram_block1a21.PORTBADDR3
address_b[3] => ram_block1a22.PORTBADDR3
address_b[3] => ram_block1a23.PORTBADDR3
address_b[3] => ram_block1a24.PORTBADDR3
address_b[3] => ram_block1a25.PORTBADDR3
address_b[3] => ram_block1a26.PORTBADDR3
address_b[3] => ram_block1a27.PORTBADDR3
address_b[3] => ram_block1a28.PORTBADDR3
address_b[3] => ram_block1a29.PORTBADDR3
address_b[3] => ram_block1a30.PORTBADDR3
address_b[3] => ram_block1a31.PORTBADDR3
address_b[3] => ram_block1a32.PORTBADDR3
address_b[3] => ram_block1a33.PORTBADDR3
address_b[3] => ram_block1a34.PORTBADDR3
address_b[3] => ram_block1a35.PORTBADDR3
address_b[3] => ram_block1a36.PORTBADDR3
address_b[3] => ram_block1a37.PORTBADDR3
address_b[3] => ram_block1a38.PORTBADDR3
address_b[3] => ram_block1a39.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[4] => ram_block1a8.PORTBADDR4
address_b[4] => ram_block1a9.PORTBADDR4
address_b[4] => ram_block1a10.PORTBADDR4
address_b[4] => ram_block1a11.PORTBADDR4
address_b[4] => ram_block1a12.PORTBADDR4
address_b[4] => ram_block1a13.PORTBADDR4
address_b[4] => ram_block1a14.PORTBADDR4
address_b[4] => ram_block1a15.PORTBADDR4
address_b[4] => ram_block1a16.PORTBADDR4
address_b[4] => ram_block1a17.PORTBADDR4
address_b[4] => ram_block1a18.PORTBADDR4
address_b[4] => ram_block1a19.PORTBADDR4
address_b[4] => ram_block1a20.PORTBADDR4
address_b[4] => ram_block1a21.PORTBADDR4
address_b[4] => ram_block1a22.PORTBADDR4
address_b[4] => ram_block1a23.PORTBADDR4
address_b[4] => ram_block1a24.PORTBADDR4
address_b[4] => ram_block1a25.PORTBADDR4
address_b[4] => ram_block1a26.PORTBADDR4
address_b[4] => ram_block1a27.PORTBADDR4
address_b[4] => ram_block1a28.PORTBADDR4
address_b[4] => ram_block1a29.PORTBADDR4
address_b[4] => ram_block1a30.PORTBADDR4
address_b[4] => ram_block1a31.PORTBADDR4
address_b[4] => ram_block1a32.PORTBADDR4
address_b[4] => ram_block1a33.PORTBADDR4
address_b[4] => ram_block1a34.PORTBADDR4
address_b[4] => ram_block1a35.PORTBADDR4
address_b[4] => ram_block1a36.PORTBADDR4
address_b[4] => ram_block1a37.PORTBADDR4
address_b[4] => ram_block1a38.PORTBADDR4
address_b[4] => ram_block1a39.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[5] => ram_block1a8.PORTBADDR5
address_b[5] => ram_block1a9.PORTBADDR5
address_b[5] => ram_block1a10.PORTBADDR5
address_b[5] => ram_block1a11.PORTBADDR5
address_b[5] => ram_block1a12.PORTBADDR5
address_b[5] => ram_block1a13.PORTBADDR5
address_b[5] => ram_block1a14.PORTBADDR5
address_b[5] => ram_block1a15.PORTBADDR5
address_b[5] => ram_block1a16.PORTBADDR5
address_b[5] => ram_block1a17.PORTBADDR5
address_b[5] => ram_block1a18.PORTBADDR5
address_b[5] => ram_block1a19.PORTBADDR5
address_b[5] => ram_block1a20.PORTBADDR5
address_b[5] => ram_block1a21.PORTBADDR5
address_b[5] => ram_block1a22.PORTBADDR5
address_b[5] => ram_block1a23.PORTBADDR5
address_b[5] => ram_block1a24.PORTBADDR5
address_b[5] => ram_block1a25.PORTBADDR5
address_b[5] => ram_block1a26.PORTBADDR5
address_b[5] => ram_block1a27.PORTBADDR5
address_b[5] => ram_block1a28.PORTBADDR5
address_b[5] => ram_block1a29.PORTBADDR5
address_b[5] => ram_block1a30.PORTBADDR5
address_b[5] => ram_block1a31.PORTBADDR5
address_b[5] => ram_block1a32.PORTBADDR5
address_b[5] => ram_block1a33.PORTBADDR5
address_b[5] => ram_block1a34.PORTBADDR5
address_b[5] => ram_block1a35.PORTBADDR5
address_b[5] => ram_block1a36.PORTBADDR5
address_b[5] => ram_block1a37.PORTBADDR5
address_b[5] => ram_block1a38.PORTBADDR5
address_b[5] => ram_block1a39.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[6] => ram_block1a8.PORTBADDR6
address_b[6] => ram_block1a9.PORTBADDR6
address_b[6] => ram_block1a10.PORTBADDR6
address_b[6] => ram_block1a11.PORTBADDR6
address_b[6] => ram_block1a12.PORTBADDR6
address_b[6] => ram_block1a13.PORTBADDR6
address_b[6] => ram_block1a14.PORTBADDR6
address_b[6] => ram_block1a15.PORTBADDR6
address_b[6] => ram_block1a16.PORTBADDR6
address_b[6] => ram_block1a17.PORTBADDR6
address_b[6] => ram_block1a18.PORTBADDR6
address_b[6] => ram_block1a19.PORTBADDR6
address_b[6] => ram_block1a20.PORTBADDR6
address_b[6] => ram_block1a21.PORTBADDR6
address_b[6] => ram_block1a22.PORTBADDR6
address_b[6] => ram_block1a23.PORTBADDR6
address_b[6] => ram_block1a24.PORTBADDR6
address_b[6] => ram_block1a25.PORTBADDR6
address_b[6] => ram_block1a26.PORTBADDR6
address_b[6] => ram_block1a27.PORTBADDR6
address_b[6] => ram_block1a28.PORTBADDR6
address_b[6] => ram_block1a29.PORTBADDR6
address_b[6] => ram_block1a30.PORTBADDR6
address_b[6] => ram_block1a31.PORTBADDR6
address_b[6] => ram_block1a32.PORTBADDR6
address_b[6] => ram_block1a33.PORTBADDR6
address_b[6] => ram_block1a34.PORTBADDR6
address_b[6] => ram_block1a35.PORTBADDR6
address_b[6] => ram_block1a36.PORTBADDR6
address_b[6] => ram_block1a37.PORTBADDR6
address_b[6] => ram_block1a38.PORTBADDR6
address_b[6] => ram_block1a39.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[7] => ram_block1a8.PORTBADDR7
address_b[7] => ram_block1a9.PORTBADDR7
address_b[7] => ram_block1a10.PORTBADDR7
address_b[7] => ram_block1a11.PORTBADDR7
address_b[7] => ram_block1a12.PORTBADDR7
address_b[7] => ram_block1a13.PORTBADDR7
address_b[7] => ram_block1a14.PORTBADDR7
address_b[7] => ram_block1a15.PORTBADDR7
address_b[7] => ram_block1a16.PORTBADDR7
address_b[7] => ram_block1a17.PORTBADDR7
address_b[7] => ram_block1a18.PORTBADDR7
address_b[7] => ram_block1a19.PORTBADDR7
address_b[7] => ram_block1a20.PORTBADDR7
address_b[7] => ram_block1a21.PORTBADDR7
address_b[7] => ram_block1a22.PORTBADDR7
address_b[7] => ram_block1a23.PORTBADDR7
address_b[7] => ram_block1a24.PORTBADDR7
address_b[7] => ram_block1a25.PORTBADDR7
address_b[7] => ram_block1a26.PORTBADDR7
address_b[7] => ram_block1a27.PORTBADDR7
address_b[7] => ram_block1a28.PORTBADDR7
address_b[7] => ram_block1a29.PORTBADDR7
address_b[7] => ram_block1a30.PORTBADDR7
address_b[7] => ram_block1a31.PORTBADDR7
address_b[7] => ram_block1a32.PORTBADDR7
address_b[7] => ram_block1a33.PORTBADDR7
address_b[7] => ram_block1a34.PORTBADDR7
address_b[7] => ram_block1a35.PORTBADDR7
address_b[7] => ram_block1a36.PORTBADDR7
address_b[7] => ram_block1a37.PORTBADDR7
address_b[7] => ram_block1a38.PORTBADDR7
address_b[7] => ram_block1a39.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[8] => ram_block1a8.PORTBADDR8
address_b[8] => ram_block1a9.PORTBADDR8
address_b[8] => ram_block1a10.PORTBADDR8
address_b[8] => ram_block1a11.PORTBADDR8
address_b[8] => ram_block1a12.PORTBADDR8
address_b[8] => ram_block1a13.PORTBADDR8
address_b[8] => ram_block1a14.PORTBADDR8
address_b[8] => ram_block1a15.PORTBADDR8
address_b[8] => ram_block1a16.PORTBADDR8
address_b[8] => ram_block1a17.PORTBADDR8
address_b[8] => ram_block1a18.PORTBADDR8
address_b[8] => ram_block1a19.PORTBADDR8
address_b[8] => ram_block1a20.PORTBADDR8
address_b[8] => ram_block1a21.PORTBADDR8
address_b[8] => ram_block1a22.PORTBADDR8
address_b[8] => ram_block1a23.PORTBADDR8
address_b[8] => ram_block1a24.PORTBADDR8
address_b[8] => ram_block1a25.PORTBADDR8
address_b[8] => ram_block1a26.PORTBADDR8
address_b[8] => ram_block1a27.PORTBADDR8
address_b[8] => ram_block1a28.PORTBADDR8
address_b[8] => ram_block1a29.PORTBADDR8
address_b[8] => ram_block1a30.PORTBADDR8
address_b[8] => ram_block1a31.PORTBADDR8
address_b[8] => ram_block1a32.PORTBADDR8
address_b[8] => ram_block1a33.PORTBADDR8
address_b[8] => ram_block1a34.PORTBADDR8
address_b[8] => ram_block1a35.PORTBADDR8
address_b[8] => ram_block1a36.PORTBADDR8
address_b[8] => ram_block1a37.PORTBADDR8
address_b[8] => ram_block1a38.PORTBADDR8
address_b[8] => ram_block1a39.PORTBADDR8
address_b[9] => ram_block1a0.PORTBADDR9
address_b[9] => ram_block1a1.PORTBADDR9
address_b[9] => ram_block1a2.PORTBADDR9
address_b[9] => ram_block1a3.PORTBADDR9
address_b[9] => ram_block1a4.PORTBADDR9
address_b[9] => ram_block1a5.PORTBADDR9
address_b[9] => ram_block1a6.PORTBADDR9
address_b[9] => ram_block1a7.PORTBADDR9
address_b[9] => ram_block1a8.PORTBADDR9
address_b[9] => ram_block1a9.PORTBADDR9
address_b[9] => ram_block1a10.PORTBADDR9
address_b[9] => ram_block1a11.PORTBADDR9
address_b[9] => ram_block1a12.PORTBADDR9
address_b[9] => ram_block1a13.PORTBADDR9
address_b[9] => ram_block1a14.PORTBADDR9
address_b[9] => ram_block1a15.PORTBADDR9
address_b[9] => ram_block1a16.PORTBADDR9
address_b[9] => ram_block1a17.PORTBADDR9
address_b[9] => ram_block1a18.PORTBADDR9
address_b[9] => ram_block1a19.PORTBADDR9
address_b[9] => ram_block1a20.PORTBADDR9
address_b[9] => ram_block1a21.PORTBADDR9
address_b[9] => ram_block1a22.PORTBADDR9
address_b[9] => ram_block1a23.PORTBADDR9
address_b[9] => ram_block1a24.PORTBADDR9
address_b[9] => ram_block1a25.PORTBADDR9
address_b[9] => ram_block1a26.PORTBADDR9
address_b[9] => ram_block1a27.PORTBADDR9
address_b[9] => ram_block1a28.PORTBADDR9
address_b[9] => ram_block1a29.PORTBADDR9
address_b[9] => ram_block1a30.PORTBADDR9
address_b[9] => ram_block1a31.PORTBADDR9
address_b[9] => ram_block1a32.PORTBADDR9
address_b[9] => ram_block1a33.PORTBADDR9
address_b[9] => ram_block1a34.PORTBADDR9
address_b[9] => ram_block1a35.PORTBADDR9
address_b[9] => ram_block1a36.PORTBADDR9
address_b[9] => ram_block1a37.PORTBADDR9
address_b[9] => ram_block1a38.PORTBADDR9
address_b[9] => ram_block1a39.PORTBADDR9
address_b[10] => ram_block1a0.PORTBADDR10
address_b[10] => ram_block1a1.PORTBADDR10
address_b[10] => ram_block1a2.PORTBADDR10
address_b[10] => ram_block1a3.PORTBADDR10
address_b[10] => ram_block1a4.PORTBADDR10
address_b[10] => ram_block1a5.PORTBADDR10
address_b[10] => ram_block1a6.PORTBADDR10
address_b[10] => ram_block1a7.PORTBADDR10
address_b[10] => ram_block1a8.PORTBADDR10
address_b[10] => ram_block1a9.PORTBADDR10
address_b[10] => ram_block1a10.PORTBADDR10
address_b[10] => ram_block1a11.PORTBADDR10
address_b[10] => ram_block1a12.PORTBADDR10
address_b[10] => ram_block1a13.PORTBADDR10
address_b[10] => ram_block1a14.PORTBADDR10
address_b[10] => ram_block1a15.PORTBADDR10
address_b[10] => ram_block1a16.PORTBADDR10
address_b[10] => ram_block1a17.PORTBADDR10
address_b[10] => ram_block1a18.PORTBADDR10
address_b[10] => ram_block1a19.PORTBADDR10
address_b[10] => ram_block1a20.PORTBADDR10
address_b[10] => ram_block1a21.PORTBADDR10
address_b[10] => ram_block1a22.PORTBADDR10
address_b[10] => ram_block1a23.PORTBADDR10
address_b[10] => ram_block1a24.PORTBADDR10
address_b[10] => ram_block1a25.PORTBADDR10
address_b[10] => ram_block1a26.PORTBADDR10
address_b[10] => ram_block1a27.PORTBADDR10
address_b[10] => ram_block1a28.PORTBADDR10
address_b[10] => ram_block1a29.PORTBADDR10
address_b[10] => ram_block1a30.PORTBADDR10
address_b[10] => ram_block1a31.PORTBADDR10
address_b[10] => ram_block1a32.PORTBADDR10
address_b[10] => ram_block1a33.PORTBADDR10
address_b[10] => ram_block1a34.PORTBADDR10
address_b[10] => ram_block1a35.PORTBADDR10
address_b[10] => ram_block1a36.PORTBADDR10
address_b[10] => ram_block1a37.PORTBADDR10
address_b[10] => ram_block1a38.PORTBADDR10
address_b[10] => ram_block1a39.PORTBADDR10
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
clock0 => ram_block1a32.CLK0
clock0 => ram_block1a33.CLK0
clock0 => ram_block1a34.CLK0
clock0 => ram_block1a35.CLK0
clock0 => ram_block1a36.CLK0
clock0 => ram_block1a37.CLK0
clock0 => ram_block1a38.CLK0
clock0 => ram_block1a39.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
clock1 => ram_block1a8.CLK1
clock1 => ram_block1a9.CLK1
clock1 => ram_block1a10.CLK1
clock1 => ram_block1a11.CLK1
clock1 => ram_block1a12.CLK1
clock1 => ram_block1a13.CLK1
clock1 => ram_block1a14.CLK1
clock1 => ram_block1a15.CLK1
clock1 => ram_block1a16.CLK1
clock1 => ram_block1a17.CLK1
clock1 => ram_block1a18.CLK1
clock1 => ram_block1a19.CLK1
clock1 => ram_block1a20.CLK1
clock1 => ram_block1a21.CLK1
clock1 => ram_block1a22.CLK1
clock1 => ram_block1a23.CLK1
clock1 => ram_block1a24.CLK1
clock1 => ram_block1a25.CLK1
clock1 => ram_block1a26.CLK1
clock1 => ram_block1a27.CLK1
clock1 => ram_block1a28.CLK1
clock1 => ram_block1a29.CLK1
clock1 => ram_block1a30.CLK1
clock1 => ram_block1a31.CLK1
clock1 => ram_block1a32.CLK1
clock1 => ram_block1a33.CLK1
clock1 => ram_block1a34.CLK1
clock1 => ram_block1a35.CLK1
clock1 => ram_block1a36.CLK1
clock1 => ram_block1a37.CLK1
clock1 => ram_block1a38.CLK1
clock1 => ram_block1a39.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
data_a[16] => ram_block1a16.PORTADATAIN
data_a[17] => ram_block1a17.PORTADATAIN
data_a[18] => ram_block1a18.PORTADATAIN
data_a[19] => ram_block1a19.PORTADATAIN
data_a[20] => ram_block1a20.PORTADATAIN
data_a[21] => ram_block1a21.PORTADATAIN
data_a[22] => ram_block1a22.PORTADATAIN
data_a[23] => ram_block1a23.PORTADATAIN
data_a[24] => ram_block1a24.PORTADATAIN
data_a[25] => ram_block1a25.PORTADATAIN
data_a[26] => ram_block1a26.PORTADATAIN
data_a[27] => ram_block1a27.PORTADATAIN
data_a[28] => ram_block1a28.PORTADATAIN
data_a[29] => ram_block1a29.PORTADATAIN
data_a[30] => ram_block1a30.PORTADATAIN
data_a[31] => ram_block1a31.PORTADATAIN
data_a[32] => ram_block1a32.PORTADATAIN
data_a[33] => ram_block1a33.PORTADATAIN
data_a[34] => ram_block1a34.PORTADATAIN
data_a[35] => ram_block1a35.PORTADATAIN
data_a[36] => ram_block1a36.PORTADATAIN
data_a[37] => ram_block1a37.PORTADATAIN
data_a[38] => ram_block1a38.PORTADATAIN
data_a[39] => ram_block1a39.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
q_b[8] <= ram_block1a8.PORTBDATAOUT
q_b[9] <= ram_block1a9.PORTBDATAOUT
q_b[10] <= ram_block1a10.PORTBDATAOUT
q_b[11] <= ram_block1a11.PORTBDATAOUT
q_b[12] <= ram_block1a12.PORTBDATAOUT
q_b[13] <= ram_block1a13.PORTBDATAOUT
q_b[14] <= ram_block1a14.PORTBDATAOUT
q_b[15] <= ram_block1a15.PORTBDATAOUT
q_b[16] <= ram_block1a16.PORTBDATAOUT
q_b[17] <= ram_block1a17.PORTBDATAOUT
q_b[18] <= ram_block1a18.PORTBDATAOUT
q_b[19] <= ram_block1a19.PORTBDATAOUT
q_b[20] <= ram_block1a20.PORTBDATAOUT
q_b[21] <= ram_block1a21.PORTBDATAOUT
q_b[22] <= ram_block1a22.PORTBDATAOUT
q_b[23] <= ram_block1a23.PORTBDATAOUT
q_b[24] <= ram_block1a24.PORTBDATAOUT
q_b[25] <= ram_block1a25.PORTBDATAOUT
q_b[26] <= ram_block1a26.PORTBDATAOUT
q_b[27] <= ram_block1a27.PORTBDATAOUT
q_b[28] <= ram_block1a28.PORTBDATAOUT
q_b[29] <= ram_block1a29.PORTBDATAOUT
q_b[30] <= ram_block1a30.PORTBDATAOUT
q_b[31] <= ram_block1a31.PORTBDATAOUT
q_b[32] <= ram_block1a32.PORTBDATAOUT
q_b[33] <= ram_block1a33.PORTBDATAOUT
q_b[34] <= ram_block1a34.PORTBDATAOUT
q_b[35] <= ram_block1a35.PORTBDATAOUT
q_b[36] <= ram_block1a36.PORTBDATAOUT
q_b[37] <= ram_block1a37.PORTBDATAOUT
q_b[38] <= ram_block1a38.PORTBDATAOUT
q_b[39] <= ram_block1a39.PORTBDATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a7.ENA0
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a8.ENA0
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a9.ENA0
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a10.ENA0
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a11.ENA0
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a12.ENA0
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a13.ENA0
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a14.ENA0
wren_a => ram_block1a15.PORTAWE
wren_a => ram_block1a15.ENA0
wren_a => ram_block1a16.PORTAWE
wren_a => ram_block1a16.ENA0
wren_a => ram_block1a17.PORTAWE
wren_a => ram_block1a17.ENA0
wren_a => ram_block1a18.PORTAWE
wren_a => ram_block1a18.ENA0
wren_a => ram_block1a19.PORTAWE
wren_a => ram_block1a19.ENA0
wren_a => ram_block1a20.PORTAWE
wren_a => ram_block1a20.ENA0
wren_a => ram_block1a21.PORTAWE
wren_a => ram_block1a21.ENA0
wren_a => ram_block1a22.PORTAWE
wren_a => ram_block1a22.ENA0
wren_a => ram_block1a23.PORTAWE
wren_a => ram_block1a23.ENA0
wren_a => ram_block1a24.PORTAWE
wren_a => ram_block1a24.ENA0
wren_a => ram_block1a25.PORTAWE
wren_a => ram_block1a25.ENA0
wren_a => ram_block1a26.PORTAWE
wren_a => ram_block1a26.ENA0
wren_a => ram_block1a27.PORTAWE
wren_a => ram_block1a27.ENA0
wren_a => ram_block1a28.PORTAWE
wren_a => ram_block1a28.ENA0
wren_a => ram_block1a29.PORTAWE
wren_a => ram_block1a29.ENA0
wren_a => ram_block1a30.PORTAWE
wren_a => ram_block1a30.ENA0
wren_a => ram_block1a31.PORTAWE
wren_a => ram_block1a31.ENA0
wren_a => ram_block1a32.PORTAWE
wren_a => ram_block1a32.ENA0
wren_a => ram_block1a33.PORTAWE
wren_a => ram_block1a33.ENA0
wren_a => ram_block1a34.PORTAWE
wren_a => ram_block1a34.ENA0
wren_a => ram_block1a35.PORTAWE
wren_a => ram_block1a35.ENA0
wren_a => ram_block1a36.PORTAWE
wren_a => ram_block1a36.ENA0
wren_a => ram_block1a37.PORTAWE
wren_a => ram_block1a37.ENA0
wren_a => ram_block1a38.PORTAWE
wren_a => ram_block1a38.ENA0
wren_a => ram_block1a39.PORTAWE
wren_a => ram_block1a39.ENA0


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT
clk => g_out[0]~reg0.CLK
clk => g_out[1]~reg0.CLK
clk => g_out[2]~reg0.CLK
clk => g_out[3]~reg0.CLK
clk => g_out[4]~reg0.CLK
clk => g_out[5]~reg0.CLK
clk => g_out[6]~reg0.CLK
clk => g_out[7]~reg0.CLK
clk => g_out[8]~reg0.CLK
clk => g_out[9]~reg0.CLK
clk => g_out[10]~reg0.CLK
clk => b_out[0]~reg0.CLK
clk => b_out[1]~reg0.CLK
clk => b_out[2]~reg0.CLK
clk => b_out[3]~reg0.CLK
clk => b_out[4]~reg0.CLK
clk => b_out[5]~reg0.CLK
clk => b_out[6]~reg0.CLK
clk => b_out[7]~reg0.CLK
clk => b_out[8]~reg0.CLK
clk => b_out[9]~reg0.CLK
clk => b_out[10]~reg0.CLK
clk => b_int[0].CLK
clk => b_int[1].CLK
clk => b_int[2].CLK
clk => b_int[3].CLK
clk => b_int[4].CLK
clk => b_int[5].CLK
clk => b_int[6].CLK
clk => b_int[7].CLK
clk => b_int[8].CLK
clk => b_int[9].CLK
clk => b_int[10].CLK
clkena => always1.IN0
reset => g_out[0]~reg0.ACLR
reset => g_out[1]~reg0.ACLR
reset => g_out[2]~reg0.ACLR
reset => g_out[3]~reg0.ACLR
reset => g_out[4]~reg0.ACLR
reset => g_out[5]~reg0.ACLR
reset => g_out[6]~reg0.ACLR
reset => g_out[7]~reg0.ACLR
reset => g_out[8]~reg0.ACLR
reset => g_out[9]~reg0.ACLR
reset => g_out[10]~reg0.ACLR
reset => b_out[0]~reg0.ACLR
reset => b_out[1]~reg0.ACLR
reset => b_out[2]~reg0.ACLR
reset => b_out[3]~reg0.ACLR
reset => b_out[4]~reg0.ACLR
reset => b_out[5]~reg0.ACLR
reset => b_out[6]~reg0.ACLR
reset => b_out[7]~reg0.ACLR
reset => b_out[8]~reg0.ACLR
reset => b_out[9]~reg0.ACLR
reset => b_out[10]~reg0.ACLR
reset => b_int[0].PRESET
reset => b_int[1].ACLR
reset => b_int[2].ACLR
reset => b_int[3].ACLR
reset => b_int[4].ACLR
reset => b_int[5].ACLR
reset => b_int[6].ACLR
reset => b_int[7].ACLR
reset => b_int[8].ACLR
reset => b_int[9].ACLR
reset => b_int[10].ACLR
enable => always1.IN1
b_out[0] <= b_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[1] <= b_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[2] <= b_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[3] <= b_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[4] <= b_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[5] <= b_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[6] <= b_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[7] <= b_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[8] <= b_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[9] <= b_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[10] <= b_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[0] <= g_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[1] <= g_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[2] <= g_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[3] <= g_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[4] <= g_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[5] <= g_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[6] <= g_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[7] <= g_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[8] <= g_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[9] <= g_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[10] <= g_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD
clk => g_out[0]~reg0.CLK
clk => g_out[1]~reg0.CLK
clk => g_out[2]~reg0.CLK
clk => g_out[3]~reg0.CLK
clk => g_out[4]~reg0.CLK
clk => g_out[5]~reg0.CLK
clk => g_out[6]~reg0.CLK
clk => g_out[7]~reg0.CLK
clk => g_out[8]~reg0.CLK
clk => g_out[9]~reg0.CLK
clk => g_out[10]~reg0.CLK
clk => b_out[0]~reg0.CLK
clk => b_out[1]~reg0.CLK
clk => b_out[2]~reg0.CLK
clk => b_out[3]~reg0.CLK
clk => b_out[4]~reg0.CLK
clk => b_out[5]~reg0.CLK
clk => b_out[6]~reg0.CLK
clk => b_out[7]~reg0.CLK
clk => b_out[8]~reg0.CLK
clk => b_out[9]~reg0.CLK
clk => b_out[10]~reg0.CLK
clk => b_int[0].CLK
clk => b_int[1].CLK
clk => b_int[2].CLK
clk => b_int[3].CLK
clk => b_int[4].CLK
clk => b_int[5].CLK
clk => b_int[6].CLK
clk => b_int[7].CLK
clk => b_int[8].CLK
clk => b_int[9].CLK
clk => b_int[10].CLK
clkena => always1.IN0
reset => g_out[0]~reg0.ACLR
reset => g_out[1]~reg0.ACLR
reset => g_out[2]~reg0.ACLR
reset => g_out[3]~reg0.ACLR
reset => g_out[4]~reg0.ACLR
reset => g_out[5]~reg0.ACLR
reset => g_out[6]~reg0.ACLR
reset => g_out[7]~reg0.ACLR
reset => g_out[8]~reg0.ACLR
reset => g_out[9]~reg0.ACLR
reset => g_out[10]~reg0.ACLR
reset => b_out[0]~reg0.ACLR
reset => b_out[1]~reg0.ACLR
reset => b_out[2]~reg0.ACLR
reset => b_out[3]~reg0.ACLR
reset => b_out[4]~reg0.ACLR
reset => b_out[5]~reg0.ACLR
reset => b_out[6]~reg0.ACLR
reset => b_out[7]~reg0.ACLR
reset => b_out[8]~reg0.ACLR
reset => b_out[9]~reg0.ACLR
reset => b_out[10]~reg0.ACLR
reset => b_int[0].PRESET
reset => b_int[1].ACLR
reset => b_int[2].ACLR
reset => b_int[3].ACLR
reset => b_int[4].ACLR
reset => b_int[5].ACLR
reset => b_int[6].ACLR
reset => b_int[7].ACLR
reset => b_int[8].ACLR
reset => b_int[9].ACLR
reset => b_int[10].ACLR
enable => always1.IN1
b_out[0] <= b_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[1] <= b_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[2] <= b_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[3] <= b_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[4] <= b_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[5] <= b_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[6] <= b_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[7] <= b_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[8] <= b_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[9] <= b_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[10] <= b_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[0] <= g_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[1] <= g_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[2] <= g_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[3] <= g_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[4] <= g_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[5] <= g_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[6] <= g_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[7] <= g_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[8] <= g_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[9] <= g_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[10] <= g_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_1
clk => clk.IN11
reset_n => reset_n.IN11
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
din[9] => din[9].IN1
din[10] => din[10].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout
dout[9] <= altera_std_synchronizer:sync[9].u.dout
dout[10] <= altera_std_synchronizer:sync[10].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[9].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[10].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_2
clk => clk.IN11
reset_n => reset_n.IN11
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
din[9] => din[9].IN1
din[10] => din[10].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout
dout[9] <= altera_std_synchronizer:sync[9].u.dout
dout[10] <= altera_std_synchronizer:sync[10].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[9].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[10].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_3
clk => clk.IN11
reset_n => reset_n.IN11
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
din[9] => din[9].IN1
din[10] => din[10].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout
dout[9] <= altera_std_synchronizer:sync[9].u.dout
dout[10] <= altera_std_synchronizer:sync[10].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[9].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[10].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_4
clk => clk.IN11
reset_n => reset_n.IN11
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
din[9] => din[9].IN1
din[10] => din[10].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout
dout[9] <= altera_std_synchronizer:sync[9].u.dout
dout[10] <= altera_std_synchronizer:sync[10].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[9].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[10].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS
reset_wclk => reset_wclk.IN1
reset_rclk => reset_rclk.IN1
wclk => wclk.IN2
wclk_ena => wclk_ena.IN1
wren => wren.IN2
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
din[9] => din[9].IN1
din[10] => din[10].IN1
din[11] => din[11].IN1
din[12] => din[12].IN1
din[13] => din[13].IN1
din[14] => din[14].IN1
din[15] => din[15].IN1
din[16] => din[16].IN1
din[17] => din[17].IN1
din[18] => din[18].IN1
din[19] => din[19].IN1
din[20] => din[20].IN1
din[21] => din[21].IN1
din[22] => din[22].IN1
rclk => rclk.IN2
rclk_ena => rclk_ena.IN1
rden => rden.IN1
dout[0] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[1] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[2] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[3] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[4] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[5] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[6] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[7] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[8] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[9] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[10] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[11] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[12] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[13] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[14] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[15] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[16] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[17] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[18] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[19] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[20] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[21] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[22] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
empty <= empty_flag.DB_MAX_OUTPUT_PORT_TYPE
aempty <= aempty_flag.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM
data[0] => data[0].IN1
data[1] => data[1].IN1
data[2] => data[2].IN1
data[3] => data[3].IN1
data[4] => data[4].IN1
data[5] => data[5].IN1
data[6] => data[6].IN1
data[7] => data[7].IN1
data[8] => data[8].IN1
data[9] => data[9].IN1
data[10] => data[10].IN1
data[11] => data[11].IN1
data[12] => data[12].IN1
data[13] => data[13].IN1
data[14] => data[14].IN1
data[15] => data[15].IN1
data[16] => data[16].IN1
data[17] => data[17].IN1
data[18] => data[18].IN1
data[19] => data[19].IN1
data[20] => data[20].IN1
data[21] => data[21].IN1
data[22] => data[22].IN1
rdaddress[0] => rdaddress[0].IN1
rdaddress[1] => rdaddress[1].IN1
rdaddress[2] => rdaddress[2].IN1
rdaddress[3] => rdaddress[3].IN1
rdaddress[4] => rdaddress[4].IN1
rdaddress[5] => rdaddress[5].IN1
rdaddress[6] => rdaddress[6].IN1
rdaddress[7] => rdaddress[7].IN1
rdaddress[8] => rdaddress[8].IN1
rdclock => rdclock.IN1
wraddress[0] => wraddress[0].IN1
wraddress[1] => wraddress[1].IN1
wraddress[2] => wraddress[2].IN1
wraddress[3] => wraddress[3].IN1
wraddress[4] => wraddress[4].IN1
wraddress[5] => wraddress[5].IN1
wraddress[6] => wraddress[6].IN1
wraddress[7] => wraddress[7].IN1
wraddress[8] => wraddress[8].IN1
wrclock => wrclock.IN1
wren => wren.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b
q[4] <= altsyncram:altsyncram_component.q_b
q[5] <= altsyncram:altsyncram_component.q_b
q[6] <= altsyncram:altsyncram_component.q_b
q[7] <= altsyncram:altsyncram_component.q_b
q[8] <= altsyncram:altsyncram_component.q_b
q[9] <= altsyncram:altsyncram_component.q_b
q[10] <= altsyncram:altsyncram_component.q_b
q[11] <= altsyncram:altsyncram_component.q_b
q[12] <= altsyncram:altsyncram_component.q_b
q[13] <= altsyncram:altsyncram_component.q_b
q[14] <= altsyncram:altsyncram_component.q_b
q[15] <= altsyncram:altsyncram_component.q_b
q[16] <= altsyncram:altsyncram_component.q_b
q[17] <= altsyncram:altsyncram_component.q_b
q[18] <= altsyncram:altsyncram_component.q_b
q[19] <= altsyncram:altsyncram_component.q_b
q[20] <= altsyncram:altsyncram_component.q_b
q[21] <= altsyncram:altsyncram_component.q_b
q[22] <= altsyncram:altsyncram_component.q_b


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component
wren_a => altsyncram_g9g1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_g9g1:auto_generated.data_a[0]
data_a[1] => altsyncram_g9g1:auto_generated.data_a[1]
data_a[2] => altsyncram_g9g1:auto_generated.data_a[2]
data_a[3] => altsyncram_g9g1:auto_generated.data_a[3]
data_a[4] => altsyncram_g9g1:auto_generated.data_a[4]
data_a[5] => altsyncram_g9g1:auto_generated.data_a[5]
data_a[6] => altsyncram_g9g1:auto_generated.data_a[6]
data_a[7] => altsyncram_g9g1:auto_generated.data_a[7]
data_a[8] => altsyncram_g9g1:auto_generated.data_a[8]
data_a[9] => altsyncram_g9g1:auto_generated.data_a[9]
data_a[10] => altsyncram_g9g1:auto_generated.data_a[10]
data_a[11] => altsyncram_g9g1:auto_generated.data_a[11]
data_a[12] => altsyncram_g9g1:auto_generated.data_a[12]
data_a[13] => altsyncram_g9g1:auto_generated.data_a[13]
data_a[14] => altsyncram_g9g1:auto_generated.data_a[14]
data_a[15] => altsyncram_g9g1:auto_generated.data_a[15]
data_a[16] => altsyncram_g9g1:auto_generated.data_a[16]
data_a[17] => altsyncram_g9g1:auto_generated.data_a[17]
data_a[18] => altsyncram_g9g1:auto_generated.data_a[18]
data_a[19] => altsyncram_g9g1:auto_generated.data_a[19]
data_a[20] => altsyncram_g9g1:auto_generated.data_a[20]
data_a[21] => altsyncram_g9g1:auto_generated.data_a[21]
data_a[22] => altsyncram_g9g1:auto_generated.data_a[22]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
data_b[8] => ~NO_FANOUT~
data_b[9] => ~NO_FANOUT~
data_b[10] => ~NO_FANOUT~
data_b[11] => ~NO_FANOUT~
data_b[12] => ~NO_FANOUT~
data_b[13] => ~NO_FANOUT~
data_b[14] => ~NO_FANOUT~
data_b[15] => ~NO_FANOUT~
data_b[16] => ~NO_FANOUT~
data_b[17] => ~NO_FANOUT~
data_b[18] => ~NO_FANOUT~
data_b[19] => ~NO_FANOUT~
data_b[20] => ~NO_FANOUT~
data_b[21] => ~NO_FANOUT~
data_b[22] => ~NO_FANOUT~
address_a[0] => altsyncram_g9g1:auto_generated.address_a[0]
address_a[1] => altsyncram_g9g1:auto_generated.address_a[1]
address_a[2] => altsyncram_g9g1:auto_generated.address_a[2]
address_a[3] => altsyncram_g9g1:auto_generated.address_a[3]
address_a[4] => altsyncram_g9g1:auto_generated.address_a[4]
address_a[5] => altsyncram_g9g1:auto_generated.address_a[5]
address_a[6] => altsyncram_g9g1:auto_generated.address_a[6]
address_a[7] => altsyncram_g9g1:auto_generated.address_a[7]
address_a[8] => altsyncram_g9g1:auto_generated.address_a[8]
address_b[0] => altsyncram_g9g1:auto_generated.address_b[0]
address_b[1] => altsyncram_g9g1:auto_generated.address_b[1]
address_b[2] => altsyncram_g9g1:auto_generated.address_b[2]
address_b[3] => altsyncram_g9g1:auto_generated.address_b[3]
address_b[4] => altsyncram_g9g1:auto_generated.address_b[4]
address_b[5] => altsyncram_g9g1:auto_generated.address_b[5]
address_b[6] => altsyncram_g9g1:auto_generated.address_b[6]
address_b[7] => altsyncram_g9g1:auto_generated.address_b[7]
address_b[8] => altsyncram_g9g1:auto_generated.address_b[8]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_g9g1:auto_generated.clock0
clock1 => altsyncram_g9g1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_a[8] <= <GND>
q_a[9] <= <GND>
q_a[10] <= <GND>
q_a[11] <= <GND>
q_a[12] <= <GND>
q_a[13] <= <GND>
q_a[14] <= <GND>
q_a[15] <= <GND>
q_a[16] <= <GND>
q_a[17] <= <GND>
q_a[18] <= <GND>
q_a[19] <= <GND>
q_a[20] <= <GND>
q_a[21] <= <GND>
q_a[22] <= <GND>
q_b[0] <= altsyncram_g9g1:auto_generated.q_b[0]
q_b[1] <= altsyncram_g9g1:auto_generated.q_b[1]
q_b[2] <= altsyncram_g9g1:auto_generated.q_b[2]
q_b[3] <= altsyncram_g9g1:auto_generated.q_b[3]
q_b[4] <= altsyncram_g9g1:auto_generated.q_b[4]
q_b[5] <= altsyncram_g9g1:auto_generated.q_b[5]
q_b[6] <= altsyncram_g9g1:auto_generated.q_b[6]
q_b[7] <= altsyncram_g9g1:auto_generated.q_b[7]
q_b[8] <= altsyncram_g9g1:auto_generated.q_b[8]
q_b[9] <= altsyncram_g9g1:auto_generated.q_b[9]
q_b[10] <= altsyncram_g9g1:auto_generated.q_b[10]
q_b[11] <= altsyncram_g9g1:auto_generated.q_b[11]
q_b[12] <= altsyncram_g9g1:auto_generated.q_b[12]
q_b[13] <= altsyncram_g9g1:auto_generated.q_b[13]
q_b[14] <= altsyncram_g9g1:auto_generated.q_b[14]
q_b[15] <= altsyncram_g9g1:auto_generated.q_b[15]
q_b[16] <= altsyncram_g9g1:auto_generated.q_b[16]
q_b[17] <= altsyncram_g9g1:auto_generated.q_b[17]
q_b[18] <= altsyncram_g9g1:auto_generated.q_b[18]
q_b[19] <= altsyncram_g9g1:auto_generated.q_b[19]
q_b[20] <= altsyncram_g9g1:auto_generated.q_b[20]
q_b[21] <= altsyncram_g9g1:auto_generated.q_b[21]
q_b[22] <= altsyncram_g9g1:auto_generated.q_b[22]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[7] => ram_block1a16.PORTAADDR7
address_a[7] => ram_block1a17.PORTAADDR7
address_a[7] => ram_block1a18.PORTAADDR7
address_a[7] => ram_block1a19.PORTAADDR7
address_a[7] => ram_block1a20.PORTAADDR7
address_a[7] => ram_block1a21.PORTAADDR7
address_a[7] => ram_block1a22.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[8] => ram_block1a16.PORTAADDR8
address_a[8] => ram_block1a17.PORTAADDR8
address_a[8] => ram_block1a18.PORTAADDR8
address_a[8] => ram_block1a19.PORTAADDR8
address_a[8] => ram_block1a20.PORTAADDR8
address_a[8] => ram_block1a21.PORTAADDR8
address_a[8] => ram_block1a22.PORTAADDR8
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[0] => ram_block1a16.PORTBADDR
address_b[0] => ram_block1a17.PORTBADDR
address_b[0] => ram_block1a18.PORTBADDR
address_b[0] => ram_block1a19.PORTBADDR
address_b[0] => ram_block1a20.PORTBADDR
address_b[0] => ram_block1a21.PORTBADDR
address_b[0] => ram_block1a22.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[1] => ram_block1a16.PORTBADDR1
address_b[1] => ram_block1a17.PORTBADDR1
address_b[1] => ram_block1a18.PORTBADDR1
address_b[1] => ram_block1a19.PORTBADDR1
address_b[1] => ram_block1a20.PORTBADDR1
address_b[1] => ram_block1a21.PORTBADDR1
address_b[1] => ram_block1a22.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
address_b[2] => ram_block1a16.PORTBADDR2
address_b[2] => ram_block1a17.PORTBADDR2
address_b[2] => ram_block1a18.PORTBADDR2
address_b[2] => ram_block1a19.PORTBADDR2
address_b[2] => ram_block1a20.PORTBADDR2
address_b[2] => ram_block1a21.PORTBADDR2
address_b[2] => ram_block1a22.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[3] => ram_block1a8.PORTBADDR3
address_b[3] => ram_block1a9.PORTBADDR3
address_b[3] => ram_block1a10.PORTBADDR3
address_b[3] => ram_block1a11.PORTBADDR3
address_b[3] => ram_block1a12.PORTBADDR3
address_b[3] => ram_block1a13.PORTBADDR3
address_b[3] => ram_block1a14.PORTBADDR3
address_b[3] => ram_block1a15.PORTBADDR3
address_b[3] => ram_block1a16.PORTBADDR3
address_b[3] => ram_block1a17.PORTBADDR3
address_b[3] => ram_block1a18.PORTBADDR3
address_b[3] => ram_block1a19.PORTBADDR3
address_b[3] => ram_block1a20.PORTBADDR3
address_b[3] => ram_block1a21.PORTBADDR3
address_b[3] => ram_block1a22.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[4] => ram_block1a8.PORTBADDR4
address_b[4] => ram_block1a9.PORTBADDR4
address_b[4] => ram_block1a10.PORTBADDR4
address_b[4] => ram_block1a11.PORTBADDR4
address_b[4] => ram_block1a12.PORTBADDR4
address_b[4] => ram_block1a13.PORTBADDR4
address_b[4] => ram_block1a14.PORTBADDR4
address_b[4] => ram_block1a15.PORTBADDR4
address_b[4] => ram_block1a16.PORTBADDR4
address_b[4] => ram_block1a17.PORTBADDR4
address_b[4] => ram_block1a18.PORTBADDR4
address_b[4] => ram_block1a19.PORTBADDR4
address_b[4] => ram_block1a20.PORTBADDR4
address_b[4] => ram_block1a21.PORTBADDR4
address_b[4] => ram_block1a22.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[5] => ram_block1a8.PORTBADDR5
address_b[5] => ram_block1a9.PORTBADDR5
address_b[5] => ram_block1a10.PORTBADDR5
address_b[5] => ram_block1a11.PORTBADDR5
address_b[5] => ram_block1a12.PORTBADDR5
address_b[5] => ram_block1a13.PORTBADDR5
address_b[5] => ram_block1a14.PORTBADDR5
address_b[5] => ram_block1a15.PORTBADDR5
address_b[5] => ram_block1a16.PORTBADDR5
address_b[5] => ram_block1a17.PORTBADDR5
address_b[5] => ram_block1a18.PORTBADDR5
address_b[5] => ram_block1a19.PORTBADDR5
address_b[5] => ram_block1a20.PORTBADDR5
address_b[5] => ram_block1a21.PORTBADDR5
address_b[5] => ram_block1a22.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[6] => ram_block1a8.PORTBADDR6
address_b[6] => ram_block1a9.PORTBADDR6
address_b[6] => ram_block1a10.PORTBADDR6
address_b[6] => ram_block1a11.PORTBADDR6
address_b[6] => ram_block1a12.PORTBADDR6
address_b[6] => ram_block1a13.PORTBADDR6
address_b[6] => ram_block1a14.PORTBADDR6
address_b[6] => ram_block1a15.PORTBADDR6
address_b[6] => ram_block1a16.PORTBADDR6
address_b[6] => ram_block1a17.PORTBADDR6
address_b[6] => ram_block1a18.PORTBADDR6
address_b[6] => ram_block1a19.PORTBADDR6
address_b[6] => ram_block1a20.PORTBADDR6
address_b[6] => ram_block1a21.PORTBADDR6
address_b[6] => ram_block1a22.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[7] => ram_block1a8.PORTBADDR7
address_b[7] => ram_block1a9.PORTBADDR7
address_b[7] => ram_block1a10.PORTBADDR7
address_b[7] => ram_block1a11.PORTBADDR7
address_b[7] => ram_block1a12.PORTBADDR7
address_b[7] => ram_block1a13.PORTBADDR7
address_b[7] => ram_block1a14.PORTBADDR7
address_b[7] => ram_block1a15.PORTBADDR7
address_b[7] => ram_block1a16.PORTBADDR7
address_b[7] => ram_block1a17.PORTBADDR7
address_b[7] => ram_block1a18.PORTBADDR7
address_b[7] => ram_block1a19.PORTBADDR7
address_b[7] => ram_block1a20.PORTBADDR7
address_b[7] => ram_block1a21.PORTBADDR7
address_b[7] => ram_block1a22.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[8] => ram_block1a8.PORTBADDR8
address_b[8] => ram_block1a9.PORTBADDR8
address_b[8] => ram_block1a10.PORTBADDR8
address_b[8] => ram_block1a11.PORTBADDR8
address_b[8] => ram_block1a12.PORTBADDR8
address_b[8] => ram_block1a13.PORTBADDR8
address_b[8] => ram_block1a14.PORTBADDR8
address_b[8] => ram_block1a15.PORTBADDR8
address_b[8] => ram_block1a16.PORTBADDR8
address_b[8] => ram_block1a17.PORTBADDR8
address_b[8] => ram_block1a18.PORTBADDR8
address_b[8] => ram_block1a19.PORTBADDR8
address_b[8] => ram_block1a20.PORTBADDR8
address_b[8] => ram_block1a21.PORTBADDR8
address_b[8] => ram_block1a22.PORTBADDR8
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
clock1 => ram_block1a8.CLK1
clock1 => ram_block1a9.CLK1
clock1 => ram_block1a10.CLK1
clock1 => ram_block1a11.CLK1
clock1 => ram_block1a12.CLK1
clock1 => ram_block1a13.CLK1
clock1 => ram_block1a14.CLK1
clock1 => ram_block1a15.CLK1
clock1 => ram_block1a16.CLK1
clock1 => ram_block1a17.CLK1
clock1 => ram_block1a18.CLK1
clock1 => ram_block1a19.CLK1
clock1 => ram_block1a20.CLK1
clock1 => ram_block1a21.CLK1
clock1 => ram_block1a22.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
data_a[16] => ram_block1a16.PORTADATAIN
data_a[17] => ram_block1a17.PORTADATAIN
data_a[18] => ram_block1a18.PORTADATAIN
data_a[19] => ram_block1a19.PORTADATAIN
data_a[20] => ram_block1a20.PORTADATAIN
data_a[21] => ram_block1a21.PORTADATAIN
data_a[22] => ram_block1a22.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
q_b[8] <= ram_block1a8.PORTBDATAOUT
q_b[9] <= ram_block1a9.PORTBDATAOUT
q_b[10] <= ram_block1a10.PORTBDATAOUT
q_b[11] <= ram_block1a11.PORTBDATAOUT
q_b[12] <= ram_block1a12.PORTBDATAOUT
q_b[13] <= ram_block1a13.PORTBDATAOUT
q_b[14] <= ram_block1a14.PORTBDATAOUT
q_b[15] <= ram_block1a15.PORTBDATAOUT
q_b[16] <= ram_block1a16.PORTBDATAOUT
q_b[17] <= ram_block1a17.PORTBDATAOUT
q_b[18] <= ram_block1a18.PORTBDATAOUT
q_b[19] <= ram_block1a19.PORTBDATAOUT
q_b[20] <= ram_block1a20.PORTBDATAOUT
q_b[21] <= ram_block1a21.PORTBDATAOUT
q_b[22] <= ram_block1a22.PORTBDATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a7.ENA0
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a8.ENA0
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a9.ENA0
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a10.ENA0
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a11.ENA0
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a12.ENA0
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a13.ENA0
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a14.ENA0
wren_a => ram_block1a15.PORTAWE
wren_a => ram_block1a15.ENA0
wren_a => ram_block1a16.PORTAWE
wren_a => ram_block1a16.ENA0
wren_a => ram_block1a17.PORTAWE
wren_a => ram_block1a17.ENA0
wren_a => ram_block1a18.PORTAWE
wren_a => ram_block1a18.ENA0
wren_a => ram_block1a19.PORTAWE
wren_a => ram_block1a19.ENA0
wren_a => ram_block1a20.PORTAWE
wren_a => ram_block1a20.ENA0
wren_a => ram_block1a21.PORTAWE
wren_a => ram_block1a21.ENA0
wren_a => ram_block1a22.PORTAWE
wren_a => ram_block1a22.ENA0


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_gray_cnt:U_WRT
clk => g_out[0]~reg0.CLK
clk => g_out[1]~reg0.CLK
clk => g_out[2]~reg0.CLK
clk => g_out[3]~reg0.CLK
clk => g_out[4]~reg0.CLK
clk => g_out[5]~reg0.CLK
clk => g_out[6]~reg0.CLK
clk => g_out[7]~reg0.CLK
clk => g_out[8]~reg0.CLK
clk => b_out[0]~reg0.CLK
clk => b_out[1]~reg0.CLK
clk => b_out[2]~reg0.CLK
clk => b_out[3]~reg0.CLK
clk => b_out[4]~reg0.CLK
clk => b_out[5]~reg0.CLK
clk => b_out[6]~reg0.CLK
clk => b_out[7]~reg0.CLK
clk => b_out[8]~reg0.CLK
clk => b_int[0].CLK
clk => b_int[1].CLK
clk => b_int[2].CLK
clk => b_int[3].CLK
clk => b_int[4].CLK
clk => b_int[5].CLK
clk => b_int[6].CLK
clk => b_int[7].CLK
clk => b_int[8].CLK
clkena => always1.IN0
reset => g_out[0]~reg0.ACLR
reset => g_out[1]~reg0.ACLR
reset => g_out[2]~reg0.ACLR
reset => g_out[3]~reg0.ACLR
reset => g_out[4]~reg0.ACLR
reset => g_out[5]~reg0.ACLR
reset => g_out[6]~reg0.ACLR
reset => g_out[7]~reg0.ACLR
reset => g_out[8]~reg0.ACLR
reset => b_out[0]~reg0.ACLR
reset => b_out[1]~reg0.ACLR
reset => b_out[2]~reg0.ACLR
reset => b_out[3]~reg0.ACLR
reset => b_out[4]~reg0.ACLR
reset => b_out[5]~reg0.ACLR
reset => b_out[6]~reg0.ACLR
reset => b_out[7]~reg0.ACLR
reset => b_out[8]~reg0.ACLR
reset => b_int[0].PRESET
reset => b_int[1].ACLR
reset => b_int[2].ACLR
reset => b_int[3].ACLR
reset => b_int[4].ACLR
reset => b_int[5].ACLR
reset => b_int[6].ACLR
reset => b_int[7].ACLR
reset => b_int[8].ACLR
enable => always1.IN1
b_out[0] <= b_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[1] <= b_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[2] <= b_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[3] <= b_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[4] <= b_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[5] <= b_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[6] <= b_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[7] <= b_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[8] <= b_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[0] <= g_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[1] <= g_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[2] <= g_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[3] <= g_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[4] <= g_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[5] <= g_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[6] <= g_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[7] <= g_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[8] <= g_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_bin_cnt:U_RD
clk => b_out[0]~reg0.CLK
clk => b_out[1]~reg0.CLK
clk => b_out[2]~reg0.CLK
clk => b_out[3]~reg0.CLK
clk => b_out[4]~reg0.CLK
clk => b_out[5]~reg0.CLK
clk => b_out[6]~reg0.CLK
clk => b_out[7]~reg0.CLK
clk => b_out[8]~reg0.CLK
clk => b_int[0].CLK
clk => b_int[1].CLK
clk => b_int[2].CLK
clk => b_int[3].CLK
clk => b_int[4].CLK
clk => b_int[5].CLK
clk => b_int[6].CLK
clk => b_int[7].CLK
clk => b_int[8].CLK
clkena => b_int[8].ENA
clkena => b_int[7].ENA
clkena => b_int[6].ENA
clkena => b_int[5].ENA
clkena => b_int[4].ENA
clkena => b_int[3].ENA
clkena => b_int[2].ENA
clkena => b_int[1].ENA
clkena => b_out[0]~reg0.ENA
clkena => b_int[0].ENA
clkena => b_out[8]~reg0.ENA
clkena => b_out[7]~reg0.ENA
clkena => b_out[6]~reg0.ENA
clkena => b_out[5]~reg0.ENA
clkena => b_out[4]~reg0.ENA
clkena => b_out[3]~reg0.ENA
clkena => b_out[2]~reg0.ENA
clkena => b_out[1]~reg0.ENA
reset => b_out[0]~reg0.ACLR
reset => b_out[1]~reg0.ACLR
reset => b_out[2]~reg0.ACLR
reset => b_out[3]~reg0.ACLR
reset => b_out[4]~reg0.ACLR
reset => b_out[5]~reg0.ACLR
reset => b_out[6]~reg0.ACLR
reset => b_out[7]~reg0.ACLR
reset => b_out[8]~reg0.ACLR
reset => b_int[0].PRESET
reset => b_int[1].ACLR
reset => b_int[2].ACLR
reset => b_int[3].ACLR
reset => b_int[4].ACLR
reset => b_int[5].ACLR
reset => b_int[6].ACLR
reset => b_int[7].ACLR
reset => b_int[8].ACLR
enable => b_int.OUTPUTSELECT
enable => b_int.OUTPUTSELECT
enable => b_int.OUTPUTSELECT
enable => b_int.OUTPUTSELECT
enable => b_int.OUTPUTSELECT
enable => b_int.OUTPUTSELECT
enable => b_int.OUTPUTSELECT
enable => b_int.OUTPUTSELECT
enable => b_int.OUTPUTSELECT
enable => b_out.OUTPUTSELECT
enable => b_out.OUTPUTSELECT
enable => b_out.OUTPUTSELECT
enable => b_out.OUTPUTSELECT
enable => b_out.OUTPUTSELECT
enable => b_out.OUTPUTSELECT
enable => b_out.OUTPUTSELECT
enable => b_out.OUTPUTSELECT
enable => b_out.OUTPUTSELECT
b_out[0] <= b_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[1] <= b_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[2] <= b_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[3] <= b_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[4] <= b_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[5] <= b_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[6] <= b_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[7] <= b_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[8] <= b_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF
col => ~NO_FANOUT~
crs => ~NO_FANOUT~
half_duplex_ena => ~NO_FANOUT~
excess_col <= <GND>
late_col <= <GND>
tx_clk_ena => ~NO_FANOUT~
reset_tx_clk => reset_tx_clk.IN2
reset_ff_tx_clk => reset_ff_tx_clk.IN2
ethernet_mode => ~NO_FANOUT~
tx_shift16 => tx_shift16.IN1
ff_tx_clk => ff_tx_clk.IN4
ff_tx_data[0] => data_tmp.DATAB
ff_tx_data[0] => data_tmp.DATAB
ff_tx_data[1] => data_tmp.DATAB
ff_tx_data[1] => data_tmp.DATAB
ff_tx_data[2] => data_tmp.DATAB
ff_tx_data[2] => data_tmp.DATAB
ff_tx_data[3] => data_tmp.DATAB
ff_tx_data[3] => data_tmp.DATAB
ff_tx_data[4] => data_tmp.DATAB
ff_tx_data[4] => data_tmp.DATAB
ff_tx_data[5] => data_tmp.DATAB
ff_tx_data[5] => data_tmp.DATAB
ff_tx_data[6] => data_tmp.DATAB
ff_tx_data[6] => data_tmp.DATAB
ff_tx_data[7] => data_tmp.DATAB
ff_tx_data[7] => data_tmp.DATAB
ff_tx_data[8] => data_tmp.DATAB
ff_tx_data[8] => data_tmp.DATAB
ff_tx_data[9] => data_tmp.DATAB
ff_tx_data[9] => data_tmp.DATAB
ff_tx_data[10] => data_tmp.DATAB
ff_tx_data[10] => data_tmp.DATAB
ff_tx_data[11] => data_tmp.DATAB
ff_tx_data[11] => data_tmp.DATAB
ff_tx_data[12] => data_tmp.DATAB
ff_tx_data[12] => data_tmp.DATAB
ff_tx_data[13] => data_tmp.DATAB
ff_tx_data[13] => data_tmp.DATAB
ff_tx_data[14] => data_tmp.DATAB
ff_tx_data[14] => data_tmp.DATAB
ff_tx_data[15] => data_tmp.DATAB
ff_tx_data[15] => data_tmp.DATAB
ff_tx_data[16] => data_tmp.DATAB
ff_tx_data[16] => data_tmp.DATAB
ff_tx_data[16] => data_sig.DATAB
ff_tx_data[17] => data_tmp.DATAB
ff_tx_data[17] => data_tmp.DATAB
ff_tx_data[17] => data_sig.DATAB
ff_tx_data[18] => data_tmp.DATAB
ff_tx_data[18] => data_tmp.DATAB
ff_tx_data[18] => data_sig.DATAB
ff_tx_data[19] => data_tmp.DATAB
ff_tx_data[19] => data_tmp.DATAB
ff_tx_data[19] => data_sig.DATAB
ff_tx_data[20] => data_tmp.DATAB
ff_tx_data[20] => data_tmp.DATAB
ff_tx_data[20] => data_sig.DATAB
ff_tx_data[21] => data_tmp.DATAB
ff_tx_data[21] => data_tmp.DATAB
ff_tx_data[21] => data_sig.DATAB
ff_tx_data[22] => data_tmp.DATAB
ff_tx_data[22] => data_tmp.DATAB
ff_tx_data[22] => data_sig.DATAB
ff_tx_data[23] => data_tmp.DATAB
ff_tx_data[23] => data_tmp.DATAB
ff_tx_data[23] => data_sig.DATAB
ff_tx_data[24] => data_tmp.DATAB
ff_tx_data[24] => data_tmp.DATAB
ff_tx_data[24] => data_sig.DATAB
ff_tx_data[25] => data_tmp.DATAB
ff_tx_data[25] => data_tmp.DATAB
ff_tx_data[25] => data_sig.DATAB
ff_tx_data[26] => data_tmp.DATAB
ff_tx_data[26] => data_tmp.DATAB
ff_tx_data[26] => data_sig.DATAB
ff_tx_data[27] => data_tmp.DATAB
ff_tx_data[27] => data_tmp.DATAB
ff_tx_data[27] => data_sig.DATAB
ff_tx_data[28] => data_tmp.DATAB
ff_tx_data[28] => data_tmp.DATAB
ff_tx_data[28] => data_sig.DATAB
ff_tx_data[29] => data_tmp.DATAB
ff_tx_data[29] => data_tmp.DATAB
ff_tx_data[29] => data_sig.DATAB
ff_tx_data[30] => data_tmp.DATAB
ff_tx_data[30] => data_tmp.DATAB
ff_tx_data[30] => data_sig.DATAB
ff_tx_data[31] => data_tmp.DATAB
ff_tx_data[31] => data_tmp.DATAB
ff_tx_data[31] => data_sig.DATAB
ff_tx_mod[0] => mod_tmp.DATAB
ff_tx_mod[0] => mod_tmp.DATAB
ff_tx_mod[0] => mod_tmp.DATAB
ff_tx_mod[0] => Equal0.IN1
ff_tx_mod[1] => mod_tmp.DATAB
ff_tx_mod[1] => mod_tmp.DATAB
ff_tx_mod[1] => eop_sig.IN1
ff_tx_mod[1] => err_sig.IN1
ff_tx_mod[1] => crc_fwd_sig.IN1
ff_tx_mod[1] => always0.IN0
ff_tx_mod[1] => Equal0.IN0
ff_tx_sop => sop_tmp.DATAB
ff_tx_sop => always0.IN0
ff_tx_sop => sop_tmp.DATAA
ff_tx_eop => eop_tmp.DATAB
ff_tx_eop => eop_tmp.DATAB
ff_tx_eop => always0.IN1
ff_tx_eop => mod_sig.IN1
ff_tx_eop => eop_sig.IN1
ff_tx_eop => err_sig.IN1
ff_tx_eop => crc_fwd_sig.IN1
ff_tx_err => err_tmp.DATAB
ff_tx_err => err_tmp.DATAB
ff_tx_err => err_sig.DATAB
ff_tx_wren => sop_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => data_tmp.OUTPUTSELECT
ff_tx_wren => eop_tmp.OUTPUTSELECT
ff_tx_wren => err_tmp.OUTPUTSELECT
ff_tx_wren => crc_fwd_tmp.OUTPUTSELECT
ff_tx_wren => always0.IN1
ff_tx_wren => wren_tmp.OUTPUTSELECT
ff_tx_wren => always0.IN1
ff_tx_wren => mod_tmp.OUTPUTSELECT
ff_tx_wren => mod_tmp.OUTPUTSELECT
ff_tx_wren => wren_sig.IN1
ff_tx_wren => mod_sig.IN1
ff_tx_wren => eop_sig.IN1
ff_tx_wren => err_sig.IN1
ff_tx_wren => crc_fwd_sig.IN1
ff_tx_wren => wren_tmp.DATAA
ff_crc_fwd => crc_fwd_tmp.DATAB
ff_crc_fwd => crc_fwd_tmp.DATAB
ff_crc_fwd => crc_fwd_sig.DATAB
ff_tx_rdy <= ff_tx_rdy.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_septy <= altera_tse_a_fifo_opt_1246:TX_DATA.septy
tx_clk => tx_clk.IN3
tx_stat_empty <= altera_tse_a_fifo_13:TX_STATUS.empty
tx_stat[0] <= tx_stat[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_stat[1] <= tx_stat[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_stat_rden => comb.IN1
sav_section[0] => sav_section[0].IN1
sav_section[1] => sav_section[1].IN1
sav_section[2] => sav_section[2].IN1
sav_section[3] => sav_section[3].IN1
sav_section[4] => sav_section[4].IN1
sav_section[5] => sav_section[5].IN1
sav_section[6] => sav_section[6].IN1
sav_section[7] => sav_section[7].IN1
sav_section[8] => sav_section[8].IN1
sav_section[9] => sav_section[9].IN1
sav_section[10] => sav_section[10].IN1
septy_section[0] => septy_section[0].IN1
septy_section[1] => septy_section[1].IN1
septy_section[2] => septy_section[2].IN1
septy_section[3] => septy_section[3].IN1
septy_section[4] => septy_section[4].IN1
septy_section[5] => septy_section[5].IN1
septy_section[6] => septy_section[6].IN1
septy_section[7] => septy_section[7].IN1
septy_section[8] => septy_section[8].IN1
septy_section[9] => septy_section[9].IN1
septy_section[10] => septy_section[10].IN1
af_level[0] => af_level[0].IN1
af_level[1] => af_level[1].IN1
af_level[2] => af_level[2].IN1
af_level[3] => af_level[3].IN1
af_level[4] => af_level[4].IN1
af_level[5] => af_level[5].IN1
af_level[6] => af_level[6].IN1
af_level[7] => af_level[7].IN1
af_level[8] => af_level[8].IN1
af_level[9] => af_level[9].IN1
af_level[10] => af_level[10].IN1
ae_level[0] => ae_level[0].IN1
ae_level[1] => ae_level[1].IN1
ae_level[2] => ae_level[2].IN1
ae_level[3] => ae_level[3].IN1
ae_level[4] => ae_level[4].IN1
ae_level[5] => ae_level[5].IN1
ae_level[6] => ae_level[6].IN1
ae_level[7] => ae_level[7].IN1
ae_level[8] => ae_level[8].IN1
ae_level[9] => ae_level[9].IN1
ae_level[10] => ae_level[10].IN1
mac_ena <= <VCC>
tx_data_int[0] <= dout_reg_sft[24].DB_MAX_OUTPUT_PORT_TYPE
tx_data_int[1] <= dout_reg_sft[25].DB_MAX_OUTPUT_PORT_TYPE
tx_data_int[2] <= dout_reg_sft[26].DB_MAX_OUTPUT_PORT_TYPE
tx_data_int[3] <= dout_reg_sft[27].DB_MAX_OUTPUT_PORT_TYPE
tx_data_int[4] <= dout_reg_sft[28].DB_MAX_OUTPUT_PORT_TYPE
tx_data_int[5] <= dout_reg_sft[29].DB_MAX_OUTPUT_PORT_TYPE
tx_data_int[6] <= dout_reg_sft[30].DB_MAX_OUTPUT_PORT_TYPE
tx_data_int[7] <= dout_reg_sft[31].DB_MAX_OUTPUT_PORT_TYPE
tx_sav_int <= altera_tse_a_fifo_opt_1246:TX_DATA.sav
tx_empty <= tx_empty~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_a_full <= altera_tse_a_fifo_opt_1246:TX_DATA.afull
tx_a_empty <= altera_tse_a_fifo_opt_1246:TX_DATA.aempty
tx_sop_int <= sop_reg.DB_MAX_OUTPUT_PORT_TYPE
tx_eop_int <= eop_sft[0].DB_MAX_OUTPUT_PORT_TYPE
tx_rden_int => byte_empty.OUTPUTSELECT
tx_rden_int => byte_empty.OUTPUTSELECT
tx_rden_int => tx_rden32.IN1
tx_rden_int => always2.IN1
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => dout_reg_sft.OUTPUTSELECT
tx_rden_int => sop_reg.OUTPUTSELECT
tx_rden_int => eop_sft.OUTPUTSELECT
tx_rden_int => eop_sft.OUTPUTSELECT
tx_rden_int => eop_sft.OUTPUTSELECT
tx_rden_int => eop_sft.OUTPUTSELECT


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_1
clk => clk.IN11
reset_n => reset_n.IN11
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
din[9] => din[9].IN1
din[10] => din[10].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout
dout[9] <= altera_std_synchronizer:sync[9].u.dout
dout[10] <= altera_std_synchronizer:sync[10].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[9].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[10].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_2
clk => clk.IN11
reset_n => reset_n.IN11
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
din[9] => din[9].IN1
din[10] => din[10].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout
dout[9] <= altera_std_synchronizer:sync[9].u.dout
dout[10] <= altera_std_synchronizer:sync[10].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[9].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[10].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_std_synchronizer:U_SYNC_TX_SHIFT16
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA
reset_wclk => reset_wclk.IN1
reset_rclk => reset_rclk.IN1
wclk => wclk.IN4
wclk_ena => wclk_ena.IN1
wren => write_reg.IN2
din[0] => din_reg[0].IN1
din[1] => din_reg[1].IN1
din[2] => din_reg[2].IN1
din[3] => din_reg[3].IN1
din[4] => din_reg[4].IN1
din[5] => din_reg[5].IN1
din[6] => din_reg[6].IN1
din[7] => din_reg[7].IN1
din[8] => din_reg[8].IN1
din[9] => din_reg[9].IN1
din[10] => din_reg[10].IN1
din[11] => din_reg[11].IN1
din[12] => din_reg[12].IN1
din[13] => din_reg[13].IN1
din[14] => din_reg[14].IN1
din[15] => din_reg[15].IN1
din[16] => din_reg[16].IN1
din[17] => din_reg[17].IN1
din[18] => din_reg[18].IN1
din[19] => din_reg[19].IN1
din[20] => din_reg[20].IN1
din[21] => din_reg[21].IN1
din[22] => din_reg[22].IN1
din[23] => din_reg[23].IN1
din[24] => din_reg[24].IN1
din[25] => din_reg[25].IN1
din[26] => din_reg[26].IN1
din[27] => din_reg[27].IN1
din[28] => din_reg[28].IN1
din[29] => din_reg[29].IN1
din[30] => din_reg[30].IN1
din[31] => din_reg[31].IN1
din[32] => din_reg[32].IN1
din[33] => din_reg[33].IN1
din[34] => din_reg[34].IN1
din[35] => din_reg[35].IN1
rclk => rclk.IN4
rclk_ena => rclk_ena.IN1
rden => rden.IN1
dout[0] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[1] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[2] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[3] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[4] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[5] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[6] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[7] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[8] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[9] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[10] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[11] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[12] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[13] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[14] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[15] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[16] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[17] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[18] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[19] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[20] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[21] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[22] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[23] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[24] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[25] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[26] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[27] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[28] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[29] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[30] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[31] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[32] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[33] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[34] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[35] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
section[0] => LessThan4.IN11
section[0] => Equal5.IN10
section[1] => LessThan4.IN10
section[1] => Equal5.IN9
section[2] => LessThan4.IN9
section[2] => Equal5.IN8
section[3] => LessThan4.IN8
section[3] => Equal5.IN7
section[4] => LessThan4.IN7
section[4] => Equal5.IN6
section[5] => LessThan4.IN6
section[5] => Equal5.IN5
section[6] => LessThan4.IN5
section[6] => Equal5.IN4
section[7] => LessThan4.IN4
section[7] => Equal5.IN3
section[8] => LessThan4.IN3
section[8] => Equal5.IN2
section[9] => LessThan4.IN2
section[9] => Equal5.IN1
section[10] => LessThan4.IN1
section[10] => Equal5.IN0
sect_e[0] => LessThan2.IN11
sect_e[0] => Equal1.IN10
sect_e[1] => LessThan2.IN10
sect_e[1] => Equal1.IN9
sect_e[2] => LessThan2.IN9
sect_e[2] => Equal1.IN8
sect_e[3] => LessThan2.IN8
sect_e[3] => Equal1.IN7
sect_e[4] => LessThan2.IN7
sect_e[4] => Equal1.IN6
sect_e[5] => LessThan2.IN6
sect_e[5] => Equal1.IN5
sect_e[6] => LessThan2.IN5
sect_e[6] => Equal1.IN4
sect_e[7] => LessThan2.IN4
sect_e[7] => Equal1.IN3
sect_e[8] => LessThan2.IN3
sect_e[8] => Equal1.IN2
sect_e[9] => LessThan2.IN2
sect_e[9] => Equal1.IN1
sect_e[10] => LessThan2.IN1
sect_e[10] => Equal1.IN0
af_level[0] => af_level[0].IN1
af_level[1] => af_level[1].IN1
af_level[2] => af_level[2].IN1
af_level[3] => af_level[3].IN1
af_level[4] => af_level[4].IN1
af_level[5] => af_level[5].IN1
af_level[6] => af_level[6].IN1
af_level[7] => af_level[7].IN1
af_level[8] => af_level[8].IN1
af_level[9] => af_level[9].IN1
af_level[10] => af_level[10].IN1
ae_level[0] => ae_level[0].IN1
ae_level[1] => ae_level[1].IN1
ae_level[2] => ae_level[2].IN1
ae_level[3] => ae_level[3].IN1
ae_level[4] => ae_level[4].IN1
ae_level[5] => ae_level[5].IN1
ae_level[6] => ae_level[6].IN1
ae_level[7] => ae_level[7].IN1
ae_level[8] => ae_level[8].IN1
ae_level[9] => ae_level[9].IN1
ae_level[10] => ae_level[10].IN1
sav <= sav_flag.DB_MAX_OUTPUT_PORT_TYPE
septy <= septy_flag.DB_MAX_OUTPUT_PORT_TYPE
afull <= afull_flag.DB_MAX_OUTPUT_PORT_TYPE
full <= full_flag.DB_MAX_OUTPUT_PORT_TYPE
aempty <= aempty_flag.DB_MAX_OUTPUT_PORT_TYPE
empty <= empty_flag.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM
data[0] => data[0].IN1
data[1] => data[1].IN1
data[2] => data[2].IN1
data[3] => data[3].IN1
data[4] => data[4].IN1
data[5] => data[5].IN1
data[6] => data[6].IN1
data[7] => data[7].IN1
data[8] => data[8].IN1
data[9] => data[9].IN1
data[10] => data[10].IN1
data[11] => data[11].IN1
data[12] => data[12].IN1
data[13] => data[13].IN1
data[14] => data[14].IN1
data[15] => data[15].IN1
data[16] => data[16].IN1
data[17] => data[17].IN1
data[18] => data[18].IN1
data[19] => data[19].IN1
data[20] => data[20].IN1
data[21] => data[21].IN1
data[22] => data[22].IN1
data[23] => data[23].IN1
data[24] => data[24].IN1
data[25] => data[25].IN1
data[26] => data[26].IN1
data[27] => data[27].IN1
data[28] => data[28].IN1
data[29] => data[29].IN1
data[30] => data[30].IN1
data[31] => data[31].IN1
data[32] => data[32].IN1
data[33] => data[33].IN1
data[34] => data[34].IN1
data[35] => data[35].IN1
rdaddress[0] => rdaddress[0].IN1
rdaddress[1] => rdaddress[1].IN1
rdaddress[2] => rdaddress[2].IN1
rdaddress[3] => rdaddress[3].IN1
rdaddress[4] => rdaddress[4].IN1
rdaddress[5] => rdaddress[5].IN1
rdaddress[6] => rdaddress[6].IN1
rdaddress[7] => rdaddress[7].IN1
rdaddress[8] => rdaddress[8].IN1
rdaddress[9] => rdaddress[9].IN1
rdaddress[10] => rdaddress[10].IN1
rdclock => rdclock.IN1
wraddress[0] => wraddress[0].IN1
wraddress[1] => wraddress[1].IN1
wraddress[2] => wraddress[2].IN1
wraddress[3] => wraddress[3].IN1
wraddress[4] => wraddress[4].IN1
wraddress[5] => wraddress[5].IN1
wraddress[6] => wraddress[6].IN1
wraddress[7] => wraddress[7].IN1
wraddress[8] => wraddress[8].IN1
wraddress[9] => wraddress[9].IN1
wraddress[10] => wraddress[10].IN1
wrclock => wrclock.IN1
wren => wren.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b
q[4] <= altsyncram:altsyncram_component.q_b
q[5] <= altsyncram:altsyncram_component.q_b
q[6] <= altsyncram:altsyncram_component.q_b
q[7] <= altsyncram:altsyncram_component.q_b
q[8] <= altsyncram:altsyncram_component.q_b
q[9] <= altsyncram:altsyncram_component.q_b
q[10] <= altsyncram:altsyncram_component.q_b
q[11] <= altsyncram:altsyncram_component.q_b
q[12] <= altsyncram:altsyncram_component.q_b
q[13] <= altsyncram:altsyncram_component.q_b
q[14] <= altsyncram:altsyncram_component.q_b
q[15] <= altsyncram:altsyncram_component.q_b
q[16] <= altsyncram:altsyncram_component.q_b
q[17] <= altsyncram:altsyncram_component.q_b
q[18] <= altsyncram:altsyncram_component.q_b
q[19] <= altsyncram:altsyncram_component.q_b
q[20] <= altsyncram:altsyncram_component.q_b
q[21] <= altsyncram:altsyncram_component.q_b
q[22] <= altsyncram:altsyncram_component.q_b
q[23] <= altsyncram:altsyncram_component.q_b
q[24] <= altsyncram:altsyncram_component.q_b
q[25] <= altsyncram:altsyncram_component.q_b
q[26] <= altsyncram:altsyncram_component.q_b
q[27] <= altsyncram:altsyncram_component.q_b
q[28] <= altsyncram:altsyncram_component.q_b
q[29] <= altsyncram:altsyncram_component.q_b
q[30] <= altsyncram:altsyncram_component.q_b
q[31] <= altsyncram:altsyncram_component.q_b
q[32] <= altsyncram:altsyncram_component.q_b
q[33] <= altsyncram:altsyncram_component.q_b
q[34] <= altsyncram:altsyncram_component.q_b
q[35] <= altsyncram:altsyncram_component.q_b


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component
wren_a => altsyncram_mfg1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_mfg1:auto_generated.data_a[0]
data_a[1] => altsyncram_mfg1:auto_generated.data_a[1]
data_a[2] => altsyncram_mfg1:auto_generated.data_a[2]
data_a[3] => altsyncram_mfg1:auto_generated.data_a[3]
data_a[4] => altsyncram_mfg1:auto_generated.data_a[4]
data_a[5] => altsyncram_mfg1:auto_generated.data_a[5]
data_a[6] => altsyncram_mfg1:auto_generated.data_a[6]
data_a[7] => altsyncram_mfg1:auto_generated.data_a[7]
data_a[8] => altsyncram_mfg1:auto_generated.data_a[8]
data_a[9] => altsyncram_mfg1:auto_generated.data_a[9]
data_a[10] => altsyncram_mfg1:auto_generated.data_a[10]
data_a[11] => altsyncram_mfg1:auto_generated.data_a[11]
data_a[12] => altsyncram_mfg1:auto_generated.data_a[12]
data_a[13] => altsyncram_mfg1:auto_generated.data_a[13]
data_a[14] => altsyncram_mfg1:auto_generated.data_a[14]
data_a[15] => altsyncram_mfg1:auto_generated.data_a[15]
data_a[16] => altsyncram_mfg1:auto_generated.data_a[16]
data_a[17] => altsyncram_mfg1:auto_generated.data_a[17]
data_a[18] => altsyncram_mfg1:auto_generated.data_a[18]
data_a[19] => altsyncram_mfg1:auto_generated.data_a[19]
data_a[20] => altsyncram_mfg1:auto_generated.data_a[20]
data_a[21] => altsyncram_mfg1:auto_generated.data_a[21]
data_a[22] => altsyncram_mfg1:auto_generated.data_a[22]
data_a[23] => altsyncram_mfg1:auto_generated.data_a[23]
data_a[24] => altsyncram_mfg1:auto_generated.data_a[24]
data_a[25] => altsyncram_mfg1:auto_generated.data_a[25]
data_a[26] => altsyncram_mfg1:auto_generated.data_a[26]
data_a[27] => altsyncram_mfg1:auto_generated.data_a[27]
data_a[28] => altsyncram_mfg1:auto_generated.data_a[28]
data_a[29] => altsyncram_mfg1:auto_generated.data_a[29]
data_a[30] => altsyncram_mfg1:auto_generated.data_a[30]
data_a[31] => altsyncram_mfg1:auto_generated.data_a[31]
data_a[32] => altsyncram_mfg1:auto_generated.data_a[32]
data_a[33] => altsyncram_mfg1:auto_generated.data_a[33]
data_a[34] => altsyncram_mfg1:auto_generated.data_a[34]
data_a[35] => altsyncram_mfg1:auto_generated.data_a[35]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
data_b[8] => ~NO_FANOUT~
data_b[9] => ~NO_FANOUT~
data_b[10] => ~NO_FANOUT~
data_b[11] => ~NO_FANOUT~
data_b[12] => ~NO_FANOUT~
data_b[13] => ~NO_FANOUT~
data_b[14] => ~NO_FANOUT~
data_b[15] => ~NO_FANOUT~
data_b[16] => ~NO_FANOUT~
data_b[17] => ~NO_FANOUT~
data_b[18] => ~NO_FANOUT~
data_b[19] => ~NO_FANOUT~
data_b[20] => ~NO_FANOUT~
data_b[21] => ~NO_FANOUT~
data_b[22] => ~NO_FANOUT~
data_b[23] => ~NO_FANOUT~
data_b[24] => ~NO_FANOUT~
data_b[25] => ~NO_FANOUT~
data_b[26] => ~NO_FANOUT~
data_b[27] => ~NO_FANOUT~
data_b[28] => ~NO_FANOUT~
data_b[29] => ~NO_FANOUT~
data_b[30] => ~NO_FANOUT~
data_b[31] => ~NO_FANOUT~
data_b[32] => ~NO_FANOUT~
data_b[33] => ~NO_FANOUT~
data_b[34] => ~NO_FANOUT~
data_b[35] => ~NO_FANOUT~
address_a[0] => altsyncram_mfg1:auto_generated.address_a[0]
address_a[1] => altsyncram_mfg1:auto_generated.address_a[1]
address_a[2] => altsyncram_mfg1:auto_generated.address_a[2]
address_a[3] => altsyncram_mfg1:auto_generated.address_a[3]
address_a[4] => altsyncram_mfg1:auto_generated.address_a[4]
address_a[5] => altsyncram_mfg1:auto_generated.address_a[5]
address_a[6] => altsyncram_mfg1:auto_generated.address_a[6]
address_a[7] => altsyncram_mfg1:auto_generated.address_a[7]
address_a[8] => altsyncram_mfg1:auto_generated.address_a[8]
address_a[9] => altsyncram_mfg1:auto_generated.address_a[9]
address_a[10] => altsyncram_mfg1:auto_generated.address_a[10]
address_b[0] => altsyncram_mfg1:auto_generated.address_b[0]
address_b[1] => altsyncram_mfg1:auto_generated.address_b[1]
address_b[2] => altsyncram_mfg1:auto_generated.address_b[2]
address_b[3] => altsyncram_mfg1:auto_generated.address_b[3]
address_b[4] => altsyncram_mfg1:auto_generated.address_b[4]
address_b[5] => altsyncram_mfg1:auto_generated.address_b[5]
address_b[6] => altsyncram_mfg1:auto_generated.address_b[6]
address_b[7] => altsyncram_mfg1:auto_generated.address_b[7]
address_b[8] => altsyncram_mfg1:auto_generated.address_b[8]
address_b[9] => altsyncram_mfg1:auto_generated.address_b[9]
address_b[10] => altsyncram_mfg1:auto_generated.address_b[10]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_mfg1:auto_generated.clock0
clock1 => altsyncram_mfg1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_a[8] <= <GND>
q_a[9] <= <GND>
q_a[10] <= <GND>
q_a[11] <= <GND>
q_a[12] <= <GND>
q_a[13] <= <GND>
q_a[14] <= <GND>
q_a[15] <= <GND>
q_a[16] <= <GND>
q_a[17] <= <GND>
q_a[18] <= <GND>
q_a[19] <= <GND>
q_a[20] <= <GND>
q_a[21] <= <GND>
q_a[22] <= <GND>
q_a[23] <= <GND>
q_a[24] <= <GND>
q_a[25] <= <GND>
q_a[26] <= <GND>
q_a[27] <= <GND>
q_a[28] <= <GND>
q_a[29] <= <GND>
q_a[30] <= <GND>
q_a[31] <= <GND>
q_a[32] <= <GND>
q_a[33] <= <GND>
q_a[34] <= <GND>
q_a[35] <= <GND>
q_b[0] <= altsyncram_mfg1:auto_generated.q_b[0]
q_b[1] <= altsyncram_mfg1:auto_generated.q_b[1]
q_b[2] <= altsyncram_mfg1:auto_generated.q_b[2]
q_b[3] <= altsyncram_mfg1:auto_generated.q_b[3]
q_b[4] <= altsyncram_mfg1:auto_generated.q_b[4]
q_b[5] <= altsyncram_mfg1:auto_generated.q_b[5]
q_b[6] <= altsyncram_mfg1:auto_generated.q_b[6]
q_b[7] <= altsyncram_mfg1:auto_generated.q_b[7]
q_b[8] <= altsyncram_mfg1:auto_generated.q_b[8]
q_b[9] <= altsyncram_mfg1:auto_generated.q_b[9]
q_b[10] <= altsyncram_mfg1:auto_generated.q_b[10]
q_b[11] <= altsyncram_mfg1:auto_generated.q_b[11]
q_b[12] <= altsyncram_mfg1:auto_generated.q_b[12]
q_b[13] <= altsyncram_mfg1:auto_generated.q_b[13]
q_b[14] <= altsyncram_mfg1:auto_generated.q_b[14]
q_b[15] <= altsyncram_mfg1:auto_generated.q_b[15]
q_b[16] <= altsyncram_mfg1:auto_generated.q_b[16]
q_b[17] <= altsyncram_mfg1:auto_generated.q_b[17]
q_b[18] <= altsyncram_mfg1:auto_generated.q_b[18]
q_b[19] <= altsyncram_mfg1:auto_generated.q_b[19]
q_b[20] <= altsyncram_mfg1:auto_generated.q_b[20]
q_b[21] <= altsyncram_mfg1:auto_generated.q_b[21]
q_b[22] <= altsyncram_mfg1:auto_generated.q_b[22]
q_b[23] <= altsyncram_mfg1:auto_generated.q_b[23]
q_b[24] <= altsyncram_mfg1:auto_generated.q_b[24]
q_b[25] <= altsyncram_mfg1:auto_generated.q_b[25]
q_b[26] <= altsyncram_mfg1:auto_generated.q_b[26]
q_b[27] <= altsyncram_mfg1:auto_generated.q_b[27]
q_b[28] <= altsyncram_mfg1:auto_generated.q_b[28]
q_b[29] <= altsyncram_mfg1:auto_generated.q_b[29]
q_b[30] <= altsyncram_mfg1:auto_generated.q_b[30]
q_b[31] <= altsyncram_mfg1:auto_generated.q_b[31]
q_b[32] <= altsyncram_mfg1:auto_generated.q_b[32]
q_b[33] <= altsyncram_mfg1:auto_generated.q_b[33]
q_b[34] <= altsyncram_mfg1:auto_generated.q_b[34]
q_b[35] <= altsyncram_mfg1:auto_generated.q_b[35]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_mfg1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[0] => ram_block1a32.PORTAADDR
address_a[0] => ram_block1a33.PORTAADDR
address_a[0] => ram_block1a34.PORTAADDR
address_a[0] => ram_block1a35.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[1] => ram_block1a32.PORTAADDR1
address_a[1] => ram_block1a33.PORTAADDR1
address_a[1] => ram_block1a34.PORTAADDR1
address_a[1] => ram_block1a35.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[2] => ram_block1a32.PORTAADDR2
address_a[2] => ram_block1a33.PORTAADDR2
address_a[2] => ram_block1a34.PORTAADDR2
address_a[2] => ram_block1a35.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[3] => ram_block1a32.PORTAADDR3
address_a[3] => ram_block1a33.PORTAADDR3
address_a[3] => ram_block1a34.PORTAADDR3
address_a[3] => ram_block1a35.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_a[4] => ram_block1a32.PORTAADDR4
address_a[4] => ram_block1a33.PORTAADDR4
address_a[4] => ram_block1a34.PORTAADDR4
address_a[4] => ram_block1a35.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_a[5] => ram_block1a24.PORTAADDR5
address_a[5] => ram_block1a25.PORTAADDR5
address_a[5] => ram_block1a26.PORTAADDR5
address_a[5] => ram_block1a27.PORTAADDR5
address_a[5] => ram_block1a28.PORTAADDR5
address_a[5] => ram_block1a29.PORTAADDR5
address_a[5] => ram_block1a30.PORTAADDR5
address_a[5] => ram_block1a31.PORTAADDR5
address_a[5] => ram_block1a32.PORTAADDR5
address_a[5] => ram_block1a33.PORTAADDR5
address_a[5] => ram_block1a34.PORTAADDR5
address_a[5] => ram_block1a35.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[6] => ram_block1a26.PORTAADDR6
address_a[6] => ram_block1a27.PORTAADDR6
address_a[6] => ram_block1a28.PORTAADDR6
address_a[6] => ram_block1a29.PORTAADDR6
address_a[6] => ram_block1a30.PORTAADDR6
address_a[6] => ram_block1a31.PORTAADDR6
address_a[6] => ram_block1a32.PORTAADDR6
address_a[6] => ram_block1a33.PORTAADDR6
address_a[6] => ram_block1a34.PORTAADDR6
address_a[6] => ram_block1a35.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[7] => ram_block1a16.PORTAADDR7
address_a[7] => ram_block1a17.PORTAADDR7
address_a[7] => ram_block1a18.PORTAADDR7
address_a[7] => ram_block1a19.PORTAADDR7
address_a[7] => ram_block1a20.PORTAADDR7
address_a[7] => ram_block1a21.PORTAADDR7
address_a[7] => ram_block1a22.PORTAADDR7
address_a[7] => ram_block1a23.PORTAADDR7
address_a[7] => ram_block1a24.PORTAADDR7
address_a[7] => ram_block1a25.PORTAADDR7
address_a[7] => ram_block1a26.PORTAADDR7
address_a[7] => ram_block1a27.PORTAADDR7
address_a[7] => ram_block1a28.PORTAADDR7
address_a[7] => ram_block1a29.PORTAADDR7
address_a[7] => ram_block1a30.PORTAADDR7
address_a[7] => ram_block1a31.PORTAADDR7
address_a[7] => ram_block1a32.PORTAADDR7
address_a[7] => ram_block1a33.PORTAADDR7
address_a[7] => ram_block1a34.PORTAADDR7
address_a[7] => ram_block1a35.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[8] => ram_block1a16.PORTAADDR8
address_a[8] => ram_block1a17.PORTAADDR8
address_a[8] => ram_block1a18.PORTAADDR8
address_a[8] => ram_block1a19.PORTAADDR8
address_a[8] => ram_block1a20.PORTAADDR8
address_a[8] => ram_block1a21.PORTAADDR8
address_a[8] => ram_block1a22.PORTAADDR8
address_a[8] => ram_block1a23.PORTAADDR8
address_a[8] => ram_block1a24.PORTAADDR8
address_a[8] => ram_block1a25.PORTAADDR8
address_a[8] => ram_block1a26.PORTAADDR8
address_a[8] => ram_block1a27.PORTAADDR8
address_a[8] => ram_block1a28.PORTAADDR8
address_a[8] => ram_block1a29.PORTAADDR8
address_a[8] => ram_block1a30.PORTAADDR8
address_a[8] => ram_block1a31.PORTAADDR8
address_a[8] => ram_block1a32.PORTAADDR8
address_a[8] => ram_block1a33.PORTAADDR8
address_a[8] => ram_block1a34.PORTAADDR8
address_a[8] => ram_block1a35.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[9] => ram_block1a16.PORTAADDR9
address_a[9] => ram_block1a17.PORTAADDR9
address_a[9] => ram_block1a18.PORTAADDR9
address_a[9] => ram_block1a19.PORTAADDR9
address_a[9] => ram_block1a20.PORTAADDR9
address_a[9] => ram_block1a21.PORTAADDR9
address_a[9] => ram_block1a22.PORTAADDR9
address_a[9] => ram_block1a23.PORTAADDR9
address_a[9] => ram_block1a24.PORTAADDR9
address_a[9] => ram_block1a25.PORTAADDR9
address_a[9] => ram_block1a26.PORTAADDR9
address_a[9] => ram_block1a27.PORTAADDR9
address_a[9] => ram_block1a28.PORTAADDR9
address_a[9] => ram_block1a29.PORTAADDR9
address_a[9] => ram_block1a30.PORTAADDR9
address_a[9] => ram_block1a31.PORTAADDR9
address_a[9] => ram_block1a32.PORTAADDR9
address_a[9] => ram_block1a33.PORTAADDR9
address_a[9] => ram_block1a34.PORTAADDR9
address_a[9] => ram_block1a35.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[10] => ram_block1a16.PORTAADDR10
address_a[10] => ram_block1a17.PORTAADDR10
address_a[10] => ram_block1a18.PORTAADDR10
address_a[10] => ram_block1a19.PORTAADDR10
address_a[10] => ram_block1a20.PORTAADDR10
address_a[10] => ram_block1a21.PORTAADDR10
address_a[10] => ram_block1a22.PORTAADDR10
address_a[10] => ram_block1a23.PORTAADDR10
address_a[10] => ram_block1a24.PORTAADDR10
address_a[10] => ram_block1a25.PORTAADDR10
address_a[10] => ram_block1a26.PORTAADDR10
address_a[10] => ram_block1a27.PORTAADDR10
address_a[10] => ram_block1a28.PORTAADDR10
address_a[10] => ram_block1a29.PORTAADDR10
address_a[10] => ram_block1a30.PORTAADDR10
address_a[10] => ram_block1a31.PORTAADDR10
address_a[10] => ram_block1a32.PORTAADDR10
address_a[10] => ram_block1a33.PORTAADDR10
address_a[10] => ram_block1a34.PORTAADDR10
address_a[10] => ram_block1a35.PORTAADDR10
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[0] => ram_block1a8.PORTBADDR
address_b[0] => ram_block1a9.PORTBADDR
address_b[0] => ram_block1a10.PORTBADDR
address_b[0] => ram_block1a11.PORTBADDR
address_b[0] => ram_block1a12.PORTBADDR
address_b[0] => ram_block1a13.PORTBADDR
address_b[0] => ram_block1a14.PORTBADDR
address_b[0] => ram_block1a15.PORTBADDR
address_b[0] => ram_block1a16.PORTBADDR
address_b[0] => ram_block1a17.PORTBADDR
address_b[0] => ram_block1a18.PORTBADDR
address_b[0] => ram_block1a19.PORTBADDR
address_b[0] => ram_block1a20.PORTBADDR
address_b[0] => ram_block1a21.PORTBADDR
address_b[0] => ram_block1a22.PORTBADDR
address_b[0] => ram_block1a23.PORTBADDR
address_b[0] => ram_block1a24.PORTBADDR
address_b[0] => ram_block1a25.PORTBADDR
address_b[0] => ram_block1a26.PORTBADDR
address_b[0] => ram_block1a27.PORTBADDR
address_b[0] => ram_block1a28.PORTBADDR
address_b[0] => ram_block1a29.PORTBADDR
address_b[0] => ram_block1a30.PORTBADDR
address_b[0] => ram_block1a31.PORTBADDR
address_b[0] => ram_block1a32.PORTBADDR
address_b[0] => ram_block1a33.PORTBADDR
address_b[0] => ram_block1a34.PORTBADDR
address_b[0] => ram_block1a35.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[1] => ram_block1a8.PORTBADDR1
address_b[1] => ram_block1a9.PORTBADDR1
address_b[1] => ram_block1a10.PORTBADDR1
address_b[1] => ram_block1a11.PORTBADDR1
address_b[1] => ram_block1a12.PORTBADDR1
address_b[1] => ram_block1a13.PORTBADDR1
address_b[1] => ram_block1a14.PORTBADDR1
address_b[1] => ram_block1a15.PORTBADDR1
address_b[1] => ram_block1a16.PORTBADDR1
address_b[1] => ram_block1a17.PORTBADDR1
address_b[1] => ram_block1a18.PORTBADDR1
address_b[1] => ram_block1a19.PORTBADDR1
address_b[1] => ram_block1a20.PORTBADDR1
address_b[1] => ram_block1a21.PORTBADDR1
address_b[1] => ram_block1a22.PORTBADDR1
address_b[1] => ram_block1a23.PORTBADDR1
address_b[1] => ram_block1a24.PORTBADDR1
address_b[1] => ram_block1a25.PORTBADDR1
address_b[1] => ram_block1a26.PORTBADDR1
address_b[1] => ram_block1a27.PORTBADDR1
address_b[1] => ram_block1a28.PORTBADDR1
address_b[1] => ram_block1a29.PORTBADDR1
address_b[1] => ram_block1a30.PORTBADDR1
address_b[1] => ram_block1a31.PORTBADDR1
address_b[1] => ram_block1a32.PORTBADDR1
address_b[1] => ram_block1a33.PORTBADDR1
address_b[1] => ram_block1a34.PORTBADDR1
address_b[1] => ram_block1a35.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[2] => ram_block1a8.PORTBADDR2
address_b[2] => ram_block1a9.PORTBADDR2
address_b[2] => ram_block1a10.PORTBADDR2
address_b[2] => ram_block1a11.PORTBADDR2
address_b[2] => ram_block1a12.PORTBADDR2
address_b[2] => ram_block1a13.PORTBADDR2
address_b[2] => ram_block1a14.PORTBADDR2
address_b[2] => ram_block1a15.PORTBADDR2
address_b[2] => ram_block1a16.PORTBADDR2
address_b[2] => ram_block1a17.PORTBADDR2
address_b[2] => ram_block1a18.PORTBADDR2
address_b[2] => ram_block1a19.PORTBADDR2
address_b[2] => ram_block1a20.PORTBADDR2
address_b[2] => ram_block1a21.PORTBADDR2
address_b[2] => ram_block1a22.PORTBADDR2
address_b[2] => ram_block1a23.PORTBADDR2
address_b[2] => ram_block1a24.PORTBADDR2
address_b[2] => ram_block1a25.PORTBADDR2
address_b[2] => ram_block1a26.PORTBADDR2
address_b[2] => ram_block1a27.PORTBADDR2
address_b[2] => ram_block1a28.PORTBADDR2
address_b[2] => ram_block1a29.PORTBADDR2
address_b[2] => ram_block1a30.PORTBADDR2
address_b[2] => ram_block1a31.PORTBADDR2
address_b[2] => ram_block1a32.PORTBADDR2
address_b[2] => ram_block1a33.PORTBADDR2
address_b[2] => ram_block1a34.PORTBADDR2
address_b[2] => ram_block1a35.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[3] => ram_block1a8.PORTBADDR3
address_b[3] => ram_block1a9.PORTBADDR3
address_b[3] => ram_block1a10.PORTBADDR3
address_b[3] => ram_block1a11.PORTBADDR3
address_b[3] => ram_block1a12.PORTBADDR3
address_b[3] => ram_block1a13.PORTBADDR3
address_b[3] => ram_block1a14.PORTBADDR3
address_b[3] => ram_block1a15.PORTBADDR3
address_b[3] => ram_block1a16.PORTBADDR3
address_b[3] => ram_block1a17.PORTBADDR3
address_b[3] => ram_block1a18.PORTBADDR3
address_b[3] => ram_block1a19.PORTBADDR3
address_b[3] => ram_block1a20.PORTBADDR3
address_b[3] => ram_block1a21.PORTBADDR3
address_b[3] => ram_block1a22.PORTBADDR3
address_b[3] => ram_block1a23.PORTBADDR3
address_b[3] => ram_block1a24.PORTBADDR3
address_b[3] => ram_block1a25.PORTBADDR3
address_b[3] => ram_block1a26.PORTBADDR3
address_b[3] => ram_block1a27.PORTBADDR3
address_b[3] => ram_block1a28.PORTBADDR3
address_b[3] => ram_block1a29.PORTBADDR3
address_b[3] => ram_block1a30.PORTBADDR3
address_b[3] => ram_block1a31.PORTBADDR3
address_b[3] => ram_block1a32.PORTBADDR3
address_b[3] => ram_block1a33.PORTBADDR3
address_b[3] => ram_block1a34.PORTBADDR3
address_b[3] => ram_block1a35.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[4] => ram_block1a8.PORTBADDR4
address_b[4] => ram_block1a9.PORTBADDR4
address_b[4] => ram_block1a10.PORTBADDR4
address_b[4] => ram_block1a11.PORTBADDR4
address_b[4] => ram_block1a12.PORTBADDR4
address_b[4] => ram_block1a13.PORTBADDR4
address_b[4] => ram_block1a14.PORTBADDR4
address_b[4] => ram_block1a15.PORTBADDR4
address_b[4] => ram_block1a16.PORTBADDR4
address_b[4] => ram_block1a17.PORTBADDR4
address_b[4] => ram_block1a18.PORTBADDR4
address_b[4] => ram_block1a19.PORTBADDR4
address_b[4] => ram_block1a20.PORTBADDR4
address_b[4] => ram_block1a21.PORTBADDR4
address_b[4] => ram_block1a22.PORTBADDR4
address_b[4] => ram_block1a23.PORTBADDR4
address_b[4] => ram_block1a24.PORTBADDR4
address_b[4] => ram_block1a25.PORTBADDR4
address_b[4] => ram_block1a26.PORTBADDR4
address_b[4] => ram_block1a27.PORTBADDR4
address_b[4] => ram_block1a28.PORTBADDR4
address_b[4] => ram_block1a29.PORTBADDR4
address_b[4] => ram_block1a30.PORTBADDR4
address_b[4] => ram_block1a31.PORTBADDR4
address_b[4] => ram_block1a32.PORTBADDR4
address_b[4] => ram_block1a33.PORTBADDR4
address_b[4] => ram_block1a34.PORTBADDR4
address_b[4] => ram_block1a35.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[5] => ram_block1a8.PORTBADDR5
address_b[5] => ram_block1a9.PORTBADDR5
address_b[5] => ram_block1a10.PORTBADDR5
address_b[5] => ram_block1a11.PORTBADDR5
address_b[5] => ram_block1a12.PORTBADDR5
address_b[5] => ram_block1a13.PORTBADDR5
address_b[5] => ram_block1a14.PORTBADDR5
address_b[5] => ram_block1a15.PORTBADDR5
address_b[5] => ram_block1a16.PORTBADDR5
address_b[5] => ram_block1a17.PORTBADDR5
address_b[5] => ram_block1a18.PORTBADDR5
address_b[5] => ram_block1a19.PORTBADDR5
address_b[5] => ram_block1a20.PORTBADDR5
address_b[5] => ram_block1a21.PORTBADDR5
address_b[5] => ram_block1a22.PORTBADDR5
address_b[5] => ram_block1a23.PORTBADDR5
address_b[5] => ram_block1a24.PORTBADDR5
address_b[5] => ram_block1a25.PORTBADDR5
address_b[5] => ram_block1a26.PORTBADDR5
address_b[5] => ram_block1a27.PORTBADDR5
address_b[5] => ram_block1a28.PORTBADDR5
address_b[5] => ram_block1a29.PORTBADDR5
address_b[5] => ram_block1a30.PORTBADDR5
address_b[5] => ram_block1a31.PORTBADDR5
address_b[5] => ram_block1a32.PORTBADDR5
address_b[5] => ram_block1a33.PORTBADDR5
address_b[5] => ram_block1a34.PORTBADDR5
address_b[5] => ram_block1a35.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[6] => ram_block1a8.PORTBADDR6
address_b[6] => ram_block1a9.PORTBADDR6
address_b[6] => ram_block1a10.PORTBADDR6
address_b[6] => ram_block1a11.PORTBADDR6
address_b[6] => ram_block1a12.PORTBADDR6
address_b[6] => ram_block1a13.PORTBADDR6
address_b[6] => ram_block1a14.PORTBADDR6
address_b[6] => ram_block1a15.PORTBADDR6
address_b[6] => ram_block1a16.PORTBADDR6
address_b[6] => ram_block1a17.PORTBADDR6
address_b[6] => ram_block1a18.PORTBADDR6
address_b[6] => ram_block1a19.PORTBADDR6
address_b[6] => ram_block1a20.PORTBADDR6
address_b[6] => ram_block1a21.PORTBADDR6
address_b[6] => ram_block1a22.PORTBADDR6
address_b[6] => ram_block1a23.PORTBADDR6
address_b[6] => ram_block1a24.PORTBADDR6
address_b[6] => ram_block1a25.PORTBADDR6
address_b[6] => ram_block1a26.PORTBADDR6
address_b[6] => ram_block1a27.PORTBADDR6
address_b[6] => ram_block1a28.PORTBADDR6
address_b[6] => ram_block1a29.PORTBADDR6
address_b[6] => ram_block1a30.PORTBADDR6
address_b[6] => ram_block1a31.PORTBADDR6
address_b[6] => ram_block1a32.PORTBADDR6
address_b[6] => ram_block1a33.PORTBADDR6
address_b[6] => ram_block1a34.PORTBADDR6
address_b[6] => ram_block1a35.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[7] => ram_block1a8.PORTBADDR7
address_b[7] => ram_block1a9.PORTBADDR7
address_b[7] => ram_block1a10.PORTBADDR7
address_b[7] => ram_block1a11.PORTBADDR7
address_b[7] => ram_block1a12.PORTBADDR7
address_b[7] => ram_block1a13.PORTBADDR7
address_b[7] => ram_block1a14.PORTBADDR7
address_b[7] => ram_block1a15.PORTBADDR7
address_b[7] => ram_block1a16.PORTBADDR7
address_b[7] => ram_block1a17.PORTBADDR7
address_b[7] => ram_block1a18.PORTBADDR7
address_b[7] => ram_block1a19.PORTBADDR7
address_b[7] => ram_block1a20.PORTBADDR7
address_b[7] => ram_block1a21.PORTBADDR7
address_b[7] => ram_block1a22.PORTBADDR7
address_b[7] => ram_block1a23.PORTBADDR7
address_b[7] => ram_block1a24.PORTBADDR7
address_b[7] => ram_block1a25.PORTBADDR7
address_b[7] => ram_block1a26.PORTBADDR7
address_b[7] => ram_block1a27.PORTBADDR7
address_b[7] => ram_block1a28.PORTBADDR7
address_b[7] => ram_block1a29.PORTBADDR7
address_b[7] => ram_block1a30.PORTBADDR7
address_b[7] => ram_block1a31.PORTBADDR7
address_b[7] => ram_block1a32.PORTBADDR7
address_b[7] => ram_block1a33.PORTBADDR7
address_b[7] => ram_block1a34.PORTBADDR7
address_b[7] => ram_block1a35.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[8] => ram_block1a8.PORTBADDR8
address_b[8] => ram_block1a9.PORTBADDR8
address_b[8] => ram_block1a10.PORTBADDR8
address_b[8] => ram_block1a11.PORTBADDR8
address_b[8] => ram_block1a12.PORTBADDR8
address_b[8] => ram_block1a13.PORTBADDR8
address_b[8] => ram_block1a14.PORTBADDR8
address_b[8] => ram_block1a15.PORTBADDR8
address_b[8] => ram_block1a16.PORTBADDR8
address_b[8] => ram_block1a17.PORTBADDR8
address_b[8] => ram_block1a18.PORTBADDR8
address_b[8] => ram_block1a19.PORTBADDR8
address_b[8] => ram_block1a20.PORTBADDR8
address_b[8] => ram_block1a21.PORTBADDR8
address_b[8] => ram_block1a22.PORTBADDR8
address_b[8] => ram_block1a23.PORTBADDR8
address_b[8] => ram_block1a24.PORTBADDR8
address_b[8] => ram_block1a25.PORTBADDR8
address_b[8] => ram_block1a26.PORTBADDR8
address_b[8] => ram_block1a27.PORTBADDR8
address_b[8] => ram_block1a28.PORTBADDR8
address_b[8] => ram_block1a29.PORTBADDR8
address_b[8] => ram_block1a30.PORTBADDR8
address_b[8] => ram_block1a31.PORTBADDR8
address_b[8] => ram_block1a32.PORTBADDR8
address_b[8] => ram_block1a33.PORTBADDR8
address_b[8] => ram_block1a34.PORTBADDR8
address_b[8] => ram_block1a35.PORTBADDR8
address_b[9] => ram_block1a0.PORTBADDR9
address_b[9] => ram_block1a1.PORTBADDR9
address_b[9] => ram_block1a2.PORTBADDR9
address_b[9] => ram_block1a3.PORTBADDR9
address_b[9] => ram_block1a4.PORTBADDR9
address_b[9] => ram_block1a5.PORTBADDR9
address_b[9] => ram_block1a6.PORTBADDR9
address_b[9] => ram_block1a7.PORTBADDR9
address_b[9] => ram_block1a8.PORTBADDR9
address_b[9] => ram_block1a9.PORTBADDR9
address_b[9] => ram_block1a10.PORTBADDR9
address_b[9] => ram_block1a11.PORTBADDR9
address_b[9] => ram_block1a12.PORTBADDR9
address_b[9] => ram_block1a13.PORTBADDR9
address_b[9] => ram_block1a14.PORTBADDR9
address_b[9] => ram_block1a15.PORTBADDR9
address_b[9] => ram_block1a16.PORTBADDR9
address_b[9] => ram_block1a17.PORTBADDR9
address_b[9] => ram_block1a18.PORTBADDR9
address_b[9] => ram_block1a19.PORTBADDR9
address_b[9] => ram_block1a20.PORTBADDR9
address_b[9] => ram_block1a21.PORTBADDR9
address_b[9] => ram_block1a22.PORTBADDR9
address_b[9] => ram_block1a23.PORTBADDR9
address_b[9] => ram_block1a24.PORTBADDR9
address_b[9] => ram_block1a25.PORTBADDR9
address_b[9] => ram_block1a26.PORTBADDR9
address_b[9] => ram_block1a27.PORTBADDR9
address_b[9] => ram_block1a28.PORTBADDR9
address_b[9] => ram_block1a29.PORTBADDR9
address_b[9] => ram_block1a30.PORTBADDR9
address_b[9] => ram_block1a31.PORTBADDR9
address_b[9] => ram_block1a32.PORTBADDR9
address_b[9] => ram_block1a33.PORTBADDR9
address_b[9] => ram_block1a34.PORTBADDR9
address_b[9] => ram_block1a35.PORTBADDR9
address_b[10] => ram_block1a0.PORTBADDR10
address_b[10] => ram_block1a1.PORTBADDR10
address_b[10] => ram_block1a2.PORTBADDR10
address_b[10] => ram_block1a3.PORTBADDR10
address_b[10] => ram_block1a4.PORTBADDR10
address_b[10] => ram_block1a5.PORTBADDR10
address_b[10] => ram_block1a6.PORTBADDR10
address_b[10] => ram_block1a7.PORTBADDR10
address_b[10] => ram_block1a8.PORTBADDR10
address_b[10] => ram_block1a9.PORTBADDR10
address_b[10] => ram_block1a10.PORTBADDR10
address_b[10] => ram_block1a11.PORTBADDR10
address_b[10] => ram_block1a12.PORTBADDR10
address_b[10] => ram_block1a13.PORTBADDR10
address_b[10] => ram_block1a14.PORTBADDR10
address_b[10] => ram_block1a15.PORTBADDR10
address_b[10] => ram_block1a16.PORTBADDR10
address_b[10] => ram_block1a17.PORTBADDR10
address_b[10] => ram_block1a18.PORTBADDR10
address_b[10] => ram_block1a19.PORTBADDR10
address_b[10] => ram_block1a20.PORTBADDR10
address_b[10] => ram_block1a21.PORTBADDR10
address_b[10] => ram_block1a22.PORTBADDR10
address_b[10] => ram_block1a23.PORTBADDR10
address_b[10] => ram_block1a24.PORTBADDR10
address_b[10] => ram_block1a25.PORTBADDR10
address_b[10] => ram_block1a26.PORTBADDR10
address_b[10] => ram_block1a27.PORTBADDR10
address_b[10] => ram_block1a28.PORTBADDR10
address_b[10] => ram_block1a29.PORTBADDR10
address_b[10] => ram_block1a30.PORTBADDR10
address_b[10] => ram_block1a31.PORTBADDR10
address_b[10] => ram_block1a32.PORTBADDR10
address_b[10] => ram_block1a33.PORTBADDR10
address_b[10] => ram_block1a34.PORTBADDR10
address_b[10] => ram_block1a35.PORTBADDR10
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
clock0 => ram_block1a32.CLK0
clock0 => ram_block1a33.CLK0
clock0 => ram_block1a34.CLK0
clock0 => ram_block1a35.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
clock1 => ram_block1a8.CLK1
clock1 => ram_block1a9.CLK1
clock1 => ram_block1a10.CLK1
clock1 => ram_block1a11.CLK1
clock1 => ram_block1a12.CLK1
clock1 => ram_block1a13.CLK1
clock1 => ram_block1a14.CLK1
clock1 => ram_block1a15.CLK1
clock1 => ram_block1a16.CLK1
clock1 => ram_block1a17.CLK1
clock1 => ram_block1a18.CLK1
clock1 => ram_block1a19.CLK1
clock1 => ram_block1a20.CLK1
clock1 => ram_block1a21.CLK1
clock1 => ram_block1a22.CLK1
clock1 => ram_block1a23.CLK1
clock1 => ram_block1a24.CLK1
clock1 => ram_block1a25.CLK1
clock1 => ram_block1a26.CLK1
clock1 => ram_block1a27.CLK1
clock1 => ram_block1a28.CLK1
clock1 => ram_block1a29.CLK1
clock1 => ram_block1a30.CLK1
clock1 => ram_block1a31.CLK1
clock1 => ram_block1a32.CLK1
clock1 => ram_block1a33.CLK1
clock1 => ram_block1a34.CLK1
clock1 => ram_block1a35.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
data_a[16] => ram_block1a16.PORTADATAIN
data_a[17] => ram_block1a17.PORTADATAIN
data_a[18] => ram_block1a18.PORTADATAIN
data_a[19] => ram_block1a19.PORTADATAIN
data_a[20] => ram_block1a20.PORTADATAIN
data_a[21] => ram_block1a21.PORTADATAIN
data_a[22] => ram_block1a22.PORTADATAIN
data_a[23] => ram_block1a23.PORTADATAIN
data_a[24] => ram_block1a24.PORTADATAIN
data_a[25] => ram_block1a25.PORTADATAIN
data_a[26] => ram_block1a26.PORTADATAIN
data_a[27] => ram_block1a27.PORTADATAIN
data_a[28] => ram_block1a28.PORTADATAIN
data_a[29] => ram_block1a29.PORTADATAIN
data_a[30] => ram_block1a30.PORTADATAIN
data_a[31] => ram_block1a31.PORTADATAIN
data_a[32] => ram_block1a32.PORTADATAIN
data_a[33] => ram_block1a33.PORTADATAIN
data_a[34] => ram_block1a34.PORTADATAIN
data_a[35] => ram_block1a35.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
q_b[8] <= ram_block1a8.PORTBDATAOUT
q_b[9] <= ram_block1a9.PORTBDATAOUT
q_b[10] <= ram_block1a10.PORTBDATAOUT
q_b[11] <= ram_block1a11.PORTBDATAOUT
q_b[12] <= ram_block1a12.PORTBDATAOUT
q_b[13] <= ram_block1a13.PORTBDATAOUT
q_b[14] <= ram_block1a14.PORTBDATAOUT
q_b[15] <= ram_block1a15.PORTBDATAOUT
q_b[16] <= ram_block1a16.PORTBDATAOUT
q_b[17] <= ram_block1a17.PORTBDATAOUT
q_b[18] <= ram_block1a18.PORTBDATAOUT
q_b[19] <= ram_block1a19.PORTBDATAOUT
q_b[20] <= ram_block1a20.PORTBDATAOUT
q_b[21] <= ram_block1a21.PORTBDATAOUT
q_b[22] <= ram_block1a22.PORTBDATAOUT
q_b[23] <= ram_block1a23.PORTBDATAOUT
q_b[24] <= ram_block1a24.PORTBDATAOUT
q_b[25] <= ram_block1a25.PORTBDATAOUT
q_b[26] <= ram_block1a26.PORTBDATAOUT
q_b[27] <= ram_block1a27.PORTBDATAOUT
q_b[28] <= ram_block1a28.PORTBDATAOUT
q_b[29] <= ram_block1a29.PORTBDATAOUT
q_b[30] <= ram_block1a30.PORTBDATAOUT
q_b[31] <= ram_block1a31.PORTBDATAOUT
q_b[32] <= ram_block1a32.PORTBDATAOUT
q_b[33] <= ram_block1a33.PORTBDATAOUT
q_b[34] <= ram_block1a34.PORTBDATAOUT
q_b[35] <= ram_block1a35.PORTBDATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a7.ENA0
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a8.ENA0
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a9.ENA0
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a10.ENA0
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a11.ENA0
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a12.ENA0
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a13.ENA0
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a14.ENA0
wren_a => ram_block1a15.PORTAWE
wren_a => ram_block1a15.ENA0
wren_a => ram_block1a16.PORTAWE
wren_a => ram_block1a16.ENA0
wren_a => ram_block1a17.PORTAWE
wren_a => ram_block1a17.ENA0
wren_a => ram_block1a18.PORTAWE
wren_a => ram_block1a18.ENA0
wren_a => ram_block1a19.PORTAWE
wren_a => ram_block1a19.ENA0
wren_a => ram_block1a20.PORTAWE
wren_a => ram_block1a20.ENA0
wren_a => ram_block1a21.PORTAWE
wren_a => ram_block1a21.ENA0
wren_a => ram_block1a22.PORTAWE
wren_a => ram_block1a22.ENA0
wren_a => ram_block1a23.PORTAWE
wren_a => ram_block1a23.ENA0
wren_a => ram_block1a24.PORTAWE
wren_a => ram_block1a24.ENA0
wren_a => ram_block1a25.PORTAWE
wren_a => ram_block1a25.ENA0
wren_a => ram_block1a26.PORTAWE
wren_a => ram_block1a26.ENA0
wren_a => ram_block1a27.PORTAWE
wren_a => ram_block1a27.ENA0
wren_a => ram_block1a28.PORTAWE
wren_a => ram_block1a28.ENA0
wren_a => ram_block1a29.PORTAWE
wren_a => ram_block1a29.ENA0
wren_a => ram_block1a30.PORTAWE
wren_a => ram_block1a30.ENA0
wren_a => ram_block1a31.PORTAWE
wren_a => ram_block1a31.ENA0
wren_a => ram_block1a32.PORTAWE
wren_a => ram_block1a32.ENA0
wren_a => ram_block1a33.PORTAWE
wren_a => ram_block1a33.ENA0
wren_a => ram_block1a34.PORTAWE
wren_a => ram_block1a34.ENA0
wren_a => ram_block1a35.PORTAWE
wren_a => ram_block1a35.ENA0


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT
clk => g_out[0]~reg0.CLK
clk => g_out[1]~reg0.CLK
clk => g_out[2]~reg0.CLK
clk => g_out[3]~reg0.CLK
clk => g_out[4]~reg0.CLK
clk => g_out[5]~reg0.CLK
clk => g_out[6]~reg0.CLK
clk => g_out[7]~reg0.CLK
clk => g_out[8]~reg0.CLK
clk => g_out[9]~reg0.CLK
clk => g_out[10]~reg0.CLK
clk => b_out[0]~reg0.CLK
clk => b_out[1]~reg0.CLK
clk => b_out[2]~reg0.CLK
clk => b_out[3]~reg0.CLK
clk => b_out[4]~reg0.CLK
clk => b_out[5]~reg0.CLK
clk => b_out[6]~reg0.CLK
clk => b_out[7]~reg0.CLK
clk => b_out[8]~reg0.CLK
clk => b_out[9]~reg0.CLK
clk => b_out[10]~reg0.CLK
clk => b_int[0].CLK
clk => b_int[1].CLK
clk => b_int[2].CLK
clk => b_int[3].CLK
clk => b_int[4].CLK
clk => b_int[5].CLK
clk => b_int[6].CLK
clk => b_int[7].CLK
clk => b_int[8].CLK
clk => b_int[9].CLK
clk => b_int[10].CLK
clkena => always1.IN0
reset => g_out[0]~reg0.ACLR
reset => g_out[1]~reg0.ACLR
reset => g_out[2]~reg0.ACLR
reset => g_out[3]~reg0.ACLR
reset => g_out[4]~reg0.ACLR
reset => g_out[5]~reg0.ACLR
reset => g_out[6]~reg0.ACLR
reset => g_out[7]~reg0.ACLR
reset => g_out[8]~reg0.ACLR
reset => g_out[9]~reg0.ACLR
reset => g_out[10]~reg0.ACLR
reset => b_out[0]~reg0.ACLR
reset => b_out[1]~reg0.ACLR
reset => b_out[2]~reg0.ACLR
reset => b_out[3]~reg0.ACLR
reset => b_out[4]~reg0.ACLR
reset => b_out[5]~reg0.ACLR
reset => b_out[6]~reg0.ACLR
reset => b_out[7]~reg0.ACLR
reset => b_out[8]~reg0.ACLR
reset => b_out[9]~reg0.ACLR
reset => b_out[10]~reg0.ACLR
reset => b_int[0].PRESET
reset => b_int[1].ACLR
reset => b_int[2].ACLR
reset => b_int[3].ACLR
reset => b_int[4].ACLR
reset => b_int[5].ACLR
reset => b_int[6].ACLR
reset => b_int[7].ACLR
reset => b_int[8].ACLR
reset => b_int[9].ACLR
reset => b_int[10].ACLR
enable => always1.IN1
b_out[0] <= b_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[1] <= b_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[2] <= b_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[3] <= b_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[4] <= b_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[5] <= b_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[6] <= b_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[7] <= b_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[8] <= b_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[9] <= b_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[10] <= b_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[0] <= g_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[1] <= g_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[2] <= g_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[3] <= g_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[4] <= g_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[5] <= g_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[6] <= g_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[7] <= g_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[8] <= g_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[9] <= g_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[10] <= g_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD
clk => g_out[0]~reg0.CLK
clk => g_out[1]~reg0.CLK
clk => g_out[2]~reg0.CLK
clk => g_out[3]~reg0.CLK
clk => g_out[4]~reg0.CLK
clk => g_out[5]~reg0.CLK
clk => g_out[6]~reg0.CLK
clk => g_out[7]~reg0.CLK
clk => g_out[8]~reg0.CLK
clk => g_out[9]~reg0.CLK
clk => g_out[10]~reg0.CLK
clk => b_out[0]~reg0.CLK
clk => b_out[1]~reg0.CLK
clk => b_out[2]~reg0.CLK
clk => b_out[3]~reg0.CLK
clk => b_out[4]~reg0.CLK
clk => b_out[5]~reg0.CLK
clk => b_out[6]~reg0.CLK
clk => b_out[7]~reg0.CLK
clk => b_out[8]~reg0.CLK
clk => b_out[9]~reg0.CLK
clk => b_out[10]~reg0.CLK
clk => b_int[0].CLK
clk => b_int[1].CLK
clk => b_int[2].CLK
clk => b_int[3].CLK
clk => b_int[4].CLK
clk => b_int[5].CLK
clk => b_int[6].CLK
clk => b_int[7].CLK
clk => b_int[8].CLK
clk => b_int[9].CLK
clk => b_int[10].CLK
clkena => always1.IN0
reset => g_out[0]~reg0.ACLR
reset => g_out[1]~reg0.ACLR
reset => g_out[2]~reg0.ACLR
reset => g_out[3]~reg0.ACLR
reset => g_out[4]~reg0.ACLR
reset => g_out[5]~reg0.ACLR
reset => g_out[6]~reg0.ACLR
reset => g_out[7]~reg0.ACLR
reset => g_out[8]~reg0.ACLR
reset => g_out[9]~reg0.ACLR
reset => g_out[10]~reg0.ACLR
reset => b_out[0]~reg0.ACLR
reset => b_out[1]~reg0.ACLR
reset => b_out[2]~reg0.ACLR
reset => b_out[3]~reg0.ACLR
reset => b_out[4]~reg0.ACLR
reset => b_out[5]~reg0.ACLR
reset => b_out[6]~reg0.ACLR
reset => b_out[7]~reg0.ACLR
reset => b_out[8]~reg0.ACLR
reset => b_out[9]~reg0.ACLR
reset => b_out[10]~reg0.ACLR
reset => b_int[0].PRESET
reset => b_int[1].ACLR
reset => b_int[2].ACLR
reset => b_int[3].ACLR
reset => b_int[4].ACLR
reset => b_int[5].ACLR
reset => b_int[6].ACLR
reset => b_int[7].ACLR
reset => b_int[8].ACLR
reset => b_int[9].ACLR
reset => b_int[10].ACLR
enable => always1.IN1
b_out[0] <= b_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[1] <= b_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[2] <= b_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[3] <= b_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[4] <= b_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[5] <= b_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[6] <= b_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[7] <= b_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[8] <= b_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[9] <= b_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[10] <= b_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[0] <= g_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[1] <= g_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[2] <= g_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[3] <= g_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[4] <= g_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[5] <= g_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[6] <= g_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[7] <= g_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[8] <= g_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[9] <= g_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[10] <= g_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_1
clk => clk.IN11
reset_n => reset_n.IN11
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
din[9] => din[9].IN1
din[10] => din[10].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout
dout[9] <= altera_std_synchronizer:sync[9].u.dout
dout[10] <= altera_std_synchronizer:sync[10].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[9].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[10].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_2
clk => clk.IN11
reset_n => reset_n.IN11
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
din[9] => din[9].IN1
din[10] => din[10].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout
dout[9] <= altera_std_synchronizer:sync[9].u.dout
dout[10] <= altera_std_synchronizer:sync[10].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[9].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[10].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_3
clk => clk.IN11
reset_n => reset_n.IN11
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
din[9] => din[9].IN1
din[10] => din[10].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout
dout[9] <= altera_std_synchronizer:sync[9].u.dout
dout[10] <= altera_std_synchronizer:sync[10].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[9].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_3|altera_std_synchronizer:sync[10].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_4
clk => clk.IN11
reset_n => reset_n.IN11
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
din[9] => din[9].IN1
din[10] => din[10].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout
dout[9] <= altera_std_synchronizer:sync[9].u.dout
dout[10] <= altera_std_synchronizer:sync[10].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[9].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt_1246:TX_DATA|altera_std_synchronizer_bundle:U_SYNC_4|altera_std_synchronizer:sync[10].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS
reset_wclk => reset_wclk.IN1
reset_rclk => reset_rclk.IN1
wclk => wclk.IN3
wclk_ena => wclk_ena.IN1
wren => wren.IN2
din[0] => din[0].IN1
din[1] => din[1].IN1
rclk => rclk.IN3
rclk_ena => rclk_ena.IN1
rden => rden.IN1
dout[0] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
dout[1] <= altera_tse_altsyncram_dpm_fifo:U_RAM.q
full <= full_flag.DB_MAX_OUTPUT_PORT_TYPE
empty <= empty_flag.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM
data[0] => data[0].IN1
data[1] => data[1].IN1
rdaddress[0] => rdaddress[0].IN1
rdaddress[1] => rdaddress[1].IN1
rdaddress[2] => rdaddress[2].IN1
rdaddress[3] => rdaddress[3].IN1
rdaddress[4] => rdaddress[4].IN1
rdaddress[5] => rdaddress[5].IN1
rdaddress[6] => rdaddress[6].IN1
rdaddress[7] => rdaddress[7].IN1
rdaddress[8] => rdaddress[8].IN1
rdclock => rdclock.IN1
wraddress[0] => wraddress[0].IN1
wraddress[1] => wraddress[1].IN1
wraddress[2] => wraddress[2].IN1
wraddress[3] => wraddress[3].IN1
wraddress[4] => wraddress[4].IN1
wraddress[5] => wraddress[5].IN1
wraddress[6] => wraddress[6].IN1
wraddress[7] => wraddress[7].IN1
wraddress[8] => wraddress[8].IN1
wrclock => wrclock.IN1
wren => wren.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component
wren_a => altsyncram_a6g1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_a6g1:auto_generated.data_a[0]
data_a[1] => altsyncram_a6g1:auto_generated.data_a[1]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
address_a[0] => altsyncram_a6g1:auto_generated.address_a[0]
address_a[1] => altsyncram_a6g1:auto_generated.address_a[1]
address_a[2] => altsyncram_a6g1:auto_generated.address_a[2]
address_a[3] => altsyncram_a6g1:auto_generated.address_a[3]
address_a[4] => altsyncram_a6g1:auto_generated.address_a[4]
address_a[5] => altsyncram_a6g1:auto_generated.address_a[5]
address_a[6] => altsyncram_a6g1:auto_generated.address_a[6]
address_a[7] => altsyncram_a6g1:auto_generated.address_a[7]
address_a[8] => altsyncram_a6g1:auto_generated.address_a[8]
address_b[0] => altsyncram_a6g1:auto_generated.address_b[0]
address_b[1] => altsyncram_a6g1:auto_generated.address_b[1]
address_b[2] => altsyncram_a6g1:auto_generated.address_b[2]
address_b[3] => altsyncram_a6g1:auto_generated.address_b[3]
address_b[4] => altsyncram_a6g1:auto_generated.address_b[4]
address_b[5] => altsyncram_a6g1:auto_generated.address_b[5]
address_b[6] => altsyncram_a6g1:auto_generated.address_b[6]
address_b[7] => altsyncram_a6g1:auto_generated.address_b[7]
address_b[8] => altsyncram_a6g1:auto_generated.address_b[8]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_a6g1:auto_generated.clock0
clock1 => altsyncram_a6g1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_b[0] <= altsyncram_a6g1:auto_generated.q_b[0]
q_b[1] <= altsyncram_a6g1:auto_generated.q_b[1]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_a6g1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a1.ENA0


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT
clk => g_out[0]~reg0.CLK
clk => g_out[1]~reg0.CLK
clk => g_out[2]~reg0.CLK
clk => g_out[3]~reg0.CLK
clk => g_out[4]~reg0.CLK
clk => g_out[5]~reg0.CLK
clk => g_out[6]~reg0.CLK
clk => g_out[7]~reg0.CLK
clk => g_out[8]~reg0.CLK
clk => b_out[0]~reg0.CLK
clk => b_out[1]~reg0.CLK
clk => b_out[2]~reg0.CLK
clk => b_out[3]~reg0.CLK
clk => b_out[4]~reg0.CLK
clk => b_out[5]~reg0.CLK
clk => b_out[6]~reg0.CLK
clk => b_out[7]~reg0.CLK
clk => b_out[8]~reg0.CLK
clk => b_int[0].CLK
clk => b_int[1].CLK
clk => b_int[2].CLK
clk => b_int[3].CLK
clk => b_int[4].CLK
clk => b_int[5].CLK
clk => b_int[6].CLK
clk => b_int[7].CLK
clk => b_int[8].CLK
clkena => always1.IN0
reset => g_out[0]~reg0.ACLR
reset => g_out[1]~reg0.ACLR
reset => g_out[2]~reg0.ACLR
reset => g_out[3]~reg0.ACLR
reset => g_out[4]~reg0.ACLR
reset => g_out[5]~reg0.ACLR
reset => g_out[6]~reg0.ACLR
reset => g_out[7]~reg0.ACLR
reset => g_out[8]~reg0.ACLR
reset => b_out[0]~reg0.ACLR
reset => b_out[1]~reg0.ACLR
reset => b_out[2]~reg0.ACLR
reset => b_out[3]~reg0.ACLR
reset => b_out[4]~reg0.ACLR
reset => b_out[5]~reg0.ACLR
reset => b_out[6]~reg0.ACLR
reset => b_out[7]~reg0.ACLR
reset => b_out[8]~reg0.ACLR
reset => b_int[0].PRESET
reset => b_int[1].ACLR
reset => b_int[2].ACLR
reset => b_int[3].ACLR
reset => b_int[4].ACLR
reset => b_int[5].ACLR
reset => b_int[6].ACLR
reset => b_int[7].ACLR
reset => b_int[8].ACLR
enable => always1.IN1
b_out[0] <= b_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[1] <= b_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[2] <= b_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[3] <= b_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[4] <= b_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[5] <= b_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[6] <= b_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[7] <= b_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[8] <= b_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[0] <= g_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[1] <= g_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[2] <= g_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[3] <= g_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[4] <= g_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[5] <= g_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[6] <= g_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[7] <= g_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[8] <= g_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_RD
clk => g_out[0]~reg0.CLK
clk => g_out[1]~reg0.CLK
clk => g_out[2]~reg0.CLK
clk => g_out[3]~reg0.CLK
clk => g_out[4]~reg0.CLK
clk => g_out[5]~reg0.CLK
clk => g_out[6]~reg0.CLK
clk => g_out[7]~reg0.CLK
clk => g_out[8]~reg0.CLK
clk => b_out[0]~reg0.CLK
clk => b_out[1]~reg0.CLK
clk => b_out[2]~reg0.CLK
clk => b_out[3]~reg0.CLK
clk => b_out[4]~reg0.CLK
clk => b_out[5]~reg0.CLK
clk => b_out[6]~reg0.CLK
clk => b_out[7]~reg0.CLK
clk => b_out[8]~reg0.CLK
clk => b_int[0].CLK
clk => b_int[1].CLK
clk => b_int[2].CLK
clk => b_int[3].CLK
clk => b_int[4].CLK
clk => b_int[5].CLK
clk => b_int[6].CLK
clk => b_int[7].CLK
clk => b_int[8].CLK
clkena => always1.IN0
reset => g_out[0]~reg0.ACLR
reset => g_out[1]~reg0.ACLR
reset => g_out[2]~reg0.ACLR
reset => g_out[3]~reg0.ACLR
reset => g_out[4]~reg0.ACLR
reset => g_out[5]~reg0.ACLR
reset => g_out[6]~reg0.ACLR
reset => g_out[7]~reg0.ACLR
reset => g_out[8]~reg0.ACLR
reset => b_out[0]~reg0.ACLR
reset => b_out[1]~reg0.ACLR
reset => b_out[2]~reg0.ACLR
reset => b_out[3]~reg0.ACLR
reset => b_out[4]~reg0.ACLR
reset => b_out[5]~reg0.ACLR
reset => b_out[6]~reg0.ACLR
reset => b_out[7]~reg0.ACLR
reset => b_out[8]~reg0.ACLR
reset => b_int[0].PRESET
reset => b_int[1].ACLR
reset => b_int[2].ACLR
reset => b_int[3].ACLR
reset => b_int[4].ACLR
reset => b_int[5].ACLR
reset => b_int[6].ACLR
reset => b_int[7].ACLR
reset => b_int[8].ACLR
enable => always1.IN1
b_out[0] <= b_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[1] <= b_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[2] <= b_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[3] <= b_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[4] <= b_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[5] <= b_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[6] <= b_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[7] <= b_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b_out[8] <= b_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[0] <= g_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[1] <= g_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[2] <= g_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[3] <= g_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[4] <= g_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[5] <= g_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[6] <= g_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[7] <= g_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
g_out[8] <= g_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_1
clk => clk.IN9
reset_n => reset_n.IN9
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_1|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_2
clk => clk.IN9
reset_n => reset_n.IN9
din[0] => din[0].IN1
din[1] => din[1].IN1
din[2] => din[2].IN1
din[3] => din[3].IN1
din[4] => din[4].IN1
din[5] => din[5].IN1
din[6] => din[6].IN1
din[7] => din[7].IN1
din[8] => din[8].IN1
dout[0] <= altera_std_synchronizer:sync[0].u.dout
dout[1] <= altera_std_synchronizer:sync[1].u.dout
dout[2] <= altera_std_synchronizer:sync[2].u.dout
dout[3] <= altera_std_synchronizer:sync[3].u.dout
dout[4] <= altera_std_synchronizer:sync[4].u.dout
dout[5] <= altera_std_synchronizer:sync[5].u.dout
dout[6] <= altera_std_synchronizer:sync[6].u.dout
dout[7] <= altera_std_synchronizer:sync[7].u.dout
dout[8] <= altera_std_synchronizer:sync[8].u.dout


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[0].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[1].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[2].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[3].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[4].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[5].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[6].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[7].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_std_synchronizer_bundle:U_SYNC_2|altera_std_synchronizer:sync[8].u
clk => dreg[0].CLK
clk => dreg[1].CLK
clk => din_s1.CLK
reset_n => dreg[0].ACLR
reset_n => dreg[1].ACLR
reset_n => din_s1.ACLR
din => din_s1.DATAIN
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE


|project_top|data_transmit:data_transmit_ins
clk => cnt_pack[0].CLK
clk => cnt_pack[1].CLK
clk => cnt_pack[2].CLK
clk => cnt_pack[3].CLK
clk => cnt_pack[4].CLK
clk => cnt_pack[5].CLK
clk => cnt_pack[6].CLK
clk => cnt_pack[7].CLK
clk => cnt_pack[8].CLK
clk => cnt_pack[9].CLK
clk => cnt_pack[10].CLK
clk => cnt_pack[11].CLK
clk => cnt_pack[12].CLK
clk => cnt_pack[13].CLK
clk => cnt_pack[14].CLK
clk => cnt_pack[15].CLK
clk => ff_tx_eop~reg0.CLK
clk => ff_tx_vld~reg0.CLK
clk => ff_tx_sop~reg0.CLK
clk => start_en.CLK
clk => cnt_sec[0].CLK
clk => cnt_sec[1].CLK
clk => cnt_sec[2].CLK
clk => cnt_sec[3].CLK
clk => cnt_sec[4].CLK
clk => cnt_sec[5].CLK
clk => cnt_sec[6].CLK
clk => cnt_sec[7].CLK
clk => cnt_time[0].CLK
clk => cnt_time[1].CLK
clk => cnt_time[2].CLK
clk => cnt_time[3].CLK
clk => cnt_time[4].CLK
clk => cnt_time[5].CLK
clk => cnt_time[6].CLK
clk => cnt_time[7].CLK
clk => cnt_time[8].CLK
clk => cnt_time[9].CLK
clk => cnt_time[10].CLK
clk => cnt_time[11].CLK
clk => cnt_time[12].CLK
clk => cnt_time[13].CLK
clk => cnt_time[14].CLK
clk => cnt_time[15].CLK
clk => cnt_time[16].CLK
clk => cnt_time[17].CLK
clk => cnt_time[18].CLK
clk => cnt_time[19].CLK
clk => cnt_time[20].CLK
clk => cnt_time[21].CLK
clk => cnt_time[22].CLK
clk => cnt_time[23].CLK
clk => cnt_time[24].CLK
clk => cnt_time[25].CLK
clk => cnt_time[26].CLK
clk => cnt_time[27].CLK
clk => cnt_time[28].CLK
clk => cnt_time[29].CLK
clk => cnt_time[30].CLK
clk => cnt_time[31].CLK
clk => ff_tx_data[0]~reg0.CLK
clk => ff_tx_data[1]~reg0.CLK
clk => ff_tx_data[2]~reg0.CLK
clk => ff_tx_data[3]~reg0.CLK
clk => ff_tx_data[4]~reg0.CLK
clk => ff_tx_data[5]~reg0.CLK
clk => ff_tx_data[6]~reg0.CLK
clk => ff_tx_data[7]~reg0.CLK
clk => ff_tx_data[8]~reg0.CLK
clk => ff_tx_data[9]~reg0.CLK
clk => ff_tx_data[10]~reg0.CLK
clk => ff_tx_data[11]~reg0.CLK
clk => ff_tx_data[12]~reg0.CLK
clk => ff_tx_data[13]~reg0.CLK
clk => ff_tx_data[14]~reg0.CLK
clk => ff_tx_data[15]~reg0.CLK
clk => ff_tx_data[16]~reg0.CLK
clk => ff_tx_data[17]~reg0.CLK
clk => ff_tx_data[18]~reg0.CLK
clk => ff_tx_data[19]~reg0.CLK
clk => ff_tx_data[20]~reg0.CLK
clk => ff_tx_data[21]~reg0.CLK
clk => ff_tx_data[22]~reg0.CLK
clk => ff_tx_data[23]~reg0.CLK
clk => ff_tx_data[24]~reg0.CLK
clk => ff_tx_data[25]~reg0.CLK
clk => ff_tx_data[26]~reg0.CLK
clk => ff_tx_data[27]~reg0.CLK
clk => ff_tx_data[28]~reg0.CLK
clk => ff_tx_data[29]~reg0.CLK
clk => ff_tx_data[30]~reg0.CLK
clk => ff_tx_data[31]~reg0.CLK
clk => cnt_zu[0].CLK
clk => cnt_zu[1].CLK
clk => cnt_data[0].CLK
clk => cnt_data[1].CLK
clk => cnt_data[2].CLK
clk => cnt_data[3].CLK
clk => cnt_data[4].CLK
clk => cnt_data[5].CLK
clk => cnt_data[6].CLK
clk => cnt_data[7].CLK
clk => cnt_data[8].CLK
clk => cnt_data[9].CLK
clk => cnt_data[10].CLK
clk => cnt_data[11].CLK
clk => cnt_data[12].CLK
clk => cnt_data[13].CLK
clk => cnt_data[14].CLK
clk => cnt_data[15].CLK
clk => ip_sum3_0[0].CLK
clk => ip_sum3_0[1].CLK
clk => ip_sum3_0[2].CLK
clk => ip_sum3_0[3].CLK
clk => ip_sum3_0[4].CLK
clk => ip_sum3_0[5].CLK
clk => ip_sum3_0[6].CLK
clk => ip_sum3_0[7].CLK
clk => ip_sum3_0[8].CLK
clk => ip_sum3_0[9].CLK
clk => ip_sum3_0[10].CLK
clk => ip_sum3_0[11].CLK
clk => ip_sum3_0[12].CLK
clk => ip_sum3_0[13].CLK
clk => ip_sum3_0[14].CLK
clk => ip_sum3_0[15].CLK
clk => ip_sum2_1[0].CLK
clk => ip_sum2_1[1].CLK
clk => ip_sum2_1[2].CLK
clk => ip_sum2_1[3].CLK
clk => ip_sum2_1[4].CLK
clk => ip_sum2_1[5].CLK
clk => ip_sum2_1[6].CLK
clk => ip_sum2_1[7].CLK
clk => ip_sum2_1[8].CLK
clk => ip_sum2_1[9].CLK
clk => ip_sum2_1[10].CLK
clk => ip_sum2_1[11].CLK
clk => ip_sum2_1[12].CLK
clk => ip_sum2_1[13].CLK
clk => ip_sum2_1[14].CLK
clk => ip_sum2_1[15].CLK
clk => ip_sum2_0[0].CLK
clk => ip_sum2_0[1].CLK
clk => ip_sum2_0[2].CLK
clk => ip_sum2_0[3].CLK
clk => ip_sum2_0[4].CLK
clk => ip_sum2_0[5].CLK
clk => ip_sum2_0[6].CLK
clk => ip_sum2_0[7].CLK
clk => ip_sum2_0[8].CLK
clk => ip_sum2_0[9].CLK
clk => ip_sum2_0[10].CLK
clk => ip_sum2_0[11].CLK
clk => ip_sum2_0[12].CLK
clk => ip_sum2_0[13].CLK
clk => ip_sum2_0[14].CLK
clk => ip_sum2_0[15].CLK
clk => ip_sum1_2[0].CLK
clk => ip_sum1_2[1].CLK
clk => ip_sum1_2[2].CLK
clk => ip_sum1_2[3].CLK
clk => ip_sum1_2[4].CLK
clk => ip_sum1_2[5].CLK
clk => ip_sum1_2[6].CLK
clk => ip_sum1_2[7].CLK
clk => ip_sum1_2[8].CLK
clk => ip_sum1_2[9].CLK
clk => ip_sum1_2[10].CLK
clk => ip_sum1_2[11].CLK
clk => ip_sum1_2[12].CLK
clk => ip_sum1_2[13].CLK
clk => ip_sum1_2[14].CLK
clk => ip_sum1_2[15].CLK
clk => ip_sum1_1[0].CLK
clk => ip_sum1_1[1].CLK
clk => ip_sum1_1[2].CLK
clk => ip_sum1_1[3].CLK
clk => ip_sum1_1[4].CLK
clk => ip_sum1_1[5].CLK
clk => ip_sum1_1[6].CLK
clk => ip_sum1_1[7].CLK
clk => ip_sum1_1[8].CLK
clk => ip_sum1_1[9].CLK
clk => ip_sum1_1[10].CLK
clk => ip_sum1_1[11].CLK
clk => ip_sum1_1[12].CLK
clk => ip_sum1_1[13].CLK
clk => ip_sum1_1[14].CLK
clk => ip_sum1_1[15].CLK
clk => ip_sum1_0[0].CLK
clk => ip_sum1_0[1].CLK
clk => ip_sum1_0[2].CLK
clk => ip_sum1_0[3].CLK
clk => ip_sum1_0[4].CLK
clk => ip_sum1_0[5].CLK
clk => ip_sum1_0[6].CLK
clk => ip_sum1_0[7].CLK
clk => ip_sum1_0[8].CLK
clk => ip_sum1_0[9].CLK
clk => ip_sum1_0[10].CLK
clk => ip_sum1_0[11].CLK
clk => ip_sum1_0[12].CLK
clk => ip_sum1_0[13].CLK
clk => ip_sum1_0[14].CLK
clk => ip_sum1_0[15].CLK
clk => ip_sum0_4[0].CLK
clk => ip_sum0_4[1].CLK
clk => ip_sum0_4[2].CLK
clk => ip_sum0_4[3].CLK
clk => ip_sum0_4[4].CLK
clk => ip_sum0_4[5].CLK
clk => ip_sum0_4[6].CLK
clk => ip_sum0_4[7].CLK
clk => ip_sum0_4[8].CLK
clk => ip_sum0_4[9].CLK
clk => ip_sum0_4[10].CLK
clk => ip_sum0_4[11].CLK
clk => ip_sum0_4[12].CLK
clk => ip_sum0_4[13].CLK
clk => ip_sum0_4[14].CLK
clk => ip_sum0_4[15].CLK
clk => ip_sum0_3[0].CLK
clk => ip_sum0_3[1].CLK
clk => ip_sum0_3[2].CLK
clk => ip_sum0_3[3].CLK
clk => ip_sum0_3[4].CLK
clk => ip_sum0_3[5].CLK
clk => ip_sum0_3[6].CLK
clk => ip_sum0_3[7].CLK
clk => ip_sum0_3[8].CLK
clk => ip_sum0_3[9].CLK
clk => ip_sum0_3[10].CLK
clk => ip_sum0_3[11].CLK
clk => ip_sum0_3[12].CLK
clk => ip_sum0_3[13].CLK
clk => ip_sum0_3[14].CLK
clk => ip_sum0_3[15].CLK
clk => ip_sum0_2[0].CLK
clk => ip_sum0_2[1].CLK
clk => ip_sum0_2[2].CLK
clk => ip_sum0_2[3].CLK
clk => ip_sum0_2[4].CLK
clk => ip_sum0_2[5].CLK
clk => ip_sum0_2[6].CLK
clk => ip_sum0_2[7].CLK
clk => ip_sum0_2[8].CLK
clk => ip_sum0_2[9].CLK
clk => ip_sum0_2[10].CLK
clk => ip_sum0_2[11].CLK
clk => ip_sum0_2[12].CLK
clk => ip_sum0_2[13].CLK
clk => ip_sum0_2[14].CLK
clk => ip_sum0_2[15].CLK
clk => ip_sum0_1[0].CLK
clk => ip_sum0_1[1].CLK
clk => ip_sum0_1[2].CLK
clk => ip_sum0_1[3].CLK
clk => ip_sum0_1[4].CLK
clk => ip_sum0_1[5].CLK
clk => ip_sum0_1[6].CLK
clk => ip_sum0_1[7].CLK
clk => ip_sum0_1[8].CLK
clk => ip_sum0_1[9].CLK
clk => ip_sum0_1[10].CLK
clk => ip_sum0_1[11].CLK
clk => ip_sum0_1[12].CLK
clk => ip_sum0_1[13].CLK
clk => ip_sum0_1[14].CLK
clk => ip_sum0_1[15].CLK
clk => ip_sum0_0[0].CLK
clk => ip_sum0_0[1].CLK
clk => ip_sum0_0[2].CLK
clk => ip_sum0_0[3].CLK
clk => ip_sum0_0[4].CLK
clk => ip_sum0_0[5].CLK
clk => ip_sum0_0[6].CLK
clk => ip_sum0_0[7].CLK
clk => ip_sum0_0[8].CLK
clk => ip_sum0_0[9].CLK
clk => ip_sum0_0[10].CLK
clk => ip_sum0_0[11].CLK
clk => ip_sum0_0[12].CLK
clk => ip_sum0_0[13].CLK
clk => ip_sum0_0[14].CLK
clk => ip_sum0_0[15].CLK
rst_n => ip_sum0_4[0].ACLR
rst_n => ip_sum0_4[1].ACLR
rst_n => ip_sum0_4[2].ACLR
rst_n => ip_sum0_4[3].ACLR
rst_n => ip_sum0_4[4].ACLR
rst_n => ip_sum0_4[5].ACLR
rst_n => ip_sum0_4[6].ACLR
rst_n => ip_sum0_4[7].ACLR
rst_n => ip_sum0_4[8].ACLR
rst_n => ip_sum0_4[9].ACLR
rst_n => ip_sum0_4[10].ACLR
rst_n => ip_sum0_4[11].ACLR
rst_n => ip_sum0_4[12].ACLR
rst_n => ip_sum0_4[13].ACLR
rst_n => ip_sum0_4[14].ACLR
rst_n => ip_sum0_4[15].ACLR
rst_n => ip_sum0_3[0].ACLR
rst_n => ip_sum0_3[1].ACLR
rst_n => ip_sum0_3[2].ACLR
rst_n => ip_sum0_3[3].ACLR
rst_n => ip_sum0_3[4].ACLR
rst_n => ip_sum0_3[5].ACLR
rst_n => ip_sum0_3[6].ACLR
rst_n => ip_sum0_3[7].ACLR
rst_n => ip_sum0_3[8].ACLR
rst_n => ip_sum0_3[9].ACLR
rst_n => ip_sum0_3[10].ACLR
rst_n => ip_sum0_3[11].ACLR
rst_n => ip_sum0_3[12].ACLR
rst_n => ip_sum0_3[13].ACLR
rst_n => ip_sum0_3[14].ACLR
rst_n => ip_sum0_3[15].ACLR
rst_n => ip_sum0_2[0].ACLR
rst_n => ip_sum0_2[1].ACLR
rst_n => ip_sum0_2[2].ACLR
rst_n => ip_sum0_2[3].ACLR
rst_n => ip_sum0_2[4].ACLR
rst_n => ip_sum0_2[5].ACLR
rst_n => ip_sum0_2[6].ACLR
rst_n => ip_sum0_2[7].ACLR
rst_n => ip_sum0_2[8].ACLR
rst_n => ip_sum0_2[9].ACLR
rst_n => ip_sum0_2[10].ACLR
rst_n => ip_sum0_2[11].ACLR
rst_n => ip_sum0_2[12].ACLR
rst_n => ip_sum0_2[13].ACLR
rst_n => ip_sum0_2[14].ACLR
rst_n => ip_sum0_2[15].ACLR
rst_n => ip_sum0_1[0].ACLR
rst_n => ip_sum0_1[1].ACLR
rst_n => ip_sum0_1[2].ACLR
rst_n => ip_sum0_1[3].ACLR
rst_n => ip_sum0_1[4].ACLR
rst_n => ip_sum0_1[5].ACLR
rst_n => ip_sum0_1[6].ACLR
rst_n => ip_sum0_1[7].ACLR
rst_n => ip_sum0_1[8].ACLR
rst_n => ip_sum0_1[9].ACLR
rst_n => ip_sum0_1[10].ACLR
rst_n => ip_sum0_1[11].ACLR
rst_n => ip_sum0_1[12].ACLR
rst_n => ip_sum0_1[13].ACLR
rst_n => ip_sum0_1[14].ACLR
rst_n => ip_sum0_1[15].ACLR
rst_n => ip_sum0_0[0].ACLR
rst_n => ip_sum0_0[1].ACLR
rst_n => ip_sum0_0[2].ACLR
rst_n => ip_sum0_0[3].ACLR
rst_n => ip_sum0_0[4].ACLR
rst_n => ip_sum0_0[5].ACLR
rst_n => ip_sum0_0[6].ACLR
rst_n => ip_sum0_0[7].ACLR
rst_n => ip_sum0_0[8].ACLR
rst_n => ip_sum0_0[9].ACLR
rst_n => ip_sum0_0[10].ACLR
rst_n => ip_sum0_0[11].ACLR
rst_n => ip_sum0_0[12].ACLR
rst_n => ip_sum0_0[13].ACLR
rst_n => ip_sum0_0[14].ACLR
rst_n => ip_sum0_0[15].ACLR
rst_n => ff_tx_data[0]~reg0.ACLR
rst_n => ff_tx_data[1]~reg0.ACLR
rst_n => ff_tx_data[2]~reg0.ACLR
rst_n => ff_tx_data[3]~reg0.ACLR
rst_n => ff_tx_data[4]~reg0.ACLR
rst_n => ff_tx_data[5]~reg0.ACLR
rst_n => ff_tx_data[6]~reg0.ACLR
rst_n => ff_tx_data[7]~reg0.ACLR
rst_n => ff_tx_data[8]~reg0.ACLR
rst_n => ff_tx_data[9]~reg0.ACLR
rst_n => ff_tx_data[10]~reg0.ACLR
rst_n => ff_tx_data[11]~reg0.ACLR
rst_n => ff_tx_data[12]~reg0.ACLR
rst_n => ff_tx_data[13]~reg0.ACLR
rst_n => ff_tx_data[14]~reg0.ACLR
rst_n => ff_tx_data[15]~reg0.ACLR
rst_n => ff_tx_data[16]~reg0.ACLR
rst_n => ff_tx_data[17]~reg0.ACLR
rst_n => ff_tx_data[18]~reg0.ACLR
rst_n => ff_tx_data[19]~reg0.ACLR
rst_n => ff_tx_data[20]~reg0.ACLR
rst_n => ff_tx_data[21]~reg0.ACLR
rst_n => ff_tx_data[22]~reg0.ACLR
rst_n => ff_tx_data[23]~reg0.ACLR
rst_n => ff_tx_data[24]~reg0.ACLR
rst_n => ff_tx_data[25]~reg0.ACLR
rst_n => ff_tx_data[26]~reg0.ACLR
rst_n => ff_tx_data[27]~reg0.ACLR
rst_n => ff_tx_data[28]~reg0.ACLR
rst_n => ff_tx_data[29]~reg0.ACLR
rst_n => ff_tx_data[30]~reg0.ACLR
rst_n => ff_tx_data[31]~reg0.ACLR
rst_n => ff_tx_vld~reg0.ACLR
rst_n => ff_tx_sop~reg0.ACLR
rst_n => ff_tx_eop~reg0.ACLR
rst_n => ip_sum1_2[0].ACLR
rst_n => ip_sum1_2[1].ACLR
rst_n => ip_sum1_2[2].ACLR
rst_n => ip_sum1_2[3].ACLR
rst_n => ip_sum1_2[4].ACLR
rst_n => ip_sum1_2[5].ACLR
rst_n => ip_sum1_2[6].ACLR
rst_n => ip_sum1_2[7].ACLR
rst_n => ip_sum1_2[8].ACLR
rst_n => ip_sum1_2[9].ACLR
rst_n => ip_sum1_2[10].ACLR
rst_n => ip_sum1_2[11].ACLR
rst_n => ip_sum1_2[12].ACLR
rst_n => ip_sum1_2[13].ACLR
rst_n => ip_sum1_2[14].ACLR
rst_n => ip_sum1_2[15].ACLR
rst_n => ip_sum1_1[0].ACLR
rst_n => ip_sum1_1[1].ACLR
rst_n => ip_sum1_1[2].ACLR
rst_n => ip_sum1_1[3].ACLR
rst_n => ip_sum1_1[4].ACLR
rst_n => ip_sum1_1[5].ACLR
rst_n => ip_sum1_1[6].ACLR
rst_n => ip_sum1_1[7].ACLR
rst_n => ip_sum1_1[8].ACLR
rst_n => ip_sum1_1[9].ACLR
rst_n => ip_sum1_1[10].ACLR
rst_n => ip_sum1_1[11].ACLR
rst_n => ip_sum1_1[12].ACLR
rst_n => ip_sum1_1[13].ACLR
rst_n => ip_sum1_1[14].ACLR
rst_n => ip_sum1_1[15].ACLR
rst_n => ip_sum1_0[0].ACLR
rst_n => ip_sum1_0[1].ACLR
rst_n => ip_sum1_0[2].ACLR
rst_n => ip_sum1_0[3].ACLR
rst_n => ip_sum1_0[4].ACLR
rst_n => ip_sum1_0[5].ACLR
rst_n => ip_sum1_0[6].ACLR
rst_n => ip_sum1_0[7].ACLR
rst_n => ip_sum1_0[8].ACLR
rst_n => ip_sum1_0[9].ACLR
rst_n => ip_sum1_0[10].ACLR
rst_n => ip_sum1_0[11].ACLR
rst_n => ip_sum1_0[12].ACLR
rst_n => ip_sum1_0[13].ACLR
rst_n => ip_sum1_0[14].ACLR
rst_n => ip_sum1_0[15].ACLR
rst_n => ip_sum2_1[0].ACLR
rst_n => ip_sum2_1[1].ACLR
rst_n => ip_sum2_1[2].ACLR
rst_n => ip_sum2_1[3].ACLR
rst_n => ip_sum2_1[4].ACLR
rst_n => ip_sum2_1[5].ACLR
rst_n => ip_sum2_1[6].ACLR
rst_n => ip_sum2_1[7].ACLR
rst_n => ip_sum2_1[8].ACLR
rst_n => ip_sum2_1[9].ACLR
rst_n => ip_sum2_1[10].ACLR
rst_n => ip_sum2_1[11].ACLR
rst_n => ip_sum2_1[12].ACLR
rst_n => ip_sum2_1[13].ACLR
rst_n => ip_sum2_1[14].ACLR
rst_n => ip_sum2_1[15].ACLR
rst_n => ip_sum2_0[0].ACLR
rst_n => ip_sum2_0[1].ACLR
rst_n => ip_sum2_0[2].ACLR
rst_n => ip_sum2_0[3].ACLR
rst_n => ip_sum2_0[4].ACLR
rst_n => ip_sum2_0[5].ACLR
rst_n => ip_sum2_0[6].ACLR
rst_n => ip_sum2_0[7].ACLR
rst_n => ip_sum2_0[8].ACLR
rst_n => ip_sum2_0[9].ACLR
rst_n => ip_sum2_0[10].ACLR
rst_n => ip_sum2_0[11].ACLR
rst_n => ip_sum2_0[12].ACLR
rst_n => ip_sum2_0[13].ACLR
rst_n => ip_sum2_0[14].ACLR
rst_n => ip_sum2_0[15].ACLR
rst_n => ip_sum3_0[0].PRESET
rst_n => ip_sum3_0[1].PRESET
rst_n => ip_sum3_0[2].PRESET
rst_n => ip_sum3_0[3].PRESET
rst_n => ip_sum3_0[4].PRESET
rst_n => ip_sum3_0[5].PRESET
rst_n => ip_sum3_0[6].PRESET
rst_n => ip_sum3_0[7].PRESET
rst_n => ip_sum3_0[8].PRESET
rst_n => ip_sum3_0[9].PRESET
rst_n => ip_sum3_0[10].PRESET
rst_n => ip_sum3_0[11].PRESET
rst_n => ip_sum3_0[12].PRESET
rst_n => ip_sum3_0[13].PRESET
rst_n => ip_sum3_0[14].PRESET
rst_n => ip_sum3_0[15].PRESET
rst_n => cnt_data[0].ACLR
rst_n => cnt_data[1].ACLR
rst_n => cnt_data[2].ACLR
rst_n => cnt_data[3].ACLR
rst_n => cnt_data[4].ACLR
rst_n => cnt_data[5].ACLR
rst_n => cnt_data[6].ACLR
rst_n => cnt_data[7].ACLR
rst_n => cnt_data[8].ACLR
rst_n => cnt_data[9].ACLR
rst_n => cnt_data[10].ACLR
rst_n => cnt_data[11].ACLR
rst_n => cnt_data[12].ACLR
rst_n => cnt_data[13].ACLR
rst_n => cnt_data[14].ACLR
rst_n => cnt_data[15].ACLR
rst_n => cnt_zu[0].ACLR
rst_n => cnt_zu[1].ACLR
rst_n => cnt_time[0].ACLR
rst_n => cnt_time[1].ACLR
rst_n => cnt_time[2].ACLR
rst_n => cnt_time[3].ACLR
rst_n => cnt_time[4].ACLR
rst_n => cnt_time[5].ACLR
rst_n => cnt_time[6].ACLR
rst_n => cnt_time[7].ACLR
rst_n => cnt_time[8].ACLR
rst_n => cnt_time[9].ACLR
rst_n => cnt_time[10].ACLR
rst_n => cnt_time[11].ACLR
rst_n => cnt_time[12].ACLR
rst_n => cnt_time[13].ACLR
rst_n => cnt_time[14].ACLR
rst_n => cnt_time[15].ACLR
rst_n => cnt_time[16].ACLR
rst_n => cnt_time[17].ACLR
rst_n => cnt_time[18].ACLR
rst_n => cnt_time[19].ACLR
rst_n => cnt_time[20].ACLR
rst_n => cnt_time[21].ACLR
rst_n => cnt_time[22].ACLR
rst_n => cnt_time[23].ACLR
rst_n => cnt_time[24].ACLR
rst_n => cnt_time[25].ACLR
rst_n => cnt_time[26].ACLR
rst_n => cnt_time[27].ACLR
rst_n => cnt_time[28].ACLR
rst_n => cnt_time[29].ACLR
rst_n => cnt_time[30].ACLR
rst_n => cnt_time[31].ACLR
rst_n => cnt_sec[0].ACLR
rst_n => cnt_sec[1].ACLR
rst_n => cnt_sec[2].ACLR
rst_n => cnt_sec[3].ACLR
rst_n => cnt_sec[4].ACLR
rst_n => cnt_sec[5].ACLR
rst_n => cnt_sec[6].ACLR
rst_n => cnt_sec[7].ACLR
rst_n => start_en.ACLR
rst_n => cnt_pack[0].ACLR
rst_n => cnt_pack[1].ACLR
rst_n => cnt_pack[2].ACLR
rst_n => cnt_pack[3].ACLR
rst_n => cnt_pack[4].ACLR
rst_n => cnt_pack[5].ACLR
rst_n => cnt_pack[6].ACLR
rst_n => cnt_pack[7].ACLR
rst_n => cnt_pack[8].ACLR
rst_n => cnt_pack[9].ACLR
rst_n => cnt_pack[10].ACLR
rst_n => cnt_pack[11].ACLR
rst_n => cnt_pack[12].ACLR
rst_n => cnt_pack[13].ACLR
rst_n => cnt_pack[14].ACLR
rst_n => cnt_pack[15].ACLR
mac_sour[0] => Mux31.IN376
mac_sour[1] => Mux30.IN375
mac_sour[2] => Mux29.IN374
mac_sour[3] => Mux28.IN373
mac_sour[4] => Mux27.IN372
mac_sour[5] => Mux26.IN371
mac_sour[6] => Mux25.IN370
mac_sour[7] => Mux24.IN369
mac_sour[8] => Mux23.IN368
mac_sour[9] => Mux22.IN367
mac_sour[10] => Mux21.IN366
mac_sour[11] => Mux20.IN365
mac_sour[12] => Mux19.IN364
mac_sour[13] => Mux18.IN363
mac_sour[14] => Mux17.IN362
mac_sour[15] => Mux16.IN361
mac_sour[16] => Mux15.IN360
mac_sour[17] => Mux14.IN359
mac_sour[18] => Mux13.IN358
mac_sour[19] => Mux12.IN357
mac_sour[20] => Mux11.IN356
mac_sour[21] => Mux10.IN355
mac_sour[22] => Mux9.IN354
mac_sour[23] => Mux8.IN353
mac_sour[24] => Mux7.IN352
mac_sour[25] => Mux6.IN351
mac_sour[26] => Mux5.IN350
mac_sour[27] => Mux4.IN349
mac_sour[28] => Mux3.IN348
mac_sour[29] => Mux2.IN347
mac_sour[30] => Mux1.IN346
mac_sour[31] => Mux0.IN345
mac_sour[32] => Mux31.IN344
mac_sour[33] => Mux30.IN343
mac_sour[34] => Mux29.IN342
mac_sour[35] => Mux28.IN341
mac_sour[36] => Mux27.IN340
mac_sour[37] => Mux26.IN339
mac_sour[38] => Mux25.IN338
mac_sour[39] => Mux24.IN337
mac_sour[40] => Mux23.IN336
mac_sour[41] => Mux22.IN335
mac_sour[42] => Mux21.IN334
mac_sour[43] => Mux20.IN333
mac_sour[44] => Mux19.IN332
mac_sour[45] => Mux18.IN331
mac_sour[46] => Mux17.IN330
mac_sour[47] => Mux16.IN329
mac_self[0] => Mux15.IN424
mac_self[1] => Mux14.IN423
mac_self[2] => Mux13.IN422
mac_self[3] => Mux12.IN421
mac_self[4] => Mux11.IN420
mac_self[5] => Mux10.IN419
mac_self[6] => Mux9.IN418
mac_self[7] => Mux8.IN417
mac_self[8] => Mux7.IN416
mac_self[9] => Mux6.IN415
mac_self[10] => Mux5.IN414
mac_self[11] => Mux4.IN413
mac_self[12] => Mux3.IN412
mac_self[13] => Mux2.IN411
mac_self[14] => Mux1.IN410
mac_self[15] => Mux0.IN409
mac_self[16] => Mux31.IN408
mac_self[17] => Mux30.IN407
mac_self[18] => Mux29.IN406
mac_self[19] => Mux28.IN405
mac_self[20] => Mux27.IN404
mac_self[21] => Mux26.IN403
mac_self[22] => Mux25.IN402
mac_self[23] => Mux24.IN401
mac_self[24] => Mux23.IN400
mac_self[25] => Mux22.IN399
mac_self[26] => Mux21.IN398
mac_self[27] => Mux20.IN397
mac_self[28] => Mux19.IN396
mac_self[29] => Mux18.IN395
mac_self[30] => Mux17.IN394
mac_self[31] => Mux16.IN393
mac_self[32] => Mux15.IN392
mac_self[33] => Mux14.IN391
mac_self[34] => Mux13.IN390
mac_self[35] => Mux12.IN389
mac_self[36] => Mux11.IN388
mac_self[37] => Mux10.IN387
mac_self[38] => Mux9.IN386
mac_self[39] => Mux8.IN385
mac_self[40] => Mux7.IN384
mac_self[41] => Mux6.IN383
mac_self[42] => Mux5.IN382
mac_self[43] => Mux4.IN381
mac_self[44] => Mux3.IN380
mac_self[45] => Mux2.IN379
mac_self[46] => Mux1.IN378
mac_self[47] => Mux0.IN377
ip_sour[0] => Mux31.IN520
ip_sour[0] => Add4.IN32
ip_sour[1] => Mux30.IN519
ip_sour[1] => Add4.IN31
ip_sour[2] => Mux29.IN518
ip_sour[2] => Add4.IN30
ip_sour[3] => Mux28.IN517
ip_sour[3] => Add4.IN29
ip_sour[4] => Mux27.IN516
ip_sour[4] => Add4.IN28
ip_sour[5] => Mux26.IN515
ip_sour[5] => Add4.IN27
ip_sour[6] => Mux25.IN514
ip_sour[6] => Add4.IN26
ip_sour[7] => Mux24.IN513
ip_sour[7] => Add4.IN25
ip_sour[8] => Mux23.IN512
ip_sour[8] => Add4.IN24
ip_sour[9] => Mux22.IN511
ip_sour[9] => Add4.IN23
ip_sour[10] => Mux21.IN510
ip_sour[10] => Add4.IN22
ip_sour[11] => Mux20.IN509
ip_sour[11] => Add4.IN21
ip_sour[12] => Mux19.IN508
ip_sour[12] => Add4.IN20
ip_sour[13] => Mux18.IN507
ip_sour[13] => Add4.IN19
ip_sour[14] => Mux17.IN506
ip_sour[14] => Add4.IN18
ip_sour[15] => Mux16.IN505
ip_sour[15] => Add4.IN17
ip_sour[16] => Mux15.IN504
ip_sour[16] => Add4.IN16
ip_sour[17] => Mux14.IN503
ip_sour[17] => Add4.IN15
ip_sour[18] => Mux13.IN502
ip_sour[18] => Add4.IN14
ip_sour[19] => Mux12.IN501
ip_sour[19] => Add4.IN13
ip_sour[20] => Mux11.IN500
ip_sour[20] => Add4.IN12
ip_sour[21] => Mux10.IN499
ip_sour[21] => Add4.IN11
ip_sour[22] => Mux9.IN498
ip_sour[22] => Add4.IN10
ip_sour[23] => Mux8.IN497
ip_sour[23] => Add4.IN9
ip_sour[24] => Mux7.IN496
ip_sour[24] => Add4.IN8
ip_sour[25] => Mux6.IN495
ip_sour[25] => Add4.IN7
ip_sour[26] => Mux5.IN494
ip_sour[26] => Add4.IN6
ip_sour[27] => Mux4.IN493
ip_sour[27] => Add4.IN5
ip_sour[28] => Mux3.IN492
ip_sour[28] => Add4.IN4
ip_sour[29] => Mux2.IN491
ip_sour[29] => Add4.IN3
ip_sour[30] => Mux1.IN490
ip_sour[30] => Add4.IN2
ip_sour[31] => Mux0.IN489
ip_sour[31] => Add4.IN1
ip_self[0] => Mux31.IN488
ip_self[0] => Add3.IN32
ip_self[1] => Mux30.IN487
ip_self[1] => Add3.IN31
ip_self[2] => Mux29.IN486
ip_self[2] => Add3.IN30
ip_self[3] => Mux28.IN485
ip_self[3] => Add3.IN29
ip_self[4] => Mux27.IN484
ip_self[4] => Add3.IN28
ip_self[5] => Mux26.IN483
ip_self[5] => Add3.IN27
ip_self[6] => Mux25.IN482
ip_self[6] => Add3.IN26
ip_self[7] => Mux24.IN481
ip_self[7] => Add3.IN25
ip_self[8] => Mux23.IN480
ip_self[8] => Add3.IN24
ip_self[9] => Mux22.IN479
ip_self[9] => Add3.IN23
ip_self[10] => Mux21.IN478
ip_self[10] => Add3.IN22
ip_self[11] => Mux20.IN477
ip_self[11] => Add3.IN21
ip_self[12] => Mux19.IN476
ip_self[12] => Add3.IN20
ip_self[13] => Mux18.IN475
ip_self[13] => Add3.IN19
ip_self[14] => Mux17.IN474
ip_self[14] => Add3.IN18
ip_self[15] => Mux16.IN473
ip_self[15] => Add3.IN17
ip_self[16] => Mux15.IN472
ip_self[16] => Add3.IN16
ip_self[17] => Mux14.IN471
ip_self[17] => Add3.IN15
ip_self[18] => Mux13.IN470
ip_self[18] => Add3.IN14
ip_self[19] => Mux12.IN469
ip_self[19] => Add3.IN13
ip_self[20] => Mux11.IN468
ip_self[20] => Add3.IN12
ip_self[21] => Mux10.IN467
ip_self[21] => Add3.IN11
ip_self[22] => Mux9.IN466
ip_self[22] => Add3.IN10
ip_self[23] => Mux8.IN465
ip_self[23] => Add3.IN9
ip_self[24] => Mux7.IN464
ip_self[24] => Add3.IN8
ip_self[25] => Mux6.IN463
ip_self[25] => Add3.IN7
ip_self[26] => Mux5.IN462
ip_self[26] => Add3.IN6
ip_self[27] => Mux4.IN461
ip_self[27] => Add3.IN5
ip_self[28] => Mux3.IN460
ip_self[28] => Add3.IN4
ip_self[29] => Mux2.IN459
ip_self[29] => Add3.IN3
ip_self[30] => Mux1.IN458
ip_self[30] => Add3.IN2
ip_self[31] => Mux0.IN457
ip_self[31] => Add3.IN1
cmd_arq => ~NO_FANOUT~
cmd_start => ~NO_FANOUT~
cmd_stop => ~NO_FANOUT~
ff_tx_vld <= ff_tx_vld~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[0] <= ff_tx_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[1] <= ff_tx_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[2] <= ff_tx_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[3] <= ff_tx_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[4] <= ff_tx_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[5] <= ff_tx_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[6] <= ff_tx_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[7] <= ff_tx_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[8] <= ff_tx_data[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[9] <= ff_tx_data[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[10] <= ff_tx_data[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[11] <= ff_tx_data[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[12] <= ff_tx_data[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[13] <= ff_tx_data[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[14] <= ff_tx_data[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[15] <= ff_tx_data[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[16] <= ff_tx_data[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[17] <= ff_tx_data[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[18] <= ff_tx_data[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[19] <= ff_tx_data[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[20] <= ff_tx_data[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[21] <= ff_tx_data[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[22] <= ff_tx_data[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[23] <= ff_tx_data[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[24] <= ff_tx_data[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[25] <= ff_tx_data[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[26] <= ff_tx_data[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[27] <= ff_tx_data[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[28] <= ff_tx_data[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[29] <= ff_tx_data[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[30] <= ff_tx_data[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_data[31] <= ff_tx_data[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_sop <= ff_tx_sop~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_eop <= ff_tx_eop~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_tx_rdy => add_cnt_data.IN1


|project_top|data_receive:data_receive_ins
clk => data[0]~reg0.CLK
clk => data[1]~reg0.CLK
clk => data[2]~reg0.CLK
clk => data[3]~reg0.CLK
clk => data[4]~reg0.CLK
clk => data[5]~reg0.CLK
clk => data[6]~reg0.CLK
clk => data[7]~reg0.CLK
rst_n => data[0]~reg0.ACLR
rst_n => data[1]~reg0.ACLR
rst_n => data[2]~reg0.ACLR
rst_n => data[3]~reg0.ACLR
rst_n => data[4]~reg0.ACLR
rst_n => data[5]~reg0.ACLR
rst_n => data[6]~reg0.ACLR
rst_n => data[7]~reg0.ACLR
ip_sour[0] <= <GND>
ip_sour[1] <= <GND>
ip_sour[2] <= <GND>
ip_sour[3] <= <GND>
ip_sour[4] <= <GND>
ip_sour[5] <= <GND>
ip_sour[6] <= <GND>
ip_sour[7] <= <GND>
ip_sour[8] <= <GND>
ip_sour[9] <= <GND>
ip_sour[10] <= <GND>
ip_sour[11] <= <GND>
ip_sour[12] <= <GND>
ip_sour[13] <= <GND>
ip_sour[14] <= <GND>
ip_sour[15] <= <GND>
ip_sour[16] <= <GND>
ip_sour[17] <= <GND>
ip_sour[18] <= <GND>
ip_sour[19] <= <GND>
ip_sour[20] <= <GND>
ip_sour[21] <= <GND>
ip_sour[22] <= <GND>
ip_sour[23] <= <GND>
ip_sour[24] <= <GND>
ip_sour[25] <= <GND>
ip_sour[26] <= <GND>
ip_sour[27] <= <GND>
ip_sour[28] <= <GND>
ip_sour[29] <= <GND>
ip_sour[30] <= <GND>
ip_sour[31] <= <GND>
ip_self[0] => ~NO_FANOUT~
ip_self[1] => ~NO_FANOUT~
ip_self[2] => ~NO_FANOUT~
ip_self[3] => ~NO_FANOUT~
ip_self[4] => ~NO_FANOUT~
ip_self[5] => ~NO_FANOUT~
ip_self[6] => ~NO_FANOUT~
ip_self[7] => ~NO_FANOUT~
ip_self[8] => ~NO_FANOUT~
ip_self[9] => ~NO_FANOUT~
ip_self[10] => ~NO_FANOUT~
ip_self[11] => ~NO_FANOUT~
ip_self[12] => ~NO_FANOUT~
ip_self[13] => ~NO_FANOUT~
ip_self[14] => ~NO_FANOUT~
ip_self[15] => ~NO_FANOUT~
ip_self[16] => ~NO_FANOUT~
ip_self[17] => ~NO_FANOUT~
ip_self[18] => ~NO_FANOUT~
ip_self[19] => ~NO_FANOUT~
ip_self[20] => ~NO_FANOUT~
ip_self[21] => ~NO_FANOUT~
ip_self[22] => ~NO_FANOUT~
ip_self[23] => ~NO_FANOUT~
ip_self[24] => ~NO_FANOUT~
ip_self[25] => ~NO_FANOUT~
ip_self[26] => ~NO_FANOUT~
ip_self[27] => ~NO_FANOUT~
ip_self[28] => ~NO_FANOUT~
ip_self[29] => ~NO_FANOUT~
ip_self[30] => ~NO_FANOUT~
ip_self[31] => ~NO_FANOUT~
mac_sour[0] <= <GND>
mac_sour[1] <= <GND>
mac_sour[2] <= <GND>
mac_sour[3] <= <GND>
mac_sour[4] <= <GND>
mac_sour[5] <= <GND>
mac_sour[6] <= <GND>
mac_sour[7] <= <GND>
mac_sour[8] <= <GND>
mac_sour[9] <= <GND>
mac_sour[10] <= <GND>
mac_sour[11] <= <GND>
mac_sour[12] <= <GND>
mac_sour[13] <= <GND>
mac_sour[14] <= <GND>
mac_sour[15] <= <GND>
mac_sour[16] <= <GND>
mac_sour[17] <= <GND>
mac_sour[18] <= <GND>
mac_sour[19] <= <GND>
mac_sour[20] <= <GND>
mac_sour[21] <= <GND>
mac_sour[22] <= <GND>
mac_sour[23] <= <GND>
mac_sour[24] <= <GND>
mac_sour[25] <= <GND>
mac_sour[26] <= <GND>
mac_sour[27] <= <GND>
mac_sour[28] <= <GND>
mac_sour[29] <= <GND>
mac_sour[30] <= <GND>
mac_sour[31] <= <GND>
mac_sour[32] <= <GND>
mac_sour[33] <= <GND>
mac_sour[34] <= <GND>
mac_sour[35] <= <GND>
mac_sour[36] <= <GND>
mac_sour[37] <= <GND>
mac_sour[38] <= <GND>
mac_sour[39] <= <GND>
mac_sour[40] <= <GND>
mac_sour[41] <= <GND>
mac_sour[42] <= <GND>
mac_sour[43] <= <GND>
mac_sour[44] <= <GND>
mac_sour[45] <= <GND>
mac_sour[46] <= <GND>
mac_sour[47] <= <GND>
mac_self[0] => ~NO_FANOUT~
mac_self[1] => ~NO_FANOUT~
mac_self[2] => ~NO_FANOUT~
mac_self[3] => ~NO_FANOUT~
mac_self[4] => ~NO_FANOUT~
mac_self[5] => ~NO_FANOUT~
mac_self[6] => ~NO_FANOUT~
mac_self[7] => ~NO_FANOUT~
mac_self[8] => ~NO_FANOUT~
mac_self[9] => ~NO_FANOUT~
mac_self[10] => ~NO_FANOUT~
mac_self[11] => ~NO_FANOUT~
mac_self[12] => ~NO_FANOUT~
mac_self[13] => ~NO_FANOUT~
mac_self[14] => ~NO_FANOUT~
mac_self[15] => ~NO_FANOUT~
mac_self[16] => ~NO_FANOUT~
mac_self[17] => ~NO_FANOUT~
mac_self[18] => ~NO_FANOUT~
mac_self[19] => ~NO_FANOUT~
mac_self[20] => ~NO_FANOUT~
mac_self[21] => ~NO_FANOUT~
mac_self[22] => ~NO_FANOUT~
mac_self[23] => ~NO_FANOUT~
mac_self[24] => ~NO_FANOUT~
mac_self[25] => ~NO_FANOUT~
mac_self[26] => ~NO_FANOUT~
mac_self[27] => ~NO_FANOUT~
mac_self[28] => ~NO_FANOUT~
mac_self[29] => ~NO_FANOUT~
mac_self[30] => ~NO_FANOUT~
mac_self[31] => ~NO_FANOUT~
mac_self[32] => ~NO_FANOUT~
mac_self[33] => ~NO_FANOUT~
mac_self[34] => ~NO_FANOUT~
mac_self[35] => ~NO_FANOUT~
mac_self[36] => ~NO_FANOUT~
mac_self[37] => ~NO_FANOUT~
mac_self[38] => ~NO_FANOUT~
mac_self[39] => ~NO_FANOUT~
mac_self[40] => ~NO_FANOUT~
mac_self[41] => ~NO_FANOUT~
mac_self[42] => ~NO_FANOUT~
mac_self[43] => ~NO_FANOUT~
mac_self[44] => ~NO_FANOUT~
mac_self[45] => ~NO_FANOUT~
mac_self[46] => ~NO_FANOUT~
mac_self[47] => ~NO_FANOUT~
data[0] <= data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ff_rx_valid => data.OUTPUTSELECT
ff_rx_valid => data.OUTPUTSELECT
ff_rx_valid => data.OUTPUTSELECT
ff_rx_valid => data.OUTPUTSELECT
ff_rx_valid => data.OUTPUTSELECT
ff_rx_valid => data.OUTPUTSELECT
ff_rx_valid => data.OUTPUTSELECT
ff_rx_valid => data.OUTPUTSELECT
ff_rx_data[0] => data.DATAB
ff_rx_data[1] => data.DATAB
ff_rx_data[2] => data.DATAB
ff_rx_data[3] => data.DATAB
ff_rx_data[4] => data.DATAB
ff_rx_data[5] => data.DATAB
ff_rx_data[6] => data.DATAB
ff_rx_data[7] => data.DATAB
ff_rx_data[8] => ~NO_FANOUT~
ff_rx_data[9] => ~NO_FANOUT~
ff_rx_data[10] => ~NO_FANOUT~
ff_rx_data[11] => ~NO_FANOUT~
ff_rx_data[12] => ~NO_FANOUT~
ff_rx_data[13] => ~NO_FANOUT~
ff_rx_data[14] => ~NO_FANOUT~
ff_rx_data[15] => ~NO_FANOUT~
ff_rx_data[16] => ~NO_FANOUT~
ff_rx_data[17] => ~NO_FANOUT~
ff_rx_data[18] => ~NO_FANOUT~
ff_rx_data[19] => ~NO_FANOUT~
ff_rx_data[20] => ~NO_FANOUT~
ff_rx_data[21] => ~NO_FANOUT~
ff_rx_data[22] => ~NO_FANOUT~
ff_rx_data[23] => ~NO_FANOUT~
ff_rx_data[24] => ~NO_FANOUT~
ff_rx_data[25] => ~NO_FANOUT~
ff_rx_data[26] => ~NO_FANOUT~
ff_rx_data[27] => ~NO_FANOUT~
ff_rx_data[28] => ~NO_FANOUT~
ff_rx_data[29] => ~NO_FANOUT~
ff_rx_data[30] => ~NO_FANOUT~
ff_rx_data[31] => ~NO_FANOUT~
ff_rx_sop => ~NO_FANOUT~
ff_rx_eop => ~NO_FANOUT~
ff_rx_err[0] => ~NO_FANOUT~
ff_rx_err[1] => ~NO_FANOUT~
ff_rx_err[2] => ~NO_FANOUT~
ff_rx_err[3] => ~NO_FANOUT~
ff_rx_err[4] => ~NO_FANOUT~
ff_rx_err[5] => ~NO_FANOUT~
ff_rx_dsay => ~NO_FANOUT~
ff_rx_full => ~NO_FANOUT~
ff_rx_empty => ~NO_FANOUT~
rx_err_stat[0] => ~NO_FANOUT~
rx_err_stat[1] => ~NO_FANOUT~
rx_err_stat[2] => ~NO_FANOUT~
rx_err_stat[3] => ~NO_FANOUT~
rx_err_stat[4] => ~NO_FANOUT~
rx_err_stat[5] => ~NO_FANOUT~
rx_err_stat[6] => ~NO_FANOUT~
rx_err_stat[7] => ~NO_FANOUT~
rx_err_stat[8] => ~NO_FANOUT~
rx_err_stat[9] => ~NO_FANOUT~
rx_err_stat[10] => ~NO_FANOUT~
rx_err_stat[11] => ~NO_FANOUT~
rx_err_stat[12] => ~NO_FANOUT~
rx_err_stat[13] => ~NO_FANOUT~
rx_err_stat[14] => ~NO_FANOUT~
rx_err_stat[15] => ~NO_FANOUT~
rx_err_stat[16] => ~NO_FANOUT~
rx_err_stat[17] => ~NO_FANOUT~
rx_frm_type[0] => ~NO_FANOUT~
rx_frm_type[1] => ~NO_FANOUT~
rx_frm_type[2] => ~NO_FANOUT~
rx_frm_type[3] => ~NO_FANOUT~
cmd_arq <= <GND>
cmd_start <= <GND>
cmd_stop <= <GND>


|project_top|pll_sys:pll_sys_ins
inclk0 => sub_wire5[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk
c2 <= altpll:altpll_component.clk


|project_top|pll_sys:pll_sys_ins|altpll:altpll_component
inclk[0] => pll_sys_altpll:auto_generated.inclk[0]
inclk[1] => pll_sys_altpll:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>
clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>
fref <= <GND>
icdrclk <= <GND>


|project_top|pll_sys:pll_sys_ins|altpll:altpll_component|pll_sys_altpll:auto_generated
clk[0] <= pll1.CLK
clk[1] <= pll1.CLK1
clk[2] <= pll1.CLK2
clk[3] <= pll1.CLK3
clk[4] <= pll1.CLK4
inclk[0] => pll1.CLK
inclk[1] => pll1.CLK1


|project_top|led:led_ins
clk => led_out~reg0.CLK
clk => cnt_2[0].CLK
clk => cnt_2[1].CLK
clk => cnt_1[0].CLK
clk => cnt_1[1].CLK
clk => cnt_1[2].CLK
clk => cnt_1[3].CLK
clk => cnt_1[4].CLK
clk => cnt_1[5].CLK
clk => cnt_1[6].CLK
clk => cnt_1[7].CLK
clk => cnt_1[8].CLK
clk => cnt_1[9].CLK
clk => cnt_1[10].CLK
clk => cnt_1[11].CLK
clk => cnt_1[12].CLK
clk => cnt_1[13].CLK
clk => cnt_1[14].CLK
clk => cnt_1[15].CLK
clk => cnt_1[16].CLK
clk => cnt_1[17].CLK
clk => cnt_1[18].CLK
clk => cnt_1[19].CLK
clk => cnt_1[20].CLK
clk => cnt_1[21].CLK
clk => cnt_1[22].CLK
clk => cnt_1[23].CLK
clk => cnt_1[24].CLK
clk => cnt_1[25].CLK
clk => cnt_1[26].CLK
clk => cnt_1[27].CLK
clk => cnt_1[28].CLK
clk => cnt_1[29].CLK
clk => cnt_1[30].CLK
clk => cnt_1[31].CLK
rst_n => cnt_1[0].ACLR
rst_n => cnt_1[1].ACLR
rst_n => cnt_1[2].ACLR
rst_n => cnt_1[3].ACLR
rst_n => cnt_1[4].ACLR
rst_n => cnt_1[5].ACLR
rst_n => cnt_1[6].ACLR
rst_n => cnt_1[7].ACLR
rst_n => cnt_1[8].ACLR
rst_n => cnt_1[9].ACLR
rst_n => cnt_1[10].ACLR
rst_n => cnt_1[11].ACLR
rst_n => cnt_1[12].ACLR
rst_n => cnt_1[13].ACLR
rst_n => cnt_1[14].ACLR
rst_n => cnt_1[15].ACLR
rst_n => cnt_1[16].ACLR
rst_n => cnt_1[17].ACLR
rst_n => cnt_1[18].ACLR
rst_n => cnt_1[19].ACLR
rst_n => cnt_1[20].ACLR
rst_n => cnt_1[21].ACLR
rst_n => cnt_1[22].ACLR
rst_n => cnt_1[23].ACLR
rst_n => cnt_1[24].ACLR
rst_n => cnt_1[25].ACLR
rst_n => cnt_1[26].ACLR
rst_n => cnt_1[27].ACLR
rst_n => cnt_1[28].ACLR
rst_n => cnt_1[29].ACLR
rst_n => cnt_1[30].ACLR
rst_n => cnt_1[31].ACLR
rst_n => led_out~reg0.ACLR
rst_n => cnt_2[0].ACLR
rst_n => cnt_2[1].ACLR
cmd_arq => ~NO_FANOUT~
cmd_start => ~NO_FANOUT~
cmd_stop => ~NO_FANOUT~
led_out <= led_out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|project_top|dp83848_rst:dp83848_rst_ins
clk => config_en~reg0.CLK
clk => phy_rst~reg0.CLK
clk => flag_phyrst.CLK
clk => cnt_zu[0].CLK
clk => cnt_zu[1].CLK
clk => cnt_zu[2].CLK
clk => cnt_zu[3].CLK
clk => cnt_zu[4].CLK
clk => cnt_zu[5].CLK
clk => cnt_zu[6].CLK
clk => cnt_zu[7].CLK
clk => cnt_zu[8].CLK
clk => cnt_zu[9].CLK
clk => cnt_zu[10].CLK
clk => cnt_zu[11].CLK
clk => cnt_zu[12].CLK
clk => cnt_zu[13].CLK
clk => cnt_zu[14].CLK
clk => cnt_zu[15].CLK
clk => cnt_phyrst[0].CLK
clk => cnt_phyrst[1].CLK
clk => cnt_phyrst[2].CLK
clk => cnt_phyrst[3].CLK
clk => cnt_phyrst[4].CLK
clk => cnt_phyrst[5].CLK
clk => cnt_phyrst[6].CLK
clk => cnt_phyrst[7].CLK
clk => cnt_phyrst[8].CLK
clk => cnt_phyrst[9].CLK
clk => cnt_phyrst[10].CLK
clk => cnt_phyrst[11].CLK
clk => cnt_phyrst[12].CLK
clk => cnt_phyrst[13].CLK
clk => cnt_phyrst[14].CLK
clk => cnt_phyrst[15].CLK
clk => cnt_phyrst[16].CLK
clk => cnt_phyrst[17].CLK
clk => cnt_phyrst[18].CLK
clk => cnt_phyrst[19].CLK
clk => cnt_phyrst[20].CLK
clk => cnt_phyrst[21].CLK
clk => cnt_phyrst[22].CLK
clk => cnt_phyrst[23].CLK
clk => cnt_phyrst[24].CLK
clk => cnt_phyrst[25].CLK
clk => cnt_phyrst[26].CLK
clk => cnt_phyrst[27].CLK
clk => cnt_phyrst[28].CLK
clk => cnt_phyrst[29].CLK
clk => cnt_phyrst[30].CLK
clk => cnt_phyrst[31].CLK
rst_n => cnt_phyrst[0].ACLR
rst_n => cnt_phyrst[1].ACLR
rst_n => cnt_phyrst[2].ACLR
rst_n => cnt_phyrst[3].ACLR
rst_n => cnt_phyrst[4].ACLR
rst_n => cnt_phyrst[5].ACLR
rst_n => cnt_phyrst[6].ACLR
rst_n => cnt_phyrst[7].ACLR
rst_n => cnt_phyrst[8].ACLR
rst_n => cnt_phyrst[9].ACLR
rst_n => cnt_phyrst[10].ACLR
rst_n => cnt_phyrst[11].ACLR
rst_n => cnt_phyrst[12].ACLR
rst_n => cnt_phyrst[13].ACLR
rst_n => cnt_phyrst[14].ACLR
rst_n => cnt_phyrst[15].ACLR
rst_n => cnt_phyrst[16].ACLR
rst_n => cnt_phyrst[17].ACLR
rst_n => cnt_phyrst[18].ACLR
rst_n => cnt_phyrst[19].ACLR
rst_n => cnt_phyrst[20].ACLR
rst_n => cnt_phyrst[21].ACLR
rst_n => cnt_phyrst[22].ACLR
rst_n => cnt_phyrst[23].ACLR
rst_n => cnt_phyrst[24].ACLR
rst_n => cnt_phyrst[25].ACLR
rst_n => cnt_phyrst[26].ACLR
rst_n => cnt_phyrst[27].ACLR
rst_n => cnt_phyrst[28].ACLR
rst_n => cnt_phyrst[29].ACLR
rst_n => cnt_phyrst[30].ACLR
rst_n => cnt_phyrst[31].ACLR
rst_n => config_en~reg0.ACLR
rst_n => phy_rst~reg0.PRESET
rst_n => cnt_zu[0].ACLR
rst_n => cnt_zu[1].ACLR
rst_n => cnt_zu[2].ACLR
rst_n => cnt_zu[3].ACLR
rst_n => cnt_zu[4].ACLR
rst_n => cnt_zu[5].ACLR
rst_n => cnt_zu[6].ACLR
rst_n => cnt_zu[7].ACLR
rst_n => cnt_zu[8].ACLR
rst_n => cnt_zu[9].ACLR
rst_n => cnt_zu[10].ACLR
rst_n => cnt_zu[11].ACLR
rst_n => cnt_zu[12].ACLR
rst_n => cnt_zu[13].ACLR
rst_n => cnt_zu[14].ACLR
rst_n => cnt_zu[15].ACLR
rst_n => flag_phyrst.ACLR
config_en <= config_en~reg0.DB_MAX_OUTPUT_PORT_TYPE
phy_rst <= phy_rst~reg0.DB_MAX_OUTPUT_PORT_TYPE


