{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1589246450365 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "project_top EP4CE10F17I7 " "Selected device EP4CE10F17I7 for design \"project_top\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1589246450411 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1589246450462 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1589246450462 ""}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] 5 1 0 0 " "Implementing clock multiplication of 5, clock division of 1, and phase shift of 0 degrees (0 ps) for pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] port" {  } { { "db/pll_sys_altpll.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/pll_sys_altpll.v" 43 -1 0 } } { "" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 515 9224 9983 0}  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1589246450520 ""}  } { { "db/pll_sys_altpll.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/pll_sys_altpll.v" 43 -1 0 } } { "" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 515 9224 9983 0}  }  } }  } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1589246450520 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1589246450674 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17A7 " "Device EP4CE10F17A7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246450868 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C7 " "Device EP4CE10F17C7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246450868 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17A7 " "Device EP4CE6F17A7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246450868 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C7 " "Device EP4CE6F17C7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246450868 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17I7 " "Device EP4CE6F17I7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246450868 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17A7 " "Device EP4CE15F17A7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246450868 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C7 " "Device EP4CE15F17C7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246450868 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17I7 " "Device EP4CE15F17I7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246450868 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17A7 " "Device EP4CE22F17A7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246450868 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C7 " "Device EP4CE22F17C7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246450868 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17I7 " "Device EP4CE22F17I7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246450868 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1589246450868 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" {  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 11354 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1589246450875 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" {  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 11356 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1589246450875 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" {  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 11358 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1589246450875 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" {  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 11360 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1589246450875 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" {  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 11362 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1589246450875 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1589246450875 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1589246450877 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1589246450885 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1589246451901 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1589246451901 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_tse_a_fifo_34 " "Entity altera_tse_a_fifo_34" { { "Info" "ISTA_SDC_STATEMENT_EVAL" " set_false_path -to \[get_registers *altera_tse_a_fifo_34:*\|wr_g_rptr*\] " " set_false_path -to \[get_registers *altera_tse_a_fifo_34:*\|wr_g_rptr*\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1589246451901 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1589246451901 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz    " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz   " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1589246451901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1589246451901 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1589246451901 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1589246451901 ""}
{ "Info" "ISTA_SDC_FOUND" "mac_ip/altera_eth_tse_mac.sdc " "Reading SDC File: 'mac_ip/altera_eth_tse_mac.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1589246451934 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "mii_rx_clk " "Node: mii_rx_clk was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1589246451968 "|project_top|mii_rx_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_in " "Node: clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1589246451968 "|project_top|clk_in"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "mii_tx_clk " "Node: mii_tx_clk was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1589246451968 "|project_top|mii_tx_clk"}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: pll_sys_ins\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 50.000 " "Node: pll_sys_ins\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 50.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1589246452001 ""}  } {  } 0 332056 "%1!s!" 0 0 "Fitter" 0 -1 1589246452001 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1589246452002 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1589246452002 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1589246452002 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1589246452002 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1589246452003 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1589246452003 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1589246452003 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1589246452003 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2) " "Automatically promoted node pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G8 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246452212 ""}  } { { "db/pll_sys_altpll.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/pll_sys_altpll.v" 77 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:pll_sys_ins|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 515 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246452212 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246452212 ""}  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 8321 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246452212 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_0\|altera_tse_reset_synchronizer_chain_out  " "Automatically promoted node mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_0\|altera_tse_reset_synchronizer_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246452212 ""}  } { { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 76 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_0|altera_tse_reset_synchronizer_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 2600 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246452212 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_1\|altera_tse_reset_synchronizer_chain_out  " "Automatically promoted node mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_1\|altera_tse_reset_synchronizer_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246452213 ""}  } { { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 76 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_1|altera_tse_reset_synchronizer_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 3852 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246452213 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|reset_all  " "Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|reset_all " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246452213 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~0 " "Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~0" {  } { { "sld_buffer_manager.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 627 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 10077 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1589246452213 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" {  } { { "sld_buffer_manager.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 627 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 8850 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1589246452213 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1589246452213 ""}  } { { "sld_signaltap_impl.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd" 842 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 9462 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246452213 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_2\|altera_tse_reset_synchronizer_chain_out  " "Automatically promoted node mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_2\|altera_tse_reset_synchronizer_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246452213 ""}  } { { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 76 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_2|altera_tse_reset_synchronizer_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 3848 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246452213 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_3\|altera_tse_reset_synchronizer_chain_out  " "Automatically promoted node mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_3\|altera_tse_reset_synchronizer_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246452214 ""}  } { { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 76 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_3|altera_tse_reset_synchronizer_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 3844 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246452214 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_4\|altera_tse_reset_synchronizer_chain_out  " "Automatically promoted node mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_4\|altera_tse_reset_synchronizer_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246452214 ""}  } { { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 76 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_4|altera_tse_reset_synchronizer_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 3840 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246452214 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1589246452937 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1589246452945 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1589246452946 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1589246452954 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1589246452966 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1589246452974 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1589246452974 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1589246452981 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1589246453597 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "1 EC " "Packed 1 registers into blocks of type EC" {  } {  } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1589246453606 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1589246453606 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1589246453713 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1589246454550 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1589246455394 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1589246455419 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1589246456286 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1589246456286 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1589246457103 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "8 " "Router estimated average interconnect usage is 8% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "15 X11_Y12 X22_Y24 " "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24" {  } { { "loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 1 { 0 "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} { { 11 { 0 "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} 11 12 12 13 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1589246458353 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1589246458353 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1589246458824 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1589246458827 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1589246458827 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1589246458827 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.70 " "Total time spent on timing analysis during the Fitter is 0.70 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1589246458954 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1589246459015 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1589246459459 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1589246459516 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1589246460150 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1589246461156 ""}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "1 " "Following 1 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "eth_mdio a permanently enabled " "Pin eth_mdio has a permanently enabled output enable" {  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { eth_mdio } } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/softwareinstall/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "eth_mdio" } } } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 36 0 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { eth_mdio } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 321 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1589246461718 ""}  } {  } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1589246461718 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/output_files/project_top.fit.smsg " "Generated suppressed messages file F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/output_files/project_top.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1589246462129 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 10 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1112 " "Peak virtual memory: 1112 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1589246463279 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 12 09:21:03 2020 " "Processing ended: Tue May 12 09:21:03 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1589246463279 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1589246463279 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1589246463279 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1589246463279 ""}
