{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1589246431083 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1589246431084 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 12 09:20:30 2020 " "Processing started: Tue May 12 09:20:30 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1589246431084 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1589246431084 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off project_top -c project_top " "Command: quartus_map --read_settings_files=on --write_settings_files=off project_top -c project_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1589246431084 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1589246431374 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "project_top.v 1 1 " "Found 1 design units, including 1 entities, in source file project_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 project_top " "Found entity 1: project_top" {  } { { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431422 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431422 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_reg_config.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_reg_config.v" { { "Info" "ISGN_ENTITY_NAME" "1 mac_reg_config " "Found entity 1: mac_reg_config" {  } { { "mac_reg_config.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_reg_config.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431425 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431425 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_reg.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_reg.v" { { "Info" "ISGN_ENTITY_NAME" "1 mac_reg " "Found entity 1: mac_reg" {  } { { "mac_reg.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_reg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431428 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431428 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip.v" { { "Info" "ISGN_ENTITY_NAME" "1 mac_ip " "Found entity 1: mac_ip" {  } { { "mac_ip.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip.v" 8 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431430 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431430 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led.v 1 1 " "Found 1 design units, including 1 entities, in source file led.v" { { "Info" "ISGN_ENTITY_NAME" "1 led " "Found entity 1: led" {  } { { "led.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/led.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431433 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431433 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dp83848_rst.v 1 1 " "Found 1 design units, including 1 entities, in source file dp83848_rst.v" { { "Info" "ISGN_ENTITY_NAME" "1 dp83848_rst " "Found entity 1: dp83848_rst" {  } { { "dp83848_rst.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/dp83848_rst.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431436 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431436 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_transmit.v 1 1 " "Found 1 design units, including 1 entities, in source file data_transmit.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_transmit " "Found entity 1: data_transmit" {  } { { "data_transmit.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_transmit.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431439 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431439 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_receive.v 1 1 " "Found 1 design units, including 1 entities, in source file data_receive.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_receive " "Found entity 1: data_receive" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431442 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431442 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip.v" { { "Info" "ISGN_ENTITY_NAME" "1 mac_ip " "Found entity 1: mac_ip" {  } { { "mac_ip.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip.v" 8 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431445 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431445 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/mac_ip_0002.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/mac_ip_0002.v" { { "Info" "ISGN_ENTITY_NAME" "1 mac_ip_0002 " "Found entity 1: mac_ip_0002" {  } { { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431447 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431447 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_eth_tse_mac.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_eth_tse_mac.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_eth_tse_mac " "Found entity 1: altera_eth_tse_mac" {  } { { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431557 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431557 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_clk_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_clk_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_clk_cntl " "Found entity 1: altera_tse_clk_cntl" {  } { { "mac_ip/altera_tse_clk_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_clk_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431578 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431578 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_crc328checker.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_crc328checker.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_crc328checker " "Found entity 1: altera_tse_crc328checker" {  } { { "mac_ip/altera_tse_crc328checker.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_crc328checker.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431600 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431600 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_crc328generator.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_crc328generator.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_crc328generator " "Found entity 1: altera_tse_crc328generator" {  } { { "mac_ip/altera_tse_crc328generator.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_crc328generator.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431619 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431619 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_crc32ctl8.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_crc32ctl8.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_crc32ctl8 " "Found entity 1: altera_tse_crc32ctl8" {  } { { "mac_ip/altera_tse_crc32ctl8.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_crc32ctl8.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431638 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431638 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_crc32galois8.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_crc32galois8.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_crc32galois8 " "Found entity 1: altera_tse_crc32galois8" {  } { { "mac_ip/altera_tse_crc32galois8.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_crc32galois8.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431663 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431663 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_gmii_io.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_gmii_io.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_gmii_io " "Found entity 1: altera_tse_gmii_io" {  } { { "mac_ip/altera_tse_gmii_io.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_gmii_io.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431687 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431687 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_lb_read_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_lb_read_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_lb_read_cntl " "Found entity 1: altera_tse_lb_read_cntl" {  } { { "mac_ip/altera_tse_lb_read_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_lb_read_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431706 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431706 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_lb_wrt_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_lb_wrt_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_lb_wrt_cntl " "Found entity 1: altera_tse_lb_wrt_cntl" {  } { { "mac_ip/altera_tse_lb_wrt_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_lb_wrt_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431726 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431726 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_hashing.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_hashing.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_hashing " "Found entity 1: altera_tse_hashing" {  } { { "mac_ip/altera_tse_hashing.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_hashing.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431747 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431747 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_host_control.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_host_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_host_control " "Found entity 1: altera_tse_host_control" {  } { { "mac_ip/altera_tse_host_control.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_host_control.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431780 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431780 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_host_control_small.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_host_control_small.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_host_control_small " "Found entity 1: altera_tse_host_control_small" {  } { { "mac_ip/altera_tse_host_control_small.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_host_control_small.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431812 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431812 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mac_control.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mac_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mac_control " "Found entity 1: altera_tse_mac_control" {  } { { "mac_ip/altera_tse_mac_control.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_control.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246431890 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246431890 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_register_map.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_register_map.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_register_map " "Found entity 1: altera_tse_register_map" {  } { { "mac_ip/altera_tse_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246432039 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246432039 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_register_map_small.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_register_map_small.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_register_map_small " "Found entity 1: altera_tse_register_map_small" {  } { { "mac_ip/altera_tse_register_map_small.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map_small.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246432176 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246432176 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_counter_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_counter_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_counter_cntl " "Found entity 1: altera_tse_rx_counter_cntl" {  } { { "mac_ip/altera_tse_rx_counter_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_counter_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246432228 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246432228 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_shared_mac_control.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_shared_mac_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_shared_mac_control " "Found entity 1: altera_tse_shared_mac_control" {  } { { "mac_ip/altera_tse_shared_mac_control.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_shared_mac_control.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246432288 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246432288 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_shared_register_map.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_shared_register_map.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_shared_register_map " "Found entity 1: altera_tse_shared_register_map" {  } { { "mac_ip/altera_tse_shared_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_shared_register_map.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246432440 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246432440 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_counter_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_counter_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_counter_cntl " "Found entity 1: altera_tse_tx_counter_cntl" {  } { { "mac_ip/altera_tse_tx_counter_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_counter_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246432480 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246432480 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_lfsr_10.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_lfsr_10.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_lfsr_10 " "Found entity 1: altera_tse_lfsr_10" {  } { { "mac_ip/altera_tse_lfsr_10.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_lfsr_10.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246432500 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246432500 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_loopback_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_loopback_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_loopback_ff " "Found entity 1: altera_tse_loopback_ff" {  } { { "mac_ip/altera_tse_loopback_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_loopback_ff.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246432525 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246432525 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_altshifttaps.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_altshifttaps.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_altshifttaps " "Found entity 1: altera_tse_altshifttaps" {  } { { "mac_ip/altera_tse_altshifttaps.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altshifttaps.v" 32 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246432544 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246432544 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_fifoless_mac_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_fifoless_mac_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_fifoless_mac_rx " "Found entity 1: altera_tse_fifoless_mac_rx" {  } { { "mac_ip/altera_tse_fifoless_mac_rx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_fifoless_mac_rx.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246432732 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246432732 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mac_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mac_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mac_rx " "Found entity 1: altera_tse_mac_rx" {  } { { "mac_ip/altera_tse_mac_rx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246432903 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246432903 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_fifoless_mac_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_fifoless_mac_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_fifoless_mac_tx " "Found entity 1: altera_tse_fifoless_mac_tx" {  } { { "mac_ip/altera_tse_fifoless_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_fifoless_mac_tx.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433065 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433065 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mac_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mac_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mac_tx " "Found entity 1: altera_tse_mac_tx" {  } { { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433207 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433207 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_magic_detection.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_magic_detection.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_magic_detection " "Found entity 1: altera_tse_magic_detection" {  } { { "mac_ip/altera_tse_magic_detection.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_magic_detection.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433247 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433247 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mdio.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mdio.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mdio " "Found entity 1: altera_tse_mdio" {  } { { "mac_ip/altera_tse_mdio.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mdio.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433286 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433286 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mdio_clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mdio_clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mdio_clk_gen " "Found entity 1: altera_tse_mdio_clk_gen" {  } { { "mac_ip/altera_tse_mdio_clk_gen.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mdio_clk_gen.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433305 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433305 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mdio_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mdio_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mdio_cntl " "Found entity 1: altera_tse_mdio_cntl" {  } { { "mac_ip/altera_tse_mdio_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mdio_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433333 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433333 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_mdio.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_mdio.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_mdio " "Found entity 1: altera_tse_top_mdio" {  } { { "mac_ip/altera_tse_top_mdio.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_mdio.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433357 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433357 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mii_rx_if.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mii_rx_if.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mii_rx_if " "Found entity 1: altera_tse_mii_rx_if" {  } { { "mac_ip/altera_tse_mii_rx_if.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mii_rx_if.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433384 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433384 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mii_tx_if.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mii_tx_if.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mii_tx_if " "Found entity 1: altera_tse_mii_tx_if" {  } { { "mac_ip/altera_tse_mii_tx_if.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mii_tx_if.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433406 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433406 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_pipeline_base " "Found entity 1: altera_tse_pipeline_base" {  } { { "mac_ip/altera_tse_pipeline_base.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_pipeline_base.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433426 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433426 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_pipeline_stage.sv 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_pipeline_stage.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_pipeline_stage " "Found entity 1: altera_tse_pipeline_stage" {  } { { "mac_ip/altera_tse_pipeline_stage.sv" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_pipeline_stage.sv" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433447 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433447 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_dpram_16x32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_dpram_16x32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_dpram_16x32 " "Found entity 1: altera_tse_dpram_16x32" {  } { { "mac_ip/altera_tse_dpram_16x32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_dpram_16x32.v" 52 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433475 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433475 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_dpram_8x32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_dpram_8x32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_dpram_8x32 " "Found entity 1: altera_tse_dpram_8x32" {  } { { "mac_ip/altera_tse_dpram_8x32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_dpram_8x32.v" 52 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433505 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433505 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_quad_16x32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_quad_16x32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_quad_16x32 " "Found entity 1: altera_tse_quad_16x32" {  } { { "mac_ip/altera_tse_quad_16x32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_quad_16x32.v" 52 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433531 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433531 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_quad_8x32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_quad_8x32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_quad_8x32 " "Found entity 1: altera_tse_quad_8x32" {  } { { "mac_ip/altera_tse_quad_8x32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_quad_8x32.v" 52 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433557 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433557 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_fifoless_retransmit_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_fifoless_retransmit_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_fifoless_retransmit_cntl " "Found entity 1: altera_tse_fifoless_retransmit_cntl" {  } { { "mac_ip/altera_tse_fifoless_retransmit_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_fifoless_retransmit_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433610 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433610 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_retransmit_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_retransmit_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_retransmit_cntl " "Found entity 1: altera_tse_retransmit_cntl" {  } { { "mac_ip/altera_tse_retransmit_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_retransmit_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433662 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433662 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rgmii_in1.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rgmii_in1.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rgmii_in1 " "Found entity 1: altera_tse_rgmii_in1" {  } { { "mac_ip/altera_tse_rgmii_in1.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rgmii_in1.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433665 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433665 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rgmii_in4.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rgmii_in4.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rgmii_in4 " "Found entity 1: altera_tse_rgmii_in4" {  } { { "mac_ip/altera_tse_rgmii_in4.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rgmii_in4.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433667 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433667 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rgmii_module.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rgmii_module.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rgmii_module " "Found entity 1: altera_tse_rgmii_module" {  } { { "mac_ip/altera_tse_rgmii_module.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rgmii_module.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433669 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433669 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rgmii_out1.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rgmii_out1.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rgmii_out1 " "Found entity 1: altera_tse_rgmii_out1" {  } { { "mac_ip/altera_tse_rgmii_out1.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rgmii_out1.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433671 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433671 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rgmii_out4.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rgmii_out4.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rgmii_out4 " "Found entity 1: altera_tse_rgmii_out4" {  } { { "mac_ip/altera_tse_rgmii_out4.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rgmii_out4.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433673 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433673 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_ff " "Found entity 1: altera_tse_rx_ff" {  } { { "mac_ip/altera_tse_rx_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_ff.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433719 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433719 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_min_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_min_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_min_ff " "Found entity 1: altera_tse_rx_min_ff" {  } { { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433775 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433775 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_ff_cntrl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_ff_cntrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_ff_cntrl " "Found entity 1: altera_tse_rx_ff_cntrl" {  } { { "mac_ip/altera_tse_rx_ff_cntrl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_ff_cntrl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433819 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433819 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_ff_cntrl_32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_ff_cntrl_32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_ff_cntrl_32 " "Found entity 1: altera_tse_rx_ff_cntrl_32" {  } { { "mac_ip/altera_tse_rx_ff_cntrl_32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_ff_cntrl_32.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433866 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433866 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_ff_cntrl_32_shift16.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_ff_cntrl_32_shift16.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_ff_cntrl_32_shift16 " "Found entity 1: altera_tse_rx_ff_cntrl_32_shift16" {  } { { "mac_ip/altera_tse_rx_ff_cntrl_32_shift16.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_ff_cntrl_32_shift16.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433924 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433924 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_ff_length.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_ff_length.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_ff_length " "Found entity 1: altera_tse_rx_ff_length" {  } { { "mac_ip/altera_tse_rx_ff_length.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_ff_length.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433944 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433944 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_stat_extract.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_stat_extract.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_stat_extract " "Found entity 1: altera_tse_rx_stat_extract" {  } { { "mac_ip/altera_tse_rx_stat_extract.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_stat_extract.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246433984 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246433984 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_timing_adapter32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_timing_adapter32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_timing_adapter32 " "Found entity 1: altera_tse_timing_adapter32" {  } { { "mac_ip/altera_tse_timing_adapter32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_timing_adapter32.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434005 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434005 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_timing_adapter8.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_timing_adapter8.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_timing_adapter8 " "Found entity 1: altera_tse_timing_adapter8" {  } { { "mac_ip/altera_tse_timing_adapter8.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_timing_adapter8.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434027 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434027 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_timing_adapter_fifo32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_timing_adapter_fifo32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_timing_adapter_fifo32 " "Found entity 1: altera_tse_timing_adapter_fifo32" {  } { { "mac_ip/altera_tse_timing_adapter_fifo32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_timing_adapter_fifo32.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434060 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434060 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_timing_adapter_fifo8.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_timing_adapter_fifo8.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_timing_adapter_fifo8 " "Found entity 1: altera_tse_timing_adapter_fifo8" {  } { { "mac_ip/altera_tse_timing_adapter_fifo8.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_timing_adapter_fifo8.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434091 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434091 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_1geth.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_1geth.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_1geth " "Found entity 1: altera_tse_top_1geth" {  } { { "mac_ip/altera_tse_top_1geth.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_1geth.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434150 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434150 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_fifoless_1geth.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_fifoless_1geth.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_fifoless_1geth " "Found entity 1: altera_tse_top_fifoless_1geth" {  } { { "mac_ip/altera_tse_top_fifoless_1geth.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_fifoless_1geth.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434211 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434211 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_w_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_w_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_w_fifo " "Found entity 1: altera_tse_top_w_fifo" {  } { { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434296 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434296 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_w_fifo_10_100_1000.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_w_fifo_10_100_1000.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_w_fifo_10_100_1000 " "Found entity 1: altera_tse_top_w_fifo_10_100_1000" {  } { { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434377 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434377 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_wo_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_wo_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_wo_fifo " "Found entity 1: altera_tse_top_wo_fifo" {  } { { "mac_ip/altera_tse_top_wo_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_wo_fifo.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434464 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434464 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_wo_fifo_10_100_1000.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_wo_fifo_10_100_1000.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_wo_fifo_10_100_1000 " "Found entity 1: altera_tse_top_wo_fifo_10_100_1000" {  } { { "mac_ip/altera_tse_top_wo_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_wo_fifo_10_100_1000.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434553 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434553 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mac_woff.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mac_woff.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mac_woff " "Found entity 1: altera_tse_mac_woff" {  } { { "mac_ip/altera_tse_mac_woff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_woff.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434668 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434668 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_gen_host.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_gen_host.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_gen_host " "Found entity 1: altera_tse_top_gen_host" {  } { { "mac_ip/altera_tse_top_gen_host.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_gen_host.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434777 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434777 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_ff " "Found entity 1: altera_tse_tx_ff" {  } { { "mac_ip/altera_tse_tx_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_ff.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434853 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434853 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_min_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_min_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_min_ff " "Found entity 1: altera_tse_tx_min_ff" {  } { { "mac_ip/altera_tse_tx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_min_ff.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434907 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434907 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_ff_cntrl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_ff_cntrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_ff_cntrl " "Found entity 1: altera_tse_tx_ff_cntrl" {  } { { "mac_ip/altera_tse_tx_ff_cntrl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_ff_cntrl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434937 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434937 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_ff_cntrl_32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_ff_cntrl_32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_ff_cntrl_32 " "Found entity 1: altera_tse_tx_ff_cntrl_32" {  } { { "mac_ip/altera_tse_tx_ff_cntrl_32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_ff_cntrl_32.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246434968 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246434968 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_ff_cntrl_32_shift16.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_ff_cntrl_32_shift16.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_ff_cntrl_32_shift16 " "Found entity 1: altera_tse_tx_ff_cntrl_32_shift16" {  } { { "mac_ip/altera_tse_tx_ff_cntrl_32_shift16.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_ff_cntrl_32_shift16.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435005 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435005 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_ff_length.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_ff_length.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_ff_length " "Found entity 1: altera_tse_tx_ff_length" {  } { { "mac_ip/altera_tse_tx_ff_length.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_ff_length.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435024 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435024 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_ff_read_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_ff_read_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_ff_read_cntl " "Found entity 1: altera_tse_tx_ff_read_cntl" {  } { { "mac_ip/altera_tse_tx_ff_read_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_ff_read_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435054 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435054 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_stat_extract.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_stat_extract.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_stat_extract " "Found entity 1: altera_tse_tx_stat_extract" {  } { { "mac_ip/altera_tse_tx_stat_extract.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_stat_extract.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435090 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435090 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_false_path_marker.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_false_path_marker.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_false_path_marker " "Found entity 1: altera_tse_false_path_marker" {  } { { "mac_ip/altera_tse_false_path_marker.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_false_path_marker.v" 38 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435092 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435092 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_reset_synchronizer " "Found entity 1: altera_tse_reset_synchronizer" {  } { { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 36 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435094 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435094 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_clock_crosser.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_clock_crosser.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_clock_crosser " "Found entity 1: altera_tse_clock_crosser" {  } { { "mac_ip/altera_tse_clock_crosser.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_clock_crosser.v" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435115 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435115 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_a_fifo_13.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_a_fifo_13.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_a_fifo_13 " "Found entity 1: altera_tse_a_fifo_13" {  } { { "mac_ip/altera_tse_a_fifo_13.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435141 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435141 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_a_fifo_24.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_a_fifo_24.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_a_fifo_24 " "Found entity 1: altera_tse_a_fifo_24" {  } { { "mac_ip/altera_tse_a_fifo_24.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_24.v" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435169 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435169 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_a_fifo_34.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_a_fifo_34.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_a_fifo_34 " "Found entity 1: altera_tse_a_fifo_34" {  } { { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435193 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435193 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_a_fifo_opt_1246.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_a_fifo_opt_1246.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_a_fifo_opt_1246 " "Found entity 1: altera_tse_a_fifo_opt_1246" {  } { { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 53 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435227 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435227 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_a_fifo_opt_14_44.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_a_fifo_opt_14_44.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_a_fifo_opt_14_44 " "Found entity 1: altera_tse_a_fifo_opt_14_44" {  } { { "mac_ip/altera_tse_a_fifo_opt_14_44.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_14_44.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435260 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435260 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_a_fifo_opt_36_10.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_a_fifo_opt_36_10.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_a_fifo_opt_36_10 " "Found entity 1: altera_tse_a_fifo_opt_36_10" {  } { { "mac_ip/altera_tse_a_fifo_opt_36_10.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_36_10.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435296 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435296 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_gray_cnt.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_gray_cnt.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_gray_cnt " "Found entity 1: altera_tse_gray_cnt" {  } { { "mac_ip/altera_tse_gray_cnt.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_gray_cnt.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435317 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435317 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_sdpm_altsyncram.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_sdpm_altsyncram.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_sdpm_altsyncram " "Found entity 1: altera_tse_sdpm_altsyncram" {  } { { "mac_ip/altera_tse_sdpm_altsyncram.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_sdpm_altsyncram.v" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435337 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435337 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_altsyncram_dpm_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_altsyncram_dpm_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_altsyncram_dpm_fifo " "Found entity 1: altera_tse_altsyncram_dpm_fifo" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435356 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435356 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_bin_cnt.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_bin_cnt.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_bin_cnt " "Found entity 1: altera_tse_bin_cnt" {  } { { "mac_ip/altera_tse_bin_cnt.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_bin_cnt.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435375 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435375 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_ph_calculator.sv 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_ph_calculator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_ph_calculator " "Found entity 1: altera_tse_ph_calculator" {  } { { "mac_ip/altera_tse_ph_calculator.sv" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_ph_calculator.sv" 15 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435397 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435397 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_sdpm_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_sdpm_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_sdpm_gen " "Found entity 1: altera_tse_sdpm_gen" {  } { { "mac_ip/altera_tse_sdpm_gen.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_sdpm_gen.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435416 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435416 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_dc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_dc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_dc_fifo " "Found entity 1: altera_tse_dc_fifo" {  } { { "mac_ip/altera_tse_dc_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_dc_fifo.v" 52 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435443 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435443 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_sys.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_sys.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_sys " "Found entity 1: pll_sys" {  } { { "pll_sys.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/pll_sys.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246435447 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246435447 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "project_top " "Elaborating entity \"project_top\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1589246435711 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mac_reg mac_reg:mac_reg_ins " "Elaborating entity \"mac_reg\" for hierarchy \"mac_reg:mac_reg_ins\"" {  } { { "project_top.v" "mac_reg_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 114 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435715 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mac_reg_config mac_reg_config:mac_reg_config_ins " "Elaborating entity \"mac_reg_config\" for hierarchy \"mac_reg_config:mac_reg_config_ins\"" {  } { { "project_top.v" "mac_reg_config_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 134 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435718 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mac_ip_0002 mac_ip_0002:mac_ip_inst " "Elaborating entity \"mac_ip_0002\" for hierarchy \"mac_ip_0002:mac_ip_inst\"" {  } { { "project_top.v" "mac_ip_inst" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435721 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_eth_tse_mac mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac " "Elaborating entity \"altera_eth_tse_mac\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\"" {  } { { "mac_ip/mac_ip_0002.v" "i_tse_mac" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435730 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_reset_synchronizer mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_0 " "Elaborating entity \"altera_tse_reset_synchronizer\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_0\"" {  } { { "mac_ip/altera_eth_tse_mac.v" "reset_sync_0" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 479 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435742 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mac_control mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL " "Elaborating entity \"altera_tse_mac_control\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\"" {  } { { "mac_ip/altera_eth_tse_mac.v" "U_MAC_CONTROL" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 708 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435756 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_register_map mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG " "Elaborating entity \"altera_tse_register_map\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\"" {  } { { "mac_ip/altera_tse_mac_control.v" "U_REG" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_control.v" 620 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435773 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\|altera_std_synchronizer:U_SYNC_1 " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\|altera_std_synchronizer:U_SYNC_1\"" {  } { { "mac_ip/altera_tse_register_map.v" "U_SYNC_1" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 439 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435797 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\|altera_std_synchronizer:U_SYNC_1 " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\|altera_std_synchronizer:U_SYNC_1\"" {  } { { "mac_ip/altera_tse_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 439 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246435798 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\|altera_std_synchronizer:U_SYNC_1 " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\|altera_std_synchronizer:U_SYNC_1\" with the following parameter:" {  } { { "mac_ip/altera_tse_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 439 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246435798 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_host_control mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_host_control:U_CTRL " "Elaborating entity \"altera_tse_host_control\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_host_control:U_CTRL\"" {  } { { "mac_ip/altera_tse_mac_control.v" "U_CTRL" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_control.v" 661 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435814 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_top_mdio mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO " "Elaborating entity \"altera_tse_top_mdio\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\"" {  } { { "mac_ip/altera_eth_tse_mac.v" "U_MDIO" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 747 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435831 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mdio_clk_gen mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\|altera_tse_mdio_clk_gen:U_CLKGEN " "Elaborating entity \"altera_tse_mdio_clk_gen\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\|altera_tse_mdio_clk_gen:U_CLKGEN\"" {  } { { "mac_ip/altera_tse_top_mdio.v" "U_CLKGEN" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_mdio.v" 105 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435845 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mdio_cntl mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\|altera_tse_mdio_cntl:U_CNTL " "Elaborating entity \"altera_tse_mdio_cntl\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\|altera_tse_mdio_cntl:U_CNTL\"" {  } { { "mac_ip/altera_tse_top_mdio.v" "U_CNTL" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_mdio.v" 130 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435860 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mdio mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\|altera_tse_mdio:U_MDIO " "Elaborating entity \"altera_tse_mdio\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\|altera_tse_mdio:U_MDIO\"" {  } { { "mac_ip/altera_tse_top_mdio.v" "U_MDIO" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_mdio.v" 147 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435874 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_top_w_fifo_10_100_1000 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP " "Elaborating entity \"altera_tse_top_w_fifo_10_100_1000\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\"" {  } { { "mac_ip/altera_eth_tse_mac.v" "U_MAC_TOP" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435890 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_clk_cntl mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_clk_cntl:U_CLKCT " "Elaborating entity \"altera_tse_clk_cntl\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_clk_cntl:U_CLKCT\"" {  } { { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "U_CLKCT" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 476 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435908 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mii_rx_if mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_mii_rx_if:U_MRX " "Elaborating entity \"altera_tse_mii_rx_if\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_mii_rx_if:U_MRX\"" {  } { { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "U_MRX" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 491 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435924 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mii_tx_if mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_mii_tx_if:U_MTX " "Elaborating entity \"altera_tse_mii_tx_if\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_mii_tx_if:U_MTX\"" {  } { { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "U_MTX" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 504 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435939 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_gmii_io mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_gmii_io:U_GMIF " "Elaborating entity \"altera_tse_gmii_io\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_gmii_io:U_GMIF\"" {  } { { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "U_GMIF" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 548 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435955 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_top_w_fifo mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC " "Elaborating entity \"altera_tse_top_w_fifo\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\"" {  } { { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "U_MAC" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435972 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_top_1geth mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH " "Elaborating entity \"altera_tse_top_1geth\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\"" {  } { { "mac_ip/altera_tse_top_w_fifo.v" "U_GETH" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 530 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246435989 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_rx_stat_extract mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_rx_stat_extract:U_RXSTAT " "Elaborating entity \"altera_tse_rx_stat_extract\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_rx_stat_extract:U_RXSTAT\"" {  } { { "mac_ip/altera_tse_top_1geth.v" "U_RXSTAT" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_1geth.v" 389 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436006 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mac_rx mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX " "Elaborating entity \"altera_tse_mac_rx\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\"" {  } { { "mac_ip/altera_tse_top_1geth.v" "U_RX" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_1geth.v" 457 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436024 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_crc328checker mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_crc328checker:U_CRC " "Elaborating entity \"altera_tse_crc328checker\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_crc328checker:U_CRC\"" {  } { { "mac_ip/altera_tse_mac_rx.v" "U_CRC" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 2676 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436054 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_crc32galois8 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_crc328checker:U_CRC\|altera_tse_crc32galois8:U_GALS " "Elaborating entity \"altera_tse_crc32galois8\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_crc328checker:U_CRC\|altera_tse_crc32galois8:U_GALS\"" {  } { { "mac_ip/altera_tse_crc328checker.v" "U_GALS" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_crc328checker.v" 110 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436069 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_altshifttaps mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS " "Elaborating entity \"altera_tse_altshifttaps\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\"" {  } { { "mac_ip/altera_tse_mac_rx.v" "U_SHIFTTAPS" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 3112 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436084 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_tx_stat_extract mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_tx_stat_extract:U_TXSTAT " "Elaborating entity \"altera_tse_tx_stat_extract\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_tx_stat_extract:U_TXSTAT\"" {  } { { "mac_ip/altera_tse_top_1geth.v" "U_TXSTAT" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_1geth.v" 489 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436099 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mac_tx mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX " "Elaborating entity \"altera_tse_mac_tx\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\"" {  } { { "mac_ip/altera_tse_top_1geth.v" "U_TX" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_1geth.v" 538 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436116 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer_bundle mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3 " "Elaborating entity \"altera_std_synchronizer_bundle\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\"" {  } { { "mac_ip/altera_tse_mac_tx.v" "U_SYNC_3" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 418 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436139 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3 " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\"" {  } { { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 418 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246436140 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3 " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\" with the following parameter:" {  } { { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 418 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246436140 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\|altera_std_synchronizer:sync\[0\].u " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\|altera_std_synchronizer:sync\[0\].u\"" {  } { { "altera_std_synchronizer_bundle.v" "sync\[0\].u" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altera_std_synchronizer_bundle.v" 41 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436142 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\|altera_std_synchronizer:sync\[0\].u mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3 " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\|altera_std_synchronizer:sync\[0\].u\", which is child of megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\"" {  } { { "altera_std_synchronizer_bundle.v" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altera_std_synchronizer_bundle.v" 41 0 0 } } { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 418 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436143 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_crc328generator mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_tse_crc328generator:U_CRC " "Elaborating entity \"altera_tse_crc328generator\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_tse_crc328generator:U_CRC\"" {  } { { "mac_ip/altera_tse_mac_tx.v" "U_CRC" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 2321 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436157 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_crc32ctl8 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_tse_crc328generator:U_CRC\|altera_tse_crc32ctl8:U_CTL " "Elaborating entity \"altera_tse_crc32ctl8\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_tse_crc328generator:U_CRC\|altera_tse_crc32ctl8:U_CTL\"" {  } { { "mac_ip/altera_tse_crc328generator.v" "U_CTL" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_crc328generator.v" 104 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436173 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_rx_min_ff mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF " "Elaborating entity \"altera_tse_rx_min_ff\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\"" {  } { { "mac_ip/altera_tse_top_w_fifo.v" "U_RXFF" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436188 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer_bundle mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_std_synchronizer_bundle:U_SYNC_2 " "Elaborating entity \"altera_std_synchronizer_bundle\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_std_synchronizer_bundle:U_SYNC_2\"" {  } { { "mac_ip/altera_tse_rx_min_ff.v" "U_SYNC_2" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 204 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436199 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_std_synchronizer_bundle:U_SYNC_2 " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_std_synchronizer_bundle:U_SYNC_2\"" {  } { { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 204 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246436200 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_std_synchronizer_bundle:U_SYNC_2 " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_std_synchronizer_bundle:U_SYNC_2\" with the following parameter:" {  } { { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 204 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246436200 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_a_fifo_opt_1246 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA " "Elaborating entity \"altera_tse_a_fifo_opt_1246\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\"" {  } { { "mac_ip/altera_tse_rx_min_ff.v" "RX_DATA" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436243 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_altsyncram_dpm_fifo mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM " "Elaborating entity \"altera_tse_altsyncram_dpm_fifo\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\"" {  } { { "mac_ip/altera_tse_a_fifo_opt_1246.v" "U_RAM" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436259 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "altsyncram_component" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436319 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246436323 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 40 " "Parameter \"width_a\" = \"40\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 40 " "Parameter \"width_b\" = \"40\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436324 ""}  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246436324 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_cfg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_cfg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_cfg1 " "Found entity 1: altsyncram_cfg1" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246436388 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246436388 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_cfg1 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated " "Elaborating entity \"altsyncram_cfg1\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436391 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_gray_cnt mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_gray_cnt:U_WRT " "Elaborating entity \"altera_tse_gray_cnt\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_gray_cnt:U_WRT\"" {  } { { "mac_ip/altera_tse_a_fifo_opt_1246.v" "U_WRT" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 184 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436403 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_a_fifo_34 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS " "Elaborating entity \"altera_tse_a_fifo_34\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\"" {  } { { "mac_ip/altera_tse_rx_min_ff.v" "RX_STATUS" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436493 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_altsyncram_dpm_fifo mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM " "Elaborating entity \"altera_tse_altsyncram_dpm_fifo\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\"" {  } { { "mac_ip/altera_tse_a_fifo_34.v" "U_RAM" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436502 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "altsyncram_component" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436511 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 512 " "Parameter \"numwords_a\" = \"512\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 512 " "Parameter \"numwords_b\" = \"512\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 9 " "Parameter \"widthad_a\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 9 " "Parameter \"widthad_b\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 23 " "Parameter \"width_a\" = \"23\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 23 " "Parameter \"width_b\" = \"23\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436515 ""}  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246436515 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9g1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9g1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9g1 " "Found entity 1: altsyncram_g9g1" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246436576 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246436576 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9g1 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated " "Elaborating entity \"altsyncram_g9g1\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436579 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_gray_cnt mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_gray_cnt:U_WRT " "Elaborating entity \"altera_tse_gray_cnt\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_gray_cnt:U_WRT\"" {  } { { "mac_ip/altera_tse_a_fifo_34.v" "U_WRT" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 124 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436583 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_bin_cnt mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_bin_cnt:U_RD " "Elaborating entity \"altera_tse_bin_cnt\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_bin_cnt:U_RD\"" {  } { { "mac_ip/altera_tse_a_fifo_34.v" "U_RD" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 132 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436592 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_tx_min_ff mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF " "Elaborating entity \"altera_tse_tx_min_ff\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\"" {  } { { "mac_ip/altera_tse_top_w_fifo.v" "U_TXFF" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 674 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436607 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_a_fifo_opt_1246 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA " "Elaborating entity \"altera_tse_a_fifo_opt_1246\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\"" {  } { { "mac_ip/altera_tse_tx_min_ff.v" "TX_DATA" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_min_ff.v" 463 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436652 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_altsyncram_dpm_fifo mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM " "Elaborating entity \"altera_tse_altsyncram_dpm_fifo\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\"" {  } { { "mac_ip/altera_tse_a_fifo_opt_1246.v" "U_RAM" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436655 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "altsyncram_component" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436664 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 36 " "Parameter \"width_a\" = \"36\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 36 " "Parameter \"width_b\" = \"36\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436669 ""}  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246436669 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_mfg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_mfg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_mfg1 " "Found entity 1: altsyncram_mfg1" {  } { { "db/altsyncram_mfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_mfg1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246436731 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246436731 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_mfg1 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_mfg1:auto_generated " "Elaborating entity \"altsyncram_mfg1\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_mfg1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436733 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_a_fifo_13 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS " "Elaborating entity \"altera_tse_a_fifo_13\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\"" {  } { { "mac_ip/altera_tse_tx_min_ff.v" "TX_STATUS" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_min_ff.v" 486 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436822 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_altsyncram_dpm_fifo mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM " "Elaborating entity \"altera_tse_altsyncram_dpm_fifo\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\"" {  } { { "mac_ip/altera_tse_a_fifo_13.v" "U_RAM" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 119 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436830 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "altsyncram_component" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436838 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 512 " "Parameter \"numwords_a\" = \"512\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 512 " "Parameter \"numwords_b\" = \"512\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 9 " "Parameter \"widthad_a\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 9 " "Parameter \"widthad_b\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 2 " "Parameter \"width_a\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 2 " "Parameter \"width_b\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436844 ""}  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246436844 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_a6g1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_a6g1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_a6g1 " "Found entity 1: altsyncram_a6g1" {  } { { "db/altsyncram_a6g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_a6g1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246436900 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246436900 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_a6g1 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_a6g1:auto_generated " "Elaborating entity \"altsyncram_a6g1\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_a6g1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436903 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer_bundle mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_std_synchronizer_bundle:U_SYNC_1 " "Elaborating entity \"altera_std_synchronizer_bundle\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_std_synchronizer_bundle:U_SYNC_1\"" {  } { { "mac_ip/altera_tse_a_fifo_13.v" "U_SYNC_1" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 146 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436910 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_std_synchronizer_bundle:U_SYNC_1 " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_std_synchronizer_bundle:U_SYNC_1\"" {  } { { "mac_ip/altera_tse_a_fifo_13.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 146 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246436911 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_std_synchronizer_bundle:U_SYNC_1 " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_std_synchronizer_bundle:U_SYNC_1\" with the following parameter:" {  } { { "mac_ip/altera_tse_a_fifo_13.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 146 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246436911 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_transmit data_transmit:data_transmit_ins " "Elaborating entity \"data_transmit\" for hierarchy \"data_transmit:data_transmit_ins\"" {  } { { "project_top.v" "data_transmit_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 223 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436943 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "flag_f012 data_transmit.v(47) " "Verilog HDL or VHDL warning at data_transmit.v(47): object \"flag_f012\" assigned a value but never read" {  } { { "data_transmit.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_transmit.v" 47 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1589246436951 "|project_top|data_transmit:data_transmit_ins"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_receive data_receive:data_receive_ins " "Elaborating entity \"data_receive\" for hierarchy \"data_receive:data_receive_ins\"" {  } { { "project_top.v" "data_receive_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 246 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436953 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 data_receive.v(93) " "Verilog HDL assignment warning at data_receive.v(93): truncated value with size 32 to match size of target (8)" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 93 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1589246436954 "|project_top|data_receive:data_receive_ins"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ip_sour data_receive.v(55) " "Output port \"ip_sour\" at data_receive.v(55) has no driver" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 55 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1589246436954 "|project_top|data_receive:data_receive_ins"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "mac_sour data_receive.v(56) " "Output port \"mac_sour\" at data_receive.v(56) has no driver" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 56 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1589246436954 "|project_top|data_receive:data_receive_ins"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "cmd_arq data_receive.v(52) " "Output port \"cmd_arq\" at data_receive.v(52) has no driver" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 52 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1589246436954 "|project_top|data_receive:data_receive_ins"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "cmd_start data_receive.v(53) " "Output port \"cmd_start\" at data_receive.v(53) has no driver" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 53 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1589246436954 "|project_top|data_receive:data_receive_ins"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "cmd_stop data_receive.v(54) " "Output port \"cmd_stop\" at data_receive.v(54) has no driver" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 54 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1589246436954 "|project_top|data_receive:data_receive_ins"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys pll_sys:pll_sys_ins " "Elaborating entity \"pll_sys\" for hierarchy \"pll_sys:pll_sys_ins\"" {  } { { "project_top.v" "pll_sys_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 253 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246436957 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll_sys:pll_sys_ins\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"pll_sys:pll_sys_ins\|altpll:altpll_component\"" {  } { { "pll_sys.v" "altpll_component" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/pll_sys.v" 98 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437002 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "pll_sys:pll_sys_ins\|altpll:altpll_component " "Elaborated megafunction instantiation \"pll_sys:pll_sys_ins\|altpll:altpll_component\"" {  } { { "pll_sys.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/pll_sys.v" 98 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "pll_sys:pll_sys_ins\|altpll:altpll_component " "Instantiated megafunction \"pll_sys:pll_sys_ins\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5 " "Parameter \"clk0_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 2 " "Parameter \"clk1_divide_by\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 5 " "Parameter \"clk1_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 4 " "Parameter \"clk2_divide_by\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 5 " "Parameter \"clk2_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 50000 " "Parameter \"inclk0_input_frequency\" = \"50000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll_sys " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll_sys\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437006 ""}  } { { "pll_sys.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/pll_sys.v" 98 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246437006 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_sys_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_sys_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_sys_altpll " "Found entity 1: pll_sys_altpll" {  } { { "db/pll_sys_altpll.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/pll_sys_altpll.v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246437069 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246437069 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys_altpll pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated " "Elaborating entity \"pll_sys_altpll\" for hierarchy \"pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437072 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led led:led_ins " "Elaborating entity \"led\" for hierarchy \"led:led_ins\"" {  } { { "project_top.v" "led_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 263 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437076 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cnt_enable led.v(27) " "Verilog HDL or VHDL warning at led.v(27): object \"cnt_enable\" assigned a value but never read" {  } { { "led.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/led.v" 27 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1589246437077 "|project_top|led:led_ins"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dp83848_rst dp83848_rst:dp83848_rst_ins " "Elaborating entity \"dp83848_rst\" for hierarchy \"dp83848_rst:dp83848_rst_ins\"" {  } { { "project_top.v" "dp83848_rst_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 270 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246437079 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_c124.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_c124.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_c124 " "Found entity 1: altsyncram_c124" {  } { { "db/altsyncram_c124.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_c124.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246438626 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246438626 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_tsc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_tsc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_tsc " "Found entity 1: mux_tsc" {  } { { "db/mux_tsc.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/mux_tsc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246438802 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246438802 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_dvf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_dvf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_dvf " "Found entity 1: decode_dvf" {  } { { "db/decode_dvf.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/decode_dvf.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246438879 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246438879 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_kgi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_kgi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_kgi " "Found entity 1: cntr_kgi" {  } { { "db/cntr_kgi.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cntr_kgi.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246438997 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246438997 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_sgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_sgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_sgc " "Found entity 1: cmpr_sgc" {  } { { "db/cmpr_sgc.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cmpr_sgc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246439059 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246439059 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_m9j.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_m9j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_m9j " "Found entity 1: cntr_m9j" {  } { { "db/cntr_m9j.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cntr_m9j.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246439146 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246439146 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ggi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_ggi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ggi " "Found entity 1: cntr_ggi" {  } { { "db/cntr_ggi.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cntr_ggi.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246439245 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246439245 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_rgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_rgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_rgc " "Found entity 1: cmpr_rgc" {  } { { "db/cmpr_rgc.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cmpr_rgc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246439302 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246439302 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_23j.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_23j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_23j " "Found entity 1: cntr_23j" {  } { { "db/cntr_23j.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cntr_23j.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246439384 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246439384 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ngc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ngc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ngc " "Found entity 1: cmpr_ngc" {  } { { "db/cmpr_ngc.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cmpr_ngc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246439440 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246439440 ""}
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" {  } {  } 0 12033 "Analysis and Synthesis generated SignalTap II or debug node instance \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246439521 ""}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_a6g1:auto_generated\|q_b\[0\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_a6g1:auto_generated\|q_b\[0\]\"" {  } { { "db/altsyncram_a6g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_a6g1.tdf" 38 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_13.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 119 0 0 } } { "mac_ip/altera_tse_tx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_min_ff.v" 486 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 674 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_a6g1:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[4\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[4\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 162 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[5\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[5\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 193 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[6\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[6\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 224 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[7\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[7\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 255 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[8\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[8\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 286 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[9\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[9\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 317 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[10\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[10\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 348 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[11\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[11\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 379 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[12\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[12\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 410 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[13\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[13\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 441 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[14\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[14\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 472 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[15\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[15\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 503 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[16\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[16\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 534 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[17\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[17\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 565 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[18\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[18\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 596 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a18"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[19\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[19\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 627 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a19"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[20\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[20\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 658 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a20"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[22\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[22\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 720 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a22"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[34\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[34\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 1092 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a34"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[35\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[35\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 1123 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a35"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[36\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[36\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 1154 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a36"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[37\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[37\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 1185 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a37"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[38\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[38\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 1216 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246440083 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a38"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Quartus II" 0 -1 1589246440083 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Quartus II" 0 -1 1589246440083 ""}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IINFER_ALTSHIFT_TAPS_INFERRED" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\|shift_reg_rtl_0 " "Inferred altshift_taps megafunction from the following design logic: \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\|shift_reg_rtl_0\"" { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMBER_OF_TAPS 1 " "Parameter NUMBER_OF_TAPS set to 1" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1589246442043 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "TAP_DISTANCE 16 " "Parameter TAP_DISTANCE set to 16" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1589246442043 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH 8 " "Parameter WIDTH set to 8" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1589246442043 ""}  } {  } 0 276034 "Inferred altshift_taps megafunction from the following design logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246442043 ""}  } {  } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1589246442043 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\|altshift_taps:shift_reg_rtl_0 " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\|altshift_taps:shift_reg_rtl_0\"" {  } {  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246442083 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\|altshift_taps:shift_reg_rtl_0 " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\|altshift_taps:shift_reg_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMBER_OF_TAPS 1 " "Parameter \"NUMBER_OF_TAPS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246442084 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "TAP_DISTANCE 16 " "Parameter \"TAP_DISTANCE\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246442084 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH 8 " "Parameter \"WIDTH\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246442084 ""}  } {  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246442084 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_unm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/shift_taps_unm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_unm " "Found entity 1: shift_taps_unm" {  } { { "db/shift_taps_unm.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/shift_taps_unm.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246442137 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246442137 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ce81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_ce81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ce81 " "Found entity 1: altsyncram_ce81" {  } { { "db/altsyncram_ce81.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_ce81.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246442195 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246442195 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_qqf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_qqf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_qqf " "Found entity 1: cntr_qqf" {  } { { "db/cntr_qqf.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cntr_qqf.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246442252 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246442252 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_qgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_qgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_qgc " "Found entity 1: cmpr_qgc" {  } { { "db/cmpr_qgc.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cmpr_qgc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246442307 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246442307 ""}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1589246443470 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "dp83848_rst.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/dp83848_rst.v" 14 -1 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 366 -1 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 192 -1 0 } } { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 76 -1 0 } } { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 271 -1 0 } } { "mac_ip/altera_tse_mac_rx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 368 -1 0 } } { "mac_ip/altera_tse_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 2151 -1 0 } } { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 183 -1 0 } } { "mac_ip/altera_tse_a_fifo_13.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 245 -1 0 } } { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 155 -1 0 } } { "mac_ip/altera_tse_tx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_min_ff.v" 125 -1 0 } } { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 193 -1 0 } } { "mac_reg_config.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_reg_config.v" 54 -1 0 } } { "mac_ip/altera_tse_mac_rx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 1674 -1 0 } } { "mac_ip/altera_tse_tx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_min_ff.v" 507 -1 0 } } { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 795 -1 0 } } { "mac_ip/altera_tse_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 849 -1 0 } } { "mac_ip/altera_tse_mac_rx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 370 -1 0 } } { "mac_ip/altera_tse_mac_rx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 307 -1 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 412 -1 0 } } { "mac_ip/altera_tse_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 2114 -1 0 } } { "data_transmit.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_transmit.v" 209 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1589246443656 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1589246443657 ""}
{ "Warning" "WMLS_MLS_ENABLED_OE" "" "TRI or OPNDRN buffers permanently enabled" { { "Warning" "WMLS_MLS_NODE_NAME" "eth_mdio~synth " "Node \"eth_mdio~synth\"" {  } { { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 36 -1 0 } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246444303 ""}  } {  } 0 13009 "TRI or OPNDRN buffers permanently enabled" 0 0 "Quartus II" 0 -1 1589246444303 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246444597 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "89 " "89 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1589246445692 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "sld_buffer_manager.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 350 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1589246445831 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1589246445831 ""}
{ "Warning" "WFTM_IGNORED_NOT_GATE_PUSH_ASSIGNMENT" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|trigger_out_mode_ff " "The assignment to disallow NOT gate push-back on register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|trigger_out_mode_ff\" is ignored" {  } { { "sld_signaltap_impl.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd" 942 -1 0 } }  } 0 18057 "The assignment to disallow NOT gate push-back on register \"%1!s!\" is ignored" 0 0 "Quartus II" 0 -1 1589246446003 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_signaltap:auto_signaltap_0 " "Timing-Driven Synthesis is running on partition \"sld_signaltap:auto_signaltap_0\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246446164 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "sld_jtag_hub.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 384 -1 0 } } { "sld_jtag_hub.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 521 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1589246446641 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1589246446641 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "sld_hub:auto_hub\|receive\[0\]\[0\] GND " "Pin \"sld_hub:auto_hub\|receive\[0\]\[0\]\" is stuck at GND" {  } { { "sld_hub.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_hub.vhd" 181 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1589246446690 "|project_top|sld_hub:auto_hub|receive[0][0]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1589246446690 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_hub:auto_hub " "Timing-Driven Synthesis is running on partition \"sld_hub:auto_hub\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246446812 ""}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "mac_ip " "Ignored assignments for entity \"mac_ip\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_NAME altera_eth_tse -entity mac_ip -qip mac_ip.qip -library mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_NAME altera_eth_tse -entity mac_ip -qip mac_ip.qip -library mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246447042 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_NAME altera_eth_tse -entity mac_ip -sip mac_ip.sip -library lib_mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_NAME altera_eth_tse -entity mac_ip -sip mac_ip.sip -library lib_mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246447042 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_VERSION 13.0sp1 -entity mac_ip -qip mac_ip.qip -library mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_VERSION 13.0sp1 -entity mac_ip -qip mac_ip.qip -library mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246447042 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_VERSION 13.0sp1 -entity mac_ip -sip mac_ip.sip -library lib_mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_VERSION 13.0sp1 -entity mac_ip -sip mac_ip.sip -library lib_mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246447042 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_ENV mwpim -entity mac_ip -qip mac_ip.qip -library mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_ENV mwpim -entity mac_ip -qip mac_ip.qip -library mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246447042 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_ENV mwpim -entity mac_ip -sip mac_ip.sip -library lib_mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_ENV mwpim -entity mac_ip -sip mac_ip.sip -library lib_mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246447042 ""}  } {  } 0 20013 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Quartus II" 0 -1 1589246447042 ""}
{ "Info" "IAMERGE_SLD_INSTANCE_WITH_FULL_CONNECTIONS" "auto_signaltap_0 75 " "Succesfully connected in-system debug instance \"auto_signaltap_0\" to all 75 required data inputs, trigger inputs, acquisition clocks, and dynamic pins" {  } {  } 0 35024 "Succesfully connected in-system debug instance \"%1!s!\" to all %2!d! required data inputs, trigger inputs, acquisition clocks, and dynamic pins" 0 0 "Quartus II" 0 -1 1589246448335 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1589246448410 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246448410 ""}
{ "Warning" "WCUT_PLL_MULT_DIV_SPECIFIED_CLOCK_NOT_CONNECTED" "pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 CLK\[1\] clk1_multiply_by clk1_divide_by " "PLL \"pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK\[1\] is not connected" {  } { { "db/pll_sys_altpll.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/pll_sys_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "pll_sys.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/pll_sys.v" 98 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 253 0 0 } }  } 0 15899 "PLL \"%1!s!\" has parameters %3!s! and %4!s! specified but port %2!s! is not connected" 0 0 "Quartus II" 0 -1 1589246448650 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "crs " "No output dependent on input pin \"crs\"" {  } { { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 28 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246448884 "|project_top|crs"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "col " "No output dependent on input pin \"col\"" {  } { { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 29 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246448884 "|project_top|col"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1589246448884 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "4061 " "Implemented 4061 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "15 " "Implemented 15 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1589246448885 ""} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Implemented 9 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1589246448885 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "1 " "Implemented 1 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1589246448885 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3912 " "Implemented 3912 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1589246448885 ""} { "Info" "ICUT_CUT_TM_RAMS" "122 " "Implemented 122 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1589246448885 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1589246448885 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1589246448885 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 51 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 51 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "596 " "Peak virtual memory: 596 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1589246448940 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 12 09:20:48 2020 " "Processing ended: Tue May 12 09:20:48 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1589246448940 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1589246448940 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:18 " "Total CPU time (on all processors): 00:00:18" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1589246448940 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1589246448940 ""}
