{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1589246101414 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1589246101415 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 12 09:15:01 2020 " "Processing started: Tue May 12 09:15:01 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1589246101415 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1589246101415 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off project_top -c project_top " "Command: quartus_map --read_settings_files=on --write_settings_files=off project_top -c project_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1589246101415 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1589246101695 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "project_top.v 1 1 " "Found 1 design units, including 1 entities, in source file project_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 project_top " "Found entity 1: project_top" {  } { { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101743 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101743 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_reg_config.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_reg_config.v" { { "Info" "ISGN_ENTITY_NAME" "1 mac_reg_config " "Found entity 1: mac_reg_config" {  } { { "mac_reg_config.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_reg_config.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101746 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101746 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_reg.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_reg.v" { { "Info" "ISGN_ENTITY_NAME" "1 mac_reg " "Found entity 1: mac_reg" {  } { { "mac_reg.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_reg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101748 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101748 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip.v" { { "Info" "ISGN_ENTITY_NAME" "1 mac_ip " "Found entity 1: mac_ip" {  } { { "mac_ip.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip.v" 8 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101750 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101750 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led.v 1 1 " "Found 1 design units, including 1 entities, in source file led.v" { { "Info" "ISGN_ENTITY_NAME" "1 led " "Found entity 1: led" {  } { { "led.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/led.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101752 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101752 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dp83848_rst.v 1 1 " "Found 1 design units, including 1 entities, in source file dp83848_rst.v" { { "Info" "ISGN_ENTITY_NAME" "1 dp83848_rst " "Found entity 1: dp83848_rst" {  } { { "dp83848_rst.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/dp83848_rst.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101754 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101754 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_transmit.v 1 1 " "Found 1 design units, including 1 entities, in source file data_transmit.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_transmit " "Found entity 1: data_transmit" {  } { { "data_transmit.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_transmit.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101757 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101757 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_receive.v 1 1 " "Found 1 design units, including 1 entities, in source file data_receive.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_receive " "Found entity 1: data_receive" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101759 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101759 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip.v" { { "Info" "ISGN_ENTITY_NAME" "1 mac_ip " "Found entity 1: mac_ip" {  } { { "mac_ip.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip.v" 8 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101761 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101761 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/mac_ip_0002.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/mac_ip_0002.v" { { "Info" "ISGN_ENTITY_NAME" "1 mac_ip_0002 " "Found entity 1: mac_ip_0002" {  } { { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101764 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101764 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_eth_tse_mac.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_eth_tse_mac.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_eth_tse_mac " "Found entity 1: altera_eth_tse_mac" {  } { { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101876 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101876 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_clk_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_clk_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_clk_cntl " "Found entity 1: altera_tse_clk_cntl" {  } { { "mac_ip/altera_tse_clk_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_clk_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101897 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101897 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_crc328checker.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_crc328checker.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_crc328checker " "Found entity 1: altera_tse_crc328checker" {  } { { "mac_ip/altera_tse_crc328checker.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_crc328checker.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101917 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101917 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_crc328generator.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_crc328generator.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_crc328generator " "Found entity 1: altera_tse_crc328generator" {  } { { "mac_ip/altera_tse_crc328generator.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_crc328generator.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101936 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101936 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_crc32ctl8.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_crc32ctl8.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_crc32ctl8 " "Found entity 1: altera_tse_crc32ctl8" {  } { { "mac_ip/altera_tse_crc32ctl8.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_crc32ctl8.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101953 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101953 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_crc32galois8.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_crc32galois8.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_crc32galois8 " "Found entity 1: altera_tse_crc32galois8" {  } { { "mac_ip/altera_tse_crc32galois8.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_crc32galois8.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246101978 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246101978 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_gmii_io.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_gmii_io.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_gmii_io " "Found entity 1: altera_tse_gmii_io" {  } { { "mac_ip/altera_tse_gmii_io.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_gmii_io.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102002 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102002 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_lb_read_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_lb_read_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_lb_read_cntl " "Found entity 1: altera_tse_lb_read_cntl" {  } { { "mac_ip/altera_tse_lb_read_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_lb_read_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102021 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102021 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_lb_wrt_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_lb_wrt_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_lb_wrt_cntl " "Found entity 1: altera_tse_lb_wrt_cntl" {  } { { "mac_ip/altera_tse_lb_wrt_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_lb_wrt_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102041 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102041 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_hashing.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_hashing.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_hashing " "Found entity 1: altera_tse_hashing" {  } { { "mac_ip/altera_tse_hashing.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_hashing.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102062 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102062 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_host_control.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_host_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_host_control " "Found entity 1: altera_tse_host_control" {  } { { "mac_ip/altera_tse_host_control.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_host_control.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102094 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102094 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_host_control_small.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_host_control_small.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_host_control_small " "Found entity 1: altera_tse_host_control_small" {  } { { "mac_ip/altera_tse_host_control_small.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_host_control_small.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102125 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102125 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mac_control.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mac_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mac_control " "Found entity 1: altera_tse_mac_control" {  } { { "mac_ip/altera_tse_mac_control.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_control.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102203 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102203 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_register_map.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_register_map.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_register_map " "Found entity 1: altera_tse_register_map" {  } { { "mac_ip/altera_tse_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102351 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102351 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_register_map_small.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_register_map_small.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_register_map_small " "Found entity 1: altera_tse_register_map_small" {  } { { "mac_ip/altera_tse_register_map_small.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map_small.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102488 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102488 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_counter_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_counter_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_counter_cntl " "Found entity 1: altera_tse_rx_counter_cntl" {  } { { "mac_ip/altera_tse_rx_counter_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_counter_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102539 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102539 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_shared_mac_control.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_shared_mac_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_shared_mac_control " "Found entity 1: altera_tse_shared_mac_control" {  } { { "mac_ip/altera_tse_shared_mac_control.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_shared_mac_control.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102598 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102598 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_shared_register_map.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_shared_register_map.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_shared_register_map " "Found entity 1: altera_tse_shared_register_map" {  } { { "mac_ip/altera_tse_shared_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_shared_register_map.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102749 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102749 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_counter_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_counter_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_counter_cntl " "Found entity 1: altera_tse_tx_counter_cntl" {  } { { "mac_ip/altera_tse_tx_counter_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_counter_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102789 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102789 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_lfsr_10.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_lfsr_10.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_lfsr_10 " "Found entity 1: altera_tse_lfsr_10" {  } { { "mac_ip/altera_tse_lfsr_10.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_lfsr_10.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102809 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102809 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_loopback_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_loopback_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_loopback_ff " "Found entity 1: altera_tse_loopback_ff" {  } { { "mac_ip/altera_tse_loopback_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_loopback_ff.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102832 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102832 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_altshifttaps.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_altshifttaps.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_altshifttaps " "Found entity 1: altera_tse_altshifttaps" {  } { { "mac_ip/altera_tse_altshifttaps.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altshifttaps.v" 32 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246102849 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246102849 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_fifoless_mac_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_fifoless_mac_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_fifoless_mac_rx " "Found entity 1: altera_tse_fifoless_mac_rx" {  } { { "mac_ip/altera_tse_fifoless_mac_rx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_fifoless_mac_rx.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103035 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103035 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mac_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mac_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mac_rx " "Found entity 1: altera_tse_mac_rx" {  } { { "mac_ip/altera_tse_mac_rx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103208 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103208 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_fifoless_mac_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_fifoless_mac_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_fifoless_mac_tx " "Found entity 1: altera_tse_fifoless_mac_tx" {  } { { "mac_ip/altera_tse_fifoless_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_fifoless_mac_tx.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103371 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103371 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mac_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mac_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mac_tx " "Found entity 1: altera_tse_mac_tx" {  } { { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103515 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103515 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_magic_detection.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_magic_detection.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_magic_detection " "Found entity 1: altera_tse_magic_detection" {  } { { "mac_ip/altera_tse_magic_detection.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_magic_detection.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103554 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103554 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mdio.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mdio.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mdio " "Found entity 1: altera_tse_mdio" {  } { { "mac_ip/altera_tse_mdio.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mdio.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103593 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103593 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mdio_clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mdio_clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mdio_clk_gen " "Found entity 1: altera_tse_mdio_clk_gen" {  } { { "mac_ip/altera_tse_mdio_clk_gen.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mdio_clk_gen.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103612 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103612 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mdio_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mdio_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mdio_cntl " "Found entity 1: altera_tse_mdio_cntl" {  } { { "mac_ip/altera_tse_mdio_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mdio_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103639 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103639 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_mdio.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_mdio.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_mdio " "Found entity 1: altera_tse_top_mdio" {  } { { "mac_ip/altera_tse_top_mdio.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_mdio.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103664 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103664 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mii_rx_if.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mii_rx_if.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mii_rx_if " "Found entity 1: altera_tse_mii_rx_if" {  } { { "mac_ip/altera_tse_mii_rx_if.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mii_rx_if.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103691 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103691 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mii_tx_if.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mii_tx_if.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mii_tx_if " "Found entity 1: altera_tse_mii_tx_if" {  } { { "mac_ip/altera_tse_mii_tx_if.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mii_tx_if.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103712 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103712 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_pipeline_base " "Found entity 1: altera_tse_pipeline_base" {  } { { "mac_ip/altera_tse_pipeline_base.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_pipeline_base.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103732 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103732 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_pipeline_stage.sv 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_pipeline_stage.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_pipeline_stage " "Found entity 1: altera_tse_pipeline_stage" {  } { { "mac_ip/altera_tse_pipeline_stage.sv" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_pipeline_stage.sv" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103754 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103754 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_dpram_16x32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_dpram_16x32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_dpram_16x32 " "Found entity 1: altera_tse_dpram_16x32" {  } { { "mac_ip/altera_tse_dpram_16x32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_dpram_16x32.v" 52 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103783 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103783 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_dpram_8x32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_dpram_8x32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_dpram_8x32 " "Found entity 1: altera_tse_dpram_8x32" {  } { { "mac_ip/altera_tse_dpram_8x32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_dpram_8x32.v" 52 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103812 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103812 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_quad_16x32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_quad_16x32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_quad_16x32 " "Found entity 1: altera_tse_quad_16x32" {  } { { "mac_ip/altera_tse_quad_16x32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_quad_16x32.v" 52 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103838 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103838 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_quad_8x32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_quad_8x32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_quad_8x32 " "Found entity 1: altera_tse_quad_8x32" {  } { { "mac_ip/altera_tse_quad_8x32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_quad_8x32.v" 52 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103865 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103865 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_fifoless_retransmit_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_fifoless_retransmit_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_fifoless_retransmit_cntl " "Found entity 1: altera_tse_fifoless_retransmit_cntl" {  } { { "mac_ip/altera_tse_fifoless_retransmit_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_fifoless_retransmit_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103920 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103920 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_retransmit_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_retransmit_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_retransmit_cntl " "Found entity 1: altera_tse_retransmit_cntl" {  } { { "mac_ip/altera_tse_retransmit_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_retransmit_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103972 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103972 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rgmii_in1.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rgmii_in1.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rgmii_in1 " "Found entity 1: altera_tse_rgmii_in1" {  } { { "mac_ip/altera_tse_rgmii_in1.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rgmii_in1.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103974 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103974 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rgmii_in4.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rgmii_in4.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rgmii_in4 " "Found entity 1: altera_tse_rgmii_in4" {  } { { "mac_ip/altera_tse_rgmii_in4.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rgmii_in4.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103976 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103976 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rgmii_module.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rgmii_module.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rgmii_module " "Found entity 1: altera_tse_rgmii_module" {  } { { "mac_ip/altera_tse_rgmii_module.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rgmii_module.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103979 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103979 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rgmii_out1.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rgmii_out1.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rgmii_out1 " "Found entity 1: altera_tse_rgmii_out1" {  } { { "mac_ip/altera_tse_rgmii_out1.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rgmii_out1.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103981 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103981 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rgmii_out4.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rgmii_out4.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rgmii_out4 " "Found entity 1: altera_tse_rgmii_out4" {  } { { "mac_ip/altera_tse_rgmii_out4.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rgmii_out4.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246103983 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246103983 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_ff " "Found entity 1: altera_tse_rx_ff" {  } { { "mac_ip/altera_tse_rx_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_ff.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104028 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104028 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_min_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_min_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_min_ff " "Found entity 1: altera_tse_rx_min_ff" {  } { { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104084 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104084 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_ff_cntrl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_ff_cntrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_ff_cntrl " "Found entity 1: altera_tse_rx_ff_cntrl" {  } { { "mac_ip/altera_tse_rx_ff_cntrl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_ff_cntrl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104127 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104127 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_ff_cntrl_32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_ff_cntrl_32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_ff_cntrl_32 " "Found entity 1: altera_tse_rx_ff_cntrl_32" {  } { { "mac_ip/altera_tse_rx_ff_cntrl_32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_ff_cntrl_32.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104173 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104173 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_ff_cntrl_32_shift16.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_ff_cntrl_32_shift16.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_ff_cntrl_32_shift16 " "Found entity 1: altera_tse_rx_ff_cntrl_32_shift16" {  } { { "mac_ip/altera_tse_rx_ff_cntrl_32_shift16.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_ff_cntrl_32_shift16.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104231 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104231 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_ff_length.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_ff_length.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_ff_length " "Found entity 1: altera_tse_rx_ff_length" {  } { { "mac_ip/altera_tse_rx_ff_length.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_ff_length.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104250 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104250 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_rx_stat_extract.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_rx_stat_extract.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_rx_stat_extract " "Found entity 1: altera_tse_rx_stat_extract" {  } { { "mac_ip/altera_tse_rx_stat_extract.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_stat_extract.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104289 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104289 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_timing_adapter32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_timing_adapter32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_timing_adapter32 " "Found entity 1: altera_tse_timing_adapter32" {  } { { "mac_ip/altera_tse_timing_adapter32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_timing_adapter32.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104311 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104311 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_timing_adapter8.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_timing_adapter8.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_timing_adapter8 " "Found entity 1: altera_tse_timing_adapter8" {  } { { "mac_ip/altera_tse_timing_adapter8.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_timing_adapter8.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104333 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104333 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_timing_adapter_fifo32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_timing_adapter_fifo32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_timing_adapter_fifo32 " "Found entity 1: altera_tse_timing_adapter_fifo32" {  } { { "mac_ip/altera_tse_timing_adapter_fifo32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_timing_adapter_fifo32.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104364 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104364 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_timing_adapter_fifo8.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_timing_adapter_fifo8.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_timing_adapter_fifo8 " "Found entity 1: altera_tse_timing_adapter_fifo8" {  } { { "mac_ip/altera_tse_timing_adapter_fifo8.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_timing_adapter_fifo8.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104395 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104395 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_1geth.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_1geth.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_1geth " "Found entity 1: altera_tse_top_1geth" {  } { { "mac_ip/altera_tse_top_1geth.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_1geth.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104453 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104453 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_fifoless_1geth.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_fifoless_1geth.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_fifoless_1geth " "Found entity 1: altera_tse_top_fifoless_1geth" {  } { { "mac_ip/altera_tse_top_fifoless_1geth.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_fifoless_1geth.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104516 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104516 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_w_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_w_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_w_fifo " "Found entity 1: altera_tse_top_w_fifo" {  } { { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104601 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104601 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_w_fifo_10_100_1000.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_w_fifo_10_100_1000.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_w_fifo_10_100_1000 " "Found entity 1: altera_tse_top_w_fifo_10_100_1000" {  } { { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104684 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104684 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_wo_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_wo_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_wo_fifo " "Found entity 1: altera_tse_top_wo_fifo" {  } { { "mac_ip/altera_tse_top_wo_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_wo_fifo.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104772 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104772 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_wo_fifo_10_100_1000.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_wo_fifo_10_100_1000.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_wo_fifo_10_100_1000 " "Found entity 1: altera_tse_top_wo_fifo_10_100_1000" {  } { { "mac_ip/altera_tse_top_wo_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_wo_fifo_10_100_1000.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104867 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104867 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_mac_woff.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_mac_woff.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_mac_woff " "Found entity 1: altera_tse_mac_woff" {  } { { "mac_ip/altera_tse_mac_woff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_woff.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246104984 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246104984 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_top_gen_host.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_top_gen_host.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_top_gen_host " "Found entity 1: altera_tse_top_gen_host" {  } { { "mac_ip/altera_tse_top_gen_host.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_gen_host.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105094 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105094 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_ff " "Found entity 1: altera_tse_tx_ff" {  } { { "mac_ip/altera_tse_tx_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_ff.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105172 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105172 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_min_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_min_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_min_ff " "Found entity 1: altera_tse_tx_min_ff" {  } { { "mac_ip/altera_tse_tx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_min_ff.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105228 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105228 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_ff_cntrl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_ff_cntrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_ff_cntrl " "Found entity 1: altera_tse_tx_ff_cntrl" {  } { { "mac_ip/altera_tse_tx_ff_cntrl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_ff_cntrl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105257 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105257 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_ff_cntrl_32.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_ff_cntrl_32.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_ff_cntrl_32 " "Found entity 1: altera_tse_tx_ff_cntrl_32" {  } { { "mac_ip/altera_tse_tx_ff_cntrl_32.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_ff_cntrl_32.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105290 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105290 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_ff_cntrl_32_shift16.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_ff_cntrl_32_shift16.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_ff_cntrl_32_shift16 " "Found entity 1: altera_tse_tx_ff_cntrl_32_shift16" {  } { { "mac_ip/altera_tse_tx_ff_cntrl_32_shift16.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_ff_cntrl_32_shift16.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105328 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105328 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_ff_length.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_ff_length.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_ff_length " "Found entity 1: altera_tse_tx_ff_length" {  } { { "mac_ip/altera_tse_tx_ff_length.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_ff_length.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105347 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105347 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_ff_read_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_ff_read_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_ff_read_cntl " "Found entity 1: altera_tse_tx_ff_read_cntl" {  } { { "mac_ip/altera_tse_tx_ff_read_cntl.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_ff_read_cntl.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105375 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105375 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_tx_stat_extract.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_tx_stat_extract.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_tx_stat_extract " "Found entity 1: altera_tse_tx_stat_extract" {  } { { "mac_ip/altera_tse_tx_stat_extract.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_stat_extract.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105414 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105414 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_false_path_marker.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_false_path_marker.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_false_path_marker " "Found entity 1: altera_tse_false_path_marker" {  } { { "mac_ip/altera_tse_false_path_marker.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_false_path_marker.v" 38 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105416 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105416 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_reset_synchronizer " "Found entity 1: altera_tse_reset_synchronizer" {  } { { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 36 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105418 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105418 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_clock_crosser.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_clock_crosser.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_clock_crosser " "Found entity 1: altera_tse_clock_crosser" {  } { { "mac_ip/altera_tse_clock_crosser.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_clock_crosser.v" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105439 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105439 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_a_fifo_13.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_a_fifo_13.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_a_fifo_13 " "Found entity 1: altera_tse_a_fifo_13" {  } { { "mac_ip/altera_tse_a_fifo_13.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105466 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105466 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_a_fifo_24.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_a_fifo_24.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_a_fifo_24 " "Found entity 1: altera_tse_a_fifo_24" {  } { { "mac_ip/altera_tse_a_fifo_24.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_24.v" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105494 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105494 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_a_fifo_34.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_a_fifo_34.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_a_fifo_34 " "Found entity 1: altera_tse_a_fifo_34" {  } { { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105519 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105519 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_a_fifo_opt_1246.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_a_fifo_opt_1246.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_a_fifo_opt_1246 " "Found entity 1: altera_tse_a_fifo_opt_1246" {  } { { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 53 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105555 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105555 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_a_fifo_opt_14_44.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_a_fifo_opt_14_44.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_a_fifo_opt_14_44 " "Found entity 1: altera_tse_a_fifo_opt_14_44" {  } { { "mac_ip/altera_tse_a_fifo_opt_14_44.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_14_44.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105588 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105588 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_a_fifo_opt_36_10.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_a_fifo_opt_36_10.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_a_fifo_opt_36_10 " "Found entity 1: altera_tse_a_fifo_opt_36_10" {  } { { "mac_ip/altera_tse_a_fifo_opt_36_10.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_36_10.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105624 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105624 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_gray_cnt.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_gray_cnt.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_gray_cnt " "Found entity 1: altera_tse_gray_cnt" {  } { { "mac_ip/altera_tse_gray_cnt.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_gray_cnt.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105646 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105646 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_sdpm_altsyncram.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_sdpm_altsyncram.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_sdpm_altsyncram " "Found entity 1: altera_tse_sdpm_altsyncram" {  } { { "mac_ip/altera_tse_sdpm_altsyncram.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_sdpm_altsyncram.v" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105666 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105666 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_altsyncram_dpm_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_altsyncram_dpm_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_altsyncram_dpm_fifo " "Found entity 1: altera_tse_altsyncram_dpm_fifo" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105686 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105686 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_bin_cnt.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_bin_cnt.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_bin_cnt " "Found entity 1: altera_tse_bin_cnt" {  } { { "mac_ip/altera_tse_bin_cnt.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_bin_cnt.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105706 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105706 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_ph_calculator.sv 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_ph_calculator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_ph_calculator " "Found entity 1: altera_tse_ph_calculator" {  } { { "mac_ip/altera_tse_ph_calculator.sv" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_ph_calculator.sv" 15 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105730 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105730 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_sdpm_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_sdpm_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_sdpm_gen " "Found entity 1: altera_tse_sdpm_gen" {  } { { "mac_ip/altera_tse_sdpm_gen.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_sdpm_gen.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105748 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105748 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mac_ip/altera_tse_dc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file mac_ip/altera_tse_dc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_tse_dc_fifo " "Found entity 1: altera_tse_dc_fifo" {  } { { "mac_ip/altera_tse_dc_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_dc_fifo.v" 52 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105775 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105775 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_sys.v 1 1 " "Found 1 design units, including 1 entities, in source file pll_sys.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_sys " "Found entity 1: pll_sys" {  } { { "pll_sys.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/pll_sys.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246105778 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246105778 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "project_top " "Elaborating entity \"project_top\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1589246106030 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mac_reg mac_reg:mac_reg_ins " "Elaborating entity \"mac_reg\" for hierarchy \"mac_reg:mac_reg_ins\"" {  } { { "project_top.v" "mac_reg_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 114 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106034 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mac_reg_config mac_reg_config:mac_reg_config_ins " "Elaborating entity \"mac_reg_config\" for hierarchy \"mac_reg_config:mac_reg_config_ins\"" {  } { { "project_top.v" "mac_reg_config_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 134 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106038 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mac_ip_0002 mac_ip_0002:mac_ip_inst " "Elaborating entity \"mac_ip_0002\" for hierarchy \"mac_ip_0002:mac_ip_inst\"" {  } { { "project_top.v" "mac_ip_inst" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106041 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_eth_tse_mac mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac " "Elaborating entity \"altera_eth_tse_mac\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\"" {  } { { "mac_ip/mac_ip_0002.v" "i_tse_mac" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106049 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_reset_synchronizer mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_0 " "Elaborating entity \"altera_tse_reset_synchronizer\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_0\"" {  } { { "mac_ip/altera_eth_tse_mac.v" "reset_sync_0" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 479 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106061 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mac_control mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL " "Elaborating entity \"altera_tse_mac_control\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\"" {  } { { "mac_ip/altera_eth_tse_mac.v" "U_MAC_CONTROL" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 708 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106076 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_register_map mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG " "Elaborating entity \"altera_tse_register_map\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\"" {  } { { "mac_ip/altera_tse_mac_control.v" "U_REG" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_control.v" 620 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106092 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\|altera_std_synchronizer:U_SYNC_1 " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\|altera_std_synchronizer:U_SYNC_1\"" {  } { { "mac_ip/altera_tse_register_map.v" "U_SYNC_1" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 439 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106116 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\|altera_std_synchronizer:U_SYNC_1 " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\|altera_std_synchronizer:U_SYNC_1\"" {  } { { "mac_ip/altera_tse_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 439 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246106117 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\|altera_std_synchronizer:U_SYNC_1 " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_register_map:U_REG\|altera_std_synchronizer:U_SYNC_1\" with the following parameter:" {  } { { "mac_ip/altera_tse_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 439 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246106117 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_host_control mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_host_control:U_CTRL " "Elaborating entity \"altera_tse_host_control\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_mac_control:U_MAC_CONTROL\|altera_tse_host_control:U_CTRL\"" {  } { { "mac_ip/altera_tse_mac_control.v" "U_CTRL" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_control.v" 661 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106132 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_top_mdio mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO " "Elaborating entity \"altera_tse_top_mdio\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\"" {  } { { "mac_ip/altera_eth_tse_mac.v" "U_MDIO" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 747 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106151 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mdio_clk_gen mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\|altera_tse_mdio_clk_gen:U_CLKGEN " "Elaborating entity \"altera_tse_mdio_clk_gen\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\|altera_tse_mdio_clk_gen:U_CLKGEN\"" {  } { { "mac_ip/altera_tse_top_mdio.v" "U_CLKGEN" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_mdio.v" 105 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106165 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mdio_cntl mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\|altera_tse_mdio_cntl:U_CNTL " "Elaborating entity \"altera_tse_mdio_cntl\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\|altera_tse_mdio_cntl:U_CNTL\"" {  } { { "mac_ip/altera_tse_top_mdio.v" "U_CNTL" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_mdio.v" 130 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106180 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mdio mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\|altera_tse_mdio:U_MDIO " "Elaborating entity \"altera_tse_mdio\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_mdio:U_MDIO\|altera_tse_mdio:U_MDIO\"" {  } { { "mac_ip/altera_tse_top_mdio.v" "U_MDIO" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_mdio.v" 147 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106194 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_top_w_fifo_10_100_1000 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP " "Elaborating entity \"altera_tse_top_w_fifo_10_100_1000\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\"" {  } { { "mac_ip/altera_eth_tse_mac.v" "U_MAC_TOP" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106210 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_clk_cntl mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_clk_cntl:U_CLKCT " "Elaborating entity \"altera_tse_clk_cntl\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_clk_cntl:U_CLKCT\"" {  } { { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "U_CLKCT" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 476 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106227 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mii_rx_if mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_mii_rx_if:U_MRX " "Elaborating entity \"altera_tse_mii_rx_if\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_mii_rx_if:U_MRX\"" {  } { { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "U_MRX" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 491 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106244 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mii_tx_if mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_mii_tx_if:U_MTX " "Elaborating entity \"altera_tse_mii_tx_if\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_mii_tx_if:U_MTX\"" {  } { { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "U_MTX" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 504 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106259 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_gmii_io mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_gmii_io:U_GMIF " "Elaborating entity \"altera_tse_gmii_io\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_gmii_io:U_GMIF\"" {  } { { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "U_GMIF" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 548 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106275 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_top_w_fifo mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC " "Elaborating entity \"altera_tse_top_w_fifo\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\"" {  } { { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "U_MAC" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106292 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_top_1geth mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH " "Elaborating entity \"altera_tse_top_1geth\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\"" {  } { { "mac_ip/altera_tse_top_w_fifo.v" "U_GETH" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 530 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106309 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_rx_stat_extract mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_rx_stat_extract:U_RXSTAT " "Elaborating entity \"altera_tse_rx_stat_extract\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_rx_stat_extract:U_RXSTAT\"" {  } { { "mac_ip/altera_tse_top_1geth.v" "U_RXSTAT" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_1geth.v" 389 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106325 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mac_rx mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX " "Elaborating entity \"altera_tse_mac_rx\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\"" {  } { { "mac_ip/altera_tse_top_1geth.v" "U_RX" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_1geth.v" 457 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106342 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_crc328checker mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_crc328checker:U_CRC " "Elaborating entity \"altera_tse_crc328checker\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_crc328checker:U_CRC\"" {  } { { "mac_ip/altera_tse_mac_rx.v" "U_CRC" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 2676 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106374 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_crc32galois8 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_crc328checker:U_CRC\|altera_tse_crc32galois8:U_GALS " "Elaborating entity \"altera_tse_crc32galois8\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_crc328checker:U_CRC\|altera_tse_crc32galois8:U_GALS\"" {  } { { "mac_ip/altera_tse_crc328checker.v" "U_GALS" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_crc328checker.v" 110 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106388 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_altshifttaps mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS " "Elaborating entity \"altera_tse_altshifttaps\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\"" {  } { { "mac_ip/altera_tse_mac_rx.v" "U_SHIFTTAPS" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 3112 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106404 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_tx_stat_extract mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_tx_stat_extract:U_TXSTAT " "Elaborating entity \"altera_tse_tx_stat_extract\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_tx_stat_extract:U_TXSTAT\"" {  } { { "mac_ip/altera_tse_top_1geth.v" "U_TXSTAT" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_1geth.v" 489 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106419 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_mac_tx mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX " "Elaborating entity \"altera_tse_mac_tx\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\"" {  } { { "mac_ip/altera_tse_top_1geth.v" "U_TX" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_1geth.v" 538 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106435 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer_bundle mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3 " "Elaborating entity \"altera_std_synchronizer_bundle\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\"" {  } { { "mac_ip/altera_tse_mac_tx.v" "U_SYNC_3" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 418 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106458 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3 " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\"" {  } { { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 418 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246106459 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3 " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\" with the following parameter:" {  } { { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 418 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246106459 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\|altera_std_synchronizer:sync\[0\].u " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\|altera_std_synchronizer:sync\[0\].u\"" {  } { { "altera_std_synchronizer_bundle.v" "sync\[0\].u" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altera_std_synchronizer_bundle.v" 41 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106461 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\|altera_std_synchronizer:sync\[0\].u mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3 " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\|altera_std_synchronizer:sync\[0\].u\", which is child of megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_std_synchronizer_bundle:U_SYNC_3\"" {  } { { "altera_std_synchronizer_bundle.v" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altera_std_synchronizer_bundle.v" 41 0 0 } } { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 418 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106462 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_crc328generator mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_tse_crc328generator:U_CRC " "Elaborating entity \"altera_tse_crc328generator\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_tse_crc328generator:U_CRC\"" {  } { { "mac_ip/altera_tse_mac_tx.v" "U_CRC" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 2321 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106477 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_crc32ctl8 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_tse_crc328generator:U_CRC\|altera_tse_crc32ctl8:U_CTL " "Elaborating entity \"altera_tse_crc32ctl8\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_tx:U_TX\|altera_tse_crc328generator:U_CRC\|altera_tse_crc32ctl8:U_CTL\"" {  } { { "mac_ip/altera_tse_crc328generator.v" "U_CTL" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_crc328generator.v" 104 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106493 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_rx_min_ff mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF " "Elaborating entity \"altera_tse_rx_min_ff\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\"" {  } { { "mac_ip/altera_tse_top_w_fifo.v" "U_RXFF" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106509 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer_bundle mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_std_synchronizer_bundle:U_SYNC_2 " "Elaborating entity \"altera_std_synchronizer_bundle\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_std_synchronizer_bundle:U_SYNC_2\"" {  } { { "mac_ip/altera_tse_rx_min_ff.v" "U_SYNC_2" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 204 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106520 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_std_synchronizer_bundle:U_SYNC_2 " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_std_synchronizer_bundle:U_SYNC_2\"" {  } { { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 204 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246106521 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_std_synchronizer_bundle:U_SYNC_2 " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_std_synchronizer_bundle:U_SYNC_2\" with the following parameter:" {  } { { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 204 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246106521 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_a_fifo_opt_1246 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA " "Elaborating entity \"altera_tse_a_fifo_opt_1246\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\"" {  } { { "mac_ip/altera_tse_rx_min_ff.v" "RX_DATA" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106564 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_altsyncram_dpm_fifo mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM " "Elaborating entity \"altera_tse_altsyncram_dpm_fifo\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\"" {  } { { "mac_ip/altera_tse_a_fifo_opt_1246.v" "U_RAM" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106581 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "altsyncram_component" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106644 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 40 " "Parameter \"width_a\" = \"40\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 40 " "Parameter \"width_b\" = \"40\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106648 ""}  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246106648 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_cfg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_cfg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_cfg1 " "Found entity 1: altsyncram_cfg1" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246106713 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246106713 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_cfg1 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated " "Elaborating entity \"altsyncram_cfg1\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106715 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_gray_cnt mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_gray_cnt:U_WRT " "Elaborating entity \"altera_tse_gray_cnt\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_gray_cnt:U_WRT\"" {  } { { "mac_ip/altera_tse_a_fifo_opt_1246.v" "U_WRT" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 184 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106728 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_a_fifo_34 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS " "Elaborating entity \"altera_tse_a_fifo_34\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\"" {  } { { "mac_ip/altera_tse_rx_min_ff.v" "RX_STATUS" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106820 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_altsyncram_dpm_fifo mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM " "Elaborating entity \"altera_tse_altsyncram_dpm_fifo\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\"" {  } { { "mac_ip/altera_tse_a_fifo_34.v" "U_RAM" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106829 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "altsyncram_component" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106837 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 512 " "Parameter \"numwords_a\" = \"512\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 512 " "Parameter \"numwords_b\" = \"512\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 9 " "Parameter \"widthad_a\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 9 " "Parameter \"widthad_b\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 23 " "Parameter \"width_a\" = \"23\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 23 " "Parameter \"width_b\" = \"23\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106842 ""}  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246106842 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g9g1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_g9g1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g9g1 " "Found entity 1: altsyncram_g9g1" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246106904 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246106904 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_g9g1 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated " "Elaborating entity \"altsyncram_g9g1\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106906 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_gray_cnt mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_gray_cnt:U_WRT " "Elaborating entity \"altera_tse_gray_cnt\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_gray_cnt:U_WRT\"" {  } { { "mac_ip/altera_tse_a_fifo_34.v" "U_WRT" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 124 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106911 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_bin_cnt mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_bin_cnt:U_RD " "Elaborating entity \"altera_tse_bin_cnt\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_bin_cnt:U_RD\"" {  } { { "mac_ip/altera_tse_a_fifo_34.v" "U_RD" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 132 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106921 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_tx_min_ff mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF " "Elaborating entity \"altera_tse_tx_min_ff\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\"" {  } { { "mac_ip/altera_tse_top_w_fifo.v" "U_TXFF" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 674 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106937 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_a_fifo_opt_1246 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA " "Elaborating entity \"altera_tse_a_fifo_opt_1246\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\"" {  } { { "mac_ip/altera_tse_tx_min_ff.v" "TX_DATA" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_min_ff.v" 463 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106981 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_altsyncram_dpm_fifo mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM " "Elaborating entity \"altera_tse_altsyncram_dpm_fifo\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\"" {  } { { "mac_ip/altera_tse_a_fifo_opt_1246.v" "U_RAM" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106984 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "altsyncram_component" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106992 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 36 " "Parameter \"width_a\" = \"36\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 36 " "Parameter \"width_b\" = \"36\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246106997 ""}  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246106997 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_mfg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_mfg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_mfg1 " "Found entity 1: altsyncram_mfg1" {  } { { "db/altsyncram_mfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_mfg1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246107059 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246107059 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_mfg1 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_mfg1:auto_generated " "Elaborating entity \"altsyncram_mfg1\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_opt_1246:TX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_mfg1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107061 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_a_fifo_13 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS " "Elaborating entity \"altera_tse_a_fifo_13\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\"" {  } { { "mac_ip/altera_tse_tx_min_ff.v" "TX_STATUS" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_min_ff.v" 486 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107151 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_tse_altsyncram_dpm_fifo mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM " "Elaborating entity \"altera_tse_altsyncram_dpm_fifo\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\"" {  } { { "mac_ip/altera_tse_a_fifo_13.v" "U_RAM" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 119 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107160 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "altsyncram_component" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107168 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\"" {  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 512 " "Parameter \"numwords_a\" = \"512\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 512 " "Parameter \"numwords_b\" = \"512\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 9 " "Parameter \"widthad_a\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 9 " "Parameter \"widthad_b\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 2 " "Parameter \"width_a\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 2 " "Parameter \"width_b\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107174 ""}  } { { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246107174 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_a6g1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_a6g1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_a6g1 " "Found entity 1: altsyncram_a6g1" {  } { { "db/altsyncram_a6g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_a6g1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246107232 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246107232 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_a6g1 mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_a6g1:auto_generated " "Elaborating entity \"altsyncram_a6g1\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_a6g1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107234 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer_bundle mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_std_synchronizer_bundle:U_SYNC_1 " "Elaborating entity \"altera_std_synchronizer_bundle\" for hierarchy \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_std_synchronizer_bundle:U_SYNC_1\"" {  } { { "mac_ip/altera_tse_a_fifo_13.v" "U_SYNC_1" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 146 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107242 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_std_synchronizer_bundle:U_SYNC_1 " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_std_synchronizer_bundle:U_SYNC_1\"" {  } { { "mac_ip/altera_tse_a_fifo_13.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 146 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246107243 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_std_synchronizer_bundle:U_SYNC_1 " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_std_synchronizer_bundle:U_SYNC_1\" with the following parameter:" {  } { { "mac_ip/altera_tse_a_fifo_13.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 146 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246107243 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_transmit data_transmit:data_transmit_ins " "Elaborating entity \"data_transmit\" for hierarchy \"data_transmit:data_transmit_ins\"" {  } { { "project_top.v" "data_transmit_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 223 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107277 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "flag_f012 data_transmit.v(47) " "Verilog HDL or VHDL warning at data_transmit.v(47): object \"flag_f012\" assigned a value but never read" {  } { { "data_transmit.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_transmit.v" 47 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1589246107284 "|project_top|data_transmit:data_transmit_ins"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_receive data_receive:data_receive_ins " "Elaborating entity \"data_receive\" for hierarchy \"data_receive:data_receive_ins\"" {  } { { "project_top.v" "data_receive_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 246 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107286 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 data_receive.v(93) " "Verilog HDL assignment warning at data_receive.v(93): truncated value with size 32 to match size of target (8)" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 93 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1589246107287 "|project_top|data_receive:data_receive_ins"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ip_sour data_receive.v(55) " "Output port \"ip_sour\" at data_receive.v(55) has no driver" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 55 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1589246107287 "|project_top|data_receive:data_receive_ins"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "mac_sour data_receive.v(56) " "Output port \"mac_sour\" at data_receive.v(56) has no driver" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 56 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1589246107287 "|project_top|data_receive:data_receive_ins"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "cmd_arq data_receive.v(52) " "Output port \"cmd_arq\" at data_receive.v(52) has no driver" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 52 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1589246107287 "|project_top|data_receive:data_receive_ins"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "cmd_start data_receive.v(53) " "Output port \"cmd_start\" at data_receive.v(53) has no driver" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 53 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1589246107287 "|project_top|data_receive:data_receive_ins"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "cmd_stop data_receive.v(54) " "Output port \"cmd_stop\" at data_receive.v(54) has no driver" {  } { { "data_receive.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_receive.v" 54 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1589246107287 "|project_top|data_receive:data_receive_ins"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys pll_sys:pll_sys_ins " "Elaborating entity \"pll_sys\" for hierarchy \"pll_sys:pll_sys_ins\"" {  } { { "project_top.v" "pll_sys_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 253 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107290 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll_sys:pll_sys_ins\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"pll_sys:pll_sys_ins\|altpll:altpll_component\"" {  } { { "pll_sys.v" "altpll_component" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/pll_sys.v" 98 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107335 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "pll_sys:pll_sys_ins\|altpll:altpll_component " "Elaborated megafunction instantiation \"pll_sys:pll_sys_ins\|altpll:altpll_component\"" {  } { { "pll_sys.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/pll_sys.v" 98 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "pll_sys:pll_sys_ins\|altpll:altpll_component " "Instantiated megafunction \"pll_sys:pll_sys_ins\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5 " "Parameter \"clk0_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 2 " "Parameter \"clk1_divide_by\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 5 " "Parameter \"clk1_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 4 " "Parameter \"clk2_divide_by\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 5 " "Parameter \"clk2_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 50000 " "Parameter \"inclk0_input_frequency\" = \"50000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll_sys " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll_sys\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107338 ""}  } { { "pll_sys.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/pll_sys.v" 98 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246107338 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_sys_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_sys_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_sys_altpll " "Found entity 1: pll_sys_altpll" {  } { { "db/pll_sys_altpll.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/pll_sys_altpll.v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246107402 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246107402 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys_altpll pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated " "Elaborating entity \"pll_sys_altpll\" for hierarchy \"pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107404 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led led:led_ins " "Elaborating entity \"led\" for hierarchy \"led:led_ins\"" {  } { { "project_top.v" "led_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 263 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107408 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cnt_enable led.v(27) " "Verilog HDL or VHDL warning at led.v(27): object \"cnt_enable\" assigned a value but never read" {  } { { "led.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/led.v" 27 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1589246107409 "|project_top|led:led_ins"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dp83848_rst dp83848_rst:dp83848_rst_ins " "Elaborating entity \"dp83848_rst\" for hierarchy \"dp83848_rst:dp83848_rst_ins\"" {  } { { "project_top.v" "dp83848_rst_ins" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 270 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246107411 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4u14.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4u14.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4u14 " "Found entity 1: altsyncram_4u14" {  } { { "db/altsyncram_4u14.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_4u14.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246108804 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246108804 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_tsc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_tsc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_tsc " "Found entity 1: mux_tsc" {  } { { "db/mux_tsc.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/mux_tsc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246108946 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246108946 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_dvf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_dvf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_dvf " "Found entity 1: decode_dvf" {  } { { "db/decode_dvf.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/decode_dvf.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246109023 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246109023 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_tei.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_tei.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_tei " "Found entity 1: cntr_tei" {  } { { "db/cntr_tei.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cntr_tei.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246109142 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246109142 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_pgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_pgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_pgc " "Found entity 1: cmpr_pgc" {  } { { "db/cmpr_pgc.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cmpr_pgc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246109205 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246109205 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_m9j.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_m9j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_m9j " "Found entity 1: cntr_m9j" {  } { { "db/cntr_m9j.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cntr_m9j.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246109289 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246109289 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ggi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_ggi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ggi " "Found entity 1: cntr_ggi" {  } { { "db/cntr_ggi.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cntr_ggi.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246109385 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246109385 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_rgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_rgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_rgc " "Found entity 1: cmpr_rgc" {  } { { "db/cmpr_rgc.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cmpr_rgc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246109442 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246109442 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_23j.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_23j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_23j " "Found entity 1: cntr_23j" {  } { { "db/cntr_23j.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cntr_23j.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246109523 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246109523 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ngc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ngc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ngc " "Found entity 1: cmpr_ngc" {  } { { "db/cmpr_ngc.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cmpr_ngc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246109580 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246109580 ""}
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" {  } {  } 0 12033 "Analysis and Synthesis generated SignalTap II or debug node instance \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246109647 ""}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_a6g1:auto_generated\|q_b\[0\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_tx_min_ff:U_TXFF\|altera_tse_a_fifo_13:TX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_a6g1:auto_generated\|q_b\[0\]\"" {  } { { "db/altsyncram_a6g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_a6g1.tdf" 38 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_13.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 119 0 0 } } { "mac_ip/altera_tse_tx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_min_ff.v" 486 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 674 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_13:TX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_a6g1:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[4\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[4\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 162 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[5\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[5\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 193 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[6\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[6\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 224 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[7\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[7\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 255 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[8\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[8\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 286 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[9\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[9\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 317 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[10\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[10\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 348 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[11\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[11\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 379 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[12\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[12\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 410 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[13\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[13\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 441 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[14\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[14\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 472 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[15\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[15\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 503 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[16\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[16\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 534 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[17\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[17\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 565 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[18\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[18\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 596 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a18"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[19\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[19\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 627 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a19"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[20\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[20\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 658 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a20"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[22\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_34:RX_STATUS\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_g9g1:auto_generated\|q_b\[22\]\"" {  } { { "db/altsyncram_g9g1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_g9g1.tdf" 720 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 115 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 785 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_34:RX_STATUS|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_g9g1:auto_generated|ram_block1a22"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[0\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[0\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 38 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[1\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[1\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 69 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[2\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[2\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 100 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[3\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[3\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 131 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[4\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[4\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 162 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[5\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[5\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 193 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[6\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[6\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 224 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[7\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[7\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 255 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[8\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[8\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 286 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[9\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[9\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 317 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[10\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[10\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 348 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[11\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[11\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 379 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[12\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[12\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 410 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[13\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[13\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 441 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[14\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[14\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 472 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[15\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[15\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 503 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[16\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[16\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 534 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[17\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[17\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 565 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[18\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[18\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 596 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a18"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[19\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[19\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 627 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a19"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[20\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[20\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 658 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a20"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[21\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[21\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 689 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a21"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[22\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[22\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 720 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a22"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[23\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[23\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 751 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[24\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[24\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 782 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[25\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[25\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 813 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a25"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[26\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[26\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 844 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a26"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[27\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[27\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 875 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a27"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[28\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[28\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 906 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a28"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[29\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[29\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 937 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a29"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[30\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[30\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 968 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a30"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[31\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[31\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 999 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a31"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[33\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[33\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 1061 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a33"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[34\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[34\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 1092 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a34"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[35\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[35\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 1123 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a35"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[36\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[36\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 1154 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a36"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[37\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[37\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 1185 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a37"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[38\] " "Synthesized away node \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_rx_min_ff:U_RXFF\|altera_tse_a_fifo_opt_1246:RX_DATA\|altera_tse_altsyncram_dpm_fifo:U_RAM\|altsyncram:altsyncram_component\|altsyncram_cfg1:auto_generated\|q_b\[38\]\"" {  } { { "db/altsyncram_cfg1.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_cfg1.tdf" 1216 2 0 } } { "altsyncram.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "mac_ip/altera_tse_altsyncram_dpm_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_altsyncram_dpm_fifo.v" 94 0 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 175 0 0 } } { "mac_ip/altera_tse_rx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_rx_min_ff.v" 379 0 0 } } { "mac_ip/altera_tse_top_w_fifo.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo.v" 625 0 0 } } { "mac_ip/altera_tse_top_w_fifo_10_100_1000.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_top_w_fifo_10_100_1000.v" 801 0 0 } } { "mac_ip/altera_eth_tse_mac.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_eth_tse_mac.v" 1090 0 0 } } { "mac_ip/mac_ip_0002.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/mac_ip_0002.v" 178 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 203 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246110188 "|project_top|mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_w_fifo:U_MAC|altera_tse_rx_min_ff:U_RXFF|altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM|altsyncram:altsyncram_component|altsyncram_cfg1:auto_generated|ram_block1a38"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Quartus II" 0 -1 1589246110188 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Quartus II" 0 -1 1589246110188 ""}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IINFER_ALTSHIFT_TAPS_INFERRED" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\|shift_reg_rtl_0 " "Inferred altshift_taps megafunction from the following design logic: \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\|shift_reg_rtl_0\"" { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMBER_OF_TAPS 1 " "Parameter NUMBER_OF_TAPS set to 1" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1589246112064 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "TAP_DISTANCE 16 " "Parameter TAP_DISTANCE set to 16" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1589246112064 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH 8 " "Parameter WIDTH set to 8" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1589246112064 ""}  } {  } 0 276034 "Inferred altshift_taps megafunction from the following design logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246112064 ""}  } {  } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1589246112064 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\|altshift_taps:shift_reg_rtl_0 " "Elaborated megafunction instantiation \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\|altshift_taps:shift_reg_rtl_0\"" {  } {  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246112105 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\|altshift_taps:shift_reg_rtl_0 " "Instantiated megafunction \"mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_top_w_fifo_10_100_1000:U_MAC_TOP\|altera_tse_top_w_fifo:U_MAC\|altera_tse_top_1geth:U_GETH\|altera_tse_mac_rx:U_RX\|altera_tse_altshifttaps:U_SHIFTTAPS\|altshift_taps:shift_reg_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMBER_OF_TAPS 1 " "Parameter \"NUMBER_OF_TAPS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246112105 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "TAP_DISTANCE 16 " "Parameter \"TAP_DISTANCE\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246112105 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH 8 " "Parameter \"WIDTH\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1589246112105 ""}  } {  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1589246112105 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_unm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/shift_taps_unm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_unm " "Found entity 1: shift_taps_unm" {  } { { "db/shift_taps_unm.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/shift_taps_unm.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246112159 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246112159 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ce81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_ce81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ce81 " "Found entity 1: altsyncram_ce81" {  } { { "db/altsyncram_ce81.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/altsyncram_ce81.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246112220 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246112220 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_qqf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_qqf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_qqf " "Found entity 1: cntr_qqf" {  } { { "db/cntr_qqf.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cntr_qqf.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246112279 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246112279 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_qgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_qgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_qgc " "Found entity 1: cmpr_qgc" {  } { { "db/cmpr_qgc.tdf" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/cmpr_qgc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1589246112334 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1589246112334 ""}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1589246113288 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "dp83848_rst.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/dp83848_rst.v" 14 -1 0 } } { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 76 -1 0 } } { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 271 -1 0 } } { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 183 -1 0 } } { "mac_ip/altera_tse_a_fifo_13.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_13.v" 245 -1 0 } } { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 155 -1 0 } } { "mac_ip/altera_tse_tx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_min_ff.v" 125 -1 0 } } { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 193 -1 0 } } { "mac_ip/altera_tse_tx_min_ff.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_tx_min_ff.v" 507 -1 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 366 -1 0 } } { "mac_ip/altera_tse_mac_tx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_tx.v" 795 -1 0 } } { "mac_reg_config.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_reg_config.v" 54 -1 0 } } { "mac_ip/altera_tse_a_fifo_opt_1246.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_opt_1246.v" 412 -1 0 } } { "mac_ip/altera_tse_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 2114 -1 0 } } { "mac_ip/altera_tse_a_fifo_34.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_a_fifo_34.v" 192 -1 0 } } { "mac_ip/altera_tse_mac_rx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 368 -1 0 } } { "mac_ip/altera_tse_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 2151 -1 0 } } { "data_transmit.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/data_transmit.v" 209 -1 0 } } { "mac_ip/altera_tse_mac_rx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 1674 -1 0 } } { "mac_ip/altera_tse_register_map.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_register_map.v" 849 -1 0 } } { "mac_ip/altera_tse_mac_rx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 370 -1 0 } } { "mac_ip/altera_tse_mac_rx.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_mac_rx.v" 307 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1589246113470 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1589246113470 ""}
{ "Warning" "WMLS_MLS_ENABLED_OE" "" "TRI or OPNDRN buffers permanently enabled" { { "Warning" "WMLS_MLS_NODE_NAME" "eth_mdio~synth " "Node \"eth_mdio~synth\"" {  } { { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 36 -1 0 } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246114114 ""}  } {  } 0 13009 "TRI or OPNDRN buffers permanently enabled" 0 0 "Quartus II" 0 -1 1589246114114 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246114395 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "138 " "138 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1589246115436 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "sld_buffer_manager.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 350 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1589246115544 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1589246115544 ""}
{ "Warning" "WFTM_IGNORED_NOT_GATE_PUSH_ASSIGNMENT" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|trigger_out_mode_ff " "The assignment to disallow NOT gate push-back on register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|trigger_out_mode_ff\" is ignored" {  } { { "sld_signaltap_impl.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd" 942 -1 0 } }  } 0 18057 "The assignment to disallow NOT gate push-back on register \"%1!s!\" is ignored" 0 0 "Quartus II" 0 -1 1589246115651 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_signaltap:auto_signaltap_0 " "Timing-Driven Synthesis is running on partition \"sld_signaltap:auto_signaltap_0\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246115783 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "sld_jtag_hub.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 384 -1 0 } } { "sld_jtag_hub.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 521 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1589246116031 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1589246116031 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "sld_hub:auto_hub\|receive\[0\]\[0\] GND " "Pin \"sld_hub:auto_hub\|receive\[0\]\[0\]\" is stuck at GND" {  } { { "sld_hub.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_hub.vhd" 181 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1589246116080 "|project_top|sld_hub:auto_hub|receive[0][0]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1589246116080 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_hub:auto_hub " "Timing-Driven Synthesis is running on partition \"sld_hub:auto_hub\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246116193 ""}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "mac_ip " "Ignored assignments for entity \"mac_ip\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_NAME altera_eth_tse -entity mac_ip -qip mac_ip.qip -library mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_NAME altera_eth_tse -entity mac_ip -qip mac_ip.qip -library mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246116434 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_NAME altera_eth_tse -entity mac_ip -sip mac_ip.sip -library lib_mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_NAME altera_eth_tse -entity mac_ip -sip mac_ip.sip -library lib_mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246116434 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_VERSION 13.0sp1 -entity mac_ip -qip mac_ip.qip -library mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_VERSION 13.0sp1 -entity mac_ip -qip mac_ip.qip -library mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246116434 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_VERSION 13.0sp1 -entity mac_ip -sip mac_ip.sip -library lib_mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_VERSION 13.0sp1 -entity mac_ip -sip mac_ip.sip -library lib_mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246116434 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_ENV mwpim -entity mac_ip -qip mac_ip.qip -library mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_ENV mwpim -entity mac_ip -qip mac_ip.qip -library mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246116434 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_ENV mwpim -entity mac_ip -sip mac_ip.sip -library lib_mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_ENV mwpim -entity mac_ip -sip mac_ip.sip -library lib_mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246116434 ""}  } {  } 0 20013 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Quartus II" 0 -1 1589246116434 ""}
{ "Info" "IAMERGE_SLD_INSTANCE_WITH_FULL_CONNECTIONS" "auto_signaltap_0 13 " "Succesfully connected in-system debug instance \"auto_signaltap_0\" to all 13 required data inputs, trigger inputs, acquisition clocks, and dynamic pins" {  } {  } 0 35024 "Succesfully connected in-system debug instance \"%1!s!\" to all %2!d! required data inputs, trigger inputs, acquisition clocks, and dynamic pins" 0 0 "Quartus II" 0 -1 1589246117812 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1589246117889 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246117889 ""}
{ "Warning" "WCUT_PLL_MULT_DIV_SPECIFIED_CLOCK_NOT_CONNECTED" "pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 CLK\[1\] clk1_multiply_by clk1_divide_by " "PLL \"pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK\[1\] is not connected" {  } { { "db/pll_sys_altpll.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/pll_sys_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "pll_sys.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/pll_sys.v" 98 0 0 } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 253 0 0 } }  } 0 15899 "PLL \"%1!s!\" has parameters %3!s! and %4!s! specified but port %2!s! is not connected" 0 0 "Quartus II" 0 -1 1589246118157 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "crs " "No output dependent on input pin \"crs\"" {  } { { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 28 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246118393 "|project_top|crs"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "col " "No output dependent on input pin \"col\"" {  } { { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 29 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1589246118393 "|project_top|col"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1589246118393 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "3478 " "Implemented 3478 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "15 " "Implemented 15 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1589246118394 ""} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Implemented 9 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1589246118394 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "1 " "Implemented 1 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1589246118394 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3393 " "Implemented 3393 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1589246118394 ""} { "Info" "ICUT_CUT_TM_RAMS" "58 " "Implemented 58 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1589246118394 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1589246118394 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1589246118394 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 84 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 84 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1589246118452 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 12 09:15:18 2020 " "Processing ended: Tue May 12 09:15:18 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1589246118452 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1589246118452 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1589246118452 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1589246118452 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1589246119771 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1589246119774 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 12 09:15:19 2020 " "Processing started: Tue May 12 09:15:19 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1589246119774 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1589246119774 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off project_top -c project_top " "Command: quartus_fit --read_settings_files=off --write_settings_files=off project_top -c project_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1589246119774 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1589246119837 ""}
{ "Info" "0" "" "Project  = project_top" {  } {  } 0 0 "Project  = project_top" 0 0 "Fitter" 0 0 1589246119837 ""}
{ "Info" "0" "" "Revision = project_top" {  } {  } 0 0 "Revision = project_top" 0 0 "Fitter" 0 0 1589246119837 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1589246119941 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "project_top EP4CE10F17I7 " "Selected device EP4CE10F17I7 for design \"project_top\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1589246119980 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1589246120027 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1589246120027 ""}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] 5 1 0 0 " "Implementing clock multiplication of 5, clock division of 1, and phase shift of 0 degrees (0 ps) for pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] port" {  } { { "db/pll_sys_altpll.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/pll_sys_altpll.v" 43 -1 0 } } { "" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 445 9224 9983 0}  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1589246120083 ""}  } { { "db/pll_sys_altpll.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/pll_sys_altpll.v" 43 -1 0 } } { "" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 445 9224 9983 0}  }  } }  } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1589246120083 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1589246120222 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17A7 " "Device EP4CE10F17A7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246120409 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C7 " "Device EP4CE10F17C7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246120409 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17A7 " "Device EP4CE6F17A7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246120409 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C7 " "Device EP4CE6F17C7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246120409 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17I7 " "Device EP4CE6F17I7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246120409 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17A7 " "Device EP4CE15F17A7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246120409 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C7 " "Device EP4CE15F17C7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246120409 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17I7 " "Device EP4CE15F17I7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246120409 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17A7 " "Device EP4CE22F17A7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246120409 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C7 " "Device EP4CE22F17C7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246120409 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17I7 " "Device EP4CE22F17I7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1589246120409 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1589246120409 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" {  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 8535 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1589246120415 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" {  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 8537 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1589246120415 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" {  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 8539 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1589246120415 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" {  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 8541 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1589246120415 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" {  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 8543 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1589246120415 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1589246120415 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1589246120417 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1589246120423 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1589246121438 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1589246121438 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_tse_a_fifo_34 " "Entity altera_tse_a_fifo_34" { { "Info" "ISTA_SDC_STATEMENT_EVAL" " set_false_path -to \[get_registers *altera_tse_a_fifo_34:*\|wr_g_rptr*\] " " set_false_path -to \[get_registers *altera_tse_a_fifo_34:*\|wr_g_rptr*\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1589246121438 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1589246121438 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz    " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz   " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1589246121438 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1589246121438 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1589246121438 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1589246121438 ""}
{ "Info" "ISTA_SDC_FOUND" "mac_ip/altera_eth_tse_mac.sdc " "Reading SDC File: 'mac_ip/altera_eth_tse_mac.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1589246121466 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "mii_tx_clk " "Node: mii_tx_clk was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1589246121495 "|project_top|mii_tx_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_in " "Node: clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1589246121495 "|project_top|clk_in"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "mii_rx_clk " "Node: mii_rx_clk was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1589246121495 "|project_top|mii_rx_clk"}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: pll_sys_ins\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 50.000 " "Node: pll_sys_ins\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 50.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1589246121530 ""}  } {  } 0 332056 "%1!s!" 0 0 "Fitter" 0 -1 1589246121530 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1589246121531 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1589246121531 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1589246121531 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1589246121531 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1589246121532 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1589246121532 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1589246121532 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1589246121532 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2) " "Automatically promoted node pll_sys:pll_sys_ins\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G8 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246121788 ""}  } { { "db/pll_sys_altpll.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/db/pll_sys_altpll.v" 77 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:pll_sys_ins|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 445 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246121788 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246121788 ""}  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 7075 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246121788 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_0\|altera_tse_reset_synchronizer_chain_out  " "Automatically promoted node mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_0\|altera_tse_reset_synchronizer_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246121789 ""}  } { { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 76 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_0|altera_tse_reset_synchronizer_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 2336 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246121789 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_1\|altera_tse_reset_synchronizer_chain_out  " "Automatically promoted node mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_1\|altera_tse_reset_synchronizer_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246121789 ""}  } { { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 76 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_1|altera_tse_reset_synchronizer_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 3588 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246121789 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_2\|altera_tse_reset_synchronizer_chain_out  " "Automatically promoted node mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_2\|altera_tse_reset_synchronizer_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246121789 ""}  } { { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 76 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_2|altera_tse_reset_synchronizer_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 3584 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246121789 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_3\|altera_tse_reset_synchronizer_chain_out  " "Automatically promoted node mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_3\|altera_tse_reset_synchronizer_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246121789 ""}  } { { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 76 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_3|altera_tse_reset_synchronizer_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 3580 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246121789 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_4\|altera_tse_reset_synchronizer_chain_out  " "Automatically promoted node mac_ip_0002:mac_ip_inst\|altera_eth_tse_mac:i_tse_mac\|altera_tse_reset_synchronizer:reset_sync_4\|altera_tse_reset_synchronizer_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246121789 ""}  } { { "mac_ip/altera_tse_reset_synchronizer.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/mac_ip/altera_tse_reset_synchronizer.v" 76 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { mac_ip_0002:mac_ip_inst|altera_eth_tse_mac:i_tse_mac|altera_tse_reset_synchronizer:reset_sync_4|altera_tse_reset_synchronizer_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 3576 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246121789 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|reset_all  " "Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|reset_all " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1589246121790 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~0 " "Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~0" {  } { { "sld_buffer_manager.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 627 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 8219 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1589246121790 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" {  } { { "sld_buffer_manager.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 627 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 7565 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1589246121790 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1589246121790 ""}  } { { "sld_signaltap_impl.vhd" "" { Text "d:/softwareinstall/altera/13.0sp1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd" 842 -1 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 7898 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1589246121790 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1589246122555 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1589246122562 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1589246122563 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1589246122572 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1589246122585 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1589246122592 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1589246122592 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1589246122600 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1589246123224 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "1 EC " "Packed 1 registers into blocks of type EC" {  } {  } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1589246123232 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1589246123232 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1589246123328 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1589246124148 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1589246124912 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1589246124935 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1589246125718 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1589246125718 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1589246126509 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "6 " "Router estimated average interconnect usage is 6% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "14 X11_Y12 X22_Y24 " "Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24" {  } { { "loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 1 { 0 "Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} { { 11 { 0 "Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} 11 12 12 13 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1589246127746 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1589246127746 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1589246128222 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1589246128226 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1589246128226 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1589246128226 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.69 " "Total time spent on timing analysis during the Fitter is 0.69 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1589246128330 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1589246128396 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1589246128809 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1589246128868 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1589246129472 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1589246130416 ""}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "1 " "Following 1 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "eth_mdio a permanently enabled " "Pin eth_mdio has a permanently enabled output enable" {  } { { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/softwareinstall/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { eth_mdio } } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/softwareinstall/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "eth_mdio" } } } } { "project_top.v" "" { Text "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/project_top.v" 36 0 0 } } { "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/softwareinstall/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { eth_mdio } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/" { { 0 { 0 ""} 0 282 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1589246130998 ""}  } {  } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1589246130998 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/output_files/project_top.fit.smsg " "Generated suppressed messages file F:/FPGA Code/iPotest-04A140-ADS1274(S)-ACDCICP-Channel04 - 1.0/output_files/project_top.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1589246131376 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 10 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1097 " "Peak virtual memory: 1097 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1589246132481 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 12 09:15:32 2020 " "Processing ended: Tue May 12 09:15:32 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1589246132481 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1589246132481 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1589246132481 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1589246132481 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1589246133602 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1589246133603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 12 09:15:33 2020 " "Processing started: Tue May 12 09:15:33 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1589246133603 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1589246133603 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off project_top -c project_top " "Command: quartus_asm --read_settings_files=off --write_settings_files=off project_top -c project_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1589246133603 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1589246134618 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1589246134636 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "413 " "Peak virtual memory: 413 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1589246134888 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 12 09:15:34 2020 " "Processing ended: Tue May 12 09:15:34 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1589246134888 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1589246134888 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1589246134888 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1589246134888 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1589246135525 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1589246136083 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1589246136084 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 12 09:15:35 2020 " "Processing started: Tue May 12 09:15:35 2020" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1589246136084 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1589246136084 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta project_top -c project_top " "Command: quartus_sta project_top -c project_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1589246136084 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1589246136142 ""}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "mac_ip " "Ignored assignments for entity \"mac_ip\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_NAME altera_eth_tse -entity mac_ip -qip mac_ip.qip -library mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_NAME altera_eth_tse -entity mac_ip -qip mac_ip.qip -library mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246136363 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_NAME altera_eth_tse -entity mac_ip -sip mac_ip.sip -library lib_mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_NAME altera_eth_tse -entity mac_ip -sip mac_ip.sip -library lib_mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246136363 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_VERSION 13.0sp1 -entity mac_ip -qip mac_ip.qip -library mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_VERSION 13.0sp1 -entity mac_ip -qip mac_ip.qip -library mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246136363 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_VERSION 13.0sp1 -entity mac_ip -sip mac_ip.sip -library lib_mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_VERSION 13.0sp1 -entity mac_ip -sip mac_ip.sip -library lib_mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246136363 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_ENV mwpim -entity mac_ip -qip mac_ip.qip -library mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_ENV mwpim -entity mac_ip -qip mac_ip.qip -library mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246136363 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name IP_TOOL_ENV mwpim -entity mac_ip -sip mac_ip.sip -library lib_mac_ip " "Assignment for entity set_global_assignment -name IP_TOOL_ENV mwpim -entity mac_ip -sip mac_ip.sip -library lib_mac_ip was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1589246136363 ""}  } {  } 0 20013 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Quartus II" 0 -1 1589246136363 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1589246136439 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1589246136490 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1589246136491 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1589246136954 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1589246136954 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_tse_a_fifo_34 " "Entity altera_tse_a_fifo_34" { { "Info" "ISTA_SDC_STATEMENT_EVAL" " set_false_path -to \[get_registers *altera_tse_a_fifo_34:*\|wr_g_rptr*\] " " set_false_path -to \[get_registers *altera_tse_a_fifo_34:*\|wr_g_rptr*\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1589246136954 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1589246136954 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz    " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz   " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1589246136954 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1589246136954 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1589246136954 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Quartus II" 0 -1 1589246136954 ""}
{ "Info" "ISTA_SDC_FOUND" "mac_ip/altera_eth_tse_mac.sdc " "Reading SDC File: 'mac_ip/altera_eth_tse_mac.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1589246136982 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "mii_tx_clk " "Node: mii_tx_clk was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1589246137015 "|project_top|mii_tx_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_in " "Node: clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1589246137015 "|project_top|clk_in"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "mii_rx_clk " "Node: mii_rx_clk was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1589246137015 "|project_top|mii_rx_clk"}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: pll_sys_ins\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 50.000 " "Node: pll_sys_ins\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 50.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137130 ""}  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137130 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1589246137131 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1589246137131 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1589246137131 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1589246137132 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 100C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 100C Model" 0 0 "Quartus II" 0 0 1589246137145 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 42.553 " "Worst-case setup slack is 42.553" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137165 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137165 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   42.553         0.000 altera_reserved_tck  " "   42.553         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137165 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246137165 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.417 " "Worst-case hold slack is 0.417" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137172 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137172 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.417         0.000 altera_reserved_tck  " "    0.417         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137172 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246137172 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 48.198 " "Worst-case recovery slack is 48.198" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137177 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137177 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   48.198         0.000 altera_reserved_tck  " "   48.198         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137177 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246137177 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.418 " "Worst-case removal slack is 1.418" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137182 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137182 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.418         0.000 altera_reserved_tck  " "    1.418         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137182 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246137182 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.554 " "Worst-case minimum pulse width slack is 49.554" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137185 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137185 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.554         0.000 altera_reserved_tck  " "   49.554         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246137185 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246137185 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV -40C Model" {  } {  } 0 0 "Analyzing Slow 1200mV -40C Model" 0 0 "Quartus II" 0 0 1589246137284 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1589246137315 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1589246137914 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "mii_tx_clk " "Node: mii_tx_clk was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1589246138150 "|project_top|mii_tx_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_in " "Node: clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1589246138150 "|project_top|clk_in"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "mii_rx_clk " "Node: mii_rx_clk was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1589246138150 "|project_top|mii_rx_clk"}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: pll_sys_ins\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 50.000 " "Node: pll_sys_ins\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 50.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138160 ""}  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138160 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1589246138160 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1589246138160 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1589246138160 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 43.497 " "Worst-case setup slack is 43.497" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138175 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138175 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   43.497         0.000 altera_reserved_tck  " "   43.497         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138175 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246138175 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.343 " "Worst-case hold slack is 0.343" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.343         0.000 altera_reserved_tck  " "    0.343         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138180 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246138180 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 48.567 " "Worst-case recovery slack is 48.567" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138186 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138186 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   48.567         0.000 altera_reserved_tck  " "   48.567         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138186 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246138186 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.262 " "Worst-case removal slack is 1.262" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.262         0.000 altera_reserved_tck  " "    1.262         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138192 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246138192 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.426 " "Worst-case minimum pulse width slack is 49.426" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138195 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138195 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.426         0.000 altera_reserved_tck  " "   49.426         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138195 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246138195 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV -40C Model" {  } {  } 0 0 "Analyzing Fast 1200mV -40C Model" 0 0 "Quartus II" 0 0 1589246138279 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "mii_tx_clk " "Node: mii_tx_clk was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1589246138554 "|project_top|mii_tx_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_in " "Node: clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1589246138554 "|project_top|clk_in"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "mii_rx_clk " "Node: mii_rx_clk was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1589246138554 "|project_top|mii_rx_clk"}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: pll_sys_ins\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 50.000 " "Node: pll_sys_ins\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 50.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138563 ""}  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138563 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1589246138564 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1589246138564 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1589246138564 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 46.756 " "Worst-case setup slack is 46.756" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138573 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138573 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   46.756         0.000 altera_reserved_tck  " "   46.756         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138573 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246138573 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138580 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138580 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.179         0.000 altera_reserved_tck  " "    0.179         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138580 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246138580 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 49.352 " "Worst-case recovery slack is 49.352" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138587 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138587 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.352         0.000 altera_reserved_tck  " "   49.352         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138587 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246138587 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.639 " "Worst-case removal slack is 0.639" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138594 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138594 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.639         0.000 altera_reserved_tck  " "    0.639         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138594 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246138594 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.451 " "Worst-case minimum pulse width slack is 49.451" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.451         0.000 altera_reserved_tck  " "   49.451         0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1589246138599 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1589246138599 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1589246139006 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1589246139006 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 31 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 31 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "514 " "Peak virtual memory: 514 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1589246139138 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 12 09:15:39 2020 " "Processing ended: Tue May 12 09:15:39 2020" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1589246139138 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1589246139138 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1589246139138 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1589246139138 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 125 s " "Quartus II Full Compilation was successful. 0 errors, 125 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1589246139838 ""}
