##Created by Li, Mingqiang for clock separation. package require -exact qsys 15.1 set_module_property NAME lsu_ic_top set_module_property DESCRIPTION "lsu_ic_top for separated clock control" set_module_property AUTHOR "Li, Mingqiang" set_module_property INTERNAL false set_module_property DISPLAY_NAME lsu_ic_top set_module_property EDITABLE true ##Parameters first: some of parameters will be dynamically written by the tool whereas some will be fixed. #address: need dynamic writing. add_parameter AWIDTH INTEGER 32 "" set_parameter_value AWIDTH 31 set_parameter_property AWIDTH DISPLAY_NAME AWIDTH set_parameter_property AWIDTH TYPE INTEGER set_parameter_property AWIDTH DESCRIPTION "memory address wdith" set_parameter_property AWIDTH HDL_PARAMETER true set_parameter_property AWIDTH AFFECTS_GENERATION true ##Shift: need dynamic writing values add_parameter SHIFT INTEGER 10 "" set_parameter_value SHIFT 30 # set_parameter_property SHIFT DEFAULT_VALUE 10 set_parameter_property SHIFT DISPLAY_NAME SHIFT set_parameter_property SHIFT TYPE INTEGER set_parameter_property SHIFT DESCRIPTION "for address permutation" set_parameter_property SHIFT HDL_PARAMETER true set_parameter_property SHIFT AFFECTS_GENERATION true #Constant enable permute: add_parameter ENABLE_PERMUTE INTEGER 1 "" set_parameter_value ENABLE_PERMUTE 1 # set_parameter_property ENABLE_PERMUTE DEFAULT_VALUE 1 set_parameter_property ENABLE_PERMUTE DISPLAY_NAME ENABLE_PERMUTE set_parameter_property ENABLE_PERMUTE TYPE INTEGER set_parameter_property ENABLE_PERMUTE DESCRIPTION "enable address permutation" set_parameter_property ENABLE_PERMUTE ALLOWED_RANGES 0:1 set_parameter_property ENABLE_PERMUTE HDL_PARAMETER true set_parameter_property ENABLE_PERMUTE AFFECTS_GENERATION true #dynamic change needed add_parameter MWIDTH_BYTES INTEGER 64 set_parameter_value MWIDTH_BYTES 32 # set_parameter_property MWIDTH_BYTES DEFAULT_VALUE 64 set_parameter_property MWIDTH_BYTES DISPLAY_NAME MWIDTH_BYTES set_parameter_property MWIDTH_BYTES TYPE INTEGER set_parameter_property MWIDTH_BYTES DESCRIPTION "memory bus width" set_parameter_property MWIDTH_BYTES HDL_PARAMETER true set_parameter_property MWIDTH_BYTES AFFECTS_GENERATION true #may require dynamic change add_parameter BURST_CNT_W INTEGER 5 set_parameter_value BURST_CNT_W 5 # set_parameter_property BURST_CNT_W DEFAULT_VALUE 5 set_parameter_property BURST_CNT_W DISPLAY_NAME BURST_CNT_W set_parameter_property BURST_CNT_W TYPE INTEGER set_parameter_property BURST_CNT_W DESCRIPTION "max burst number width" set_parameter_property BURST_CNT_W HDL_PARAMETER true set_parameter_property BURST_CNT_W AFFECTS_GENERATION true #require dynamic change add_parameter NUM_RD_PORT INTEGER 2 set_parameter_value NUM_RD_PORT 4 # set_parameter_property NUM_RD_PORT DEFAULT_VALUE 2 set_parameter_property NUM_RD_PORT DISPLAY_NAME NUM_RD_PORT set_parameter_property NUM_RD_PORT TYPE INTEGER set_parameter_property NUM_RD_PORT DESCRIPTION "number of read ports" set_parameter_property NUM_RD_PORT HDL_PARAMETER true set_parameter_property NUM_RD_PORT AFFECTS_GENERATION true #require dynamic change add_parameter NUM_WR_PORT INTEGER 2 set_parameter_value NUM_WR_PORT 2 # set_parameter_property NUM_WR_PORT DEFAULT_VALUE 2 set_parameter_property NUM_WR_PORT DISPLAY_NAME NUM_WR_PORT set_parameter_property NUM_WR_PORT TYPE INTEGER set_parameter_property NUM_WR_PORT DESCRIPTION "number of write ports" set_parameter_property NUM_WR_PORT HDL_PARAMETER true set_parameter_property NUM_WR_PORT AFFECTS_GENERATION true #require dynamic change add_parameter NUM_DIMM INTEGER 1 set_parameter_value NUM_DIMM 2 # set_parameter_property NUM_DIMM DEFAULT_VALUE 1 set_parameter_property NUM_WR_PORT DISPLAY_NAME NUM_DIMM set_parameter_property NUM_WR_PORT TYPE INTEGER set_parameter_property NUM_WR_PORT DESCRIPTION "number of physical banks" set_parameter_property NUM_WR_PORT HDL_PARAMETER true set_parameter_property NUM_WR_PORT AFFECTS_GENERATION true #constant or may change: add_parameter RETURN_DATA_FIFO_DEPTH INTEGER 512 set_parameter_value RETURN_DATA_FIFO_DEPTH 512 # set_parameter_property RETURN_DATA_FIFO_DEPTH DEFAULT_VALUE 512 set_parameter_property RETURN_DATA_FIFO_DEPTH DISPLAY_NAME RETURN_DATA_FIFO_DEPTH set_parameter_property RETURN_DATA_FIFO_DEPTH TYPE INTEGER set_parameter_property RETURN_DATA_FIFO_DEPTH DESCRIPTION "data reordering FIFO depth per bank" set_parameter_property RETURN_DATA_FIFO_DEPTH HDL_PARAMETER true set_parameter_property RETURN_DATA_FIFO_DEPTH AFFECTS_GENERATION true #may need to change add_parameter ENABLE_REORDER INTEGER 0 set_parameter_value ENABLE_REORDER 0 # set_parameter_property ENABLE_REORDER DEFAULT_VALUE 0 set_parameter_property ENABLE_REORDER DISPLAY_NAME ENABLE_REORDER set_parameter_property ENABLE_REORDER TYPE INTEGER set_parameter_property ENABLE_REORDER DESCRIPTION "set it to 0 in SW_DIMM_PARTITION mode" set_parameter_property ENABLE_PERMUTE ALLOWED_RANGES 0:1 set_parameter_property ENABLE_REORDER HDL_PARAMETER true set_parameter_property ENABLE_REORDER AFFECTS_GENERATION true # add_parameter DISABLE_ROOT_FIFO INTEGER 0 set_parameter_value DISABLE_ROOT_FIFO 0 # set_parameter_property DISABLE_ROOT_FIFO DEFAULT_VALUE 0 set_parameter_property DISABLE_ROOT_FIFO DISPLAY_NAME DISABLE_ROOT_FIFO set_parameter_property DISABLE_ROOT_FIFO TYPE INTEGER set_parameter_property DISABLE_ROOT_FIFO DESCRIPTION "disable root fifo if token ring's root FIFO is merged in iface" set_parameter_property DISABLE_ROOT_FIFO ALLOWED_RANGES 0:1 set_parameter_property DISABLE_ROOT_FIFO HDL_PARAMETER true set_parameter_property DISABLE_ROOT_FIFO AFFECTS_GENERATION true #may need change: add_parameter ENABLE_DUAL_RING INTEGER 1 set_parameter_value ENABLE_DUAL_RING 1 # set_parameter_property ENABLE_DUAL_RING DEFAULT_VALUE 1 set_parameter_property ENABLE_DUAL_RING DISPLAY_NAME ENABLE_DUAL_RING set_parameter_property ENABLE_DUAL_RING TYPE INTEGER set_parameter_property ENABLE_DUAL_RING ALLOWED_RANGES 0:1 set_parameter_property ENABLE_DUAL_RING HDL_PARAMETER true set_parameter_property ENABLE_DUAL_RING AFFECTS_GENERATION true #May need change: add_parameter ENABLE_MULTIPLE_WR_RING INTEGER 0 set_parameter_value ENABLE_MULTIPLE_WR_RING 0 # set_parameter_property ENABLE_MULTIPLE_WR_RING DEFAULT_VALUE 0 set_parameter_property ENABLE_MULTIPLE_WR_RING DISPLAY_NAME ENABLE_MULTIPLE_WR_RING set_parameter_property ENABLE_MULTIPLE_WR_RING TYPE INTEGER set_parameter_property ENABLE_MULTIPLE_WR_RING DESCRIPTION "enable N write rings; N == number of banks" set_parameter_property ENABLE_MULTIPLE_WR_RING ALLOWED_RANGES 0:1 set_parameter_property ENABLE_MULTIPLE_WR_RING HDL_PARAMETER true set_parameter_property ENABLE_MULTIPLE_WR_RING AFFECTS_GENERATION true # add_parameter ROOT_FIFO_DEPTH INTEGER 512 set_parameter_value ROOT_FIFO_DEPTH 512 # set_parameter_property ROOT_FIFO_DEPTH DEFAULT_VALUE 512 set_parameter_property ROOT_FIFO_DEPTH DISPLAY_NAME ROOT_FIFO_DEPTH set_parameter_property ROOT_FIFO_DEPTH TYPE INTEGER set_parameter_property DISABLE_ROOT_FIFO DESCRIPTION "Token root FIFO depth" set_parameter_property DISABLE_ROOT_FIFO HDL_PARAMETER true set_parameter_property DISABLE_ROOT_FIFO AFFECTS_GENERATION true #May need change: add_parameter NUM_REORDER INTEGER 1 set_parameter_value NUM_REORDER 1 # set_parameter_property NUM_REORDER DEFAULT_VALUE 1 set_parameter_property NUM_REORDER DISPLAY_NAME NUM_REORDER set_parameter_property NUM_REORDER TYPE INTEGER set_parameter_property NUM_REORDER DESCRIPTION "Number of reordering blocks for burst interleaved mode" set_parameter_property NUM_REORDER HDL_PARAMETER true set_parameter_property NUM_REORDER AFFECTS_GENERATION true add_parameter ENABLE_LAST_WAIT INTEGER 0 set_parameter_value ENABLE_LAST_WAIT 0 # set_parameter_property ENABLE_LAST_WAIT DEFAULT_VALUE 0 set_parameter_property ENABLE_LAST_WAIT DISPLAY_NAME ENABLE_LAST_WAIT set_parameter_property ENABLE_LAST_WAIT TYPE INTEGER set_parameter_property ENABLE_LAST_WAIT DESCRIPTION "A temperary fix for global const_cache, which needs avm_waitrequest == 0 to send load request in some cases" set_parameter_property ENABLE_LAST_WAIT ALLOWED_RANGES 0:1 set_parameter_property ENABLE_LAST_WAIT HDL_PARAMETER true set_parameter_property ENABLE_LAST_WAIT AFFECTS_GENERATION true ##Port Declaration: add_interface lsu_clock clock end set_interface_property lsu_clock ENABLED true add_interface_port lsu_clock clock clk Input 1 add_interface_port lsu_clock resetn reset_n Input 1 #local parameters for ports widths: set MWIDTH [ expr { [get_parameter_value MWIDTH_BYTES]*8 } ] # set P_NUM_RD_PORT [ expr { ( NUM_RD_PORT > 0 ) ? NUM_RD_PORT : 1 } ] # set P_NUM_WR_PORT [ expr { ( NUM_WR_PORT > 0 ) ? NUM_WR_PORT : 1 } ] set NUM_DIMM_W [ expr { ceil( log( [get_parameter_value NUM_DIMM])/log(2.0) ) } ] set PENDING_CNT_W [ expr { ceil( log( [get_parameter_value RETURN_DATA_FIFO_DEPTH])/log(2.0) ) } ] ##for i=0 < number of write ports. # input [MWIDTH_BYTES-1:0] i_rd_byteenable [P_NUM_RD_PORT]; # input [AWIDTH-1:0] i_rd_address [P_NUM_RD_PORT]; # input i_rd_request [P_NUM_RD_PORT]; # input [BURST_CNT_W-1:0] i_rd_burstcount [P_NUM_RD_PORT]; # input [MWIDTH_BYTES-1:0] i_wr_byteenable [P_NUM_WR_PORT]; # input [AWIDTH-1:0] i_wr_address [P_NUM_WR_PORT]; # input i_wr_request [P_NUM_WR_PORT]; # input [BURST_CNT_W-1:0] i_wr_burstcount [P_NUM_WR_PORT]; # input [MWIDTH-1:0] i_wr_writedata [P_NUM_WR_PORT]; # // from MEM # input i_avm_waitrequest [NUM_DIMM]; # input [MWIDTH-1:0] i_avm_readdata [NUM_DIMM]; # input i_avm_readdatavalid [NUM_DIMM]; # // to MEM # output [MWIDTH_BYTES-1:0] o_avm_byteenable [NUM_DIMM]; # output [AWIDTH-NUM_DIMM_W-1:0] o_avm_address [NUM_DIMM]; # output o_avm_read [NUM_DIMM]; # output o_avm_write [NUM_DIMM]; # output [BURST_CNT_W-1:0] o_avm_burstcount [NUM_DIMM]; # output [MWIDTH-1:0] o_avm_writedata [NUM_DIMM]; # // to LSU # output o_rd_waitrequest [P_NUM_RD_PORT]; # output o_wr_waitrequest [P_NUM_WR_PORT]; # output [MWIDTH-1:0] o_avm_readdata [P_NUM_RD_PORT]; # output o_avm_readdatavalid [P_NUM_RD_PORT]; # output logic o_avm_writeack [P_NUM_WR_PORT]; for {set i 0} {$i < [get_parameter_value NUM_WR_PORT]} {incr i} { ##Starting from the master to memory: add_interface avm_MEM_rw_$i avalon start set_interface_property avm_MEM_rw_$i ENABLED true set_interface_property avm_MEM_rw_$i associatedClock lsu_clock set_interface_property avm_MEM_rw_$i burstOnBurstBoundariesOnly false set_interface_property avm_MEM_rw_$i doStreamReads false set_interface_property avm_MEM_rw_$i doStreamWrites false set_interface_property avm_MEM_rw_$i linewrapBursts false set_interface_property avm_MEM_rw_$i readWaitTime 0 add_interface_port avm_MEM_rw_$i o_avm_address[$i] address output AWIDTH-$NUM_DIMM_W add_interface_port avm_MEM_rw_$i o_avm_read[$i] read output 1 add_interface_port avm_MEM_rw_$i o_avm_write[$i] write output 1 add_interface_port avm_MEM_rw_$i o_avm_writedata[$i] writedata output $MWIDTH add_interface_port avm_MEM_rw_$i o_avm_byteenable[$i] byteenable output MWIDTH_BYTES add_interface_port avm_MEM_rw_$i i_avm_readdata[$i] readdata input $MWIDTH add_interface_port avm_MEM_rw_$i o_avm_burstcount[$i] burstcount output BURST_CNT_W add_interface_port avm_MEM_rw_$i i_avm_waitrequest[$i] waitrequest input 1 add_interface_port avm_MEM_rw_$i i_avm_readdatavalid[$i] readdatavalid input 1 set j [expr {2*$i}] set k [expr {$j+1}] ##Next start slaves from the kernel: we separate read and write interfaces; ##this is read interface: add_interface avs_LSU_rd_$j avalon end set_interface_property avs_LSU_rd_$j true set_interface_property associatedClock lsu_clock set_interface_property avs_LSU_rd_$j timingUnits Cycles ##This interface is not of fixed pipeline length and so readLatency should be 0. add_interface_property avs_LSU_rd_$j readLatency 0 #we use waitrequest and so this should be set to 0: add_interface_property avs_LSU_rd_$j readWaitTime 0 ##It does not necessarily need to be exact multiple of words from the latter derivation and so set false: add_interface_property avs_LSU_rd_$j burstOnBurstBoundariesOnly false #PENDING_CNT_W = $clog2(RETURN_DATA_FIFO_DEPTH); here set to this number: #reg [PENDING_CNT_W-1:0] max_pending [NUM_DIMM]; add_interface_property avs_LSU_rd_$j maximumPendingReadTransactions $PENDING_CNT_W add_interface_property avs_LSU_rd_$j setupTime 0 add_interface_port avs_LSU_rd_$j i_rd_byteenable[$j] byteenable output MWIDTH_BYTES add_interface_port avs_LSU_rd_$j i_rd_address[$j] adress input AWIDTH ##This acts as read because in the lsu_ic_token module: essentially assert read. #assign o_avm_read[0] = (NUM_RD_PORT == 1)? i_rd_request[0] & !i_rd_address[0][AWIDTH-1] : 1'b0; add_interface_port avs_LSU_rd_$j i_rd_request[$j] read input 1 add_interface_port avs_LSU_rd_$j i_rd_burstcount[$j] burstcount input BURST_CNT_W add_interface_port avm_LSU_rd_$j o_rd_waitrequest[$j] waitrequest output 1 add_interface_port avm_LSU_rd_$j o_avm_readdata[$j] readdata output $MWIDTH add_interface_port avm_LSU_rd_$j o_avm_readdatavalid[$j] readdatavalid output 1 add_interface avs_LSU_rd_$k avalon end add_interface avs_LSU_rd_$k avalon end set_interface_property avs_LSU_rd_$k true set_interface_property associatedClock lsu_clock set_interface_property avs_LSU_rd_$k timingUnits Cycles add_interface_property avs_LSU_rd_$k readLatency 0 add_interface_property avs_LSU_rd_$k readWaitTime 0 add_interface_property avs_LSU_rd_$k burstOnBurstBoundariesOnly false add_interface_property avs_LSU_rd_$k maximumPendingReadTransactions $PENDING_CNT_W add_interface_property avs_LSU_rd_$k setupTime 0 add_interface_port avs_LSU_rd_$k i_rd_byteenable[$k] byteenable output MWIDTH_BYTES add_interface_port avs_LSU_rd_$k i_rd_address[$k] adress input AWIDTH add_interface_port avs_LSU_rd_$k i_rd_request[$k] read input 1 add_interface_port avs_LSU_rd_$k i_rd_burstcount[$k] burstcount input BURST_CNT_W add_interface_port avm_LSU_rd_$k o_rd_waitrequest[$k] waitrequest output 1 add_interface_port avm_LSU_rd_$k o_avm_readdata[$k] readdata output $MWIDTH add_interface_port avm_LSU_rd_$k o_avm_readdatavalid[$k] readdatavalid output 1 ##write interface: add_interface avs_LSU_wr_$i avalon end set_interface_property avs_LSU_wr_$i true set_interface_property associatedClock lsu_clock set_interface_property avs_LSU_wr_$i timingUnits Cycles set_interface_property avs_LSU_wr_$i writeWaitTime 0 set_interface_property avs_LSU_wr_$i readLatency 0 set_interface_property avs_LSU_wr_$i burstOnBurstBoundariesOnly false set_interface_property avs_LSU_wr_$i maximumPendingWriteTransactions $PENDING_CNT_W add_interface_port avs_LSU_wr_$i i_wr_byteenable[$i] byteenable output MWIDTH_BYTES add_interface_port avs_LSU_wr_$i i_wr_address[$i] adress input AWIDTH ##i_wr_reqeust is write judging from #o_avm_write[0] = (NUM_RD_PORT == 1)? 1'b0 : i_wr_request[0] & !i_wr_address[0][AWIDTH-1]; add_interface_port avs_LSU_wr_$i i_wr_request[$i] write input 1 add_interface_port avs_LSU_wr_$i i_wr_burstcount[$i] burstcount input BURST_CNT_W add_interface_port avs_LSU_wr_$i i_wr_writedata[$i] writedata input $MWIDTH add_interface_port avs_LSU_wr_$i o_wr_waitrequest[$i] waitrequest output 1 #for(i=0; i