module ed_sim_mem (
		input  wire [0:0]  mem_ck,    // mem.mem_ck,    CK clock
		input  wire [0:0]  mem_ck_n,  //    .mem_ck_n,  CK clock (negative leg)
		input  wire [9:0]  mem_a,     //    .mem_a,     Address
		input  wire [0:0]  mem_cke,   //    .mem_cke,   Clock enable
		input  wire [0:0]  mem_cs_n,  //    .mem_cs_n,  Chip select
		input  wire [0:0]  mem_odt,   //    .mem_odt,   On-die termination
		inout  wire [3:0]  mem_dqs,   //    .mem_dqs,   Data strobe
		inout  wire [3:0]  mem_dqs_n, //    .mem_dqs_n, Data strobe (negative leg)
		inout  wire [31:0] mem_dq,    //    .mem_dq,    Read/write data
		input  wire [3:0]  mem_dm     //    .mem_dm,    Write data mask
	);
endmodule

