module ed_synth (
		input  wire        emif_0_pll_ref_clk_clk,          // emif_0_pll_ref_clk.clk
		input  wire        emif_0_oct_oct_rzqin,            //         emif_0_oct.oct_rzqin
		output wire [0:0]  emif_0_mem_mem_ck,               //         emif_0_mem.mem_ck
		output wire [0:0]  emif_0_mem_mem_ck_n,             //                   .mem_ck_n
		output wire [9:0]  emif_0_mem_mem_a,                //                   .mem_a
		output wire [0:0]  emif_0_mem_mem_cke,              //                   .mem_cke
		output wire [0:0]  emif_0_mem_mem_cs_n,             //                   .mem_cs_n
		output wire [0:0]  emif_0_mem_mem_odt,              //                   .mem_odt
		inout  wire [3:0]  emif_0_mem_mem_dqs,              //                   .mem_dqs
		inout  wire [3:0]  emif_0_mem_mem_dqs_n,            //                   .mem_dqs_n
		inout  wire [31:0] emif_0_mem_mem_dq,               //                   .mem_dq
		output wire [3:0]  emif_0_mem_mem_dm,               //                   .mem_dm
		output wire        emif_0_status_local_cal_success, //      emif_0_status.local_cal_success
		output wire        emif_0_status_local_cal_fail,    //                   .local_cal_fail
		input  wire        global_reset_reset_n,            //       global_reset.reset_n
		output wire        emif_0_tg_0_traffic_gen_pass,    //        emif_0_tg_0.traffic_gen_pass
		output wire        emif_0_tg_0_traffic_gen_fail,    //                   .traffic_gen_fail
		output wire        emif_0_tg_0_traffic_gen_timeout  //                   .traffic_gen_timeout
	);
endmodule

