// ed_sim_mem.v

// Generated using ACDS version 21.3 170

`timescale 1 ps / 1 ps
module ed_sim_mem (
		input  wire [0:0]  mem_ck,    // mem.mem_ck,    CK clock
		input  wire [0:0]  mem_ck_n,  //    .mem_ck_n,  CK clock (negative leg)
		input  wire [9:0]  mem_a,     //    .mem_a,     Address
		input  wire [0:0]  mem_cke,   //    .mem_cke,   Clock enable
		input  wire [0:0]  mem_cs_n,  //    .mem_cs_n,  Chip select
		input  wire [0:0]  mem_odt,   //    .mem_odt,   On-die termination
		inout  wire [3:0]  mem_dqs,   //    .mem_dqs,   Data strobe
		inout  wire [3:0]  mem_dqs_n, //    .mem_dqs_n, Data strobe (negative leg)
		inout  wire [31:0] mem_dq,    //    .mem_dq,    Read/write data
		input  wire [3:0]  mem_dm     //    .mem_dm,    Write data mask
	);

	ed_sim_mem_altera_emif_mem_model_191_hqhlvji mem (
		.mem_ck    (mem_ck),    //   input,   width = 1, mem.mem_ck
		.mem_ck_n  (mem_ck_n),  //   input,   width = 1,    .mem_ck_n
		.mem_a     (mem_a),     //   input,  width = 10,    .mem_a
		.mem_cke   (mem_cke),   //   input,   width = 1,    .mem_cke
		.mem_cs_n  (mem_cs_n),  //   input,   width = 1,    .mem_cs_n
		.mem_odt   (mem_odt),   //   input,   width = 1,    .mem_odt
		.mem_dqs   (mem_dqs),   //   inout,   width = 4,    .mem_dqs
		.mem_dqs_n (mem_dqs_n), //   inout,   width = 4,    .mem_dqs_n
		.mem_dq    (mem_dq),    //   inout,  width = 32,    .mem_dq
		.mem_dm    (mem_dm)     //   input,   width = 4,    .mem_dm
	);

endmodule
