	component ed_sim_mem is
		port (
			mem_ck    : in    std_logic_vector(0 downto 0)  := (others => 'X'); -- mem_ck
			mem_ck_n  : in    std_logic_vector(0 downto 0)  := (others => 'X'); -- mem_ck_n
			mem_a     : in    std_logic_vector(9 downto 0)  := (others => 'X'); -- mem_a
			mem_cke   : in    std_logic_vector(0 downto 0)  := (others => 'X'); -- mem_cke
			mem_cs_n  : in    std_logic_vector(0 downto 0)  := (others => 'X'); -- mem_cs_n
			mem_odt   : in    std_logic_vector(0 downto 0)  := (others => 'X'); -- mem_odt
			mem_dqs   : inout std_logic_vector(3 downto 0)  := (others => 'X'); -- mem_dqs
			mem_dqs_n : inout std_logic_vector(3 downto 0)  := (others => 'X'); -- mem_dqs_n
			mem_dq    : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
			mem_dm    : in    std_logic_vector(3 downto 0)  := (others => 'X')  -- mem_dm
		);
	end component ed_sim_mem;

	u0 : component ed_sim_mem
		port map (
			mem_ck    => CONNECTED_TO_mem_ck,    -- mem.mem_ck
			mem_ck_n  => CONNECTED_TO_mem_ck_n,  --    .mem_ck_n
			mem_a     => CONNECTED_TO_mem_a,     --    .mem_a
			mem_cke   => CONNECTED_TO_mem_cke,   --    .mem_cke
			mem_cs_n  => CONNECTED_TO_mem_cs_n,  --    .mem_cs_n
			mem_odt   => CONNECTED_TO_mem_odt,   --    .mem_odt
			mem_dqs   => CONNECTED_TO_mem_dqs,   --    .mem_dqs
			mem_dqs_n => CONNECTED_TO_mem_dqs_n, --    .mem_dqs_n
			mem_dq    => CONNECTED_TO_mem_dq,    --    .mem_dq
			mem_dm    => CONNECTED_TO_mem_dm     --    .mem_dm
		);

