ed_sim |

2022.04.06.02:14:42 | Datasheet

Overview

All Components
emif_0 altera_emif 19.2.0
Memory Map

| tg
ctrl_amm_0
emif_0 |
ctrl_amm_0 | 0x00000000

## emif_0

altera_emif v19.2.0

tg | ctrl_amm_0 | emif_0
ctrl_amm_0
pll_ref_clk_source | clk
pll_ref_clk
global_reset_n_splitter | sig_output_if_0
global_reset_n
|  | emif_usr_clk | tg
|  | emif_usr_clk
|  | emif_usr_reset_n
|  | emif_usr_reset_n
|  | mem | mem
|  | mem
|  | status | sim_checker
|  | status_0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## global_reset_n_source

altera_avalon_reset_source v19.1

pll_ref_clk_source | clk | global_reset_n_source
clk
|  | reset | global_reset_n_splitter
|  | sig_input_if

## Parameters
generateLegacySim | false

## Software Assignments (none)

## global_reset_n_splitter

altera_emif_sig_splitter v19.1

global_reset_n_source | reset | global_reset_n_splitter
sig_input_if
|  | sig_output_if_0 | emif_0
|  | global_reset_n

## Parameters
generateLegacySim | false

## Software Assignments (none)

## mem

altera_emif_mem_model v19.1

emif_0 | mem | mem
mem

## Parameters
generateLegacySim | false

## Software Assignments (none)

## pll_ref_clk_source

altera_avalon_clock_source v19.1

## Parameters
generateLegacySim | false

## Software Assignments (none)

## sim_checker

altera_emif_sim_checker v19.1

emif_0 | status | sim_checker
status_0
tg | tg_status_0
tg_status_0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## tg

altera_emif_tg_avl v19.1

emif_0 | emif_usr_clk | tg
emif_usr_clk
emif_usr_reset_n
emif_usr_reset_n
|  | ctrl_amm_0 | emif_0
|  | ctrl_amm_0
|  | tg_status_0 | sim_checker
|  | tg_status_0

## Parameters
generateLegacySim | false

## Software Assignments (none)

generation took 0.01 seconds | rendering took 0.03 seconds