// ed_sim_global_reset_n_source.v

// Generated using ACDS version 21.3 170

`timescale 1 ps / 1 ps
module ed_sim_global_reset_n_source #(
		parameter ASSERT_HIGH_RESET    = 0,
		parameter INITIAL_RESET_CYCLES = 5
	) (
		output wire  reset, // reset.reset_n
		input  wire  clk    //   clk.clk
	);

	altera_avalon_reset_source #(
		.ASSERT_HIGH_RESET    (ASSERT_HIGH_RESET),
		.INITIAL_RESET_CYCLES (INITIAL_RESET_CYCLES)
	) global_reset_n_source (
		.reset (reset), //  output,  width = 1, reset.reset_n
		.clk   (clk)    //   input,  width = 1,   clk.clk
	);

endmodule
