	ed_sim_mem u0 (
		.mem_ck    (_connected_to_mem_ck_),    //   input,   width = 1, mem.mem_ck
		.mem_ck_n  (_connected_to_mem_ck_n_),  //   input,   width = 1,    .mem_ck_n
		.mem_a     (_connected_to_mem_a_),     //   input,  width = 10,    .mem_a
		.mem_cke   (_connected_to_mem_cke_),   //   input,   width = 1,    .mem_cke
		.mem_cs_n  (_connected_to_mem_cs_n_),  //   input,   width = 1,    .mem_cs_n
		.mem_odt   (_connected_to_mem_odt_),   //   input,   width = 1,    .mem_odt
		.mem_dqs   (_connected_to_mem_dqs_),   //   inout,   width = 4,    .mem_dqs
		.mem_dqs_n (_connected_to_mem_dqs_n_), //   inout,   width = 4,    .mem_dqs_n
		.mem_dq    (_connected_to_mem_dq_),    //   inout,  width = 32,    .mem_dq
		.mem_dm    (_connected_to_mem_dm_)     //   input,   width = 4,    .mem_dm
	);

