# This file is auto-generated.
# It is used by make_qii_design.tcl and make_sim_design.tcl, and
# is not intended to be executed directly.

set ip_params(SYS_INFO_DEVICE_FAMILY) "Arria 10"
set ip_params(SYS_INFO_DEVICE) "10AX022C3U19I2SG"
set ip_params(SYS_INFO_DEVICE_SPEEDGRADE) "2"
set ip_params(SYS_INFO_DEVICE_TEMPERATURE_GRADE) "INDUSTRIAL"
set ip_params(SYS_INFO_DEVICE_POWER_MODEL) "STANDARD"
set ip_params(SYS_INFO_DEVICE_DIE_REVISIONS) ""
set ip_params(FAMILY_ENUM) "FAMILY_ARRIA10"
set ip_params(TRAIT_SUPPORTS_VID) "0"
set ip_params(TRAIT_IOBANK_REVISION) ""
set ip_params(PROTOCOL_ENUM) "PROTOCOL_LPDDR3"
set ip_params(IS_ED_SLAVE) "false"
set ip_params(INTERNAL_TESTING_MODE) "false"
set ip_params(CAL_DEBUG_CLOCK_FREQUENCY) "50000000"
set ip_params(SYS_INFO_UNIQUE_ID) "lpddr3xx_emif_0"
set ip_params(PREV_PROTOCOL_ENUM) "PROTOCOL_LPDDR3"
set ip_params(PHY_FPGA_SPEEDGRADE_GUI) "I2 (Production) - change device under 'View'->'Device Family'"
set ip_params(PHY_TARGET_SPEEDGRADE) "I2"
set ip_params(PHY_TARGET_IS_ES) "false"
set ip_params(PHY_TARGET_IS_ES2) "false"
set ip_params(PHY_TARGET_IS_ES3) "false"
set ip_params(PHY_TARGET_IS_PRODUCTION) "true"
set ip_params(PHY_CONFIG_ENUM) "CONFIG_PHY_AND_HARD_CTRL"
set ip_params(PHY_PING_PONG_EN) "false"
set ip_params(PHY_CLAMSHELL_EN) "false"
set ip_params(PHY_RATE_ENUM) "RATE_QUARTER"
set ip_params(PHY_MEM_CLK_FREQ_MHZ) "800.0"
set ip_params(PHY_REF_CLK_FREQ_MHZ) "200.0"
set ip_params(PHY_REF_CLK_JITTER_PS) "10.0"
set ip_params(PHY_DLL_CORE_UPDN_EN) "true"
set ip_params(PHY_CORE_CLKS_SHARING_ENUM) "CORE_CLKS_SHARING_DISABLED"
set ip_params(PHY_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT) "false"
set ip_params(PHY_CALIBRATED_OCT) "true"
set ip_params(PHY_AC_CALIBRATED_OCT) "true"
set ip_params(PHY_CK_CALIBRATED_OCT) "true"
set ip_params(PHY_DATA_CALIBRATED_OCT) "true"
set ip_params(PHY_RZQ) "240"
set ip_params(PHY_HPS_ENABLE_EARLY_RELEASE) "false"
set ip_params(PHY_USER_PERIODIC_OCT_RECAL_ENUM) "PERIODIC_OCT_RECAL_AUTO"
set ip_params(PHY_AC_IO_STD_ENUM) "IO_STD_HSUL_12"
set ip_params(PHY_CK_IO_STD_ENUM) "IO_STD_HSUL_12"
set ip_params(PHY_DATA_IO_STD_ENUM) "IO_STD_HSUL_12"
set ip_params(PHY_AC_MODE_ENUM) "OUT_OCT_40_CAL"
set ip_params(PHY_CK_MODE_ENUM) "OUT_OCT_40_CAL"
set ip_params(PHY_AC_DEEMPHASIS_ENUM) "DEEMPHASIS_MODE_INVALID"
set ip_params(PHY_CK_DEEMPHASIS_ENUM) "DEEMPHASIS_MODE_INVALID"
set ip_params(PHY_DATA_OUT_DEEMPHASIS_ENUM) "DEEMPHASIS_MODE_INVALID"
set ip_params(PHY_DATA_OUT_SLEW_RATE_ENUM) ""
set ip_params(PHY_DATA_OUT_MODE_ENUM) "OUT_OCT_40_CAL"
set ip_params(PHY_MIMIC_HPS_EMIF) "false"
set ip_params(PLL_ADD_EXTRA_CLKS) "false"
set ip_params(PLL_USER_NUM_OF_EXTRA_CLKS) "0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0) "0.0"
set ip_params(PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0) "ps"
set ip_params(PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1) "0.0"
set ip_params(PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1) "ps"
set ip_params(PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2) "0.0"
set ip_params(PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2) "ps"
set ip_params(PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3) "0.0"
set ip_params(PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3) "ps"
set ip_params(PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4) "0.0"
set ip_params(PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4) "ps"
set ip_params(PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5) "0.0"
set ip_params(PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5) "ps"
set ip_params(PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6) "0.0"
set ip_params(PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6) "ps"
set ip_params(PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7) "0.0"
set ip_params(PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7) "ps"
set ip_params(PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8) "0.0"
set ip_params(PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8) "ps"
set ip_params(PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8) "0.0"
set ip_params(PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8) "50.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8) "50.0"
set ip_params(PLL_VCO_CLK_FREQ_MHZ) "800.0"
set ip_params(PLL_NUM_OF_EXTRA_CLKS) "0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_0) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_0) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_1) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_1) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_2) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_2) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_3) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_3) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_4) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_4) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_5) "800.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_5) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_6) "800.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_6) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_7) "800.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_7) "0.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_8) "800.0"
set ip_params(PLL_EXTRA_CLK_ACTUAL_PHASE_PS_8) "0.0"
set ip_params(PHY_DDR3_CONFIG_ENUM) "CONFIG_PHY_AND_HARD_CTRL"
set ip_params(PHY_DDR3_USER_PING_PONG_EN) "false"
set ip_params(PHY_DDR3_MEM_CLK_FREQ_MHZ) "1066.667"
set ip_params(PHY_DDR3_DEFAULT_REF_CLK_FREQ) "true"
set ip_params(PHY_DDR3_USER_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_DDR3_REF_CLK_JITTER_PS) "10.0"
set ip_params(PHY_DDR3_RATE_ENUM) "RATE_QUARTER"
set ip_params(PHY_DDR3_CORE_CLKS_SHARING_ENUM) "CORE_CLKS_SHARING_DISABLED"
set ip_params(PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT) "false"
set ip_params(PHY_DDR3_IO_VOLTAGE) "1.5"
set ip_params(PHY_DDR3_DEFAULT_IO) "true"
set ip_params(PHY_DDR3_HPS_ENABLE_EARLY_RELEASE) "false"
set ip_params(PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM) "PERIODIC_OCT_RECAL_AUTO"
set ip_params(PHY_DDR3_USER_DLL_CORE_UPDN_EN) "true"
set ip_params(PHY_DDR3_MIMIC_HPS_EMIF) "false"
set ip_params(PHY_DDR3_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_DDR3_PING_PONG_EN) "false"
set ip_params(PHY_DDR3_USER_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR3_USER_AC_MODE_ENUM) "unset"
set ip_params(PHY_DDR3_USER_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDR3_USER_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDR3_USER_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR3_USER_CK_MODE_ENUM) "unset"
set ip_params(PHY_DDR3_USER_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDR3_USER_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDR3_USER_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR3_USER_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_DDR3_USER_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDR3_USER_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDR3_USER_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_DDR3_USER_STARTING_VREFIN) "70.0"
set ip_params(PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR3_USER_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR3_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR3_AC_MODE_ENUM) "unset"
set ip_params(PHY_DDR3_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDR3_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDR3_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR3_CK_MODE_ENUM) "unset"
set ip_params(PHY_DDR3_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDR3_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDR3_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR3_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_DDR3_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDR3_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDR3_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_DDR3_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_DDR3_STARTING_VREFIN) "70.0"
set ip_params(PHY_DDR3_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR3_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR3_CAL_ADDR0) "0"
set ip_params(PHY_DDR3_CAL_ADDR1) "8"
set ip_params(PHY_DDR3_CAL_ENABLE_NON_DES) "false"
set ip_params(PHY_DDR4_CONFIG_ENUM) "CONFIG_PHY_AND_HARD_CTRL"
set ip_params(PHY_DDR4_USER_PING_PONG_EN) "false"
set ip_params(PHY_DDR4_USER_CLAMSHELL_EN) "false"
set ip_params(PHY_DDR4_USER_DLL_CORE_UPDN_EN) "true"
set ip_params(PHY_DDR4_MEM_CLK_FREQ_MHZ) "1200.0"
set ip_params(PHY_DDR4_DEFAULT_REF_CLK_FREQ) "true"
set ip_params(PHY_DDR4_USER_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_DDR4_REF_CLK_JITTER_PS) "10.0"
set ip_params(PHY_DDR4_RATE_ENUM) "RATE_QUARTER"
set ip_params(PHY_DDR4_CORE_CLKS_SHARING_ENUM) "CORE_CLKS_SHARING_DISABLED"
set ip_params(PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT) "false"
set ip_params(PHY_DDR4_IO_VOLTAGE) "1.2"
set ip_params(PHY_DDR4_DEFAULT_IO) "true"
set ip_params(PHY_DDR4_HPS_ENABLE_EARLY_RELEASE) "false"
set ip_params(PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM) "PERIODIC_OCT_RECAL_AUTO"
set ip_params(PHY_DDR4_MIMIC_HPS_EMIF) "false"
set ip_params(PHY_DDR4_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_DDR4_PING_PONG_EN) "false"
set ip_params(PHY_DDR4_CLAMSHELL_EN) "false"
set ip_params(PHY_DDR4_USER_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR4_USER_AC_MODE_ENUM) "unset"
set ip_params(PHY_DDR4_USER_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDR4_USER_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDR4_USER_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR4_USER_CK_MODE_ENUM) "unset"
set ip_params(PHY_DDR4_USER_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDR4_USER_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDR4_USER_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR4_USER_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDR4_USER_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_DDR4_USER_STARTING_VREFIN) "70.0"
set ip_params(PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR4_USER_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR4_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR4_AC_MODE_ENUM) "unset"
set ip_params(PHY_DDR4_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDR4_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDR4_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR4_CK_MODE_ENUM) "unset"
set ip_params(PHY_DDR4_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDR4_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDR4_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR4_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_DDR4_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDR4_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDR4_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_DDR4_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_DDR4_STARTING_VREFIN) "70.0"
set ip_params(PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_DDR4_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR2_CONFIG_ENUM) "CONFIG_PHY_AND_SOFT_CTRL"
set ip_params(PHY_QDR2_USER_PING_PONG_EN) "false"
set ip_params(PHY_QDR2_MEM_CLK_FREQ_MHZ) "633.333"
set ip_params(PHY_QDR2_DEFAULT_REF_CLK_FREQ) "true"
set ip_params(PHY_QDR2_USER_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_QDR2_REF_CLK_JITTER_PS) "10.0"
set ip_params(PHY_QDR2_RATE_ENUM) "RATE_HALF"
set ip_params(PHY_QDR2_CORE_CLKS_SHARING_ENUM) "CORE_CLKS_SHARING_DISABLED"
set ip_params(PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT) "false"
set ip_params(PHY_QDR2_IO_VOLTAGE) "1.5"
set ip_params(PHY_QDR2_DEFAULT_IO) "true"
set ip_params(PHY_QDR2_HPS_ENABLE_EARLY_RELEASE) "false"
set ip_params(PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM) "PERIODIC_OCT_RECAL_AUTO"
set ip_params(PHY_QDR2_USER_DLL_CORE_UPDN_EN) "true"
set ip_params(PHY_QDR2_MIMIC_HPS_EMIF) "false"
set ip_params(PHY_QDR2_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_QDR2_PING_PONG_EN) "false"
set ip_params(PHY_QDR2_USER_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR2_USER_AC_MODE_ENUM) "unset"
set ip_params(PHY_QDR2_USER_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_QDR2_USER_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_QDR2_USER_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR2_USER_CK_MODE_ENUM) "unset"
set ip_params(PHY_QDR2_USER_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_QDR2_USER_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_QDR2_USER_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR2_USER_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_QDR2_USER_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_QDR2_USER_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_QDR2_USER_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_QDR2_USER_STARTING_VREFIN) "70.0"
set ip_params(PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR2_USER_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR2_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR2_AC_MODE_ENUM) "unset"
set ip_params(PHY_QDR2_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_QDR2_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_QDR2_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR2_CK_MODE_ENUM) "unset"
set ip_params(PHY_QDR2_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_QDR2_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_QDR2_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR2_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_QDR2_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_QDR2_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_QDR2_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_QDR2_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_QDR2_STARTING_VREFIN) "70.0"
set ip_params(PHY_QDR2_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR2_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR4_CONFIG_ENUM) "CONFIG_PHY_AND_SOFT_CTRL"
set ip_params(PHY_QDR4_USER_PING_PONG_EN) "false"
set ip_params(PHY_QDR4_MEM_CLK_FREQ_MHZ) "1066.667"
set ip_params(PHY_QDR4_DEFAULT_REF_CLK_FREQ) "true"
set ip_params(PHY_QDR4_USER_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_QDR4_REF_CLK_JITTER_PS) "10.0"
set ip_params(PHY_QDR4_RATE_ENUM) "RATE_QUARTER"
set ip_params(PHY_QDR4_CORE_CLKS_SHARING_ENUM) "CORE_CLKS_SHARING_DISABLED"
set ip_params(PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT) "false"
set ip_params(PHY_QDR4_IO_VOLTAGE) "1.2"
set ip_params(PHY_QDR4_DEFAULT_IO) "true"
set ip_params(PHY_QDR4_HPS_ENABLE_EARLY_RELEASE) "false"
set ip_params(PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM) "PERIODIC_OCT_RECAL_AUTO"
set ip_params(PHY_QDR4_USER_DLL_CORE_UPDN_EN) "true"
set ip_params(PHY_QDR4_MIMIC_HPS_EMIF) "false"
set ip_params(PHY_QDR4_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_QDR4_PING_PONG_EN) "false"
set ip_params(PHY_QDR4_USER_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR4_USER_AC_MODE_ENUM) "unset"
set ip_params(PHY_QDR4_USER_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_QDR4_USER_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_QDR4_USER_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR4_USER_CK_MODE_ENUM) "unset"
set ip_params(PHY_QDR4_USER_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_QDR4_USER_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_QDR4_USER_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR4_USER_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_QDR4_USER_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_QDR4_USER_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_QDR4_USER_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_QDR4_USER_STARTING_VREFIN) "70.0"
set ip_params(PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR4_USER_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR4_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR4_AC_MODE_ENUM) "unset"
set ip_params(PHY_QDR4_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_QDR4_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_QDR4_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR4_CK_MODE_ENUM) "unset"
set ip_params(PHY_QDR4_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_QDR4_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_QDR4_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR4_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_QDR4_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_QDR4_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_QDR4_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_QDR4_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_QDR4_STARTING_VREFIN) "70.0"
set ip_params(PHY_QDR4_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_QDR4_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD2_CONFIG_ENUM) "CONFIG_PHY_AND_SOFT_CTRL"
set ip_params(PHY_RLD2_USER_PING_PONG_EN) "false"
set ip_params(PHY_RLD2_MEM_CLK_FREQ_MHZ) "533.333"
set ip_params(PHY_RLD2_DEFAULT_REF_CLK_FREQ) "true"
set ip_params(PHY_RLD2_USER_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_RLD2_REF_CLK_JITTER_PS) "10.0"
set ip_params(PHY_RLD2_RATE_ENUM) "RATE_HALF"
set ip_params(PHY_RLD2_CORE_CLKS_SHARING_ENUM) "CORE_CLKS_SHARING_DISABLED"
set ip_params(PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT) "false"
set ip_params(PHY_RLD2_IO_VOLTAGE) "1.8"
set ip_params(PHY_RLD2_DEFAULT_IO) "true"
set ip_params(PHY_RLD2_HPS_ENABLE_EARLY_RELEASE) "false"
set ip_params(PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM) "PERIODIC_OCT_RECAL_AUTO"
set ip_params(PHY_RLD2_USER_DLL_CORE_UPDN_EN) "true"
set ip_params(PHY_RLD2_MIMIC_HPS_EMIF) "false"
set ip_params(PHY_RLD2_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_RLD2_PING_PONG_EN) "false"
set ip_params(PHY_RLD2_USER_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD2_USER_AC_MODE_ENUM) "unset"
set ip_params(PHY_RLD2_USER_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_RLD2_USER_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_RLD2_USER_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD2_USER_CK_MODE_ENUM) "unset"
set ip_params(PHY_RLD2_USER_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_RLD2_USER_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_RLD2_USER_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD2_USER_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_RLD2_USER_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_RLD2_USER_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_RLD2_USER_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_RLD2_USER_STARTING_VREFIN) "70.0"
set ip_params(PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD2_USER_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD2_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD2_AC_MODE_ENUM) "unset"
set ip_params(PHY_RLD2_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_RLD2_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_RLD2_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD2_CK_MODE_ENUM) "unset"
set ip_params(PHY_RLD2_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_RLD2_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_RLD2_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD2_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_RLD2_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_RLD2_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_RLD2_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_RLD2_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_RLD2_STARTING_VREFIN) "70.0"
set ip_params(PHY_RLD2_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD2_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD3_CONFIG_ENUM) "CONFIG_PHY_ONLY"
set ip_params(PHY_RLD3_USER_PING_PONG_EN) "false"
set ip_params(PHY_RLD3_MEM_CLK_FREQ_MHZ) "1066.667"
set ip_params(PHY_RLD3_DEFAULT_REF_CLK_FREQ) "true"
set ip_params(PHY_RLD3_USER_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_RLD3_REF_CLK_JITTER_PS) "10.0"
set ip_params(PHY_RLD3_RATE_ENUM) "RATE_QUARTER"
set ip_params(PHY_RLD3_CORE_CLKS_SHARING_ENUM) "CORE_CLKS_SHARING_DISABLED"
set ip_params(PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT) "false"
set ip_params(PHY_RLD3_IO_VOLTAGE) "1.2"
set ip_params(PHY_RLD3_DEFAULT_IO) "true"
set ip_params(PHY_RLD3_HPS_ENABLE_EARLY_RELEASE) "false"
set ip_params(PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM) "PERIODIC_OCT_RECAL_AUTO"
set ip_params(PHY_RLD3_USER_DLL_CORE_UPDN_EN) "true"
set ip_params(PHY_RLD3_MIMIC_HPS_EMIF) "false"
set ip_params(PHY_RLD3_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_RLD3_PING_PONG_EN) "false"
set ip_params(PHY_RLD3_USER_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD3_USER_AC_MODE_ENUM) "unset"
set ip_params(PHY_RLD3_USER_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_RLD3_USER_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_RLD3_USER_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD3_USER_CK_MODE_ENUM) "unset"
set ip_params(PHY_RLD3_USER_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_RLD3_USER_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_RLD3_USER_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD3_USER_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_RLD3_USER_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_RLD3_USER_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_RLD3_USER_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_RLD3_USER_STARTING_VREFIN) "70.0"
set ip_params(PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD3_USER_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD3_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD3_AC_MODE_ENUM) "unset"
set ip_params(PHY_RLD3_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_RLD3_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_RLD3_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD3_CK_MODE_ENUM) "unset"
set ip_params(PHY_RLD3_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_RLD3_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_RLD3_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD3_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_RLD3_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_RLD3_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_RLD3_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_RLD3_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_RLD3_STARTING_VREFIN) "70.0"
set ip_params(PHY_RLD3_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_RLD3_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_LPDDR3_CONFIG_ENUM) "CONFIG_PHY_AND_HARD_CTRL"
set ip_params(PHY_LPDDR3_USER_PING_PONG_EN) "false"
set ip_params(PHY_LPDDR3_MEM_CLK_FREQ_MHZ) "800.0"
set ip_params(PHY_LPDDR3_DEFAULT_REF_CLK_FREQ) "true"
set ip_params(PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ) "200.0"
set ip_params(PHY_LPDDR3_REF_CLK_JITTER_PS) "10.0"
set ip_params(PHY_LPDDR3_RATE_ENUM) "RATE_QUARTER"
set ip_params(PHY_LPDDR3_CORE_CLKS_SHARING_ENUM) "CORE_CLKS_SHARING_DISABLED"
set ip_params(PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT) "false"
set ip_params(PHY_LPDDR3_IO_VOLTAGE) "1.2"
set ip_params(PHY_LPDDR3_DEFAULT_IO) "true"
set ip_params(PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE) "false"
set ip_params(PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM) "PERIODIC_OCT_RECAL_AUTO"
set ip_params(PHY_LPDDR3_USER_DLL_CORE_UPDN_EN) "true"
set ip_params(PHY_LPDDR3_MIMIC_HPS_EMIF) "false"
set ip_params(PHY_LPDDR3_REF_CLK_FREQ_MHZ) "200.0"
set ip_params(PHY_LPDDR3_PING_PONG_EN) "false"
set ip_params(PHY_LPDDR3_USER_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_AC_MODE_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_CK_MODE_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_LPDDR3_USER_STARTING_VREFIN) "70.0"
set ip_params(PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_LPDDR3_USER_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_LPDDR3_AC_IO_STD_ENUM) "IO_STD_HSUL_12"
set ip_params(PHY_LPDDR3_AC_MODE_ENUM) "OUT_OCT_40_CAL"
set ip_params(PHY_LPDDR3_AC_SLEW_RATE_ENUM) "SLEW_RATE_FAST"
set ip_params(PHY_LPDDR3_AC_DEEMPHASIS_ENUM) "DEEMPHASIS_MODE_INVALID"
set ip_params(PHY_LPDDR3_CK_IO_STD_ENUM) "IO_STD_HSUL_12"
set ip_params(PHY_LPDDR3_CK_MODE_ENUM) "OUT_OCT_40_CAL"
set ip_params(PHY_LPDDR3_CK_SLEW_RATE_ENUM) "SLEW_RATE_FAST"
set ip_params(PHY_LPDDR3_CK_DEEMPHASIS_ENUM) "DEEMPHASIS_MODE_INVALID"
set ip_params(PHY_LPDDR3_DATA_IO_STD_ENUM) "IO_STD_HSUL_12"
set ip_params(PHY_LPDDR3_DATA_OUT_MODE_ENUM) "OUT_OCT_40_CAL"
set ip_params(PHY_LPDDR3_DATA_OUT_SLEW_RATE_ENUM) "SLEW_RATE_INVALID"
set ip_params(PHY_LPDDR3_DATA_OUT_DEEMPHASIS_ENUM) "DEEMPHASIS_MODE_INVALID"
set ip_params(PHY_LPDDR3_DATA_IN_MODE_ENUM) "IN_OCT_INFINITE_CAL"
set ip_params(PHY_LPDDR3_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_LPDDR3_STARTING_VREFIN) "50.0"
set ip_params(PHY_LPDDR3_PLL_REF_CLK_IO_STD_ENUM) "IO_STD_LVDS"
set ip_params(PHY_LPDDR3_RZQ_IO_STD_ENUM) "IO_STD_CMOS_12"
set ip_params(PHY_DDRT_CONFIG_ENUM) "CONFIG_PHY_AND_SOFT_CTRL"
set ip_params(PHY_DDRT_USER_PING_PONG_EN) "false"
set ip_params(PHY_DDRT_USER_DLL_CORE_UPDN_EN) "false"
set ip_params(PHY_DDRT_MEM_CLK_FREQ_MHZ) "1200.0"
set ip_params(PHY_DDRT_DEFAULT_REF_CLK_FREQ) "true"
set ip_params(PHY_DDRT_USER_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_DDRT_REF_CLK_JITTER_PS) "10.0"
set ip_params(PHY_DDRT_RATE_ENUM) "RATE_QUARTER"
set ip_params(PHY_DDRT_CORE_CLKS_SHARING_ENUM) "CORE_CLKS_SHARING_DISABLED"
set ip_params(PHY_DDRT_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT) "false"
set ip_params(PHY_DDRT_IO_VOLTAGE) "1.2"
set ip_params(PHY_DDRT_DEFAULT_IO) "true"
set ip_params(PHY_DDRT_HPS_ENABLE_EARLY_RELEASE) "false"
set ip_params(PHY_DDRT_USER_PERIODIC_OCT_RECAL_ENUM) "PERIODIC_OCT_RECAL_AUTO"
set ip_params(PHY_DDRT_MIMIC_HPS_EMIF) "false"
set ip_params(PHY_DDRT_IC_EN) "true"
set ip_params(PHY_DDRT_2CH_EN) "false"
set ip_params(PHY_DDRT_USE_OLD_SMBUS_MULTICOL) "false"
set ip_params(PHY_DDRT_EXPORT_CLK_STP_IF) "false"
set ip_params(PHY_DDRT_REF_CLK_FREQ_MHZ) "-1.0"
set ip_params(PHY_DDRT_PING_PONG_EN) "false"
set ip_params(PHY_DDRT_USER_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_DDRT_USER_AC_MODE_ENUM) "unset"
set ip_params(PHY_DDRT_USER_AC_IN_MODE_ENUM) "unset"
set ip_params(PHY_DDRT_USER_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDRT_USER_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDRT_USER_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_DDRT_USER_CK_MODE_ENUM) "unset"
set ip_params(PHY_DDRT_USER_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDRT_USER_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDRT_USER_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_DDRT_USER_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_DDRT_USER_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDRT_USER_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDRT_USER_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_DDRT_USER_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_DDRT_USER_STARTING_VREFIN) "70.0"
set ip_params(PHY_DDRT_USER_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_DDRT_USER_RZQ_IO_STD_ENUM) "unset"
set ip_params(PHY_DDRT_AC_IO_STD_ENUM) "unset"
set ip_params(PHY_DDRT_AC_MODE_ENUM) "unset"
set ip_params(PHY_DDRT_AC_IN_MODE_ENUM) "unset"
set ip_params(PHY_DDRT_AC_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDRT_AC_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDRT_CK_IO_STD_ENUM) "unset"
set ip_params(PHY_DDRT_CK_MODE_ENUM) "unset"
set ip_params(PHY_DDRT_CK_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDRT_CK_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDRT_DATA_IO_STD_ENUM) "unset"
set ip_params(PHY_DDRT_DATA_OUT_MODE_ENUM) "unset"
set ip_params(PHY_DDRT_DATA_OUT_SLEW_RATE_ENUM) "unset"
set ip_params(PHY_DDRT_DATA_OUT_DEEMPHASIS_ENUM) "unset"
set ip_params(PHY_DDRT_DATA_IN_MODE_ENUM) "unset"
set ip_params(PHY_DDRT_AUTO_STARTING_VREFIN_EN) "true"
set ip_params(PHY_DDRT_STARTING_VREFIN) "70.0"
set ip_params(PHY_DDRT_PLL_REF_CLK_IO_STD_ENUM) "unset"
set ip_params(PHY_DDRT_RZQ_IO_STD_ENUM) "unset"
set ip_params(MEM_FORMAT_ENUM) "MEM_FORMAT_DISCRETE"
set ip_params(MEM_READ_LATENCY) "12.0"
set ip_params(MEM_WRITE_LATENCY) "6"
set ip_params(MEM_BURST_LENGTH) "8"
set ip_params(MEM_DATA_MASK_EN) "true"
set ip_params(MEM_HAS_SIM_SUPPORT) "true"
set ip_params(MEM_HAS_BSI_SUPPORT) "false"
set ip_params(MEM_NUM_OF_PHYSICAL_RANKS) "1"
set ip_params(MEM_NUM_OF_LOGICAL_RANKS) "1"
set ip_params(MEM_NUM_OF_DATA_ENDPOINTS) "1"
set ip_params(MEM_TTL_DATA_WIDTH) "32"
set ip_params(MEM_TTL_NUM_OF_READ_GROUPS) "4"
set ip_params(MEM_TTL_NUM_OF_WRITE_GROUPS) "4"
set ip_params(MEM_DDR3_FORMAT_ENUM) "MEM_FORMAT_UDIMM"
set ip_params(MEM_DDR3_DQ_WIDTH) "72"
set ip_params(MEM_DDR3_DQ_PER_DQS) "8"
set ip_params(MEM_DDR3_DISCRETE_CS_WIDTH) "1"
set ip_params(MEM_DDR3_NUM_OF_DIMMS) "1"
set ip_params(MEM_DDR3_RANKS_PER_DIMM) "1"
set ip_params(MEM_DDR3_CKE_PER_DIMM) "1"
set ip_params(MEM_DDR3_CK_WIDTH) "1"
set ip_params(MEM_DDR3_ROW_ADDR_WIDTH) "15"
set ip_params(MEM_DDR3_COL_ADDR_WIDTH) "10"
set ip_params(MEM_DDR3_BANK_ADDR_WIDTH) "3"
set ip_params(MEM_DDR3_DM_EN) "true"
set ip_params(MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN) "false"
set ip_params(MEM_DDR3_MIRROR_ADDRESSING_EN) "true"
set ip_params(MEM_DDR3_HIDE_ADV_MR_SETTINGS) "true"
set ip_params(MEM_DDR3_RDIMM_CONFIG) "0000000000000000"
set ip_params(MEM_DDR3_LRDIMM_EXTENDED_CONFIG) "000000000000000000"
set ip_params(MEM_DDR3_ALERT_N_PLACEMENT_ENUM) "DDR3_ALERT_N_PLACEMENT_AC_LANES"
set ip_params(MEM_DDR3_ALERT_N_DQS_GROUP) "0"
set ip_params(MEM_DDR3_DQS_WIDTH) "8"
set ip_params(MEM_DDR3_DM_WIDTH) "1"
set ip_params(MEM_DDR3_CS_WIDTH) "1"
set ip_params(MEM_DDR3_CS_PER_DIMM) "1"
set ip_params(MEM_DDR3_CKE_WIDTH) "1"
set ip_params(MEM_DDR3_ODT_WIDTH) "1"
set ip_params(MEM_DDR3_ADDR_WIDTH) "1"
set ip_params(MEM_DDR3_RM_WIDTH) "0"
set ip_params(MEM_DDR3_AC_PAR_EN) "false"
set ip_params(MEM_DDR3_NUM_OF_PHYSICAL_RANKS) "1"
set ip_params(MEM_DDR3_NUM_OF_LOGICAL_RANKS) "1"
set ip_params(MEM_DDR3_TTL_DQS_WIDTH) "8"
set ip_params(MEM_DDR3_TTL_DQ_WIDTH) "72"
set ip_params(MEM_DDR3_TTL_DM_WIDTH) "1"
set ip_params(MEM_DDR3_TTL_CS_WIDTH) "1"
set ip_params(MEM_DDR3_TTL_CK_WIDTH) "1"
set ip_params(MEM_DDR3_TTL_CKE_WIDTH) "1"
set ip_params(MEM_DDR3_TTL_ODT_WIDTH) "1"
set ip_params(MEM_DDR3_TTL_BANK_ADDR_WIDTH) "3"
set ip_params(MEM_DDR3_TTL_ADDR_WIDTH) "1"
set ip_params(MEM_DDR3_TTL_RM_WIDTH) "0"
set ip_params(MEM_DDR3_TTL_NUM_OF_DIMMS) "1"
set ip_params(MEM_DDR3_TTL_NUM_OF_PHYSICAL_RANKS) "1"
set ip_params(MEM_DDR3_TTL_NUM_OF_LOGICAL_RANKS) "1"
set ip_params(MEM_DDR3_MR0) "0"
set ip_params(MEM_DDR3_MR1) "0"
set ip_params(MEM_DDR3_MR2) "0"
set ip_params(MEM_DDR3_MR3) "0"
set ip_params(MEM_DDR3_ADDRESS_MIRROR_BITVEC) "0"
set ip_params(MEM_DDR3_BL_ENUM) "DDR3_BL_BL8"
set ip_params(MEM_DDR3_BT_ENUM) "DDR3_BT_SEQUENTIAL"
set ip_params(MEM_DDR3_ASR_ENUM) "DDR3_ASR_MANUAL"
set ip_params(MEM_DDR3_SRT_ENUM) "DDR3_SRT_NORMAL"
set ip_params(MEM_DDR3_PD_ENUM) "DDR3_PD_OFF"
set ip_params(MEM_DDR3_DRV_STR_ENUM) "DDR3_DRV_STR_RZQ_7"
set ip_params(MEM_DDR3_DLL_EN) "true"
set ip_params(MEM_DDR3_RTT_NOM_ENUM) "DDR3_RTT_NOM_ODT_DISABLED"
set ip_params(MEM_DDR3_RTT_WR_ENUM) "DDR3_RTT_WR_RZQ_4"
set ip_params(MEM_DDR3_WTCL) "10"
set ip_params(MEM_DDR3_ATCL_ENUM) "DDR3_ATCL_DISABLED"
set ip_params(MEM_DDR3_TCL) "14"
set ip_params(MEM_DDR3_USE_DEFAULT_ODT) "true"
set ip_params(MEM_DDR3_R_ODTN_1X1) "{Rank 0}"
set ip_params(MEM_DDR3_R_ODT0_1X1) "off"
set ip_params(MEM_DDR3_W_ODTN_1X1) "{Rank 0}"
set ip_params(MEM_DDR3_W_ODT0_1X1) "on"
set ip_params(MEM_DDR3_R_ODTN_2X2) "{Rank 0} {Rank 1}"
set ip_params(MEM_DDR3_R_ODT0_2X2) "off off"
set ip_params(MEM_DDR3_R_ODT1_2X2) "off off"
set ip_params(MEM_DDR3_W_ODTN_2X2) "{Rank 0} {Rank 1}"
set ip_params(MEM_DDR3_W_ODT0_2X2) "on off"
set ip_params(MEM_DDR3_W_ODT1_2X2) "off on"
set ip_params(MEM_DDR3_R_ODTN_4X2) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_DDR3_R_ODT0_4X2) "off off on on"
set ip_params(MEM_DDR3_R_ODT1_4X2) "on on off off"
set ip_params(MEM_DDR3_W_ODTN_4X2) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_DDR3_W_ODT0_4X2) "off off on on"
set ip_params(MEM_DDR3_W_ODT1_4X2) "on on off off"
set ip_params(MEM_DDR3_R_ODTN_4X4) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_DDR3_R_ODT0_4X4) "off off on off"
set ip_params(MEM_DDR3_R_ODT1_4X4) "off off off on"
set ip_params(MEM_DDR3_R_ODT2_4X4) "on off off off"
set ip_params(MEM_DDR3_R_ODT3_4X4) "off on off off"
set ip_params(MEM_DDR3_W_ODTN_4X4) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_DDR3_W_ODT0_4X4) "on off on off"
set ip_params(MEM_DDR3_W_ODT1_4X4) "off on off on"
set ip_params(MEM_DDR3_W_ODT2_4X4) "on off on off"
set ip_params(MEM_DDR3_W_ODT3_4X4) "off on off on"
set ip_params(MEM_DDR3_R_DERIVED_ODTN) "{} {} {}"
set ip_params(MEM_DDR3_R_DERIVED_ODT0) "{} {} {}"
set ip_params(MEM_DDR3_R_DERIVED_ODT1) "{} {} {}"
set ip_params(MEM_DDR3_R_DERIVED_ODT2) "{} {} {}"
set ip_params(MEM_DDR3_R_DERIVED_ODT3) "{} {} {}"
set ip_params(MEM_DDR3_W_DERIVED_ODTN) "{} {} {}"
set ip_params(MEM_DDR3_W_DERIVED_ODT0) "{} {} {}"
set ip_params(MEM_DDR3_W_DERIVED_ODT1) "{} {} {}"
set ip_params(MEM_DDR3_W_DERIVED_ODT2) "{} {} {}"
set ip_params(MEM_DDR3_W_DERIVED_ODT3) "{} {} {}"
set ip_params(MEM_DDR3_SEQ_ODT_TABLE_LO) "0"
set ip_params(MEM_DDR3_SEQ_ODT_TABLE_HI) "0"
set ip_params(MEM_DDR3_CTRL_CFG_READ_ODT_CHIP) "0"
set ip_params(MEM_DDR3_CTRL_CFG_WRITE_ODT_CHIP) "0"
set ip_params(MEM_DDR3_CTRL_CFG_READ_ODT_RANK) "0"
set ip_params(MEM_DDR3_CTRL_CFG_WRITE_ODT_RANK) "0"
set ip_params(MEM_DDR3_SPEEDBIN_ENUM) "DDR3_SPEEDBIN_2133"
set ip_params(MEM_DDR3_TIS_PS) "60"
set ip_params(MEM_DDR3_TIS_AC_MV) "135"
set ip_params(MEM_DDR3_TIH_PS) "95"
set ip_params(MEM_DDR3_TIH_DC_MV) "100"
set ip_params(MEM_DDR3_TDS_PS) "53"
set ip_params(MEM_DDR3_TDS_AC_MV) "135"
set ip_params(MEM_DDR3_TDH_PS) "55"
set ip_params(MEM_DDR3_TDH_DC_MV) "100"
set ip_params(MEM_DDR3_TDQSQ_PS) "75"
set ip_params(MEM_DDR3_TQH_CYC) "0.38"
set ip_params(MEM_DDR3_TDQSCK_PS) "180"
set ip_params(MEM_DDR3_TDQSS_CYC) "0.27"
set ip_params(MEM_DDR3_TQSH_CYC) "0.4"
set ip_params(MEM_DDR3_TDSH_CYC) "0.18"
set ip_params(MEM_DDR3_TWLS_PS) "125.0"
set ip_params(MEM_DDR3_TWLH_PS) "125.0"
set ip_params(MEM_DDR3_TDSS_CYC) "0.18"
set ip_params(MEM_DDR3_TINIT_US) "500"
set ip_params(MEM_DDR3_TMRD_CK_CYC) "4"
set ip_params(MEM_DDR3_TRAS_NS) "33.0"
set ip_params(MEM_DDR3_TRCD_NS) "13.09"
set ip_params(MEM_DDR3_TRP_NS) "13.09"
set ip_params(MEM_DDR3_TREFI_US) "7.8"
set ip_params(MEM_DDR3_TRFC_NS) "160.0"
set ip_params(MEM_DDR3_TWR_NS) "15.0"
set ip_params(MEM_DDR3_TWTR_CYC) "8"
set ip_params(MEM_DDR3_TFAW_NS) "25.0"
set ip_params(MEM_DDR3_TRRD_CYC) "6"
set ip_params(MEM_DDR3_TRTP_CYC) "8"
set ip_params(MEM_DDR3_TINIT_CK) "499"
set ip_params(MEM_DDR3_TDQSCK_DERV_PS) "2"
set ip_params(MEM_DDR3_TDQSCKDS) "450"
set ip_params(MEM_DDR3_TDQSCKDM) "900"
set ip_params(MEM_DDR3_TDQSCKDL) "1200"
set ip_params(MEM_DDR3_TRAS_CYC) "36"
set ip_params(MEM_DDR3_TRCD_CYC) "14"
set ip_params(MEM_DDR3_TRP_CYC) "14"
set ip_params(MEM_DDR3_TRFC_CYC) "171"
set ip_params(MEM_DDR3_TWR_CYC) "16"
set ip_params(MEM_DDR3_TFAW_CYC) "27"
set ip_params(MEM_DDR3_TREFI_CYC) "8320"
set ip_params(MEM_DDR3_CFG_GEN_SBE) "false"
set ip_params(MEM_DDR3_CFG_GEN_DBE) "false"
set ip_params(MEM_DDR4_FORMAT_ENUM) "MEM_FORMAT_UDIMM"
set ip_params(MEM_DDR4_DQ_WIDTH) "72"
set ip_params(MEM_DDR4_DQ_PER_DQS) "8"
set ip_params(MEM_DDR4_DISCRETE_CS_WIDTH) "1"
set ip_params(MEM_DDR4_NUM_OF_DIMMS) "1"
set ip_params(MEM_DDR4_CHIP_ID_WIDTH) "0"
set ip_params(MEM_DDR4_RANKS_PER_DIMM) "1"
set ip_params(MEM_DDR4_CKE_PER_DIMM) "1"
set ip_params(MEM_DDR4_CK_WIDTH) "1"
set ip_params(MEM_DDR4_ROW_ADDR_WIDTH) "15"
set ip_params(MEM_DDR4_COL_ADDR_WIDTH) "10"
set ip_params(MEM_DDR4_BANK_ADDR_WIDTH) "2"
set ip_params(MEM_DDR4_BANK_GROUP_WIDTH) "2"
set ip_params(MEM_DDR4_DM_EN) "true"
set ip_params(MEM_DDR4_ALERT_PAR_EN) "true"
set ip_params(MEM_DDR4_ALERT_N_PLACEMENT_ENUM) "DDR4_ALERT_N_PLACEMENT_AUTO"
set ip_params(MEM_DDR4_ALERT_N_DQS_GROUP) "0"
set ip_params(MEM_DDR4_ALERT_N_AC_LANE) "0"
set ip_params(MEM_DDR4_ALERT_N_AC_PIN) "0"
set ip_params(MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN) "false"
set ip_params(MEM_DDR4_MIRROR_ADDRESSING_EN) "true"
set ip_params(MEM_DDR4_HIDE_ADV_MR_SETTINGS) "true"
set ip_params(MEM_DDR4_INTEL_DEFAULT_TERM) "true"
set ip_params(MEM_DDR4_BL_ENUM) "DDR4_BL_BL8"
set ip_params(MEM_DDR4_BT_ENUM) "DDR4_BT_SEQUENTIAL"
set ip_params(MEM_DDR4_TCL) "18"
set ip_params(MEM_DDR4_RTT_NOM_ENUM) "DDR4_RTT_NOM_RZQ_4"
set ip_params(MEM_DDR4_DLL_EN) "true"
set ip_params(MEM_DDR4_ATCL_ENUM) "DDR4_ATCL_DISABLED"
set ip_params(MEM_DDR4_DRV_STR_ENUM) "DDR4_DRV_STR_RZQ_7"
set ip_params(MEM_DDR4_ASR_ENUM) "DDR4_ASR_MANUAL_NORMAL"
set ip_params(MEM_DDR4_RTT_WR_ENUM) "DDR4_RTT_WR_ODT_DISABLED"
set ip_params(MEM_DDR4_WTCL) "12"
set ip_params(MEM_DDR4_WRITE_CRC) "false"
set ip_params(MEM_DDR4_GEARDOWN) "DDR4_GEARDOWN_HR"
set ip_params(MEM_DDR4_PER_DRAM_ADDR) "false"
set ip_params(MEM_DDR4_TEMP_SENSOR_READOUT) "false"
set ip_params(MEM_DDR4_FINE_GRANULARITY_REFRESH) "DDR4_FINE_REFRESH_FIXED_1X"
set ip_params(MEM_DDR4_MPR_READ_FORMAT) "DDR4_MPR_READ_FORMAT_SERIAL"
set ip_params(MEM_DDR4_MAX_POWERDOWN) "false"
set ip_params(MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE) "DDR4_TEMP_CONTROLLED_RFSH_NORMAL"
set ip_params(MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA) "false"
set ip_params(MEM_DDR4_INTERNAL_VREFDQ_MONITOR) "false"
set ip_params(MEM_DDR4_CAL_MODE) "0"
set ip_params(MEM_DDR4_SELF_RFSH_ABORT) "false"
set ip_params(MEM_DDR4_READ_PREAMBLE_TRAINING) "false"
set ip_params(MEM_DDR4_READ_PREAMBLE) "2"
set ip_params(MEM_DDR4_WRITE_PREAMBLE) "1"
set ip_params(MEM_DDR4_AC_PARITY_LATENCY) "DDR4_AC_PARITY_LATENCY_DISABLE"
set ip_params(MEM_DDR4_ODT_IN_POWERDOWN) "true"
set ip_params(MEM_DDR4_RTT_PARK) "DDR4_RTT_PARK_ODT_DISABLED"
set ip_params(MEM_DDR4_AC_PERSISTENT_ERROR) "false"
set ip_params(MEM_DDR4_WRITE_DBI) "false"
set ip_params(MEM_DDR4_READ_DBI) "true"
set ip_params(MEM_DDR4_DEFAULT_VREFOUT) "true"
set ip_params(MEM_DDR4_USER_VREFDQ_TRAINING_VALUE) "56.0"
set ip_params(MEM_DDR4_USER_VREFDQ_TRAINING_RANGE) "DDR4_VREFDQ_TRAINING_RANGE_1"
set ip_params(MEM_DDR4_RCD_CA_IBT_ENUM) "DDR4_RCD_CA_IBT_100"
set ip_params(MEM_DDR4_RCD_CS_IBT_ENUM) "DDR4_RCD_CS_IBT_100"
set ip_params(MEM_DDR4_RCD_CKE_IBT_ENUM) "DDR4_RCD_CKE_IBT_100"
set ip_params(MEM_DDR4_RCD_ODT_IBT_ENUM) "DDR4_RCD_ODT_IBT_100"
set ip_params(MEM_DDR4_DB_RTT_NOM_ENUM) "DDR4_DB_RTT_NOM_ODT_DISABLED"
set ip_params(MEM_DDR4_DB_RTT_WR_ENUM) "DDR4_DB_RTT_WR_RZQ_3"
set ip_params(MEM_DDR4_DB_RTT_PARK_ENUM) "DDR4_DB_RTT_PARK_ODT_DISABLED"
set ip_params(MEM_DDR4_DB_DQ_DRV_ENUM) "DDR4_DB_DRV_STR_RZQ_7"
set ip_params(MEM_DDR4_SPD_137_RCD_CA_DRV) "101"
set ip_params(MEM_DDR4_SPD_138_RCD_CK_DRV) "5"
set ip_params(MEM_DDR4_SPD_140_DRAM_VREFDQ_R0) "29"
set ip_params(MEM_DDR4_SPD_141_DRAM_VREFDQ_R1) "29"
set ip_params(MEM_DDR4_SPD_142_DRAM_VREFDQ_R2) "29"
set ip_params(MEM_DDR4_SPD_143_DRAM_VREFDQ_R3) "29"
set ip_params(MEM_DDR4_SPD_144_DB_VREFDQ) "37"
set ip_params(MEM_DDR4_SPD_145_DB_MDQ_DRV) "21"
set ip_params(MEM_DDR4_SPD_148_DRAM_DRV) "0"
set ip_params(MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM) "20"
set ip_params(MEM_DDR4_SPD_152_DRAM_RTT_PARK) "39"
set ip_params(MEM_DDR4_SPD_155_DB_VREFDQ_RANGE) "0"
set ip_params(MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB) "0"
set ip_params(MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB) "0"
set ip_params(MEM_DDR4_SPD_135_RCD_REV) "0"
set ip_params(MEM_DDR4_SPD_139_DB_REV) "0"
set ip_params(MEM_DDR4_LRDIMM_ODT_LESS_BS) "true"
set ip_params(MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM) "240"
set ip_params(MEM_DDR4_DQS_WIDTH) "8"
set ip_params(MEM_DDR4_CS_WIDTH) "1"
set ip_params(MEM_DDR4_CS_PER_DIMM) "1"
set ip_params(MEM_DDR4_CKE_WIDTH) "1"
set ip_params(MEM_DDR4_ODT_WIDTH) "1"
set ip_params(MEM_DDR4_ADDR_WIDTH) "1"
set ip_params(MEM_DDR4_RM_WIDTH) "0"
set ip_params(MEM_DDR4_NUM_OF_PHYSICAL_RANKS) "1"
set ip_params(MEM_DDR4_NUM_OF_LOGICAL_RANKS) "1"
set ip_params(MEM_DDR4_IDEAL_VREF_IN_PCT) "60.0"
set ip_params(MEM_DDR4_IDEAL_VREF_OUT_PCT) "60.0"
set ip_params(MEM_DDR4_VREFDQ_TRAINING_VALUE) "56.0"
set ip_params(MEM_DDR4_VREFDQ_TRAINING_RANGE) "DDR4_VREFDQ_TRAINING_RANGE_1"
set ip_params(MEM_DDR4_VREFDQ_TRAINING_RANGE_DISP) "Range 2 - 45% to 77.5%"
set ip_params(MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM) "DDR4_DRV_STR_RZQ_7"
set ip_params(MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM) "DDR4_RTT_WR_ODT_DISABLED"
set ip_params(MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM) "DDR4_RTT_NOM_RZQ_4"
set ip_params(MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM) "DDR4_RTT_PARK_ODT_DISABLED"
set ip_params(MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM_DISP) "RZQ/7 (34 Ohm)"
set ip_params(MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM_DISP) "Dynamic ODT off"
set ip_params(MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM_DISP) "RZQ/4 (60 Ohm)"
set ip_params(MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM_DISP) "Park ODT off"
set ip_params(MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM) "DDR4_DB_RTT_NOM_ODT_DISABLED"
set ip_params(MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM) "DDR4_DB_RTT_WR_RZQ_3"
set ip_params(MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM) "DDR4_DB_RTT_PARK_ODT_DISABLED"
set ip_params(MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM) "DDR4_DB_DRV_STR_RZQ_7"
set ip_params(MEM_DDR4_INTEL_DEFAULT_DB_RTT_NOM_ENUM_DISP) "RTT_NOM disabled"
set ip_params(MEM_DDR4_INTEL_DEFAULT_DB_RTT_WR_ENUM_DISP) "RZQ/3 (80 Ohm)"
set ip_params(MEM_DDR4_INTEL_DEFAULT_DB_RTT_PARK_ENUM_DISP) "RTT_PARK disabled"
set ip_params(MEM_DDR4_INTEL_DEFAULT_DB_DQ_DRV_ENUM_DISP) "RZQ/7 (34 Ohm)"
set ip_params(MEM_DDR4_TTL_DQS_WIDTH) "8"
set ip_params(MEM_DDR4_TTL_DQ_WIDTH) "72"
set ip_params(MEM_DDR4_TTL_CS_WIDTH) "1"
set ip_params(MEM_DDR4_TTL_CK_WIDTH) "1"
set ip_params(MEM_DDR4_TTL_CKE_WIDTH) "1"
set ip_params(MEM_DDR4_TTL_ODT_WIDTH) "1"
set ip_params(MEM_DDR4_TTL_BANK_ADDR_WIDTH) "2"
set ip_params(MEM_DDR4_TTL_BANK_GROUP_WIDTH) "2"
set ip_params(MEM_DDR4_TTL_CHIP_ID_WIDTH) "0"
set ip_params(MEM_DDR4_TTL_ADDR_WIDTH) "1"
set ip_params(MEM_DDR4_TTL_RM_WIDTH) "0"
set ip_params(MEM_DDR4_TTL_NUM_OF_DIMMS) "1"
set ip_params(MEM_DDR4_TTL_NUM_OF_PHYSICAL_RANKS) "1"
set ip_params(MEM_DDR4_TTL_NUM_OF_LOGICAL_RANKS) "1"
set ip_params(MEM_DDR4_MR0) "0"
set ip_params(MEM_DDR4_MR1) "0"
set ip_params(MEM_DDR4_MR2) "0"
set ip_params(MEM_DDR4_MR3) "0"
set ip_params(MEM_DDR4_MR4) "0"
set ip_params(MEM_DDR4_MR5) "0"
set ip_params(MEM_DDR4_MR6) "0"
set ip_params(MEM_DDR4_RDIMM_CONFIG) ""
set ip_params(MEM_DDR4_LRDIMM_EXTENDED_CONFIG) ""
set ip_params(MEM_DDR4_ADDRESS_MIRROR_BITVEC) "0"
set ip_params(MEM_DDR4_RCD_PARITY_CONTROL_WORD) "13"
set ip_params(MEM_DDR4_RCD_COMMAND_LATENCY) "1"
set ip_params(MEM_DDR4_USE_DEFAULT_ODT) "true"
set ip_params(MEM_DDR4_R_ODTN_1X1) "{Rank 0}"
set ip_params(MEM_DDR4_R_ODT0_1X1) "off"
set ip_params(MEM_DDR4_W_ODTN_1X1) "{Rank 0}"
set ip_params(MEM_DDR4_W_ODT0_1X1) "on"
set ip_params(MEM_DDR4_R_ODTN_2X2) "{Rank 0} {Rank 1}"
set ip_params(MEM_DDR4_R_ODT0_2X2) "off off"
set ip_params(MEM_DDR4_R_ODT1_2X2) "off off"
set ip_params(MEM_DDR4_W_ODTN_2X2) "{Rank 0} {Rank 1}"
set ip_params(MEM_DDR4_W_ODT0_2X2) "on off"
set ip_params(MEM_DDR4_W_ODT1_2X2) "off on"
set ip_params(MEM_DDR4_R_ODTN_4X2) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_DDR4_R_ODT0_4X2) "off off on on"
set ip_params(MEM_DDR4_R_ODT1_4X2) "on on off off"
set ip_params(MEM_DDR4_W_ODTN_4X2) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_DDR4_W_ODT0_4X2) "off off on on"
set ip_params(MEM_DDR4_W_ODT1_4X2) "on on off off"
set ip_params(MEM_DDR4_R_ODTN_4X4) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_DDR4_R_ODT0_4X4) "off off on off"
set ip_params(MEM_DDR4_R_ODT1_4X4) "off off off on"
set ip_params(MEM_DDR4_R_ODT2_4X4) "on off off off"
set ip_params(MEM_DDR4_R_ODT3_4X4) "off on off off"
set ip_params(MEM_DDR4_W_ODTN_4X4) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_DDR4_W_ODT0_4X4) "on off on off"
set ip_params(MEM_DDR4_W_ODT1_4X4) "off on off on"
set ip_params(MEM_DDR4_W_ODT2_4X4) "on off on off"
set ip_params(MEM_DDR4_W_ODT3_4X4) "off on off on"
set ip_params(MEM_DDR4_R_DERIVED_ODTN) "{} {} {}"
set ip_params(MEM_DDR4_R_DERIVED_ODT0) "{} {} {}"
set ip_params(MEM_DDR4_R_DERIVED_ODT1) "{} {} {}"
set ip_params(MEM_DDR4_R_DERIVED_ODT2) "{} {} {}"
set ip_params(MEM_DDR4_R_DERIVED_ODT3) "{} {} {}"
set ip_params(MEM_DDR4_R_DERIVED_BODTN) ""
set ip_params(MEM_DDR4_R_DERIVED_BODT0) ""
set ip_params(MEM_DDR4_R_DERIVED_BODT1) ""
set ip_params(MEM_DDR4_W_DERIVED_ODTN) "{} {} {}"
set ip_params(MEM_DDR4_W_DERIVED_ODT0) "{} {} {}"
set ip_params(MEM_DDR4_W_DERIVED_ODT1) "{} {} {}"
set ip_params(MEM_DDR4_W_DERIVED_ODT2) "{} {} {}"
set ip_params(MEM_DDR4_W_DERIVED_ODT3) "{} {} {}"
set ip_params(MEM_DDR4_W_DERIVED_BODTN) ""
set ip_params(MEM_DDR4_W_DERIVED_BODT0) ""
set ip_params(MEM_DDR4_W_DERIVED_BODT1) ""
set ip_params(MEM_DDR4_SEQ_ODT_TABLE_LO) "0"
set ip_params(MEM_DDR4_SEQ_ODT_TABLE_HI) "0"
set ip_params(MEM_DDR4_CTRL_CFG_READ_ODT_CHIP) "0"
set ip_params(MEM_DDR4_CTRL_CFG_WRITE_ODT_CHIP) "0"
set ip_params(MEM_DDR4_CTRL_CFG_READ_ODT_RANK) "0"
set ip_params(MEM_DDR4_CTRL_CFG_WRITE_ODT_RANK) "0"
set ip_params(MEM_DDR4_SPEEDBIN_ENUM) "DDR4_SPEEDBIN_2400"
set ip_params(MEM_DDR4_TIS_PS) "60"
set ip_params(MEM_DDR4_TIS_AC_MV) "100"
set ip_params(MEM_DDR4_TIH_PS) "95"
set ip_params(MEM_DDR4_TIH_DC_MV) "75"
set ip_params(MEM_DDR4_TDIVW_TOTAL_UI) "0.2"
set ip_params(MEM_DDR4_VDIVW_TOTAL) "136"
set ip_params(MEM_DDR4_TDQSQ_UI) "0.16"
set ip_params(MEM_DDR4_TQH_UI) "0.76"
set ip_params(MEM_DDR4_TDVWP_UI) "0.72"
set ip_params(MEM_DDR4_TDQSCK_PS) "165"
set ip_params(MEM_DDR4_TDQSS_CYC) "0.27"
set ip_params(MEM_DDR4_TQSH_CYC) "0.38"
set ip_params(MEM_DDR4_TDSH_CYC) "0.18"
set ip_params(MEM_DDR4_TDSS_CYC) "0.18"
set ip_params(MEM_DDR4_TWLS_CYC) "0.13"
set ip_params(MEM_DDR4_TWLH_CYC) "0.13"
set ip_params(MEM_DDR4_TINIT_US) "500"
set ip_params(MEM_DDR4_TMRD_CK_CYC) "8"
set ip_params(MEM_DDR4_TRAS_NS) "32.0"
set ip_params(MEM_DDR4_TRCD_NS) "15.0"
set ip_params(MEM_DDR4_TRP_NS) "15.0"
set ip_params(MEM_DDR4_TREFI_US) "7.8"
set ip_params(MEM_DDR4_TRFC_NS) "260.0"
set ip_params(MEM_DDR4_TWR_NS) "15.0"
set ip_params(MEM_DDR4_TWTR_L_CYC) "9"
set ip_params(MEM_DDR4_TWTR_S_CYC) "3"
set ip_params(MEM_DDR4_TFAW_NS) "21.0"
set ip_params(MEM_DDR4_TRRD_L_CYC) "6"
set ip_params(MEM_DDR4_TRRD_S_CYC) "4"
set ip_params(MEM_DDR4_TCCD_L_CYC) "6"
set ip_params(MEM_DDR4_TCCD_S_CYC) "4"
set ip_params(MEM_DDR4_TRFC_DLR_NS) "90.0"
set ip_params(MEM_DDR4_TFAW_DLR_CYC) "16"
set ip_params(MEM_DDR4_TRRD_DLR_CYC) "4"
set ip_params(MEM_DDR4_TDIVW_DJ_CYC) "0.1"
set ip_params(MEM_DDR4_TDQSQ_PS) "66"
set ip_params(MEM_DDR4_TQH_CYC) "0.38"
set ip_params(MEM_DDR4_TINIT_CK) "499"
set ip_params(MEM_DDR4_TDQSCK_DERV_PS) "2"
set ip_params(MEM_DDR4_TDQSCKDS) "450"
set ip_params(MEM_DDR4_TDQSCKDM) "900"
set ip_params(MEM_DDR4_TDQSCKDL) "1200"
set ip_params(MEM_DDR4_TRAS_CYC) "36"
set ip_params(MEM_DDR4_TRCD_CYC) "14"
set ip_params(MEM_DDR4_TRP_CYC) "14"
set ip_params(MEM_DDR4_TRFC_CYC) "171"
set ip_params(MEM_DDR4_TWR_CYC) "18"
set ip_params(MEM_DDR4_TRTP_CYC) "9"
set ip_params(MEM_DDR4_TFAW_CYC) "27"
set ip_params(MEM_DDR4_TREFI_CYC) "8320"
set ip_params(MEM_DDR4_WRITE_CMD_LATENCY) "5"
set ip_params(MEM_DDR4_TRFC_DLR_CYC) "109"
set ip_params(MEM_DDR4_CFG_GEN_SBE) "false"
set ip_params(MEM_DDR4_CFG_GEN_DBE) "false"
set ip_params(MEM_DDR4_LRDIMM_VREFDQ_VALUE) ""
set ip_params(MEM_DDR4_TWLS_PS) "0.0"
set ip_params(MEM_DDR4_TWLH_PS) "0.0"
set ip_params(MEM_QDR2_WIDTH_EXPANDED) "false"
set ip_params(MEM_QDR2_DATA_PER_DEVICE) "36"
set ip_params(MEM_QDR2_ADDR_WIDTH) "19"
set ip_params(MEM_QDR2_BWS_EN) "true"
set ip_params(MEM_QDR2_BL) "4"
set ip_params(MEM_QDR2_FORMAT_ENUM) "MEM_FORMAT_DISCRETE"
set ip_params(MEM_QDR2_DEVICE_WIDTH) "1"
set ip_params(MEM_QDR2_DATA_WIDTH) "36"
set ip_params(MEM_QDR2_BWS_N_WIDTH) "4"
set ip_params(MEM_QDR2_BWS_N_PER_DEVICE) "4"
set ip_params(MEM_QDR2_CQ_WIDTH) "1"
set ip_params(MEM_QDR2_K_WIDTH) "1"
set ip_params(MEM_QDR2_TWL_CYC) "1"
set ip_params(MEM_QDR2_SPEEDBIN_ENUM) "QDR2_SPEEDBIN_633"
set ip_params(MEM_QDR2_TRL_CYC) "2.5"
set ip_params(MEM_QDR2_TSA_NS) "0.23"
set ip_params(MEM_QDR2_THA_NS) "0.18"
set ip_params(MEM_QDR2_TSD_NS) "0.23"
set ip_params(MEM_QDR2_THD_NS) "0.18"
set ip_params(MEM_QDR2_TCQD_NS) "0.09"
set ip_params(MEM_QDR2_TCQDOH_NS) "-0.09"
set ip_params(MEM_QDR2_INTERNAL_JITTER_NS) "0.08"
set ip_params(MEM_QDR2_TCQH_NS) "0.71"
set ip_params(MEM_QDR2_TCCQO_NS) "0.45"
set ip_params(MEM_QDR4_WIDTH_EXPANDED) "false"
set ip_params(MEM_QDR4_DQ_PER_PORT_PER_DEVICE) "36"
set ip_params(MEM_QDR4_ADDR_WIDTH) "21"
set ip_params(MEM_QDR4_SKIP_ODT_SWEEPING) "true"
set ip_params(MEM_QDR4_CK_ODT_MODE_ENUM) "QDR4_ODT_25_PCT"
set ip_params(MEM_QDR4_AC_ODT_MODE_ENUM) "QDR4_ODT_25_PCT"
set ip_params(MEM_QDR4_DATA_ODT_MODE_ENUM) "QDR4_ODT_25_PCT"
set ip_params(MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM) "QDR4_OUTPUT_DRIVE_25_PCT"
set ip_params(MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM) "QDR4_OUTPUT_DRIVE_25_PCT"
set ip_params(MEM_QDR4_MEM_TYPE_ENUM) "MEM_XP"
set ip_params(MEM_QDR4_DATA_INV_ENA) "true"
set ip_params(MEM_QDR4_ADDR_INV_ENA) "false"
set ip_params(MEM_QDR4_USE_ADDR_PARITY) "false"
set ip_params(MEM_QDR4_FORMAT_ENUM) "MEM_FORMAT_DISCRETE"
set ip_params(MEM_QDR4_DEVICE_WIDTH) "1"
set ip_params(MEM_QDR4_DEVICE_DEPTH) "1"
set ip_params(MEM_QDR4_DQ_PER_RD_GROUP) "18"
set ip_params(MEM_QDR4_DQ_PER_WR_GROUP) "18"
set ip_params(MEM_QDR4_DQ_WIDTH) "72"
set ip_params(MEM_QDR4_QK_WIDTH) "4"
set ip_params(MEM_QDR4_DK_WIDTH) "4"
set ip_params(MEM_QDR4_DINV_WIDTH) "4"
set ip_params(MEM_QDR4_DQ_PER_PORT_WIDTH) "36"
set ip_params(MEM_QDR4_QK_PER_PORT_WIDTH) "2"
set ip_params(MEM_QDR4_DK_PER_PORT_WIDTH) "2"
set ip_params(MEM_QDR4_DINV_PER_PORT_WIDTH) "2"
set ip_params(MEM_QDR4_BL) "2"
set ip_params(MEM_QDR4_TRL_CYC) "8"
set ip_params(MEM_QDR4_TWL_CYC) "5"
set ip_params(MEM_QDR4_AVL_CHNLS) "8"
set ip_params(MEM_QDR4_CR0) "0"
set ip_params(MEM_QDR4_CR1) "0"
set ip_params(MEM_QDR4_CR2) "0"
set ip_params(MEM_QDR4_SPEEDBIN_ENUM) "QDR4_SPEEDBIN_2133"
set ip_params(MEM_QDR4_TISH_PS) "150"
set ip_params(MEM_QDR4_TQKQ_MAX_PS) "75"
set ip_params(MEM_QDR4_TQH_CYC) "0.4"
set ip_params(MEM_QDR4_TCKDK_MAX_PS) "150"
set ip_params(MEM_QDR4_TCKDK_MIN_PS) "-150"
set ip_params(MEM_QDR4_TCKQK_MAX_PS) "225"
set ip_params(MEM_QDR4_TASH_PS) "170"
set ip_params(MEM_QDR4_TCSH_PS) "170"
set ip_params(MEM_RLD2_WIDTH_EXPANDED) "false"
set ip_params(MEM_RLD2_DQ_PER_DEVICE) "9"
set ip_params(MEM_RLD2_ADDR_WIDTH) "21"
set ip_params(MEM_RLD2_BANK_ADDR_WIDTH) "3"
set ip_params(MEM_RLD2_DM_EN) "true"
set ip_params(MEM_RLD2_BL) "4"
set ip_params(MEM_RLD2_CONFIG_ENUM) "RLD2_CONFIG_TRC_8_TRL_8_TWL_9"
set ip_params(MEM_RLD2_DRIVE_IMPEDENCE_ENUM) "RLD2_DRIVE_IMPEDENCE_INTERNAL_50"
set ip_params(MEM_RLD2_ODT_MODE_ENUM) "RLD2_ODT_ON"
set ip_params(MEM_RLD2_FORMAT_ENUM) "MEM_FORMAT_DISCRETE"
set ip_params(MEM_RLD2_DEVICE_WIDTH) "1"
set ip_params(MEM_RLD2_DEVICE_DEPTH) "1"
set ip_params(MEM_RLD2_DQ_WIDTH) "9"
set ip_params(MEM_RLD2_DQ_PER_RD_GROUP) "9"
set ip_params(MEM_RLD2_DQ_PER_WR_GROUP) "9"
set ip_params(MEM_RLD2_QK_WIDTH) "1"
set ip_params(MEM_RLD2_DK_WIDTH) "1"
set ip_params(MEM_RLD2_DM_WIDTH) "1"
set ip_params(MEM_RLD2_CS_WIDTH) "1"
set ip_params(MEM_RLD2_TRC) "8"
set ip_params(MEM_RLD2_TRL) "8"
set ip_params(MEM_RLD2_TWL) "9"
set ip_params(MEM_RLD2_MR) "0"
set ip_params(MEM_RLD2_SPEEDBIN_ENUM) "RLD2_SPEEDBIN_18"
set ip_params(MEM_RLD2_REFRESH_INTERVAL_US) "0.24"
set ip_params(MEM_RLD2_TCKH_CYC) "0.45"
set ip_params(MEM_RLD2_TQKH_HCYC) "0.9"
set ip_params(MEM_RLD2_TAS_NS) "0.3"
set ip_params(MEM_RLD2_TAH_NS) "0.3"
set ip_params(MEM_RLD2_TDS_NS) "0.17"
set ip_params(MEM_RLD2_TDH_NS) "0.17"
set ip_params(MEM_RLD2_TQKQ_MAX_NS) "0.12"
set ip_params(MEM_RLD2_TQKQ_MIN_NS) "-0.12"
set ip_params(MEM_RLD2_TCKDK_MAX_NS) "0.3"
set ip_params(MEM_RLD2_TCKDK_MIN_NS) "-0.3"
set ip_params(MEM_RLD2_TCKQK_MAX_NS) "0.2"
set ip_params(MEM_RLD3_WIDTH_EXPANDED) "false"
set ip_params(MEM_RLD3_DEPTH_EXPANDED) "false"
set ip_params(MEM_RLD3_DQ_PER_DEVICE) "36"
set ip_params(MEM_RLD3_ADDR_WIDTH) "20"
set ip_params(MEM_RLD3_BANK_ADDR_WIDTH) "4"
set ip_params(MEM_RLD3_DM_EN) "true"
set ip_params(MEM_RLD3_BL) "2"
set ip_params(MEM_RLD3_DATA_LATENCY_MODE_ENUM) "RLD3_DL_RL16_WL17"
set ip_params(MEM_RLD3_T_RC_MODE_ENUM) "RLD3_TRC_9"
set ip_params(MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM) "RLD3_OUTPUT_DRIVE_40"
set ip_params(MEM_RLD3_ODT_MODE_ENUM) "RLD3_ODT_40"
set ip_params(MEM_RLD3_AREF_PROTOCOL_ENUM) "RLD3_AREF_BAC"
set ip_params(MEM_RLD3_WRITE_PROTOCOL_ENUM) "RLD3_WRITE_1BANK"
set ip_params(MEM_RLD3_FORMAT_ENUM) "MEM_FORMAT_DISCRETE"
set ip_params(MEM_RLD3_DEVICE_WIDTH) "1"
set ip_params(MEM_RLD3_DEVICE_DEPTH) "1"
set ip_params(MEM_RLD3_DQ_WIDTH) "36"
set ip_params(MEM_RLD3_DQ_PER_RD_GROUP) "9"
set ip_params(MEM_RLD3_DQ_PER_WR_GROUP) "18"
set ip_params(MEM_RLD3_QK_WIDTH) "4"
set ip_params(MEM_RLD3_DK_WIDTH) "2"
set ip_params(MEM_RLD3_DM_WIDTH) "2"
set ip_params(MEM_RLD3_CS_WIDTH) "1"
set ip_params(MEM_RLD3_MR0) "0"
set ip_params(MEM_RLD3_MR1) "0"
set ip_params(MEM_RLD3_MR2) "0"
set ip_params(MEM_RLD3_SPEEDBIN_ENUM) "RLD3_SPEEDBIN_093E"
set ip_params(MEM_RLD3_TDS_PS) "-30"
set ip_params(MEM_RLD3_TDS_AC_MV) "150"
set ip_params(MEM_RLD3_TDH_PS) "5"
set ip_params(MEM_RLD3_TDH_DC_MV) "100"
set ip_params(MEM_RLD3_TQKQ_MAX_PS) "75"
set ip_params(MEM_RLD3_TQH_CYC) "0.38"
set ip_params(MEM_RLD3_TCKDK_MAX_CYC) "0.27"
set ip_params(MEM_RLD3_TCKDK_MIN_CYC) "-0.27"
set ip_params(MEM_RLD3_TCKQK_MAX_PS) "135"
set ip_params(MEM_RLD3_TIS_PS) "85"
set ip_params(MEM_RLD3_TIS_AC_MV) "150"
set ip_params(MEM_RLD3_TIH_PS) "65"
set ip_params(MEM_RLD3_TIH_DC_MV) "100"
set ip_params(MEM_LPDDR3_DQ_WIDTH) "32"
set ip_params(MEM_LPDDR3_DISCRETE_CS_WIDTH) "1"
set ip_params(MEM_LPDDR3_CK_WIDTH) "1"
set ip_params(MEM_LPDDR3_DM_EN) "true"
set ip_params(MEM_LPDDR3_ROW_ADDR_WIDTH) "15"
set ip_params(MEM_LPDDR3_COL_ADDR_WIDTH) "10"
set ip_params(MEM_LPDDR3_BANK_ADDR_WIDTH) "3"
set ip_params(MEM_LPDDR3_DQS_WIDTH) "4"
set ip_params(MEM_LPDDR3_DM_WIDTH) "4"
set ip_params(MEM_LPDDR3_CS_WIDTH) "1"
set ip_params(MEM_LPDDR3_CKE_WIDTH) "1"
set ip_params(MEM_LPDDR3_ODT_WIDTH) "1"
set ip_params(MEM_LPDDR3_ADDR_WIDTH) "10"
set ip_params(MEM_LPDDR3_DQ_PER_DQS) "8"
set ip_params(MEM_LPDDR3_FORMAT_ENUM) "MEM_FORMAT_DISCRETE"
set ip_params(MEM_LPDDR3_MR1) "536592"
set ip_params(MEM_LPDDR3_MR2) "106528"
set ip_params(MEM_LPDDR3_MR3) "8240"
set ip_params(MEM_LPDDR3_MR11) "176"
set ip_params(MEM_LPDDR3_BL) "LPDDR3_BL_BL8"
set ip_params(MEM_LPDDR3_DATA_LATENCY) "LPDDR3_DL_RL12_WL6"
set ip_params(MEM_LPDDR3_DRV_STR) "LPDDR3_DRV_STR_40D_40U"
set ip_params(MEM_LPDDR3_DQODT) "LPDDR3_DQODT_DISABLE"
set ip_params(MEM_LPDDR3_PDODT) "LPDDR3_PDODT_DISABLED"
set ip_params(MEM_LPDDR3_WLSELECT) "Set A"
set ip_params(MEM_LPDDR3_NWR) "LPDDR3_NWR_NWR12"
set ip_params(MEM_LPDDR3_NUM_OF_LOGICAL_RANKS) "1"
set ip_params(MEM_LPDDR3_NUM_OF_PHYSICAL_RANKS) "1"
set ip_params(MEM_LPDDR3_USE_DEFAULT_ODT) "true"
set ip_params(MEM_LPDDR3_R_ODTN_1X1) "{Rank 0}"
set ip_params(MEM_LPDDR3_R_ODT0_1X1) "off"
set ip_params(MEM_LPDDR3_W_ODTN_1X1) "{Rank 0}"
set ip_params(MEM_LPDDR3_W_ODT0_1X1) "on"
set ip_params(MEM_LPDDR3_R_ODTN_2X2) "{Rank 0} {Rank 1}"
set ip_params(MEM_LPDDR3_R_ODT0_2X2) "off off"
set ip_params(MEM_LPDDR3_R_ODT1_2X2) "off off"
set ip_params(MEM_LPDDR3_W_ODTN_2X2) "{Rank 0} {Rank 1}"
set ip_params(MEM_LPDDR3_W_ODT0_2X2) "on on"
set ip_params(MEM_LPDDR3_W_ODT1_2X2) "off off"
set ip_params(MEM_LPDDR3_R_ODTN_4X4) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_LPDDR3_R_ODT0_4X4) "off off off off"
set ip_params(MEM_LPDDR3_R_ODT1_4X4) "off off off off"
set ip_params(MEM_LPDDR3_R_ODT2_4X4) "off off off off"
set ip_params(MEM_LPDDR3_R_ODT3_4X4) "off off off off"
set ip_params(MEM_LPDDR3_W_ODTN_4X4) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_LPDDR3_W_ODT0_4X4) "on on on on"
set ip_params(MEM_LPDDR3_W_ODT1_4X4) "off off off off"
set ip_params(MEM_LPDDR3_W_ODT2_4X4) "off off off off"
set ip_params(MEM_LPDDR3_W_ODT3_4X4) "off off off off"
set ip_params(MEM_LPDDR3_R_DERIVED_ODTN) "{Rank 0} - - -"
set ip_params(MEM_LPDDR3_R_DERIVED_ODT0) "{(Drive) 40 ohm pull-down/pull-up} - - -"
set ip_params(MEM_LPDDR3_R_DERIVED_ODT1) "- - - -"
set ip_params(MEM_LPDDR3_R_DERIVED_ODT2) "- - - -"
set ip_params(MEM_LPDDR3_R_DERIVED_ODT3) "- - - -"
set ip_params(MEM_LPDDR3_W_DERIVED_ODTN) "{Rank 0} - - -"
set ip_params(MEM_LPDDR3_W_DERIVED_ODT0) "Disabled - - -"
set ip_params(MEM_LPDDR3_W_DERIVED_ODT1) "- - - -"
set ip_params(MEM_LPDDR3_W_DERIVED_ODT2) "- - - -"
set ip_params(MEM_LPDDR3_W_DERIVED_ODT3) "- - - -"
set ip_params(MEM_LPDDR3_SEQ_ODT_TABLE_LO) "4"
set ip_params(MEM_LPDDR3_SEQ_ODT_TABLE_HI) "0"
set ip_params(MEM_LPDDR3_CTRL_CFG_READ_ODT_CHIP) "0"
set ip_params(MEM_LPDDR3_CTRL_CFG_WRITE_ODT_CHIP) "0"
set ip_params(MEM_LPDDR3_CTRL_CFG_READ_ODT_RANK) "0"
set ip_params(MEM_LPDDR3_CTRL_CFG_WRITE_ODT_RANK) "0"
set ip_params(MEM_LPDDR3_SPEEDBIN_ENUM) "LPDDR3_SPEEDBIN_1600"
set ip_params(MEM_LPDDR3_TIS_PS) "75"
set ip_params(MEM_LPDDR3_TIS_AC_MV) "150"
set ip_params(MEM_LPDDR3_TIH_PS) "100"
set ip_params(MEM_LPDDR3_TIH_DC_MV) "100"
set ip_params(MEM_LPDDR3_TDS_PS) "75"
set ip_params(MEM_LPDDR3_TDS_AC_MV) "150"
set ip_params(MEM_LPDDR3_TDH_PS) "100"
set ip_params(MEM_LPDDR3_TDH_DC_MV) "100"
set ip_params(MEM_LPDDR3_TDQSQ_PS) "135"
set ip_params(MEM_LPDDR3_TQH_CYC) "0.38"
set ip_params(MEM_LPDDR3_TDQSCKDL) "614"
set ip_params(MEM_LPDDR3_TDQSS_CYC) "1.25"
set ip_params(MEM_LPDDR3_TQSH_CYC) "0.38"
set ip_params(MEM_LPDDR3_TDSH_CYC) "0.2"
set ip_params(MEM_LPDDR3_TWLS_PS) "175.0"
set ip_params(MEM_LPDDR3_TWLH_PS) "175.0"
set ip_params(MEM_LPDDR3_TDSS_CYC) "0.2"
set ip_params(MEM_LPDDR3_TINIT_US) "500"
set ip_params(MEM_LPDDR3_TMRR_CK_CYC) "4"
set ip_params(MEM_LPDDR3_TMRW_CK_CYC) "10"
set ip_params(MEM_LPDDR3_TRAS_NS) "42.0"
set ip_params(MEM_LPDDR3_TRCD_NS) "18.0"
set ip_params(MEM_LPDDR3_TRP_NS) "18.0"
set ip_params(MEM_LPDDR3_TREFI_US) "3.9"
set ip_params(MEM_LPDDR3_TRFC_NS) "210.0"
set ip_params(MEM_LPDDR3_TWR_NS) "15.0"
set ip_params(MEM_LPDDR3_TWTR_CYC) "6"
set ip_params(MEM_LPDDR3_TFAW_NS) "50.0"
set ip_params(MEM_LPDDR3_TRRD_CYC) "8"
set ip_params(MEM_LPDDR3_TRTP_CYC) "6"
set ip_params(MEM_LPDDR3_TINIT_CK) "400000"
set ip_params(MEM_LPDDR3_TDQSCK_DERV_PS) "2"
set ip_params(MEM_LPDDR3_TDQSCKDS) "220"
set ip_params(MEM_LPDDR3_TDQSCKDM) "511"
set ip_params(MEM_LPDDR3_TDQSCK_PS) "5500"
set ip_params(MEM_LPDDR3_TRAS_CYC) "34"
set ip_params(MEM_LPDDR3_TRCD_CYC) "15"
set ip_params(MEM_LPDDR3_TRP_CYC) "15"
set ip_params(MEM_LPDDR3_TRFC_CYC) "168"
set ip_params(MEM_LPDDR3_TWR_CYC) "12"
set ip_params(MEM_LPDDR3_TFAW_CYC) "40"
set ip_params(MEM_LPDDR3_TREFI_CYC) "3120"
set ip_params(MEM_LPDDR3_TRL_CYC) "10"
set ip_params(MEM_LPDDR3_TWL_CYC) "6"
set ip_params(MEM_DDRT_FORMAT_ENUM) "MEM_FORMAT_LRDIMM"
set ip_params(MEM_DDRT_DQ_WIDTH) "72"
set ip_params(MEM_DDRT_DQ_PER_DQS) "4"
set ip_params(MEM_DDRT_DISCRETE_CS_WIDTH) "1"
set ip_params(MEM_DDRT_NUM_OF_DIMMS) "1"
set ip_params(MEM_DDRT_RANKS_PER_DIMM) "1"
set ip_params(MEM_DDRT_CKE_PER_DIMM) "1"
set ip_params(MEM_DDRT_ROW_ADDR_WIDTH) "18"
set ip_params(MEM_DDRT_COL_ADDR_WIDTH) "10"
set ip_params(MEM_DDRT_BANK_ADDR_WIDTH) "2"
set ip_params(MEM_DDRT_BANK_GROUP_WIDTH) "2"
set ip_params(MEM_DDRT_DM_EN) "false"
set ip_params(MEM_DDRT_ALERT_PAR_EN) "true"
set ip_params(MEM_DDRT_ALERT_N_PLACEMENT_ENUM) "DDRT_ALERT_N_PLACEMENT_AUTO"
set ip_params(MEM_DDRT_ALERT_N_DQS_GROUP) "0"
set ip_params(MEM_DDRT_ALERT_N_AC_LANE) "0"
set ip_params(MEM_DDRT_ALERT_N_AC_PIN) "0"
set ip_params(MEM_DDRT_DISCRETE_MIRROR_ADDRESSING_EN) "false"
set ip_params(MEM_DDRT_MIRROR_ADDRESSING_EN) "true"
set ip_params(MEM_DDRT_HIDE_ADV_MR_SETTINGS) "true"
set ip_params(MEM_DDRT_HIDE_LATENCY_SETTINGS) "true"
set ip_params(MEM_DDRT_PWR_MODE) "DDRT_PWR_MODE_12W"
set ip_params(MEM_DDRT_BL_ENUM) "DDRT_BL_BL8"
set ip_params(MEM_DDRT_BT_ENUM) "DDRT_BT_SEQUENTIAL"
set ip_params(MEM_DDRT_TCL) "15"
set ip_params(MEM_DDRT_RTT_NOM_ENUM) "DDRT_RTT_NOM_RZQ_4"
set ip_params(MEM_DDRT_DLL_EN) "true"
set ip_params(MEM_DDRT_ATCL_ENUM) "DDRT_ATCL_DISABLED"
set ip_params(MEM_DDRT_DRV_STR_ENUM) "DDRT_DRV_STR_RZQ_7"
set ip_params(MEM_DDRT_ASR_ENUM) "DDRT_ASR_MANUAL_NORMAL"
set ip_params(MEM_DDRT_RTT_WR_ENUM) "DDRT_RTT_WR_ODT_DISABLED"
set ip_params(MEM_DDRT_WTCL) "18"
set ip_params(MEM_DDRT_WRITE_CRC) "false"
set ip_params(MEM_DDRT_GEARDOWN) "DDRT_GEARDOWN_HR"
set ip_params(MEM_DDRT_PER_DRAM_ADDR) "false"
set ip_params(MEM_DDRT_TEMP_SENSOR_READOUT) "false"
set ip_params(MEM_DDRT_FINE_GRANULARITY_REFRESH) "DDRT_FINE_REFRESH_FIXED_1X"
set ip_params(MEM_DDRT_MPR_READ_FORMAT) "DDRT_MPR_READ_FORMAT_SERIAL"
set ip_params(MEM_DDRT_MAX_POWERDOWN) "false"
set ip_params(MEM_DDRT_TEMP_CONTROLLED_RFSH_RANGE) "DDRT_TEMP_CONTROLLED_RFSH_NORMAL"
set ip_params(MEM_DDRT_TEMP_CONTROLLED_RFSH_ENA) "false"
set ip_params(MEM_DDRT_INTERNAL_VREFDQ_MONITOR) "false"
set ip_params(MEM_DDRT_CAL_MODE) "0"
set ip_params(MEM_DDRT_SELF_RFSH_ABORT) "false"
set ip_params(MEM_DDRT_READ_PREAMBLE_TRAINING) "false"
set ip_params(MEM_DDRT_DEFAULT_PREAMBLE) "true"
set ip_params(MEM_DDRT_USER_READ_PREAMBLE) "1"
set ip_params(MEM_DDRT_USER_WRITE_PREAMBLE) "1"
set ip_params(MEM_DDRT_AC_PARITY_LATENCY) "DDRT_AC_PARITY_LATENCY_DISABLE"
set ip_params(MEM_DDRT_ODT_IN_POWERDOWN) "true"
set ip_params(MEM_DDRT_RTT_PARK) "DDRT_RTT_PARK_ODT_DISABLED"
set ip_params(MEM_DDRT_AC_PERSISTENT_ERROR) "false"
set ip_params(MEM_DDRT_WRITE_DBI) "false"
set ip_params(MEM_DDRT_READ_DBI) "false"
set ip_params(MEM_DDRT_PARTIAL_WRITES) "false"
set ip_params(MEM_DDRT_DEFAULT_VREFOUT) "true"
set ip_params(MEM_DDRT_USER_VREFDQ_TRAINING_VALUE) "56.0"
set ip_params(MEM_DDRT_USER_VREFDQ_TRAINING_RANGE) "DDRT_VREFDQ_TRAINING_RANGE_1"
set ip_params(MEM_DDRT_DEFAULT_ADDED_LATENCY) "true"
set ip_params(MEM_DDRT_USER_TCL_ADDED) "0"
set ip_params(MEM_DDRT_USER_WTCL_ADDED) "6"
set ip_params(MEM_DDRT_RCD_CA_IBT_ENUM) "DDRT_RCD_CA_IBT_100"
set ip_params(MEM_DDRT_RCD_CS_IBT_ENUM) "DDRT_RCD_CS_IBT_100"
set ip_params(MEM_DDRT_RCD_CKE_IBT_ENUM) "DDRT_RCD_CKE_IBT_100"
set ip_params(MEM_DDRT_RCD_ODT_IBT_ENUM) "DDRT_RCD_ODT_IBT_100"
set ip_params(MEM_DDRT_DB_RTT_NOM_ENUM) "DDRT_DB_RTT_NOM_ODT_DISABLED"
set ip_params(MEM_DDRT_DB_RTT_WR_ENUM) "DDRT_DB_RTT_WR_RZQ_4"
set ip_params(MEM_DDRT_DB_RTT_PARK_ENUM) "DDRT_DB_RTT_PARK_ODT_DISABLED"
set ip_params(MEM_DDRT_DB_DQ_DRV_ENUM) "DDRT_DB_DRV_STR_RZQ_7"
set ip_params(MEM_DDRT_SPD_137_RCD_CA_DRV) "85"
set ip_params(MEM_DDRT_SPD_138_RCD_CK_DRV) "5"
set ip_params(MEM_DDRT_SPD_140_DRAM_VREFDQ_R0) "29"
set ip_params(MEM_DDRT_SPD_141_DRAM_VREFDQ_R1) "29"
set ip_params(MEM_DDRT_SPD_142_DRAM_VREFDQ_R2) "29"
set ip_params(MEM_DDRT_SPD_143_DRAM_VREFDQ_R3) "29"
set ip_params(MEM_DDRT_SPD_144_DB_VREFDQ) "25"
set ip_params(MEM_DDRT_SPD_145_DB_MDQ_DRV) "21"
set ip_params(MEM_DDRT_SPD_148_DRAM_DRV) "0"
set ip_params(MEM_DDRT_SPD_149_DRAM_RTT_WR_NOM) "20"
set ip_params(MEM_DDRT_SPD_152_DRAM_RTT_PARK) "39"
set ip_params(MEM_DDRT_SPD_133_RCD_DB_VENDOR_LSB) "0"
set ip_params(MEM_DDRT_SPD_134_RCD_DB_VENDOR_MSB) "0"
set ip_params(MEM_DDRT_SPD_135_RCD_REV) "0"
set ip_params(MEM_DDRT_SPD_139_DB_REV) "0"
set ip_params(MEM_DDRT_LRDIMM_ODT_LESS_BS) "false"
set ip_params(MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM) "240"
set ip_params(MEM_DDRT_I2C_DIMM_0_SA) "0"
set ip_params(MEM_DDRT_I2C_DIMM_1_SA) "1"
set ip_params(MEM_DDRT_I2C_DIMM_2_SA) "2"
set ip_params(MEM_DDRT_I2C_DIMM_3_SA) "3"
set ip_params(MEM_DDRT_PERSISTENT_MODE) "1"
set ip_params(MEM_DDRT_DQS_WIDTH) "8"
set ip_params(MEM_DDRT_CS_WIDTH) "1"
set ip_params(MEM_DDRT_CS_PER_DIMM) "1"
set ip_params(MEM_DDRT_CKE_WIDTH) "1"
set ip_params(MEM_DDRT_GNT_N_WIDTH) "1"
set ip_params(MEM_DDRT_REQ_N_WIDTH) "1"
set ip_params(MEM_DDRT_ERR_N_WIDTH) "1"
set ip_params(MEM_DDRT_ERID_WIDTH) "2"
set ip_params(MEM_DDRT_ODT_WIDTH) "1"
set ip_params(MEM_DDRT_ADDR_WIDTH) "1"
set ip_params(MEM_DDRT_RM_WIDTH) "0"
set ip_params(MEM_DDRT_NUM_OF_PHYSICAL_RANKS) "1"
set ip_params(MEM_DDRT_NUM_OF_LOGICAL_RANKS) "1"
set ip_params(MEM_DDRT_CK_WIDTH) "1"
set ip_params(MEM_DDRT_READ_PREAMBLE) "1"
set ip_params(MEM_DDRT_WRITE_PREAMBLE) "1"
set ip_params(MEM_DDRT_VREFDQ_TRAINING_VALUE) "56.0"
set ip_params(MEM_DDRT_VREFDQ_TRAINING_RANGE) "DDRT_VREFDQ_TRAINING_RANGE_1"
set ip_params(MEM_DDRT_VREFDQ_TRAINING_RANGE_DISP) "Range 2 - 45% to 77.5%"
set ip_params(MEM_DDRT_CHIP_ID_WIDTH) "2"
set ip_params(MEM_DDRT_TCL_ADDED) "-1"
set ip_params(MEM_DDRT_WTCL_ADDED) "-1"
set ip_params(MEM_DDRT_TTL_DQS_WIDTH) "8"
set ip_params(MEM_DDRT_TTL_DQ_WIDTH) "72"
set ip_params(MEM_DDRT_TTL_CS_WIDTH) "1"
set ip_params(MEM_DDRT_TTL_CK_WIDTH) "1"
set ip_params(MEM_DDRT_TTL_CKE_WIDTH) "1"
set ip_params(MEM_DDRT_TTL_GNT_N_WIDTH) "1"
set ip_params(MEM_DDRT_TTL_REQ_N_WIDTH) "1"
set ip_params(MEM_DDRT_TTL_ERR_N_WIDTH) "1"
set ip_params(MEM_DDRT_TTL_ERID_WIDTH) "2"
set ip_params(MEM_DDRT_TTL_ODT_WIDTH) "1"
set ip_params(MEM_DDRT_TTL_BANK_ADDR_WIDTH) "2"
set ip_params(MEM_DDRT_TTL_BANK_GROUP_WIDTH) "2"
set ip_params(MEM_DDRT_TTL_CHIP_ID_WIDTH) "2"
set ip_params(MEM_DDRT_TTL_ADDR_WIDTH) "1"
set ip_params(MEM_DDRT_TTL_RM_WIDTH) "0"
set ip_params(MEM_DDRT_TTL_NUM_OF_DIMMS) "1"
set ip_params(MEM_DDRT_TTL_NUM_OF_PHYSICAL_RANKS) "1"
set ip_params(MEM_DDRT_TTL_NUM_OF_LOGICAL_RANKS) "1"
set ip_params(MEM_DDRT_MR0) "0"
set ip_params(MEM_DDRT_MR1) "0"
set ip_params(MEM_DDRT_MR2) "0"
set ip_params(MEM_DDRT_MR3) "0"
set ip_params(MEM_DDRT_MR4) "0"
set ip_params(MEM_DDRT_MR5) "0"
set ip_params(MEM_DDRT_MR6) "0"
set ip_params(MEM_DDRT_RDIMM_CONFIG) ""
set ip_params(MEM_DDRT_LRDIMM_EXTENDED_CONFIG) ""
set ip_params(MEM_DDRT_ADDRESS_MIRROR_BITVEC) "0"
set ip_params(MEM_DDRT_RCD_PARITY_CONTROL_WORD) "1"
set ip_params(MEM_DDRT_RCD_COMMAND_LATENCY) "1"
set ip_params(MEM_DDRT_USE_DEFAULT_ODT) "true"
set ip_params(MEM_DDRT_R_ODTN_1X1) "{Rank 0}"
set ip_params(MEM_DDRT_R_ODT0_1X1) "off"
set ip_params(MEM_DDRT_W_ODTN_1X1) "{Rank 0}"
set ip_params(MEM_DDRT_W_ODT0_1X1) "on"
set ip_params(MEM_DDRT_R_ODTN_2X2) "{Rank 0} {Rank 1}"
set ip_params(MEM_DDRT_R_ODT0_2X2) "off off"
set ip_params(MEM_DDRT_R_ODT1_2X2) "off off"
set ip_params(MEM_DDRT_W_ODTN_2X2) "{Rank 0} {Rank 1}"
set ip_params(MEM_DDRT_W_ODT0_2X2) "on off"
set ip_params(MEM_DDRT_W_ODT1_2X2) "off on"
set ip_params(MEM_DDRT_R_ODTN_4X2) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_DDRT_R_ODT0_4X2) "off off on on"
set ip_params(MEM_DDRT_R_ODT1_4X2) "on on off off"
set ip_params(MEM_DDRT_W_ODTN_4X2) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_DDRT_W_ODT0_4X2) "off off on on"
set ip_params(MEM_DDRT_W_ODT1_4X2) "on on off off"
set ip_params(MEM_DDRT_R_ODTN_4X4) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_DDRT_R_ODT0_4X4) "off off off off"
set ip_params(MEM_DDRT_R_ODT1_4X4) "off off on on"
set ip_params(MEM_DDRT_R_ODT2_4X4) "off off off off"
set ip_params(MEM_DDRT_R_ODT3_4X4) "on on off off"
set ip_params(MEM_DDRT_W_ODTN_4X4) "{Rank 0} {Rank 1} {Rank 2} {Rank 3}"
set ip_params(MEM_DDRT_W_ODT0_4X4) "on on off off"
set ip_params(MEM_DDRT_W_ODT1_4X4) "off off on on"
set ip_params(MEM_DDRT_W_ODT2_4X4) "off off on on"
set ip_params(MEM_DDRT_W_ODT3_4X4) "on on off off"
set ip_params(MEM_DDRT_R_DERIVED_ODTN) "{} {} {}"
set ip_params(MEM_DDRT_R_DERIVED_ODT0) "{} {} {}"
set ip_params(MEM_DDRT_R_DERIVED_ODT1) "{} {} {}"
set ip_params(MEM_DDRT_R_DERIVED_ODT2) "{} {} {}"
set ip_params(MEM_DDRT_R_DERIVED_ODT3) "{} {} {}"
set ip_params(MEM_DDRT_R_DERIVED_BODTN) ""
set ip_params(MEM_DDRT_R_DERIVED_BODT0) ""
set ip_params(MEM_DDRT_R_DERIVED_BODT1) ""
set ip_params(MEM_DDRT_W_DERIVED_ODTN) "{} {} {}"
set ip_params(MEM_DDRT_W_DERIVED_ODT0) "{} {} {}"
set ip_params(MEM_DDRT_W_DERIVED_ODT1) "{} {} {}"
set ip_params(MEM_DDRT_W_DERIVED_ODT2) "{} {} {}"
set ip_params(MEM_DDRT_W_DERIVED_ODT3) "{} {} {}"
set ip_params(MEM_DDRT_W_DERIVED_BODTN) ""
set ip_params(MEM_DDRT_W_DERIVED_BODT0) ""
set ip_params(MEM_DDRT_W_DERIVED_BODT1) ""
set ip_params(MEM_DDRT_SEQ_ODT_TABLE_LO) "0"
set ip_params(MEM_DDRT_SEQ_ODT_TABLE_HI) "0"
set ip_params(MEM_DDRT_CTRL_CFG_READ_ODT_CHIP) "0"
set ip_params(MEM_DDRT_CTRL_CFG_WRITE_ODT_CHIP) "0"
set ip_params(MEM_DDRT_CTRL_CFG_READ_ODT_RANK) "0"
set ip_params(MEM_DDRT_CTRL_CFG_WRITE_ODT_RANK) "0"
set ip_params(MEM_DDRT_SPEEDBIN_ENUM) "DDRT_SPEEDBIN_2400"
set ip_params(MEM_DDRT_TIS_PS) "60"
set ip_params(MEM_DDRT_TIS_AC_MV) "100"
set ip_params(MEM_DDRT_TIH_PS) "95"
set ip_params(MEM_DDRT_TIH_DC_MV) "75"
set ip_params(MEM_DDRT_TDIVW_TOTAL_UI) "0.2"
set ip_params(MEM_DDRT_VDIVW_TOTAL) "136"
set ip_params(MEM_DDRT_TDQSQ_UI) "0.16"
set ip_params(MEM_DDRT_TQH_UI) "0.76"
set ip_params(MEM_DDRT_TDVWP_UI) "0.72"
set ip_params(MEM_DDRT_TDQSCK_PS) "165"
set ip_params(MEM_DDRT_TDQSS_CYC) "0.27"
set ip_params(MEM_DDRT_TQSH_CYC) "0.38"
set ip_params(MEM_DDRT_TDSH_CYC) "0.18"
set ip_params(MEM_DDRT_TDSS_CYC) "0.18"
set ip_params(MEM_DDRT_TWLS_CYC) "0.13"
set ip_params(MEM_DDRT_TWLH_CYC) "0.13"
set ip_params(MEM_DDRT_TINIT_US) "500"
set ip_params(MEM_DDRT_TMRD_CK_CYC) "8"
set ip_params(MEM_DDRT_TRAS_NS) "32.0"
set ip_params(MEM_DDRT_TRCD_NS) "15.0"
set ip_params(MEM_DDRT_TRP_NS) "15.0"
set ip_params(MEM_DDRT_TREFI_US) "7.8"
set ip_params(MEM_DDRT_TRFC_NS) "260.0"
set ip_params(MEM_DDRT_TWR_NS) "15.0"
set ip_params(MEM_DDRT_TWTR_L_CYC) "9"
set ip_params(MEM_DDRT_TWTR_S_CYC) "3"
set ip_params(MEM_DDRT_TFAW_NS) "21.0"
set ip_params(MEM_DDRT_TRRD_L_CYC) "6"
set ip_params(MEM_DDRT_TRRD_S_CYC) "4"
set ip_params(MEM_DDRT_TCCD_L_CYC) "6"
set ip_params(MEM_DDRT_TCCD_S_CYC) "4"
set ip_params(MEM_DDRT_TRFC_DLR_NS) "90.0"
set ip_params(MEM_DDRT_TFAW_DLR_CYC) "16"
set ip_params(MEM_DDRT_TRRD_DLR_CYC) "4"
set ip_params(MEM_DDRT_TDIVW_DJ_CYC) "0.1"
set ip_params(MEM_DDRT_TDQSQ_PS) "66"
set ip_params(MEM_DDRT_TQH_CYC) "0.38"
set ip_params(MEM_DDRT_TINIT_CK) "499"
set ip_params(MEM_DDRT_TDQSCK_DERV_PS) "2"
set ip_params(MEM_DDRT_TDQSCKDS) "450"
set ip_params(MEM_DDRT_TDQSCKDM) "900"
set ip_params(MEM_DDRT_TDQSCKDL) "1200"
set ip_params(MEM_DDRT_TRAS_CYC) "36"
set ip_params(MEM_DDRT_TRCD_CYC) "14"
set ip_params(MEM_DDRT_TRP_CYC) "14"
set ip_params(MEM_DDRT_TRFC_CYC) "171"
set ip_params(MEM_DDRT_TWR_CYC) "18"
set ip_params(MEM_DDRT_TRTP_CYC) "9"
set ip_params(MEM_DDRT_TFAW_CYC) "27"
set ip_params(MEM_DDRT_TREFI_CYC) "8320"
set ip_params(MEM_DDRT_WRITE_CMD_LATENCY) "5"
set ip_params(MEM_DDRT_TRFC_DLR_CYC) "109"
set ip_params(MEM_DDRT_CFG_GEN_SBE) "false"
set ip_params(MEM_DDRT_CFG_GEN_DBE) "false"
set ip_params(MEM_DDRT_LRDIMM_VREFDQ_VALUE) ""
set ip_params(MEM_DDRT_TWLS_PS) "0.0"
set ip_params(MEM_DDRT_TWLH_PS) "0.0"
set ip_params(BOARD_DDR3_USE_DEFAULT_SLEW_RATES) "true"
set ip_params(BOARD_DDR3_USE_DEFAULT_ISI_VALUES) "true"
set ip_params(BOARD_DDR3_USER_CK_SLEW_RATE) "4.0"
set ip_params(BOARD_DDR3_USER_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_DDR3_USER_RCLK_SLEW_RATE) "5.0"
set ip_params(BOARD_DDR3_USER_WCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_DDR3_USER_RDATA_SLEW_RATE) "2.5"
set ip_params(BOARD_DDR3_USER_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_DDR3_USER_AC_ISI_NS) "0.0"
set ip_params(BOARD_DDR3_USER_RCLK_ISI_NS) "0.0"
set ip_params(BOARD_DDR3_USER_WCLK_ISI_NS) "0.0"
set ip_params(BOARD_DDR3_USER_RDATA_ISI_NS) "0.0"
set ip_params(BOARD_DDR3_USER_WDATA_ISI_NS) "0.0"
set ip_params(BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED) "false"
set ip_params(BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS) "0.02"
set ip_params(BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS) "0.02"
set ip_params(BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED) "true"
set ip_params(BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_DDR3_DQS_TO_CK_SKEW_NS) "0.02"
set ip_params(BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS) "0.05"
set ip_params(BOARD_DDR3_SKEW_BETWEEN_DQS_NS) "0.02"
set ip_params(BOARD_DDR3_AC_TO_CK_SKEW_NS) "0.0"
set ip_params(BOARD_DDR3_MAX_CK_DELAY_NS) "0.6"
set ip_params(BOARD_DDR3_MAX_DQS_DELAY_NS) "0.6"
set ip_params(BOARD_DDR3_TIS_DERATING_PS) "0"
set ip_params(BOARD_DDR3_TIH_DERATING_PS) "0"
set ip_params(BOARD_DDR3_TDS_DERATING_PS) "0"
set ip_params(BOARD_DDR3_TDH_DERATING_PS) "0"
set ip_params(BOARD_DDR3_CK_SLEW_RATE) "4.0"
set ip_params(BOARD_DDR3_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_DDR3_RCLK_SLEW_RATE) "5.0"
set ip_params(BOARD_DDR3_WCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_DDR3_RDATA_SLEW_RATE) "2.5"
set ip_params(BOARD_DDR3_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_DDR3_AC_ISI_NS) "0.0"
set ip_params(BOARD_DDR3_RCLK_ISI_NS) "0.0"
set ip_params(BOARD_DDR3_WCLK_ISI_NS) "0.0"
set ip_params(BOARD_DDR3_RDATA_ISI_NS) "0.0"
set ip_params(BOARD_DDR3_WDATA_ISI_NS) "0.0"
set ip_params(BOARD_DDR3_SKEW_WITHIN_DQS_NS) "0.0"
set ip_params(BOARD_DDR3_SKEW_WITHIN_AC_NS) "0.0"
set ip_params(BOARD_DDR4_USE_DEFAULT_SLEW_RATES) "true"
set ip_params(BOARD_DDR4_USE_DEFAULT_ISI_VALUES) "true"
set ip_params(BOARD_DDR4_USER_CK_SLEW_RATE) "4.0"
set ip_params(BOARD_DDR4_USER_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_DDR4_USER_RCLK_SLEW_RATE) "8.0"
set ip_params(BOARD_DDR4_USER_WCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_DDR4_USER_RDATA_SLEW_RATE) "4.0"
set ip_params(BOARD_DDR4_USER_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_DDR4_USER_AC_ISI_NS) "0.0"
set ip_params(BOARD_DDR4_USER_RCLK_ISI_NS) "0.0"
set ip_params(BOARD_DDR4_USER_WCLK_ISI_NS) "0.0"
set ip_params(BOARD_DDR4_USER_RDATA_ISI_NS) "0.0"
set ip_params(BOARD_DDR4_USER_WDATA_ISI_NS) "0.0"
set ip_params(BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED) "true"
set ip_params(BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS) "0.02"
set ip_params(BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS) "0.02"
set ip_params(BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED) "false"
set ip_params(BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_DDR4_DQS_TO_CK_SKEW_NS) "0.02"
set ip_params(BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS) "0.05"
set ip_params(BOARD_DDR4_SKEW_BETWEEN_DQS_NS) "0.02"
set ip_params(BOARD_DDR4_AC_TO_CK_SKEW_NS) "0.0"
set ip_params(BOARD_DDR4_MAX_CK_DELAY_NS) "0.6"
set ip_params(BOARD_DDR4_MAX_DQS_DELAY_NS) "0.6"
set ip_params(BOARD_DDR4_TIS_DERATING_PS) "0"
set ip_params(BOARD_DDR4_TIH_DERATING_PS) "0"
set ip_params(BOARD_DDR4_CK_SLEW_RATE) "4.0"
set ip_params(BOARD_DDR4_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_DDR4_RCLK_SLEW_RATE) "8.0"
set ip_params(BOARD_DDR4_WCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_DDR4_RDATA_SLEW_RATE) "4.0"
set ip_params(BOARD_DDR4_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_DDR4_AC_ISI_NS) "0.0"
set ip_params(BOARD_DDR4_RCLK_ISI_NS) "0.0"
set ip_params(BOARD_DDR4_WCLK_ISI_NS) "0.0"
set ip_params(BOARD_DDR4_RDATA_ISI_NS) "0.0"
set ip_params(BOARD_DDR4_WDATA_ISI_NS) "0.0"
set ip_params(BOARD_DDR4_SKEW_WITHIN_DQS_NS) "0.0"
set ip_params(BOARD_DDR4_SKEW_WITHIN_AC_NS) "0.0"
set ip_params(BOARD_QDR2_USE_DEFAULT_SLEW_RATES) "true"
set ip_params(BOARD_QDR2_USE_DEFAULT_ISI_VALUES) "true"
set ip_params(BOARD_QDR2_USER_K_SLEW_RATE) "4.0"
set ip_params(BOARD_QDR2_USER_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_QDR2_USER_RCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_QDR2_USER_RDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_QDR2_USER_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_QDR2_USER_AC_ISI_NS) "0.0"
set ip_params(BOARD_QDR2_USER_RCLK_ISI_NS) "0.0"
set ip_params(BOARD_QDR2_USER_WCLK_ISI_NS) "0.0"
set ip_params(BOARD_QDR2_USER_RDATA_ISI_NS) "0.0"
set ip_params(BOARD_QDR2_USER_WDATA_ISI_NS) "0.0"
set ip_params(BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED) "false"
set ip_params(BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED) "false"
set ip_params(BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED) "true"
set ip_params(BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS) "0.02"
set ip_params(BOARD_QDR2_BRD_SKEW_WITHIN_D_NS) "0.02"
set ip_params(BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS) "0.02"
set ip_params(BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS) "0.02"
set ip_params(BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_QDR2_AC_TO_K_SKEW_NS) "0.0"
set ip_params(BOARD_QDR2_MAX_K_DELAY_NS) "0.6"
set ip_params(BOARD_QDR2_K_SLEW_RATE) "4.0"
set ip_params(BOARD_QDR2_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_QDR2_RCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_QDR2_WCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_QDR2_RDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_QDR2_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_QDR2_AC_ISI_NS) "0.0"
set ip_params(BOARD_QDR2_RCLK_ISI_NS) "0.0"
set ip_params(BOARD_QDR2_WCLK_ISI_NS) "0.0"
set ip_params(BOARD_QDR2_RDATA_ISI_NS) "0.0"
set ip_params(BOARD_QDR2_WDATA_ISI_NS) "0.0"
set ip_params(BOARD_QDR2_SKEW_WITHIN_Q_NS) "0.0"
set ip_params(BOARD_QDR2_SKEW_WITHIN_D_NS) "0.0"
set ip_params(BOARD_QDR2_SKEW_WITHIN_AC_NS) "0.0"
set ip_params(BOARD_QDR4_USE_DEFAULT_SLEW_RATES) "true"
set ip_params(BOARD_QDR4_USE_DEFAULT_ISI_VALUES) "true"
set ip_params(BOARD_QDR4_USER_CK_SLEW_RATE) "4.0"
set ip_params(BOARD_QDR4_USER_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_QDR4_USER_RCLK_SLEW_RATE) "5.0"
set ip_params(BOARD_QDR4_USER_WCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_QDR4_USER_RDATA_SLEW_RATE) "2.5"
set ip_params(BOARD_QDR4_USER_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_QDR4_USER_AC_ISI_NS) "0.0"
set ip_params(BOARD_QDR4_USER_RCLK_ISI_NS) "0.0"
set ip_params(BOARD_QDR4_USER_WCLK_ISI_NS) "0.0"
set ip_params(BOARD_QDR4_USER_RDATA_ISI_NS) "0.0"
set ip_params(BOARD_QDR4_USER_WDATA_ISI_NS) "0.0"
set ip_params(BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED) "true"
set ip_params(BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS) "0.02"
set ip_params(BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS) "0.02"
set ip_params(BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED) "true"
set ip_params(BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_QDR4_DK_TO_CK_SKEW_NS) "-0.02"
set ip_params(BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS) "0.05"
set ip_params(BOARD_QDR4_SKEW_BETWEEN_DK_NS) "0.02"
set ip_params(BOARD_QDR4_AC_TO_CK_SKEW_NS) "0.0"
set ip_params(BOARD_QDR4_MAX_CK_DELAY_NS) "0.6"
set ip_params(BOARD_QDR4_MAX_DK_DELAY_NS) "0.6"
set ip_params(BOARD_QDR4_CK_SLEW_RATE) "4.0"
set ip_params(BOARD_QDR4_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_QDR4_RCLK_SLEW_RATE) "5.0"
set ip_params(BOARD_QDR4_WCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_QDR4_RDATA_SLEW_RATE) "2.5"
set ip_params(BOARD_QDR4_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_QDR4_AC_ISI_NS) "0.0"
set ip_params(BOARD_QDR4_RCLK_ISI_NS) "0.0"
set ip_params(BOARD_QDR4_WCLK_ISI_NS) "0.0"
set ip_params(BOARD_QDR4_RDATA_ISI_NS) "0.0"
set ip_params(BOARD_QDR4_WDATA_ISI_NS) "0.0"
set ip_params(BOARD_QDR4_SKEW_WITHIN_QK_NS) "0.0"
set ip_params(BOARD_QDR4_SKEW_WITHIN_AC_NS) "0.0"
set ip_params(BOARD_RLD3_USE_DEFAULT_SLEW_RATES) "true"
set ip_params(BOARD_RLD3_USE_DEFAULT_ISI_VALUES) "true"
set ip_params(BOARD_RLD3_USER_CK_SLEW_RATE) "4.0"
set ip_params(BOARD_RLD3_USER_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_RLD3_USER_RCLK_SLEW_RATE) "7.0"
set ip_params(BOARD_RLD3_USER_WCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_RLD3_USER_RDATA_SLEW_RATE) "3.5"
set ip_params(BOARD_RLD3_USER_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_RLD3_USER_AC_ISI_NS) "0.0"
set ip_params(BOARD_RLD3_USER_RCLK_ISI_NS) "0.0"
set ip_params(BOARD_RLD3_USER_WCLK_ISI_NS) "0.0"
set ip_params(BOARD_RLD3_USER_RDATA_ISI_NS) "0.0"
set ip_params(BOARD_RLD3_USER_WDATA_ISI_NS) "0.0"
set ip_params(BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED) "false"
set ip_params(BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS) "0.02"
set ip_params(BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS) "0.02"
set ip_params(BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED) "true"
set ip_params(BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_RLD3_DK_TO_CK_SKEW_NS) "-0.02"
set ip_params(BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS) "0.05"
set ip_params(BOARD_RLD3_SKEW_BETWEEN_DK_NS) "0.02"
set ip_params(BOARD_RLD3_AC_TO_CK_SKEW_NS) "0.0"
set ip_params(BOARD_RLD3_MAX_CK_DELAY_NS) "0.6"
set ip_params(BOARD_RLD3_MAX_DK_DELAY_NS) "0.6"
set ip_params(BOARD_RLD3_TIS_DERATING_PS) "0"
set ip_params(BOARD_RLD3_TIH_DERATING_PS) "0"
set ip_params(BOARD_RLD3_TDS_DERATING_PS) "0"
set ip_params(BOARD_RLD3_TDH_DERATING_PS) "0"
set ip_params(BOARD_RLD3_CK_SLEW_RATE) "4.0"
set ip_params(BOARD_RLD3_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_RLD3_RCLK_SLEW_RATE) "7.0"
set ip_params(BOARD_RLD3_WCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_RLD3_RDATA_SLEW_RATE) "3.5"
set ip_params(BOARD_RLD3_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_RLD3_AC_ISI_NS) "0.0"
set ip_params(BOARD_RLD3_RCLK_ISI_NS) "0.0"
set ip_params(BOARD_RLD3_WCLK_ISI_NS) "0.0"
set ip_params(BOARD_RLD3_RDATA_ISI_NS) "0.0"
set ip_params(BOARD_RLD3_WDATA_ISI_NS) "0.0"
set ip_params(BOARD_RLD3_SKEW_WITHIN_QK_NS) "0.0"
set ip_params(BOARD_RLD3_SKEW_WITHIN_AC_NS) "0.0"
set ip_params(BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES) "true"
set ip_params(BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES) "true"
set ip_params(BOARD_LPDDR3_USER_CK_SLEW_RATE) "4.0"
set ip_params(BOARD_LPDDR3_USER_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_LPDDR3_USER_RCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_LPDDR3_USER_WCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_LPDDR3_USER_RDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_LPDDR3_USER_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_LPDDR3_USER_AC_ISI_NS) "0.0"
set ip_params(BOARD_LPDDR3_USER_RCLK_ISI_NS) "0.0"
set ip_params(BOARD_LPDDR3_USER_WCLK_ISI_NS) "0.0"
set ip_params(BOARD_LPDDR3_USER_RDATA_ISI_NS) "0.0"
set ip_params(BOARD_LPDDR3_USER_WDATA_ISI_NS) "0.0"
set ip_params(BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED) "false"
set ip_params(BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS) "0.02"
set ip_params(BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS) "0.02"
set ip_params(BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED) "true"
set ip_params(BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_LPDDR3_DQS_TO_CK_SKEW_NS) "0.02"
set ip_params(BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS) "0.05"
set ip_params(BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS) "0.02"
set ip_params(BOARD_LPDDR3_AC_TO_CK_SKEW_NS) "0.0"
set ip_params(BOARD_LPDDR3_MAX_CK_DELAY_NS) "0.6"
set ip_params(BOARD_LPDDR3_MAX_DQS_DELAY_NS) "0.6"
set ip_params(BOARD_LPDDR3_TIS_DERATING_PS) "0"
set ip_params(BOARD_LPDDR3_TIH_DERATING_PS) "0"
set ip_params(BOARD_LPDDR3_TDS_DERATING_PS) "0"
set ip_params(BOARD_LPDDR3_TDH_DERATING_PS) "0"
set ip_params(BOARD_LPDDR3_CK_SLEW_RATE) "4.0"
set ip_params(BOARD_LPDDR3_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_LPDDR3_RCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_LPDDR3_WCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_LPDDR3_RDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_LPDDR3_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_LPDDR3_AC_ISI_NS) "0.125"
set ip_params(BOARD_LPDDR3_RCLK_ISI_NS) "0.125"
set ip_params(BOARD_LPDDR3_WCLK_ISI_NS) "0.063"
set ip_params(BOARD_LPDDR3_RDATA_ISI_NS) "0.1"
set ip_params(BOARD_LPDDR3_WDATA_ISI_NS) "0.125"
set ip_params(BOARD_LPDDR3_SKEW_WITHIN_DQS_NS) "0.12000000000000001"
set ip_params(BOARD_LPDDR3_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_DDRT_USE_DEFAULT_SLEW_RATES) "true"
set ip_params(BOARD_DDRT_USE_DEFAULT_ISI_VALUES) "true"
set ip_params(BOARD_DDRT_USER_CK_SLEW_RATE) "4.0"
set ip_params(BOARD_DDRT_USER_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_DDRT_USER_RCLK_SLEW_RATE) "8.0"
set ip_params(BOARD_DDRT_USER_WCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_DDRT_USER_RDATA_SLEW_RATE) "4.0"
set ip_params(BOARD_DDRT_USER_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_DDRT_USER_AC_ISI_NS) "0.0"
set ip_params(BOARD_DDRT_USER_RCLK_ISI_NS) "0.0"
set ip_params(BOARD_DDRT_USER_WCLK_ISI_NS) "0.0"
set ip_params(BOARD_DDRT_USER_RDATA_ISI_NS) "0.0"
set ip_params(BOARD_DDRT_USER_WDATA_ISI_NS) "0.0"
set ip_params(BOARD_DDRT_IS_SKEW_WITHIN_DQS_DESKEWED) "true"
set ip_params(BOARD_DDRT_BRD_SKEW_WITHIN_DQS_NS) "0.02"
set ip_params(BOARD_DDRT_PKG_BRD_SKEW_WITHIN_DQS_NS) "0.02"
set ip_params(BOARD_DDRT_IS_SKEW_WITHIN_AC_DESKEWED) "false"
set ip_params(BOARD_DDRT_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_DDRT_PKG_BRD_SKEW_WITHIN_AC_NS) "0.02"
set ip_params(BOARD_DDRT_DQS_TO_CK_SKEW_NS) "0.02"
set ip_params(BOARD_DDRT_SKEW_BETWEEN_DIMMS_NS) "0.05"
set ip_params(BOARD_DDRT_SKEW_BETWEEN_DQS_NS) "0.02"
set ip_params(BOARD_DDRT_AC_TO_CK_SKEW_NS) "0.0"
set ip_params(BOARD_DDRT_MAX_CK_DELAY_NS) "0.6"
set ip_params(BOARD_DDRT_MAX_DQS_DELAY_NS) "0.6"
set ip_params(BOARD_DDRT_TIS_DERATING_PS) "0"
set ip_params(BOARD_DDRT_TIH_DERATING_PS) "0"
set ip_params(BOARD_DDRT_CK_SLEW_RATE) "4.0"
set ip_params(BOARD_DDRT_AC_SLEW_RATE) "2.0"
set ip_params(BOARD_DDRT_RCLK_SLEW_RATE) "8.0"
set ip_params(BOARD_DDRT_WCLK_SLEW_RATE) "4.0"
set ip_params(BOARD_DDRT_RDATA_SLEW_RATE) "4.0"
set ip_params(BOARD_DDRT_WDATA_SLEW_RATE) "2.0"
set ip_params(BOARD_DDRT_AC_ISI_NS) "0.0"
set ip_params(BOARD_DDRT_RCLK_ISI_NS) "0.0"
set ip_params(BOARD_DDRT_WCLK_ISI_NS) "0.0"
set ip_params(BOARD_DDRT_RDATA_ISI_NS) "0.0"
set ip_params(BOARD_DDRT_WDATA_ISI_NS) "0.0"
set ip_params(BOARD_DDRT_SKEW_WITHIN_DQS_NS) "0.0"
set ip_params(BOARD_DDRT_SKEW_WITHIN_AC_NS) "0.0"
set ip_params(CTRL_ECC_EN) "false"
set ip_params(CTRL_MMR_EN) "false"
set ip_params(CTRL_AUTO_PRECHARGE_EN) "false"
set ip_params(CTRL_USER_PRIORITY_EN) "false"
set ip_params(CTRL_REORDER_EN) "false"
set ip_params(CTRL_ECC_READDATAERROR_EN) "false"
set ip_params(CTRL_ECC_STATUS_EN) "false"
set ip_params(CTRL_DDR3_AVL_PROTOCOL_ENUM) "CTRL_AVL_PROTOCOL_MM"
set ip_params(CTRL_DDR3_SELF_REFRESH_EN) "false"
set ip_params(CTRL_DDR3_AUTO_POWER_DOWN_EN) "false"
set ip_params(CTRL_DDR3_AUTO_POWER_DOWN_CYCS) "32"
set ip_params(CTRL_DDR3_USER_REFRESH_EN) "false"
set ip_params(CTRL_DDR3_USER_PRIORITY_EN) "false"
set ip_params(CTRL_DDR3_AUTO_PRECHARGE_EN) "false"
set ip_params(CTRL_DDR3_ADDR_ORDER_ENUM) "DDR3_CTRL_ADDR_ORDER_CS_R_B_C"
set ip_params(CTRL_DDR3_ECC_EN) "false"
set ip_params(CTRL_DDR3_ECC_AUTO_CORRECTION_EN) "false"
set ip_params(CTRL_DDR3_ECC_READDATAERROR_EN) "false"
set ip_params(CTRL_DDR3_ECC_STATUS_EN) "false"
set ip_params(CTRL_DDR3_REORDER_EN) "true"
set ip_params(CTRL_DDR3_STARVE_LIMIT) "10"
set ip_params(CTRL_DDR3_MMR_EN) "false"
set ip_params(CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDR4_AVL_PROTOCOL_ENUM) "CTRL_AVL_PROTOCOL_MM"
set ip_params(CTRL_DDR4_SELF_REFRESH_EN) "false"
set ip_params(CTRL_DDR4_AUTO_POWER_DOWN_EN) "false"
set ip_params(CTRL_DDR4_AUTO_POWER_DOWN_CYCS) "32"
set ip_params(CTRL_DDR4_USER_REFRESH_EN) "false"
set ip_params(CTRL_DDR4_USER_PRIORITY_EN) "false"
set ip_params(CTRL_DDR4_AUTO_PRECHARGE_EN) "false"
set ip_params(CTRL_DDR4_ADDR_ORDER_ENUM) "DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG"
set ip_params(CTRL_DDR4_ECC_EN) "false"
set ip_params(CTRL_DDR4_ECC_AUTO_CORRECTION_EN) "false"
set ip_params(CTRL_DDR4_ECC_READDATAERROR_EN) "false"
set ip_params(CTRL_DDR4_ECC_STATUS_EN) "false"
set ip_params(CTRL_DDR4_REORDER_EN) "true"
set ip_params(CTRL_DDR4_STARVE_LIMIT) "10"
set ip_params(CTRL_DDR4_MMR_EN) "false"
set ip_params(CTRL_DDR4_MAJOR_MODE_EN) "false"
set ip_params(CTRL_DDR4_POST_REFRESH_EN) "false"
set ip_params(CTRL_DDR4_POST_REFRESH_LOWER_LIMIT) "0"
set ip_params(CTRL_DDR4_POST_REFRESH_UPPER_LIMIT) "2"
set ip_params(CTRL_DDR4_PRE_REFRESH_EN) "false"
set ip_params(CTRL_DDR4_PRE_REFRESH_UPPER_LIMIT) "1"
set ip_params(CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_QDR2_AVL_PROTOCOL_ENUM) "CTRL_AVL_PROTOCOL_MM"
set ip_params(CTRL_QDR2_AVL_MAX_BURST_COUNT) "4"
set ip_params(CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS) "false"
set ip_params(CTRL_QDR2_AVL_SYMBOL_WIDTH) "9"
set ip_params(CTRL_QDR4_AVL_PROTOCOL_ENUM) "CTRL_AVL_PROTOCOL_MM"
set ip_params(CTRL_QDR4_AVL_MAX_BURST_COUNT) "4"
set ip_params(CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS) "false"
set ip_params(CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC) "0"
set ip_params(CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC) "0"
set ip_params(CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC) "4"
set ip_params(CTRL_QDR4_AVL_SYMBOL_WIDTH) "9"
set ip_params(CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC) "4"
set ip_params(CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC) "11"
set ip_params(CTRL_RLD2_AVL_PROTOCOL_ENUM) "CTRL_AVL_PROTOCOL_MM"
set ip_params(CTRL_RLD3_AVL_PROTOCOL_ENUM) "CTRL_AVL_PROTOCOL_MM"
set ip_params(CTRL_RLD3_ADDR_ORDER_ENUM) "RLD3_CTRL_ADDR_ORDER_CS_R_B_C"
set ip_params(CTRL_LPDDR3_AVL_PROTOCOL_ENUM) "CTRL_AVL_PROTOCOL_MM"
set ip_params(CTRL_LPDDR3_SELF_REFRESH_EN) "false"
set ip_params(CTRL_LPDDR3_AUTO_POWER_DOWN_EN) "false"
set ip_params(CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS) "32"
set ip_params(CTRL_LPDDR3_USER_REFRESH_EN) "false"
set ip_params(CTRL_LPDDR3_USER_PRIORITY_EN) "false"
set ip_params(CTRL_LPDDR3_AUTO_PRECHARGE_EN) "false"
set ip_params(CTRL_LPDDR3_ADDR_ORDER_ENUM) "LPDDR3_CTRL_ADDR_ORDER_R_CS_B_C"
set ip_params(CTRL_LPDDR3_REORDER_EN) "false"
set ip_params(CTRL_LPDDR3_STARVE_LIMIT) "10"
set ip_params(CTRL_LPDDR3_MMR_EN) "false"
set ip_params(CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDRT_AVL_PROTOCOL_ENUM) "CTRL_AVL_PROTOCOL_MM"
set ip_params(CTRL_DDRT_SELF_REFRESH_EN) "false"
set ip_params(CTRL_DDRT_AUTO_POWER_DOWN_EN) "false"
set ip_params(CTRL_DDRT_AUTO_POWER_DOWN_CYCS) "32"
set ip_params(CTRL_DDRT_USER_REFRESH_EN) "false"
set ip_params(CTRL_DDRT_USER_PRIORITY_EN) "false"
set ip_params(CTRL_DDRT_AUTO_PRECHARGE_EN) "false"
set ip_params(CTRL_DDRT_ADDR_ORDER_ENUM) "DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG"
set ip_params(CTRL_DDRT_ECC_EN) "false"
set ip_params(CTRL_DDRT_ECC_AUTO_CORRECTION_EN) "false"
set ip_params(CTRL_DDRT_ECC_READDATAERROR_EN) "true"
set ip_params(CTRL_DDRT_ECC_STATUS_EN) "true"
set ip_params(CTRL_DDRT_REORDER_EN) "true"
set ip_params(CTRL_DDRT_STARVE_LIMIT) "10"
set ip_params(CTRL_DDRT_MMR_EN) "false"
set ip_params(CTRL_DDRT_RD_TO_WR_SAME_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDRT_WR_TO_RD_SAME_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDRT_RD_TO_RD_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDRT_RD_TO_WR_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDRT_WR_TO_RD_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDRT_DIMM_DENSITY) "128"
set ip_params(CTRL_DDRT_NUM_OF_AXIS_ID) "1"
set ip_params(CTRL_DDRT_WR_ACK_POLICY) "POSTED"
set ip_params(CTRL_DDRT_ERR_REPLAY_EN) "false"
set ip_params(CTRL_DDRT_HOST_VIRAL_FLOW_EN) "false"
set ip_params(CTRL_DDRT_DIMM_VIRAL_FLOW_EN) "false"
set ip_params(CTRL_DDRT_POISON_DETECTION_EN) "false"
set ip_params(CTRL_DDRT_PMM_ADR_FLOW_EN) "false"
set ip_params(CTRL_DDRT_PMM_WPQ_FLUSH_EN) "false"
set ip_params(CTRL_DDRT_UPI_EN) "false"
set ip_params(CTRL_DDRT_UPI_ID_WIDTH) "8"
set ip_params(CTRL_DDRT_PARITY_CMD_EN) "false"
set ip_params(CTRL_DDRT_ADDR_INTERLEAVING) "COARSE"
set ip_params(CTRL_DDRT_PORT_AFI_C_WIDTH) "2"
set ip_params(CTRL_DDRT_ZQ_INTERVAL_MS) "3"
set ip_params(CTRL_DDRT_ERR_INJECT_EN) "false"
set ip_params(CTRL_DDRT_GNT_TO_WR_SAME_CHIP_DELTA_CYCS) "1"
set ip_params(CTRL_DDRT_WR_TO_GNT_SAME_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDRT_GNT_TO_GNT_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDRT_GNT_TO_WR_DIFF_CHIP_DELTA_CYCS) "1"
set ip_params(CTRL_DDRT_WR_TO_GNT_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDRT_WR_TO_WR_DIFF_CHIP_DELTA_CYCS) "0"
set ip_params(CTRL_DDRT_DRIVER_MARGINING_EN) "0"
set ip_params(CTRL_DDRT_AXIS_DATA_WIDTH) "512"
set ip_params(DIAG_SIM_REGTEST_MODE) "false"
set ip_params(DIAG_TIMING_REGTEST_MODE) "false"
set ip_params(DIAG_SYNTH_FOR_SIM) "false"
set ip_params(DIAG_FAST_SIM_OVERRIDE) "FAST_SIM_OVERRIDE_DEFAULT"
set ip_params(DIAG_SEQ_RESET_AUTO_RELEASE) "avl"
set ip_params(DIAG_DB_RESET_AUTO_RELEASE) "avl_release"
set ip_params(DIAG_ADD_READY_PIPELINE) "true"
set ip_params(DIAG_EXPOSE_EARLY_READY) "false"
set ip_params(DIAG_EXPOSE_RD_TYPE) "false"
set ip_params(DIAG_VERBOSE_IOAUX) "false"
set ip_params(DIAG_ECLIPSE_DEBUG) "false"
set ip_params(DIAG_EXPORT_VJI) "false"
set ip_params(DIAG_ENABLE_JTAG_UART) "false"
set ip_params(DIAG_ENABLE_JTAG_UART_HEX) "false"
set ip_params(DIAG_ENABLE_HPS_EMIF_DEBUG) "false"
set ip_params(DIAG_SOFT_NIOS_MODE) "SOFT_NIOS_MODE_DISABLED"
set ip_params(DIAG_SOFT_NIOS_CLOCK_FREQUENCY) "100"
set ip_params(DIAG_USE_RS232_UART) "false"
set ip_params(DIAG_RS232_UART_BAUDRATE) "57600"
set ip_params(DIAG_EX_DESIGN_ADD_TEST_EMIFS) ""
set ip_params(DIAG_EX_DESIGN_SEPARATE_RESETS) "false"
set ip_params(DIAG_EXPOSE_DFT_SIGNALS) "false"
set ip_params(DIAG_EXTRA_CONFIGS) ""
set ip_params(DIAG_USE_BOARD_DELAY_MODEL) "false"
set ip_params(DIAG_BOARD_DELAY_CONFIG_STR) ""
set ip_params(DIAG_TG_AVL_2_NUM_CFG_INTERFACES) "0"
set ip_params(DIAG_EXPORT_PLL_REF_CLK_OUT) "false"
set ip_params(DIAG_EXPORT_PLL_LOCKED) "false"
set ip_params(DIAG_HMC_HRC) "auto"
set ip_params(SHORT_QSYS_INTERFACE_NAMES) "true"
set ip_params(DIAG_EXT_DOCS) "false"
set ip_params(DIAG_SIM_CAL_MODE_ENUM) "SIM_CAL_MODE_SKIP"
set ip_params(DIAG_EXPORT_SEQ_AVALON_SLAVE) "CAL_DEBUG_EXPORT_MODE_DISABLED"
set ip_params(DIAG_EXPORT_SEQ_AVALON_MASTER) "false"
set ip_params(DIAG_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN) "true"
set ip_params(DIAG_EX_DESIGN_NUM_OF_SLAVES) "1"
set ip_params(DIAG_EX_DESIGN_ISSP_EN) "false"
set ip_params(DIAG_INTERFACE_ID) "0"
set ip_params(DIAG_EFFICIENCY_MONITOR) "EFFMON_MODE_DISABLED"
set ip_params(DIAG_USE_NEW_EFFMON_S10) "false"
set ip_params(DIAG_USE_ABSTRACT_PHY) "false"
set ip_params(DIAG_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) ""
set ip_params(DIAG_SIM_MEMORY_PRELOAD_PRI_ECC_FILE) ""
set ip_params(DIAG_SIM_MEMORY_PRELOAD_PRI_MEM_FILE) ""
set ip_params(DIAG_SIM_MEMORY_PRELOAD_PRI_ABPHY_FILE) ""
set ip_params(DIAG_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) ""
set ip_params(DIAG_SIM_MEMORY_PRELOAD_SEC_ECC_FILE) ""
set ip_params(DIAG_SIM_MEMORY_PRELOAD_SEC_MEM_FILE) ""
set ip_params(DIAG_SIM_MEMORY_PRELOAD_SEC_ABPHY_FILE) ""
set ip_params(DIAG_USE_SIM_MEMORY_VALIDATION_TG) "false"
set ip_params(DIAG_SIM_VERBOSE_LEVEL) "5"
set ip_params(DIAG_FAST_SIM) "true"
set ip_params(DIAG_USE_TG_AVL_2) "false"
set ip_params(DIAG_TG2_TEST_DURATION) "SHORT"
set ip_params(DIAG_USE_TG_HBM) "false"
set ip_params(DIAG_EXPORT_TG_CFG_AVALON_SLAVE) "TG_CFG_AMM_EXPORT_MODE_JTAG"
set ip_params(DIAG_ENABLE_DEFAULT_MODE) "false"
set ip_params(DIAG_ENABLE_USER_MODE) "true"
set ip_params(DIAG_ENABLE_SOFT_M20K) "true"
set ip_params(DIAG_SIM_CHECKER_SKIP_TG) "false"
set ip_params(DIAG_AC_PARITY_ERR) "false"
set ip_params(DIAG_DISABLE_AFI_P2C_REGISTERS) "false"
set ip_params(DIAG_EX_DESIGN_SEPARATE_RZQS) "true"
set ip_params(DIAG_DDR3_SIM_CAL_MODE_ENUM) "SIM_CAL_MODE_SKIP"
set ip_params(DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE) "CAL_DEBUG_EXPORT_MODE_DISABLED"
set ip_params(DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER) "false"
set ip_params(DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN) "true"
set ip_params(DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES) "1"
set ip_params(DIAG_DDR3_EX_DESIGN_ISSP_EN) "true"
set ip_params(DIAG_DDR3_INTERFACE_ID) "0"
set ip_params(DIAG_DDR3_EFFICIENCY_MONITOR) "EFFMON_MODE_DISABLED"
set ip_params(DIAG_DDR3_USE_NEW_EFFMON_S10) "false"
set ip_params(DIAG_DDR3_USER_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) "EMIF_PRI_PRELOAD.txt"
set ip_params(DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) "EMIF_SEC_PRELOAD.txt"
set ip_params(DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG) "true"
set ip_params(DIAG_DDR3_USE_TG_AVL_2) "false"
set ip_params(DIAG_DDR3_USE_TG_HBM) "false"
set ip_params(DIAG_DDR3_ABSTRACT_PHY) "false"
set ip_params(DIAG_DDR3_ENABLE_DEFAULT_MODE) "false"
set ip_params(DIAG_DDR3_ENABLE_USER_MODE) "true"
set ip_params(DIAG_DDR3_EXPORT_TG_CFG_AVALON_SLAVE) "TG_CFG_AMM_EXPORT_MODE_JTAG"
set ip_params(DIAG_DDR3_TG2_TEST_DURATION) "SHORT"
set ip_params(DIAG_DDR3_SEPARATE_READ_WRITE_ITFS) "false"
set ip_params(DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS) "false"
set ip_params(DIAG_DDR3_AC_PARITY_ERR) "false"
set ip_params(DIAG_DDR3_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_DDR3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) ""
set ip_params(DIAG_DDR3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) ""
set ip_params(DIAG_DDR3_USE_SIM_MEMORY_VALIDATION_TG) "false"
set ip_params(DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS) "true"
set ip_params(DIAG_DDR3_SIM_VERBOSE) "true"
set ip_params(DIAG_DDR3_CA_LEVEL_EN) "false"
set ip_params(DIAG_DDR3_CA_DESKEW_EN) "false"
set ip_params(DIAG_DDR3_CAL_ADDR0) "0"
set ip_params(DIAG_DDR3_CAL_ADDR1) "8"
set ip_params(DIAG_DDR3_CAL_ENABLE_NON_DES) "false"
set ip_params(DIAG_DDR3_CAL_FULL_CAL_ON_RESET) "true"
set ip_params(DIAG_DDR3_CAL_ENABLE_MICRON_AP) "false"
set ip_params(DIAG_DDR4_SIM_CAL_MODE_ENUM) "SIM_CAL_MODE_SKIP"
set ip_params(DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE) "CAL_DEBUG_EXPORT_MODE_DISABLED"
set ip_params(DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER) "false"
set ip_params(DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN) "true"
set ip_params(DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES) "1"
set ip_params(DIAG_DDR4_EX_DESIGN_ISSP_EN) "true"
set ip_params(DIAG_DDR4_INTERFACE_ID) "0"
set ip_params(DIAG_DDR4_EFFICIENCY_MONITOR) "EFFMON_MODE_DISABLED"
set ip_params(DIAG_DDR4_USE_NEW_EFFMON_S10) "false"
set ip_params(DIAG_DDR4_USER_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) "EMIF_PRI_PRELOAD.txt"
set ip_params(DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) "EMIF_SEC_PRELOAD.txt"
set ip_params(DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG) "true"
set ip_params(DIAG_DDR4_USE_TG_AVL_2) "false"
set ip_params(DIAG_DDR4_USE_TG_HBM) "false"
set ip_params(DIAG_DDR4_ABSTRACT_PHY) "false"
set ip_params(DIAG_DDR4_ENABLE_DEFAULT_MODE) "false"
set ip_params(DIAG_DDR4_ENABLE_USER_MODE) "true"
set ip_params(DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE) "TG_CFG_AMM_EXPORT_MODE_JTAG"
set ip_params(DIAG_DDR4_TG2_TEST_DURATION) "SHORT"
set ip_params(DIAG_DDR4_SEPARATE_READ_WRITE_ITFS) "false"
set ip_params(DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS) "false"
set ip_params(DIAG_DDR4_AC_PARITY_ERR) "false"
set ip_params(DIAG_DDR4_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_DDR4_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) ""
set ip_params(DIAG_DDR4_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) ""
set ip_params(DIAG_DDR4_USE_SIM_MEMORY_VALIDATION_TG) "false"
set ip_params(DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS) "true"
set ip_params(DIAG_DDR4_SIM_VERBOSE) "true"
set ip_params(DIAG_DDR4_SKIP_CA_LEVEL) "false"
set ip_params(DIAG_DDR4_SKIP_CA_DESKEW) "false"
set ip_params(DIAG_DDR4_SKIP_VREF_CAL) "false"
set ip_params(DIAG_DDR4_SKIP_AC_PARITY_CHECK) "false"
set ip_params(DIAG_DDR4_CAL_ADDR0) "0"
set ip_params(DIAG_DDR4_CAL_ADDR1) "8"
set ip_params(DIAG_DDR4_CAL_ENABLE_NON_DES) "false"
set ip_params(DIAG_DDR4_CAL_FULL_CAL_ON_RESET) "true"
set ip_params(DIAG_QDR2_SIM_CAL_MODE_ENUM) "SIM_CAL_MODE_SKIP"
set ip_params(DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE) "CAL_DEBUG_EXPORT_MODE_DISABLED"
set ip_params(DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER) "false"
set ip_params(DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN) "true"
set ip_params(DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES) "1"
set ip_params(DIAG_QDR2_EX_DESIGN_ISSP_EN) "true"
set ip_params(DIAG_QDR2_INTERFACE_ID) "0"
set ip_params(DIAG_QDR2_EFFICIENCY_MONITOR) "EFFMON_MODE_DISABLED"
set ip_params(DIAG_QDR2_USE_NEW_EFFMON_S10) "false"
set ip_params(DIAG_QDR2_USER_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) "EMIF_PRI_PRELOAD.txt"
set ip_params(DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) "EMIF_SEC_PRELOAD.txt"
set ip_params(DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG) "true"
set ip_params(DIAG_QDR2_USE_TG_AVL_2) "false"
set ip_params(DIAG_QDR2_USE_TG_HBM) "false"
set ip_params(DIAG_QDR2_ABSTRACT_PHY) "false"
set ip_params(DIAG_QDR2_ENABLE_DEFAULT_MODE) "false"
set ip_params(DIAG_QDR2_ENABLE_USER_MODE) "true"
set ip_params(DIAG_QDR2_EXPORT_TG_CFG_AVALON_SLAVE) "TG_CFG_AMM_EXPORT_MODE_JTAG"
set ip_params(DIAG_QDR2_TG2_TEST_DURATION) "SHORT"
set ip_params(DIAG_QDR2_SEPARATE_READ_WRITE_ITFS) "false"
set ip_params(DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS) "false"
set ip_params(DIAG_QDR2_AC_PARITY_ERR) "false"
set ip_params(DIAG_QDR2_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_QDR2_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) ""
set ip_params(DIAG_QDR2_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) ""
set ip_params(DIAG_QDR2_USE_SIM_MEMORY_VALIDATION_TG) "false"
set ip_params(DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS) "true"
set ip_params(DIAG_QDR2_SIM_VERBOSE) "true"
set ip_params(DIAG_QDR4_SIM_CAL_MODE_ENUM) "SIM_CAL_MODE_SKIP"
set ip_params(DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE) "CAL_DEBUG_EXPORT_MODE_DISABLED"
set ip_params(DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER) "false"
set ip_params(DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN) "true"
set ip_params(DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES) "1"
set ip_params(DIAG_QDR4_EX_DESIGN_ISSP_EN) "true"
set ip_params(DIAG_QDR4_INTERFACE_ID) "0"
set ip_params(DIAG_QDR4_EFFICIENCY_MONITOR) "EFFMON_MODE_DISABLED"
set ip_params(DIAG_QDR4_USE_NEW_EFFMON_S10) "false"
set ip_params(DIAG_QDR4_USER_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) "EMIF_PRI_PRELOAD.txt"
set ip_params(DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) "EMIF_SEC_PRELOAD.txt"
set ip_params(DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG) "true"
set ip_params(DIAG_QDR4_USE_TG_AVL_2) "false"
set ip_params(DIAG_QDR4_USE_TG_HBM) "false"
set ip_params(DIAG_QDR4_ABSTRACT_PHY) "false"
set ip_params(DIAG_QDR4_ENABLE_DEFAULT_MODE) "false"
set ip_params(DIAG_QDR4_ENABLE_USER_MODE) "true"
set ip_params(DIAG_QDR4_EXPORT_TG_CFG_AVALON_SLAVE) "TG_CFG_AMM_EXPORT_MODE_JTAG"
set ip_params(DIAG_QDR4_TG2_TEST_DURATION) "SHORT"
set ip_params(DIAG_QDR4_SEPARATE_READ_WRITE_ITFS) "false"
set ip_params(DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS) "false"
set ip_params(DIAG_QDR4_AC_PARITY_ERR) "false"
set ip_params(DIAG_QDR4_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_QDR4_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) ""
set ip_params(DIAG_QDR4_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) ""
set ip_params(DIAG_QDR4_USE_SIM_MEMORY_VALIDATION_TG) "false"
set ip_params(DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS) "true"
set ip_params(DIAG_QDR4_SIM_VERBOSE) "true"
set ip_params(DIAG_QDR4_SKIP_VREF_CAL) "false"
set ip_params(DIAG_RLD2_SIM_CAL_MODE_ENUM) "SIM_CAL_MODE_SKIP"
set ip_params(DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE) "CAL_DEBUG_EXPORT_MODE_DISABLED"
set ip_params(DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER) "false"
set ip_params(DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN) "true"
set ip_params(DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES) "1"
set ip_params(DIAG_RLD2_EX_DESIGN_ISSP_EN) "true"
set ip_params(DIAG_RLD2_INTERFACE_ID) "0"
set ip_params(DIAG_RLD2_EFFICIENCY_MONITOR) "EFFMON_MODE_DISABLED"
set ip_params(DIAG_RLD2_USE_NEW_EFFMON_S10) "false"
set ip_params(DIAG_RLD2_USER_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) "EMIF_PRI_PRELOAD.txt"
set ip_params(DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) "EMIF_SEC_PRELOAD.txt"
set ip_params(DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG) "true"
set ip_params(DIAG_RLD2_USE_TG_AVL_2) "false"
set ip_params(DIAG_RLD2_USE_TG_HBM) "false"
set ip_params(DIAG_RLD2_ABSTRACT_PHY) "false"
set ip_params(DIAG_RLD2_ENABLE_DEFAULT_MODE) "false"
set ip_params(DIAG_RLD2_ENABLE_USER_MODE) "true"
set ip_params(DIAG_RLD2_EXPORT_TG_CFG_AVALON_SLAVE) "TG_CFG_AMM_EXPORT_MODE_JTAG"
set ip_params(DIAG_RLD2_TG2_TEST_DURATION) "SHORT"
set ip_params(DIAG_RLD2_SEPARATE_READ_WRITE_ITFS) "false"
set ip_params(DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS) "false"
set ip_params(DIAG_RLD2_AC_PARITY_ERR) "false"
set ip_params(DIAG_RLD2_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_RLD2_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) ""
set ip_params(DIAG_RLD2_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) ""
set ip_params(DIAG_RLD2_USE_SIM_MEMORY_VALIDATION_TG) "false"
set ip_params(DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS) "true"
set ip_params(DIAG_RLD2_SIM_VERBOSE) "true"
set ip_params(DIAG_RLD3_SIM_CAL_MODE_ENUM) "SIM_CAL_MODE_SKIP"
set ip_params(DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE) "CAL_DEBUG_EXPORT_MODE_DISABLED"
set ip_params(DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER) "false"
set ip_params(DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN) "true"
set ip_params(DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES) "1"
set ip_params(DIAG_RLD3_EX_DESIGN_ISSP_EN) "true"
set ip_params(DIAG_RLD3_INTERFACE_ID) "0"
set ip_params(DIAG_RLD3_EFFICIENCY_MONITOR) "EFFMON_MODE_DISABLED"
set ip_params(DIAG_RLD3_USE_NEW_EFFMON_S10) "false"
set ip_params(DIAG_RLD3_USER_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) "EMIF_PRI_PRELOAD.txt"
set ip_params(DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) "EMIF_SEC_PRELOAD.txt"
set ip_params(DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG) "true"
set ip_params(DIAG_RLD3_USE_TG_AVL_2) "false"
set ip_params(DIAG_RLD3_USE_TG_HBM) "false"
set ip_params(DIAG_RLD3_ABSTRACT_PHY) "false"
set ip_params(DIAG_RLD3_ENABLE_DEFAULT_MODE) "false"
set ip_params(DIAG_RLD3_ENABLE_USER_MODE) "true"
set ip_params(DIAG_RLD3_EXPORT_TG_CFG_AVALON_SLAVE) "TG_CFG_AMM_EXPORT_MODE_JTAG"
set ip_params(DIAG_RLD3_TG2_TEST_DURATION) "SHORT"
set ip_params(DIAG_RLD3_SEPARATE_READ_WRITE_ITFS) "false"
set ip_params(DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS) "false"
set ip_params(DIAG_RLD3_AC_PARITY_ERR) "false"
set ip_params(DIAG_RLD3_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_RLD3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) ""
set ip_params(DIAG_RLD3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) ""
set ip_params(DIAG_RLD3_USE_SIM_MEMORY_VALIDATION_TG) "false"
set ip_params(DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS) "true"
set ip_params(DIAG_RLD3_SIM_VERBOSE) "true"
set ip_params(DIAG_RLD3_CA_LEVEL_EN) "false"
set ip_params(DIAG_RLD3_CA_DESKEW_EN) "false"
set ip_params(DIAG_LPDDR3_SIM_CAL_MODE_ENUM) "SIM_CAL_MODE_SKIP"
set ip_params(DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE) "CAL_DEBUG_EXPORT_MODE_DISABLED"
set ip_params(DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER) "false"
set ip_params(DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN) "true"
set ip_params(DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES) "1"
set ip_params(DIAG_LPDDR3_EX_DESIGN_ISSP_EN) "false"
set ip_params(DIAG_LPDDR3_INTERFACE_ID) "0"
set ip_params(DIAG_LPDDR3_EFFICIENCY_MONITOR) "EFFMON_MODE_DISABLED"
set ip_params(DIAG_LPDDR3_USE_NEW_EFFMON_S10) "false"
set ip_params(DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) "EMIF_PRI_PRELOAD.txt"
set ip_params(DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) "EMIF_SEC_PRELOAD.txt"
set ip_params(DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG) "true"
set ip_params(DIAG_LPDDR3_USE_TG_AVL_2) "false"
set ip_params(DIAG_LPDDR3_USE_TG_HBM) "false"
set ip_params(DIAG_LPDDR3_ABSTRACT_PHY) "false"
set ip_params(DIAG_LPDDR3_ENABLE_DEFAULT_MODE) "false"
set ip_params(DIAG_LPDDR3_ENABLE_USER_MODE) "true"
set ip_params(DIAG_LPDDR3_EXPORT_TG_CFG_AVALON_SLAVE) "TG_CFG_AMM_EXPORT_MODE_JTAG"
set ip_params(DIAG_LPDDR3_TG2_TEST_DURATION) "SHORT"
set ip_params(DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS) "false"
set ip_params(DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS) "false"
set ip_params(DIAG_LPDDR3_AC_PARITY_ERR) "false"
set ip_params(DIAG_LPDDR3_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_LPDDR3_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) ""
set ip_params(DIAG_LPDDR3_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) ""
set ip_params(DIAG_LPDDR3_USE_SIM_MEMORY_VALIDATION_TG) "false"
set ip_params(DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS) "true"
set ip_params(DIAG_LPDDR3_SIM_VERBOSE) "true"
set ip_params(DIAG_LPDDR3_SKIP_CA_LEVEL) "false"
set ip_params(DIAG_LPDDR3_SKIP_CA_DESKEW) "false"
set ip_params(DIAG_DDRT_SIM_CAL_MODE_ENUM) "SIM_CAL_MODE_SKIP"
set ip_params(DIAG_DDRT_EXPORT_SEQ_AVALON_SLAVE) "CAL_DEBUG_EXPORT_MODE_DISABLED"
set ip_params(DIAG_DDRT_EXPORT_SEQ_AVALON_MASTER) "false"
set ip_params(DIAG_DDRT_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN) "true"
set ip_params(DIAG_DDRT_EX_DESIGN_NUM_OF_SLAVES) "1"
set ip_params(DIAG_DDRT_EX_DESIGN_ISSP_EN) "true"
set ip_params(DIAG_DDRT_INTERFACE_ID) "0"
set ip_params(DIAG_DDRT_EFFICIENCY_MONITOR) "EFFMON_MODE_DISABLED"
set ip_params(DIAG_DDRT_USE_NEW_EFFMON_S10) "false"
set ip_params(DIAG_DDRT_USER_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) "EMIF_PRI_PRELOAD.txt"
set ip_params(DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) "EMIF_SEC_PRELOAD.txt"
set ip_params(DIAG_DDRT_USER_USE_SIM_MEMORY_VALIDATION_TG) "true"
set ip_params(DIAG_DDRT_USE_TG_AVL_2) "true"
set ip_params(DIAG_DDRT_USE_TG_HBM) "false"
set ip_params(DIAG_DDRT_ABSTRACT_PHY) "false"
set ip_params(DIAG_DDRT_ENABLE_DEFAULT_MODE) "false"
set ip_params(DIAG_DDRT_ENABLE_USER_MODE) "true"
set ip_params(DIAG_DDRT_EXPORT_TG_CFG_AVALON_SLAVE) "TG_CFG_AMM_EXPORT_MODE_JTAG"
set ip_params(DIAG_DDRT_TG2_TEST_DURATION) "SHORT"
set ip_params(DIAG_DDRT_SEPARATE_READ_WRITE_ITFS) "false"
set ip_params(DIAG_DDRT_DISABLE_AFI_P2C_REGISTERS) "false"
set ip_params(DIAG_DDRT_AC_PARITY_ERR) "false"
set ip_params(DIAG_DDRT_SIM_MEMORY_PRELOAD) "false"
set ip_params(DIAG_DDRT_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE) ""
set ip_params(DIAG_DDRT_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE) ""
set ip_params(DIAG_DDRT_USE_SIM_MEMORY_VALIDATION_TG) "false"
set ip_params(DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS) "true"
set ip_params(DIAG_DDRT_SIM_VERBOSE) "true"
set ip_params(DIAG_DDRT_SKIP_CA_LEVEL) "false"
set ip_params(DIAG_DDRT_SKIP_CA_DESKEW) "false"
set ip_params(DIAG_DDRT_SKIP_VREF_CAL) "false"
set ip_params(DIAG_DDRT_CAL_ADDR0) "0"
set ip_params(DIAG_DDRT_CAL_ADDR1) "8"
set ip_params(DIAG_DDRT_CAL_ENABLE_NON_DES) "false"
set ip_params(DIAG_DDRT_CAL_FULL_CAL_ON_RESET) "true"
set ip_params(DIAG_DDRT_ENABLE_ENHANCED_TESTING) "false"
set ip_params(DIAG_DDRT_ENABLE_DRIVER_MARGINING) "false"
set ed_params(NUM_IPS) "1"
set ed_params(EMIF_0_CONN_TO_CALIP) "0"
set ed_params(EMIF_0_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_1_CONN_TO_CALIP) "0"
set ed_params(EMIF_1_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_2_CONN_TO_CALIP) "0"
set ed_params(EMIF_2_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_3_CONN_TO_CALIP) "0"
set ed_params(EMIF_3_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_4_CONN_TO_CALIP) "0"
set ed_params(EMIF_4_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_5_CONN_TO_CALIP) "0"
set ed_params(EMIF_5_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_6_CONN_TO_CALIP) "0"
set ed_params(EMIF_6_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_7_CONN_TO_CALIP) "0"
set ed_params(EMIF_7_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_8_CONN_TO_CALIP) "0"
set ed_params(EMIF_8_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_9_CONN_TO_CALIP) "0"
set ed_params(EMIF_9_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_10_CONN_TO_CALIP) "0"
set ed_params(EMIF_10_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_11_CONN_TO_CALIP) "0"
set ed_params(EMIF_11_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_12_CONN_TO_CALIP) "0"
set ed_params(EMIF_12_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_13_CONN_TO_CALIP) "0"
set ed_params(EMIF_13_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_14_CONN_TO_CALIP) "0"
set ed_params(EMIF_14_REF_CLK_SHARING) "EXPORTED"
set ed_params(EMIF_15_CONN_TO_CALIP) "0"
set ed_params(EMIF_15_REF_CLK_SHARING) "EXPORTED"
set ip_params(EX_DESIGN_GUI_GEN_SIM) "true"
set ip_params(EX_DESIGN_GUI_GEN_SYNTH) "true"
set ip_params(EX_DESIGN_GUI_GEN_BSI) "false"
set ip_params(EX_DESIGN_GUI_GEN_CDC) "false"
set ip_params(EX_DESIGN_GUI_TARGET_DEV_KIT) "TARGET_DEV_KIT_NONE"
set ed_params(NUM_IPS_SAVED) "0"
set ip_params(EX_DESIGN_GUI_PREV_PRESET) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_DDR3_SEL_DESIGN) "AVAIL_EX_DESIGNS_GEN_DESIGN"
set ip_params(EX_DESIGN_GUI_DDR3_GEN_SIM) "true"
set ip_params(EX_DESIGN_GUI_DDR3_GEN_SYNTH) "true"
set ip_params(EX_DESIGN_GUI_DDR3_GEN_BSI) "false"
set ip_params(EX_DESIGN_GUI_DDR3_GEN_CDC) "false"
set ip_params(EX_DESIGN_GUI_DDR3_HDL_FORMAT) "HDL_FORMAT_VERILOG"
set ip_params(EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_DDR3_PREV_PRESET) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_DDR4_SEL_DESIGN) "AVAIL_EX_DESIGNS_GEN_DESIGN"
set ip_params(EX_DESIGN_GUI_DDR4_GEN_SIM) "true"
set ip_params(EX_DESIGN_GUI_DDR4_GEN_SYNTH) "true"
set ip_params(EX_DESIGN_GUI_DDR4_GEN_BSI) "false"
set ip_params(EX_DESIGN_GUI_DDR4_GEN_CDC) "false"
set ip_params(EX_DESIGN_GUI_DDR4_HDL_FORMAT) "HDL_FORMAT_VERILOG"
set ip_params(EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_DDR4_PREV_PRESET) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_QDR2_SEL_DESIGN) "AVAIL_EX_DESIGNS_GEN_DESIGN"
set ip_params(EX_DESIGN_GUI_QDR2_GEN_SIM) "true"
set ip_params(EX_DESIGN_GUI_QDR2_GEN_SYNTH) "true"
set ip_params(EX_DESIGN_GUI_QDR2_GEN_BSI) "false"
set ip_params(EX_DESIGN_GUI_QDR2_GEN_CDC) "false"
set ip_params(EX_DESIGN_GUI_QDR2_HDL_FORMAT) "HDL_FORMAT_VERILOG"
set ip_params(EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_QDR2_PREV_PRESET) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_QDR4_SEL_DESIGN) "AVAIL_EX_DESIGNS_GEN_DESIGN"
set ip_params(EX_DESIGN_GUI_QDR4_GEN_SIM) "true"
set ip_params(EX_DESIGN_GUI_QDR4_GEN_SYNTH) "true"
set ip_params(EX_DESIGN_GUI_QDR4_GEN_BSI) "false"
set ip_params(EX_DESIGN_GUI_QDR4_GEN_CDC) "false"
set ip_params(EX_DESIGN_GUI_QDR4_HDL_FORMAT) "HDL_FORMAT_VERILOG"
set ip_params(EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_QDR4_PREV_PRESET) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_RLD2_SEL_DESIGN) "AVAIL_EX_DESIGNS_GEN_DESIGN"
set ip_params(EX_DESIGN_GUI_RLD2_GEN_SIM) "true"
set ip_params(EX_DESIGN_GUI_RLD2_GEN_SYNTH) "true"
set ip_params(EX_DESIGN_GUI_RLD2_GEN_BSI) "false"
set ip_params(EX_DESIGN_GUI_RLD2_GEN_CDC) "false"
set ip_params(EX_DESIGN_GUI_RLD2_HDL_FORMAT) "HDL_FORMAT_VERILOG"
set ip_params(EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_RLD2_PREV_PRESET) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_RLD3_SEL_DESIGN) "AVAIL_EX_DESIGNS_GEN_DESIGN"
set ip_params(EX_DESIGN_GUI_RLD3_GEN_SIM) "true"
set ip_params(EX_DESIGN_GUI_RLD3_GEN_SYNTH) "true"
set ip_params(EX_DESIGN_GUI_RLD3_GEN_BSI) "false"
set ip_params(EX_DESIGN_GUI_RLD3_GEN_CDC) "false"
set ip_params(EX_DESIGN_GUI_RLD3_HDL_FORMAT) "HDL_FORMAT_VERILOG"
set ip_params(EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_RLD3_PREV_PRESET) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_LPDDR3_SEL_DESIGN) "AVAIL_EX_DESIGNS_GEN_DESIGN"
set ip_params(EX_DESIGN_GUI_LPDDR3_GEN_SIM) "true"
set ip_params(EX_DESIGN_GUI_LPDDR3_GEN_SYNTH) "true"
set ip_params(EX_DESIGN_GUI_LPDDR3_GEN_BSI) "false"
set ip_params(EX_DESIGN_GUI_LPDDR3_GEN_CDC) "false"
set ip_params(EX_DESIGN_GUI_LPDDR3_HDL_FORMAT) "HDL_FORMAT_VERILOG"
set ip_params(EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_LPDDR3_PREV_PRESET) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_DDRT_SEL_DESIGN) "AVAIL_EX_DESIGNS_GEN_DESIGN"
set ip_params(EX_DESIGN_GUI_DDRT_GEN_SIM) "true"
set ip_params(EX_DESIGN_GUI_DDRT_GEN_SYNTH) "true"
set ip_params(EX_DESIGN_GUI_DDRT_GEN_BSI) "false"
set ip_params(EX_DESIGN_GUI_DDRT_GEN_CDC) "false"
set ip_params(EX_DESIGN_GUI_DDRT_HDL_FORMAT) "HDL_FORMAT_VERILOG"
set ip_params(EX_DESIGN_GUI_DDRT_TARGET_DEV_KIT) "TARGET_DEV_KIT_NONE"
set ip_params(EX_DESIGN_GUI_DDRT_PREV_PRESET) "TARGET_DEV_KIT_NONE"
set ed_params(GUI) 1
set ip_params(SHORT_QSYS_INTERFACE_NAMES) "true"
set ed_params(EMIF_MODULE_NAME)           "altera_emif"
set ed_params(EMIF_NAME)                  "emif_0"
set ed_params(DEFAULT_DEVICE)             "10AX022C3U19I2SG"
set ed_params(SYNTH_QSYS_NAME)            "ed_synth"
set ed_params(SIM_QSYS_NAME)              "ed_sim"
set ed_params(TMP_SYNTH_QSYS_PATH)        "C:/Users/kcm/AppData/Local/Temp/alt9088_5772947488816820061.dir/0028_emif_0_gen/ed_synth.qsys"
set ed_params(TMP_SYNTH_BCM_QSYS_PATH)    "C:/Users/kcm/AppData/Local/Temp/alt9088_5772947488816820061.dir/0028_emif_0_gen/ed_synth_bcm.qsys"
set ed_params(TMP_SIM_QSYS_PATH)          "C:/Users/kcm/AppData/Local/Temp/alt9088_5772947488816820061.dir/0028_emif_0_gen/ed_sim.qsys"
set ed_params(SYSTEM_CONSOLE_DESIGN_ID)   "emif__ed_synth__a10"
