ed_synth_tg |

2022.04.06.02:14:12 | Datasheet

Overview

Memory Map

| tg
ctrl_amm_0

## tg

altera_emif_tg_avl v19.1

## Parameters
MEGAFUNC_DEVICE_FAMILY | ARRIA 10
NUM_OF_CTRL_PORTS | 1
SEPARATE_READ_WRITE_IFS | 0
CTRL_AVL_PROTOCOL_ENUM | CTRL_AVL_PROTOCOL_MM
USE_AVL_BYTEEN | 1
AMM_WORD_ADDRESS_WIDTH | 25
AMM_WORD_ADDRESS_DIVISIBLE_BY | 1
AMM_BURST_COUNT_DIVISIBLE_BY | 1
USE_SIM_MEM_VALIDATION_TG | false
USE_SIMPLE_TG | false
TEST_DURATION | SHORT
PORT_CTRL_AMM_ADDRESS_WIDTH | 30
PORT_CTRL_AMM_RDATA_WIDTH | 256
PORT_CTRL_AMM_WDATA_WIDTH | 256
PORT_CTRL_AMM_BCOUNT_WIDTH | 7
PORT_CTRL_AMM_BYTEEN_WIDTH | 32
PORT_CTRL_MMR_MASTER_ADDRESS_WIDTH | 10
PORT_CTRL_MMR_MASTER_RDATA_WIDTH | 32
PORT_CTRL_MMR_MASTER_WDATA_WIDTH | 32
PORT_CTRL_MMR_MASTER_BCOUNT_WIDTH | 2
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

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