// ed_sim_pll_ref_clk_source.v

// Generated using ACDS version 21.3 170

`timescale 1 ps / 1 ps
module ed_sim_pll_ref_clk_source #(
		parameter CLOCK_RATE = 200000000,
		parameter CLOCK_UNIT = 1
	) (
		output wire  clk  // clk.clk
	);

	altera_avalon_clock_source #(
		.CLOCK_RATE (CLOCK_RATE),
		.CLOCK_UNIT (CLOCK_UNIT)
	) pll_ref_clk_source (
		.clk (clk)  //  output,  width = 1, clk.clk
	);

endmodule
