// ed_sim_altera_mm_interconnect_1920_lpnfwuy.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 21.3 170

`timescale 1 ps / 1 ps
module ed_sim_altera_mm_interconnect_1920_lpnfwuy (
		input  wire [29:0]  tg_ctrl_amm_0_address,                                      //                                        tg_ctrl_amm_0.address
		output wire         tg_ctrl_amm_0_waitrequest,                                  //                                                     .waitrequest
		input  wire [6:0]   tg_ctrl_amm_0_burstcount,                                   //                                                     .burstcount
		input  wire [31:0]  tg_ctrl_amm_0_byteenable,                                   //                                                     .byteenable
		input  wire         tg_ctrl_amm_0_read,                                         //                                                     .read
		output wire [255:0] tg_ctrl_amm_0_readdata,                                     //                                                     .readdata
		output wire         tg_ctrl_amm_0_readdatavalid,                                //                                                     .readdatavalid
		input  wire         tg_ctrl_amm_0_write,                                        //                                                     .write
		input  wire [255:0] tg_ctrl_amm_0_writedata,                                    //                                                     .writedata
		output wire [24:0]  emif_0_ctrl_amm_0_address,                                  //                                    emif_0_ctrl_amm_0.address
		output wire         emif_0_ctrl_amm_0_write,                                    //                                                     .write
		output wire         emif_0_ctrl_amm_0_read,                                     //                                                     .read
		input  wire [255:0] emif_0_ctrl_amm_0_readdata,                                 //                                                     .readdata
		output wire [255:0] emif_0_ctrl_amm_0_writedata,                                //                                                     .writedata
		output wire [6:0]   emif_0_ctrl_amm_0_burstcount,                               //                                                     .burstcount
		output wire [31:0]  emif_0_ctrl_amm_0_byteenable,                               //                                                     .byteenable
		input  wire         emif_0_ctrl_amm_0_readdatavalid,                            //                                                     .readdatavalid
		input  wire         emif_0_ctrl_amm_0_waitrequest,                              //                                                     .waitrequest
		input  wire         tg_ctrl_amm_0_translator_reset_reset_bridge_in_reset_reset, // tg_ctrl_amm_0_translator_reset_reset_bridge_in_reset.reset
		input  wire         emif_0_emif_usr_clk_clk                                     //                                  emif_0_emif_usr_clk.clk
	);

	wire          tg_ctrl_amm_0_translator_avalon_universal_master_0_waitrequest;   // emif_0_ctrl_amm_0_translator:uav_waitrequest -> tg_ctrl_amm_0_translator:uav_waitrequest
	wire  [255:0] tg_ctrl_amm_0_translator_avalon_universal_master_0_readdata;      // emif_0_ctrl_amm_0_translator:uav_readdata -> tg_ctrl_amm_0_translator:uav_readdata
	wire          tg_ctrl_amm_0_translator_avalon_universal_master_0_debugaccess;   // tg_ctrl_amm_0_translator:uav_debugaccess -> emif_0_ctrl_amm_0_translator:uav_debugaccess
	wire   [29:0] tg_ctrl_amm_0_translator_avalon_universal_master_0_address;       // tg_ctrl_amm_0_translator:uav_address -> emif_0_ctrl_amm_0_translator:uav_address
	wire          tg_ctrl_amm_0_translator_avalon_universal_master_0_read;          // tg_ctrl_amm_0_translator:uav_read -> emif_0_ctrl_amm_0_translator:uav_read
	wire   [31:0] tg_ctrl_amm_0_translator_avalon_universal_master_0_byteenable;    // tg_ctrl_amm_0_translator:uav_byteenable -> emif_0_ctrl_amm_0_translator:uav_byteenable
	wire          tg_ctrl_amm_0_translator_avalon_universal_master_0_readdatavalid; // emif_0_ctrl_amm_0_translator:uav_readdatavalid -> tg_ctrl_amm_0_translator:uav_readdatavalid
	wire          tg_ctrl_amm_0_translator_avalon_universal_master_0_lock;          // tg_ctrl_amm_0_translator:uav_lock -> emif_0_ctrl_amm_0_translator:uav_lock
	wire          tg_ctrl_amm_0_translator_avalon_universal_master_0_write;         // tg_ctrl_amm_0_translator:uav_write -> emif_0_ctrl_amm_0_translator:uav_write
	wire  [255:0] tg_ctrl_amm_0_translator_avalon_universal_master_0_writedata;     // tg_ctrl_amm_0_translator:uav_writedata -> emif_0_ctrl_amm_0_translator:uav_writedata
	wire   [11:0] tg_ctrl_amm_0_translator_avalon_universal_master_0_burstcount;    // tg_ctrl_amm_0_translator:uav_burstcount -> emif_0_ctrl_amm_0_translator:uav_burstcount

	ed_sim_altera_merlin_master_translator_191_g7h47bq #(
		.AV_ADDRESS_W                (30),
		.AV_DATA_W                   (256),
		.AV_BURSTCOUNT_W             (7),
		.AV_BYTEENABLE_W             (32),
		.UAV_ADDRESS_W               (30),
		.UAV_BURSTCOUNT_W            (12),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (32),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (1),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0),
		.SYNC_RESET                  (0),
		.WAITREQUEST_ALLOWANCE       (0)
	) tg_ctrl_amm_0_translator (
		.clk                    (emif_0_emif_usr_clk_clk),                                          //   input,    width = 1,                       clk.clk
		.reset                  (tg_ctrl_amm_0_translator_reset_reset_bridge_in_reset_reset),       //   input,    width = 1,                     reset.reset
		.uav_address            (tg_ctrl_amm_0_translator_avalon_universal_master_0_address),       //  output,   width = 30, avalon_universal_master_0.address
		.uav_burstcount         (tg_ctrl_amm_0_translator_avalon_universal_master_0_burstcount),    //  output,   width = 12,                          .burstcount
		.uav_read               (tg_ctrl_amm_0_translator_avalon_universal_master_0_read),          //  output,    width = 1,                          .read
		.uav_write              (tg_ctrl_amm_0_translator_avalon_universal_master_0_write),         //  output,    width = 1,                          .write
		.uav_waitrequest        (tg_ctrl_amm_0_translator_avalon_universal_master_0_waitrequest),   //   input,    width = 1,                          .waitrequest
		.uav_readdatavalid      (tg_ctrl_amm_0_translator_avalon_universal_master_0_readdatavalid), //   input,    width = 1,                          .readdatavalid
		.uav_byteenable         (tg_ctrl_amm_0_translator_avalon_universal_master_0_byteenable),    //  output,   width = 32,                          .byteenable
		.uav_readdata           (tg_ctrl_amm_0_translator_avalon_universal_master_0_readdata),      //   input,  width = 256,                          .readdata
		.uav_writedata          (tg_ctrl_amm_0_translator_avalon_universal_master_0_writedata),     //  output,  width = 256,                          .writedata
		.uav_lock               (tg_ctrl_amm_0_translator_avalon_universal_master_0_lock),          //  output,    width = 1,                          .lock
		.uav_debugaccess        (tg_ctrl_amm_0_translator_avalon_universal_master_0_debugaccess),   //  output,    width = 1,                          .debugaccess
		.av_address             (tg_ctrl_amm_0_address),                                            //   input,   width = 30,      avalon_anti_master_0.address
		.av_waitrequest         (tg_ctrl_amm_0_waitrequest),                                        //  output,    width = 1,                          .waitrequest
		.av_burstcount          (tg_ctrl_amm_0_burstcount),                                         //   input,    width = 7,                          .burstcount
		.av_byteenable          (tg_ctrl_amm_0_byteenable),                                         //   input,   width = 32,                          .byteenable
		.av_read                (tg_ctrl_amm_0_read),                                               //   input,    width = 1,                          .read
		.av_readdata            (tg_ctrl_amm_0_readdata),                                           //  output,  width = 256,                          .readdata
		.av_readdatavalid       (tg_ctrl_amm_0_readdatavalid),                                      //  output,    width = 1,                          .readdatavalid
		.av_write               (tg_ctrl_amm_0_write),                                              //   input,    width = 1,                          .write
		.av_writedata           (tg_ctrl_amm_0_writedata),                                          //   input,  width = 256,                          .writedata
		.av_beginbursttransfer  (1'b0),                                                             // (terminated),                                         
		.av_begintransfer       (1'b0),                                                             // (terminated),                                         
		.av_chipselect          (1'b0),                                                             // (terminated),                                         
		.av_lock                (1'b0),                                                             // (terminated),                                         
		.av_debugaccess         (1'b0),                                                             // (terminated),                                         
		.uav_clken              (),                                                                 // (terminated),                                         
		.av_clken               (1'b1),                                                             // (terminated),                                         
		.uav_response           (2'b00),                                                            // (terminated),                                         
		.av_response            (),                                                                 // (terminated),                                         
		.uav_writeresponsevalid (1'b0),                                                             // (terminated),                                         
		.av_writeresponsevalid  ()                                                                  // (terminated),                                         
	);

	ed_sim_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (25),
		.AV_DATA_W                      (256),
		.UAV_DATA_W                     (256),
		.AV_BURSTCOUNT_W                (7),
		.AV_BYTEENABLE_W                (32),
		.UAV_BYTEENABLE_W               (32),
		.UAV_ADDRESS_W                  (30),
		.UAV_BURSTCOUNT_W               (12),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (32),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) emif_0_ctrl_amm_0_translator (
		.clk                    (emif_0_emif_usr_clk_clk),                                          //   input,    width = 1,                      clk.clk
		.reset                  (tg_ctrl_amm_0_translator_reset_reset_bridge_in_reset_reset),       //   input,    width = 1,                    reset.reset
		.uav_address            (tg_ctrl_amm_0_translator_avalon_universal_master_0_address),       //   input,   width = 30, avalon_universal_slave_0.address
		.uav_burstcount         (tg_ctrl_amm_0_translator_avalon_universal_master_0_burstcount),    //   input,   width = 12,                         .burstcount
		.uav_read               (tg_ctrl_amm_0_translator_avalon_universal_master_0_read),          //   input,    width = 1,                         .read
		.uav_write              (tg_ctrl_amm_0_translator_avalon_universal_master_0_write),         //   input,    width = 1,                         .write
		.uav_waitrequest        (tg_ctrl_amm_0_translator_avalon_universal_master_0_waitrequest),   //  output,    width = 1,                         .waitrequest
		.uav_readdatavalid      (tg_ctrl_amm_0_translator_avalon_universal_master_0_readdatavalid), //  output,    width = 1,                         .readdatavalid
		.uav_byteenable         (tg_ctrl_amm_0_translator_avalon_universal_master_0_byteenable),    //   input,   width = 32,                         .byteenable
		.uav_readdata           (tg_ctrl_amm_0_translator_avalon_universal_master_0_readdata),      //  output,  width = 256,                         .readdata
		.uav_writedata          (tg_ctrl_amm_0_translator_avalon_universal_master_0_writedata),     //   input,  width = 256,                         .writedata
		.uav_lock               (tg_ctrl_amm_0_translator_avalon_universal_master_0_lock),          //   input,    width = 1,                         .lock
		.uav_debugaccess        (tg_ctrl_amm_0_translator_avalon_universal_master_0_debugaccess),   //   input,    width = 1,                         .debugaccess
		.av_address             (emif_0_ctrl_amm_0_address),                                        //  output,   width = 25,      avalon_anti_slave_0.address
		.av_write               (emif_0_ctrl_amm_0_write),                                          //  output,    width = 1,                         .write
		.av_read                (emif_0_ctrl_amm_0_read),                                           //  output,    width = 1,                         .read
		.av_readdata            (emif_0_ctrl_amm_0_readdata),                                       //   input,  width = 256,                         .readdata
		.av_writedata           (emif_0_ctrl_amm_0_writedata),                                      //  output,  width = 256,                         .writedata
		.av_burstcount          (emif_0_ctrl_amm_0_burstcount),                                     //  output,    width = 7,                         .burstcount
		.av_byteenable          (emif_0_ctrl_amm_0_byteenable),                                     //  output,   width = 32,                         .byteenable
		.av_readdatavalid       (emif_0_ctrl_amm_0_readdatavalid),                                  //   input,    width = 1,                         .readdatavalid
		.av_waitrequest         (emif_0_ctrl_amm_0_waitrequest),                                    //   input,    width = 1,                         .waitrequest
		.av_begintransfer       (),                                                                 // (terminated),                                        
		.av_beginbursttransfer  (),                                                                 // (terminated),                                        
		.av_writebyteenable     (),                                                                 // (terminated),                                        
		.av_lock                (),                                                                 // (terminated),                                        
		.av_chipselect          (),                                                                 // (terminated),                                        
		.av_clken               (),                                                                 // (terminated),                                        
		.uav_clken              (1'b0),                                                             // (terminated),                                        
		.av_debugaccess         (),                                                                 // (terminated),                                        
		.av_outputenable        (),                                                                 // (terminated),                                        
		.uav_response           (),                                                                 // (terminated),                                        
		.av_response            (2'b00),                                                            // (terminated),                                        
		.uav_writeresponsevalid (),                                                                 // (terminated),                                        
		.av_writeresponsevalid  (1'b0)                                                              // (terminated),                                        
	);

endmodule
