`timescale	1ns/100ps

module AC_main_tb;

wire[15:0]	data_LTC1668;
wire			clk_LTC1668;

wire			mclk_DDS;
wire			ctrl_DDS;
wire			sclk_DDS;
wire			sdata_DDS;
wire			fsync_DDS;
wire			int_DDS;
reg			dds_out;

reg 			clk=0;
reg 			res;
wire			mosi;
reg			clk_PC;
reg			data_PC;
reg			cs_PC;
reg[127:0]	data_for_DDS;
integer		i;

parameter interval=100;
parameter in_tact=200;

main main_inst(
	.data_LTC1668(data_LTC1668),
	.clk_LTC1668(clk_LTC1668),
	.sdin_AD5791(),
	.sclk_AD5791(),
	.sync_AD5791_n(),
	.ldac_AD5791_n(),
	.clr_AD5791_n(),
	.reset_AD5791_n(),
	.mclk_DDS(mclk_DDS),
	.ctrl_DDS(ctrl_DDS),
	.sclk_DDS(sclk_DDS),
	.sdata_DDS(sdata_DDS),
	.fsync_DDS(fsync_DDS),
	.int_DDS(int_DDS),
	.dds_out(dds_out),
	.external_reset_n(res),
	.clk_50MHz_in(clk),
	.leds(),
	.switches(),
	.clk_PC(clk_PC),
	.data_PC(data_PC),
	.cs_PC(cs_PC)
);

initial
begin
	//$dumpfile("AC_main_tb.vcd");
	//$dumpvars(0, tb);
	data_for_DDS=128'h09D3C555D55520003000100200002710;	//младшие 2 слова (32 бита) это частота. h00002710=10000Гц
	cs_PC=1;
	data_PC=0;
	clk_PC=0;
	res=0;
	#400;		//400ns
	res=1;
	#600;		//1us
	cs_PC=0;
	for(i=0;i<128;i=i+1)
	begin
		data_PC=data_for_DDS[127];
		data_for_DDS=data_for_DDS<<1;
		#in_tact;
		clk_PC=1;
		#in_tact;
		clk_PC=0;
	end
	#in_tact;
	cs_PC=1;

	#100000;
	$stop;
end

always
	#10 clk=~clk;

endmodule