Model {
  Name			  "progetto_nuovo"
  Version		  6.4
  MdlSubVersion		  0
  GraphicalInterface {
    NumRootInports	    0
    NumRootOutports	    0
    ParameterArgumentNames  ""
    ComputedModelVersion    "1.88"
    NumModelReferences	    0
    NumTestPointedSignals   0
  }
  SavedCharacterEncoding  "windows-1252"
  SaveDefaultBlockParams  on
  SampleTimeColors	  off
  LibraryLinkDisplay	  "none"
  WideLines		  off
  ShowLineDimensions	  on
  ShowPortDataTypes	  on
  ShowLoopsOnError	  on
  IgnoreBidirectionalLines off
  ShowStorageClass	  off
  ShowTestPointIcons	  on
  ShowViewerIcons	  on
  SortedOrder		  off
  ExecutionContextIcon	  off
  ShowLinearizationAnnotations on
  ScopeRefreshTime	  0.035000
  OverrideScopeRefreshTime on
  DisableAllScopes	  off
  DataTypeOverride	  "UseLocalSettings"
  MinMaxOverflowLogging	  "UseLocalSettings"
  MinMaxOverflowArchiveMode "Overwrite"
  BlockNameDataTip	  off
  BlockParametersDataTip  off
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks off
  BrowserLookUnderMasks	  off
  CloseFcn		  "rtwprivate ssgencode ModelCloseRequest progetto"
  InitFcn		  "%% DSPBuilder Start\nalt_dspbuilder_update_model(bd"
"root)\n%% DSPBuilder End\n"
  Created		  "Mon Nov 19 08:35:45 2007"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "Matteo"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Mon Nov 10 17:09:26 2008"
  ModelVersionFormat	  "1.%<AutoIncrement:88>"
  ConfigurationManager	  "None"
  LinearizationMsg	  "none"
  Profile		  off
  ParamWorkspaceSource	  "MATLABWorkspace"
  AccelSystemTargetFile	  "accel.tlc"
  AccelTemplateMakefile	  "accel_default_tmf"
  AccelMakeCommand	  "make_rtw"
  TryForcingSFcnDF	  off
  RecordCoverage	  off
  CovPath		  "/"
  CovSaveName		  "covdata"
  CovMetricSettings	  "dw"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  covSaveCumulativeToWorkspaceVar on
  CovSaveSingleToWorkspaceVar on
  CovCumulativeVarName	  "covCumulativeData"
  CovCumulativeReport	  off
  CovReportOnPause	  on
  ExtModeBatchMode	  off
  ExtModeEnableFloating	  on
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "normal"
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  ExtModeTrigElement	  "any"
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  ExtModeTrigDurationFloating "auto"
  ExtModeTrigHoldOff	  0
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  ExtModeTrigDirection	  "rising"
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  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  on
  ExtModeSkipDownloadWhenConnect off
  ExtModeLogAll		  on
  ExtModeAutoUpdateStatusClock on
  BufferReuse		  on
  ProdHWDeviceType	  "32-bit Generic"
  ShowModelReferenceBlockVersion off
  ShowModelReferenceBlockIO off
  Array {
    Type		    "Handle"
    Dimension		    1
    Simulink.ConfigSet {
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      Version		      "1.2.0"
      Array {
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	  ConsecutiveZCsStepRelTol "10*128*eps"
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	  MaxDataPoints		  "1000"
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	  SaveFormat		  "Array"
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	  OutputOption		  "RefineOutputTimes"
	  OutputTimes		  "[]"
	  Refine		  "1"
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	Simulink.OptimizationCC {
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	  Array {
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	    Dimension		    5
	    Cell		    "ZeroExternalMemoryAtStartup"
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	    Cell		    "InitFltsAndDblsToZero"
	    Cell		    "OptimizeModelRefInitCode"
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	    PropName		    "DisabledProps"
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	  Version		  "1.2.0"
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	  ZeroExternalMemoryAtStartup on
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	  EfficientFloat2IntCast  off
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	  LifeSpan		  "inf"
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	Simulink.DebuggingCC {
	  $ObjectID		  5
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	  SignalInfNanChecking	  "none"
	  ReadBeforeWriteMsg	  "UseLocalSettings"
	  WriteAfterWriteMsg	  "UseLocalSettings"
	  WriteAfterReadMsg	  "UseLocalSettings"
	  AlgebraicLoopMsg	  "warning"
	  ArtificialAlgebraicLoopMsg "warning"
	  CheckSSInitialOutputMsg on
	  CheckExecutionContextPreStartOutputMsg off
	  CheckExecutionContextRuntimeOutputMsg	off
	  SignalResolutionControl "TryResolveAllWithWarning"
	  BlockPriorityViolationMsg "warning"
	  MinStepSizeMsg	  "warning"
	  MaxConsecutiveZCsMsg	  "error"
	  SolverPrmCheckMsg	  "warning"
	  InheritedTsInSrcMsg	  "warning"
	  DiscreteInheritContinuousMsg "warning"
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	  MultiTaskRateTransMsg	  "error"
	  SingleTaskRateTransMsg  "none"
	  TasksWithSamePriorityMsg "warning"
	  SigSpecEnsureSampleTimeMsg "warning"
	  CheckMatrixSingularityMsg "none"
	  IntegerOverflowMsg	  "warning"
	  Int32ToFloatConvMsg	  "warning"
	  ParameterDowncastMsg	  "error"
	  ParameterOverflowMsg	  "error"
	  ParameterUnderflowMsg	  "none"
	  ParameterPrecisionLossMsg "warning"
	  UnderSpecifiedDataTypeMsg "none"
	  UnnecessaryDatatypeConvMsg "none"
	  VectorMatrixConversionMsg "none"
	  InvalidFcnCallConnMsg	  "error"
	  FcnCallInpInsideContextMsg "Use local settings"
	  SignalLabelMismatchMsg  "none"
	  UnconnectedInputMsg	  "warning"
	  UnconnectedOutputMsg	  "warning"
	  UnconnectedLineMsg	  "warning"
	  SFcnCompatibilityMsg	  "none"
	  UniqueDataStoreMsg	  "none"
	  BusObjectLabelMismatch  "warning"
	  RootOutportRequireBusObject "warning"
	  AssertControl		  "UseLocalSettings"
	  EnableOverflowDetection off
	  ModelReferenceIOMsg	  "none"
	  ModelReferenceVersionMismatchMessage "none"
	  ModelReferenceIOMismatchMessage "none"
	  ModelReferenceCSMismatchMessage "none"
	  ModelReferenceSimTargetVerbose off
	  UnknownTsInhSupMsg	  "warning"
	  ModelReferenceDataLoggingMessage "warning"
	  ModelReferenceSymbolNameMessage "warning"
	  ModelReferenceExtraNoncontSigs "error"
	  StrictBusMsg		  "Warning"
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	Simulink.HardwareCC {
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	  ProdBitPerLong	  32
	  ProdIntDivRoundTo	  "Undefined"
	  ProdEndianess		  "Unspecified"
	  ProdWordSize		  32
	  ProdShiftRightIntArith  on
	  ProdHWDeviceType	  "32-bit Generic"
	  TargetBitPerChar	  8
	  TargetBitPerShort	  16
	  TargetBitPerInt	  32
	  TargetBitPerLong	  32
	  TargetShiftRightIntArith on
	  TargetIntDivRoundTo	  "Undefined"
	  TargetEndianess	  "Unspecified"
	  TargetWordSize	  32
	  TargetTypeEmulationWarnSuppressLevel 0
	  TargetPreprocMaxBitsSint 32
	  TargetPreprocMaxBitsUint 32
	  TargetHWDeviceType	  "Specified"
	  TargetUnknown		  off
	  ProdEqTarget		  on
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	Simulink.ModelReferenceCC {
	  $ObjectID		  7
	  Version		  "1.2.0"
	  UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange"
	  CheckModelReferenceTargetMessage "error"
	  ModelReferenceNumInstancesAllowed "Multi"
	  ModelReferencePassRootInputsByReference on
	  ModelReferenceMinAlgLoopOccurrences off
	}
	Simulink.RTWCC {
	  $BackupClass		  "Simulink.RTWCC"
	  $ObjectID		  8
	  Array {
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	    Cell		    "IncludeHyperlinkInReport"
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	  Version		  "1.2.0"
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	  MakeCommand		  "make_rtw"
	  GenerateMakefile	  on
	  TemplateMakefile	  "grt_default_tmf"
	  GenerateReport	  off
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	  RetainRTWFile		  off
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	  ProcessScriptMode	  "Default"
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	  ConfigAtBuild		  off
	  IncludeHyperlinkInReport off
	  LaunchReport		  off
	  TargetLang		  "C"
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	  Array {
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	    Simulink.CodeAppCC {
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		Cell			"IgnoreCustomStorageClasses"
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		Cell			"DefineNamingRule"
		Cell			"SignalNamingRule"
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		Cell			"InlinedPrmAccess"
		Cell			"CustomSymbolStr"
		Cell			"CustomSymbolStrGlobalVar"
		Cell			"CustomSymbolStrType"
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	      Version		      "1.2.0"
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	      CustomSymbolStrGlobalVar "$R$N$M"
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	    Simulink.GRTTargetCC {
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	      Array {
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	      Version		      "1.2.0"
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	    PropName		    "Components"
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    PropName		    "ConfigurationSets"
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  BlockDefaults {
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    FontName		    "Arial"
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    Block {
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    Block {
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      ConvertRealWorld	      "Real World Value (RWV)"
      RndMeth		      "Zero"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      DiscretePulseGenerator
      PulseType		      "Sample based"
      TimeSource	      "Use simulation time"
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      Period		      "2"
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      PhaseDelay	      "0"
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    Block {
      BlockType		      Inport
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      BusObject		      "BusObject"
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      SignalType	      "auto"
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      LatchByDelayingOutsideSignal off
      LatchByCopyingInsideSignal off
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    Block {
      BlockType		      Math
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    Block {
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      BusObject		      "BusObject"
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      PortDimensions	      "-1"
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      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
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    Block {
      BlockType		      Product
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      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Zero"
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      SampleTime	      "-1"
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    Block {
      BlockType		      Scope
      ModelBased	      off
      TickLabels	      "OneTimeTick"
      ZoomMode		      "on"
      Grid		      "on"
      TimeRange		      "auto"
      YMin		      "-5"
      YMax		      "5"
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      SaveName		      "ScopeData"
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      MaxDataPoints	      "5000"
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      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
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    Block {
      BlockType		      Sin
      SineType		      "Time based"
      TimeSource	      "Use simulation time"
      Amplitude		      "1"
      Bias		      "0"
      Frequency		      "1"
      Phase		      "0"
      Samples		      "10"
      Offset		      "0"
      SampleTime	      "-1"
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    Block {
      BlockType		      SubSystem
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      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      TreatAsAtomicUnit	      off
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
      Inputs		      "++"
      InputSameDT	      on
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    ModelBrowserWidth	    200
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      Ports		      [1, 1]
      Position		      [170, 515, 220, 565]
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      SourceType	      "Buffer"
      N			      "256"
      V			      "0"
      ic		      "0"
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      Position		      [75, 25, 125, 43]
      ForegroundColor	      "blue"
      SourceBlock	      "allblocks_alteradspbuilder2/Clock"
      SourceType	      "BaseClock AlteraBlockset"
      ClockPeriod	      "1"
      ClockPeriodUnit	      "us"
      SampleTime	      "0.001"
      SimulationStartCycle    "5"
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      Reset		      "aclr"
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      Export		      off
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    Block {
      BlockType		      ComplexToRealImag
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      Position		      [400, 499, 460, 581]
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      SampleTime	      "inf"
      FramePeriod	      "inf"
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    Block {
      BlockType		      Reference
      Name		      "Cyclone II Development \nand Education Board Co"
"nfiguration "
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      SourceBlock	      "Cyclone_II_DE2_alteradspbuilder2/Cyclone II Dev"
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      SourceType	      "CycloneIIDE2 Configuration AlteraBlockSet"
      ClockPinIn	      "Pin_N2"
      GlobalResetPin	      "PIN_G26"
      device		      "EP2C35F672C6"
    }
    Block {
      BlockType		      Reference
      Name		      "FFT"
      Ports		      [1, 1]
      Position		      [280, 523, 320, 557]
      DialogController	      "dspDDGCreate"
      DialogControllerArgs    "DataTag0"
      SourceBlock	      "dspxfrm3/FFT"
      SourceType	      "FFT"
      CompMethod	      "Table lookup"
      TableOpt		      "Speed"
      BitRevOrder	      off
      additionalParams	      off
      SkipNorm		      on
      allowOverrides	      on
      firstCoeffMode	      "Same word length as input"
      firstCoeffWordLength    "16"
      firstCoeffFracLength    "15"
      outputMode	      "Inherit via internal rule"
      outputWordLength	      "16"
      outputFracLength	      "15"
      accumMode		      "Inherit via internal rule"
      accumWordLength	      "32"
      accumFracLength	      "30"
      prodOutputMode	      "Inherit via internal rule"
      prodOutputWordLength    "32"
      prodOutputFracLength    "30"
      roundingMode	      "Floor"
      overflowMode	      off
      LockScale		      off
    }
    Block {
      BlockType		      Reference
      Name		      "Input"
      Ports		      [1, 1]
      Position		      [210, 191, 265, 209]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Input"
      SourceType	      "Input AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
"rogetto_nuovo\\progetto_nuovo_Input.salt"
      BusType		      "Signed Integer"
      bwl		      "12"
      bwr		      "12"
      SpecifyClock	      on
      clock		      "Clock"
      PORTTYPE		      "Input"
      externalType	      "Inferred"
    }
    Block {
      BlockType		      Reference
      Name		      "Input1"
      Ports		      [1, 1]
      Position		      [450, 72, 515, 88]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Input"
      SourceType	      "Input AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
"rogetto_nuovo\\progetto_nuovo_Input1.salt"
      BusType		      "Single Bit"
      bwl		      "8"
      bwr		      "0"
      SpecifyClock	      off
      clock		      "Clock"
      PORTTYPE		      "Input"
      externalType	      "Inferred"
    }
    Block {
      BlockType		      Reference
      Name		      "Input2"
      Ports		      [1, 1]
      Position		      [455, 252, 520, 268]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Input"
      SourceType	      "Input AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
"rogetto_nuovo\\progetto_nuovo_Input2.salt"
      BusType		      "Signed Integer"
      bwl		      "2"
      bwr		      "12"
      SpecifyClock	      off
      clock		      "Clock"
      PORTTYPE		      "Input"
      externalType	      "Inferred"
    }
    Block {
      BlockType		      Reference
      Name		      "Input3"
      Ports		      [1, 1]
      Position		      [455, 222, 520, 238]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Input"
      SourceType	      "Input AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
"rogetto_nuovo\\progetto_nuovo_Input3.salt"
      BusType		      "Signed Integer"
      bwl		      "12"
      bwr		      "12"
      SpecifyClock	      off
      clock		      "Clock"
      PORTTYPE		      "Input"
      externalType	      "Inferred"
    }
    Block {
      BlockType		      Reference
      Name		      "Input4"
      Ports		      [1, 1]
      Position		      [450, 132, 515, 148]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Input"
      SourceType	      "Input AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
"rogetto_nuovo\\progetto_nuovo_Input4.salt"
      BusType		      "Single Bit"
      bwl		      "8"
      bwr		      "0"
      SpecifyClock	      off
      clock		      "Clock"
      PORTTYPE		      "Input"
      externalType	      "Inferred"
    }
    Block {
      BlockType		      Reference
      Name		      "Input5"
      Ports		      [1, 1]
      Position		      [450, 162, 515, 178]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Input"
      SourceType	      "Input AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
"rogetto_nuovo\\progetto_nuovo_Input5.salt"
      BusType		      "Single Bit"
      bwl		      "8"
      bwr		      "0"
      SpecifyClock	      off
      clock		      "Clock"
      PORTTYPE		      "Input"
      externalType	      "Inferred"
    }
    Block {
      BlockType		      Reference
      Name		      "Integer Delay"
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      Position		      [100, 373, 120, 397]
      ShowName		      off
      SourceBlock	      "simulink/Discrete/Integer Delay"
      SourceType	      "Integer Delay"
      vinit		      "0.0"
      samptime		      "-1"
      NumDelays		      "2"
    }
    Block {
      BlockType		      Reference
      Name		      "Integer Delay1"
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      Position		      [1085, 468, 1100, 492]
      ShowName		      off
      SourceBlock	      "simulink/Discrete/Integer Delay"
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      vinit		      "0.0"
      samptime		      "-1"
      NumDelays		      "232"
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    Block {
      BlockType		      Reference
      Name		      "Matlab FFT Spectrum2"
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      Position		      [200, 415, 235, 465]
      DialogController	      "dspdialog.SpectrumScope"
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      SourceBlock	      "dspsnks4/Spectrum\nScope"
      SourceType	      "Spectrum Scope"
      ShowPortLabels	      off
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      ScopeProperties	      on
      Domain		      "Frequency"
      HorizSpan		      "1"
      UseBuffer		      on
      BufferSize	      "256"
      Overlap		      "0"
      inpFftLenInherit	      on
      FFTlength		      "256"
      numAvg		      "2"
      DisplayProperties	      off
      AxisGrid		      on
      Memory		      off
      FrameNumber	      on
      AxisLegend	      off
      AxisZoom		      off
      OpenScopeAtSimStart     on
      OpenScopeImmediately    off
      FigPos		      "get(0,'defaultfigureposition')"
      AxisProperties	      off
      XUnits		      "Hertz"
      XRange		      "[-Fs/2...Fs/2]"
      InheritXIncr	      on
      XIncr		      "1.0"
      XLabel		      "Samples"
      YUnits		      "dB"
      YMin		      "0"
      YMax		      "100"
      YLabel		      "Magnitude-squared, dB"
      LineProperties	      off
      wintypeSpecScope	      "Hann"
      RsSpecScope	      "50"
      betaSpecScope	      "5"
      winsampSpecScope	      "Symmetric"
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    Block {
      BlockType		      Reference
      Name		      "Output"
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      Position		      [785, 252, 850, 268]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Output"
      SourceType	      "Output AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
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      BusType		      "Inferred"
      bwl		      "12"
      bwr		      "12"
      externalType	      "Inferred"
      PORTTYPE		      "Output"
      Port {
	PortNumber		1
	Name			"Source Real"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
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    }
    Block {
      BlockType		      Reference
      Name		      "Output1"
      Ports		      [1, 1]
      Position		      [785, 287, 850, 303]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Output"
      SourceType	      "Output AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
"rogetto_nuovo\\progetto_nuovo_Output1.capture"
      BusType		      "Inferred"
      bwl		      "12"
      bwr		      "12"
      externalType	      "Inferred"
      PORTTYPE		      "Output"
      Port {
	PortNumber		1
	Name			"Source Imag"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Output12"
      Ports		      [1, 1]
      Position		      [285, 225, 295, 255]
      Orientation	      "down"
      ForegroundColor	      "blue"
      NamePlacement	      "alternate"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Output"
      SourceType	      "Output AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
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      BusType		      "Inferred"
      bwl		      "12"
      bwr		      "12"
      externalType	      "Inferred"
      PORTTYPE		      "Output"
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    Block {
      BlockType		      Reference
      Name		      "Output2"
      Ports		      [1, 1]
      Position		      [785, 217, 850, 233]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Output"
      SourceType	      "Output AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
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      BusType		      "Inferred"
      bwl		      "6"
      bwr		      "6"
      externalType	      "Inferred"
      PORTTYPE		      "Output"
      Port {
	PortNumber		1
	Name			"Source Exp"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
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    }
    Block {
      BlockType		      Reference
      Name		      "Output3"
      Ports		      [1, 1]
      Position		      [785, 112, 850, 128]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Output"
      SourceType	      "Output AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
"rogetto_nuovo\\progetto_nuovo_Output3.capture"
      BusType		      "Single Bit"
      bwl		      "2"
      bwr		      "0"
      externalType	      "Inferred"
      PORTTYPE		      "Output"
      Port {
	PortNumber		1
	Name			"Source Sop"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
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    Block {
      BlockType		      Reference
      Name		      "Output4"
      Ports		      [1, 1]
      Position		      [785, 147, 850, 163]
      ForegroundColor	      "blue"
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      SourceBlock	      "allblocks_alteradspbuilder2/Output"
      SourceType	      "Output AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
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      BusType		      "Single Bit"
      bwl		      "2"
      bwr		      "0"
      externalType	      "Inferred"
      PORTTYPE		      "Output"
      Port {
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	Name			"Source Eop"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
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    Block {
      BlockType		      Reference
      Name		      "Output5"
      Ports		      [1, 1]
      Position		      [785, 182, 850, 198]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Output"
      SourceType	      "Output AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
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      BusType		      "Single Bit"
      bwl		      "2"
      bwr		      "0"
      externalType	      "Inferred"
      PORTTYPE		      "Output"
      Port {
	PortNumber		1
	Name			"Source Valid"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
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    }
    Block {
      BlockType		      Reference
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      Ports		      [1, 1]
      Position		      [785, 77, 850, 93]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Output"
      SourceType	      "Output AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
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      BusType		      "Signed Integer"
      bwl		      "2"
      bwr		      "0"
      externalType	      "Inferred"
      PORTTYPE		      "Output"
      Port {
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	Name			"Source Error"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
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    Block {
      BlockType		      Reference
      Name		      "Output9"
      Ports		      [1, 1]
      Position		      [925, 359, 990, 371]
      ForegroundColor	      "blue"
      ShowName		      off
      SourceBlock	      "allblocks_alteradspbuilder2/Output"
      SourceType	      "Output AlteraBlockset"
      iofile		      "C:\\Programmi\\MATLAB\\R2006a\\work\\Tesi\\tb_p"
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      BusType		      "Inferred"
      bwl		      "12"
      bwr		      "12"
      externalType	      "Inferred"
      PORTTYPE		      "Output"
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    Block {
      BlockType		      SubSystem
      Name		      "Power Spectrum"
      Ports		      [2, 1]
      Position		      [950, 438, 1050, 522]
      BackgroundColor	      "green"
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      MaskHideContents	      off
      System {
	Name			"Power Spectrum"
	Location		[510, 176, 952, 354]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "Real"
	  Position		  [25, 28, 55, 42]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "Imm"
	  Position		  [45, 123, 75, 137]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant"
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	  Value			  "1"
	  VectorParams1D	  on
	  SamplingMode		  "Sample based"
	  OutDataTypeMode	  "Inherit from 'Constant value'"
	  OutDataType		  "sfix(16)"
	  ConRadixGroup		  "Use specified scaling"
	  OutScaling		  "2^0"
	  SampleTime		  "inf"
	  FramePeriod		  "inf"
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	Block {
	  BlockType		  Product
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	  Ports			  [2, 1]
	  Position		  [315, 72, 345, 103]
	  Inputs		  "*/"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  OutScaling		  "2^-10"
	  RndMeth		  "Floor"
	  SaturateOnIntegerOverflow off
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	Block {
	  BlockType		  Product
	  Name			  "Product"
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	  Position		  [115, 27, 145, 58]
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
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	Block {
	  BlockType		  Product
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	  Position		  [115, 122, 145, 153]
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
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	Block {
	  BlockType		  Sum
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	  Ports			  [2, 1]
	  Position		  [200, 70, 220, 90]
	  ShowName		  off
	  IconShape		  "round"
	  Inputs		  "|++"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
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	Block {
	  BlockType		  Outport
	  Name			  "Power\n Spectrum"
	  Position		  [370, 83, 400, 97]
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
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	  SrcPort		  1
	  DstBlock		  "Divide"
	  DstPort		  1
	}
	Line {
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	  DstBlock		  "Divide"
	  DstPort		  2
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	Line {
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	  Points		  [15, 0; 0, 35]
	  DstBlock		  "Sum"
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	}
	Line {
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	  Points		  [60, 0]
	  DstBlock		  "Sum"
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	}
	Line {
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	  Points		  [0, 0; 15, 0]
	  Branch {
	    DstBlock		    "Product1"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 15]
	    DstBlock		    "Product1"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Real"
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	  Points		  [0, 0; 15, 0]
	  Branch {
	    DstBlock		    "Product"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [15, 0; 0, 15]
	    DstBlock		    "Product"
	    DstPort		    2
	  }
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	Line {
	  SrcBlock		  "Divide"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "Power\n Spectrum"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Power Spectrum1"
      Ports		      [2, 1]
      Position		      [535, 500, 635, 580]
      BackgroundColor	      "green"
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      MaskHideContents	      off
      System {
	Name			"Power Spectrum1"
	Location		[591, 327, 1092, 505]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "Real"
	  Position		  [25, 28, 55, 42]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
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	  Position		  [45, 123, 75, 137]
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	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Constant
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	  Value			  "256"
	  VectorParams1D	  on
	  SamplingMode		  "Sample based"
	  OutDataTypeMode	  "Inherit from 'Constant value'"
	  OutDataType		  "sfix(16)"
	  ConRadixGroup		  "Use specified scaling"
	  OutScaling		  "2^0"
	  SampleTime		  "inf"
	  FramePeriod		  "inf"
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	Block {
	  BlockType		  Product
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	  Ports			  [2, 1]
	  Position		  [315, 72, 345, 103]
	  Inputs		  "*/"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  OutScaling		  "2^-10"
	  RndMeth		  "Floor"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Product
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	  Position		  [115, 27, 145, 58]
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
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	Block {
	  BlockType		  Product
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	  Position		  [115, 122, 145, 153]
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
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	  Ports			  [2, 1]
	  Position		  [200, 70, 220, 90]
	  ShowName		  off
	  IconShape		  "round"
	  Inputs		  "|++"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
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	Block {
	  BlockType		  Outport
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	  Position		  [430, 83, 460, 97]
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
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	  DstBlock		  "Power\n Spectrum"
	  DstPort		  1
	}
	Line {
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	  Points		  [0, 0; 15, 0]
	  Branch {
	    Points		    [15, 0; 0, 15]
	    DstBlock		    "Product"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Product"
	    DstPort		    1
	  }
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	Line {
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	  Points		  [0, 0; 15, 0]
	  Branch {
	    Points		    [0, 15]
	    DstBlock		    "Product1"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Product1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Product1"
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	  Points		  [60, 0]
	  DstBlock		  "Sum"
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	Line {
	  SrcBlock		  "Product"
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	  Points		  [15, 0; 0, 35]
	  DstBlock		  "Sum"
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	Line {
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      DstBlock		      "Scope5"
      DstPort		      3
    }
    Line {
      Name		      "Source Eop"
      Labels		      [0, 0]
      SrcBlock		      "Output4"
      SrcPort		      1
      Points		      [0, 0]
      DstBlock		      "Scope5"
      DstPort		      4
    }
    Line {
      Name		      "Source Valid"
      Labels		      [0, 0]
      SrcBlock		      "Output5"
      SrcPort		      1
      Points		      [0, 0]
      DstBlock		      "Scope5"
      DstPort		      5
    }
    Line {
      Name		      "Source Exp"
      Labels		      [0, 0]
      SrcBlock		      "Output2"
      SrcPort		      1
      Points		      [0, 0; 35, 0]
      Branch {
	DstBlock		"Scope5"
	DstPort			6
      }
      Branch {
	Points			[0, 130]
	DstBlock		"Scope1"
	DstPort			1
      }
    }
    Line {
      Name		      "Source Real"
      Labels		      [0, 0]
      SrcBlock		      "Output"
      SrcPort		      1
      Points		      [0, 0]
      DstBlock		      "Scope5"
      DstPort		      7
    }
    Line {
      Name		      "Source Imag"
      Labels		      [0, 0]
      SrcBlock		      "Output1"
      SrcPort		      1
      Points		      [0, 0]
      DstBlock		      "Scope5"
      DstPort		      8
    }
    Line {
      SrcBlock		      "Sine Wave1"
      SrcPort		      1
      DstBlock		      "Integer Delay"
      DstPort		      1
    }
    Line {
      SrcBlock		      "FFT"
      SrcPort		      1
      DstBlock		      "Complex to\nReal-Imag1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "fft_v7_2"
      SrcPort		      6
      Points		      [0, 0; 20, 0]
      Branch {
	DstBlock		"Output2"
	DstPort			1
      }
      Branch {
	Labels			[0, 0]
	Points			[0, 255]
	DstBlock		"Shifting"
	DstPort			2
      }
    }
    Line {
      SrcBlock		      "Complex to\nReal-Imag1"
      SrcPort		      1
      DstBlock		      "Power Spectrum1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Complex to\nReal-Imag1"
      SrcPort		      2
      DstBlock		      "Power Spectrum1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Output12"
      SrcPort		      1
      Points		      [0, 10]
      Branch {
	Points			[0, 60]
	DstBlock		"Scope5"
	DstPort			9
      }
      Branch {
	DstBlock		"Scope2"
	DstPort			2
      }
    }
    Line {
      SrcBlock		      "Input"
      SrcPort		      1
      Points		      [20, 0; 0, 10]
      Branch {
	Points			[0, -10]
	DstBlock		"fft_v7_2"
	DstPort			6
      }
      Branch {
	DstBlock		"Output12"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Power Spectrum1"
      SrcPort		      1
      DstBlock		      "Vector\nScope"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Buffer"
      SrcPort		      1
      DstBlock		      "FFT"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Shifting"
      SrcPort		      1
      DstBlock		      "Power Spectrum"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Shifting"
      SrcPort		      2
      DstBlock		      "Power Spectrum"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Output9"
      SrcPort		      1
      DstBlock		      "Scope1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Buffer1"
      SrcPort		      1
      Points		      [35, 0]
      DstBlock		      "Vector\nScope1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Power Spectrum"
      SrcPort		      1
      Points		      [0, 0; 15, 0]
      Branch {
	Points			[0, -105]
	DstBlock		"Scope1"
	DstPort			3
      }
      Branch {
	DstBlock		"Integer Delay1"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Integer Delay"
      SrcPort		      1
      Points		      [0, 0; 30, 0]
      Branch {
	Points			[0, -185; 35, 0]
	Branch {
	  DstBlock		  "Input"
	  DstPort		  1
	}
	Branch {
	  Points		  [5, 0]
	  DstBlock		  "Scope2"
	  DstPort		  1
	}
      }
      Branch {
	Points			[0, 55]
	Branch {
	  DstBlock		  "Matlab FFT Spectrum2"
	  DstPort		  1
	}
	Branch {
	  DstBlock		  "Buffer"
	  DstPort		  1
	}
      }
    }
    Line {
      SrcBlock		      "Integer Delay1"
      SrcPort		      1
      DstBlock		      "Buffer1"
      DstPort		      1
    }
    Annotation {
      Position		      [177, 217]
      UseDisplayTextAsClickCallback off
    }
  }
}
MatData {
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    Data		    "  %)30     .    ,     8    (    !          %    "
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  DataRecord {
    Tag			    DataTag1
    Data		    "  %)30     .    ,     8    (    !          %    "
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  DataRecord {
    Tag			    DataTag0
    Data		    "  %)30     .    8     8    (     0         %    "
"\"     $    !     0         .    ,     8    (    !          %    \"     $    "
"#     0         0  , 1D94  "
  }
}

# Finite State Machines
#
#    Stateflow Version 6.4 (R2006a) dated Feb  2 2006, 05:30:12
#
#

Stateflow {

	machine {
		id                   		1
		name                 		"progetto_nuovo"
		created              		"12-Dec-2007 14:22:28"
		isLibrary            		0
		firstTarget          		2
		sfVersion            		64014000
	}

	target {
		id                        		2
		name                      		"sfun"
		description               		"Default Simulink S-Function Target."
		machine                   		1
		linkNode                  		[1 0 0]
	}
}