module avalon_mm_interface (

			clk, 
			rst,
			address,
			write,
			writedata,
			readdata,
			waitrequest
				
		);
		
// signals for connecting to system interconnect

input clk, rst, waitrequest;
output reg write;
output reg [31:0] writedata, address;
input [31:0] readdata;

reg [31:0] inp_v;		
wire [31:0] intm_r;
wire [31:0] fnl_r;

S2P_top u0(.input_v(inp_v), .inter_r(intm_r), .final_r(fnl_r));

reg [3:0] cnt1 = 4'b1111; //count to store 15 values
reg [3:0] cnt2 = 4'b1111;
reg [31:0] temp_address1;
reg [31:0] temp_address;
reg [31:0] data_inp;

//write memory
always @(posedge clk or posedge rst)
begin
	if( rst ) begin
	address  <= 32'h2000_0000;  //input values will be stored at 0x2000_0000
	temp_address <= address;
	temp_address1 <= 32'h2000_0020; // output at 0x2000_0020
	data_inp <= 32'h4f80_0001;
	end else if(!waitrequest && cnt1 !=4'b0000) begin
	write <= 1'b1;
	writedata <= data_inp;
	address <= address + 1;	 //this block writes the ip values to mem 0x2000_0000
	cnt1 <= cnt1  - 1;
	data_inp <= data_inp + 1;
	end else if(!waitrequest && cnt1 == 4'b0000 && cnt2 != 4'b0000 ) begin
	address <= temp_address;
	write <= 1'b0;		//block reads back the value ransfer to S2P_top instn..
	inp_v <= readdata;
	cnt2 <= cnt2 - 1;
	write <= 1'b1;
	address <= temp_address1;
	writedata <= fnl_r;	// writes the processed data at diff locn 0x2000_0020
	temp_address <= temp_address + 1;
	temp_address1 <= temp_address1 + 1;
	end
end

endmodule