--=============================================================
-- File : top_stm_1d_1q.vhd
-- Project : 
-- 
-- Author : Serge Sciberras
-- Subject :  VHDL Description of top_stm_1d_1q module.
--
-- =============================================================
--    Logic Design Solutions
--    Serge Sciberras
--    106 Boulevard de la Resistance
--    93460 Gournay sur Marne - France.
--    Email : info@logic-design-solutions.com
-- 
-- =============================================================
-- This program is controlled by a written license agreement.
-- Unauthorized Reproduction or Use is Expressly Prohibited. 
-- Copyright (c) 2017 Logic-design-solutions.com, France
-- Designed by : Serge Sciberras
--
--=============================================================
-- Version : 1
-- Date    : 05/06/25
-- Author  : Serge Sciberras
-- Remarks : Creation
--=============================================================



--=============================================================
--	PACKAGES
---=============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
--use work.pkg_bus_data_size.all;
--use work.pkg_record.all;
--=============================================================




--=============================================================
--  FDD_NVME_HOST_0001-1 : top_stm_1d_1q Block Diagramm
--=============================================================
entity top_stm_1d_1q is
  --	 
  generic (			
		GEN_BUS_DATA_SIZE           : integer                       := 128;  -- 256-Bits or 128-Bits defined in pkg_bus_data_size.vhd
		--
    GEN_BASE_ADD_CONF	          : std_logic_vector(31 downto 0)	:= x"00000000";
    GEN_BASE_ADD_PRP	          : std_logic_vector(31 downto 0)	:= x"50000000";  		
		GEN_BASE_ADD_EP	            : std_logic_vector(31 downto 0)	:= x"40000000";
    GEN_NB_Q_IO                 : integer                       := 0;    -- 1 Queue
    GEN_IO_MEM_SIZE             : integer                       := 1024; -- 1024KB / 512KB / 256KB / 128KB / 64KB / 32KB /     
    GEN_COMMON_CLOCK_CONFIG     : integer                       := 1;    -- 1: CLOCK is COMMON between Root and EndPoint
    GEN_CPU_ASYNC               : integer                       := 0     -- 0: CPU clock is synchronous - 1: CPU clock is asynchonous
	);
  --   
	port (  
    -------------------------
    -- PCIe Edge
    -------------------------       
    PCIE_REFCLK0                : in  std_logic; -- 100MHz PCIe edge reference clock
    --
    PCIE_RX_N_IN0               : in  std_logic; 
    PCIE_RX_P_IN0               : in  std_logic; 
    PCIE_TX_N_OUT0              : out std_logic; 
    PCIE_TX_P_OUT0              : out std_logic; 
    PCIE_RX_N_IN1               : in  std_logic; 
    PCIE_RX_P_IN1               : in  std_logic; 
    PCIE_TX_N_OUT1              : out std_logic; 
    PCIE_TX_P_OUT1              : out std_logic; 
    PCIE_RX_N_IN2               : in  std_logic; 
    PCIE_RX_P_IN2               : in  std_logic; 
    PCIE_TX_N_OUT2              : out std_logic; 
    PCIE_TX_P_OUT2              : out std_logic; 
    PCIE_RX_N_IN3               : in  std_logic; 
    PCIE_RX_P_IN3               : in  std_logic; 
    PCIE_TX_N_OUT3              : out std_logic; 
    PCIE_TX_P_OUT3              : out std_logic; 
    --
    PCIE_PIN_PERST_N            : in  std_logic; -- CF132 - HVIO_5A_6 - PIN_PERST_N_CVP_L1B_0
    PCIE_PIN_PERST_N_I          : in  std_logic; -- BU109 - HVIO_5B_6 - PIN_PERST_N_CVP_L1B_1 - Left Floating !!!
    --
    -------------------------
    -- GTS_SYSTEM_PLL
    -------------------------
    GTS_SYSTEM_PLL_REFCLK       : in  std_logic; -- 100MHz - REFCLK Pin
    --
    -------------------------
    -- FREE RUNNONG CLOCK
    -------------------------
    CLK_25MHZ                   : in  std_logic;
    --
    --------------------------------------------------
    p0_pin_perst_n                : out std_logic;                                         -- reset_n
		p0_reset_status_n             : out std_logic;                                         -- reset_n
    --
    p0_axi_st_areset_n            : in  std_logic                      := 'X';             -- reset_n
    p0_axi_lite_areset_n          : in  std_logic                      := 'X';             -- reset_n
    --  
    p0_subsystem_cold_rst_n       : in  std_logic                      := 'X';             -- reset_n
    p0_subsystem_warm_rst_n       : in  std_logic                      := 'X';             -- reset_n
    p0_subsystem_cold_rst_ack_n   : out std_logic;                                         -- subsystem_cold_rst_ack_n
    p0_subsystem_warm_rst_ack_n   : out std_logic;                                         -- subsystem_warm_rst_ack_n
    p0_subsystem_rst_req          : in  std_logic                      := 'X';             -- subsystem_rst_req
    p0_subsystem_rst_rdy          : out std_logic;                                         -- subsystem_rst_rdy
    p0_initiate_warmrst_req       : out std_logic;                                         -- initiate_warmrst_req
    p0_initiate_rst_req_rdy       : in  std_logic                      := 'X';             -- initiate_rst_req_rdy
    --
    p0_ss_app_st_rx_tvalid        : out std_logic;                                         -- tvalid
    p0_app_ss_st_rx_tready        : in  std_logic                      := 'X';             -- tready
    p0_ss_app_st_rx_tdata         : out std_logic_vector(127 downto 0);                    -- tdata
    p0_ss_app_st_rx_tkeep         : out std_logic_vector(15 downto 0);                     -- tkeep
    p0_ss_app_st_rx_tlast         : out std_logic;                                         -- tlast
    p0_ss_app_st_rx_tuser_hdr     : out std_logic_vector(255 downto 0);                    -- st_rx_tuser_hdr
    p0_ss_app_st_rx_tuser_hvalid  : out std_logic;                                         -- st_rx_tuser_hvalid
    --
    p0_app_ss_st_tx_tvalid        : in  std_logic                      := 'X';             -- tvalid
    p0_ss_app_st_tx_tready        : out std_logic;                                         -- tready
    p0_app_ss_st_tx_tdata         : in  std_logic_vector(127 downto 0) := (others => 'X'); -- tdata
    p0_app_ss_st_tx_tkeep         : in  std_logic_vector(15 downto 0)  := (others => 'X'); -- tkeep
    p0_app_ss_st_tx_tlast         : in  std_logic                      := 'X';             -- tlast
    p0_app_ss_st_tx_tuser_hdr     : in  std_logic_vector(255 downto 0) := (others => 'X'); -- st_tx_tuser_hdr
    p0_app_ss_st_tx_tuser_hvalid  : in  std_logic                      := 'X';             -- st_tx_tuser_hvalid
    --  
    p0_ss_app_st_txcrdt_tvalid    : out std_logic;                                         -- tvalid
    p0_ss_app_st_txcrdt_tdata     : out std_logic_vector(18 downto 0);                     -- tdata
    --  
    p0_app_ss_lite_csr_awvalid    : in  std_logic                      := 'X';             -- awvalid
    p0_ss_app_lite_csr_awready    : out std_logic;                                         -- awready
    p0_app_ss_lite_csr_awaddr     : in  std_logic_vector(19 downto 0)  := (others => 'X'); -- awaddr
    p0_app_ss_lite_csr_wvalid     : in  std_logic                      := 'X';             -- wvalid
    p0_ss_app_lite_csr_wready     : out std_logic;                                         -- wready
    p0_app_ss_lite_csr_wdata      : in  std_logic_vector(31 downto 0)  := (others => 'X'); -- wdata
    p0_app_ss_lite_csr_wstrb      : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- wstrb
    p0_ss_app_lite_csr_bvalid     : out std_logic;                                         -- bvalid
    p0_app_ss_lite_csr_bready     : in  std_logic                      := 'X';             -- bready
    p0_ss_app_lite_csr_bresp      : out std_logic_vector(1 downto 0);                      -- bresp
    p0_app_ss_lite_csr_arvalid    : in  std_logic                      := 'X';             -- arvalid
    p0_ss_app_lite_csr_arready    : out std_logic;                                         -- arready
    p0_app_ss_lite_csr_araddr     : in  std_logic_vector(19 downto 0)  := (others => 'X'); -- araddr
    p0_ss_app_lite_csr_rvalid     : out std_logic;                                         -- rvalid
    p0_app_ss_lite_csr_rready     : in  std_logic                      := 'X';             -- rready
    p0_ss_app_lite_csr_rdata      : out std_logic_vector(31 downto 0);                     -- rdata
    p0_ss_app_lite_csr_rresp      : out std_logic_vector(1 downto 0);                      -- rresp
    --  
    p0_ss_app_serr                : out std_logic;                                         -- ss_app_serr
    p0_ss_app_dlup                : out std_logic;                                         -- ss_app_dlup
    p0_ss_app_linkup              : out std_logic;                                         -- ss_app_linkup
    p0_ss_app_int_status          : out std_logic;                                         -- ss_app_int_status
    p0_ss_app_ltssmstate          : out std_logic_vector(5 downto 0);                      -- ss_app_ltssmstate
    p0_app_ss_st_rx_tuser_halt    : in  std_logic_vector(2 downto 0)   := (others => 'X')  -- app_ss_st_rx_tuser_halt  
    --
);                            
end top_stm_1d_1q;
--=============================================================




architecture rtl of top_stm_1d_1q is


----------------------------------
-- Components  
----------------------------------
	component gts_axi_streaming is
		port (
			refclk0                       : in  std_logic                      := 'X';             -- clk
			p0_i_syspll_c0_clk            : in  std_logic                      := 'X';             -- clk
			p0_i_ss_vccl_syspll_locked    : in  std_logic                      := 'X';             -- o_pll_lock
			i_flux_clk                    : in  std_logic_vector(0 downto 0)   := (others => 'X'); -- clk
      --  
			rx_n_in0                      : in  std_logic                      := 'X';             -- rx_n_in0
			rx_p_in0                      : in  std_logic                      := 'X';             -- rx_p_in0
			tx_n_out0                     : out std_logic;                                         -- tx_n_out0
			tx_p_out0                     : out std_logic;                                         -- tx_p_out0
			rx_n_in1                      : in  std_logic                      := 'X';             -- rx_n_in1
			rx_p_in1                      : in  std_logic                      := 'X';             -- rx_p_in1
			tx_n_out1                     : out std_logic;                                         -- tx_n_out1
			tx_p_out1                     : out std_logic;                                         -- tx_p_out1
			rx_n_in2                      : in  std_logic                      := 'X';             -- rx_n_in2
			rx_p_in2                      : in  std_logic                      := 'X';             -- rx_p_in2
			tx_n_out2                     : out std_logic;                                         -- tx_n_out2
			tx_p_out2                     : out std_logic;                                         -- tx_p_out2
			rx_n_in3                      : in  std_logic                      := 'X';             -- rx_n_in3
			rx_p_in3                      : in  std_logic                      := 'X';             -- rx_p_in3
			tx_n_out3                     : out std_logic;                                         -- tx_n_out3
			tx_p_out3                     : out std_logic;                                         -- tx_p_out3
      --  
			p0_pin_perst_n_i              : in  std_logic                      := 'X';             -- reset_n
			p0_pin_perst_n_1_i            : in  std_logic                      := 'X';             -- reset_n
      --  
			p0_coreclkout_hip_toapp       : out std_logic;                                         -- clk
			p0_pin_perst_n                : out std_logic;                                         -- reset_n
			p0_reset_status_n             : out std_logic;                                         -- reset_n
      --  
			ninit_done                    : in  std_logic                      := 'X';             -- reset
      --  
			p0_axi_st_clk                 : in  std_logic                      := 'X';             -- clk
			p0_axi_lite_clk               : in  std_logic                      := 'X';             -- clk
			p0_axi_st_areset_n            : in  std_logic                      := 'X';             -- reset_n
			p0_axi_lite_areset_n          : in  std_logic                      := 'X';             -- reset_n
      --  
			p0_subsystem_cold_rst_n       : in  std_logic                      := 'X';             -- reset_n
			p0_subsystem_warm_rst_n       : in  std_logic                      := 'X';             -- reset_n
			p0_subsystem_cold_rst_ack_n   : out std_logic;                                         -- subsystem_cold_rst_ack_n
			p0_subsystem_warm_rst_ack_n   : out std_logic;                                         -- subsystem_warm_rst_ack_n
			p0_subsystem_rst_req          : in  std_logic                      := 'X';             -- subsystem_rst_req
			p0_subsystem_rst_rdy          : out std_logic;                                         -- subsystem_rst_rdy
			p0_initiate_warmrst_req       : out std_logic;                                         -- initiate_warmrst_req
			p0_initiate_rst_req_rdy       : in  std_logic                      := 'X';             -- initiate_rst_req_rdy
      --
			p0_ss_app_st_rx_tvalid        : out std_logic;                                         -- tvalid
			p0_app_ss_st_rx_tready        : in  std_logic                      := 'X';             -- tready
			p0_ss_app_st_rx_tdata         : out std_logic_vector(127 downto 0);                    -- tdata
			p0_ss_app_st_rx_tkeep         : out std_logic_vector(15 downto 0);                     -- tkeep
			p0_ss_app_st_rx_tlast         : out std_logic;                                         -- tlast
      p0_ss_app_st_rx_tuser_hdr     : out std_logic_vector(255 downto 0);                    -- st_rx_tuser_hdr
			p0_ss_app_st_rx_tuser_hvalid  : out std_logic;                                         -- st_rx_tuser_hvalid
			--
			p0_app_ss_st_tx_tvalid        : in  std_logic                      := 'X';             -- tvalid
			p0_ss_app_st_tx_tready        : out std_logic;                                         -- tready
			p0_app_ss_st_tx_tdata         : in  std_logic_vector(127 downto 0) := (others => 'X'); -- tdata
			p0_app_ss_st_tx_tkeep         : in  std_logic_vector(15 downto 0)  := (others => 'X'); -- tkeep
			p0_app_ss_st_tx_tlast         : in  std_logic                      := 'X';             -- tlast
      p0_app_ss_st_tx_tuser_hdr     : in  std_logic_vector(255 downto 0) := (others => 'X'); -- st_tx_tuser_hdr
			p0_app_ss_st_tx_tuser_hvalid  : in  std_logic                      := 'X';             -- st_tx_tuser_hvalid
			--  
			p0_ss_app_st_txcrdt_tvalid    : out std_logic;                                         -- tvalid
			p0_ss_app_st_txcrdt_tdata     : out std_logic_vector(18 downto 0);                     -- tdata
      --  
			p0_app_ss_lite_csr_awvalid    : in  std_logic                      := 'X';             -- awvalid
			p0_ss_app_lite_csr_awready    : out std_logic;                                         -- awready
			p0_app_ss_lite_csr_awaddr     : in  std_logic_vector(19 downto 0)  := (others => 'X'); -- awaddr
			p0_app_ss_lite_csr_wvalid     : in  std_logic                      := 'X';             -- wvalid
			p0_ss_app_lite_csr_wready     : out std_logic;                                         -- wready
			p0_app_ss_lite_csr_wdata      : in  std_logic_vector(31 downto 0)  := (others => 'X'); -- wdata
			p0_app_ss_lite_csr_wstrb      : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- wstrb
			p0_ss_app_lite_csr_bvalid     : out std_logic;                                         -- bvalid
			p0_app_ss_lite_csr_bready     : in  std_logic                      := 'X';             -- bready
			p0_ss_app_lite_csr_bresp      : out std_logic_vector(1 downto 0);                      -- bresp
			p0_app_ss_lite_csr_arvalid    : in  std_logic                      := 'X';             -- arvalid
			p0_ss_app_lite_csr_arready    : out std_logic;                                         -- arready
			p0_app_ss_lite_csr_araddr     : in  std_logic_vector(19 downto 0)  := (others => 'X'); -- araddr
			p0_ss_app_lite_csr_rvalid     : out std_logic;                                         -- rvalid
			p0_app_ss_lite_csr_rready     : in  std_logic                      := 'X';             -- rready
			p0_ss_app_lite_csr_rdata      : out std_logic_vector(31 downto 0);                     -- rdata
			p0_ss_app_lite_csr_rresp      : out std_logic_vector(1 downto 0);                      -- rresp
      --  
			p0_ss_app_serr                : out std_logic;                                         -- ss_app_serr
			p0_ss_app_dlup                : out std_logic;                                         -- ss_app_dlup
			p0_ss_app_linkup              : out std_logic;                                         -- ss_app_linkup
			p0_ss_app_int_status          : out std_logic;                                         -- ss_app_int_status
			p0_ss_app_ltssmstate          : out std_logic_vector(5 downto 0);                      -- ss_app_ltssmstate
			p0_app_ss_st_rx_tuser_halt    : in  std_logic_vector(2 downto 0)   := (others => 'X')  -- app_ss_st_rx_tuser_halt
		);
	end component gts_axi_streaming;
  --
  --
  component reset_release is
		port (
			ninit_done : out std_logic   -- ninit_done
		);
	end component reset_release;
  --
  --
  component gts_reset_sequencer is
		port (
			o_pma_cu_clk                 : out std_logic_vector(0 downto 0);        -- clk
			i_refclk_bus_out             : in  std_logic                    := 'X'; -- refclk_bus_out
			o_shoreline_refclk_fail_stat : out std_logic                            -- shoreline_refclk_fail_stat
		);
	end component gts_reset_sequencer;
  --
  --
  component gts_system_pll is
		port (
			o_pll_lock  : out std_logic;        -- o_pll_lock
			o_syspll_c0 : out std_logic;        -- clk
			i_refclk    : in  std_logic := 'X'  -- clk
		);
	end component gts_system_pll;
  --
   --
  --
  component iopll_100mhz is
		port (
			refclk   : in  std_logic := 'X'; -- clk
			locked   : out std_logic;        -- export
			rst      : in  std_logic := 'X'; -- reset
			outclk_0 : out std_logic         -- clk
		);
	end component iopll_100mhz;
  --
  --

--========================================================================== 
 
  
  
-------------------------   
-- RESET_RELEASE           
-------------------------  
signal ninit_done                     : std_logic;  
--
-------------------------   
-- GTS_RESET_SEQUENCER           
-------------------------  
signal pma_cu_clk                     : std_logic_vector(0 downto 0); 
--
-------------------------   
-- GTS_SYSTEM_PLL           
-------------------------
signal gts_system_pll_clk               : std_logic; 
signal gts_system_pll_clk_lock          : std_logic;  
--  
-------------------------     
-- GTS_AXI_STREAMING            
------------------------- 
signal p0_coreclkout_hip_toapp          : std_logic;

--  

--
signal p0_axi_lite_clk                  : std_logic;

--      

--
-------------------------   
-- TOP_NVME_HOST_WRAP_1Q           
-------------------------

--
-------------------------   
-- LDS_STM_TEST_1Q     
-------------------------
   
 
-- 
-------------------------   
-- 
-------------------------       

-------------------------
  
  
begin


--===============================================
-- IOPLL_100MHZ
--===============================================
i_iopll_100mhz : iopll_100mhz
		port map(
			refclk   => CLK_25MHZ,
			locked   => open,
			rst      => ninit_done,
			outclk_0 => p0_axi_lite_clk
		);
--
--===============================================
-- RESET_RELEASE
--===============================================
i_reset_release : reset_release
		port map(
			ninit_done => ninit_done
		);
--
--===============================================
-- RESET_RELEASE
--===============================================
i_gts_reset_sequencer : gts_reset_sequencer
		port map(
			o_pma_cu_clk                 => pma_cu_clk,
			i_refclk_bus_out             => '0',
			o_shoreline_refclk_fail_stat => open
		);
--
--===============================================
-- GTS_SYSTEM_PLL
--===============================================
i_gts_system_pll : gts_system_pll
		port map(
			o_pll_lock  => gts_system_pll_clk_lock,        
			o_syspll_c0 => gts_system_pll_clk,        
			i_refclk    => GTS_SYSTEM_PLL_REFCLK
		);
--
--===============================================
-- GTS_AXI_STREAMING
--===============================================
i_gts_axi_streaming : gts_axi_streaming
		port map (
			refclk0                       => PCIE_REFCLK0,
			p0_i_syspll_c0_clk            => gts_system_pll_clk,
			p0_i_ss_vccl_syspll_locked    => gts_system_pll_clk_lock,
			i_flux_clk                    => pma_cu_clk,
      --  
			rx_n_in0                      => PCIE_RX_N_IN0 ,
			rx_p_in0                      => PCIE_RX_P_IN0 ,
			tx_n_out0                     => PCIE_TX_N_OUT0,
			tx_p_out0                     => PCIE_TX_P_OUT0,
			rx_n_in1                      => PCIE_RX_N_IN1 ,
			rx_p_in1                      => PCIE_RX_P_IN1 ,
			tx_n_out1                     => PCIE_TX_N_OUT1,
			tx_p_out1                     => PCIE_TX_P_OUT1,
			rx_n_in2                      => PCIE_RX_N_IN2 ,
			rx_p_in2                      => PCIE_RX_P_IN2 ,
			tx_n_out2                     => PCIE_TX_N_OUT2,
			tx_p_out2                     => PCIE_TX_P_OUT2,
			rx_n_in3                      => PCIE_RX_N_IN3 ,
			rx_p_in3                      => PCIE_RX_P_IN3 ,
			tx_n_out3                     => PCIE_TX_N_OUT3,
			tx_p_out3                     => PCIE_TX_P_OUT3,
      --  
			p0_pin_perst_n_i              => PCIE_PIN_PERST_N, 
			p0_pin_perst_n_1_i            => PCIE_PIN_PERST_N_I,
      --  
			p0_coreclkout_hip_toapp       => p0_coreclkout_hip_toapp,
			p0_pin_perst_n                => p0_pin_perst_n         ,
			p0_reset_status_n             => p0_reset_status_n      ,
      --  
			ninit_done                    => ninit_done,
      --  
			p0_axi_st_clk                 => p0_coreclkout_hip_toapp,
			p0_axi_lite_clk               => p0_axi_lite_clk     ,
			p0_axi_st_areset_n            => p0_axi_st_areset_n  ,
			p0_axi_lite_areset_n          => p0_axi_lite_areset_n,
      --  
			p0_subsystem_cold_rst_n       => p0_subsystem_cold_rst_n    ,
			p0_subsystem_warm_rst_n       => p0_subsystem_warm_rst_n    ,
			p0_subsystem_cold_rst_ack_n   => p0_subsystem_cold_rst_ack_n,
			p0_subsystem_warm_rst_ack_n   => p0_subsystem_warm_rst_ack_n,
			p0_subsystem_rst_req          => p0_subsystem_rst_req       ,
			p0_subsystem_rst_rdy          => p0_subsystem_rst_rdy       ,
			p0_initiate_warmrst_req       => p0_initiate_warmrst_req    ,
			p0_initiate_rst_req_rdy       => p0_initiate_rst_req_rdy    ,
      --  
			p0_ss_app_st_rx_tvalid        => p0_ss_app_st_rx_tvalid,
			p0_app_ss_st_rx_tready        => p0_app_ss_st_rx_tready,
			p0_ss_app_st_rx_tdata         => p0_ss_app_st_rx_tdata ,
			p0_ss_app_st_rx_tkeep         => p0_ss_app_st_rx_tkeep ,
			p0_ss_app_st_rx_tlast         => p0_ss_app_st_rx_tlast ,
      p0_ss_app_st_rx_tuser_hdr     => p0_ss_app_st_rx_tuser_hdr   ,
			p0_ss_app_st_rx_tuser_hvalid  => p0_ss_app_st_rx_tuser_hvalid,
			--
			p0_app_ss_st_tx_tvalid        => p0_app_ss_st_tx_tvalid,
			p0_ss_app_st_tx_tready        => p0_ss_app_st_tx_tready,
			p0_app_ss_st_tx_tdata         => p0_app_ss_st_tx_tdata ,
			p0_app_ss_st_tx_tkeep         => p0_app_ss_st_tx_tkeep ,
			p0_app_ss_st_tx_tlast         => p0_app_ss_st_tx_tlast ,
      p0_app_ss_st_tx_tuser_hdr     => p0_app_ss_st_tx_tuser_hdr   ,
			p0_app_ss_st_tx_tuser_hvalid  => p0_app_ss_st_tx_tuser_hvalid,
      --
			p0_ss_app_st_txcrdt_tvalid    => p0_ss_app_st_txcrdt_tvalid,
			p0_ss_app_st_txcrdt_tdata     => p0_ss_app_st_txcrdt_tdata ,
      --  
			p0_app_ss_lite_csr_awvalid    => p0_app_ss_lite_csr_awvalid,
			p0_ss_app_lite_csr_awready    => p0_ss_app_lite_csr_awready,
			p0_app_ss_lite_csr_awaddr     => p0_app_ss_lite_csr_awaddr ,
			p0_app_ss_lite_csr_wvalid     => p0_app_ss_lite_csr_wvalid ,
			p0_ss_app_lite_csr_wready     => p0_ss_app_lite_csr_wready ,
			p0_app_ss_lite_csr_wdata      => p0_app_ss_lite_csr_wdata  ,
			p0_app_ss_lite_csr_wstrb      => p0_app_ss_lite_csr_wstrb  ,
			p0_ss_app_lite_csr_bvalid     => p0_ss_app_lite_csr_bvalid ,
			p0_app_ss_lite_csr_bready     => p0_app_ss_lite_csr_bready ,
			p0_ss_app_lite_csr_bresp      => p0_ss_app_lite_csr_bresp  ,
			p0_app_ss_lite_csr_arvalid    => p0_app_ss_lite_csr_arvalid,
			p0_ss_app_lite_csr_arready    => p0_ss_app_lite_csr_arready,
			p0_app_ss_lite_csr_araddr     => p0_app_ss_lite_csr_araddr ,
			p0_ss_app_lite_csr_rvalid     => p0_ss_app_lite_csr_rvalid ,
			p0_app_ss_lite_csr_rready     => p0_app_ss_lite_csr_rready ,
			p0_ss_app_lite_csr_rdata      => p0_ss_app_lite_csr_rdata  ,
			p0_ss_app_lite_csr_rresp      => p0_ss_app_lite_csr_rresp  ,
      --  
			p0_ss_app_serr                => p0_ss_app_serr            ,
			p0_ss_app_dlup                => p0_ss_app_dlup            ,
			p0_ss_app_linkup              => p0_ss_app_linkup          ,
			p0_ss_app_int_status          => p0_ss_app_int_status      ,
			p0_ss_app_ltssmstate          => p0_ss_app_ltssmstate      ,
			p0_app_ss_st_rx_tuser_halt    => p0_app_ss_st_rx_tuser_halt
		);    
--===============================================



end rtl;
