// (C) 2001-2025 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License Subscription 
// Agreement, Altera IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the applicable 
// agreement for further details.





module gts_axi_streaming_pipe_hal_2100_5uv47ay #(
    parameter sris_enable        = "SRIS_ENABLE_DISABLED",
    parameter pcie_pcs_mode      = "PCIE_PCS_MODE_PCIE",
    parameter pclk_clk_hz        = 0,
    parameter num_of_lanes       = 1
) (
    input   [16:0] i_ch0_lavmm_pcie_addr,
    input    [3:0] i_ch0_lavmm_pcie_be,
    input          i_ch0_lavmm_pcie_clk,
    input          i_ch0_lavmm_pcie_read,
    input          i_ch0_lavmm_pcie_rstn,
    input   [31:0] i_ch0_lavmm_pcie_wdata,
    input          i_ch0_lavmm_pcie_write,
    input          i_ch0_pcie_rxword_clk,
    input          i_ch0_pcie_txword_clk,
    input          i_ch0_pcs_pclk,
    input          i_ch0_pcs_pipe_rstn,
    input          i_ch0_txpipe_asyncpowerchangeack,
    input          i_ch0_txpipe_blockaligncontrol,
    input          i_ch0_txpipe_cfg_hw_auto_sp_dis,
    input          i_ch0_txpipe_dirchange,
    input          i_ch0_txpipe_ebuf_mode,
    input          i_ch0_txpipe_encodedecodebypass,
    input    [5:0] i_ch0_txpipe_fs,
    input          i_ch0_txpipe_getlocalpresetcoefficients,
    input          i_ch0_txpipe_invalidrequest,
    input    [5:0] i_ch0_txpipe_lf,
    input    [4:0] i_ch0_txpipe_localpresetindex,
    input          i_ch0_txpipe_lowpin_nt,
    input    [7:0] i_ch0_txpipe_m2p_bus,
    input    [2:0] i_ch0_txpipe_pclk_rate,
    input          i_ch0_txpipe_pclkchangeack,
    input    [3:0] i_ch0_txpipe_phy_mode_nt,
    input    [3:0] i_ch0_txpipe_powerdown,
    input    [2:0] i_ch0_txpipe_rate,
    input          i_ch0_txpipe_rxelecidle_disable_a,
    input          i_ch0_txpipe_rxeqclr,
    input          i_ch0_txpipe_rxeqeval,
    input          i_ch0_txpipe_rxeqinprogress,
    input          i_ch0_txpipe_rxeqtraining,
    input          i_ch0_txpipe_rxpolarity,
    input    [2:0] i_ch0_txpipe_rxpresethint,
    input          i_ch0_txpipe_rxstandby,
    input          i_ch0_txpipe_rxtermination,
    input          i_ch0_txpipe_srisenable,
    input          i_ch0_txpipe_txcmnmode_disable_a,
    input          i_ch0_txpipe_txcompliance,
    input   [39:0] i_ch0_txpipe_txdata,
    input    [3:0] i_ch0_txpipe_txdatak,
    input          i_ch0_txpipe_txdatavalid,
    input   [17:0] i_ch0_txpipe_txdeemph,
    input          i_ch0_txpipe_txdtctrx_lb,
    input          i_ch0_txpipe_txelecidle,
    input    [2:0] i_ch0_txpipe_txmargin,
    input          i_ch0_txpipe_txoneszeros,
    input          i_ch0_txpipe_txstartblock,
    input          i_ch0_txpipe_txswing,
    input    [3:0] i_ch0_txpipe_txsyncheader,
    input    [2:0] i_ch0_txpipe_width,
    input          i_ch0_uxq_rxcdrlock2dataa,
    input   [13:0] i_ch0_uxq_rxeq_best_eye_vala,
    input          i_ch0_uxq_rxeq_donea,
    input          i_ch0_uxq_rxmargin_nacka,
    input    [1:0] i_ch0_uxq_rxmargin_status_gray_a,
    input          i_ch0_uxq_rxmargin_statusa,
    input          i_ch0_uxq_rxsignaldetect_lfpsa,
    input          i_ch0_uxq_rxsignaldetecta,
    input          i_ch0_uxq_rxstatusa,
    input   [39:0] i_ch0_uxq_rxword,
    input          i_ch0_uxq_synthlcfast_postdiv,
    input          i_ch0_uxq_synthlcmed_postdiv,
    input          i_ch0_uxq_synthlcslow_postdiv,
    input          i_ch0_uxq_txdetectrx_acka,
    input          i_ch0_uxq_txdetectrx_statct,
    input          i_ch0_uxq_txstatusa,
    output  [31:0] o_ch0_lavmm_pcie_rdata,
    output         o_ch0_lavmm_pcie_rdata_valid,
    output         o_ch0_lavmm_pcie_waitreq,
    output         o_ch0_pcs_pclk,
    output         o_ch0_pcs_pipe_rstn,
    output   [5:0] o_ch0_rxpipe_dirfeedback,
    output   [7:0] o_ch0_rxpipe_linkevaluationfeedbackfiguremerit,
    output   [5:0] o_ch0_rxpipe_localfs,
    output   [5:0] o_ch0_rxpipe_locallf,
    output         o_ch0_rxpipe_localtxcoefficientsvalid,
    output  [17:0] o_ch0_rxpipe_localtxpresetcoefficients,
    output   [7:0] o_ch0_rxpipe_p2m_bus,
    output         o_ch0_rxpipe_pclkchangeok,
    output         o_ch0_rxpipe_phystatus,
    output  [39:0] o_ch0_rxpipe_rxdata,
    output   [3:0] o_ch0_rxpipe_rxdatak,
    output         o_ch0_rxpipe_rxdatavalid,
    output         o_ch0_rxpipe_rxelecidlea,
    output         o_ch0_rxpipe_rxstandbystatus,
    output         o_ch0_rxpipe_rxstartblock,
    output   [2:0] o_ch0_rxpipe_rxstatus,
    output   [3:0] o_ch0_rxpipe_rxsyncheader,
    output         o_ch0_rxpipe_rxvalid,
    output         o_ch0_ux_ock_pma_clk,
    output         o_ch0_uxq_lfps_ennt,
    output   [1:0] o_ch0_uxq_pcie_l1ctrla,
    output         o_ch0_uxq_pma_cmn_ctrl,
    output         o_ch0_uxq_pma_ctrl,
    output         o_ch0_uxq_rst_pcs_rx_b_a,
    output         o_ch0_uxq_rst_pcs_tx_b_a,
    output         o_ch0_uxq_rxeiosdetectstata,
    output   [2:0] o_ch0_uxq_rxeq_precal_code_selnt,
    output         o_ch0_uxq_rxeq_starta,
    output         o_ch0_uxq_rxeq_static_ena,
    output         o_ch0_uxq_rxmargin_direction_nt,
    output         o_ch0_uxq_rxmargin_mode_nt,
    output         o_ch0_uxq_rxmargin_offset_change_a,
    output   [6:0] o_ch0_uxq_rxmargin_offset_nt,
    output         o_ch0_uxq_rxmargin_start_a,
    output   [2:0] o_ch0_uxq_rxpstate,
    output   [3:0] o_ch0_uxq_rxrate,
    output         o_ch0_uxq_rxterm_hiz_ena,
    output   [2:0] o_ch0_uxq_rxwidth,
    output         o_ch0_uxq_tstbus_lane,
    output         o_ch0_uxq_txbeacona,
    output   [2:0] o_ch0_uxq_txclkdivrate,
    output         o_ch0_uxq_txdetectrx_reqa,
    output   [5:0] o_ch0_uxq_txdrv_levn,
    output   [4:0] o_ch0_uxq_txdrv_levnm1,
    output   [2:0] o_ch0_uxq_txdrv_levnm2,
    output   [4:0] o_ch0_uxq_txdrv_levnp1,
    output   [3:0] o_ch0_uxq_txdrv_slew,
    output   [3:0] o_ch0_uxq_txelecidle,
    output   [2:0] o_ch0_uxq_txpstate,
    output   [3:0] o_ch0_uxq_txrate,
    output   [2:0] o_ch0_uxq_txwidth,
    output  [39:0] o_ch0_uxq_txword,

    input   [16:0] i_ch1_lavmm_pcie_addr,
    input    [3:0] i_ch1_lavmm_pcie_be,
    input          i_ch1_lavmm_pcie_clk,
    input          i_ch1_lavmm_pcie_read,
    input          i_ch1_lavmm_pcie_rstn,
    input   [31:0] i_ch1_lavmm_pcie_wdata,
    input          i_ch1_lavmm_pcie_write,
    input          i_ch1_pcie_rxword_clk,
    input          i_ch1_pcie_txword_clk,
    input          i_ch1_pcs_pclk,
    input          i_ch1_pcs_pipe_rstn,
    input          i_ch1_txpipe_asyncpowerchangeack,
    input          i_ch1_txpipe_blockaligncontrol,
    input          i_ch1_txpipe_cfg_hw_auto_sp_dis,
    input          i_ch1_txpipe_dirchange,
    input          i_ch1_txpipe_ebuf_mode,
    input          i_ch1_txpipe_encodedecodebypass,
    input    [5:0] i_ch1_txpipe_fs,
    input          i_ch1_txpipe_getlocalpresetcoefficients,
    input          i_ch1_txpipe_invalidrequest,
    input    [5:0] i_ch1_txpipe_lf,
    input    [4:0] i_ch1_txpipe_localpresetindex,
    input          i_ch1_txpipe_lowpin_nt,
    input    [7:0] i_ch1_txpipe_m2p_bus,
    input    [2:0] i_ch1_txpipe_pclk_rate,
    input          i_ch1_txpipe_pclkchangeack,
    input    [3:0] i_ch1_txpipe_phy_mode_nt,
    input    [3:0] i_ch1_txpipe_powerdown,
    input    [2:0] i_ch1_txpipe_rate,
    input          i_ch1_txpipe_rxelecidle_disable_a,
    input          i_ch1_txpipe_rxeqclr,
    input          i_ch1_txpipe_rxeqeval,
    input          i_ch1_txpipe_rxeqinprogress,
    input          i_ch1_txpipe_rxeqtraining,
    input          i_ch1_txpipe_rxpolarity,
    input    [2:0] i_ch1_txpipe_rxpresethint,
    input          i_ch1_txpipe_rxstandby,
    input          i_ch1_txpipe_rxtermination,
    input          i_ch1_txpipe_srisenable,
    input          i_ch1_txpipe_txcmnmode_disable_a,
    input          i_ch1_txpipe_txcompliance,
    input   [39:0] i_ch1_txpipe_txdata,
    input    [3:0] i_ch1_txpipe_txdatak,
    input          i_ch1_txpipe_txdatavalid,
    input   [17:0] i_ch1_txpipe_txdeemph,
    input          i_ch1_txpipe_txdtctrx_lb,
    input          i_ch1_txpipe_txelecidle,
    input    [2:0] i_ch1_txpipe_txmargin,
    input          i_ch1_txpipe_txoneszeros,
    input          i_ch1_txpipe_txstartblock,
    input          i_ch1_txpipe_txswing,
    input    [3:0] i_ch1_txpipe_txsyncheader,
    input    [2:0] i_ch1_txpipe_width,
    input          i_ch1_uxq_rxcdrlock2dataa,
    input   [13:0] i_ch1_uxq_rxeq_best_eye_vala,
    input          i_ch1_uxq_rxeq_donea,
    input          i_ch1_uxq_rxmargin_nacka,
    input    [1:0] i_ch1_uxq_rxmargin_status_gray_a,
    input          i_ch1_uxq_rxmargin_statusa,
    input          i_ch1_uxq_rxsignaldetect_lfpsa,
    input          i_ch1_uxq_rxsignaldetecta,
    input          i_ch1_uxq_rxstatusa,
    input   [39:0] i_ch1_uxq_rxword,
    input          i_ch1_uxq_synthlcfast_postdiv,
    input          i_ch1_uxq_synthlcmed_postdiv,
    input          i_ch1_uxq_synthlcslow_postdiv,
    input          i_ch1_uxq_txdetectrx_acka,
    input          i_ch1_uxq_txdetectrx_statct,
    input          i_ch1_uxq_txstatusa,
    output  [31:0] o_ch1_lavmm_pcie_rdata,
    output         o_ch1_lavmm_pcie_rdata_valid,
    output         o_ch1_lavmm_pcie_waitreq,
    output         o_ch1_pcs_pclk,
    output         o_ch1_pcs_pipe_rstn,
    output   [5:0] o_ch1_rxpipe_dirfeedback,
    output   [7:0] o_ch1_rxpipe_linkevaluationfeedbackfiguremerit,
    output   [5:0] o_ch1_rxpipe_localfs,
    output   [5:0] o_ch1_rxpipe_locallf,
    output         o_ch1_rxpipe_localtxcoefficientsvalid,
    output  [17:0] o_ch1_rxpipe_localtxpresetcoefficients,
    output   [7:0] o_ch1_rxpipe_p2m_bus,
    output         o_ch1_rxpipe_pclkchangeok,
    output         o_ch1_rxpipe_phystatus,
    output  [39:0] o_ch1_rxpipe_rxdata,
    output   [3:0] o_ch1_rxpipe_rxdatak,
    output         o_ch1_rxpipe_rxdatavalid,
    output         o_ch1_rxpipe_rxelecidlea,
    output         o_ch1_rxpipe_rxstandbystatus,
    output         o_ch1_rxpipe_rxstartblock,
    output   [2:0] o_ch1_rxpipe_rxstatus,
    output   [3:0] o_ch1_rxpipe_rxsyncheader,
    output         o_ch1_rxpipe_rxvalid,
    output         o_ch1_ux_ock_pma_clk,
    output         o_ch1_uxq_lfps_ennt,
    output   [1:0] o_ch1_uxq_pcie_l1ctrla,
    output         o_ch1_uxq_pma_cmn_ctrl,
    output         o_ch1_uxq_pma_ctrl,
    output         o_ch1_uxq_rst_pcs_rx_b_a,
    output         o_ch1_uxq_rst_pcs_tx_b_a,
    output         o_ch1_uxq_rxeiosdetectstata,
    output   [2:0] o_ch1_uxq_rxeq_precal_code_selnt,
    output         o_ch1_uxq_rxeq_starta,
    output         o_ch1_uxq_rxeq_static_ena,
    output         o_ch1_uxq_rxmargin_direction_nt,
    output         o_ch1_uxq_rxmargin_mode_nt,
    output         o_ch1_uxq_rxmargin_offset_change_a,
    output   [6:0] o_ch1_uxq_rxmargin_offset_nt,
    output         o_ch1_uxq_rxmargin_start_a,
    output   [2:0] o_ch1_uxq_rxpstate,
    output   [3:0] o_ch1_uxq_rxrate,
    output         o_ch1_uxq_rxterm_hiz_ena,
    output   [2:0] o_ch1_uxq_rxwidth,
    output         o_ch1_uxq_tstbus_lane,
    output         o_ch1_uxq_txbeacona,
    output   [2:0] o_ch1_uxq_txclkdivrate,
    output         o_ch1_uxq_txdetectrx_reqa,
    output   [5:0] o_ch1_uxq_txdrv_levn,
    output   [4:0] o_ch1_uxq_txdrv_levnm1,
    output   [2:0] o_ch1_uxq_txdrv_levnm2,
    output   [4:0] o_ch1_uxq_txdrv_levnp1,
    output   [3:0] o_ch1_uxq_txdrv_slew,
    output   [3:0] o_ch1_uxq_txelecidle,
    output   [2:0] o_ch1_uxq_txpstate,
    output   [3:0] o_ch1_uxq_txrate,
    output   [2:0] o_ch1_uxq_txwidth,
    output  [39:0] o_ch1_uxq_txword,

    input   [16:0] i_ch2_lavmm_pcie_addr,
    input    [3:0] i_ch2_lavmm_pcie_be,
    input          i_ch2_lavmm_pcie_clk,
    input          i_ch2_lavmm_pcie_read,
    input          i_ch2_lavmm_pcie_rstn,
    input   [31:0] i_ch2_lavmm_pcie_wdata,
    input          i_ch2_lavmm_pcie_write,
    input          i_ch2_pcie_rxword_clk,
    input          i_ch2_pcie_txword_clk,
    input          i_ch2_pcs_pclk,
    input          i_ch2_pcs_pipe_rstn,
    input          i_ch2_txpipe_asyncpowerchangeack,
    input          i_ch2_txpipe_blockaligncontrol,
    input          i_ch2_txpipe_cfg_hw_auto_sp_dis,
    input          i_ch2_txpipe_dirchange,
    input          i_ch2_txpipe_ebuf_mode,
    input          i_ch2_txpipe_encodedecodebypass,
    input    [5:0] i_ch2_txpipe_fs,
    input          i_ch2_txpipe_getlocalpresetcoefficients,
    input          i_ch2_txpipe_invalidrequest,
    input    [5:0] i_ch2_txpipe_lf,
    input    [4:0] i_ch2_txpipe_localpresetindex,
    input          i_ch2_txpipe_lowpin_nt,
    input    [7:0] i_ch2_txpipe_m2p_bus,
    input    [2:0] i_ch2_txpipe_pclk_rate,
    input          i_ch2_txpipe_pclkchangeack,
    input    [3:0] i_ch2_txpipe_phy_mode_nt,
    input    [3:0] i_ch2_txpipe_powerdown,
    input    [2:0] i_ch2_txpipe_rate,
    input          i_ch2_txpipe_rxelecidle_disable_a,
    input          i_ch2_txpipe_rxeqclr,
    input          i_ch2_txpipe_rxeqeval,
    input          i_ch2_txpipe_rxeqinprogress,
    input          i_ch2_txpipe_rxeqtraining,
    input          i_ch2_txpipe_rxpolarity,
    input    [2:0] i_ch2_txpipe_rxpresethint,
    input          i_ch2_txpipe_rxstandby,
    input          i_ch2_txpipe_rxtermination,
    input          i_ch2_txpipe_srisenable,
    input          i_ch2_txpipe_txcmnmode_disable_a,
    input          i_ch2_txpipe_txcompliance,
    input   [39:0] i_ch2_txpipe_txdata,
    input    [3:0] i_ch2_txpipe_txdatak,
    input          i_ch2_txpipe_txdatavalid,
    input   [17:0] i_ch2_txpipe_txdeemph,
    input          i_ch2_txpipe_txdtctrx_lb,
    input          i_ch2_txpipe_txelecidle,
    input    [2:0] i_ch2_txpipe_txmargin,
    input          i_ch2_txpipe_txoneszeros,
    input          i_ch2_txpipe_txstartblock,
    input          i_ch2_txpipe_txswing,
    input    [3:0] i_ch2_txpipe_txsyncheader,
    input    [2:0] i_ch2_txpipe_width,
    input          i_ch2_uxq_rxcdrlock2dataa,
    input   [13:0] i_ch2_uxq_rxeq_best_eye_vala,
    input          i_ch2_uxq_rxeq_donea,
    input          i_ch2_uxq_rxmargin_nacka,
    input    [1:0] i_ch2_uxq_rxmargin_status_gray_a,
    input          i_ch2_uxq_rxmargin_statusa,
    input          i_ch2_uxq_rxsignaldetect_lfpsa,
    input          i_ch2_uxq_rxsignaldetecta,
    input          i_ch2_uxq_rxstatusa,
    input   [39:0] i_ch2_uxq_rxword,
    input          i_ch2_uxq_synthlcfast_postdiv,
    input          i_ch2_uxq_synthlcmed_postdiv,
    input          i_ch2_uxq_synthlcslow_postdiv,
    input          i_ch2_uxq_txdetectrx_acka,
    input          i_ch2_uxq_txdetectrx_statct,
    input          i_ch2_uxq_txstatusa,
    output  [31:0] o_ch2_lavmm_pcie_rdata,
    output         o_ch2_lavmm_pcie_rdata_valid,
    output         o_ch2_lavmm_pcie_waitreq,
    output         o_ch2_pcs_pclk,
    output         o_ch2_pcs_pipe_rstn,
    output   [5:0] o_ch2_rxpipe_dirfeedback,
    output   [7:0] o_ch2_rxpipe_linkevaluationfeedbackfiguremerit,
    output   [5:0] o_ch2_rxpipe_localfs,
    output   [5:0] o_ch2_rxpipe_locallf,
    output         o_ch2_rxpipe_localtxcoefficientsvalid,
    output  [17:0] o_ch2_rxpipe_localtxpresetcoefficients,
    output   [7:0] o_ch2_rxpipe_p2m_bus,
    output         o_ch2_rxpipe_pclkchangeok,
    output         o_ch2_rxpipe_phystatus,
    output  [39:0] o_ch2_rxpipe_rxdata,
    output   [3:0] o_ch2_rxpipe_rxdatak,
    output         o_ch2_rxpipe_rxdatavalid,
    output         o_ch2_rxpipe_rxelecidlea,
    output         o_ch2_rxpipe_rxstandbystatus,
    output         o_ch2_rxpipe_rxstartblock,
    output   [2:0] o_ch2_rxpipe_rxstatus,
    output   [3:0] o_ch2_rxpipe_rxsyncheader,
    output         o_ch2_rxpipe_rxvalid,
    output         o_ch2_ux_ock_pma_clk,
    output         o_ch2_uxq_lfps_ennt,
    output   [1:0] o_ch2_uxq_pcie_l1ctrla,
    output         o_ch2_uxq_pma_cmn_ctrl,
    output         o_ch2_uxq_pma_ctrl,
    output         o_ch2_uxq_rst_pcs_rx_b_a,
    output         o_ch2_uxq_rst_pcs_tx_b_a,
    output         o_ch2_uxq_rxeiosdetectstata,
    output   [2:0] o_ch2_uxq_rxeq_precal_code_selnt,
    output         o_ch2_uxq_rxeq_starta,
    output         o_ch2_uxq_rxeq_static_ena,
    output         o_ch2_uxq_rxmargin_direction_nt,
    output         o_ch2_uxq_rxmargin_mode_nt,
    output         o_ch2_uxq_rxmargin_offset_change_a,
    output   [6:0] o_ch2_uxq_rxmargin_offset_nt,
    output         o_ch2_uxq_rxmargin_start_a,
    output   [2:0] o_ch2_uxq_rxpstate,
    output   [3:0] o_ch2_uxq_rxrate,
    output         o_ch2_uxq_rxterm_hiz_ena,
    output   [2:0] o_ch2_uxq_rxwidth,
    output         o_ch2_uxq_tstbus_lane,
    output         o_ch2_uxq_txbeacona,
    output   [2:0] o_ch2_uxq_txclkdivrate,
    output         o_ch2_uxq_txdetectrx_reqa,
    output   [5:0] o_ch2_uxq_txdrv_levn,
    output   [4:0] o_ch2_uxq_txdrv_levnm1,
    output   [2:0] o_ch2_uxq_txdrv_levnm2,
    output   [4:0] o_ch2_uxq_txdrv_levnp1,
    output   [3:0] o_ch2_uxq_txdrv_slew,
    output   [3:0] o_ch2_uxq_txelecidle,
    output   [2:0] o_ch2_uxq_txpstate,
    output   [3:0] o_ch2_uxq_txrate,
    output   [2:0] o_ch2_uxq_txwidth,
    output  [39:0] o_ch2_uxq_txword,

    input   [16:0] i_ch3_lavmm_pcie_addr,
    input    [3:0] i_ch3_lavmm_pcie_be,
    input          i_ch3_lavmm_pcie_clk,
    input          i_ch3_lavmm_pcie_read,
    input          i_ch3_lavmm_pcie_rstn,
    input   [31:0] i_ch3_lavmm_pcie_wdata,
    input          i_ch3_lavmm_pcie_write,
    input          i_ch3_pcie_rxword_clk,
    input          i_ch3_pcie_txword_clk,
    input          i_ch3_pcs_pclk,
    input          i_ch3_pcs_pipe_rstn,
    input          i_ch3_txpipe_asyncpowerchangeack,
    input          i_ch3_txpipe_blockaligncontrol,
    input          i_ch3_txpipe_cfg_hw_auto_sp_dis,
    input          i_ch3_txpipe_dirchange,
    input          i_ch3_txpipe_ebuf_mode,
    input          i_ch3_txpipe_encodedecodebypass,
    input    [5:0] i_ch3_txpipe_fs,
    input          i_ch3_txpipe_getlocalpresetcoefficients,
    input          i_ch3_txpipe_invalidrequest,
    input    [5:0] i_ch3_txpipe_lf,
    input    [4:0] i_ch3_txpipe_localpresetindex,
    input          i_ch3_txpipe_lowpin_nt,
    input    [7:0] i_ch3_txpipe_m2p_bus,
    input    [2:0] i_ch3_txpipe_pclk_rate,
    input          i_ch3_txpipe_pclkchangeack,
    input    [3:0] i_ch3_txpipe_phy_mode_nt,
    input    [3:0] i_ch3_txpipe_powerdown,
    input    [2:0] i_ch3_txpipe_rate,
    input          i_ch3_txpipe_rxelecidle_disable_a,
    input          i_ch3_txpipe_rxeqclr,
    input          i_ch3_txpipe_rxeqeval,
    input          i_ch3_txpipe_rxeqinprogress,
    input          i_ch3_txpipe_rxeqtraining,
    input          i_ch3_txpipe_rxpolarity,
    input    [2:0] i_ch3_txpipe_rxpresethint,
    input          i_ch3_txpipe_rxstandby,
    input          i_ch3_txpipe_rxtermination,
    input          i_ch3_txpipe_srisenable,
    input          i_ch3_txpipe_txcmnmode_disable_a,
    input          i_ch3_txpipe_txcompliance,
    input   [39:0] i_ch3_txpipe_txdata,
    input    [3:0] i_ch3_txpipe_txdatak,
    input          i_ch3_txpipe_txdatavalid,
    input   [17:0] i_ch3_txpipe_txdeemph,
    input          i_ch3_txpipe_txdtctrx_lb,
    input          i_ch3_txpipe_txelecidle,
    input    [2:0] i_ch3_txpipe_txmargin,
    input          i_ch3_txpipe_txoneszeros,
    input          i_ch3_txpipe_txstartblock,
    input          i_ch3_txpipe_txswing,
    input    [3:0] i_ch3_txpipe_txsyncheader,
    input    [2:0] i_ch3_txpipe_width,
    input          i_ch3_uxq_rxcdrlock2dataa,
    input   [13:0] i_ch3_uxq_rxeq_best_eye_vala,
    input          i_ch3_uxq_rxeq_donea,
    input          i_ch3_uxq_rxmargin_nacka,
    input    [1:0] i_ch3_uxq_rxmargin_status_gray_a,
    input          i_ch3_uxq_rxmargin_statusa,
    input          i_ch3_uxq_rxsignaldetect_lfpsa,
    input          i_ch3_uxq_rxsignaldetecta,
    input          i_ch3_uxq_rxstatusa,
    input   [39:0] i_ch3_uxq_rxword,
    input          i_ch3_uxq_synthlcfast_postdiv,
    input          i_ch3_uxq_synthlcmed_postdiv,
    input          i_ch3_uxq_synthlcslow_postdiv,
    input          i_ch3_uxq_txdetectrx_acka,
    input          i_ch3_uxq_txdetectrx_statct,
    input          i_ch3_uxq_txstatusa,
    output  [31:0] o_ch3_lavmm_pcie_rdata,
    output         o_ch3_lavmm_pcie_rdata_valid,
    output         o_ch3_lavmm_pcie_waitreq,
    output         o_ch3_pcs_pclk,
    output         o_ch3_pcs_pipe_rstn,
    output   [5:0] o_ch3_rxpipe_dirfeedback,
    output   [7:0] o_ch3_rxpipe_linkevaluationfeedbackfiguremerit,
    output   [5:0] o_ch3_rxpipe_localfs,
    output   [5:0] o_ch3_rxpipe_locallf,
    output         o_ch3_rxpipe_localtxcoefficientsvalid,
    output  [17:0] o_ch3_rxpipe_localtxpresetcoefficients,
    output   [7:0] o_ch3_rxpipe_p2m_bus,
    output         o_ch3_rxpipe_pclkchangeok,
    output         o_ch3_rxpipe_phystatus,
    output  [39:0] o_ch3_rxpipe_rxdata,
    output   [3:0] o_ch3_rxpipe_rxdatak,
    output         o_ch3_rxpipe_rxdatavalid,
    output         o_ch3_rxpipe_rxelecidlea,
    output         o_ch3_rxpipe_rxstandbystatus,
    output         o_ch3_rxpipe_rxstartblock,
    output   [2:0] o_ch3_rxpipe_rxstatus,
    output   [3:0] o_ch3_rxpipe_rxsyncheader,
    output         o_ch3_rxpipe_rxvalid,
    output         o_ch3_ux_ock_pma_clk,
    output         o_ch3_uxq_lfps_ennt,
    output   [1:0] o_ch3_uxq_pcie_l1ctrla,
    output         o_ch3_uxq_pma_cmn_ctrl,
    output         o_ch3_uxq_pma_ctrl,
    output         o_ch3_uxq_rst_pcs_rx_b_a,
    output         o_ch3_uxq_rst_pcs_tx_b_a,
    output         o_ch3_uxq_rxeiosdetectstata,
    output   [2:0] o_ch3_uxq_rxeq_precal_code_selnt,
    output         o_ch3_uxq_rxeq_starta,
    output         o_ch3_uxq_rxeq_static_ena,
    output         o_ch3_uxq_rxmargin_direction_nt,
    output         o_ch3_uxq_rxmargin_mode_nt,
    output         o_ch3_uxq_rxmargin_offset_change_a,
    output   [6:0] o_ch3_uxq_rxmargin_offset_nt,
    output         o_ch3_uxq_rxmargin_start_a,
    output   [2:0] o_ch3_uxq_rxpstate,
    output   [3:0] o_ch3_uxq_rxrate,
    output         o_ch3_uxq_rxterm_hiz_ena,
    output   [2:0] o_ch3_uxq_rxwidth,
    output         o_ch3_uxq_tstbus_lane,
    output         o_ch3_uxq_txbeacona,
    output   [2:0] o_ch3_uxq_txclkdivrate,
    output         o_ch3_uxq_txdetectrx_reqa,
    output   [5:0] o_ch3_uxq_txdrv_levn,
    output   [4:0] o_ch3_uxq_txdrv_levnm1,
    output   [2:0] o_ch3_uxq_txdrv_levnm2,
    output   [4:0] o_ch3_uxq_txdrv_levnp1,
    output   [3:0] o_ch3_uxq_txdrv_slew,
    output   [3:0] o_ch3_uxq_txelecidle,
    output   [2:0] o_ch3_uxq_txpstate,
    output   [3:0] o_ch3_uxq_txrate,
    output   [2:0] o_ch3_uxq_txwidth,
    output  [39:0] o_ch3_uxq_txword,
	
    input   [16:0] i_ch4_lavmm_pcie_addr,
    input    [3:0] i_ch4_lavmm_pcie_be,
    input          i_ch4_lavmm_pcie_clk,
    input          i_ch4_lavmm_pcie_read,
    input          i_ch4_lavmm_pcie_rstn,
    input   [31:0] i_ch4_lavmm_pcie_wdata,
    input          i_ch4_lavmm_pcie_write,
    input          i_ch4_pcie_rxword_clk,
    input          i_ch4_pcie_txword_clk,
    input          i_ch4_pcs_pclk,
    input          i_ch4_pcs_pipe_rstn,
    input          i_ch4_txpipe_asyncpowerchangeack,
    input          i_ch4_txpipe_blockaligncontrol,
    input          i_ch4_txpipe_cfg_hw_auto_sp_dis,
    input          i_ch4_txpipe_dirchange,
    input          i_ch4_txpipe_ebuf_mode,
    input          i_ch4_txpipe_encodedecodebypass,
    input    [5:0] i_ch4_txpipe_fs,
    input          i_ch4_txpipe_getlocalpresetcoefficients,
    input          i_ch4_txpipe_invalidrequest,
    input    [5:0] i_ch4_txpipe_lf,
    input    [4:0] i_ch4_txpipe_localpresetindex,
    input          i_ch4_txpipe_lowpin_nt,
    input    [7:0] i_ch4_txpipe_m2p_bus,
    input    [2:0] i_ch4_txpipe_pclk_rate,
    input          i_ch4_txpipe_pclkchangeack,
    input    [3:0] i_ch4_txpipe_phy_mode_nt,
    input    [3:0] i_ch4_txpipe_powerdown,
    input    [2:0] i_ch4_txpipe_rate,
    input          i_ch4_txpipe_rxelecidle_disable_a,
    input          i_ch4_txpipe_rxeqclr,
    input          i_ch4_txpipe_rxeqeval,
    input          i_ch4_txpipe_rxeqinprogress,
    input          i_ch4_txpipe_rxeqtraining,
    input          i_ch4_txpipe_rxpolarity,
    input    [2:0] i_ch4_txpipe_rxpresethint,
    input          i_ch4_txpipe_rxstandby,
    input          i_ch4_txpipe_rxtermination,
    input          i_ch4_txpipe_srisenable,
    input          i_ch4_txpipe_txcmnmode_disable_a,
    input          i_ch4_txpipe_txcompliance,
    input   [39:0] i_ch4_txpipe_txdata,
    input    [3:0] i_ch4_txpipe_txdatak,
    input          i_ch4_txpipe_txdatavalid,
    input   [17:0] i_ch4_txpipe_txdeemph,
    input          i_ch4_txpipe_txdtctrx_lb,
    input          i_ch4_txpipe_txelecidle,
    input    [2:0] i_ch4_txpipe_txmargin,
    input          i_ch4_txpipe_txoneszeros,
    input          i_ch4_txpipe_txstartblock,
    input          i_ch4_txpipe_txswing,
    input    [3:0] i_ch4_txpipe_txsyncheader,
    input    [2:0] i_ch4_txpipe_width,
    input          i_ch4_uxq_rxcdrlock2dataa,
    input   [13:0] i_ch4_uxq_rxeq_best_eye_vala,
    input          i_ch4_uxq_rxeq_donea,
    input          i_ch4_uxq_rxmargin_nacka,
    input    [1:0] i_ch4_uxq_rxmargin_status_gray_a,
    input          i_ch4_uxq_rxmargin_statusa,
    input          i_ch4_uxq_rxsignaldetect_lfpsa,
    input          i_ch4_uxq_rxsignaldetecta,
    input          i_ch4_uxq_rxstatusa,
    input   [39:0] i_ch4_uxq_rxword,
    input          i_ch4_uxq_synthlcfast_postdiv,
    input          i_ch4_uxq_synthlcmed_postdiv,
    input          i_ch4_uxq_synthlcslow_postdiv,
    input          i_ch4_uxq_txdetectrx_acka,
    input          i_ch4_uxq_txdetectrx_statct,
    input          i_ch4_uxq_txstatusa,
    output  [31:0] o_ch4_lavmm_pcie_rdata,
    output         o_ch4_lavmm_pcie_rdata_valid,
    output         o_ch4_lavmm_pcie_waitreq,
    output         o_ch4_pcs_pclk,
    output         o_ch4_pcs_pipe_rstn,
    output   [5:0] o_ch4_rxpipe_dirfeedback,
    output   [7:0] o_ch4_rxpipe_linkevaluationfeedbackfiguremerit,
    output   [5:0] o_ch4_rxpipe_localfs,
    output   [5:0] o_ch4_rxpipe_locallf,
    output         o_ch4_rxpipe_localtxcoefficientsvalid,
    output  [17:0] o_ch4_rxpipe_localtxpresetcoefficients,
    output   [7:0] o_ch4_rxpipe_p2m_bus,
    output         o_ch4_rxpipe_pclkchangeok,
    output         o_ch4_rxpipe_phystatus,
    output  [39:0] o_ch4_rxpipe_rxdata,
    output   [3:0] o_ch4_rxpipe_rxdatak,
    output         o_ch4_rxpipe_rxdatavalid,
    output         o_ch4_rxpipe_rxelecidlea,
    output         o_ch4_rxpipe_rxstandbystatus,
    output         o_ch4_rxpipe_rxstartblock,
    output   [2:0] o_ch4_rxpipe_rxstatus,
    output   [3:0] o_ch4_rxpipe_rxsyncheader,
    output         o_ch4_rxpipe_rxvalid,
    output         o_ch4_ux_ock_pma_clk,
    output         o_ch4_uxq_lfps_ennt,
    output   [1:0] o_ch4_uxq_pcie_l1ctrla,
    output         o_ch4_uxq_pma_cmn_ctrl,
    output         o_ch4_uxq_pma_ctrl,
    output         o_ch4_uxq_rst_pcs_rx_b_a,
    output         o_ch4_uxq_rst_pcs_tx_b_a,
    output         o_ch4_uxq_rxeiosdetectstata,
    output   [2:0] o_ch4_uxq_rxeq_precal_code_selnt,
    output         o_ch4_uxq_rxeq_starta,
    output         o_ch4_uxq_rxeq_static_ena,
    output         o_ch4_uxq_rxmargin_direction_nt,
    output         o_ch4_uxq_rxmargin_mode_nt,
    output         o_ch4_uxq_rxmargin_offset_change_a,
    output   [6:0] o_ch4_uxq_rxmargin_offset_nt,
    output         o_ch4_uxq_rxmargin_start_a,
    output   [2:0] o_ch4_uxq_rxpstate,
    output   [3:0] o_ch4_uxq_rxrate,
    output         o_ch4_uxq_rxterm_hiz_ena,
    output   [2:0] o_ch4_uxq_rxwidth,
    output         o_ch4_uxq_tstbus_lane,
    output         o_ch4_uxq_txbeacona,
    output   [2:0] o_ch4_uxq_txclkdivrate,
    output         o_ch4_uxq_txdetectrx_reqa,
    output   [5:0] o_ch4_uxq_txdrv_levn,
    output   [4:0] o_ch4_uxq_txdrv_levnm1,
    output   [2:0] o_ch4_uxq_txdrv_levnm2,
    output   [4:0] o_ch4_uxq_txdrv_levnp1,
    output   [3:0] o_ch4_uxq_txdrv_slew,
    output   [3:0] o_ch4_uxq_txelecidle,
    output   [2:0] o_ch4_uxq_txpstate,
    output   [3:0] o_ch4_uxq_txrate,
    output   [2:0] o_ch4_uxq_txwidth,
    output  [39:0] o_ch4_uxq_txword,

    input   [16:0] i_ch5_lavmm_pcie_addr,
    input    [3:0] i_ch5_lavmm_pcie_be,
    input          i_ch5_lavmm_pcie_clk,
    input          i_ch5_lavmm_pcie_read,
    input          i_ch5_lavmm_pcie_rstn,
    input   [31:0] i_ch5_lavmm_pcie_wdata,
    input          i_ch5_lavmm_pcie_write,
    input          i_ch5_pcie_rxword_clk,
    input          i_ch5_pcie_txword_clk,
    input          i_ch5_pcs_pclk,
    input          i_ch5_pcs_pipe_rstn,
    input          i_ch5_txpipe_asyncpowerchangeack,
    input          i_ch5_txpipe_blockaligncontrol,
    input          i_ch5_txpipe_cfg_hw_auto_sp_dis,
    input          i_ch5_txpipe_dirchange,
    input          i_ch5_txpipe_ebuf_mode,
    input          i_ch5_txpipe_encodedecodebypass,
    input    [5:0] i_ch5_txpipe_fs,
    input          i_ch5_txpipe_getlocalpresetcoefficients,
    input          i_ch5_txpipe_invalidrequest,
    input    [5:0] i_ch5_txpipe_lf,
    input    [4:0] i_ch5_txpipe_localpresetindex,
    input          i_ch5_txpipe_lowpin_nt,
    input    [7:0] i_ch5_txpipe_m2p_bus,
    input    [2:0] i_ch5_txpipe_pclk_rate,
    input          i_ch5_txpipe_pclkchangeack,
    input    [3:0] i_ch5_txpipe_phy_mode_nt,
    input    [3:0] i_ch5_txpipe_powerdown,
    input    [2:0] i_ch5_txpipe_rate,
    input          i_ch5_txpipe_rxelecidle_disable_a,
    input          i_ch5_txpipe_rxeqclr,
    input          i_ch5_txpipe_rxeqeval,
    input          i_ch5_txpipe_rxeqinprogress,
    input          i_ch5_txpipe_rxeqtraining,
    input          i_ch5_txpipe_rxpolarity,
    input    [2:0] i_ch5_txpipe_rxpresethint,
    input          i_ch5_txpipe_rxstandby,
    input          i_ch5_txpipe_rxtermination,
    input          i_ch5_txpipe_srisenable,
    input          i_ch5_txpipe_txcmnmode_disable_a,
    input          i_ch5_txpipe_txcompliance,
    input   [39:0] i_ch5_txpipe_txdata,
    input    [3:0] i_ch5_txpipe_txdatak,
    input          i_ch5_txpipe_txdatavalid,
    input   [17:0] i_ch5_txpipe_txdeemph,
    input          i_ch5_txpipe_txdtctrx_lb,
    input          i_ch5_txpipe_txelecidle,
    input    [2:0] i_ch5_txpipe_txmargin,
    input          i_ch5_txpipe_txoneszeros,
    input          i_ch5_txpipe_txstartblock,
    input          i_ch5_txpipe_txswing,
    input    [3:0] i_ch5_txpipe_txsyncheader,
    input    [2:0] i_ch5_txpipe_width,
    input          i_ch5_uxq_rxcdrlock2dataa,
    input   [13:0] i_ch5_uxq_rxeq_best_eye_vala,
    input          i_ch5_uxq_rxeq_donea,
    input          i_ch5_uxq_rxmargin_nacka,
    input    [1:0] i_ch5_uxq_rxmargin_status_gray_a,
    input          i_ch5_uxq_rxmargin_statusa,
    input          i_ch5_uxq_rxsignaldetect_lfpsa,
    input          i_ch5_uxq_rxsignaldetecta,
    input          i_ch5_uxq_rxstatusa,
    input   [39:0] i_ch5_uxq_rxword,
    input          i_ch5_uxq_synthlcfast_postdiv,
    input          i_ch5_uxq_synthlcmed_postdiv,
    input          i_ch5_uxq_synthlcslow_postdiv,
    input          i_ch5_uxq_txdetectrx_acka,
    input          i_ch5_uxq_txdetectrx_statct,
    input          i_ch5_uxq_txstatusa,
    output  [31:0] o_ch5_lavmm_pcie_rdata,
    output         o_ch5_lavmm_pcie_rdata_valid,
    output         o_ch5_lavmm_pcie_waitreq,
    output         o_ch5_pcs_pclk,
    output         o_ch5_pcs_pipe_rstn,
    output   [5:0] o_ch5_rxpipe_dirfeedback,
    output   [7:0] o_ch5_rxpipe_linkevaluationfeedbackfiguremerit,
    output   [5:0] o_ch5_rxpipe_localfs,
    output   [5:0] o_ch5_rxpipe_locallf,
    output         o_ch5_rxpipe_localtxcoefficientsvalid,
    output  [17:0] o_ch5_rxpipe_localtxpresetcoefficients,
    output   [7:0] o_ch5_rxpipe_p2m_bus,
    output         o_ch5_rxpipe_pclkchangeok,
    output         o_ch5_rxpipe_phystatus,
    output  [39:0] o_ch5_rxpipe_rxdata,
    output   [3:0] o_ch5_rxpipe_rxdatak,
    output         o_ch5_rxpipe_rxdatavalid,
    output         o_ch5_rxpipe_rxelecidlea,
    output         o_ch5_rxpipe_rxstandbystatus,
    output         o_ch5_rxpipe_rxstartblock,
    output   [2:0] o_ch5_rxpipe_rxstatus,
    output   [3:0] o_ch5_rxpipe_rxsyncheader,
    output         o_ch5_rxpipe_rxvalid,
    output         o_ch5_ux_ock_pma_clk,
    output         o_ch5_uxq_lfps_ennt,
    output   [1:0] o_ch5_uxq_pcie_l1ctrla,
    output         o_ch5_uxq_pma_cmn_ctrl,
    output         o_ch5_uxq_pma_ctrl,
    output         o_ch5_uxq_rst_pcs_rx_b_a,
    output         o_ch5_uxq_rst_pcs_tx_b_a,
    output         o_ch5_uxq_rxeiosdetectstata,
    output   [2:0] o_ch5_uxq_rxeq_precal_code_selnt,
    output         o_ch5_uxq_rxeq_starta,
    output         o_ch5_uxq_rxeq_static_ena,
    output         o_ch5_uxq_rxmargin_direction_nt,
    output         o_ch5_uxq_rxmargin_mode_nt,
    output         o_ch5_uxq_rxmargin_offset_change_a,
    output   [6:0] o_ch5_uxq_rxmargin_offset_nt,
    output         o_ch5_uxq_rxmargin_start_a,
    output   [2:0] o_ch5_uxq_rxpstate,
    output   [3:0] o_ch5_uxq_rxrate,
    output         o_ch5_uxq_rxterm_hiz_ena,
    output   [2:0] o_ch5_uxq_rxwidth,
    output         o_ch5_uxq_tstbus_lane,
    output         o_ch5_uxq_txbeacona,
    output   [2:0] o_ch5_uxq_txclkdivrate,
    output         o_ch5_uxq_txdetectrx_reqa,
    output   [5:0] o_ch5_uxq_txdrv_levn,
    output   [4:0] o_ch5_uxq_txdrv_levnm1,
    output   [2:0] o_ch5_uxq_txdrv_levnm2,
    output   [4:0] o_ch5_uxq_txdrv_levnp1,
    output   [3:0] o_ch5_uxq_txdrv_slew,
    output   [3:0] o_ch5_uxq_txelecidle,
    output   [2:0] o_ch5_uxq_txpstate,
    output   [3:0] o_ch5_uxq_txrate,
    output   [2:0] o_ch5_uxq_txwidth,
    output  [39:0] o_ch5_uxq_txword,

    input   [16:0] i_ch6_lavmm_pcie_addr,
    input    [3:0] i_ch6_lavmm_pcie_be,
    input          i_ch6_lavmm_pcie_clk,
    input          i_ch6_lavmm_pcie_read,
    input          i_ch6_lavmm_pcie_rstn,
    input   [31:0] i_ch6_lavmm_pcie_wdata,
    input          i_ch6_lavmm_pcie_write,
    input          i_ch6_pcie_rxword_clk,
    input          i_ch6_pcie_txword_clk,
    input          i_ch6_pcs_pclk,
    input          i_ch6_pcs_pipe_rstn,
    input          i_ch6_txpipe_asyncpowerchangeack,
    input          i_ch6_txpipe_blockaligncontrol,
    input          i_ch6_txpipe_cfg_hw_auto_sp_dis,
    input          i_ch6_txpipe_dirchange,
    input          i_ch6_txpipe_ebuf_mode,
    input          i_ch6_txpipe_encodedecodebypass,
    input    [5:0] i_ch6_txpipe_fs,
    input          i_ch6_txpipe_getlocalpresetcoefficients,
    input          i_ch6_txpipe_invalidrequest,
    input    [5:0] i_ch6_txpipe_lf,
    input    [4:0] i_ch6_txpipe_localpresetindex,
    input          i_ch6_txpipe_lowpin_nt,
    input    [7:0] i_ch6_txpipe_m2p_bus,
    input    [2:0] i_ch6_txpipe_pclk_rate,
    input          i_ch6_txpipe_pclkchangeack,
    input    [3:0] i_ch6_txpipe_phy_mode_nt,
    input    [3:0] i_ch6_txpipe_powerdown,
    input    [2:0] i_ch6_txpipe_rate,
    input          i_ch6_txpipe_rxelecidle_disable_a,
    input          i_ch6_txpipe_rxeqclr,
    input          i_ch6_txpipe_rxeqeval,
    input          i_ch6_txpipe_rxeqinprogress,
    input          i_ch6_txpipe_rxeqtraining,
    input          i_ch6_txpipe_rxpolarity,
    input    [2:0] i_ch6_txpipe_rxpresethint,
    input          i_ch6_txpipe_rxstandby,
    input          i_ch6_txpipe_rxtermination,
    input          i_ch6_txpipe_srisenable,
    input          i_ch6_txpipe_txcmnmode_disable_a,
    input          i_ch6_txpipe_txcompliance,
    input   [39:0] i_ch6_txpipe_txdata,
    input    [3:0] i_ch6_txpipe_txdatak,
    input          i_ch6_txpipe_txdatavalid,
    input   [17:0] i_ch6_txpipe_txdeemph,
    input          i_ch6_txpipe_txdtctrx_lb,
    input          i_ch6_txpipe_txelecidle,
    input    [2:0] i_ch6_txpipe_txmargin,
    input          i_ch6_txpipe_txoneszeros,
    input          i_ch6_txpipe_txstartblock,
    input          i_ch6_txpipe_txswing,
    input    [3:0] i_ch6_txpipe_txsyncheader,
    input    [2:0] i_ch6_txpipe_width,
    input          i_ch6_uxq_rxcdrlock2dataa,
    input   [13:0] i_ch6_uxq_rxeq_best_eye_vala,
    input          i_ch6_uxq_rxeq_donea,
    input          i_ch6_uxq_rxmargin_nacka,
    input    [1:0] i_ch6_uxq_rxmargin_status_gray_a,
    input          i_ch6_uxq_rxmargin_statusa,
    input          i_ch6_uxq_rxsignaldetect_lfpsa,
    input          i_ch6_uxq_rxsignaldetecta,
    input          i_ch6_uxq_rxstatusa,
    input   [39:0] i_ch6_uxq_rxword,
    input          i_ch6_uxq_synthlcfast_postdiv,
    input          i_ch6_uxq_synthlcmed_postdiv,
    input          i_ch6_uxq_synthlcslow_postdiv,
    input          i_ch6_uxq_txdetectrx_acka,
    input          i_ch6_uxq_txdetectrx_statct,
    input          i_ch6_uxq_txstatusa,
    output  [31:0] o_ch6_lavmm_pcie_rdata,
    output         o_ch6_lavmm_pcie_rdata_valid,
    output         o_ch6_lavmm_pcie_waitreq,
    output         o_ch6_pcs_pclk,
    output         o_ch6_pcs_pipe_rstn,
    output   [5:0] o_ch6_rxpipe_dirfeedback,
    output   [7:0] o_ch6_rxpipe_linkevaluationfeedbackfiguremerit,
    output   [5:0] o_ch6_rxpipe_localfs,
    output   [5:0] o_ch6_rxpipe_locallf,
    output         o_ch6_rxpipe_localtxcoefficientsvalid,
    output  [17:0] o_ch6_rxpipe_localtxpresetcoefficients,
    output   [7:0] o_ch6_rxpipe_p2m_bus,
    output         o_ch6_rxpipe_pclkchangeok,
    output         o_ch6_rxpipe_phystatus,
    output  [39:0] o_ch6_rxpipe_rxdata,
    output   [3:0] o_ch6_rxpipe_rxdatak,
    output         o_ch6_rxpipe_rxdatavalid,
    output         o_ch6_rxpipe_rxelecidlea,
    output         o_ch6_rxpipe_rxstandbystatus,
    output         o_ch6_rxpipe_rxstartblock,
    output   [2:0] o_ch6_rxpipe_rxstatus,
    output   [3:0] o_ch6_rxpipe_rxsyncheader,
    output         o_ch6_rxpipe_rxvalid,
    output         o_ch6_ux_ock_pma_clk,
    output         o_ch6_uxq_lfps_ennt,
    output   [1:0] o_ch6_uxq_pcie_l1ctrla,
    output         o_ch6_uxq_pma_cmn_ctrl,
    output         o_ch6_uxq_pma_ctrl,
    output         o_ch6_uxq_rst_pcs_rx_b_a,
    output         o_ch6_uxq_rst_pcs_tx_b_a,
    output         o_ch6_uxq_rxeiosdetectstata,
    output   [2:0] o_ch6_uxq_rxeq_precal_code_selnt,
    output         o_ch6_uxq_rxeq_starta,
    output         o_ch6_uxq_rxeq_static_ena,
    output         o_ch6_uxq_rxmargin_direction_nt,
    output         o_ch6_uxq_rxmargin_mode_nt,
    output         o_ch6_uxq_rxmargin_offset_change_a,
    output   [6:0] o_ch6_uxq_rxmargin_offset_nt,
    output         o_ch6_uxq_rxmargin_start_a,
    output   [2:0] o_ch6_uxq_rxpstate,
    output   [3:0] o_ch6_uxq_rxrate,
    output         o_ch6_uxq_rxterm_hiz_ena,
    output   [2:0] o_ch6_uxq_rxwidth,
    output         o_ch6_uxq_tstbus_lane,
    output         o_ch6_uxq_txbeacona,
    output   [2:0] o_ch6_uxq_txclkdivrate,
    output         o_ch6_uxq_txdetectrx_reqa,
    output   [5:0] o_ch6_uxq_txdrv_levn,
    output   [4:0] o_ch6_uxq_txdrv_levnm1,
    output   [2:0] o_ch6_uxq_txdrv_levnm2,
    output   [4:0] o_ch6_uxq_txdrv_levnp1,
    output   [3:0] o_ch6_uxq_txdrv_slew,
    output   [3:0] o_ch6_uxq_txelecidle,
    output   [2:0] o_ch6_uxq_txpstate,
    output   [3:0] o_ch6_uxq_txrate,
    output   [2:0] o_ch6_uxq_txwidth,
    output  [39:0] o_ch6_uxq_txword,

    input   [16:0] i_ch7_lavmm_pcie_addr,
    input    [3:0] i_ch7_lavmm_pcie_be,
    input          i_ch7_lavmm_pcie_clk,
    input          i_ch7_lavmm_pcie_read,
    input          i_ch7_lavmm_pcie_rstn,
    input   [31:0] i_ch7_lavmm_pcie_wdata,
    input          i_ch7_lavmm_pcie_write,
    input          i_ch7_pcie_rxword_clk,
    input          i_ch7_pcie_txword_clk,
    input          i_ch7_pcs_pclk,
    input          i_ch7_pcs_pipe_rstn,
    input          i_ch7_txpipe_asyncpowerchangeack,
    input          i_ch7_txpipe_blockaligncontrol,
    input          i_ch7_txpipe_cfg_hw_auto_sp_dis,
    input          i_ch7_txpipe_dirchange,
    input          i_ch7_txpipe_ebuf_mode,
    input          i_ch7_txpipe_encodedecodebypass,
    input    [5:0] i_ch7_txpipe_fs,
    input          i_ch7_txpipe_getlocalpresetcoefficients,
    input          i_ch7_txpipe_invalidrequest,
    input    [5:0] i_ch7_txpipe_lf,
    input    [4:0] i_ch7_txpipe_localpresetindex,
    input          i_ch7_txpipe_lowpin_nt,
    input    [7:0] i_ch7_txpipe_m2p_bus,
    input    [2:0] i_ch7_txpipe_pclk_rate,
    input          i_ch7_txpipe_pclkchangeack,
    input    [3:0] i_ch7_txpipe_phy_mode_nt,
    input    [3:0] i_ch7_txpipe_powerdown,
    input    [2:0] i_ch7_txpipe_rate,
    input          i_ch7_txpipe_rxelecidle_disable_a,
    input          i_ch7_txpipe_rxeqclr,
    input          i_ch7_txpipe_rxeqeval,
    input          i_ch7_txpipe_rxeqinprogress,
    input          i_ch7_txpipe_rxeqtraining,
    input          i_ch7_txpipe_rxpolarity,
    input    [2:0] i_ch7_txpipe_rxpresethint,
    input          i_ch7_txpipe_rxstandby,
    input          i_ch7_txpipe_rxtermination,
    input          i_ch7_txpipe_srisenable,
    input          i_ch7_txpipe_txcmnmode_disable_a,
    input          i_ch7_txpipe_txcompliance,
    input   [39:0] i_ch7_txpipe_txdata,
    input    [3:0] i_ch7_txpipe_txdatak,
    input          i_ch7_txpipe_txdatavalid,
    input   [17:0] i_ch7_txpipe_txdeemph,
    input          i_ch7_txpipe_txdtctrx_lb,
    input          i_ch7_txpipe_txelecidle,
    input    [2:0] i_ch7_txpipe_txmargin,
    input          i_ch7_txpipe_txoneszeros,
    input          i_ch7_txpipe_txstartblock,
    input          i_ch7_txpipe_txswing,
    input    [3:0] i_ch7_txpipe_txsyncheader,
    input    [2:0] i_ch7_txpipe_width,
    input          i_ch7_uxq_rxcdrlock2dataa,
    input   [13:0] i_ch7_uxq_rxeq_best_eye_vala,
    input          i_ch7_uxq_rxeq_donea,
    input          i_ch7_uxq_rxmargin_nacka,
    input    [1:0] i_ch7_uxq_rxmargin_status_gray_a,
    input          i_ch7_uxq_rxmargin_statusa,
    input          i_ch7_uxq_rxsignaldetect_lfpsa,
    input          i_ch7_uxq_rxsignaldetecta,
    input          i_ch7_uxq_rxstatusa,
    input   [39:0] i_ch7_uxq_rxword,
    input          i_ch7_uxq_synthlcfast_postdiv,
    input          i_ch7_uxq_synthlcmed_postdiv,
    input          i_ch7_uxq_synthlcslow_postdiv,
    input          i_ch7_uxq_txdetectrx_acka,
    input          i_ch7_uxq_txdetectrx_statct,
    input          i_ch7_uxq_txstatusa,
    output  [31:0] o_ch7_lavmm_pcie_rdata,
    output         o_ch7_lavmm_pcie_rdata_valid,
    output         o_ch7_lavmm_pcie_waitreq,
    output         o_ch7_pcs_pclk,
    output         o_ch7_pcs_pipe_rstn,
    output   [5:0] o_ch7_rxpipe_dirfeedback,
    output   [7:0] o_ch7_rxpipe_linkevaluationfeedbackfiguremerit,
    output   [5:0] o_ch7_rxpipe_localfs,
    output   [5:0] o_ch7_rxpipe_locallf,
    output         o_ch7_rxpipe_localtxcoefficientsvalid,
    output  [17:0] o_ch7_rxpipe_localtxpresetcoefficients,
    output   [7:0] o_ch7_rxpipe_p2m_bus,
    output         o_ch7_rxpipe_pclkchangeok,
    output         o_ch7_rxpipe_phystatus,
    output  [39:0] o_ch7_rxpipe_rxdata,
    output   [3:0] o_ch7_rxpipe_rxdatak,
    output         o_ch7_rxpipe_rxdatavalid,
    output         o_ch7_rxpipe_rxelecidlea,
    output         o_ch7_rxpipe_rxstandbystatus,
    output         o_ch7_rxpipe_rxstartblock,
    output   [2:0] o_ch7_rxpipe_rxstatus,
    output   [3:0] o_ch7_rxpipe_rxsyncheader,
    output         o_ch7_rxpipe_rxvalid,
    output         o_ch7_ux_ock_pma_clk,
    output         o_ch7_uxq_lfps_ennt,
    output   [1:0] o_ch7_uxq_pcie_l1ctrla,
    output         o_ch7_uxq_pma_cmn_ctrl,
    output         o_ch7_uxq_pma_ctrl,
    output         o_ch7_uxq_rst_pcs_rx_b_a,
    output         o_ch7_uxq_rst_pcs_tx_b_a,
    output         o_ch7_uxq_rxeiosdetectstata,
    output   [2:0] o_ch7_uxq_rxeq_precal_code_selnt,
    output         o_ch7_uxq_rxeq_starta,
    output         o_ch7_uxq_rxeq_static_ena,
    output         o_ch7_uxq_rxmargin_direction_nt,
    output         o_ch7_uxq_rxmargin_mode_nt,
    output         o_ch7_uxq_rxmargin_offset_change_a,
    output   [6:0] o_ch7_uxq_rxmargin_offset_nt,
    output         o_ch7_uxq_rxmargin_start_a,
    output   [2:0] o_ch7_uxq_rxpstate,
    output   [3:0] o_ch7_uxq_rxrate,
    output         o_ch7_uxq_rxterm_hiz_ena,
    output   [2:0] o_ch7_uxq_rxwidth,
    output         o_ch7_uxq_tstbus_lane,
    output         o_ch7_uxq_txbeacona,
    output   [2:0] o_ch7_uxq_txclkdivrate,
    output         o_ch7_uxq_txdetectrx_reqa,
    output   [5:0] o_ch7_uxq_txdrv_levn,
    output   [4:0] o_ch7_uxq_txdrv_levnm1,
    output   [2:0] o_ch7_uxq_txdrv_levnm2,
    output   [4:0] o_ch7_uxq_txdrv_levnp1,
    output   [3:0] o_ch7_uxq_txdrv_slew,
    output   [3:0] o_ch7_uxq_txelecidle,
    output   [2:0] o_ch7_uxq_txpstate,
    output   [3:0] o_ch7_uxq_txrate,
    output   [2:0] o_ch7_uxq_txwidth,
    output  [39:0] o_ch7_uxq_txword
);

tennm_sm_hssi_pcie_pcs_lane #(
    .sris_enable          (sris_enable),
    .pcie_pcs_mode        (pcie_pcs_mode),
    .pclk_clk_hz          (pclk_clk_hz)
    //.num_of_lanes         (num_of_lanes)
) pcie_pcs_lane_u0 (
    .i_lavmm_pcie_addr(i_ch0_lavmm_pcie_addr[16:0]),
    .i_lavmm_pcie_be(i_ch0_lavmm_pcie_be[3:0]),
    .i_lavmm_pcie_clk(i_ch0_lavmm_pcie_clk),
    .i_lavmm_pcie_read(i_ch0_lavmm_pcie_read),
    .i_lavmm_pcie_rstn(i_ch0_lavmm_pcie_rstn),
    .i_lavmm_pcie_wdata(i_ch0_lavmm_pcie_wdata[31:0]),
    .i_lavmm_pcie_write(i_ch0_lavmm_pcie_write),
    .i_pcie_rxword_clk(i_ch0_pcie_rxword_clk),
    .i_pcie_txword_clk(i_ch0_pcie_txword_clk),
    .i_pcs_pclk(i_ch0_pcs_pclk),
    .i_pcs_pipe_rstn(i_ch0_pcs_pipe_rstn),
    .i_txpipe_asyncpowerchangeack(i_ch0_txpipe_asyncpowerchangeack),
    .i_txpipe_blockaligncontrol(i_ch0_txpipe_blockaligncontrol),
    .i_txpipe_cfg_hw_auto_sp_dis(i_ch0_txpipe_cfg_hw_auto_sp_dis),
    .i_txpipe_dirchange(i_ch0_txpipe_dirchange),
    .i_txpipe_ebuf_mode(i_ch0_txpipe_ebuf_mode),
    .i_txpipe_encodedecodebypass(i_ch0_txpipe_encodedecodebypass),
    .i_txpipe_fs(i_ch0_txpipe_fs[5:0]),
    .i_txpipe_getlocalpresetcoefficients(i_ch0_txpipe_getlocalpresetcoefficients),
    .i_txpipe_invalidrequest(i_ch0_txpipe_invalidrequest),
    .i_txpipe_lf(i_ch0_txpipe_lf[5:0]),
    .i_txpipe_localpresetindex(i_ch0_txpipe_localpresetindex[4:0]),
    .i_txpipe_lowpin_nt(i_ch0_txpipe_lowpin_nt),
    .i_txpipe_m2p_bus(i_ch0_txpipe_m2p_bus[7:0]),
    .i_txpipe_pclk_rate(i_ch0_txpipe_pclk_rate[2:0]),
    .i_txpipe_pclkchangeack(i_ch0_txpipe_pclkchangeack),
    .i_txpipe_phy_mode_nt(i_ch0_txpipe_phy_mode_nt[3:0]),
    .i_txpipe_powerdown(i_ch0_txpipe_powerdown[3:0]),
    .i_txpipe_rate(i_ch0_txpipe_rate[2:0]),
    .i_txpipe_rxelecidle_disable_a(i_ch0_txpipe_rxelecidle_disable_a),
    .i_txpipe_rxeqclr(i_ch0_txpipe_rxeqclr),
    .i_txpipe_rxeqeval(i_ch0_txpipe_rxeqeval),
    .i_txpipe_rxeqinprogress(i_ch0_txpipe_rxeqinprogress),
    .i_txpipe_rxeqtraining(i_ch0_txpipe_rxeqtraining),
    .i_txpipe_rxpolarity(i_ch0_txpipe_rxpolarity),
    .i_txpipe_rxpresethint(i_ch0_txpipe_rxpresethint[2:0]),
    .i_txpipe_rxstandby(i_ch0_txpipe_rxstandby),
    .i_txpipe_rxtermination(i_ch0_txpipe_rxtermination),
    .i_txpipe_srisenable(i_ch0_txpipe_srisenable),
    .i_txpipe_txcmnmode_disable_a(i_ch0_txpipe_txcmnmode_disable_a),
    .i_txpipe_txcompliance(i_ch0_txpipe_txcompliance),
    .i_txpipe_txdata(i_ch0_txpipe_txdata[39:0]),
    .i_txpipe_txdatak(i_ch0_txpipe_txdatak[3:0]),
    .i_txpipe_txdatavalid(i_ch0_txpipe_txdatavalid),
    .i_txpipe_txdeemph(i_ch0_txpipe_txdeemph[17:0]),
    .i_txpipe_txdtctrx_lb(i_ch0_txpipe_txdtctrx_lb),
    .i_txpipe_txelecidle(i_ch0_txpipe_txelecidle),
    .i_txpipe_txmargin(i_ch0_txpipe_txmargin[2:0]),
    .i_txpipe_txoneszeros(i_ch0_txpipe_txoneszeros),
    .i_txpipe_txstartblock(i_ch0_txpipe_txstartblock),
    .i_txpipe_txswing(i_ch0_txpipe_txswing),
    .i_txpipe_txsyncheader(i_ch0_txpipe_txsyncheader[3:0]),
    .i_txpipe_width(i_ch0_txpipe_width[2:0]),
    .i_uxq_rxcdrlock2dataa(i_ch0_uxq_rxcdrlock2dataa),
    .i_uxq_rxeq_best_eye_vala(i_ch0_uxq_rxeq_best_eye_vala[13:0]),
    .i_uxq_rxeq_donea(i_ch0_uxq_rxeq_donea),
    .i_uxq_rxmargin_nacka(i_ch0_uxq_rxmargin_nacka),
    .i_uxq_rxmargin_status_gray_a(i_ch0_uxq_rxmargin_status_gray_a[1:0]),
    .i_uxq_rxmargin_statusa(i_ch0_uxq_rxmargin_statusa),
    .i_uxq_rxsignaldetect_lfpsa(i_ch0_uxq_rxsignaldetect_lfpsa),
    .i_uxq_rxsignaldetecta(i_ch0_uxq_rxsignaldetecta),
    .i_uxq_rxstatusa(i_ch0_uxq_rxstatusa),
    .i_uxq_rxword(i_ch0_uxq_rxword[39:0]),
    .i_uxq_synthlcfast_postdiv(i_ch0_uxq_synthlcfast_postdiv),
    .i_uxq_synthlcmed_postdiv(i_ch0_uxq_synthlcmed_postdiv),
    .i_uxq_synthlcslow_postdiv(i_ch0_uxq_synthlcslow_postdiv),
    .i_uxq_txdetectrx_acka(i_ch0_uxq_txdetectrx_acka),
    .i_uxq_txdetectrx_statct(i_ch0_uxq_txdetectrx_statct),
    .i_uxq_txstatusa(i_ch0_uxq_txstatusa),
    .o_lavmm_pcie_rdata(o_ch0_lavmm_pcie_rdata[31:0]),
    .o_lavmm_pcie_rdata_valid(o_ch0_lavmm_pcie_rdata_valid),
    .o_lavmm_pcie_waitreq(o_ch0_lavmm_pcie_waitreq),
    .o_pcs_pclk(o_ch0_pcs_pclk),
    .o_pcs_pipe_rstn(o_ch0_pcs_pipe_rstn),
    .o_rxpipe_dirfeedback(o_ch0_rxpipe_dirfeedback[5:0]),
    .o_rxpipe_linkevaluationfeedbackfiguremerit(o_ch0_rxpipe_linkevaluationfeedbackfiguremerit[7:0]),
    .o_rxpipe_localfs(o_ch0_rxpipe_localfs[5:0]),
    .o_rxpipe_locallf(o_ch0_rxpipe_locallf[5:0]),
    .o_rxpipe_localtxcoefficientsvalid(o_ch0_rxpipe_localtxcoefficientsvalid),
    .o_rxpipe_localtxpresetcoefficients(o_ch0_rxpipe_localtxpresetcoefficients[17:0]),
    .o_rxpipe_p2m_bus(o_ch0_rxpipe_p2m_bus[7:0]),
    .o_rxpipe_pclkchangeok(o_ch0_rxpipe_pclkchangeok),
    .o_rxpipe_phystatus(o_ch0_rxpipe_phystatus),
    .o_rxpipe_rxdata(o_ch0_rxpipe_rxdata[39:0]),
    .o_rxpipe_rxdatak(o_ch0_rxpipe_rxdatak[3:0]),
    .o_rxpipe_rxdatavalid(o_ch0_rxpipe_rxdatavalid),
    .o_rxpipe_rxelecidlea(o_ch0_rxpipe_rxelecidlea),
    .o_rxpipe_rxstandbystatus(o_ch0_rxpipe_rxstandbystatus),
    .o_rxpipe_rxstartblock(o_ch0_rxpipe_rxstartblock),
    .o_rxpipe_rxstatus(o_ch0_rxpipe_rxstatus[2:0]),
    .o_rxpipe_rxsyncheader(o_ch0_rxpipe_rxsyncheader[3:0]),
    .o_rxpipe_rxvalid(o_ch0_rxpipe_rxvalid),
    .o_ux_ock_pma_clk(o_ch0_ux_ock_pma_clk),
    .o_uxq_lfps_ennt(o_ch0_uxq_lfps_ennt),
    .o_uxq_pcie_l1ctrla(o_ch0_uxq_pcie_l1ctrla[1:0]),
    .o_uxq_pma_cmn_ctrl(o_ch0_uxq_pma_cmn_ctrl),
    .o_uxq_pma_ctrl(o_ch0_uxq_pma_ctrl),
    .o_uxq_rst_pcs_rx_b_a(o_ch0_uxq_rst_pcs_rx_b_a),
    .o_uxq_rst_pcs_tx_b_a(o_ch0_uxq_rst_pcs_tx_b_a),
    .o_uxq_rxeiosdetectstata(o_ch0_uxq_rxeiosdetectstata),
    .o_uxq_rxeq_precal_code_selnt(o_ch0_uxq_rxeq_precal_code_selnt[2:0]),
    .o_uxq_rxeq_starta(o_ch0_uxq_rxeq_starta),
    .o_uxq_rxeq_static_ena(o_ch0_uxq_rxeq_static_ena),
    .o_uxq_rxmargin_direction_nt(o_ch0_uxq_rxmargin_direction_nt),
    .o_uxq_rxmargin_mode_nt(o_ch0_uxq_rxmargin_mode_nt),
    .o_uxq_rxmargin_offset_change_a(o_ch0_uxq_rxmargin_offset_change_a),
    .o_uxq_rxmargin_offset_nt(o_ch0_uxq_rxmargin_offset_nt[6:0]),
    .o_uxq_rxmargin_start_a(o_ch0_uxq_rxmargin_start_a),
    .o_uxq_rxpstate(o_ch0_uxq_rxpstate[2:0]),
    .o_uxq_rxrate(o_ch0_uxq_rxrate[3:0]),
    .o_uxq_rxterm_hiz_ena(o_ch0_uxq_rxterm_hiz_ena),
    .o_uxq_rxwidth(o_ch0_uxq_rxwidth[2:0]),
    .o_uxq_tstbus_lane(o_ch0_uxq_tstbus_lane),
    .o_uxq_txbeacona(o_ch0_uxq_txbeacona),
    .o_uxq_txclkdivrate(o_ch0_uxq_txclkdivrate[2:0]),
    .o_uxq_txdetectrx_reqa(o_ch0_uxq_txdetectrx_reqa),
    .o_uxq_txdrv_levn(o_ch0_uxq_txdrv_levn[5:0]),
    .o_uxq_txdrv_levnm1(o_ch0_uxq_txdrv_levnm1[4:0]),
    .o_uxq_txdrv_levnm2(o_ch0_uxq_txdrv_levnm2[2:0]),
    .o_uxq_txdrv_levnp1(o_ch0_uxq_txdrv_levnp1[4:0]),
    .o_uxq_txdrv_slew(o_ch0_uxq_txdrv_slew[3:0]),
    .o_uxq_txelecidle(o_ch0_uxq_txelecidle[3:0]),
    .o_uxq_txpstate(o_ch0_uxq_txpstate[2:0]),
    .o_uxq_txrate(o_ch0_uxq_txrate[3:0]),
    .o_uxq_txwidth(o_ch0_uxq_txwidth[2:0]),
    .o_uxq_txword(o_ch0_uxq_txword[39:0])

);
tennm_sm_hssi_pcie_pcs_lane #(
    .sris_enable          (sris_enable),
    .pcie_pcs_mode        (pcie_pcs_mode),
    .pclk_clk_hz          (pclk_clk_hz)
    //.num_of_lanes         (num_of_lanes)
) pcie_pcs_lane_u1 (
    .i_lavmm_pcie_addr(i_ch1_lavmm_pcie_addr[16:0]),
    .i_lavmm_pcie_be(i_ch1_lavmm_pcie_be[3:0]),
    .i_lavmm_pcie_clk(i_ch1_lavmm_pcie_clk),
    .i_lavmm_pcie_read(i_ch1_lavmm_pcie_read),
    .i_lavmm_pcie_rstn(i_ch1_lavmm_pcie_rstn),
    .i_lavmm_pcie_wdata(i_ch1_lavmm_pcie_wdata[31:0]),
    .i_lavmm_pcie_write(i_ch1_lavmm_pcie_write),
    .i_pcie_rxword_clk(i_ch1_pcie_rxword_clk),
    .i_pcie_txword_clk(i_ch1_pcie_txword_clk),
    .i_pcs_pclk(i_ch1_pcs_pclk),
    .i_pcs_pipe_rstn(i_ch1_pcs_pipe_rstn),
    .i_txpipe_asyncpowerchangeack(i_ch1_txpipe_asyncpowerchangeack),
    .i_txpipe_blockaligncontrol(i_ch1_txpipe_blockaligncontrol),
    .i_txpipe_cfg_hw_auto_sp_dis(i_ch1_txpipe_cfg_hw_auto_sp_dis),
    .i_txpipe_dirchange(i_ch1_txpipe_dirchange),
    .i_txpipe_ebuf_mode(i_ch1_txpipe_ebuf_mode),
    .i_txpipe_encodedecodebypass(i_ch1_txpipe_encodedecodebypass),
    .i_txpipe_fs(i_ch1_txpipe_fs[5:0]),
    .i_txpipe_getlocalpresetcoefficients(i_ch1_txpipe_getlocalpresetcoefficients),
    .i_txpipe_invalidrequest(i_ch1_txpipe_invalidrequest),
    .i_txpipe_lf(i_ch1_txpipe_lf[5:0]),
    .i_txpipe_localpresetindex(i_ch1_txpipe_localpresetindex[4:0]),
    .i_txpipe_lowpin_nt(i_ch1_txpipe_lowpin_nt),
    .i_txpipe_m2p_bus(i_ch1_txpipe_m2p_bus[7:0]),
    .i_txpipe_pclk_rate(i_ch1_txpipe_pclk_rate[2:0]),
    .i_txpipe_pclkchangeack(i_ch1_txpipe_pclkchangeack),
    .i_txpipe_phy_mode_nt(i_ch1_txpipe_phy_mode_nt[3:0]),
    .i_txpipe_powerdown(i_ch1_txpipe_powerdown[3:0]),
    .i_txpipe_rate(i_ch1_txpipe_rate[2:0]),
    .i_txpipe_rxelecidle_disable_a(i_ch1_txpipe_rxelecidle_disable_a),
    .i_txpipe_rxeqclr(i_ch1_txpipe_rxeqclr),
    .i_txpipe_rxeqeval(i_ch1_txpipe_rxeqeval),
    .i_txpipe_rxeqinprogress(i_ch1_txpipe_rxeqinprogress),
    .i_txpipe_rxeqtraining(i_ch1_txpipe_rxeqtraining),
    .i_txpipe_rxpolarity(i_ch1_txpipe_rxpolarity),
    .i_txpipe_rxpresethint(i_ch1_txpipe_rxpresethint[2:0]),
    .i_txpipe_rxstandby(i_ch1_txpipe_rxstandby),
    .i_txpipe_rxtermination(i_ch1_txpipe_rxtermination),
    .i_txpipe_srisenable(i_ch1_txpipe_srisenable),
    .i_txpipe_txcmnmode_disable_a(i_ch1_txpipe_txcmnmode_disable_a),
    .i_txpipe_txcompliance(i_ch1_txpipe_txcompliance),
    .i_txpipe_txdata(i_ch1_txpipe_txdata[39:0]),
    .i_txpipe_txdatak(i_ch1_txpipe_txdatak[3:0]),
    .i_txpipe_txdatavalid(i_ch1_txpipe_txdatavalid),
    .i_txpipe_txdeemph(i_ch1_txpipe_txdeemph[17:0]),
    .i_txpipe_txdtctrx_lb(i_ch1_txpipe_txdtctrx_lb),
    .i_txpipe_txelecidle(i_ch1_txpipe_txelecidle),
    .i_txpipe_txmargin(i_ch1_txpipe_txmargin[2:0]),
    .i_txpipe_txoneszeros(i_ch1_txpipe_txoneszeros),
    .i_txpipe_txstartblock(i_ch1_txpipe_txstartblock),
    .i_txpipe_txswing(i_ch1_txpipe_txswing),
    .i_txpipe_txsyncheader(i_ch1_txpipe_txsyncheader[3:0]),
    .i_txpipe_width(i_ch1_txpipe_width[2:0]),
    .i_uxq_rxcdrlock2dataa(i_ch1_uxq_rxcdrlock2dataa),
    .i_uxq_rxeq_best_eye_vala(i_ch1_uxq_rxeq_best_eye_vala[13:0]),
    .i_uxq_rxeq_donea(i_ch1_uxq_rxeq_donea),
    .i_uxq_rxmargin_nacka(i_ch1_uxq_rxmargin_nacka),
    .i_uxq_rxmargin_status_gray_a(i_ch1_uxq_rxmargin_status_gray_a[1:0]),
    .i_uxq_rxmargin_statusa(i_ch1_uxq_rxmargin_statusa),
    .i_uxq_rxsignaldetect_lfpsa(i_ch1_uxq_rxsignaldetect_lfpsa),
    .i_uxq_rxsignaldetecta(i_ch1_uxq_rxsignaldetecta),
    .i_uxq_rxstatusa(i_ch1_uxq_rxstatusa),
    .i_uxq_rxword(i_ch1_uxq_rxword[39:0]),
    .i_uxq_synthlcfast_postdiv(i_ch1_uxq_synthlcfast_postdiv),
    .i_uxq_synthlcmed_postdiv(i_ch1_uxq_synthlcmed_postdiv),
    .i_uxq_synthlcslow_postdiv(i_ch1_uxq_synthlcslow_postdiv),
    .i_uxq_txdetectrx_acka(i_ch1_uxq_txdetectrx_acka),
    .i_uxq_txdetectrx_statct(i_ch1_uxq_txdetectrx_statct),
    .i_uxq_txstatusa(i_ch1_uxq_txstatusa),
    .o_lavmm_pcie_rdata(o_ch1_lavmm_pcie_rdata[31:0]),
    .o_lavmm_pcie_rdata_valid(o_ch1_lavmm_pcie_rdata_valid),
    .o_lavmm_pcie_waitreq(o_ch1_lavmm_pcie_waitreq),
    .o_pcs_pclk(o_ch1_pcs_pclk),
    .o_pcs_pipe_rstn(o_ch1_pcs_pipe_rstn),
    .o_rxpipe_dirfeedback(o_ch1_rxpipe_dirfeedback[5:0]),
    .o_rxpipe_linkevaluationfeedbackfiguremerit(o_ch1_rxpipe_linkevaluationfeedbackfiguremerit[7:0]),
    .o_rxpipe_localfs(o_ch1_rxpipe_localfs[5:0]),
    .o_rxpipe_locallf(o_ch1_rxpipe_locallf[5:0]),
    .o_rxpipe_localtxcoefficientsvalid(o_ch1_rxpipe_localtxcoefficientsvalid),
    .o_rxpipe_localtxpresetcoefficients(o_ch1_rxpipe_localtxpresetcoefficients[17:0]),
    .o_rxpipe_p2m_bus(o_ch1_rxpipe_p2m_bus[7:0]),
    .o_rxpipe_pclkchangeok(o_ch1_rxpipe_pclkchangeok),
    .o_rxpipe_phystatus(o_ch1_rxpipe_phystatus),
    .o_rxpipe_rxdata(o_ch1_rxpipe_rxdata[39:0]),
    .o_rxpipe_rxdatak(o_ch1_rxpipe_rxdatak[3:0]),
    .o_rxpipe_rxdatavalid(o_ch1_rxpipe_rxdatavalid),
    .o_rxpipe_rxelecidlea(o_ch1_rxpipe_rxelecidlea),
    .o_rxpipe_rxstandbystatus(o_ch1_rxpipe_rxstandbystatus),
    .o_rxpipe_rxstartblock(o_ch1_rxpipe_rxstartblock),
    .o_rxpipe_rxstatus(o_ch1_rxpipe_rxstatus[2:0]),
    .o_rxpipe_rxsyncheader(o_ch1_rxpipe_rxsyncheader[3:0]),
    .o_rxpipe_rxvalid(o_ch1_rxpipe_rxvalid),
    .o_ux_ock_pma_clk(o_ch1_ux_ock_pma_clk),
    .o_uxq_lfps_ennt(o_ch1_uxq_lfps_ennt),
    .o_uxq_pcie_l1ctrla(o_ch1_uxq_pcie_l1ctrla[1:0]),
    .o_uxq_pma_cmn_ctrl(o_ch1_uxq_pma_cmn_ctrl),
    .o_uxq_pma_ctrl(o_ch1_uxq_pma_ctrl),
    .o_uxq_rst_pcs_rx_b_a(o_ch1_uxq_rst_pcs_rx_b_a),
    .o_uxq_rst_pcs_tx_b_a(o_ch1_uxq_rst_pcs_tx_b_a),
    .o_uxq_rxeiosdetectstata(o_ch1_uxq_rxeiosdetectstata),
    .o_uxq_rxeq_precal_code_selnt(o_ch1_uxq_rxeq_precal_code_selnt[2:0]),
    .o_uxq_rxeq_starta(o_ch1_uxq_rxeq_starta),
    .o_uxq_rxeq_static_ena(o_ch1_uxq_rxeq_static_ena),
    .o_uxq_rxmargin_direction_nt(o_ch1_uxq_rxmargin_direction_nt),
    .o_uxq_rxmargin_mode_nt(o_ch1_uxq_rxmargin_mode_nt),
    .o_uxq_rxmargin_offset_change_a(o_ch1_uxq_rxmargin_offset_change_a),
    .o_uxq_rxmargin_offset_nt(o_ch1_uxq_rxmargin_offset_nt[6:0]),
    .o_uxq_rxmargin_start_a(o_ch1_uxq_rxmargin_start_a),
    .o_uxq_rxpstate(o_ch1_uxq_rxpstate[2:0]),
    .o_uxq_rxrate(o_ch1_uxq_rxrate[3:0]),
    .o_uxq_rxterm_hiz_ena(o_ch1_uxq_rxterm_hiz_ena),
    .o_uxq_rxwidth(o_ch1_uxq_rxwidth[2:0]),
    .o_uxq_tstbus_lane(o_ch1_uxq_tstbus_lane),
    .o_uxq_txbeacona(o_ch1_uxq_txbeacona),
    .o_uxq_txclkdivrate(o_ch1_uxq_txclkdivrate[2:0]),
    .o_uxq_txdetectrx_reqa(o_ch1_uxq_txdetectrx_reqa),
    .o_uxq_txdrv_levn(o_ch1_uxq_txdrv_levn[5:0]),
    .o_uxq_txdrv_levnm1(o_ch1_uxq_txdrv_levnm1[4:0]),
    .o_uxq_txdrv_levnm2(o_ch1_uxq_txdrv_levnm2[2:0]),
    .o_uxq_txdrv_levnp1(o_ch1_uxq_txdrv_levnp1[4:0]),
    .o_uxq_txdrv_slew(o_ch1_uxq_txdrv_slew[3:0]),
    .o_uxq_txelecidle(o_ch1_uxq_txelecidle[3:0]),
    .o_uxq_txpstate(o_ch1_uxq_txpstate[2:0]),
    .o_uxq_txrate(o_ch1_uxq_txrate[3:0]),
    .o_uxq_txwidth(o_ch1_uxq_txwidth[2:0]),
    .o_uxq_txword(o_ch1_uxq_txword[39:0])

);
tennm_sm_hssi_pcie_pcs_lane #(
    .sris_enable          (sris_enable),
    .pcie_pcs_mode        (pcie_pcs_mode),
    .pclk_clk_hz          (pclk_clk_hz)
    //.num_of_lanes         (num_of_lanes)
) pcie_pcs_lane_u2 (
    .i_lavmm_pcie_addr(i_ch2_lavmm_pcie_addr[16:0]),
    .i_lavmm_pcie_be(i_ch2_lavmm_pcie_be[3:0]),
    .i_lavmm_pcie_clk(i_ch2_lavmm_pcie_clk),
    .i_lavmm_pcie_read(i_ch2_lavmm_pcie_read),
    .i_lavmm_pcie_rstn(i_ch2_lavmm_pcie_rstn),
    .i_lavmm_pcie_wdata(i_ch2_lavmm_pcie_wdata[31:0]),
    .i_lavmm_pcie_write(i_ch2_lavmm_pcie_write),
    .i_pcie_rxword_clk(i_ch2_pcie_rxword_clk),
    .i_pcie_txword_clk(i_ch2_pcie_txword_clk),
    .i_pcs_pclk(i_ch2_pcs_pclk),
    .i_pcs_pipe_rstn(i_ch2_pcs_pipe_rstn),
    .i_txpipe_asyncpowerchangeack(i_ch2_txpipe_asyncpowerchangeack),
    .i_txpipe_blockaligncontrol(i_ch2_txpipe_blockaligncontrol),
    .i_txpipe_cfg_hw_auto_sp_dis(i_ch2_txpipe_cfg_hw_auto_sp_dis),
    .i_txpipe_dirchange(i_ch2_txpipe_dirchange),
    .i_txpipe_ebuf_mode(i_ch2_txpipe_ebuf_mode),
    .i_txpipe_encodedecodebypass(i_ch2_txpipe_encodedecodebypass),
    .i_txpipe_fs(i_ch2_txpipe_fs[5:0]),
    .i_txpipe_getlocalpresetcoefficients(i_ch2_txpipe_getlocalpresetcoefficients),
    .i_txpipe_invalidrequest(i_ch2_txpipe_invalidrequest),
    .i_txpipe_lf(i_ch2_txpipe_lf[5:0]),
    .i_txpipe_localpresetindex(i_ch2_txpipe_localpresetindex[4:0]),
    .i_txpipe_lowpin_nt(i_ch2_txpipe_lowpin_nt),
    .i_txpipe_m2p_bus(i_ch2_txpipe_m2p_bus[7:0]),
    .i_txpipe_pclk_rate(i_ch2_txpipe_pclk_rate[2:0]),
    .i_txpipe_pclkchangeack(i_ch2_txpipe_pclkchangeack),
    .i_txpipe_phy_mode_nt(i_ch2_txpipe_phy_mode_nt[3:0]),
    .i_txpipe_powerdown(i_ch2_txpipe_powerdown[3:0]),
    .i_txpipe_rate(i_ch2_txpipe_rate[2:0]),
    .i_txpipe_rxelecidle_disable_a(i_ch2_txpipe_rxelecidle_disable_a),
    .i_txpipe_rxeqclr(i_ch2_txpipe_rxeqclr),
    .i_txpipe_rxeqeval(i_ch2_txpipe_rxeqeval),
    .i_txpipe_rxeqinprogress(i_ch2_txpipe_rxeqinprogress),
    .i_txpipe_rxeqtraining(i_ch2_txpipe_rxeqtraining),
    .i_txpipe_rxpolarity(i_ch2_txpipe_rxpolarity),
    .i_txpipe_rxpresethint(i_ch2_txpipe_rxpresethint[2:0]),
    .i_txpipe_rxstandby(i_ch2_txpipe_rxstandby),
    .i_txpipe_rxtermination(i_ch2_txpipe_rxtermination),
    .i_txpipe_srisenable(i_ch2_txpipe_srisenable),
    .i_txpipe_txcmnmode_disable_a(i_ch2_txpipe_txcmnmode_disable_a),
    .i_txpipe_txcompliance(i_ch2_txpipe_txcompliance),
    .i_txpipe_txdata(i_ch2_txpipe_txdata[39:0]),
    .i_txpipe_txdatak(i_ch2_txpipe_txdatak[3:0]),
    .i_txpipe_txdatavalid(i_ch2_txpipe_txdatavalid),
    .i_txpipe_txdeemph(i_ch2_txpipe_txdeemph[17:0]),
    .i_txpipe_txdtctrx_lb(i_ch2_txpipe_txdtctrx_lb),
    .i_txpipe_txelecidle(i_ch2_txpipe_txelecidle),
    .i_txpipe_txmargin(i_ch2_txpipe_txmargin[2:0]),
    .i_txpipe_txoneszeros(i_ch2_txpipe_txoneszeros),
    .i_txpipe_txstartblock(i_ch2_txpipe_txstartblock),
    .i_txpipe_txswing(i_ch2_txpipe_txswing),
    .i_txpipe_txsyncheader(i_ch2_txpipe_txsyncheader[3:0]),
    .i_txpipe_width(i_ch2_txpipe_width[2:0]),
    .i_uxq_rxcdrlock2dataa(i_ch2_uxq_rxcdrlock2dataa),
    .i_uxq_rxeq_best_eye_vala(i_ch2_uxq_rxeq_best_eye_vala[13:0]),
    .i_uxq_rxeq_donea(i_ch2_uxq_rxeq_donea),
    .i_uxq_rxmargin_nacka(i_ch2_uxq_rxmargin_nacka),
    .i_uxq_rxmargin_status_gray_a(i_ch2_uxq_rxmargin_status_gray_a[1:0]),
    .i_uxq_rxmargin_statusa(i_ch2_uxq_rxmargin_statusa),
    .i_uxq_rxsignaldetect_lfpsa(i_ch2_uxq_rxsignaldetect_lfpsa),
    .i_uxq_rxsignaldetecta(i_ch2_uxq_rxsignaldetecta),
    .i_uxq_rxstatusa(i_ch2_uxq_rxstatusa),
    .i_uxq_rxword(i_ch2_uxq_rxword[39:0]),
    .i_uxq_synthlcfast_postdiv(i_ch2_uxq_synthlcfast_postdiv),
    .i_uxq_synthlcmed_postdiv(i_ch2_uxq_synthlcmed_postdiv),
    .i_uxq_synthlcslow_postdiv(i_ch2_uxq_synthlcslow_postdiv),
    .i_uxq_txdetectrx_acka(i_ch2_uxq_txdetectrx_acka),
    .i_uxq_txdetectrx_statct(i_ch2_uxq_txdetectrx_statct),
    .i_uxq_txstatusa(i_ch2_uxq_txstatusa),
    .o_lavmm_pcie_rdata(o_ch2_lavmm_pcie_rdata[31:0]),
    .o_lavmm_pcie_rdata_valid(o_ch2_lavmm_pcie_rdata_valid),
    .o_lavmm_pcie_waitreq(o_ch2_lavmm_pcie_waitreq),
    .o_pcs_pclk(o_ch2_pcs_pclk),
    .o_pcs_pipe_rstn(o_ch2_pcs_pipe_rstn),
    .o_rxpipe_dirfeedback(o_ch2_rxpipe_dirfeedback[5:0]),
    .o_rxpipe_linkevaluationfeedbackfiguremerit(o_ch2_rxpipe_linkevaluationfeedbackfiguremerit[7:0]),
    .o_rxpipe_localfs(o_ch2_rxpipe_localfs[5:0]),
    .o_rxpipe_locallf(o_ch2_rxpipe_locallf[5:0]),
    .o_rxpipe_localtxcoefficientsvalid(o_ch2_rxpipe_localtxcoefficientsvalid),
    .o_rxpipe_localtxpresetcoefficients(o_ch2_rxpipe_localtxpresetcoefficients[17:0]),
    .o_rxpipe_p2m_bus(o_ch2_rxpipe_p2m_bus[7:0]),
    .o_rxpipe_pclkchangeok(o_ch2_rxpipe_pclkchangeok),
    .o_rxpipe_phystatus(o_ch2_rxpipe_phystatus),
    .o_rxpipe_rxdata(o_ch2_rxpipe_rxdata[39:0]),
    .o_rxpipe_rxdatak(o_ch2_rxpipe_rxdatak[3:0]),
    .o_rxpipe_rxdatavalid(o_ch2_rxpipe_rxdatavalid),
    .o_rxpipe_rxelecidlea(o_ch2_rxpipe_rxelecidlea),
    .o_rxpipe_rxstandbystatus(o_ch2_rxpipe_rxstandbystatus),
    .o_rxpipe_rxstartblock(o_ch2_rxpipe_rxstartblock),
    .o_rxpipe_rxstatus(o_ch2_rxpipe_rxstatus[2:0]),
    .o_rxpipe_rxsyncheader(o_ch2_rxpipe_rxsyncheader[3:0]),
    .o_rxpipe_rxvalid(o_ch2_rxpipe_rxvalid),
    .o_ux_ock_pma_clk(o_ch2_ux_ock_pma_clk),
    .o_uxq_lfps_ennt(o_ch2_uxq_lfps_ennt),
    .o_uxq_pcie_l1ctrla(o_ch2_uxq_pcie_l1ctrla[1:0]),
    .o_uxq_pma_cmn_ctrl(o_ch2_uxq_pma_cmn_ctrl),
    .o_uxq_pma_ctrl(o_ch2_uxq_pma_ctrl),
    .o_uxq_rst_pcs_rx_b_a(o_ch2_uxq_rst_pcs_rx_b_a),
    .o_uxq_rst_pcs_tx_b_a(o_ch2_uxq_rst_pcs_tx_b_a),
    .o_uxq_rxeiosdetectstata(o_ch2_uxq_rxeiosdetectstata),
    .o_uxq_rxeq_precal_code_selnt(o_ch2_uxq_rxeq_precal_code_selnt[2:0]),
    .o_uxq_rxeq_starta(o_ch2_uxq_rxeq_starta),
    .o_uxq_rxeq_static_ena(o_ch2_uxq_rxeq_static_ena),
    .o_uxq_rxmargin_direction_nt(o_ch2_uxq_rxmargin_direction_nt),
    .o_uxq_rxmargin_mode_nt(o_ch2_uxq_rxmargin_mode_nt),
    .o_uxq_rxmargin_offset_change_a(o_ch2_uxq_rxmargin_offset_change_a),
    .o_uxq_rxmargin_offset_nt(o_ch2_uxq_rxmargin_offset_nt[6:0]),
    .o_uxq_rxmargin_start_a(o_ch2_uxq_rxmargin_start_a),
    .o_uxq_rxpstate(o_ch2_uxq_rxpstate[2:0]),
    .o_uxq_rxrate(o_ch2_uxq_rxrate[3:0]),
    .o_uxq_rxterm_hiz_ena(o_ch2_uxq_rxterm_hiz_ena),
    .o_uxq_rxwidth(o_ch2_uxq_rxwidth[2:0]),
    .o_uxq_tstbus_lane(o_ch2_uxq_tstbus_lane),
    .o_uxq_txbeacona(o_ch2_uxq_txbeacona),
    .o_uxq_txclkdivrate(o_ch2_uxq_txclkdivrate[2:0]),
    .o_uxq_txdetectrx_reqa(o_ch2_uxq_txdetectrx_reqa),
    .o_uxq_txdrv_levn(o_ch2_uxq_txdrv_levn[5:0]),
    .o_uxq_txdrv_levnm1(o_ch2_uxq_txdrv_levnm1[4:0]),
    .o_uxq_txdrv_levnm2(o_ch2_uxq_txdrv_levnm2[2:0]),
    .o_uxq_txdrv_levnp1(o_ch2_uxq_txdrv_levnp1[4:0]),
    .o_uxq_txdrv_slew(o_ch2_uxq_txdrv_slew[3:0]),
    .o_uxq_txelecidle(o_ch2_uxq_txelecidle[3:0]),
    .o_uxq_txpstate(o_ch2_uxq_txpstate[2:0]),
    .o_uxq_txrate(o_ch2_uxq_txrate[3:0]),
    .o_uxq_txwidth(o_ch2_uxq_txwidth[2:0]),
    .o_uxq_txword(o_ch2_uxq_txword[39:0])

);
tennm_sm_hssi_pcie_pcs_lane #(
    .sris_enable          (sris_enable),
    .pcie_pcs_mode        (pcie_pcs_mode),
    .pclk_clk_hz          (pclk_clk_hz)
    //.num_of_lanes         (num_of_lanes)
) pcie_pcs_lane_u3 (
    .i_lavmm_pcie_addr(i_ch3_lavmm_pcie_addr[16:0]),
    .i_lavmm_pcie_be(i_ch3_lavmm_pcie_be[3:0]),
    .i_lavmm_pcie_clk(i_ch3_lavmm_pcie_clk),
    .i_lavmm_pcie_read(i_ch3_lavmm_pcie_read),
    .i_lavmm_pcie_rstn(i_ch3_lavmm_pcie_rstn),
    .i_lavmm_pcie_wdata(i_ch3_lavmm_pcie_wdata[31:0]),
    .i_lavmm_pcie_write(i_ch3_lavmm_pcie_write),
    .i_pcie_rxword_clk(i_ch3_pcie_rxword_clk),
    .i_pcie_txword_clk(i_ch3_pcie_txword_clk),
    .i_pcs_pclk(i_ch3_pcs_pclk),
    .i_pcs_pipe_rstn(i_ch3_pcs_pipe_rstn),
    .i_txpipe_asyncpowerchangeack(i_ch3_txpipe_asyncpowerchangeack),
    .i_txpipe_blockaligncontrol(i_ch3_txpipe_blockaligncontrol),
    .i_txpipe_cfg_hw_auto_sp_dis(i_ch3_txpipe_cfg_hw_auto_sp_dis),
    .i_txpipe_dirchange(i_ch3_txpipe_dirchange),
    .i_txpipe_ebuf_mode(i_ch3_txpipe_ebuf_mode),
    .i_txpipe_encodedecodebypass(i_ch3_txpipe_encodedecodebypass),
    .i_txpipe_fs(i_ch3_txpipe_fs[5:0]),
    .i_txpipe_getlocalpresetcoefficients(i_ch3_txpipe_getlocalpresetcoefficients),
    .i_txpipe_invalidrequest(i_ch3_txpipe_invalidrequest),
    .i_txpipe_lf(i_ch3_txpipe_lf[5:0]),
    .i_txpipe_localpresetindex(i_ch3_txpipe_localpresetindex[4:0]),
    .i_txpipe_lowpin_nt(i_ch3_txpipe_lowpin_nt),
    .i_txpipe_m2p_bus(i_ch3_txpipe_m2p_bus[7:0]),
    .i_txpipe_pclk_rate(i_ch3_txpipe_pclk_rate[2:0]),
    .i_txpipe_pclkchangeack(i_ch3_txpipe_pclkchangeack),
    .i_txpipe_phy_mode_nt(i_ch3_txpipe_phy_mode_nt[3:0]),
    .i_txpipe_powerdown(i_ch3_txpipe_powerdown[3:0]),
    .i_txpipe_rate(i_ch3_txpipe_rate[2:0]),
    .i_txpipe_rxelecidle_disable_a(i_ch3_txpipe_rxelecidle_disable_a),
    .i_txpipe_rxeqclr(i_ch3_txpipe_rxeqclr),
    .i_txpipe_rxeqeval(i_ch3_txpipe_rxeqeval),
    .i_txpipe_rxeqinprogress(i_ch3_txpipe_rxeqinprogress),
    .i_txpipe_rxeqtraining(i_ch3_txpipe_rxeqtraining),
    .i_txpipe_rxpolarity(i_ch3_txpipe_rxpolarity),
    .i_txpipe_rxpresethint(i_ch3_txpipe_rxpresethint[2:0]),
    .i_txpipe_rxstandby(i_ch3_txpipe_rxstandby),
    .i_txpipe_rxtermination(i_ch3_txpipe_rxtermination),
    .i_txpipe_srisenable(i_ch3_txpipe_srisenable),
    .i_txpipe_txcmnmode_disable_a(i_ch3_txpipe_txcmnmode_disable_a),
    .i_txpipe_txcompliance(i_ch3_txpipe_txcompliance),
    .i_txpipe_txdata(i_ch3_txpipe_txdata[39:0]),
    .i_txpipe_txdatak(i_ch3_txpipe_txdatak[3:0]),
    .i_txpipe_txdatavalid(i_ch3_txpipe_txdatavalid),
    .i_txpipe_txdeemph(i_ch3_txpipe_txdeemph[17:0]),
    .i_txpipe_txdtctrx_lb(i_ch3_txpipe_txdtctrx_lb),
    .i_txpipe_txelecidle(i_ch3_txpipe_txelecidle),
    .i_txpipe_txmargin(i_ch3_txpipe_txmargin[2:0]),
    .i_txpipe_txoneszeros(i_ch3_txpipe_txoneszeros),
    .i_txpipe_txstartblock(i_ch3_txpipe_txstartblock),
    .i_txpipe_txswing(i_ch3_txpipe_txswing),
    .i_txpipe_txsyncheader(i_ch3_txpipe_txsyncheader[3:0]),
    .i_txpipe_width(i_ch3_txpipe_width[2:0]),
    .i_uxq_rxcdrlock2dataa(i_ch3_uxq_rxcdrlock2dataa),
    .i_uxq_rxeq_best_eye_vala(i_ch3_uxq_rxeq_best_eye_vala[13:0]),
    .i_uxq_rxeq_donea(i_ch3_uxq_rxeq_donea),
    .i_uxq_rxmargin_nacka(i_ch3_uxq_rxmargin_nacka),
    .i_uxq_rxmargin_status_gray_a(i_ch3_uxq_rxmargin_status_gray_a[1:0]),
    .i_uxq_rxmargin_statusa(i_ch3_uxq_rxmargin_statusa),
    .i_uxq_rxsignaldetect_lfpsa(i_ch3_uxq_rxsignaldetect_lfpsa),
    .i_uxq_rxsignaldetecta(i_ch3_uxq_rxsignaldetecta),
    .i_uxq_rxstatusa(i_ch3_uxq_rxstatusa),
    .i_uxq_rxword(i_ch3_uxq_rxword[39:0]),
    .i_uxq_synthlcfast_postdiv(i_ch3_uxq_synthlcfast_postdiv),
    .i_uxq_synthlcmed_postdiv(i_ch3_uxq_synthlcmed_postdiv),
    .i_uxq_synthlcslow_postdiv(i_ch3_uxq_synthlcslow_postdiv),
    .i_uxq_txdetectrx_acka(i_ch3_uxq_txdetectrx_acka),
    .i_uxq_txdetectrx_statct(i_ch3_uxq_txdetectrx_statct),
    .i_uxq_txstatusa(i_ch3_uxq_txstatusa),
    .o_lavmm_pcie_rdata(o_ch3_lavmm_pcie_rdata[31:0]),
    .o_lavmm_pcie_rdata_valid(o_ch3_lavmm_pcie_rdata_valid),
    .o_lavmm_pcie_waitreq(o_ch3_lavmm_pcie_waitreq),
    .o_pcs_pclk(o_ch3_pcs_pclk),
    .o_pcs_pipe_rstn(o_ch3_pcs_pipe_rstn),
    .o_rxpipe_dirfeedback(o_ch3_rxpipe_dirfeedback[5:0]),
    .o_rxpipe_linkevaluationfeedbackfiguremerit(o_ch3_rxpipe_linkevaluationfeedbackfiguremerit[7:0]),
    .o_rxpipe_localfs(o_ch3_rxpipe_localfs[5:0]),
    .o_rxpipe_locallf(o_ch3_rxpipe_locallf[5:0]),
    .o_rxpipe_localtxcoefficientsvalid(o_ch3_rxpipe_localtxcoefficientsvalid),
    .o_rxpipe_localtxpresetcoefficients(o_ch3_rxpipe_localtxpresetcoefficients[17:0]),
    .o_rxpipe_p2m_bus(o_ch3_rxpipe_p2m_bus[7:0]),
    .o_rxpipe_pclkchangeok(o_ch3_rxpipe_pclkchangeok),
    .o_rxpipe_phystatus(o_ch3_rxpipe_phystatus),
    .o_rxpipe_rxdata(o_ch3_rxpipe_rxdata[39:0]),
    .o_rxpipe_rxdatak(o_ch3_rxpipe_rxdatak[3:0]),
    .o_rxpipe_rxdatavalid(o_ch3_rxpipe_rxdatavalid),
    .o_rxpipe_rxelecidlea(o_ch3_rxpipe_rxelecidlea),
    .o_rxpipe_rxstandbystatus(o_ch3_rxpipe_rxstandbystatus),
    .o_rxpipe_rxstartblock(o_ch3_rxpipe_rxstartblock),
    .o_rxpipe_rxstatus(o_ch3_rxpipe_rxstatus[2:0]),
    .o_rxpipe_rxsyncheader(o_ch3_rxpipe_rxsyncheader[3:0]),
    .o_rxpipe_rxvalid(o_ch3_rxpipe_rxvalid),
    .o_ux_ock_pma_clk(o_ch3_ux_ock_pma_clk),
    .o_uxq_lfps_ennt(o_ch3_uxq_lfps_ennt),
    .o_uxq_pcie_l1ctrla(o_ch3_uxq_pcie_l1ctrla[1:0]),
    .o_uxq_pma_cmn_ctrl(o_ch3_uxq_pma_cmn_ctrl),
    .o_uxq_pma_ctrl(o_ch3_uxq_pma_ctrl),
    .o_uxq_rst_pcs_rx_b_a(o_ch3_uxq_rst_pcs_rx_b_a),
    .o_uxq_rst_pcs_tx_b_a(o_ch3_uxq_rst_pcs_tx_b_a),
    .o_uxq_rxeiosdetectstata(o_ch3_uxq_rxeiosdetectstata),
    .o_uxq_rxeq_precal_code_selnt(o_ch3_uxq_rxeq_precal_code_selnt[2:0]),
    .o_uxq_rxeq_starta(o_ch3_uxq_rxeq_starta),
    .o_uxq_rxeq_static_ena(o_ch3_uxq_rxeq_static_ena),
    .o_uxq_rxmargin_direction_nt(o_ch3_uxq_rxmargin_direction_nt),
    .o_uxq_rxmargin_mode_nt(o_ch3_uxq_rxmargin_mode_nt),
    .o_uxq_rxmargin_offset_change_a(o_ch3_uxq_rxmargin_offset_change_a),
    .o_uxq_rxmargin_offset_nt(o_ch3_uxq_rxmargin_offset_nt[6:0]),
    .o_uxq_rxmargin_start_a(o_ch3_uxq_rxmargin_start_a),
    .o_uxq_rxpstate(o_ch3_uxq_rxpstate[2:0]),
    .o_uxq_rxrate(o_ch3_uxq_rxrate[3:0]),
    .o_uxq_rxterm_hiz_ena(o_ch3_uxq_rxterm_hiz_ena),
    .o_uxq_rxwidth(o_ch3_uxq_rxwidth[2:0]),
    .o_uxq_tstbus_lane(o_ch3_uxq_tstbus_lane),
    .o_uxq_txbeacona(o_ch3_uxq_txbeacona),
    .o_uxq_txclkdivrate(o_ch3_uxq_txclkdivrate[2:0]),
    .o_uxq_txdetectrx_reqa(o_ch3_uxq_txdetectrx_reqa),
    .o_uxq_txdrv_levn(o_ch3_uxq_txdrv_levn[5:0]),
    .o_uxq_txdrv_levnm1(o_ch3_uxq_txdrv_levnm1[4:0]),
    .o_uxq_txdrv_levnm2(o_ch3_uxq_txdrv_levnm2[2:0]),
    .o_uxq_txdrv_levnp1(o_ch3_uxq_txdrv_levnp1[4:0]),
    .o_uxq_txdrv_slew(o_ch3_uxq_txdrv_slew[3:0]),
    .o_uxq_txelecidle(o_ch3_uxq_txelecidle[3:0]),
    .o_uxq_txpstate(o_ch3_uxq_txpstate[2:0]),
    .o_uxq_txrate(o_ch3_uxq_txrate[3:0]),
    .o_uxq_txwidth(o_ch3_uxq_txwidth[2:0]),
    .o_uxq_txword(o_ch3_uxq_txword[39:0])

);

assign o_ch4_rxpipe_dirfeedback = '0;
assign o_ch4_rxpipe_linkevaluationfeedbackfiguremerit = '0;
assign o_ch4_rxpipe_localfs = '0;
assign o_ch4_rxpipe_locallf = '0;
assign o_ch4_rxpipe_localtxcoefficientsvalid = '0;
assign o_ch4_rxpipe_localtxpresetcoefficients = '0;
assign o_ch4_rxpipe_p2m_bus = '0;
assign o_ch4_rxpipe_pclkchangeok = '0;
assign o_ch4_rxpipe_phystatus = '0;
assign o_ch4_rxpipe_rxdata = '0;
assign o_ch4_rxpipe_rxdatak = '0;
assign o_ch4_rxpipe_rxdatavalid = '0;
assign o_ch4_rxpipe_rxelecidlea = '0;
assign o_ch4_rxpipe_rxstandbystatus = '0;
assign o_ch4_rxpipe_rxstartblock = '0;
assign o_ch4_rxpipe_rxstatus = '0;
assign o_ch4_rxpipe_rxsyncheader = '0;
assign o_ch4_rxpipe_rxvalid = '0;

assign o_ch5_rxpipe_dirfeedback = '0;
assign o_ch5_rxpipe_linkevaluationfeedbackfiguremerit = '0;
assign o_ch5_rxpipe_localfs = '0;
assign o_ch5_rxpipe_locallf = '0;
assign o_ch5_rxpipe_localtxcoefficientsvalid = '0;
assign o_ch5_rxpipe_localtxpresetcoefficients = '0;
assign o_ch5_rxpipe_p2m_bus = '0;
assign o_ch5_rxpipe_pclkchangeok = '0;
assign o_ch5_rxpipe_phystatus = '0;
assign o_ch5_rxpipe_rxdata = '0;
assign o_ch5_rxpipe_rxdatak = '0;
assign o_ch5_rxpipe_rxdatavalid = '0;
assign o_ch5_rxpipe_rxelecidlea = '0;
assign o_ch5_rxpipe_rxstandbystatus = '0;
assign o_ch5_rxpipe_rxstartblock = '0;
assign o_ch5_rxpipe_rxstatus = '0;
assign o_ch5_rxpipe_rxsyncheader = '0;
assign o_ch5_rxpipe_rxvalid = '0;

assign o_ch6_rxpipe_dirfeedback = '0;
assign o_ch6_rxpipe_linkevaluationfeedbackfiguremerit = '0;
assign o_ch6_rxpipe_localfs = '0;
assign o_ch6_rxpipe_locallf = '0;
assign o_ch6_rxpipe_localtxcoefficientsvalid = '0;
assign o_ch6_rxpipe_localtxpresetcoefficients = '0;
assign o_ch6_rxpipe_p2m_bus = '0;
assign o_ch6_rxpipe_pclkchangeok = '0;
assign o_ch6_rxpipe_phystatus = '0;
assign o_ch6_rxpipe_rxdata = '0;
assign o_ch6_rxpipe_rxdatak = '0;
assign o_ch6_rxpipe_rxdatavalid = '0;
assign o_ch6_rxpipe_rxelecidlea = '0;
assign o_ch6_rxpipe_rxstandbystatus = '0;
assign o_ch6_rxpipe_rxstartblock = '0;
assign o_ch6_rxpipe_rxstatus = '0;
assign o_ch6_rxpipe_rxsyncheader = '0;
assign o_ch6_rxpipe_rxvalid = '0;

assign o_ch7_rxpipe_dirfeedback = '0;
assign o_ch7_rxpipe_linkevaluationfeedbackfiguremerit = '0;
assign o_ch7_rxpipe_localfs = '0;
assign o_ch7_rxpipe_locallf = '0;
assign o_ch7_rxpipe_localtxcoefficientsvalid = '0;
assign o_ch7_rxpipe_localtxpresetcoefficients = '0;
assign o_ch7_rxpipe_p2m_bus = '0;
assign o_ch7_rxpipe_pclkchangeok = '0;
assign o_ch7_rxpipe_phystatus = '0;
assign o_ch7_rxpipe_rxdata = '0;
assign o_ch7_rxpipe_rxdatak = '0;
assign o_ch7_rxpipe_rxdatavalid = '0;
assign o_ch7_rxpipe_rxelecidlea = '0;
assign o_ch7_rxpipe_rxstandbystatus = '0;
assign o_ch7_rxpipe_rxstartblock = '0;
assign o_ch7_rxpipe_rxstatus = '0;
assign o_ch7_rxpipe_rxsyncheader = '0;
assign o_ch7_rxpipe_rxvalid = '0;

endmodule

