-- gts_reset_sequencer.vhd

-- Generated using ACDS version 25.1 129

library IEEE;
library intel_srcss_gts_400;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity gts_reset_sequencer is
	port (
		o_pma_cu_clk                 : out std_logic_vector(0 downto 0);        --                 o_pma_cu_clk.clk,                        PMA control unit clock output, 1 per quad of a shoreline. For example, SPLL is used for QHIP/s across quads then 1 output port to be connected to each quad input.
		i_refclk_bus_out             : in  std_logic                    := '0'; --             i_refclk_bus_out.refclk_bus_out,             Refclk fail status from 1 QHIP in this shoreline which says if the clkrx refclk failure has occured
		o_shoreline_refclk_fail_stat : out std_logic                            -- o_shoreline_refclk_fail_stat.shoreline_refclk_fail_stat, Refclk fail status to the user design which says if the clkrx refclk failure has occured
	);
end entity gts_reset_sequencer;

architecture rtl of gts_reset_sequencer is
	component gts_reset_sequencer_intel_srcss_gts_400_cobgnsy_cmp is
		generic (
			SRC_RS_DISABLE      : boolean := false;
			NUM_LANES_SHORELINE : integer := 1;
			NUM_BANKS_SHORELINE : integer := 1
		);
		port (
			o_pma_cu_clk                 : out std_logic_vector(NUM_BANKS_SHORELINE-1 downto 0);                    -- clk
			i_refclk_bus_out             : in  std_logic                                        := 'X';             -- refclk_bus_out
			o_shoreline_refclk_fail_stat : out std_logic;                                                           -- shoreline_refclk_fail_stat
			o_src_rs_grant               : out std_logic_vector(0 downto 0);                                        -- src_rs_grant
			i_src_rs_priority            : in  std_logic_vector(0 downto 0)                     := (others => 'X'); -- src_rs_priority
			i_src_rs_req                 : in  std_logic_vector(0 downto 0)                     := (others => 'X')  -- src_rs_req
		);
	end component gts_reset_sequencer_intel_srcss_gts_400_cobgnsy_cmp;

	for intel_srcss_gts_0 : gts_reset_sequencer_intel_srcss_gts_400_cobgnsy_cmp
		use entity intel_srcss_gts_400.gts_reset_sequencer_intel_srcss_gts_400_cobgnsy;
begin

	intel_srcss_gts_0 : component gts_reset_sequencer_intel_srcss_gts_400_cobgnsy_cmp
		generic map (
			SRC_RS_DISABLE      => true,
			NUM_LANES_SHORELINE => 1,
			NUM_BANKS_SHORELINE => 1
		)
		port map (
			o_pma_cu_clk                 => o_pma_cu_clk,                 --                 o_pma_cu_clk.clk
			i_refclk_bus_out             => i_refclk_bus_out,             --             i_refclk_bus_out.refclk_bus_out
			o_shoreline_refclk_fail_stat => o_shoreline_refclk_fail_stat, -- o_shoreline_refclk_fail_stat.shoreline_refclk_fail_stat
			o_src_rs_grant               => open,                         --                  (terminated)
			i_src_rs_priority            => "0",                          --                  (terminated)
			i_src_rs_req                 => "0"                           --                  (terminated)
		);

end architecture rtl; -- of gts_reset_sequencer
