	component gts_reset_sequencer is
		port (
			o_pma_cu_clk                 : out std_logic_vector(0 downto 0);        -- clk
			i_refclk_bus_out             : in  std_logic                    := 'X'; -- refclk_bus_out
			o_shoreline_refclk_fail_stat : out std_logic                            -- shoreline_refclk_fail_stat
		);
	end component gts_reset_sequencer;

	u0 : component gts_reset_sequencer
		port map (
			o_pma_cu_clk                 => CONNECTED_TO_o_pma_cu_clk,                 --                 o_pma_cu_clk.clk
			i_refclk_bus_out             => CONNECTED_TO_i_refclk_bus_out,             --             i_refclk_bus_out.refclk_bus_out
			o_shoreline_refclk_fail_stat => CONNECTED_TO_o_shoreline_refclk_fail_stat  -- o_shoreline_refclk_fail_stat.shoreline_refclk_fail_stat
		);

