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(* icm_name="sm_hssi_pcie_clk_mux", module_type="mux", simple_name="UNKNOWN", atom_type__std *)
module tennm_sm_hssi_pcie_clk_mux #(
        parameter sel                                                = "SEL_UNUSED"                   /* Settings: SEL_TOP, SEL_MIDDLE, SEL_BOT, SEL_UNUSED, SEL_DISABLED */
    )
    (
        input i_bot_clk,
        input i_middle_clk,
        input i_top_clk,
        input i_unused_clk,
        output o_clk
    );

`ifdef DDM_BASED_COREIP_GENERATOR
    sm_hssi_pcie_clk_mux
`ifdef DEFINE_SF_RTL_MODULE_PARAMETERS
    #(
        .sel(sel)
    )
`endif // DEFINE_SF_RTL_MODULE_PARAMETERS
    x_sm_hssi_pcie_clk_mux (
        .i_bot_clk(i_bot_clk),
        .i_middle_clk(i_middle_clk),
        .i_top_clk(i_top_clk),
        .i_unused_clk(i_unused_clk),
        .o_clk(o_clk)
        );
`else // ifdef DDM_BASED_COREIP_GENERATOR
    generate
        if ( "SEL_BOT" == sel ) begin : sel_is_SEL_BOT
            assign o_clk = i_bot_clk;
        end : sel_is_SEL_BOT
        if ( "SEL_MIDDLE" == sel ) begin : sel_is_SEL_MIDDLE
            assign o_clk = i_middle_clk;
        end : sel_is_SEL_MIDDLE
        if ( "SEL_TOP" == sel ) begin : sel_is_SEL_TOP
            assign o_clk = i_top_clk;
        end : sel_is_SEL_TOP
        if ( "SEL_UNUSED" == sel ) begin : sel_is_SEL_UNUSED
            assign o_clk = i_unused_clk;
        end : sel_is_SEL_UNUSED
    endgenerate
`endif // ifdef DDM_BASED_COREIP_GENERATOR

endmodule // tennm_sm_hssi_pcie_clk_mux

(* icm_name="sm_hssi_pcie_data_mux", module_type="mux", simple_name="UNKNOWN", atom_type__std *)
module tennm_sm_hssi_pcie_data_mux #(
        parameter sel                                                = "SEL_UNUSED"                   /* Settings: SEL_TOP, SEL_MIDDLE, SEL_BOT, SEL_UNUSED, SEL_DISABLED */
    )
    (
        input i_bot_data,
        input i_middle_data,
        input i_top_data,
        input i_unused_data,
        output o_data
    );

`ifdef DDM_BASED_COREIP_GENERATOR
    sm_hssi_pcie_data_mux
`ifdef DEFINE_SF_RTL_MODULE_PARAMETERS
    #(
        .sel(sel)
    )
`endif // DEFINE_SF_RTL_MODULE_PARAMETERS
    x_sm_hssi_pcie_data_mux (
        .i_bot_data(i_bot_data),
        .i_middle_data(i_middle_data),
        .i_top_data(i_top_data),
        .i_unused_data(i_unused_data),
        .o_data(o_data)
        );
`else // ifdef DDM_BASED_COREIP_GENERATOR
    generate
        if ( "SEL_BOT" == sel ) begin : sel_is_SEL_BOT
            assign o_data = i_bot_data;
        end : sel_is_SEL_BOT
        if ( "SEL_MIDDLE" == sel ) begin : sel_is_SEL_MIDDLE
            assign o_data = i_middle_data;
        end : sel_is_SEL_MIDDLE
        if ( "SEL_TOP" == sel ) begin : sel_is_SEL_TOP
            assign o_data = i_top_data;
        end : sel_is_SEL_TOP
        if ( "SEL_UNUSED" == sel ) begin : sel_is_SEL_UNUSED
            assign o_data = i_unused_data;
        end : sel_is_SEL_UNUSED
    endgenerate
`endif // ifdef DDM_BASED_COREIP_GENERATOR

endmodule // tennm_sm_hssi_pcie_data_mux

(* icm_name="sm_pld_rx_mux", module_type="mux", simple_name="UNKNOWN", atom_type__std *)
module tennm_sm_pld_rx_mux 
    #(
        parameter sel                                                = "SEL_UNUSED"                   /* Settings: SEL_PCIE, SEL_PCIE_BOND, SEL_ETH, SEL_UNUSED */
    )
    (
        input [39:0] i_eth,
        input [79:0] i_pcie,
        input [79:0] i_pcie_bond,
        output [79:0] o_rx_data
    );

`ifdef DDM_BASED_COREIP_GENERATOR
    sm_pld_rx_mux 
`ifdef DEFINE_SF_RTL_MODULE_PARAMETERS
    #(
        .sel(sel)
    )
`endif // ifdef DEFINE_SF_RTL_MODULE_PARAMETERS
    x_sm_pld_rx_mux (
        .i_eth(i_eth),
        .i_pcie(i_pcie),
        .i_pcie_bond(i_pcie_bond),
        .o_rx_data(o_rx_data)
        );
`else // ifdef DDM_BASED_COREIP_GENERATOR
    generate
        if ( "SEL_PCIE" == sel ) begin : sel_is_PCIE
            assign o_rx_data = i_pcie;
        end : sel_is_PCIE
        if ( "SEL_PCIE_BOND" == sel ) begin : sel_is_PCIE_BOND
            assign o_rx_data = i_pcie_bond;
        end : sel_is_PCIE_BOND
        if ( "SEL_ETH" == sel ) begin : sel_is_ETH
            assign o_rx_data = {40'b0, i_eth};
        end : sel_is_ETH
    endgenerate
`endif // ifdef DDM_BASED_COREIP_GENERATOR

endmodule // tennm_sm_pld_rx_mux

(* icm_name="sm_pld_tx_demux", module_type="decoder", simple_name="UNKNOWN", atom_type__std *)
module tennm_sm_pld_tx_demux 
    #(
        parameter sel                                                = "SEL_UNUSED"                   /* Settings: SEL_PCIE, SEL_PCIE_BOND, SEL_ETH, SEL_UNUSED */
    )
    (
        input i_ss_tx_fifo_rd_empty,
        input i_ss_tx_fifo_rd_pempty,
        input [79:0] i_tx_data,
        output [39:0] o_eth,
        output [79:0] o_pcie,
        output [79:0] o_pcie_bond,
        output o_ss_tx_fifo_rd_en
    );

`ifdef DDM_BASED_COREIP_GENERATOR
    sm_pld_tx_demux 
`ifdef DEFINE_SF_RTL_MODULE_PARAMETERS
    #(
        .sel(sel)
    )
`endif // ifdef DEFINE_SF_RTL_MODULE_PARAMETERS
    x_sm_pld_tx_demux (
        .i_ss_tx_fifo_rd_empty(i_ss_tx_fifo_rd_empty),
        .i_ss_tx_fifo_rd_pempty(i_ss_tx_fifo_rd_pempty),
        .i_tx_data(i_tx_data),
        .o_eth(o_eth),
        .o_pcie(o_pcie),
        .o_pcie_bond(o_pcie_bond),
        .o_ss_tx_fifo_rd_en(o_ss_tx_fifo_rd_en)
        );
`else // ifdef DDM_BASED_COREIP_GENERATOR
    generate
        if ( "SEL_PCIE" == sel ) begin : sel_is_PCIE
            assign o_pcie = i_tx_data;
            assign o_eth = 40'b0;
            assign o_pcie_bond = 80'b0;
        end : sel_is_PCIE
        if ( "SEL_PCIE_BOND" == sel ) begin : sel_is_PCIE_BOND
            assign o_pcie = /* REVIEW */ 80'b0;
            assign o_eth = /* REVIEW */ 40'b0;
            assign o_pcie_bond = /* REVIEW */ 80'b0;
        end : sel_is_PCIE_BOND
        if ( "SEL_ETH" == sel ) begin : sel_is_ETH
            assign o_pcie = 80'b0;
            assign o_eth = i_tx_data[39:0];
            assign o_pcie_bond = 80'b0;
        end : sel_is_ETH
    endgenerate
`endif // ifdef DDM_BASED_COREIP_GENERATOR

endmodule // tennm_sm_pld_tx_demux

(* icm_name="sm_hssi_pld_chnl_rx_fifo_wr_clk_mux", module_type="mux", simple_name="UNKNOWN", atom_type__std *)
module tennm_sm_hssi_pld_chnl_rx_fifo_wr_clk_mux 
    #(
        parameter sel                                                = "SEL_UNUSED"                   /* Settings: SEL_ETH_OR_PTP, SEL_PCIE, SEL_PCIE_TOP, SEL_UNUSED */
    )
    (
        input i_eth_or_ptp,
        input i_pcie,
        input i_pcie_top,
        output o_rxfifo_ss_write_clk
    );

`ifdef DDM_BASED_COREIP_GENERATOR
    sm_hssi_pld_chnl_rx_fifo_wr_clk_mux 
`ifdef DEFINE_SF_RTL_MODULE_PARAMETERS
    #(
        .sel(sel)
    )
`endif // ifdef DEFINE_SF_RTL_MODULE_PARAMETERS
    x_sm_hssi_pld_chnl_rx_fifo_wr_clk_mux (
        .i_eth_or_ptp(i_eth_or_ptp),
        .i_pcie(i_pcie),
        .i_pcie_top(i_pcie_top),
        .o_rxfifo_ss_write_clk(o_rxfifo_ss_write_clk)
        );
`else // ifdef DDM_BASED_COREIP_GENERATOR
    generate
        if ( "SEL_ETH_OR_PTP" == sel ) begin : sel_is_ETH_OR_PTP
            assign o_rxfifo_ss_write_clk = i_eth_or_ptp;
        end : sel_is_ETH_OR_PTP
        if ( "SEL_PCIE" == sel ) begin : sel_is_PCIE
            assign o_rxfifo_ss_write_clk = i_pcie;
        end : sel_is_PCIE
        if ( "SEL_PCIE_TOP" == sel ) begin : sel_is_PCIE_TOP
            assign o_rxfifo_ss_write_clk = i_pcie_top;
        end : sel_is_PCIE_TOP
    endgenerate
`endif // ifdef DDM_BASED_COREIP_GENERATOR

endmodule // tennm_sm_hssi_pld_chnl_rx_fifo_wr_clk_mux


(* icm_name="sm_hssi_pld_chnl_tx_fifo_rd_clk_mux", module_type="mux", simple_name="UNKNOWN", atom_type__std *)
module tennm_sm_hssi_pld_chnl_tx_fifo_rd_clk_mux 
    #(
        parameter sel                                                = "SEL_UNUSED"                   /* Settings: SEL_ETH_OR_PTP, SEL_PCIE, SEL_PCIE_TOP, SEL_UNUSED */
    )
    (
        input i_eth_or_ptp,
        input i_pcie,
        input i_pcie_top,
        output o_tx_fifo_ss_read_clk
    );

`ifdef DDM_BASED_COREIP_GENERATOR
    sm_hssi_pld_chnl_tx_fifo_rd_clk_mux 
`ifdef DEFINE_SF_RTL_MODULE_PARAMETERS
    #(
        .sel(sel)
    )
`endif // ifdef DEFINE_SF_RTL_MODULE_PARAMETERS
    x_sm_hssi_pld_chnl_tx_fifo_rd_clk_mux (
        .i_eth_or_ptp(i_eth_or_ptp),
        .i_pcie(i_pcie),
        .i_pcie_top(i_pcie_top),
        .o_tx_fifo_ss_read_clk(o_tx_fifo_ss_read_clk)
        );
`else // ifdef DDM_BASED_COREIP_GENERATOR
    generate
        if ( "SEL_ETH_OR_PTP" == sel ) begin : sel_is_ETH_OR_PTP
            assign o_tx_fifo_ss_read_clk = i_eth_or_ptp;
        end : sel_is_ETH_OR_PTP
        if ( "SEL_PCIE" == sel ) begin : sel_is_PCIE
            assign o_tx_fifo_ss_read_clk = i_pcie;
        end : sel_is_PCIE
        if ( "SEL_PCIE_TOP" == sel ) begin : sel_is_PCIE_TOP
            assign o_tx_fifo_ss_read_clk = i_pcie_top;
        end : sel_is_PCIE_TOP
    endgenerate
`endif // ifdef DDM_BASED_COREIP_GENERATOR

endmodule // tennm_sm_hssi_pld_chnl_tx_fifo_rd_clk_mux

`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "2VFQJEphUyq8CwC8gsQTzYRiy4CKnFrR8CoPpc7J3IzqCDuq0mHM6K7V2GezThdey82bBMPNbBgDXoriW44Et6j33hxoHnsMU5dCyiGmutmx81l+P7dd/ZZHRzlYw5WTW/WUBsKFIF04NTI3bdb3z9ruzOKjaZWeulfiAYKi1f05itJlxUyPe9iDebXZUNjziA/9KjCM/P0e+uVjXL6IPI9Kd704g3ZM2iG17dIZikyyj5SrgwghBf7rxBvd74rpxZ1/8SepT6XONBjx0hG/Amo1rOSNiDAN6h5SQCGrwm5HrpsQg5GUY9I7CmVwoGG8UJoHqxcUMeWkU2rJm1mYnarIKyKo/lkMyk9ZvpS3b9THjEm/iqgRT9hALrApSuBWmcAJbF5VTqBvtOtRQ8ithnLQ2UAGLBDEMoc6kaJw79D+n97Lkbl4hQoBcUDoERirDV4gfAqp+tYpQz1A5/xNWzGBxLiBtbsBTjF8AkX58fB5dbskf7m/NDXcaiPLcApySFXdRV25NelrGL+Jgow9nNPrTNKo0/JwoDTVQNA7UEUX9tphbYcjatVeJ6aEtrjIZcWP++GwA1ecTwPGLTvHyvfXMLOpQunMxVISKhx1LWaGvJnEW3J7edKEdJRTjSVVX5oOSo9dKhR13RbymNYQs0tT0Y7M/S+j7bDvf5b1eRq3Zg5Btg7ra1cfytz3wZv2tH8wWSLFXmAdlUVJjsJGNfWPRX9qtePTQvFxNRizf8rxjCz7MlbJV/YabjnCbMJv/oJbnbp/8CiYS2dVoWhGkMogv0pjcOj51Zw1V0AEDpMvajsrtnHN3u9wLquFtUHklTum4W9TjuwxgVODKbovJDJhsZNS+kLp89ni6FiMednGiMoyyeUOJhzERPBBK+kDvfs5hYPkAv3Y+N6XluArUy/hQNLkl3tmdPZa9VLhSgvfvlKBCXhN8y99ZpOc9at2RblwgRbKNFvu8nE+WYr4cHJyzlyrrxoEagnLdXsBqcPj6YpI020z6iKI9DriNLvV"
`endif