-- gts_system_pll.vhd

-- Generated using ACDS version 25.1 129

library IEEE;
library intel_systemclk_gts_501;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity gts_system_pll is
	port (
		o_pll_lock  : out std_logic;        --  o_pll_lock.o_pll_lock, Lock signal of PLL
		o_syspll_c0 : out std_logic;        -- o_syspll_c0.clk,        Clock output C0
		i_refclk    : in  std_logic := '0'  -- refclk_xcvr.clk,        Input refclock port
	);
end entity gts_system_pll;

architecture rtl of gts_system_pll is
	component gts_system_pll_intel_systemclk_gts_501_ncsqiyy_cmp is
		generic (
			systempll_c0_output_enable_0 : string := "";
			systempll_c1_output_enable_0 : string := "";
			systempll_c2_output_enable_0 : string := "";
			systempll_f_out_c0_hz_0      : string := "";
			systempll_f_out_c1_hz_0      : string := "";
			systempll_f_out_c2_hz_0      : string := "";
			systempll_f_ref_hz_0         : string := "";
			systempll_ethernet_preset_0  : string := "";
			systempll_pcie_preset_0      : string := "";
			systempll_primary_use_0      : string := "";
			silicon_revision             : string := "10nm6awhra";
			device_revision              : string := "10nm6awhra"
		);
		port (
			o_pll_lock     : out std_logic;        -- o_pll_lock
			o_syspll_c0    : out std_logic;        -- clk
			i_refclk       : in  std_logic := 'X'; -- clk
			o_syspll_c1    : out std_logic;        -- clk
			i_refclk_ready : in  std_logic := 'X'  -- data
		);
	end component gts_system_pll_intel_systemclk_gts_501_ncsqiyy_cmp;

	for intel_systemclk_gts_0 : gts_system_pll_intel_systemclk_gts_501_ncsqiyy_cmp
		use entity intel_systemclk_gts_501.gts_system_pll_intel_systemclk_gts_501_ncsqiyy;
begin

	intel_systemclk_gts_0 : component gts_system_pll_intel_systemclk_gts_501_ncsqiyy_cmp
		generic map (
			systempll_c0_output_enable_0 => "ENABLE",
			systempll_c1_output_enable_0 => "ENABLE",
			systempll_c2_output_enable_0 => "ENABLE",
			systempll_f_out_c0_hz_0      => "300000000",
			systempll_f_out_c1_hz_0      => "300000000",
			systempll_f_out_c2_hz_0      => "300000000",
			systempll_f_ref_hz_0         => "100000000",
			systempll_ethernet_preset_0  => "ETHERNET_UNUSED",
			systempll_pcie_preset_0      => "PCIE_FREQ_300",
			systempll_primary_use_0      => "PCIE",
			silicon_revision             => "10nm6awhra",
			device_revision              => "10nm6awhra"
		)
		port map (
			o_pll_lock     => o_pll_lock,  --  o_pll_lock.o_pll_lock
			o_syspll_c0    => o_syspll_c0, -- o_syspll_c0.clk
			i_refclk       => i_refclk,    -- refclk_xcvr.clk
			o_syspll_c1    => open,        -- (terminated)
			i_refclk_ready => '1'          -- (terminated)
		);

end architecture rtl; -- of gts_system_pll
