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module pcie_phy_user_avmm_arb (
    input		phy_avmm_read,
    input		phy_avmm_write,
    input	[23:0]	phy_avmm_address,
    input	[31:0]	phy_avmm_writedata,
    output logic	phy_avmm_readdatavalid,
    output logic [31:0]	phy_avmm_readdata,
    output logic	phy_avmm_waitrequest,
	
    output         	phy0_avmm_read,
    output         	phy0_avmm_write,
    output 	[20:0]  phy0_avmm_address,
    output 	[31:0]  phy0_avmm_writedata,
    input          	phy0_avmm_readdatavalid,
    input  	[31:0]  phy0_avmm_readdata,
    input          	phy0_avmm_waitrequest,
	
    output         	phy1_avmm_read,
    output         	phy1_avmm_write,
    output 	[20:0]  phy1_avmm_address,
    output 	[31:0]  phy1_avmm_writedata,
    input          	phy1_avmm_readdatavalid,
    input  	[31:0]  phy1_avmm_readdata,
    input          	phy1_avmm_waitrequest,
	
    output         	phy2_avmm_read,
    output         	phy2_avmm_write,
    output 	[20:0]  phy2_avmm_address,
    output 	[31:0]  phy2_avmm_writedata,
    input          	phy2_avmm_readdatavalid,
    input  	[31:0]  phy2_avmm_readdata,
    input          	phy2_avmm_waitrequest,
	
    output         	phy3_avmm_read,
    output         	phy3_avmm_write,
    output 	[20:0]  phy3_avmm_address,
    output 	[31:0]  phy3_avmm_writedata,
    input          	phy3_avmm_readdatavalid,
    input  	[31:0]  phy3_avmm_readdata,
    input          	phy3_avmm_waitrequest,

    output         	phy4_avmm_read,
    output         	phy4_avmm_write,
    output 	[20:0]  phy4_avmm_address,
    output 	[31:0]  phy4_avmm_writedata,
    input          	phy4_avmm_readdatavalid,
    input  	[31:0]  phy4_avmm_readdata,
    input          	phy4_avmm_waitrequest,

    output         	phy5_avmm_read,
    output         	phy5_avmm_write,
    output 	[20:0]  phy5_avmm_address,
    output 	[31:0]  phy5_avmm_writedata,
    input          	phy5_avmm_readdatavalid,
    input  	[31:0]  phy5_avmm_readdata,
    input          	phy5_avmm_waitrequest,

    output         	phy6_avmm_read,
    output         	phy6_avmm_write,
    output 	[20:0]  phy6_avmm_address,
    output 	[31:0]  phy6_avmm_writedata,
    input          	phy6_avmm_readdatavalid,
    input  	[31:0]  phy6_avmm_readdata,
    input          	phy6_avmm_waitrequest,

    output         	phy7_avmm_read,
    output         	phy7_avmm_write,
    output 	[20:0]  phy7_avmm_address,
    output 	[31:0]  phy7_avmm_writedata,
    input          	phy7_avmm_readdatavalid,
    input  	[31:0]  phy7_avmm_readdata,
    input          	phy7_avmm_waitrequest
);	

	logic	[2:0]	phyq_sel;

	//3-bit address decoder
	assign phyq_sel = phy_avmm_address[23:21];

	//PHY0
	assign phy0_avmm_read		= (phyq_sel == 3'd0) ? phy_avmm_read : 0;
	assign phy0_avmm_write		= (phyq_sel == 3'd0) ? phy_avmm_write : 0;
	assign phy0_avmm_address	= (phyq_sel == 3'd0) ? phy_avmm_address[20:0] : 0;
	assign phy0_avmm_writedata	= (phyq_sel == 3'd0) ? phy_avmm_writedata : 0;

	//PHY1
	assign phy1_avmm_read		= (phyq_sel == 3'd1) ? phy_avmm_read : 0;
	assign phy1_avmm_write		= (phyq_sel == 3'd1) ? phy_avmm_write : 0;
	assign phy1_avmm_address	= (phyq_sel == 3'd1) ? phy_avmm_address[20:0] : 0;
	assign phy1_avmm_writedata	= (phyq_sel == 3'd1) ? phy_avmm_writedata : 0;

	//PHY2
	assign phy2_avmm_read		= (phyq_sel == 3'd2) ? phy_avmm_read : 0;
	assign phy2_avmm_write		= (phyq_sel == 3'd2) ? phy_avmm_write : 0;
	assign phy2_avmm_address	= (phyq_sel == 3'd2) ? phy_avmm_address[20:0] : 0;
	assign phy2_avmm_writedata	= (phyq_sel == 3'd2) ? phy_avmm_writedata : 0;

	//PHY3
	assign phy3_avmm_read		= (phyq_sel == 3'd3) ? phy_avmm_read : 0;
	assign phy3_avmm_write		= (phyq_sel == 3'd3) ? phy_avmm_write : 0;
	assign phy3_avmm_address	= (phyq_sel == 3'd3) ? phy_avmm_address[20:0] : 0;
	assign phy3_avmm_writedata	= (phyq_sel == 3'd3) ? phy_avmm_writedata : 0;

	//PHY4
	assign phy4_avmm_read		= (phyq_sel == 3'd4) ? phy_avmm_read : 0;
	assign phy4_avmm_write		= (phyq_sel == 3'd4) ? phy_avmm_write : 0;
	assign phy4_avmm_address	= (phyq_sel == 3'd4) ? phy_avmm_address[20:0] : 0;
	assign phy4_avmm_writedata	= (phyq_sel == 3'd4) ? phy_avmm_writedata : 0;

	//PHY5
	assign phy5_avmm_read		= (phyq_sel == 3'd5) ? phy_avmm_read : 0;
	assign phy5_avmm_write		= (phyq_sel == 3'd5) ? phy_avmm_write : 0;
	assign phy5_avmm_address	= (phyq_sel == 3'd5) ? phy_avmm_address[20:0] : 0;
	assign phy5_avmm_writedata	= (phyq_sel == 3'd5) ? phy_avmm_writedata : 0;

	//PHY6
	assign phy6_avmm_read		= (phyq_sel == 3'd6) ? phy_avmm_read : 0;
	assign phy6_avmm_write		= (phyq_sel == 3'd6) ? phy_avmm_write : 0;
	assign phy6_avmm_address	= (phyq_sel == 3'd6) ? phy_avmm_address[20:0] : 0;
	assign phy6_avmm_writedata	= (phyq_sel == 3'd6) ? phy_avmm_writedata : 0;

	//PHY7
	assign phy7_avmm_read		= (phyq_sel == 3'd7) ? phy_avmm_read : 0;
	assign phy7_avmm_write		= (phyq_sel == 3'd7) ? phy_avmm_write : 0;
	assign phy7_avmm_address	= (phyq_sel == 3'd7) ? phy_avmm_address[20:0] : 0;
	assign phy7_avmm_writedata	= (phyq_sel == 3'd7) ? phy_avmm_writedata : 0;


	assign phy_avmm_readdatavalid = (phyq_sel == 3'd0) ? phy0_avmm_readdatavalid : (phyq_sel == 3'd1) ? phy1_avmm_readdatavalid : (phyq_sel == 3'd2) ? phy2_avmm_readdatavalid : (phyq_sel == 3'd3) ? phy3_avmm_readdatavalid : (phyq_sel == 3'd4) ? phy4_avmm_readdatavalid : (phyq_sel == 3'd5) ? phy5_avmm_readdatavalid : (phyq_sel == 3'd6) ? phy6_avmm_readdatavalid : (phyq_sel == 3'd7) ? phy7_avmm_readdatavalid : phy0_avmm_readdatavalid ;
	assign phy_avmm_readdata      = (phyq_sel == 3'd0) ? phy0_avmm_readdata : (phyq_sel == 3'd1) ? phy1_avmm_readdata : (phyq_sel == 3'd2) ? phy2_avmm_readdata : (phyq_sel == 3'd3) ? phy3_avmm_readdata : (phyq_sel == 3'd4) ? phy4_avmm_readdata : (phyq_sel == 3'd5) ? phy5_avmm_readdata : (phyq_sel == 3'd6) ? phy6_avmm_readdata : (phyq_sel == 3'd7) ? phy7_avmm_readdata : phy0_avmm_readdata ;
	assign phy_avmm_waitrequest   = (phyq_sel == 3'd0) ? phy0_avmm_waitrequest : (phyq_sel == 3'd1) ? phy1_avmm_waitrequest : (phyq_sel == 3'd2) ? phy2_avmm_waitrequest : (phyq_sel == 3'd3) ? phy3_avmm_waitrequest : (phyq_sel == 3'd4) ? phy4_avmm_waitrequest : (phyq_sel == 3'd5) ? phy5_avmm_waitrequest : (phyq_sel == 3'd6) ? phy6_avmm_waitrequest : (phyq_sel == 3'd7) ? phy7_avmm_waitrequest : phy0_avmm_waitrequest ;
	
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "PNVV7/bs9iBHIRlA5ZBsyN/GPZ0TXi6qn2Dh2M7pAeu7gJ2ZBA7h3JGkvjXkuC5UIXo/z5gQmp1UZ7sTAaTT/jY49W2SxnQK1Yi3m9AqA7DQvdVNQSIP0StiA6cd/Bmb1xOyX01r0Q1kSbh1Xg00173NRrSBh6I2laKRBqIVNUuwBG6+CnWpVjqQa+TAR5sCjTNP+I8jQLtXq7doP9+lP7YXqXhRmwId5c9JhVEr4VnSKus/EHwLzMumY04D/gLtTBNdh3axzlK3g0bMMeSzAh40EmQsYBGWGk+QvV0bBE4VFroiiLxOXFdESnAHmBcAkUJAVpS0FG786EaqfNiJoNELJ3esgk/EvoRjeUTkQgIbfhph0OaCrxkhaBaXAKRF1I/9+NVjPlrLP7gvGaw+N8U8g7us0BE4exJrK8NQfwd5AEAk9Rujah7RUAXMm7E+HzqpoEiXKWbrnZa5pNIHZe987tmODzkyN2kiUnRcSbLIE8YduAvDtU77UCTglxoxUI127pZOwG40t+QcuUmDaAWtTh/KiISkZIwBuhhKsaHd864Oivi3woQ4oToOboXcTBFd352Pee+nc5shW5L2zPj5rUDrti2dZvKbnd0D4jS2QnuChHSZ5U8WagYgIoyReJgNOTcGsQHvnY1Nrh+oQFhI25mDhwWXI5cTHN1I7p+kqHlLOsFMmeIJTUQ+d8Qa6GRz1wUpJ12s986e1GqBYC8MCjhOa1Tw7D2FwRsJ8sFkWbYTtaE6zWSFVFcJCvF+pKurqcl2XyKAiBmvNRU0OpQJZnBeyz08kTW234q8RH0/CJwws6MX8sn0xyjD+DvrcFu3sIGslwQkuln2bTB2yjFjU0KbVZ1B+EhCrsjIlG19o3nXITInRGlyp0vnnkEDyfMItEHHcFr3mDM1AfRK73qae49E8lP2DA+tj6X4BFjWTVbrggQSvD0gig+smln2jebbqJuiqyTFTDgQlDdYhTIsk8Sgw7w0Buv/yPgZCV2CLp8YVbJ9bKNW9htlRJdN"
`endif