-- iopll_100mhz.vhd

-- Generated using ACDS version 25.1 129

library IEEE;
library altera_iopll_2000;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity iopll_100mhz is
	port (
		refclk   : in  std_logic := '0'; --  refclk.clk,    The reference clock source that drives the I/O PLL.
		locked   : out std_logic;        --  locked.export, The IOPLL IP core drives this port high when the PLL acquires lock. The port remains high as long as the I/O PLL is locked. The I/O PLL asserts the locked port when the phases and frequencies of the reference clock and feedback clock are the same or within the lock circuit tolerance. When the difference between the two clock signals exceeds the lock circuit tolerance, the I/O PLL loses lock.
		rst      : in  std_logic := '0'; --   reset.reset,  The asynchronous reset port for the output clocks. Drive this port high to reset all output clocks to the value of 0.
		outclk_0 : out std_logic         -- outclk0.clk,    Output clock Channel 0 from I/O PLL.
	);
end entity iopll_100mhz;

architecture rtl of iopll_100mhz is
	component iopll_100mhz_altera_iopll_2000_ifhv6lq_cmp is
		port (
			refclk   : in  std_logic := 'X'; -- clk
			locked   : out std_logic;        -- export
			rst      : in  std_logic := 'X'; -- reset
			outclk_0 : out std_logic         -- clk
		);
	end component iopll_100mhz_altera_iopll_2000_ifhv6lq_cmp;

	for iopll_0 : iopll_100mhz_altera_iopll_2000_ifhv6lq_cmp
		use entity altera_iopll_2000.iopll_100mhz_altera_iopll_2000_ifhv6lq;
begin

	iopll_0 : component iopll_100mhz_altera_iopll_2000_ifhv6lq_cmp
		port map (
			refclk   => refclk,   --  refclk.clk
			locked   => locked,   --  locked.export
			rst      => rst,      --   reset.reset
			outclk_0 => outclk_0  -- outclk0.clk
		);

end architecture rtl; -- of iopll_100mhz
