-- gts_axi_streaming_intel_pcie_gts_pcie_hal_top_800_a4pwunq.vhd

-- Generated using ACDS version 25.1 129

library IEEE;
library pcie_hal_top_2100;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity gts_axi_streaming_intel_pcie_gts_pcie_hal_top_800_a4pwunq is
	generic (
		ch0_pcs_l_tx_en_atom                                : string                        := "FALSE";
		ch0_pcs_l_rx_en_atom                                : string                        := "FALSE";
		ch0_fec_loopback_mode_atom                          : string                        := "CH0_LOOPBACK_MODE_DISABLE";
		ch0_fec_dyn_tx_mux_atom                             : string                        := "CH0_DYN_TX_MUX_UNUSED";
		ch0_fec_error_atom                                  : string                        := "FALSE";
		ch0_fec_rx_en_atom                                  : string                        := "FALSE";
		ch0_fec_tx_en_atom                                  : string                        := "FALSE";
		ch0_fec_mode_atom                                   : string                        := "CH0_FEC_MODE_DISABLED";
		ch1_pcs_l_tx_en_atom                                : string                        := "FALSE";
		ch1_pcs_l_rx_en_atom                                : string                        := "FALSE";
		ch1_fec_loopback_mode_atom                          : string                        := "CH1_LOOPBACK_MODE_DISABLE";
		ch1_fec_dyn_tx_mux_atom                             : string                        := "CH1_DYN_TX_MUX_UNUSED";
		ch1_fec_error_atom                                  : string                        := "FALSE";
		ch1_fec_rx_en_atom                                  : string                        := "FALSE";
		ch1_fec_tx_en_atom                                  : string                        := "FALSE";
		ch1_fec_mode_atom                                   : string                        := "CH1_FEC_MODE_DISABLED";
		ch2_pcs_l_tx_en_atom                                : string                        := "FALSE";
		ch2_pcs_l_rx_en_atom                                : string                        := "FALSE";
		ch2_fec_loopback_mode_atom                          : string                        := "CH2_LOOPBACK_MODE_DISABLE";
		ch2_fec_dyn_tx_mux_atom                             : string                        := "CH2_DYN_TX_MUX_UNUSED";
		ch2_fec_error_atom                                  : string                        := "FALSE";
		ch2_fec_rx_en_atom                                  : string                        := "FALSE";
		ch2_fec_tx_en_atom                                  : string                        := "FALSE";
		ch2_fec_mode_atom                                   : string                        := "CH2_FEC_MODE_DISABLED";
		ch3_pcs_l_tx_en_atom                                : string                        := "FALSE";
		ch3_pcs_l_rx_en_atom                                : string                        := "FALSE";
		ch3_fec_loopback_mode_atom                          : string                        := "CH3_LOOPBACK_MODE_DISABLE";
		ch3_fec_dyn_tx_mux_atom                             : string                        := "CH3_DYN_TX_MUX_UNUSED";
		ch3_fec_error_atom                                  : string                        := "FALSE";
		ch3_fec_rx_en_atom                                  : string                        := "FALSE";
		ch3_fec_tx_en_atom                                  : string                        := "FALSE";
		ch3_fec_mode_atom                                   : string                        := "CH3_FEC_MODE_DISABLED";
		ch0_xcvr_rx_prbs_monitor_en_atom                    : string                        := "CH0_RX_PRBS_MONITOR_EN_DISABLE";
		ch1_xcvr_rx_prbs_monitor_en_atom                    : string                        := "CH1_RX_PRBS_MONITOR_EN_ENABLE";
		ch2_xcvr_rx_prbs_monitor_en_atom                    : string                        := "CH2_RX_PRBS_MONITOR_EN_ENABLE";
		ch3_xcvr_rx_prbs_monitor_en_atom                    : string                        := "CH3_RX_PRBS_MONITOR_EN_ENABLE";
		ch0_tx_prbs_gen_en_atom                             : string                        := "CH0_TX_PRBS_GEN_EN_DISABLE";
		ch1_tx_prbs_gen_en_atom                             : string                        := "CH1_TX_PRBS_GEN_EN_DISABLE";
		ch2_tx_prbs_gen_en_atom                             : string                        := "CH2_TX_PRBS_GEN_EN_DISABLE";
		ch3_tx_prbs_gen_en_atom                             : string                        := "CH3_TX_PRBS_GEN_EN_DISABLE";
		ch0_rx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH0_RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD";
		ch0_rx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH0_RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD";
		ch0_tx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH0_TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK";
		ch0_tx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH0_TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK";
		ch1_rx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH1_RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD";
		ch1_rx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH1_RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD";
		ch1_tx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH1_TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK";
		ch1_tx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH1_TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK";
		ch2_rx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH2_RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD";
		ch2_rx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH2_RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD";
		ch2_tx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH2_TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK";
		ch2_tx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH2_TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK";
		ch3_rx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH3_RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD";
		ch3_rx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH3_RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD";
		ch3_tx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH3_TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK";
		ch3_tx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH3_TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK";
		ch0_pcie_mode_atom                                  : string                        := "CH0_PCIE_MODE_GEN3";
		ch1_pcie_mode_atom                                  : string                        := "CH1_PCIE_MODE_GEN3";
		ch2_pcie_mode_atom                                  : string                        := "CH2_PCIE_MODE_GEN3";
		ch3_pcie_mode_atom                                  : string                        := "CH3_PCIE_MODE_GEN3";
		ch0_xcvr_rx_protocol_hint_atom                      : string                        := "CH0_RX_PROTOCOL_HINT_DISABLED";
		ch1_xcvr_rx_protocol_hint_atom                      : string                        := "CH1_RX_PROTOCOL_HINT_DISABLED";
		ch2_xcvr_rx_protocol_hint_atom                      : string                        := "CH2_RX_PROTOCOL_HINT_DISABLED";
		ch3_xcvr_rx_protocol_hint_atom                      : string                        := "CH3_RX_PROTOCOL_HINT_DISABLED";
		ch0_clkrx_refclk_cssm_fw_control_atom               : string                        := "CH0_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE";
		ch1_clkrx_refclk_cssm_fw_control_atom               : string                        := "CH1_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE";
		ch2_clkrx_refclk_cssm_fw_control_atom               : string                        := "CH2_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE";
		ch3_clkrx_refclk_cssm_fw_control_atom               : string                        := "CH3_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE";
		ch0_clkrx_refclk_sector_specifies_refclk_ready_atom : string                        := "CH0_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
		ch1_clkrx_refclk_sector_specifies_refclk_ready_atom : string                        := "CH1_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
		ch2_clkrx_refclk_sector_specifies_refclk_ready_atom : string                        := "CH2_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
		ch3_clkrx_refclk_sector_specifies_refclk_ready_atom : string                        := "CH3_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
		ch0_local_refclk_cssm_fw_control_atom               : string                        := "CH0_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE";
		ch1_local_refclk_cssm_fw_control_atom               : string                        := "CH1_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE";
		ch2_local_refclk_cssm_fw_control_atom               : string                        := "CH2_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE";
		ch3_local_refclk_cssm_fw_control_atom               : string                        := "CH3_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE";
		ch0_local_refclk_sector_specifies_refclk_ready_atom : string                        := "CH0_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
		ch1_local_refclk_sector_specifies_refclk_ready_atom : string                        := "CH1_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
		ch2_local_refclk_sector_specifies_refclk_ready_atom : string                        := "CH2_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
		ch3_local_refclk_sector_specifies_refclk_ready_atom : string                        := "CH3_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
		ch0_tx_bonding_category_atom                        : string                        := "CH0_TX_BONDING_CATEGORY_BONDING_LEADER";
		ch1_tx_bonding_category_atom                        : string                        := "CH1_TX_BONDING_CATEGORY_BONDING_FOLLOWER";
		ch2_tx_bonding_category_atom                        : string                        := "CH2_TX_BONDING_CATEGORY_BONDING_FOLLOWER";
		ch3_tx_bonding_category_atom                        : string                        := "CH3_TX_BONDING_CATEGORY_BONDING_FOLLOWER";
		hal_num_of_lanes_hwtcl                              : integer                       := 4;
		is_sm4_sm7_revA                                     : integer                       := 1;
		ch0_duplex_mode_atom                                : string                        := "CH0_DUPLEX_MODE_DUPLEX";
		ch0_fec_spec_atom                                   : string                        := "CH0_FEC_SPEC_DISABLED";
		ch0_fracture_atom                                   : string                        := "CH0_FRACTURE_UNUSED";
		ch0_dr_enabled_atom                                 : string                        := "CH0_DR_ENABLED_DR_DISABLED";
		ch0_sup_mode_atom                                   : string                        := "CH0_SUP_MODE_USER_MODE";
		ch0_sim_mode_atom                                   : string                        := "CH0_SIM_MODE_DISABLE";
		ch1_duplex_mode_atom                                : string                        := "CH1_DUPLEX_MODE_DUPLEX";
		ch1_fec_spec_atom                                   : string                        := "CH1_FEC_SPEC_DISABLED";
		ch1_fracture_atom                                   : string                        := "CH1_FRACTURE_UNUSED";
		ch1_dr_enabled_atom                                 : string                        := "CH1_DR_ENABLED_DR_DISABLED";
		ch1_sup_mode_atom                                   : string                        := "CH1_SUP_MODE_USER_MODE";
		ch1_sim_mode_atom                                   : string                        := "CH1_SIM_MODE_DISABLE";
		ch2_duplex_mode_atom                                : string                        := "CH2_DUPLEX_MODE_DUPLEX";
		ch2_fec_spec_atom                                   : string                        := "CH2_FEC_SPEC_DISABLED";
		ch2_fracture_atom                                   : string                        := "CH2_FRACTURE_UNUSED";
		ch2_dr_enabled_atom                                 : string                        := "CH2_DR_ENABLED_DR_DISABLED";
		ch2_sup_mode_atom                                   : string                        := "CH2_SUP_MODE_USER_MODE";
		ch2_sim_mode_atom                                   : string                        := "CH2_SIM_MODE_DISABLE";
		ch3_duplex_mode_atom                                : string                        := "CH3_DUPLEX_MODE_DUPLEX";
		ch3_fec_spec_atom                                   : string                        := "CH3_FEC_SPEC_DISABLED";
		ch3_fracture_atom                                   : string                        := "CH3_FRACTURE_UNUSED";
		ch3_dr_enabled_atom                                 : string                        := "CH3_DR_ENABLED_DR_DISABLED";
		ch3_sup_mode_atom                                   : string                        := "CH3_SUP_MODE_USER_MODE";
		ch3_sim_mode_atom                                   : string                        := "CH3_SIM_MODE_DISABLE";
		ch0_xcvr_tx_preloaded_hardware_configs_atom         : string                        := "CH0_TX_PRELOADED_HARDWARE_CONFIGS_PCIE";
		ch0_xcvr_rx_preloaded_hardware_configs_atom         : string                        := "CH0_RX_PRELOADED_HARDWARE_CONFIGS_PCIE";
		ch0_lc_postdiv_sel_atom                             : string                        := "CH0_LC_POSTDIV_SEL_SYNTH2";
		ch0_sequencer_reg_en_atom                           : string                        := "CH0_SEQUENCER_REG_EN_ENABLE";
		ch0_rst_mux_static_sel_atom                         : string                        := "CH0_RST_MUX_STATIC_SEL_HRC";
		ch0_xcvr_tx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0000";
		ch0_xcvr_rx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0000";
		ch0_xcvr_tx_user_clk_only_mode_atom                 : string                        := "CH0_TX_USER_CLK_ONLY_MODE_DISABLE";
		ch0_xcvr_tx_width_atom                              : string                        := "CH0_TX_WIDTH_X16";
		ch0_xcvr_rx_width_atom                              : string                        := "CH0_RX_WIDTH_X16";
		ch0_phy_loopback_mode_atom                          : string                        := "CH0_LOOPBACK_MODE_DISABLED";
		ch0_flux_mode_atom                                  : string                        := "CH0_FLUX_MODE_FLUX_MODE_BYPASS";
		ch0_flux_mode_hw_atom                               : string                        := "CH0_FLUX_MODE_FLUX_MODE_BYPASS";
		ch0_tx_sim_mode_atom                                : string                        := "CH0_TX_SIM_MODE_DISABLE";
		ch0_rx_sim_mode_atom                                : string                        := "CH0_RX_SIM_MODE_DISABLE";
		ch0_tx_dl_enable_atom                               : string                        := "CH0_TX_DL_ENABLE_DISABLE";
		ch0_rx_dl_enable_atom                               : string                        := "CH0_RX_DL_ENABLE_DISABLE";
		ch0_rx_fec_type_used_atom                           : string                        := "CH0_RX_FEC_TYPE_USED_NONE";
		ch1_xcvr_tx_preloaded_hardware_configs_atom         : string                        := "CH1_TX_PRELOADED_HARDWARE_CONFIGS_PCIE";
		ch1_xcvr_rx_preloaded_hardware_configs_atom         : string                        := "CH1_RX_PRELOADED_HARDWARE_CONFIGS_PCIE";
		ch1_lc_postdiv_sel_atom                             : string                        := "CH1_LC_POSTDIV_SEL_SYNTH2";
		ch1_sequencer_reg_en_atom                           : string                        := "CH1_SEQUENCER_REG_EN_DISABLE";
		ch1_rst_mux_static_sel_atom                         : string                        := "CH1_RST_MUX_STATIC_SEL_HRC";
		ch1_xcvr_tx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0000";
		ch1_xcvr_rx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0001";
		ch1_xcvr_tx_user_clk_only_mode_atom                 : string                        := "CH1_TX_USER_CLK_ONLY_MODE_DISABLE";
		ch1_xcvr_tx_width_atom                              : string                        := "CH1_TX_WIDTH_X16";
		ch1_xcvr_rx_width_atom                              : string                        := "CH1_RX_WIDTH_X16";
		ch1_phy_loopback_mode_atom                          : string                        := "CH1_LOOPBACK_MODE_DISABLED";
		ch1_flux_mode_atom                                  : string                        := "CH1_FLUX_MODE_FLUX_MODE_BYPASS";
		ch1_flux_mode_hw_atom                               : string                        := "CH1_FLUX_MODE_FLUX_MODE_BYPASS";
		ch1_tx_sim_mode_atom                                : string                        := "CH1_TX_SIM_MODE_DISABLE";
		ch1_rx_sim_mode_atom                                : string                        := "CH1_RX_SIM_MODE_DISABLE";
		ch1_tx_dl_enable_atom                               : string                        := "CH1_TX_DL_ENABLE_DISABLE";
		ch1_rx_dl_enable_atom                               : string                        := "CH1_RX_DL_ENABLE_DISABLE";
		ch1_rx_fec_type_used_atom                           : string                        := "CH1_RX_FEC_TYPE_USED_NONE";
		ch2_xcvr_tx_preloaded_hardware_configs_atom         : string                        := "CH2_TX_PRELOADED_HARDWARE_CONFIGS_PCIE";
		ch2_xcvr_rx_preloaded_hardware_configs_atom         : string                        := "CH2_RX_PRELOADED_HARDWARE_CONFIGS_PCIE";
		ch2_lc_postdiv_sel_atom                             : string                        := "CH2_LC_POSTDIV_SEL_SYNTH2";
		ch2_sequencer_reg_en_atom                           : string                        := "CH2_SEQUENCER_REG_EN_DISABLE";
		ch2_rst_mux_static_sel_atom                         : string                        := "CH2_RST_MUX_STATIC_SEL_HRC";
		ch2_xcvr_tx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0000";
		ch2_xcvr_rx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0011";
		ch2_xcvr_tx_user_clk_only_mode_atom                 : string                        := "CH2_TX_USER_CLK_ONLY_MODE_DISABLE";
		ch2_xcvr_tx_width_atom                              : string                        := "CH2_TX_WIDTH_X16";
		ch2_xcvr_rx_width_atom                              : string                        := "CH2_RX_WIDTH_X16";
		ch2_phy_loopback_mode_atom                          : string                        := "CH2_LOOPBACK_MODE_DISABLED";
		ch2_flux_mode_atom                                  : string                        := "CH2_FLUX_MODE_FLUX_MODE_BYPASS";
		ch2_flux_mode_hw_atom                               : string                        := "CH2_FLUX_MODE_FLUX_MODE_BYPASS";
		ch2_tx_sim_mode_atom                                : string                        := "CH2_TX_SIM_MODE_DISABLE";
		ch2_rx_sim_mode_atom                                : string                        := "CH2_RX_SIM_MODE_DISABLE";
		ch2_tx_dl_enable_atom                               : string                        := "CH2_TX_DL_ENABLE_DISABLE";
		ch2_rx_dl_enable_atom                               : string                        := "CH2_RX_DL_ENABLE_DISABLE";
		ch2_rx_fec_type_used_atom                           : string                        := "CH2_RX_FEC_TYPE_USED_NONE";
		ch3_xcvr_tx_preloaded_hardware_configs_atom         : string                        := "CH3_TX_PRELOADED_HARDWARE_CONFIGS_PCIE";
		ch3_xcvr_rx_preloaded_hardware_configs_atom         : string                        := "CH3_RX_PRELOADED_HARDWARE_CONFIGS_PCIE";
		ch3_lc_postdiv_sel_atom                             : string                        := "CH3_LC_POSTDIV_SEL_SYNTH2";
		ch3_sequencer_reg_en_atom                           : string                        := "CH3_SEQUENCER_REG_EN_ENABLE";
		ch3_rst_mux_static_sel_atom                         : string                        := "CH3_RST_MUX_STATIC_SEL_HRC";
		ch3_xcvr_tx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0000";
		ch3_xcvr_rx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0111";
		ch3_xcvr_tx_user_clk_only_mode_atom                 : string                        := "CH3_TX_USER_CLK_ONLY_MODE_DISABLE";
		ch3_xcvr_tx_width_atom                              : string                        := "CH3_TX_WIDTH_X16";
		ch3_xcvr_rx_width_atom                              : string                        := "CH3_RX_WIDTH_X16";
		ch3_phy_loopback_mode_atom                          : string                        := "CH3_LOOPBACK_MODE_DISABLED";
		ch3_flux_mode_atom                                  : string                        := "CH3_FLUX_MODE_FLUX_MODE_BYPASS";
		ch3_flux_mode_hw_atom                               : string                        := "CH3_FLUX_MODE_FLUX_MODE_BYPASS";
		ch3_tx_sim_mode_atom                                : string                        := "CH3_TX_SIM_MODE_DISABLE";
		ch3_rx_sim_mode_atom                                : string                        := "CH3_RX_SIM_MODE_DISABLE";
		ch3_tx_dl_enable_atom                               : string                        := "CH3_TX_DL_ENABLE_DISABLE";
		ch3_rx_dl_enable_atom                               : string                        := "CH3_RX_DL_ENABLE_DISABLE";
		ch3_rx_fec_type_used_atom                           : string                        := "CH3_RX_FEC_TYPE_USED_NONE";
		ch0_tx_pll_l_counter_atom                           : std_logic_vector(5 downto 0)  := "000010";
		ch0_cdr_l_counter_atom                              : std_logic_vector(5 downto 0)  := "000010";
		ch0_tx_pll_refclk_select_atom                       : string                        := "CH0_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0";
		ch0_cdr_refclk_select_atom                          : string                        := "CH0_CDR_REFCLK_SELECT_GLOBAL_REFCLK0";
		ch1_tx_pll_l_counter_atom                           : std_logic_vector(5 downto 0)  := "000010";
		ch1_cdr_l_counter_atom                              : std_logic_vector(5 downto 0)  := "000010";
		ch1_tx_pll_refclk_select_atom                       : string                        := "CH1_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0";
		ch1_cdr_refclk_select_atom                          : string                        := "CH1_CDR_REFCLK_SELECT_GLOBAL_REFCLK0";
		ch2_tx_pll_l_counter_atom                           : std_logic_vector(5 downto 0)  := "000010";
		ch2_cdr_l_counter_atom                              : std_logic_vector(5 downto 0)  := "000010";
		ch2_tx_pll_refclk_select_atom                       : string                        := "CH2_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0";
		ch2_cdr_refclk_select_atom                          : string                        := "CH2_CDR_REFCLK_SELECT_GLOBAL_REFCLK0";
		ch3_tx_pll_l_counter_atom                           : std_logic_vector(5 downto 0)  := "000010";
		ch3_cdr_l_counter_atom                              : std_logic_vector(5 downto 0)  := "000010";
		ch3_tx_pll_refclk_select_atom                       : string                        := "CH3_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0";
		ch3_cdr_refclk_select_atom                          : string                        := "CH3_CDR_REFCLK_SELECT_GLOBAL_REFCLK0";
		ch0_rx_dl_rx_lat_bit_for_async_atom                 : std_logic_vector(17 downto 0) := "010100000100010011";
		ch0_rx_dl_rxbit_cntr_pma_atom                       : string                        := "CH0_RX_DL_RXBIT_CNTR_PMA_DISABLE";
		ch0_rx_dl_rxbit_rollover_atom                       : std_logic_vector(17 downto 0) := "111110100100001111";
		ch1_rx_dl_rx_lat_bit_for_async_atom                 : std_logic_vector(17 downto 0) := "111110100110100101";
		ch1_rx_dl_rxbit_cntr_pma_atom                       : string                        := "CH1_RX_DL_RXBIT_CNTR_PMA_DISABLE";
		ch1_rx_dl_rxbit_rollover_atom                       : std_logic_vector(17 downto 0) := "001001111001000101";
		ch2_rx_dl_rx_lat_bit_for_async_atom                 : std_logic_vector(17 downto 0) := "111010100000111101";
		ch2_rx_dl_rxbit_cntr_pma_atom                       : string                        := "CH2_RX_DL_RXBIT_CNTR_PMA_DISABLE";
		ch2_rx_dl_rxbit_rollover_atom                       : std_logic_vector(17 downto 0) := "111000111110011110";
		ch3_rx_dl_rx_lat_bit_for_async_atom                 : std_logic_vector(17 downto 0) := "100000100111100001";
		ch3_rx_dl_rxbit_cntr_pma_atom                       : string                        := "CH3_RX_DL_RXBIT_CNTR_PMA_DISABLE";
		ch3_rx_dl_rxbit_rollover_atom                       : std_logic_vector(17 downto 0) := "001101111001101011";
		ch0_tx_bond_size_atom                               : string                        := "CH0_TX_BOND_SIZE_X4";
		ch1_tx_bond_size_atom                               : string                        := "CH1_TX_BOND_SIZE_X4";
		ch2_tx_bond_size_atom                               : string                        := "CH2_TX_BOND_SIZE_X4";
		ch3_tx_bond_size_atom                               : string                        := "CH3_TX_BOND_SIZE_X4";
		ch0_rx_invert_pin_atom                              : string                        := "CH0_RX_INVERT_PIN_DISABLE";
		ch1_rx_invert_pin_atom                              : string                        := "CH1_RX_INVERT_PIN_DISABLE";
		ch2_rx_invert_pin_atom                              : string                        := "CH2_RX_INVERT_PIN_DISABLE";
		ch3_rx_invert_pin_atom                              : string                        := "CH3_RX_INVERT_PIN_DISABLE";
		ch0_tx_invert_pin_atom                              : string                        := "CH0_TX_INVERT_PIN_DISABLE";
		ch1_tx_invert_pin_atom                              : string                        := "CH1_TX_INVERT_PIN_DISABLE";
		ch2_tx_invert_pin_atom                              : string                        := "CH2_TX_INVERT_PIN_DISABLE";
		ch3_tx_invert_pin_atom                              : string                        := "CH3_TX_INVERT_PIN_DISABLE";
		ch0_vsr_mode_atom                                   : string                        := "CH0_VSR_MODE_DISABLED";
		ch1_vsr_mode_atom                                   : string                        := "CH1_VSR_MODE_DISABLED";
		ch2_vsr_mode_atom                                   : string                        := "CH2_VSR_MODE_DISABLED";
		ch3_vsr_mode_atom                                   : string                        := "CH3_VSR_MODE_DISABLED";
		pcie_parity_bypass                                  : string                        := "true";
		rxbuf_limit_bypass                                  : integer                       := 7;
		maxpayload_size                                     : string                        := "MAXPAYLOAD_SIZE_MAX_PAYLOAD_512";
		pldclk_rate                                         : string                        := "PLDCLK_RATE_FAST";
		port_type                                           : string                        := "PORT_TYPE_RP";
		sris_enable                                         : string                        := "SRIS_ENABLE_DISABLED";
		link_num                                            : string                        := "SRIS_ENABLE_DISABLED";
		sris_mode                                           : string                        := "false";
		sim_mode                                            : string                        := "SIM_MODE_DISABLE_VSIM_MODE";
		sup_mode                                            : string                        := "SUP_MODE_USER_MODE";
		cvp_enable                                          : string                        := "CVP_ENABLE_DISABLED";
		cii_monitor_en                                      : string                        := "CII_MONITOR_EN_DISABLE";
		pclk_clk_hz                                         : std_logic_vector(31 downto 0) := "00011101110011010110010100000000";
		pf0_cap_link_surprise_down_err_cap                  : string                        := "PF0_CAP_LINK_SURPRISE_DOWN_ERR_CAP_DISABLE";
		sys_clk_hz                                          : std_logic_vector(31 downto 0) := "00010001111000011010001100000000";
		link_rate                                           : string                        := "LINK_RATE_GEN3";
		link_width                                          : string                        := "LINK_WIDTH_X4";
		num_of_lanes                                        : string                        := "NUM_OF_LANES_NUM_4";
		pf0_dsp_16g_tx_preset0                              : integer                       := 7;
		pf0_dsp_16g_tx_preset1                              : integer                       := 7;
		pf0_dsp_16g_tx_preset2                              : integer                       := 7;
		pf0_dsp_16g_tx_preset3                              : integer                       := 7;
		pf0_dsp_16g_tx_preset4                              : integer                       := 0;
		pf0_dsp_16g_tx_preset5                              : integer                       := 0;
		pf0_dsp_16g_tx_preset6                              : integer                       := 0;
		pf0_dsp_16g_tx_preset7                              : integer                       := 0;
		pf0_dsp_16g_tx_preset8                              : integer                       := 0;
		pf0_dsp_16g_tx_preset9                              : integer                       := 0;
		pf0_dsp_16g_tx_preset10                             : integer                       := 0;
		pf0_dsp_16g_tx_preset11                             : integer                       := 0;
		pf0_dsp_16g_tx_preset12                             : integer                       := 0;
		pf0_dsp_16g_tx_preset13                             : integer                       := 0;
		pf0_dsp_16g_tx_preset14                             : integer                       := 0;
		pf0_dsp_16g_tx_preset15                             : integer                       := 0;
		pf0_dsp_tx_preset0                                  : integer                       := 9;
		pf0_dsp_tx_preset1                                  : integer                       := 9;
		pf0_dsp_tx_preset2                                  : integer                       := 9;
		pf0_dsp_tx_preset3                                  : integer                       := 9;
		pf0_dsp_tx_preset4                                  : integer                       := 0;
		pf0_dsp_tx_preset5                                  : integer                       := 0;
		pf0_dsp_tx_preset6                                  : integer                       := 0;
		pf0_dsp_tx_preset7                                  : integer                       := 0;
		pf0_dsp_tx_preset8                                  : integer                       := 0;
		pf0_dsp_tx_preset9                                  : integer                       := 0;
		pf0_dsp_tx_preset10                                 : integer                       := 0;
		pf0_dsp_tx_preset11                                 : integer                       := 0;
		pf0_dsp_tx_preset12                                 : integer                       := 0;
		pf0_dsp_tx_preset13                                 : integer                       := 0;
		pf0_dsp_tx_preset14                                 : integer                       := 0;
		pf0_dsp_tx_preset15                                 : integer                       := 0;
		pf0_usp_16g_tx_preset0                              : integer                       := 7;
		pf0_usp_16g_tx_preset1                              : integer                       := 7;
		pf0_usp_16g_tx_preset2                              : integer                       := 7;
		pf0_usp_16g_tx_preset3                              : integer                       := 7;
		pf0_usp_16g_tx_preset4                              : integer                       := 0;
		pf0_usp_16g_tx_preset5                              : integer                       := 0;
		pf0_usp_16g_tx_preset6                              : integer                       := 0;
		pf0_usp_16g_tx_preset7                              : integer                       := 0;
		pf0_usp_16g_tx_preset8                              : integer                       := 0;
		pf0_usp_16g_tx_preset9                              : integer                       := 0;
		pf0_usp_16g_tx_preset10                             : integer                       := 0;
		pf0_usp_16g_tx_preset11                             : integer                       := 0;
		pf0_usp_16g_tx_preset12                             : integer                       := 0;
		pf0_usp_16g_tx_preset13                             : integer                       := 0;
		pf0_usp_16g_tx_preset14                             : integer                       := 0;
		pf0_usp_16g_tx_preset15                             : integer                       := 0;
		pf0_usp_tx_preset0                                  : integer                       := 9;
		pf0_usp_tx_preset1                                  : integer                       := 9;
		pf0_usp_tx_preset2                                  : integer                       := 9;
		pf0_usp_tx_preset3                                  : integer                       := 9;
		pf0_usp_tx_preset4                                  : integer                       := 0;
		pf0_usp_tx_preset5                                  : integer                       := 0;
		pf0_usp_tx_preset6                                  : integer                       := 0;
		pf0_usp_tx_preset7                                  : integer                       := 0;
		pf0_usp_tx_preset8                                  : integer                       := 0;
		pf0_usp_tx_preset9                                  : integer                       := 0;
		pf0_usp_tx_preset10                                 : integer                       := 0;
		pf0_usp_tx_preset11                                 : integer                       := 0;
		pf0_usp_tx_preset12                                 : integer                       := 0;
		pf0_usp_tx_preset13                                 : integer                       := 0;
		pf0_usp_tx_preset14                                 : integer                       := 0;
		pf0_usp_tx_preset15                                 : integer                       := 0;
		pf0_pci_type0_bar0_enabled                          : string                        := "PF0_PCI_TYPE0_BAR0_ENABLED_DISABLED";
		pf0_pci_type0_bar0_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_bar0_prefetch                                   : string                        := "false";
		pf0_bar0_type                                       : string                        := "PF0_BAR0_TYPE_BAR_MEM32";
		pf0_pci_type0_bar1_enabled                          : string                        := "PF0_PCI_TYPE0_BAR1_ENABLED_DISABLED";
		pf0_pci_type0_bar1_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_bar1_prefetch                                   : string                        := "false";
		pf0_pci_type0_bar2_enabled                          : string                        := "PF0_PCI_TYPE0_BAR2_ENABLED_DISABLED";
		pf0_pci_type0_bar2_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_bar2_prefetch                                   : string                        := "false";
		pf0_bar2_type                                       : string                        := "PF0_BAR2_TYPE_BAR_MEM32";
		pf0_pci_type0_bar3_enabled                          : string                        := "PF0_PCI_TYPE0_BAR3_ENABLED_DISABLED";
		pf0_pci_type0_bar3_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_bar3_prefetch                                   : string                        := "false";
		pf0_pci_type0_bar4_enabled                          : string                        := "PF0_PCI_TYPE0_BAR4_ENABLED_DISABLED";
		pf0_pci_type0_bar4_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_bar4_prefetch                                   : string                        := "false";
		pf0_bar4_type                                       : string                        := "PF0_BAR4_TYPE_BAR_MEM32";
		pf0_pci_type0_bar5_enabled                          : string                        := "PF0_PCI_TYPE0_BAR5_ENABLED_DISABLED";
		pf0_pci_type0_bar5_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_bar5_prefetch                                   : string                        := "false";
		pf0_rom_bar_enable                                  : string                        := "PF0_ROM_BAR_ENABLE_DISABLED";
		pf0_rom_mask                                        : integer                       := 0;
		pf0_rom_bar_enabled                                 : string                        := "PF0_ROM_BAR_ENABLED_DISABLED";
		pf0_rp_rom_bar_enabled                              : string                        := "PF0_RP_ROM_BAR_ENABLED_DISABLED";
		pf0_rp_rom_mask                                     : integer                       := 0;
		pf0_sriov_vf_bar0_enabled                           : string                        := "PF0_SRIOV_VF_BAR0_ENABLED_DISABLED";
		pf0_sriov_vf_bar0_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_sriov_vf_bar0_prefetch                          : string                        := "false";
		pf0_sriov_vf_bar0_type                              : string                        := "PF0_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32";
		pf0_sriov_vf_bar1_enabled                           : string                        := "PF0_SRIOV_VF_BAR1_ENABLED_DISABLED";
		pf0_sriov_vf_bar1_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_sriov_vf_bar1_prefetch                          : string                        := "false";
		pf0_sriov_vf_bar2_enabled                           : string                        := "PF0_SRIOV_VF_BAR2_ENABLED_DISABLED";
		pf0_sriov_vf_bar2_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_sriov_vf_bar2_prefetch                          : string                        := "false";
		pf0_sriov_vf_bar2_type                              : string                        := "PF0_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32";
		pf0_sriov_vf_bar3_enabled                           : string                        := "PF0_SRIOV_VF_BAR3_ENABLED_DISABLED";
		pf0_sriov_vf_bar3_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_sriov_vf_bar3_prefetch                          : string                        := "false";
		pf0_sriov_vf_bar4_enabled                           : string                        := "PF0_SRIOV_VF_BAR4_ENABLED_DISABLED";
		pf0_sriov_vf_bar4_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_sriov_vf_bar4_prefetch                          : string                        := "false";
		pf0_sriov_vf_bar4_type                              : string                        := "PF0_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32";
		pf0_sriov_vf_bar5_enabled                           : string                        := "PF0_SRIOV_VF_BAR5_ENABLED_DISABLED";
		pf0_sriov_vf_bar5_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_sriov_vf_bar5_prefetch                          : string                        := "false";
		pf1_pci_type0_bar0_enabled                          : string                        := "PF1_PCI_TYPE0_BAR0_ENABLED_DISABLED";
		pf1_pci_type0_bar0_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_bar0_prefetch                                   : string                        := "false";
		pf1_bar0_type                                       : string                        := "PF1_BAR0_TYPE_BAR_MEM32";
		pf1_pci_type0_bar1_enabled                          : string                        := "PF1_PCI_TYPE0_BAR1_ENABLED_DISABLED";
		pf1_pci_type0_bar1_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_bar1_prefetch                                   : string                        := "false";
		pf1_pci_type0_bar2_enabled                          : string                        := "PF1_PCI_TYPE0_BAR2_ENABLED_DISABLED";
		pf1_pci_type0_bar2_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_bar2_prefetch                                   : string                        := "false";
		pf1_bar2_type                                       : string                        := "PF1_BAR2_TYPE_BAR_MEM32";
		pf1_pci_type0_bar3_enabled                          : string                        := "PF1_PCI_TYPE0_BAR3_ENABLED_DISABLED";
		pf1_pci_type0_bar3_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_bar3_prefetch                                   : string                        := "false";
		pf1_pci_type0_bar4_enabled                          : string                        := "PF1_PCI_TYPE0_BAR4_ENABLED_DISABLED";
		pf1_pci_type0_bar4_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_bar4_prefetch                                   : string                        := "false";
		pf1_bar4_type                                       : string                        := "PF1_BAR4_TYPE_BAR_MEM32";
		pf1_pci_type0_bar5_enabled                          : string                        := "PF1_PCI_TYPE0_BAR5_ENABLED_DISABLED";
		pf1_pci_type0_bar5_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_bar5_prefetch                                   : string                        := "false";
		pf1_rom_bar_enable                                  : string                        := "PF1_ROM_BAR_ENABLE_DISABLED";
		pf1_rom_mask                                        : integer                       := 0;
		pf1_rom_bar_enabled                                 : string                        := "PF1_ROM_BAR_ENABLED_DISABLED";
		pf1_sriov_vf_bar0_enabled                           : string                        := "PF1_SRIOV_VF_BAR0_ENABLED_DISABLED";
		pf1_sriov_vf_bar0_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_sriov_vf_bar0_prefetch                          : string                        := "false";
		pf1_sriov_vf_bar0_type                              : string                        := "PF1_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32";
		pf1_sriov_vf_bar1_enabled                           : string                        := "PF1_SRIOV_VF_BAR1_ENABLED_DISABLED";
		pf1_sriov_vf_bar1_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_sriov_vf_bar1_prefetch                          : string                        := "false";
		pf1_sriov_vf_bar2_enabled                           : string                        := "PF1_SRIOV_VF_BAR2_ENABLED_DISABLED";
		pf1_sriov_vf_bar2_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_sriov_vf_bar2_prefetch                          : string                        := "false";
		pf1_sriov_vf_bar2_type                              : string                        := "PF1_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32";
		pf1_sriov_vf_bar3_enabled                           : string                        := "PF1_SRIOV_VF_BAR3_ENABLED_DISABLED";
		pf1_sriov_vf_bar3_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_sriov_vf_bar3_prefetch                          : string                        := "false";
		pf1_sriov_vf_bar4_enabled                           : string                        := "PF1_SRIOV_VF_BAR4_ENABLED_DISABLED";
		pf1_sriov_vf_bar4_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_sriov_vf_bar4_prefetch                          : string                        := "false";
		pf1_sriov_vf_bar4_type                              : string                        := "PF1_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32";
		pf1_sriov_vf_bar5_enabled                           : string                        := "PF1_SRIOV_VF_BAR5_ENABLED_DISABLED";
		pf1_sriov_vf_bar5_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_sriov_vf_bar5_prefetch                          : string                        := "false";
		pf2_pci_type0_bar0_enabled                          : string                        := "PF2_PCI_TYPE0_BAR0_ENABLED_DISABLED";
		pf2_pci_type0_bar0_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_bar0_prefetch                                   : string                        := "false";
		pf2_bar0_type                                       : string                        := "PF2_BAR0_TYPE_BAR_MEM32";
		pf2_pci_type0_bar1_enabled                          : string                        := "PF2_PCI_TYPE0_BAR1_ENABLED_DISABLED";
		pf2_pci_type0_bar1_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_bar1_prefetch                                   : string                        := "false";
		pf2_pci_type0_bar2_enabled                          : string                        := "PF2_PCI_TYPE0_BAR2_ENABLED_DISABLED";
		pf2_pci_type0_bar2_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_bar2_prefetch                                   : string                        := "false";
		pf2_bar2_type                                       : string                        := "PF2_BAR2_TYPE_BAR_MEM32";
		pf2_pci_type0_bar3_enabled                          : string                        := "PF2_PCI_TYPE0_BAR3_ENABLED_DISABLED";
		pf2_pci_type0_bar3_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_bar3_prefetch                                   : string                        := "false";
		pf2_pci_type0_bar4_enabled                          : string                        := "PF2_PCI_TYPE0_BAR4_ENABLED_DISABLED";
		pf2_pci_type0_bar4_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_bar4_prefetch                                   : string                        := "false";
		pf2_bar4_type                                       : string                        := "PF2_BAR4_TYPE_BAR_MEM32";
		pf2_pci_type0_bar5_enabled                          : string                        := "PF2_PCI_TYPE0_BAR5_ENABLED_DISABLED";
		pf2_pci_type0_bar5_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_bar5_prefetch                                   : string                        := "false";
		pf2_rom_bar_enable                                  : string                        := "PF2_ROM_BAR_ENABLE_DISABLED";
		pf2_rom_mask                                        : integer                       := 0;
		pf2_rom_bar_enabled                                 : string                        := "PF2_ROM_BAR_ENABLED_DISABLED";
		pf2_sriov_vf_bar0_enabled                           : string                        := "PF2_SRIOV_VF_BAR0_ENABLED_DISABLED";
		pf2_sriov_vf_bar0_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_sriov_vf_bar0_prefetch                          : string                        := "false";
		pf2_sriov_vf_bar0_type                              : string                        := "PF2_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32";
		pf2_sriov_vf_bar1_enabled                           : string                        := "PF2_SRIOV_VF_BAR1_ENABLED_DISABLED";
		pf2_sriov_vf_bar1_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_sriov_vf_bar1_prefetch                          : string                        := "false";
		pf2_sriov_vf_bar2_enabled                           : string                        := "PF2_SRIOV_VF_BAR2_ENABLED_DISABLED";
		pf2_sriov_vf_bar2_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_sriov_vf_bar2_prefetch                          : string                        := "false";
		pf2_sriov_vf_bar2_type                              : string                        := "PF2_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32";
		pf2_sriov_vf_bar3_enabled                           : string                        := "PF2_SRIOV_VF_BAR3_ENABLED_DISABLED";
		pf2_sriov_vf_bar3_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_sriov_vf_bar3_prefetch                          : string                        := "false";
		pf2_sriov_vf_bar4_enabled                           : string                        := "PF2_SRIOV_VF_BAR4_ENABLED_DISABLED";
		pf2_sriov_vf_bar4_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_sriov_vf_bar4_prefetch                          : string                        := "false";
		pf2_sriov_vf_bar4_type                              : string                        := "PF2_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32";
		pf2_sriov_vf_bar5_enabled                           : string                        := "PF2_SRIOV_VF_BAR5_ENABLED_DISABLED";
		pf2_sriov_vf_bar5_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_sriov_vf_bar5_prefetch                          : string                        := "false";
		pf3_pci_type0_bar0_enabled                          : string                        := "PF3_PCI_TYPE0_BAR0_ENABLED_DISABLED";
		pf3_pci_type0_bar0_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_bar0_prefetch                                   : string                        := "false";
		pf3_bar0_type                                       : string                        := "PF3_BAR0_TYPE_BAR_MEM32";
		pf3_pci_type0_bar1_enabled                          : string                        := "PF3_PCI_TYPE0_BAR1_ENABLED_DISABLED";
		pf3_pci_type0_bar1_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_bar1_prefetch                                   : string                        := "false";
		pf3_pci_type0_bar2_enabled                          : string                        := "PF3_PCI_TYPE0_BAR2_ENABLED_DISABLED";
		pf3_pci_type0_bar2_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_bar2_prefetch                                   : string                        := "false";
		pf3_bar2_type                                       : string                        := "PF3_BAR2_TYPE_BAR_MEM32";
		pf3_pci_type0_bar3_enabled                          : string                        := "PF3_PCI_TYPE0_BAR3_ENABLED_DISABLED";
		pf3_pci_type0_bar3_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_bar3_prefetch                                   : string                        := "false";
		pf3_pci_type0_bar4_enabled                          : string                        := "PF3_PCI_TYPE0_BAR4_ENABLED_DISABLED";
		pf3_pci_type0_bar4_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_bar4_prefetch                                   : string                        := "false";
		pf3_bar4_type                                       : string                        := "PF3_BAR4_TYPE_BAR_MEM32";
		pf3_pci_type0_bar5_enabled                          : string                        := "PF3_PCI_TYPE0_BAR5_ENABLED_DISABLED";
		pf3_pci_type0_bar5_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_bar5_prefetch                                   : string                        := "false";
		pf3_rom_bar_enable                                  : string                        := "PF3_ROM_BAR_ENABLE_DISABLED";
		pf3_rom_mask                                        : integer                       := 0;
		pf3_rom_bar_enabled                                 : string                        := "PF3_ROM_BAR_ENABLED_DISABLED";
		pf3_sriov_vf_bar0_enabled                           : string                        := "PF3_SRIOV_VF_BAR0_ENABLED_DISABLED";
		pf3_sriov_vf_bar0_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_sriov_vf_bar0_prefetch                          : string                        := "false";
		pf3_sriov_vf_bar0_type                              : string                        := "PF3_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32";
		pf3_sriov_vf_bar1_enabled                           : string                        := "PF3_SRIOV_VF_BAR1_ENABLED_DISABLED";
		pf3_sriov_vf_bar1_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_sriov_vf_bar1_prefetch                          : string                        := "false";
		pf3_sriov_vf_bar2_enabled                           : string                        := "PF3_SRIOV_VF_BAR2_ENABLED_DISABLED";
		pf3_sriov_vf_bar2_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_sriov_vf_bar2_prefetch                          : string                        := "false";
		pf3_sriov_vf_bar2_type                              : string                        := "PF3_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32";
		pf3_sriov_vf_bar3_enabled                           : string                        := "PF3_SRIOV_VF_BAR3_ENABLED_DISABLED";
		pf3_sriov_vf_bar3_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_sriov_vf_bar3_prefetch                          : string                        := "false";
		pf3_sriov_vf_bar4_enabled                           : string                        := "PF3_SRIOV_VF_BAR4_ENABLED_DISABLED";
		pf3_sriov_vf_bar4_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_sriov_vf_bar4_prefetch                          : string                        := "false";
		pf3_sriov_vf_bar4_type                              : string                        := "PF3_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32";
		pf3_sriov_vf_bar5_enabled                           : string                        := "PF3_SRIOV_VF_BAR5_ENABLED_DISABLED";
		pf3_sriov_vf_bar5_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_sriov_vf_bar5_prefetch                          : string                        := "false";
		pf1_enable                                          : string                        := "PF1_ENABLE_DISABLED";
		pf2_enable                                          : string                        := "PF2_ENABLE_DISABLED";
		pf3_enable                                          : string                        := "PF3_ENABLE_DISABLED";
		pf0_sriov_enable                                    : string                        := "PF0_SRIOV_ENABLE_DISABLED";
		pf1_sriov_enable                                    : string                        := "PF1_SRIOV_ENABLE_DISABLED";
		pf2_sriov_enable                                    : string                        := "PF2_SRIOV_ENABLE_DISABLED";
		pf3_sriov_enable                                    : string                        := "PF3_SRIOV_ENABLE_DISABLED";
		pf0_sriov_cap_sup_page_size                         : integer                       := 0;
		pf1_sriov_cap_sup_page_size                         : integer                       := 0;
		pf2_sriov_cap_sup_page_size                         : integer                       := 0;
		pf3_sriov_cap_sup_page_size                         : integer                       := 0;
		pf0_sriov_num_vf                                    : integer                       := 0;
		pf1_sriov_num_vf                                    : integer                       := 0;
		pf2_sriov_num_vf                                    : integer                       := 0;
		pf3_sriov_num_vf                                    : integer                       := 0;
		pf0_msi_enable                                      : string                        := "PF0_MSI_ENABLE_DISABLED";
		pf0_pci_msi_ext_data_cap                            : string                        := "false";
		pf0_pci_msi_ext_data_en                             : string                        := "false";
		pf0_pci_msi_64_bit_addr_cap                         : string                        := "false";
		pf0_pci_msi_multiple_msg_cap                        : string                        := "PF0_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1";
		pf0_msix_enable                                     : string                        := "PF0_MSIX_ENABLE_DISABLED";
		pf0_pci_msix_table_size                             : integer                       := 0;
		pf0_pci_msix_table_offset                           : integer                       := 0;
		pf0_pci_msix_bir                                    : integer                       := 0;
		pf0_pci_msix_pba                                    : integer                       := 0;
		pf0_pci_msix_pba_offset                             : integer                       := 0;
		pf0_pci_msix_table_size_vfcomm_cs2                  : integer                       := 0;
		pf0_exvf_msix_cap_enable                            : string                        := "PF0_EXVF_MSIX_CAP_ENABLE_DISABLED";
		exvf_msix_tablesize_pf0                             : integer                       := 0;
		exvf_msixtable_offset_pf0                           : integer                       := 0;
		exvf_msixtable_bir_pf0                              : integer                       := 0;
		exvf_msixpba_offset_pf0                             : integer                       := 0;
		exvf_msixpba_bir_pf0                                : integer                       := 0;
		pf1_msi_enable                                      : string                        := "PF1_MSI_ENABLE_DISABLED";
		pf1_pci_msi_ext_data_cap                            : string                        := "false";
		pf1_pci_msi_ext_data_en                             : string                        := "false";
		pf1_pci_msi_64_bit_addr_cap                         : string                        := "false";
		pf1_pci_msi_multiple_msg_cap                        : string                        := "PF1_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1";
		pf1_msix_enable                                     : string                        := "PF1_MSIX_ENABLE_DISABLED";
		pf1_pci_msix_table_size                             : integer                       := 0;
		pf1_pci_msix_table_offset                           : integer                       := 0;
		pf1_pci_msix_bir                                    : integer                       := 0;
		pf1_pci_msix_pba                                    : integer                       := 0;
		pf1_pci_msix_pba_offset                             : integer                       := 0;
		pf1_pci_msix_table_size_vfcomm_cs2                  : integer                       := 0;
		pf1_exvf_msix_cap_enable                            : string                        := "PF1_EXVF_MSIX_CAP_ENABLE_DISABLED";
		exvf_msix_tablesize_pf1                             : integer                       := 0;
		exvf_msixtable_offset_pf1                           : integer                       := 0;
		exvf_msixtable_bir_pf1                              : integer                       := 0;
		exvf_msixpba_offset_pf1                             : integer                       := 0;
		exvf_msixpba_bir_pf1                                : integer                       := 0;
		pf2_msi_enable                                      : string                        := "PF2_MSI_ENABLE_DISABLED";
		pf2_pci_msi_ext_data_cap                            : string                        := "false";
		pf2_pci_msi_ext_data_en                             : string                        := "false";
		pf2_pci_msi_64_bit_addr_cap                         : string                        := "false";
		pf2_pci_msi_multiple_msg_cap                        : string                        := "PF2_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1";
		pf2_msix_enable                                     : string                        := "PF2_MSIX_ENABLE_DISABLED";
		pf2_pci_msix_bir                                    : integer                       := 0;
		pf2_pci_msix_pba                                    : integer                       := 0;
		pf2_pci_msix_pba_offset                             : integer                       := 0;
		pf2_pci_msix_table_offset                           : integer                       := 0;
		pf2_pci_msix_table_size                             : integer                       := 0;
		pf2_pci_msix_table_size_vfcomm_cs2                  : integer                       := 0;
		pf2_exvf_msix_cap_enable                            : string                        := "PF2_EXVF_MSIX_CAP_ENABLE_DISABLED";
		exvf_msix_tablesize_pf2                             : integer                       := 0;
		exvf_msixtable_offset_pf2                           : integer                       := 0;
		exvf_msixtable_bir_pf2                              : integer                       := 0;
		exvf_msixpba_offset_pf2                             : integer                       := 0;
		exvf_msixpba_bir_pf2                                : integer                       := 0;
		pf3_msi_enable                                      : string                        := "PF3_MSI_ENABLE_DISABLED";
		pf3_pci_msi_ext_data_cap                            : string                        := "false";
		pf3_pci_msi_ext_data_en                             : string                        := "false";
		pf3_pci_msi_64_bit_addr_cap                         : string                        := "false";
		pf3_pci_msi_multiple_msg_cap                        : string                        := "PF3_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1";
		pf3_msix_enable                                     : string                        := "PF3_MSIX_ENABLE_DISABLED";
		pf3_pci_msix_bir                                    : integer                       := 0;
		pf3_pci_msix_pba                                    : integer                       := 0;
		pf3_pci_msix_pba_offset                             : integer                       := 0;
		pf3_pci_msix_table_offset                           : integer                       := 0;
		pf3_pci_msix_table_size                             : integer                       := 0;
		pf3_pci_msix_table_size_vfcomm_cs2                  : integer                       := 0;
		pf3_exvf_msix_cap_enable                            : string                        := "PF3_EXVF_MSIX_CAP_ENABLE_DISABLED";
		exvf_msix_tablesize_pf3                             : integer                       := 0;
		exvf_msixtable_offset_pf3                           : integer                       := 0;
		exvf_msixtable_bir_pf3                              : integer                       := 0;
		exvf_msixpba_offset_pf3                             : integer                       := 0;
		exvf_msixpba_bir_pf3                                : integer                       := 0;
		pf0_prs_ext_cap_enable                              : string                        := "PF0_PRS_EXT_CAP_ENABLE_DISABLED";
		pf0_prs_ext_cap_outstanding_capacity                : integer                       := 0;
		pf1_prs_ext_cap_enable                              : string                        := "PF1_PRS_EXT_CAP_ENABLE_DISABLED";
		pf1_prs_ext_cap_outstanding_capacity                : integer                       := 0;
		pf2_prs_ext_cap_enable                              : string                        := "PF2_PRS_EXT_CAP_ENABLE_DISABLED";
		pf2_prs_ext_cap_outstanding_capacity                : integer                       := 0;
		pf3_prs_ext_cap_enable                              : string                        := "PF3_PRS_EXT_CAP_ENABLE_DISABLED";
		pf3_prs_ext_cap_outstanding_capacity                : integer                       := 0;
		pf0_pasid_cap_enable                                : string                        := "PF0_PASID_CAP_ENABLE_DISABLED";
		pf0_pasid_cap_execute_permission_supported          : string                        := "PF0_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED";
		pf0_pasid_cap_max_pasid_width                       : integer                       := 0;
		pf0_pasid_cap_privileged_mode_supported             : string                        := "PF0_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED";
		pf1_pasid_cap_enable                                : string                        := "PF1_PASID_CAP_ENABLE_DISABLED";
		pf1_pasid_cap_execute_permission_supported          : string                        := "PF1_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED";
		pf1_pasid_cap_max_pasid_width                       : integer                       := 0;
		pf1_pasid_cap_privileged_mode_supported             : string                        := "PF1_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED";
		pf2_pasid_cap_enable                                : string                        := "PF2_PASID_CAP_ENABLE_DISABLED";
		pf2_pasid_cap_execute_permission_supported          : string                        := "PF2_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED";
		pf2_pasid_cap_max_pasid_width                       : integer                       := 0;
		pf2_pasid_cap_privileged_mode_supported             : string                        := "PF2_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED";
		pf3_pasid_cap_enable                                : string                        := "PF3_PASID_CAP_ENABLE_DISABLED";
		pf3_pasid_cap_execute_permission_supported          : string                        := "PF3_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED";
		pf3_pasid_cap_max_pasid_width                       : integer                       := 0;
		pf3_pasid_cap_privileged_mode_supported             : string                        := "PF3_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED";
		pf0_sn_cap_enable                                   : string                        := "PF0_SN_CAP_ENABLE_DISABLED";
		pf0_sn_ser_num_reg_1_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_sn_ser_num_reg_2_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_sn_cap_enable                                   : string                        := "PF1_SN_CAP_ENABLE_DISABLED";
		pf1_sn_ser_num_reg_1_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf1_sn_ser_num_reg_2_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_sn_cap_enable                                   : string                        := "PF2_SN_CAP_ENABLE_DISABLED";
		pf2_sn_ser_num_reg_1_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf2_sn_ser_num_reg_2_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_sn_cap_enable                                   : string                        := "PF3_SN_CAP_ENABLE_DISABLED";
		pf3_sn_ser_num_reg_1_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf3_sn_ser_num_reg_2_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
		pf0_pcie_cap_ep_l0s_accpt_latency                   : integer                       := 0;
		pf0_pcie_cap_ep_l1_accpt_latency                    : integer                       := 0;
		pf0_pcie_cap_l0s_exit_latency_commclk_dis           : integer                       := 7;
		pf0_pcie_cap_l1_exit_latency_commclk_dis            : integer                       := 7;
		pf1_pcie_cap_ep_l0s_accpt_latency                   : integer                       := 0;
		pf1_pcie_cap_ep_l1_accpt_latency                    : integer                       := 0;
		pf1_pcie_cap_l0s_exit_latency_commclk_dis           : integer                       := 0;
		pf1_pcie_cap_l1_exit_latency_commclk_dis            : integer                       := 0;
		pf2_pcie_cap_ep_l0s_accpt_latency                   : integer                       := 0;
		pf2_pcie_cap_ep_l1_accpt_latency                    : integer                       := 0;
		pf2_pcie_cap_l0s_exit_latency_commclk_dis           : integer                       := 0;
		pf2_pcie_cap_l1_exit_latency_commclk_dis            : integer                       := 0;
		pf3_pcie_cap_ep_l0s_accpt_latency                   : integer                       := 0;
		pf3_pcie_cap_ep_l1_accpt_latency                    : integer                       := 0;
		pf3_pcie_cap_l0s_exit_latency_commclk_dis           : integer                       := 0;
		pf3_pcie_cap_l1_exit_latency_commclk_dis            : integer                       := 0;
		aspm_support                                        : string                        := "ASPM_SUPPORT_L0S_L1";
		dbi_ro_wr_disable                                   : string                        := "DBI_RO_WR_DISABLE_ENABLE";
		pf0_gen3_eq_pset_req_vec                            : integer                       := 292;
		pf0_gen3_eq_pset_req_vec_atg4                       : integer                       := 352;
		pf0_pcie_cap_flr_cap                                : string                        := "PF0_PCIE_CAP_FLR_CAP_NOT_CAPABLE";
		pf1_pcie_cap_flr_cap                                : string                        := "PF1_PCIE_CAP_FLR_CAP_NOT_CAPABLE";
		pf2_pcie_cap_flr_cap                                : string                        := "PF2_PCIE_CAP_FLR_CAP_NOT_CAPABLE";
		pf3_pcie_cap_flr_cap                                : string                        := "PF3_PCIE_CAP_FLR_CAP_NOT_CAPABLE";
		pf0_pcie_cap_port_num                               : integer                       := 1;
		pf1_pcie_cap_port_num                               : integer                       := 0;
		pf2_pcie_cap_port_num                               : integer                       := 0;
		pf3_pcie_cap_port_num                               : integer                       := 0;
		pf0_pcie_cap_slot_clk_config                        : string                        := "true";
		pf1_pcie_cap_slot_clk_config                        : string                        := "false";
		pf2_pcie_cap_slot_clk_config                        : string                        := "false";
		pf3_pcie_cap_slot_clk_config                        : string                        := "false";
		pf0_ltr_cap_enable                                  : string                        := "PF0_LTR_CAP_ENABLE_DISABLED";
		pf0_pcie_slot_imp                                   : string                        := "PF0_PCIE_SLOT_IMP_NOT_IMPLEMENTED";
		pf0_pcie_cap_slot_power_limit_scale                 : integer                       := 0;
		pf0_pcie_cap_slot_power_limit_value                 : integer                       := 0;
		pf0_pcie_cap_phy_slot_num                           : integer                       := 0;
		pf0_pcie_cap_hot_plug_capable                       : string                        := "false";
		pf0_pcie_cap_ext_tag_en                             : string                        := "true";
		pf1_pcie_cap_ext_tag_en                             : string                        := "false";
		pf2_pcie_cap_ext_tag_en                             : string                        := "false";
		pf3_pcie_cap_ext_tag_en                             : string                        := "false";
		cfg_ptm_auto_update_signal                          : string                        := "false";
		ptm_autoupdate                                      : string                        := "PTM_AUTOUPDATE_AUTOUPDATE_DISABLE";
		ptm_enable                                          : string                        := "PTM_ENABLE_DISABLE";
		pf0_ats_cap_enable                                  : string                        := "PF0_ATS_CAP_ENABLE_DISABLED";
		pf0_exvf_ats_cap_enable                             : string                        := "PF0_EXVF_ATS_CAP_ENABLE_DISABLED";
		pf0_ats_cap_invalidate_q_depth                      : integer                       := 0;
		pf0_ats_exvf_align_request                          : string                        := "PF0_ATS_EXVF_ALIGN_REQUEST_DISABLE";
		pf1_ats_cap_enable                                  : string                        := "PF1_ATS_CAP_ENABLE_DISABLED";
		pf1_exvf_ats_cap_enable                             : string                        := "PF1_EXVF_ATS_CAP_ENABLE_DISABLED";
		pf1_ats_cap_invalidate_q_depth                      : integer                       := 0;
		pf1_ats_exvf_align_request                          : string                        := "PF1_ATS_EXVF_ALIGN_REQUEST_DISABLE";
		pf2_ats_cap_enable                                  : string                        := "PF2_ATS_CAP_ENABLE_DISABLED";
		pf2_exvf_ats_cap_enable                             : string                        := "PF2_EXVF_ATS_CAP_ENABLE_DISABLED";
		pf2_ats_cap_invalidate_q_depth                      : integer                       := 0;
		pf2_ats_exvf_align_request                          : string                        := "PF2_ATS_EXVF_ALIGN_REQUEST_DISABLE";
		pf3_ats_cap_enable                                  : string                        := "PF3_ATS_CAP_ENABLE_DISABLED";
		pf3_exvf_ats_cap_enable                             : string                        := "PF3_EXVF_ATS_CAP_ENABLE_DISABLED";
		pf3_ats_cap_invalidate_q_depth                      : integer                       := 0;
		pf3_ats_exvf_align_request                          : string                        := "PF3_ATS_EXVF_ALIGN_REQUEST_DISABLE";
		pf0_tph_cap_enable                                  : string                        := "PF0_TPH_CAP_ENABLE_DISABLED";
		pf0_tph_req_cap_int_vec                             : string                        := "PF0_TPH_REQ_CAP_INT_VEC_DISABLED";
		pf0_tph_req_cap_int_vec_vfcomm_cs2                  : string                        := "PF0_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED";
		pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2           : string                        := "PF0_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF";
		pf0_tph_req_cap_st_table_loc_1                      : string                        := "PF0_TPH_REQ_CAP_ST_TABLE_LOC_1_NOT_IN_MSIX_TABLE";
		pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2           : string                        := "PF0_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF";
		pf0_tph_req_cap_st_table_size                       : integer                       := 0;
		pf0_tph_req_cap_st_table_size_vfcomm_cs2            : integer                       := 0;
		pf0_tph_req_device_spec                             : string                        := "PF0_TPH_REQ_DEVICE_SPEC_DISABLED";
		pf0_tph_req_device_spec_vfcomm_cs2                  : string                        := "PF0_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED";
		pf0_exvf_tph_cap_enable                             : string                        := "PF0_EXVF_TPH_CAP_ENABLE_DISABLED";
		exvf_tph_sttablelocation_pf0                        : integer                       := 0;
		exvf_tph_sttablesize_pf0                            : integer                       := 0;
		pf1_tph_cap_enable                                  : string                        := "PF1_TPH_CAP_ENABLE_DISABLED";
		pf1_tph_req_cap_int_vec                             : string                        := "PF1_TPH_REQ_CAP_INT_VEC_DISABLED";
		pf1_tph_req_cap_int_vec_vfcomm_cs2                  : string                        := "PF1_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED";
		pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2           : string                        := "PF1_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF";
		pf1_tph_req_cap_st_table_loc_1                      : string                        := "PF1_TPH_REQ_CAP_ST_TABLE_LOC_1_NOT_IN_MSIX_TABLE";
		pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2           : string                        := "PF1_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF";
		pf1_tph_req_cap_st_table_size                       : integer                       := 0;
		pf1_tph_req_cap_st_table_size_vfcomm_cs2            : integer                       := 0;
		pf1_tph_req_device_spec                             : string                        := "PF1_TPH_REQ_DEVICE_SPEC_DISABLED";
		pf1_tph_req_device_spec_vfcomm_cs2                  : string                        := "PF1_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED";
		pf1_exvf_tph_cap_enable                             : string                        := "PF1_EXVF_TPH_CAP_ENABLE_DISABLED";
		exvf_tph_sttablelocation_pf1                        : integer                       := 0;
		exvf_tph_sttablesize_pf1                            : integer                       := 0;
		pf2_tph_cap_enable                                  : string                        := "PF2_TPH_CAP_ENABLE_DISABLED";
		pf2_tph_req_cap_int_vec                             : string                        := "PF2_TPH_REQ_CAP_INT_VEC_DISABLED";
		pf2_tph_req_cap_int_vec_vfcomm_cs2                  : string                        := "PF2_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED";
		pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2           : string                        := "PF2_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF";
		pf2_tph_req_cap_st_table_loc_1                      : string                        := "PF2_TPH_REQ_CAP_ST_TABLE_LOC_1_NOT_IN_MSIX_TABLE";
		pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2           : string                        := "PF2_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF";
		pf2_tph_req_cap_st_table_size                       : integer                       := 0;
		pf2_tph_req_cap_st_table_size_vfcomm_cs2            : integer                       := 0;
		pf2_tph_req_device_spec                             : string                        := "PF2_TPH_REQ_DEVICE_SPEC_DISABLED";
		pf2_tph_req_device_spec_vfcomm_cs2                  : string                        := "PF2_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED";
		pf2_exvf_tph_cap_enable                             : string                        := "PF2_EXVF_TPH_CAP_ENABLE_DISABLED";
		exvf_tph_sttablelocation_pf2                        : integer                       := 0;
		exvf_tph_sttablesize_pf2                            : integer                       := 0;
		pf3_tph_cap_enable                                  : string                        := "PF3_TPH_CAP_ENABLE_DISABLED";
		pf3_tph_req_cap_int_vec                             : string                        := "PF3_TPH_REQ_CAP_INT_VEC_DISABLED";
		pf3_tph_req_cap_int_vec_vfcomm_cs2                  : string                        := "PF3_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED";
		pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2           : string                        := "PF3_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF";
		pf3_tph_req_cap_st_table_loc_1                      : string                        := "PF3_TPH_REQ_CAP_ST_TABLE_LOC_1_NOT_IN_MSIX_TABLE";
		pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2           : string                        := "PF3_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF";
		pf3_tph_req_cap_st_table_size                       : integer                       := 0;
		pf3_tph_req_cap_st_table_size_vfcomm_cs2            : integer                       := 0;
		pf3_tph_req_device_spec                             : string                        := "PF3_TPH_REQ_DEVICE_SPEC_DISABLED";
		pf3_tph_req_device_spec_vfcomm_cs2                  : string                        := "PF3_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED";
		pf3_exvf_tph_cap_enable                             : string                        := "PF3_EXVF_TPH_CAP_ENABLE_DISABLED";
		exvf_tph_sttablelocation_pf3                        : integer                       := 0;
		exvf_tph_sttablesize_pf3                            : integer                       := 0;
		pf0_acs_cap_enable                                  : string                        := "PF0_ACS_CAP_ENABLE_DISABLED";
		pf0_exvf_acs_cap_enable                             : string                        := "PF0_EXVF_ACS_CAP_ENABLE_DISABLED";
		pf0_acs_cap_acs_src_valid                           : string                        := "PF0_ACS_CAP_ACS_SRC_VALID_DISABLED";
		pf0_acs_cap_acs_at_block                            : string                        := "PF0_ACS_CAP_ACS_AT_BLOCK_DISABLED";
		pf0_acs_cap_acs_p2p_req_redirect                    : string                        := "PF0_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED";
		pf0_acs_cap_acs_p2p_cpl_redirect                    : string                        := "PF0_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED";
		pf0_acs_cap_acs_usp_forwarding                      : string                        := "PF0_ACS_CAP_ACS_USP_FORWARDING_DISABLED";
		pf0_acs_cap_acs_p2p_egress_control                  : string                        := "PF0_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED";
		pf0_acs_cap_acs_egress_ctrl_size                    : integer                       := 8;
		pf0_acs_cap_acs_direct_translated_p2p               : string                        := "PF0_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED";
		pf1_acs_cap_enable                                  : string                        := "PF1_ACS_CAP_ENABLE_DISABLED";
		pf1_exvf_acs_cap_enable                             : string                        := "PF1_EXVF_ACS_CAP_ENABLE_DISABLED";
		pf1_acs_cap_acs_src_valid                           : string                        := "PF1_ACS_CAP_ACS_SRC_VALID_DISABLED";
		pf1_acs_cap_acs_at_block                            : string                        := "PF1_ACS_CAP_ACS_AT_BLOCK_DISABLED";
		pf1_acs_cap_acs_p2p_req_redirect                    : string                        := "PF1_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED";
		pf1_acs_cap_acs_p2p_cpl_redirect                    : string                        := "PF1_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED";
		pf1_acs_cap_acs_usp_forwarding                      : string                        := "PF1_ACS_CAP_ACS_USP_FORWARDING_DISABLED";
		pf1_acs_cap_acs_p2p_egress_control                  : string                        := "PF1_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED";
		pf1_acs_cap_acs_egress_ctrl_size                    : integer                       := 8;
		pf1_acs_cap_acs_direct_translated_p2p               : string                        := "PF1_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED";
		pf2_acs_cap_enable                                  : string                        := "PF2_ACS_CAP_ENABLE_DISABLED";
		pf2_exvf_acs_cap_enable                             : string                        := "PF2_EXVF_ACS_CAP_ENABLE_DISABLED";
		pf2_acs_cap_acs_src_valid                           : string                        := "PF2_ACS_CAP_ACS_SRC_VALID_DISABLED";
		pf2_acs_cap_acs_at_block                            : string                        := "PF2_ACS_CAP_ACS_AT_BLOCK_DISABLED";
		pf2_acs_cap_acs_p2p_req_redirect                    : string                        := "PF2_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED";
		pf2_acs_cap_acs_p2p_cpl_redirect                    : string                        := "PF2_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED";
		pf2_acs_cap_acs_usp_forwarding                      : string                        := "PF2_ACS_CAP_ACS_USP_FORWARDING_DISABLED";
		pf2_acs_cap_acs_p2p_egress_control                  : string                        := "PF2_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED";
		pf2_acs_cap_acs_egress_ctrl_size                    : integer                       := 8;
		pf2_acs_cap_acs_direct_translated_p2p               : string                        := "PF2_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED";
		pf3_acs_cap_enable                                  : string                        := "PF3_ACS_CAP_ENABLE_DISABLED";
		pf3_exvf_acs_cap_enable                             : string                        := "PF3_EXVF_ACS_CAP_ENABLE_DISABLED";
		pf3_acs_cap_acs_src_valid                           : string                        := "PF3_ACS_CAP_ACS_SRC_VALID_DISABLED";
		pf3_acs_cap_acs_at_block                            : string                        := "PF3_ACS_CAP_ACS_AT_BLOCK_DISABLED";
		pf3_acs_cap_acs_p2p_req_redirect                    : string                        := "PF3_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED";
		pf3_acs_cap_acs_p2p_cpl_redirect                    : string                        := "PF3_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED";
		pf3_acs_cap_acs_usp_forwarding                      : string                        := "PF3_ACS_CAP_ACS_USP_FORWARDING_DISABLED";
		pf3_acs_cap_acs_p2p_egress_control                  : string                        := "PF3_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED";
		pf3_acs_cap_acs_egress_ctrl_size                    : integer                       := 8;
		pf3_acs_cap_acs_direct_translated_p2p               : string                        := "PF3_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED";
		pf0_virtio_en                                       : string                        := "PF0_VIRTIO_EN_DISABLED";
		pf1_virtio_en                                       : string                        := "PF1_VIRTIO_EN_DISABLED";
		pf2_virtio_en                                       : string                        := "PF2_VIRTIO_EN_DISABLED";
		pf3_virtio_en                                       : string                        := "PF3_VIRTIO_EN_DISABLED";
		pf0_exvf_virtio_en                                  : string                        := "PF0_EXVF_VIRTIO_EN_DISABLED";
		pf1_exvf_virtio_en                                  : string                        := "PF1_EXVF_VIRTIO_EN_DISABLED";
		pf2_exvf_virtio_en                                  : string                        := "PF2_EXVF_VIRTIO_EN_DISABLED";
		pf3_exvf_virtio_en                                  : string                        := "PF3_EXVF_VIRTIO_EN_DISABLED";
		pf0_pci_type0_device_id                             : integer                       := 0;
		pf0_pci_type0_vendor_id                             : integer                       := 4466;
		pf0_revision_id                                     : integer                       := 1;
		pf0_base_class_code                                 : integer                       := 255;
		pf0_subclass_code                                   : integer                       := 0;
		pf0_program_interface                               : integer                       := 0;
		pf0_subsys_vendor_id                                : integer                       := 0;
		pf0_subsys_dev_id                                   : integer                       := 0;
		pf0_sriov_vf_device_id                              : integer                       := 0;
		exvf_subsysid_pf0                                   : integer                       := 0;
		pf1_pci_type0_vendor_id                             : integer                       := 0;
		pf1_pci_type0_device_id                             : integer                       := 0;
		pf1_revision_id                                     : integer                       := 0;
		pf1_base_class_code                                 : integer                       := 0;
		pf1_subclass_code                                   : integer                       := 0;
		pf1_program_interface                               : integer                       := 0;
		pf1_subsys_vendor_id                                : integer                       := 0;
		pf1_subsys_dev_id                                   : integer                       := 0;
		pf1_sriov_vf_device_id                              : integer                       := 0;
		exvf_subsysid_pf1                                   : integer                       := 0;
		pf2_pci_type0_vendor_id                             : integer                       := 0;
		pf2_pci_type0_device_id                             : integer                       := 0;
		pf2_revision_id                                     : integer                       := 0;
		pf2_base_class_code                                 : integer                       := 0;
		pf2_subclass_code                                   : integer                       := 0;
		pf2_program_interface                               : integer                       := 0;
		pf2_subsys_vendor_id                                : integer                       := 0;
		pf2_subsys_dev_id                                   : integer                       := 0;
		pf2_sriov_vf_device_id                              : integer                       := 0;
		exvf_subsysid_pf2                                   : integer                       := 0;
		pf3_pci_type0_vendor_id                             : integer                       := 0;
		pf3_pci_type0_device_id                             : integer                       := 0;
		pf3_revision_id                                     : integer                       := 0;
		pf3_base_class_code                                 : integer                       := 0;
		pf3_subclass_code                                   : integer                       := 0;
		pf3_program_interface                               : integer                       := 0;
		pf3_subsys_vendor_id                                : integer                       := 0;
		pf3_subsys_dev_id                                   : integer                       := 0;
		pf3_sriov_vf_device_id                              : integer                       := 0;
		exvf_subsysid_pf3                                   : integer                       := 0;
		vsec_select                                         : string                        := "false";
		pf0_user_vsec_cap_enable                            : string                        := "PF0_USER_VSEC_CAP_ENABLE_DISABLED";
		pf1_user_vsec_cap_enable                            : string                        := "PF1_USER_VSEC_CAP_ENABLE_DISABLED";
		pf2_user_vsec_cap_enable                            : string                        := "PF2_USER_VSEC_CAP_ENABLE_DISABLED";
		pf3_user_vsec_cap_enable                            : string                        := "PF3_USER_VSEC_CAP_ENABLE_DISABLED";
		vsec_next_offset                                    : integer                       := 0;
		pf1_user_vsec_offset                                : integer                       := 0;
		pf2_user_vsec_offset                                : integer                       := 0;
		pf3_user_vsec_offset                                : integer                       := 0;
		cvp_vendor_specific_header_id                       : integer                       := 0;
		drop_vendor0_msg                                    : string                        := "FALSE";
		drop_vendor1_msg                                    : string                        := "FALSE";
		pf0_int_pin                                         : string                        := "PF0_INT_PIN_NO_INT";
		pf1_int_pin                                         : string                        := "PF1_INT_PIN_NO_INT";
		pf2_int_pin                                         : string                        := "PF2_INT_PIN_NO_INT";
		pf3_int_pin                                         : string                        := "PF3_INT_PIN_NO_INT";
		dtk_mode_en                                         : string                        := "DTK_MODE_EN_ENABLE";
		ecrc_strip                                          : string                        := "ECRC_STRIP_ENABLE";
		pf0_port_logic_fast_link_mode                       : string                        := "PF0_PORT_LOGIC_FAST_LINK_MODE_DISABLE";
		pf0_prefetch_decode                                 : string                        := "PF0_PREFETCH_DECODE_PREF32";
		pcie_pcs_mode                                       : string                        := "PCIE_PCS_MODE_PCIE";
		sm_hssi_pcie_pcs_clk_mux_0_sel                      : string                        := "SEL_SAME_QUAD_PCLK0";
		sm_hssi_pcie_pcs_clk_mux_1_sel                      : string                        := "SEL_SAME_QUAD_PCLK0";
		sm_hssi_pcie_pcs_clk_mux_2_sel                      : string                        := "SEL_SAME_QUAD_PCLK0";
		sm_hssi_pcie_pcs_clk_mux_3_sel                      : string                        := "SEL_SAME_QUAD_PCLK0";
		sm_hssi_pcie_pcs_hps_clkmux_0_sel                   : string                        := "SEL_HPS_PCS1_ENABLED";
		sm_hssi_pcie_pcs_rst_mux_0_sel                      : string                        := "SEL_SAME_QUAD_PCS_RST";
		sm_hssi_pcie_pcs_rst_mux_1_sel                      : string                        := "SEL_SAME_QUAD_PCS_RST";
		sm_hssi_pcie_pcs_rst_mux_2_sel                      : string                        := "SEL_SAME_QUAD_PCS_RST";
		sm_hssi_pcie_pcs_rst_mux_3_sel                      : string                        := "SEL_SAME_QUAD_PCS_RST";
		sm_hssi_pcie_pcs_tx_mux_0_sel                       : string                        := "SEL_SAME_QUAD_PCIE_CTRL";
		sm_hssi_pcie_pcs_tx_mux_1_sel                       : string                        := "SEL_SAME_QUAD_PCIE_CTRL";
		sm_hssi_pcie_pcs_tx_mux_2_sel                       : string                        := "SEL_SAME_QUAD_PCIE_CTRL";
		sm_hssi_pcie_pcs_tx_mux_3_sel                       : string                        := "SEL_SAME_QUAD_PCIE_CTRL";
		sm_hssi_pcie_pcs_hps_demux_0_sel                    : string                        := "SEL_HPS_PCS1_ENABLED";
		sm_hssi_pcie_pcs_hps_mux_0_sel                      : string                        := "SEL_HPS_PCS1_ENABLED";
		sm_hssi_pcie_pcs_rx_demux_0_sel                     : string                        := "SEL_SAME_QUAD_PCIE_CTRL";
		sm_hssi_pcie_pcs_rx_demux_1_sel                     : string                        := "SEL_SAME_QUAD_PCIE_CTRL";
		sm_hssi_pcie_pcs_rx_demux_2_sel                     : string                        := "SEL_SAME_QUAD_PCIE_CTRL";
		sm_hssi_pcie_pcs_rx_demux_3_sel                     : string                        := "SEL_SAME_QUAD_PCIE_CTRL";
		sm_hssi_pcie_clk_mux_0_sel                          : string                        := "SEL_MIDDLE";
		sm_hssi_pcie_data_mux_0_sel                         : string                        := "SEL_MIDDLE";
		sm_hssi_pld_chnl_dp_0_dr_enabled                    : string                        := "DR_ENABLED_DR_DISABLED";
		sm_hssi_pld_chnl_dp_0_duplex_mode                   : string                        := "DUPLEX_MODE_DUPLEX";
		sm_hssi_pld_chnl_dp_0_pld_channel_identifier        : string                        := "PLD_CHANNEL_IDENTIFIER_PHIP";
		sm_hssi_pld_chnl_dp_0_rx_clkout1_divider            : string                        := "RX_CLKOUT1_DIVIDER_DIV1";
		sm_hssi_pld_chnl_dp_0_rx_clkout2_divider            : string                        := "RX_CLKOUT2_DIVIDER_DIV1";
		sm_hssi_pld_chnl_dp_0_rx_en                         : string                        := "TRUE";
		sm_hssi_pld_chnl_dp_0_rx_fifo_mode                  : string                        := "RX_FIFO_MODE_PHASE_COMP";
		sm_hssi_pld_chnl_dp_0_rx_fifo_width                 : string                        := "RX_FIFO_WIDTH_DOUBLE_DOUBLE_WIDTH";
		sm_hssi_pld_chnl_dp_0_rx_fifo_wr_clk_hz             : std_logic_vector(35 downto 0) := "000000011101110011010110010100000000";
		sm_hssi_pld_chnl_dp_0_rx_user1_clk_dynamic_mux      : string                        := "RX_USER1_CLK_DYNAMIC_MUX_C2";
		sm_hssi_pld_chnl_dp_0_rx_user2_clk_dynamic_mux      : string                        := "RX_USER2_CLK_DYNAMIC_MUX_UX";
		sm_hssi_pld_chnl_dp_0_sup_mode                      : string                        := "SUP_MODE_USER_MODE";
		sm_hssi_pld_chnl_dp_0_tx_clkout1_divider            : string                        := "TX_CLKOUT1_DIVIDER_DIV1";
		sm_hssi_pld_chnl_dp_0_tx_clkout2_divider            : string                        := "TX_CLKOUT2_DIVIDER_DIV1";
		sm_hssi_pld_chnl_dp_0_tx_en                         : string                        := "TRUE";
		sm_hssi_pld_chnl_dp_0_tx_fifo_mode                  : string                        := "TX_FIFO_MODE_PHASE_COMP";
		sm_hssi_pld_chnl_dp_0_tx_fifo_rd_clk_hz             : std_logic_vector(35 downto 0) := "000000011101110011010110010100000000";
		sm_hssi_pld_chnl_dp_0_tx_fifo_width                 : string                        := "TX_FIFO_WIDTH_DOUBLE_DOUBLE_WIDTH";
		sm_hssi_pld_chnl_dp_0_tx_user1_clk_dynamic_mux      : string                        := "TX_USER1_CLK_DYNAMIC_MUX_C1";
		sm_hssi_pld_chnl_dp_0_tx_user2_clk_dynamic_mux      : string                        := "TX_USER2_CLK_DYNAMIC_MUX_UNUSED";
		sm_hssi_pld_chnl_dp_0_vc_rx_pldif_wm_en             : string                        := "VC_RX_PLDIF_WM_EN_DISABLE";
		sm_pld_rx_mux_0_sel                                 : string                        := "SEL_PCIE";
		sm_pld_tx_demux_0_sel                               : string                        := "SEL_PCIE";
		sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_sel           : string                        := "SEL_PCIE";
		sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_sel           : string                        := "SEL_PCIE"
	);
	port (
		i_hio_txdata                           : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*80)-1 downto 0)  := (others => '0'); --                           i_hio_txdata.data,            Stats Snapshot
		i_hio_txdata_extra                     : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*10)-1 downto 0)  := (others => '0'); --                     i_hio_txdata_extra.data,            RX PFC
		i_hio_txdata_fifo_wr_en                : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --                i_hio_txdata_fifo_wr_en.data,            CSR access address
		i_hio_rxdata_fifo_rd_en                : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --                i_hio_rxdata_fifo_rd_en.data,            RX error bits asserted on the EOP cycle
		i_hio_ptp_rst_n                        : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --                        i_hio_ptp_rst_n.reset,           Stats Snapshot
		i_hio_ehip_rx_rst_n                    : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --                    i_hio_ehip_rx_rst_n.reset,           RX PFC
		i_hio_ehip_tx_rst_n                    : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --                    i_hio_ehip_tx_rst_n.reset,           CSR access address
		i_hio_ehip_signal_ok                   : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --                   i_hio_ehip_signal_ok.reset,           RX error bits asserted on the EOP cycle
		i_hio_sfreeze_2_r03f_rx_mac_srfz_n     : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --     i_hio_sfreeze_2_r03f_rx_mac_srfz_n.reset,           Stats Snapshot
		i_hio_sfreeze_3_c2f_tx_deskew_srfz_n   : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --   i_hio_sfreeze_3_c2f_tx_deskew_srfz_n.reset,           RX PFC
		i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n     : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --     i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n.reset,           CSR access address
		i_hio_rstfec_fec_rx_rst_n              : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --              i_hio_rstfec_fec_rx_rst_n.reset,           RX error bits asserted on the EOP cycle
		i_hio_rstfec_fec_tx_rst_n              : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --              i_hio_rstfec_fec_tx_rst_n.reset,           RX error bits asserted on the EOP cycle
		i_hio_rstfec_fec_csr_ret               : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --               i_hio_rstfec_fec_csr_ret.reset,           Stats Snapshot
		i_hio_rstfec_rx_fec_sfrz_n             : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --             i_hio_rstfec_rx_fec_sfrz_n.reset,           RX PFC
		i_hio_rstfec_tx_fec_sfrz_n             : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --             i_hio_rstfec_tx_fec_sfrz_n.reset,           CSR access address
		i_hio_rstxcvrif_xcvrif_rx_rst_n        : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --        i_hio_rstxcvrif_xcvrif_rx_rst_n.reset
		i_hio_rstxcvrif_xcvrif_tx_rst_n        : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --        i_hio_rstxcvrif_xcvrif_tx_rst_n.reset,           Stats Snapshot
		i_hio_rstxcvrif_xcvrif_signal_ok       : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --       i_hio_rstxcvrif_xcvrif_signal_ok.reset,           RX PFC
		i_hio_rstxcvrif_rx_xcvrif_sfrz_n       : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --       i_hio_rstxcvrif_rx_xcvrif_sfrz_n.reset,           CSR access address
		i_hio_rstxcvrif_tx_xcvrif_sfrz_n       : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --       i_hio_rstxcvrif_tx_xcvrif_sfrz_n.reset
		i_hio_rst_pld_clrhip                   : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --                   i_hio_rst_pld_clrhip.reset,           Stats Snapshot
		i_hio_rst_pld_clrpcs                   : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --                   i_hio_rst_pld_clrpcs.reset
		i_hio_rst_pld_perstn                   : in  std_logic                                                     := '0';             --                   i_hio_rst_pld_perstn.reset,           CSR access address
		i_hio_rst_pld_ready                    : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --                    i_hio_rst_pld_ready.reset
		i_hio_rst_pld_adapter_rx_pld_rst_n     : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --     i_hio_rst_pld_adapter_rx_pld_rst_n.reset
		i_hio_rst_pld_adapter_tx_pld_rst_n     : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --     i_hio_rst_pld_adapter_tx_pld_rst_n.reset
		i_hio_rst_ux_rx_pma_rst_n              : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --              i_hio_rst_ux_rx_pma_rst_n.reset
		i_hio_rst_ux_rx_sfrz                   : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --                   i_hio_rst_ux_rx_sfrz.reset
		i_hio_rst_ux_tx_pma_rst_n              : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --              i_hio_rst_ux_tx_pma_rst_n.reset
		i_hio_pld_reset_clk_row                : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => '0'); --                i_hio_pld_reset_clk_row.reset
		i_hio_uxquad_async                     : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*80)-1 downto 0)  := (others => '0'); --                     i_hio_uxquad_async.data
		i_hio_uxquad_async_pcie_mux            : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*80)-1 downto 0)  := (others => '0'); --            i_hio_uxquad_async_pcie_mux.data
		rx_serial_n                            : in  std_logic_vector((hal_num_of_lanes_hwtcl*1)-1 downto 0)       := (others => '0'); --                            rx_serial_n.data
		rx_serial_p                            : in  std_logic_vector((hal_num_of_lanes_hwtcl*1)-1 downto 0)       := (others => '0'); --                            rx_serial_p.data
		o_hio_txdata_fifo_wr_empty             : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --             o_hio_txdata_fifo_wr_empty.data
		o_hio_txdata_fifo_wr_pempty            : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --            o_hio_txdata_fifo_wr_pempty.data
		o_hio_txdata_fifo_wr_full              : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --              o_hio_txdata_fifo_wr_full.data
		o_hio_txdata_fifo_wr_pfull             : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --             o_hio_txdata_fifo_wr_pfull.data
		o_hio_rxdata                           : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*80)-1 downto 0);                     --                           o_hio_rxdata.data
		o_hio_rxdata_extra                     : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*10)-1 downto 0);                     --                     o_hio_rxdata_extra.data
		o_hio_rxdata_fifo_rd_empty             : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --             o_hio_rxdata_fifo_rd_empty.data
		o_hio_rxdata_fifo_rd_pempty            : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --            o_hio_rxdata_fifo_rd_pempty.data
		o_hio_rxdata_fifo_rd_full              : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --              o_hio_rxdata_fifo_rd_full.data
		o_hio_rxdata_fifo_rd_pfull             : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --             o_hio_rxdata_fifo_rd_pfull.data
		o_hio_rstepcs_rx_pcs_fully_aligned     : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --     o_hio_rstepcs_rx_pcs_fully_aligned.reset
		o_hio_rstfec_fec_rx_rdy_n              : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --              o_hio_rstfec_fec_rx_rdy_n.reset
		o_hio_rst_flux0_cpi_cmn_busy           : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --           o_hio_rst_flux0_cpi_cmn_busy.reset
		o_hio_rst_oflux_rx_srds_rdy            : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --            o_hio_rst_oflux_rx_srds_rdy.reset
		o_hio_rst_ux_all_synthlockstatus       : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --       o_hio_rst_ux_all_synthlockstatus.reset
		o_hio_rst_ux_octl_pcs_rxstatus         : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --         o_hio_rst_ux_octl_pcs_rxstatus.reset
		o_hio_rst_ux_octl_pcs_txstatus         : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --         o_hio_rst_ux_octl_pcs_txstatus.reset
		o_hio_rst_ux_rxcdrlock2data            : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --            o_hio_rst_ux_rxcdrlock2data.reset
		o_hio_rst_ux_rxcdrlockstatus           : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      --           o_hio_rst_ux_rxcdrlockstatus.reset
		o_hio_uxquad_async                     : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*50)-1 downto 0);                     --                     o_hio_uxquad_async.data
		tx_serial_p                            : out std_logic_vector((hal_num_of_lanes_hwtcl*1)-1 downto 0);                          --                            tx_serial_p.data
		tx_serial_n                            : out std_logic_vector((hal_num_of_lanes_hwtcl*1)-1 downto 0);                          --                            tx_serial_n.data
		i_hio_txdata_async                     : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*100)-1 downto 0) := (others => '0'); --                     i_hio_txdata_async.data
		i_hio_txdata_direct                    : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*10)-1 downto 0)  := (others => '0'); --                    i_hio_txdata_direct.data
		o_hio_rxdata_async                     : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*100)-1 downto 0);                    --                     o_hio_rxdata_async.data
		o_hio_rxdata_direct                    : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*10)-1 downto 0);                     --                    o_hio_rxdata_direct.data
		ioack_cdrdiv_left_ux_bidir_out         : out std_logic_vector((hal_num_of_lanes_hwtcl*1)-1 downto 0);                          --         ioack_cdrdiv_left_ux_bidir_out.data
		i_refclk_tx_p                          : in  std_logic                                                     := '0';             --                          i_refclk_tx_p.clk
		i_syspll_c0_clk                        : in  std_logic                                                     := '0';             --                        i_syspll_c0_clk.clk
		i_syspll_c1_clk                        : in  std_logic                                                     := '0';             --                        i_syspll_c1_clk.clk
		i_syspll_c2_clk                        : in  std_logic                                                     := '0';             --                        i_syspll_c2_clk.clk
		i_flux_clk                             : in  std_logic                                                     := '0';             --                             i_flux_clk.clk
		i_flux_clk_1                           : in  std_logic                                                     := '0';             --                           i_flux_clk_1.clk
		i_refclk_rx_p                          : in  std_logic                                                     := '0';             --                          i_refclk_rx_p.clk
		i_ss_vccl_syspll_locked                : in  std_logic                                                     := '0';             --                i_ss_vccl_syspll_locked.clk
		o_hio_pcie_user_rx_clk1_clk            : out std_logic;                                                                        --            o_hio_pcie_user_rx_clk1_clk.clk
		o_hio_pcie_user_rx_clk2_clk            : out std_logic;                                                                        --            o_hio_pcie_user_rx_clk2_clk.clk
		o_hio_pcie_user_tx_clk1_clk            : out std_logic;                                                                        --            o_hio_pcie_user_tx_clk1_clk.clk
		o_hio_pcie_user_tx_clk2_clk            : out std_logic;                                                                        --            o_hio_pcie_user_tx_clk2_clk.clk
		i_pin_perst_n                          : in  std_logic                                                     := '0';             --                               phip_hal.i_pin_perst_n,   Check User Guide for details
		i_pin_perst_n_1                        : in  std_logic                                                     := '0';             --                                       .i_pin_perst_n_1, Check User Guide for details
		i_hio_ch0_lavmm_clk                    : in  std_logic                                                     := '0';             --                    i_hio_ch0_lavmm_clk.clk
		i_hio_ch0_lavmm_rstn                   : in  std_logic                                                     := '0';             --                   i_hio_ch0_lavmm_rstn.reset
		i_hio_ch0_lavmm_addr                   : in  std_logic_vector(20 downto 0)                                 := (others => '0'); --                          hio_ch0_lavmm.address
		i_hio_ch0_lavmm_be                     : in  std_logic_vector(3 downto 0)                                  := (others => '0'); --                                       .byteenable
		o_hio_ch0_lavmm_rdata_valid            : out std_logic;                                                                        --                                       .readdatavalid
		i_hio_ch0_lavmm_read                   : in  std_logic                                                     := '0';             --                                       .read
		i_hio_ch0_lavmm_write                  : in  std_logic                                                     := '0';             --                                       .write
		o_hio_ch0_lavmm_rdata                  : out std_logic_vector(31 downto 0);                                                    --                                       .readdata
		i_hio_ch0_lavmm_wdata                  : in  std_logic_vector(31 downto 0)                                 := (others => '0'); --                                       .writedata
		o_hio_ch0_lavmm_waitreq                : out std_logic;                                                                        --                                       .waitrequest
		i_hio_ch0_pld_rx_clk_in_row_clk        : in  std_logic                                                     := '0';             --        i_hio_ch0_pld_rx_clk_in_row_clk.clk
		i_hio_ch0_pld_tx_clk_in_row_clk        : in  std_logic                                                     := '0';             --        i_hio_ch0_pld_tx_clk_in_row_clk.clk
		i_hio_ch0_det_lat_rx_dl_clk            : in  std_logic                                                     := '0';             --            i_hio_ch0_det_lat_rx_dl_clk.clk
		i_hio_ch0_det_lat_rx_mux_select        : in  std_logic                                                     := '0';             --        i_hio_ch0_det_lat_rx_mux_select.clk
		i_hio_ch0_det_lat_rx_sclk_flop         : in  std_logic                                                     := '0';             --         i_hio_ch0_det_lat_rx_sclk_flop.clk
		i_hio_ch0_det_lat_rx_sclk_gen_clk      : in  std_logic                                                     := '0';             --      i_hio_ch0_det_lat_rx_sclk_gen_clk.clk
		i_hio_ch0_det_lat_rx_trig_flop         : in  std_logic                                                     := '0';             --         i_hio_ch0_det_lat_rx_trig_flop.clk
		i_hio_ch0_det_lat_sampling_clk         : in  std_logic                                                     := '0';             --         i_hio_ch0_det_lat_sampling_clk.clk
		i_hio_ch0_det_lat_tx_dl_clk            : in  std_logic                                                     := '0';             --            i_hio_ch0_det_lat_tx_dl_clk.clk
		i_hio_ch0_det_lat_tx_mux_select        : in  std_logic                                                     := '0';             --        i_hio_ch0_det_lat_tx_mux_select.clk
		i_hio_ch0_det_lat_tx_sclk_flop         : in  std_logic                                                     := '0';             --         i_hio_ch0_det_lat_tx_sclk_flop.clk
		i_hio_ch0_det_lat_tx_sclk_gen_clk      : in  std_logic                                                     := '0';             --      i_hio_ch0_det_lat_tx_sclk_gen_clk.clk
		i_hio_ch0_det_lat_tx_trig_flop         : in  std_logic                                                     := '0';             --         i_hio_ch0_det_lat_tx_trig_flop.clk
		o_hio_ch0_user_rx_clk1_clk             : out std_logic;                                                                        --             o_hio_ch0_user_rx_clk1_clk.clk
		o_hio_ch0_user_rx_clk2_clk             : out std_logic;                                                                        --             o_hio_ch0_user_rx_clk2_clk.clk
		o_hio_ch0_user_tx_clk1_clk             : out std_logic;                                                                        --             o_hio_ch0_user_tx_clk1_clk.clk
		o_hio_ch0_user_tx_clk2_clk             : out std_logic;                                                                        --             o_hio_ch0_user_tx_clk2_clk.clk
		o_hio_ch0_ux_chnl_refclk_mux           : out std_logic;                                                                        --           o_hio_ch0_ux_chnl_refclk_mux.clk
		o_hio_ch0_det_lat_rx_async_dl_sync     : out std_logic;                                                                        --     o_hio_ch0_det_lat_rx_async_dl_sync.clk
		o_hio_ch0_det_lat_rx_async_pulse       : out std_logic;                                                                        --       o_hio_ch0_det_lat_rx_async_pulse.clk
		o_hio_ch0_det_lat_rx_async_sample_sync : out std_logic;                                                                        -- o_hio_ch0_det_lat_rx_async_sample_sync.clk
		o_hio_ch0_det_lat_rx_sclk_sample_sync  : out std_logic;                                                                        --  o_hio_ch0_det_lat_rx_sclk_sample_sync.clk
		o_hio_ch0_det_lat_rx_trig_sample_sync  : out std_logic;                                                                        --  o_hio_ch0_det_lat_rx_trig_sample_sync.clk
		o_hio_ch0_det_lat_tx_async_dl_sync     : out std_logic;                                                                        --     o_hio_ch0_det_lat_tx_async_dl_sync.clk
		o_hio_ch0_det_lat_tx_async_pulse       : out std_logic;                                                                        --       o_hio_ch0_det_lat_tx_async_pulse.clk
		o_hio_ch0_det_lat_tx_async_sample_sync : out std_logic;                                                                        -- o_hio_ch0_det_lat_tx_async_sample_sync.clk
		o_hio_ch0_det_lat_tx_sclk_sample_sync  : out std_logic;                                                                        --  o_hio_ch0_det_lat_tx_sclk_sample_sync.clk
		o_hio_ch0_det_lat_tx_trig_sample_sync  : out std_logic;                                                                        --  o_hio_ch0_det_lat_tx_trig_sample_sync.clk
		o_hio_ch0_xcvrif_rx_latency_pulse      : out std_logic;                                                                        --      o_hio_ch0_xcvrif_rx_latency_pulse.clk
		o_hio_ch0_xcvrif_tx_latency_pulse      : out std_logic;                                                                        --      o_hio_ch0_xcvrif_tx_latency_pulse.clk
		i_hio_ch1_lavmm_clk                    : in  std_logic                                                     := '0';             --                    i_hio_ch1_lavmm_clk.clk
		i_hio_ch1_lavmm_rstn                   : in  std_logic                                                     := '0';             --                   i_hio_ch1_lavmm_rstn.reset
		i_hio_ch1_lavmm_addr                   : in  std_logic_vector(20 downto 0)                                 := (others => '0'); --                          hio_ch1_lavmm.address
		i_hio_ch1_lavmm_be                     : in  std_logic_vector(3 downto 0)                                  := (others => '0'); --                                       .byteenable
		o_hio_ch1_lavmm_rdata_valid            : out std_logic;                                                                        --                                       .readdatavalid
		i_hio_ch1_lavmm_read                   : in  std_logic                                                     := '0';             --                                       .read
		i_hio_ch1_lavmm_write                  : in  std_logic                                                     := '0';             --                                       .write
		o_hio_ch1_lavmm_rdata                  : out std_logic_vector(31 downto 0);                                                    --                                       .readdata
		i_hio_ch1_lavmm_wdata                  : in  std_logic_vector(31 downto 0)                                 := (others => '0'); --                                       .writedata
		o_hio_ch1_lavmm_waitreq                : out std_logic;                                                                        --                                       .waitrequest
		i_hio_ch1_pld_rx_clk_in_row_clk        : in  std_logic                                                     := '0';             --        i_hio_ch1_pld_rx_clk_in_row_clk.clk
		i_hio_ch1_pld_tx_clk_in_row_clk        : in  std_logic                                                     := '0';             --        i_hio_ch1_pld_tx_clk_in_row_clk.clk
		i_hio_ch1_det_lat_rx_dl_clk            : in  std_logic                                                     := '0';             --            i_hio_ch1_det_lat_rx_dl_clk.clk
		i_hio_ch1_det_lat_rx_mux_select        : in  std_logic                                                     := '0';             --        i_hio_ch1_det_lat_rx_mux_select.clk
		i_hio_ch1_det_lat_rx_sclk_flop         : in  std_logic                                                     := '0';             --         i_hio_ch1_det_lat_rx_sclk_flop.clk
		i_hio_ch1_det_lat_rx_sclk_gen_clk      : in  std_logic                                                     := '0';             --      i_hio_ch1_det_lat_rx_sclk_gen_clk.clk
		i_hio_ch1_det_lat_rx_trig_flop         : in  std_logic                                                     := '0';             --         i_hio_ch1_det_lat_rx_trig_flop.clk
		i_hio_ch1_det_lat_sampling_clk         : in  std_logic                                                     := '0';             --         i_hio_ch1_det_lat_sampling_clk.clk
		i_hio_ch1_det_lat_tx_dl_clk            : in  std_logic                                                     := '0';             --            i_hio_ch1_det_lat_tx_dl_clk.clk
		i_hio_ch1_det_lat_tx_mux_select        : in  std_logic                                                     := '0';             --        i_hio_ch1_det_lat_tx_mux_select.clk
		i_hio_ch1_det_lat_tx_sclk_flop         : in  std_logic                                                     := '0';             --         i_hio_ch1_det_lat_tx_sclk_flop.clk
		i_hio_ch1_det_lat_tx_sclk_gen_clk      : in  std_logic                                                     := '0';             --      i_hio_ch1_det_lat_tx_sclk_gen_clk.clk
		i_hio_ch1_det_lat_tx_trig_flop         : in  std_logic                                                     := '0';             --         i_hio_ch1_det_lat_tx_trig_flop.clk
		o_hio_ch1_user_rx_clk1_clk             : out std_logic;                                                                        --             o_hio_ch1_user_rx_clk1_clk.clk
		o_hio_ch1_user_rx_clk2_clk             : out std_logic;                                                                        --             o_hio_ch1_user_rx_clk2_clk.clk
		o_hio_ch1_user_tx_clk1_clk             : out std_logic;                                                                        --             o_hio_ch1_user_tx_clk1_clk.clk
		o_hio_ch1_user_tx_clk2_clk             : out std_logic;                                                                        --             o_hio_ch1_user_tx_clk2_clk.clk
		o_hio_ch1_ux_chnl_refclk_mux           : out std_logic;                                                                        --           o_hio_ch1_ux_chnl_refclk_mux.clk
		o_hio_ch1_det_lat_rx_async_dl_sync     : out std_logic;                                                                        --     o_hio_ch1_det_lat_rx_async_dl_sync.clk
		o_hio_ch1_det_lat_rx_async_pulse       : out std_logic;                                                                        --       o_hio_ch1_det_lat_rx_async_pulse.clk
		o_hio_ch1_det_lat_rx_async_sample_sync : out std_logic;                                                                        -- o_hio_ch1_det_lat_rx_async_sample_sync.clk
		o_hio_ch1_det_lat_rx_sclk_sample_sync  : out std_logic;                                                                        --  o_hio_ch1_det_lat_rx_sclk_sample_sync.clk
		o_hio_ch1_det_lat_rx_trig_sample_sync  : out std_logic;                                                                        --  o_hio_ch1_det_lat_rx_trig_sample_sync.clk
		o_hio_ch1_det_lat_tx_async_dl_sync     : out std_logic;                                                                        --     o_hio_ch1_det_lat_tx_async_dl_sync.clk
		o_hio_ch1_det_lat_tx_async_pulse       : out std_logic;                                                                        --       o_hio_ch1_det_lat_tx_async_pulse.clk
		o_hio_ch1_det_lat_tx_async_sample_sync : out std_logic;                                                                        -- o_hio_ch1_det_lat_tx_async_sample_sync.clk
		o_hio_ch1_det_lat_tx_sclk_sample_sync  : out std_logic;                                                                        --  o_hio_ch1_det_lat_tx_sclk_sample_sync.clk
		o_hio_ch1_det_lat_tx_trig_sample_sync  : out std_logic;                                                                        --  o_hio_ch1_det_lat_tx_trig_sample_sync.clk
		o_hio_ch1_xcvrif_rx_latency_pulse      : out std_logic;                                                                        --      o_hio_ch1_xcvrif_rx_latency_pulse.clk
		o_hio_ch1_xcvrif_tx_latency_pulse      : out std_logic;                                                                        --      o_hio_ch1_xcvrif_tx_latency_pulse.clk
		i_hio_ch2_lavmm_clk                    : in  std_logic                                                     := '0';             --                    i_hio_ch2_lavmm_clk.clk
		i_hio_ch2_lavmm_rstn                   : in  std_logic                                                     := '0';             --                   i_hio_ch2_lavmm_rstn.reset
		i_hio_ch2_lavmm_addr                   : in  std_logic_vector(20 downto 0)                                 := (others => '0'); --                          hio_ch2_lavmm.address
		i_hio_ch2_lavmm_be                     : in  std_logic_vector(3 downto 0)                                  := (others => '0'); --                                       .byteenable
		o_hio_ch2_lavmm_rdata_valid            : out std_logic;                                                                        --                                       .readdatavalid
		i_hio_ch2_lavmm_read                   : in  std_logic                                                     := '0';             --                                       .read
		i_hio_ch2_lavmm_write                  : in  std_logic                                                     := '0';             --                                       .write
		o_hio_ch2_lavmm_rdata                  : out std_logic_vector(31 downto 0);                                                    --                                       .readdata
		i_hio_ch2_lavmm_wdata                  : in  std_logic_vector(31 downto 0)                                 := (others => '0'); --                                       .writedata
		o_hio_ch2_lavmm_waitreq                : out std_logic;                                                                        --                                       .waitrequest
		i_hio_ch2_pld_rx_clk_in_row_clk        : in  std_logic                                                     := '0';             --        i_hio_ch2_pld_rx_clk_in_row_clk.clk
		i_hio_ch2_pld_tx_clk_in_row_clk        : in  std_logic                                                     := '0';             --        i_hio_ch2_pld_tx_clk_in_row_clk.clk
		i_hio_ch2_det_lat_rx_dl_clk            : in  std_logic                                                     := '0';             --            i_hio_ch2_det_lat_rx_dl_clk.clk
		i_hio_ch2_det_lat_rx_mux_select        : in  std_logic                                                     := '0';             --        i_hio_ch2_det_lat_rx_mux_select.clk
		i_hio_ch2_det_lat_rx_sclk_flop         : in  std_logic                                                     := '0';             --         i_hio_ch2_det_lat_rx_sclk_flop.clk
		i_hio_ch2_det_lat_rx_sclk_gen_clk      : in  std_logic                                                     := '0';             --      i_hio_ch2_det_lat_rx_sclk_gen_clk.clk
		i_hio_ch2_det_lat_rx_trig_flop         : in  std_logic                                                     := '0';             --         i_hio_ch2_det_lat_rx_trig_flop.clk
		i_hio_ch2_det_lat_sampling_clk         : in  std_logic                                                     := '0';             --         i_hio_ch2_det_lat_sampling_clk.clk
		i_hio_ch2_det_lat_tx_dl_clk            : in  std_logic                                                     := '0';             --            i_hio_ch2_det_lat_tx_dl_clk.clk
		i_hio_ch2_det_lat_tx_mux_select        : in  std_logic                                                     := '0';             --        i_hio_ch2_det_lat_tx_mux_select.clk
		i_hio_ch2_det_lat_tx_sclk_flop         : in  std_logic                                                     := '0';             --         i_hio_ch2_det_lat_tx_sclk_flop.clk
		i_hio_ch2_det_lat_tx_sclk_gen_clk      : in  std_logic                                                     := '0';             --      i_hio_ch2_det_lat_tx_sclk_gen_clk.clk
		i_hio_ch2_det_lat_tx_trig_flop         : in  std_logic                                                     := '0';             --         i_hio_ch2_det_lat_tx_trig_flop.clk
		o_hio_ch2_user_rx_clk1_clk             : out std_logic;                                                                        --             o_hio_ch2_user_rx_clk1_clk.clk
		o_hio_ch2_user_rx_clk2_clk             : out std_logic;                                                                        --             o_hio_ch2_user_rx_clk2_clk.clk
		o_hio_ch2_user_tx_clk1_clk             : out std_logic;                                                                        --             o_hio_ch2_user_tx_clk1_clk.clk
		o_hio_ch2_user_tx_clk2_clk             : out std_logic;                                                                        --             o_hio_ch2_user_tx_clk2_clk.clk
		o_hio_ch2_ux_chnl_refclk_mux           : out std_logic;                                                                        --           o_hio_ch2_ux_chnl_refclk_mux.clk
		o_hio_ch2_det_lat_rx_async_dl_sync     : out std_logic;                                                                        --     o_hio_ch2_det_lat_rx_async_dl_sync.clk
		o_hio_ch2_det_lat_rx_async_pulse       : out std_logic;                                                                        --       o_hio_ch2_det_lat_rx_async_pulse.clk
		o_hio_ch2_det_lat_rx_async_sample_sync : out std_logic;                                                                        -- o_hio_ch2_det_lat_rx_async_sample_sync.clk
		o_hio_ch2_det_lat_rx_sclk_sample_sync  : out std_logic;                                                                        --  o_hio_ch2_det_lat_rx_sclk_sample_sync.clk
		o_hio_ch2_det_lat_rx_trig_sample_sync  : out std_logic;                                                                        --  o_hio_ch2_det_lat_rx_trig_sample_sync.clk
		o_hio_ch2_det_lat_tx_async_dl_sync     : out std_logic;                                                                        --     o_hio_ch2_det_lat_tx_async_dl_sync.clk
		o_hio_ch2_det_lat_tx_async_pulse       : out std_logic;                                                                        --       o_hio_ch2_det_lat_tx_async_pulse.clk
		o_hio_ch2_det_lat_tx_async_sample_sync : out std_logic;                                                                        -- o_hio_ch2_det_lat_tx_async_sample_sync.clk
		o_hio_ch2_det_lat_tx_sclk_sample_sync  : out std_logic;                                                                        --  o_hio_ch2_det_lat_tx_sclk_sample_sync.clk
		o_hio_ch2_det_lat_tx_trig_sample_sync  : out std_logic;                                                                        --  o_hio_ch2_det_lat_tx_trig_sample_sync.clk
		o_hio_ch2_xcvrif_rx_latency_pulse      : out std_logic;                                                                        --      o_hio_ch2_xcvrif_rx_latency_pulse.clk
		o_hio_ch2_xcvrif_tx_latency_pulse      : out std_logic;                                                                        --      o_hio_ch2_xcvrif_tx_latency_pulse.clk
		i_hio_ch3_lavmm_clk                    : in  std_logic                                                     := '0';             --                    i_hio_ch3_lavmm_clk.clk
		i_hio_ch3_lavmm_rstn                   : in  std_logic                                                     := '0';             --                   i_hio_ch3_lavmm_rstn.reset
		i_hio_ch3_lavmm_addr                   : in  std_logic_vector(20 downto 0)                                 := (others => '0'); --                          hio_ch3_lavmm.address
		i_hio_ch3_lavmm_be                     : in  std_logic_vector(3 downto 0)                                  := (others => '0'); --                                       .byteenable
		o_hio_ch3_lavmm_rdata_valid            : out std_logic;                                                                        --                                       .readdatavalid
		i_hio_ch3_lavmm_read                   : in  std_logic                                                     := '0';             --                                       .read
		i_hio_ch3_lavmm_write                  : in  std_logic                                                     := '0';             --                                       .write
		o_hio_ch3_lavmm_rdata                  : out std_logic_vector(31 downto 0);                                                    --                                       .readdata
		i_hio_ch3_lavmm_wdata                  : in  std_logic_vector(31 downto 0)                                 := (others => '0'); --                                       .writedata
		o_hio_ch3_lavmm_waitreq                : out std_logic;                                                                        --                                       .waitrequest
		i_hio_ch3_pld_rx_clk_in_row_clk        : in  std_logic                                                     := '0';             --        i_hio_ch3_pld_rx_clk_in_row_clk.clk
		i_hio_ch3_pld_tx_clk_in_row_clk        : in  std_logic                                                     := '0';             --        i_hio_ch3_pld_tx_clk_in_row_clk.clk
		i_hio_ch3_det_lat_rx_dl_clk            : in  std_logic                                                     := '0';             --            i_hio_ch3_det_lat_rx_dl_clk.clk
		i_hio_ch3_det_lat_rx_mux_select        : in  std_logic                                                     := '0';             --        i_hio_ch3_det_lat_rx_mux_select.clk
		i_hio_ch3_det_lat_rx_sclk_flop         : in  std_logic                                                     := '0';             --         i_hio_ch3_det_lat_rx_sclk_flop.clk
		i_hio_ch3_det_lat_rx_sclk_gen_clk      : in  std_logic                                                     := '0';             --      i_hio_ch3_det_lat_rx_sclk_gen_clk.clk
		i_hio_ch3_det_lat_rx_trig_flop         : in  std_logic                                                     := '0';             --         i_hio_ch3_det_lat_rx_trig_flop.clk
		i_hio_ch3_det_lat_sampling_clk         : in  std_logic                                                     := '0';             --         i_hio_ch3_det_lat_sampling_clk.clk
		i_hio_ch3_det_lat_tx_dl_clk            : in  std_logic                                                     := '0';             --            i_hio_ch3_det_lat_tx_dl_clk.clk
		i_hio_ch3_det_lat_tx_mux_select        : in  std_logic                                                     := '0';             --        i_hio_ch3_det_lat_tx_mux_select.clk
		i_hio_ch3_det_lat_tx_sclk_flop         : in  std_logic                                                     := '0';             --         i_hio_ch3_det_lat_tx_sclk_flop.clk
		i_hio_ch3_det_lat_tx_sclk_gen_clk      : in  std_logic                                                     := '0';             --      i_hio_ch3_det_lat_tx_sclk_gen_clk.clk
		i_hio_ch3_det_lat_tx_trig_flop         : in  std_logic                                                     := '0';             --         i_hio_ch3_det_lat_tx_trig_flop.clk
		o_hio_ch3_user_rx_clk1_clk             : out std_logic;                                                                        --             o_hio_ch3_user_rx_clk1_clk.clk
		o_hio_ch3_user_rx_clk2_clk             : out std_logic;                                                                        --             o_hio_ch3_user_rx_clk2_clk.clk
		o_hio_ch3_user_tx_clk1_clk             : out std_logic;                                                                        --             o_hio_ch3_user_tx_clk1_clk.clk
		o_hio_ch3_user_tx_clk2_clk             : out std_logic;                                                                        --             o_hio_ch3_user_tx_clk2_clk.clk
		o_hio_ch3_ux_chnl_refclk_mux           : out std_logic;                                                                        --           o_hio_ch3_ux_chnl_refclk_mux.clk
		o_hio_ch3_det_lat_rx_async_dl_sync     : out std_logic;                                                                        --     o_hio_ch3_det_lat_rx_async_dl_sync.clk
		o_hio_ch3_det_lat_rx_async_pulse       : out std_logic;                                                                        --       o_hio_ch3_det_lat_rx_async_pulse.clk
		o_hio_ch3_det_lat_rx_async_sample_sync : out std_logic;                                                                        -- o_hio_ch3_det_lat_rx_async_sample_sync.clk
		o_hio_ch3_det_lat_rx_sclk_sample_sync  : out std_logic;                                                                        --  o_hio_ch3_det_lat_rx_sclk_sample_sync.clk
		o_hio_ch3_det_lat_rx_trig_sample_sync  : out std_logic;                                                                        --  o_hio_ch3_det_lat_rx_trig_sample_sync.clk
		o_hio_ch3_det_lat_tx_async_dl_sync     : out std_logic;                                                                        --     o_hio_ch3_det_lat_tx_async_dl_sync.clk
		o_hio_ch3_det_lat_tx_async_pulse       : out std_logic;                                                                        --       o_hio_ch3_det_lat_tx_async_pulse.clk
		o_hio_ch3_det_lat_tx_async_sample_sync : out std_logic;                                                                        -- o_hio_ch3_det_lat_tx_async_sample_sync.clk
		o_hio_ch3_det_lat_tx_sclk_sample_sync  : out std_logic;                                                                        --  o_hio_ch3_det_lat_tx_sclk_sample_sync.clk
		o_hio_ch3_det_lat_tx_trig_sample_sync  : out std_logic;                                                                        --  o_hio_ch3_det_lat_tx_trig_sample_sync.clk
		o_hio_ch3_xcvrif_rx_latency_pulse      : out std_logic;                                                                        --      o_hio_ch3_xcvrif_rx_latency_pulse.clk
		o_hio_ch3_xcvrif_tx_latency_pulse      : out std_logic;                                                                        --      o_hio_ch3_xcvrif_tx_latency_pulse.clk
		i_hio_ch4_lavmm_clk                    : in  std_logic                                                     := '0';             --                    i_hio_ch4_lavmm_clk.clk
		i_hio_ch4_lavmm_rstn                   : in  std_logic                                                     := '0';             --                   i_hio_ch4_lavmm_rstn.reset
		i_hio_ch4_lavmm_addr                   : in  std_logic_vector(20 downto 0)                                 := (others => '0'); --                          hio_ch4_lavmm.address
		i_hio_ch4_lavmm_be                     : in  std_logic_vector(3 downto 0)                                  := (others => '0'); --                                       .byteenable
		o_hio_ch4_lavmm_rdata_valid            : out std_logic;                                                                        --                                       .readdatavalid
		i_hio_ch4_lavmm_read                   : in  std_logic                                                     := '0';             --                                       .read
		i_hio_ch4_lavmm_write                  : in  std_logic                                                     := '0';             --                                       .write
		o_hio_ch4_lavmm_rdata                  : out std_logic_vector(31 downto 0);                                                    --                                       .readdata
		i_hio_ch4_lavmm_wdata                  : in  std_logic_vector(31 downto 0)                                 := (others => '0'); --                                       .writedata
		o_hio_ch4_lavmm_waitreq                : out std_logic;                                                                        --                                       .waitrequest
		i_hio_ch4_pld_rx_clk_in_row_clk        : in  std_logic                                                     := '0';             --        i_hio_ch4_pld_rx_clk_in_row_clk.clk
		i_hio_ch4_pld_tx_clk_in_row_clk        : in  std_logic                                                     := '0';             --        i_hio_ch4_pld_tx_clk_in_row_clk.clk
		i_hio_ch4_det_lat_rx_dl_clk            : in  std_logic                                                     := '0';             --            i_hio_ch4_det_lat_rx_dl_clk.clk
		i_hio_ch4_det_lat_rx_mux_select        : in  std_logic                                                     := '0';             --        i_hio_ch4_det_lat_rx_mux_select.clk
		i_hio_ch4_det_lat_rx_sclk_flop         : in  std_logic                                                     := '0';             --         i_hio_ch4_det_lat_rx_sclk_flop.clk
		i_hio_ch4_det_lat_rx_sclk_gen_clk      : in  std_logic                                                     := '0';             --      i_hio_ch4_det_lat_rx_sclk_gen_clk.clk
		i_hio_ch4_det_lat_rx_trig_flop         : in  std_logic                                                     := '0';             --         i_hio_ch4_det_lat_rx_trig_flop.clk
		i_hio_ch4_det_lat_sampling_clk         : in  std_logic                                                     := '0';             --         i_hio_ch4_det_lat_sampling_clk.clk
		i_hio_ch4_det_lat_tx_dl_clk            : in  std_logic                                                     := '0';             --            i_hio_ch4_det_lat_tx_dl_clk.clk
		i_hio_ch4_det_lat_tx_mux_select        : in  std_logic                                                     := '0';             --        i_hio_ch4_det_lat_tx_mux_select.clk
		i_hio_ch4_det_lat_tx_sclk_flop         : in  std_logic                                                     := '0';             --         i_hio_ch4_det_lat_tx_sclk_flop.clk
		i_hio_ch4_det_lat_tx_sclk_gen_clk      : in  std_logic                                                     := '0';             --      i_hio_ch4_det_lat_tx_sclk_gen_clk.clk
		i_hio_ch4_det_lat_tx_trig_flop         : in  std_logic                                                     := '0';             --         i_hio_ch4_det_lat_tx_trig_flop.clk
		o_hio_ch4_user_rx_clk1_clk             : out std_logic;                                                                        --             o_hio_ch4_user_rx_clk1_clk.clk
		o_hio_ch4_user_rx_clk2_clk             : out std_logic;                                                                        --             o_hio_ch4_user_rx_clk2_clk.clk
		o_hio_ch4_user_tx_clk1_clk             : out std_logic;                                                                        --             o_hio_ch4_user_tx_clk1_clk.clk
		o_hio_ch4_user_tx_clk2_clk             : out std_logic;                                                                        --             o_hio_ch4_user_tx_clk2_clk.clk
		o_hio_ch4_ux_chnl_refclk_mux           : out std_logic;                                                                        --           o_hio_ch4_ux_chnl_refclk_mux.clk
		o_hio_ch4_det_lat_rx_async_dl_sync     : out std_logic;                                                                        --     o_hio_ch4_det_lat_rx_async_dl_sync.clk
		o_hio_ch4_det_lat_rx_async_pulse       : out std_logic;                                                                        --       o_hio_ch4_det_lat_rx_async_pulse.clk
		o_hio_ch4_det_lat_rx_async_sample_sync : out std_logic;                                                                        -- o_hio_ch4_det_lat_rx_async_sample_sync.clk
		o_hio_ch4_det_lat_rx_sclk_sample_sync  : out std_logic;                                                                        --  o_hio_ch4_det_lat_rx_sclk_sample_sync.clk
		o_hio_ch4_det_lat_rx_trig_sample_sync  : out std_logic;                                                                        --  o_hio_ch4_det_lat_rx_trig_sample_sync.clk
		o_hio_ch4_det_lat_tx_async_dl_sync     : out std_logic;                                                                        --     o_hio_ch4_det_lat_tx_async_dl_sync.clk
		o_hio_ch4_det_lat_tx_async_pulse       : out std_logic;                                                                        --       o_hio_ch4_det_lat_tx_async_pulse.clk
		o_hio_ch4_det_lat_tx_async_sample_sync : out std_logic;                                                                        -- o_hio_ch4_det_lat_tx_async_sample_sync.clk
		o_hio_ch4_det_lat_tx_sclk_sample_sync  : out std_logic;                                                                        --  o_hio_ch4_det_lat_tx_sclk_sample_sync.clk
		o_hio_ch4_det_lat_tx_trig_sample_sync  : out std_logic;                                                                        --  o_hio_ch4_det_lat_tx_trig_sample_sync.clk
		o_hio_ch4_xcvrif_rx_latency_pulse      : out std_logic;                                                                        --      o_hio_ch4_xcvrif_rx_latency_pulse.clk
		o_hio_ch4_xcvrif_tx_latency_pulse      : out std_logic                                                                         --      o_hio_ch4_xcvrif_tx_latency_pulse.clk
	);
end entity gts_axi_streaming_intel_pcie_gts_pcie_hal_top_800_a4pwunq;

architecture rtl of gts_axi_streaming_intel_pcie_gts_pcie_hal_top_800_a4pwunq is
	component gts_axi_streaming_pcie_hal_top_2100_jipcchq_cmp is
		generic (
			ch0_pcs_l_tx_en_atom                                : string                        := "FALSE";
			ch0_pcs_l_rx_en_atom                                : string                        := "FALSE";
			ch0_fec_loopback_mode_atom                          : string                        := "CH0_LOOPBACK_MODE_DISABLE";
			ch0_fec_dyn_tx_mux_atom                             : string                        := "CH0_DYN_TX_MUX_UNUSED";
			ch0_fec_error_atom                                  : string                        := "FALSE";
			ch0_fec_rx_en_atom                                  : string                        := "FALSE";
			ch0_fec_tx_en_atom                                  : string                        := "FALSE";
			ch0_fec_mode_atom                                   : string                        := "CH0_FEC_MODE_DISABLED";
			ch1_pcs_l_tx_en_atom                                : string                        := "FALSE";
			ch1_pcs_l_rx_en_atom                                : string                        := "FALSE";
			ch1_fec_loopback_mode_atom                          : string                        := "CH1_LOOPBACK_MODE_DISABLE";
			ch1_fec_dyn_tx_mux_atom                             : string                        := "CH1_DYN_TX_MUX_UNUSED";
			ch1_fec_error_atom                                  : string                        := "FALSE";
			ch1_fec_rx_en_atom                                  : string                        := "FALSE";
			ch1_fec_tx_en_atom                                  : string                        := "FALSE";
			ch1_fec_mode_atom                                   : string                        := "CH1_FEC_MODE_DISABLED";
			ch2_pcs_l_tx_en_atom                                : string                        := "FALSE";
			ch2_pcs_l_rx_en_atom                                : string                        := "FALSE";
			ch2_fec_loopback_mode_atom                          : string                        := "CH2_LOOPBACK_MODE_DISABLE";
			ch2_fec_dyn_tx_mux_atom                             : string                        := "CH2_DYN_TX_MUX_UNUSED";
			ch2_fec_error_atom                                  : string                        := "FALSE";
			ch2_fec_rx_en_atom                                  : string                        := "FALSE";
			ch2_fec_tx_en_atom                                  : string                        := "FALSE";
			ch2_fec_mode_atom                                   : string                        := "CH2_FEC_MODE_DISABLED";
			ch3_pcs_l_tx_en_atom                                : string                        := "FALSE";
			ch3_pcs_l_rx_en_atom                                : string                        := "FALSE";
			ch3_fec_loopback_mode_atom                          : string                        := "CH3_LOOPBACK_MODE_DISABLE";
			ch3_fec_dyn_tx_mux_atom                             : string                        := "CH3_DYN_TX_MUX_UNUSED";
			ch3_fec_error_atom                                  : string                        := "FALSE";
			ch3_fec_rx_en_atom                                  : string                        := "FALSE";
			ch3_fec_tx_en_atom                                  : string                        := "FALSE";
			ch3_fec_mode_atom                                   : string                        := "CH3_FEC_MODE_DISABLED";
			ch0_xcvr_rx_prbs_monitor_en_atom                    : string                        := "CH0_RX_PRBS_MONITOR_EN_DISABLE";
			ch1_xcvr_rx_prbs_monitor_en_atom                    : string                        := "CH1_RX_PRBS_MONITOR_EN_DISABLE";
			ch2_xcvr_rx_prbs_monitor_en_atom                    : string                        := "CH2_RX_PRBS_MONITOR_EN_DISABLE";
			ch3_xcvr_rx_prbs_monitor_en_atom                    : string                        := "CH3_RX_PRBS_MONITOR_EN_DISABLE";
			ch0_tx_prbs_gen_en_atom                             : string                        := "CH0_TX_PRBS_GEN_EN_DISABLE";
			ch1_tx_prbs_gen_en_atom                             : string                        := "CH1_TX_PRBS_GEN_EN_DISABLE";
			ch2_tx_prbs_gen_en_atom                             : string                        := "CH2_TX_PRBS_GEN_EN_DISABLE";
			ch3_tx_prbs_gen_en_atom                             : string                        := "CH3_TX_PRBS_GEN_EN_DISABLE";
			ch0_rx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH0_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch0_rx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH0_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch0_tx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH0_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch0_tx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH0_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch1_rx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH1_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch1_rx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH1_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch1_tx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH1_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch1_tx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH1_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch2_rx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH2_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch2_rx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH2_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch2_tx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH2_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch2_tx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH2_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch3_rx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH3_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch3_rx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH3_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch3_tx_user1_clk_mux_dynamic_sel_atom               : string                        := "CH3_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch3_tx_user2_clk_mux_dynamic_sel_atom               : string                        := "CH3_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED";
			ch0_pcie_mode_atom                                  : string                        := "CH0_PCIE_MODE_GEN3";
			ch1_pcie_mode_atom                                  : string                        := "CH1_PCIE_MODE_GEN3";
			ch2_pcie_mode_atom                                  : string                        := "CH2_PCIE_MODE_GEN3";
			ch3_pcie_mode_atom                                  : string                        := "CH3_PCIE_MODE_GEN3";
			ch0_xcvr_rx_protocol_hint_atom                      : string                        := "CH0_RX_PROTOCOL_HINT_DISABLED";
			ch1_xcvr_rx_protocol_hint_atom                      : string                        := "CH1_RX_PROTOCOL_HINT_DISABLED";
			ch2_xcvr_rx_protocol_hint_atom                      : string                        := "CH2_RX_PROTOCOL_HINT_DISABLED";
			ch3_xcvr_rx_protocol_hint_atom                      : string                        := "CH3_RX_PROTOCOL_HINT_DISABLED";
			ch0_clkrx_refclk_cssm_fw_control_atom               : string                        := "CH0_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE";
			ch1_clkrx_refclk_cssm_fw_control_atom               : string                        := "CH1_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE";
			ch2_clkrx_refclk_cssm_fw_control_atom               : string                        := "CH2_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE";
			ch3_clkrx_refclk_cssm_fw_control_atom               : string                        := "CH3_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE";
			ch0_clkrx_refclk_sector_specifies_refclk_ready_atom : string                        := "CH0_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
			ch1_clkrx_refclk_sector_specifies_refclk_ready_atom : string                        := "CH1_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
			ch2_clkrx_refclk_sector_specifies_refclk_ready_atom : string                        := "CH2_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
			ch3_clkrx_refclk_sector_specifies_refclk_ready_atom : string                        := "CH3_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
			ch0_local_refclk_cssm_fw_control_atom               : string                        := "CH0_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE";
			ch1_local_refclk_cssm_fw_control_atom               : string                        := "CH1_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE";
			ch2_local_refclk_cssm_fw_control_atom               : string                        := "CH2_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE";
			ch3_local_refclk_cssm_fw_control_atom               : string                        := "CH3_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE";
			ch0_local_refclk_sector_specifies_refclk_ready_atom : string                        := "CH0_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
			ch1_local_refclk_sector_specifies_refclk_ready_atom : string                        := "CH1_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
			ch2_local_refclk_sector_specifies_refclk_ready_atom : string                        := "CH2_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
			ch3_local_refclk_sector_specifies_refclk_ready_atom : string                        := "CH3_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
			ch0_tx_bonding_category_atom                        : string                        := "CH0_TX_BONDING_CATEGORY_UNUSED";
			ch1_tx_bonding_category_atom                        : string                        := "CH1_TX_BONDING_CATEGORY_UNUSED";
			ch2_tx_bonding_category_atom                        : string                        := "CH2_TX_BONDING_CATEGORY_UNUSED";
			ch3_tx_bonding_category_atom                        : string                        := "CH3_TX_BONDING_CATEGORY_UNUSED";
			hal_num_of_lanes_hwtcl                              : integer                       := 4;
			is_sm4_sm7_revA                                     : integer                       := 0;
			ch0_duplex_mode_atom                                : string                        := "";
			ch0_fec_spec_atom                                   : string                        := "";
			ch0_fracture_atom                                   : string                        := "";
			ch0_dr_enabled_atom                                 : string                        := "";
			ch0_sup_mode_atom                                   : string                        := "";
			ch0_sim_mode_atom                                   : string                        := "";
			ch1_duplex_mode_atom                                : string                        := "";
			ch1_fec_spec_atom                                   : string                        := "";
			ch1_fracture_atom                                   : string                        := "";
			ch1_dr_enabled_atom                                 : string                        := "";
			ch1_sup_mode_atom                                   : string                        := "";
			ch1_sim_mode_atom                                   : string                        := "";
			ch2_duplex_mode_atom                                : string                        := "";
			ch2_fec_spec_atom                                   : string                        := "";
			ch2_fracture_atom                                   : string                        := "";
			ch2_dr_enabled_atom                                 : string                        := "";
			ch2_sup_mode_atom                                   : string                        := "";
			ch2_sim_mode_atom                                   : string                        := "";
			ch3_duplex_mode_atom                                : string                        := "";
			ch3_fec_spec_atom                                   : string                        := "";
			ch3_fracture_atom                                   : string                        := "";
			ch3_dr_enabled_atom                                 : string                        := "";
			ch3_sup_mode_atom                                   : string                        := "";
			ch3_sim_mode_atom                                   : string                        := "";
			ch0_xcvr_tx_preloaded_hardware_configs_atom         : string                        := "";
			ch0_xcvr_rx_preloaded_hardware_configs_atom         : string                        := "";
			ch0_lc_postdiv_sel_atom                             : string                        := "";
			ch0_sequencer_reg_en_atom                           : string                        := "";
			ch0_rst_mux_static_sel_atom                         : string                        := "";
			ch0_xcvr_tx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0000";
			ch0_xcvr_rx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0000";
			ch0_xcvr_tx_user_clk_only_mode_atom                 : string                        := "";
			ch0_xcvr_tx_width_atom                              : string                        := "";
			ch0_xcvr_rx_width_atom                              : string                        := "";
			ch0_phy_loopback_mode_atom                          : string                        := "";
			ch0_flux_mode_atom                                  : string                        := "";
			ch0_flux_mode_hw_atom                               : string                        := "";
			ch0_tx_sim_mode_atom                                : string                        := "";
			ch0_rx_sim_mode_atom                                : string                        := "";
			ch0_tx_dl_enable_atom                               : string                        := "";
			ch0_rx_dl_enable_atom                               : string                        := "";
			ch0_rx_fec_type_used_atom                           : string                        := "";
			ch1_xcvr_tx_preloaded_hardware_configs_atom         : string                        := "";
			ch1_xcvr_rx_preloaded_hardware_configs_atom         : string                        := "";
			ch1_lc_postdiv_sel_atom                             : string                        := "";
			ch1_sequencer_reg_en_atom                           : string                        := "";
			ch1_rst_mux_static_sel_atom                         : string                        := "";
			ch1_xcvr_tx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0000";
			ch1_xcvr_rx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0000";
			ch1_xcvr_tx_user_clk_only_mode_atom                 : string                        := "";
			ch1_xcvr_tx_width_atom                              : string                        := "";
			ch1_xcvr_rx_width_atom                              : string                        := "";
			ch1_phy_loopback_mode_atom                          : string                        := "";
			ch1_flux_mode_atom                                  : string                        := "";
			ch1_flux_mode_hw_atom                               : string                        := "";
			ch1_tx_sim_mode_atom                                : string                        := "";
			ch1_rx_sim_mode_atom                                : string                        := "";
			ch1_tx_dl_enable_atom                               : string                        := "";
			ch1_rx_dl_enable_atom                               : string                        := "";
			ch1_rx_fec_type_used_atom                           : string                        := "";
			ch2_xcvr_tx_preloaded_hardware_configs_atom         : string                        := "";
			ch2_xcvr_rx_preloaded_hardware_configs_atom         : string                        := "";
			ch2_lc_postdiv_sel_atom                             : string                        := "";
			ch2_sequencer_reg_en_atom                           : string                        := "";
			ch2_rst_mux_static_sel_atom                         : string                        := "";
			ch2_xcvr_tx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0000";
			ch2_xcvr_rx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0000";
			ch2_xcvr_tx_user_clk_only_mode_atom                 : string                        := "";
			ch2_xcvr_tx_width_atom                              : string                        := "";
			ch2_xcvr_rx_width_atom                              : string                        := "";
			ch2_phy_loopback_mode_atom                          : string                        := "";
			ch2_flux_mode_atom                                  : string                        := "";
			ch2_flux_mode_hw_atom                               : string                        := "";
			ch2_tx_sim_mode_atom                                : string                        := "";
			ch2_rx_sim_mode_atom                                : string                        := "";
			ch2_tx_dl_enable_atom                               : string                        := "";
			ch2_rx_dl_enable_atom                               : string                        := "";
			ch2_rx_fec_type_used_atom                           : string                        := "";
			ch3_xcvr_tx_preloaded_hardware_configs_atom         : string                        := "";
			ch3_xcvr_rx_preloaded_hardware_configs_atom         : string                        := "";
			ch3_lc_postdiv_sel_atom                             : string                        := "";
			ch3_sequencer_reg_en_atom                           : string                        := "";
			ch3_rst_mux_static_sel_atom                         : string                        := "";
			ch3_xcvr_tx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0000";
			ch3_xcvr_rx_prbs_pattern_atom                       : std_logic_vector(3 downto 0)  := "0000";
			ch3_xcvr_tx_user_clk_only_mode_atom                 : string                        := "";
			ch3_xcvr_tx_width_atom                              : string                        := "";
			ch3_xcvr_rx_width_atom                              : string                        := "";
			ch3_phy_loopback_mode_atom                          : string                        := "";
			ch3_flux_mode_atom                                  : string                        := "";
			ch3_flux_mode_hw_atom                               : string                        := "";
			ch3_tx_sim_mode_atom                                : string                        := "";
			ch3_rx_sim_mode_atom                                : string                        := "";
			ch3_tx_dl_enable_atom                               : string                        := "";
			ch3_rx_dl_enable_atom                               : string                        := "";
			ch3_rx_fec_type_used_atom                           : string                        := "";
			ch0_tx_pll_l_counter_atom                           : std_logic_vector(5 downto 0)  := "000000";
			ch0_cdr_l_counter_atom                              : std_logic_vector(5 downto 0)  := "000000";
			ch0_tx_pll_refclk_select_atom                       : string                        := "";
			ch0_cdr_refclk_select_atom                          : string                        := "";
			ch1_tx_pll_l_counter_atom                           : std_logic_vector(5 downto 0)  := "000000";
			ch1_cdr_l_counter_atom                              : std_logic_vector(5 downto 0)  := "000000";
			ch1_tx_pll_refclk_select_atom                       : string                        := "";
			ch1_cdr_refclk_select_atom                          : string                        := "";
			ch2_tx_pll_l_counter_atom                           : std_logic_vector(5 downto 0)  := "000000";
			ch2_cdr_l_counter_atom                              : std_logic_vector(5 downto 0)  := "000000";
			ch2_tx_pll_refclk_select_atom                       : string                        := "";
			ch2_cdr_refclk_select_atom                          : string                        := "";
			ch3_tx_pll_l_counter_atom                           : std_logic_vector(5 downto 0)  := "000000";
			ch3_cdr_l_counter_atom                              : std_logic_vector(5 downto 0)  := "000000";
			ch3_tx_pll_refclk_select_atom                       : string                        := "";
			ch3_cdr_refclk_select_atom                          : string                        := "";
			ch0_rx_dl_rx_lat_bit_for_async_atom                 : std_logic_vector(17 downto 0) := "000000000000000000";
			ch0_rx_dl_rxbit_cntr_pma_atom                       : string                        := "";
			ch0_rx_dl_rxbit_rollover_atom                       : std_logic_vector(17 downto 0) := "000000000000000000";
			ch1_rx_dl_rx_lat_bit_for_async_atom                 : std_logic_vector(17 downto 0) := "000000000000000000";
			ch1_rx_dl_rxbit_cntr_pma_atom                       : string                        := "";
			ch1_rx_dl_rxbit_rollover_atom                       : std_logic_vector(17 downto 0) := "000000000000000000";
			ch2_rx_dl_rx_lat_bit_for_async_atom                 : std_logic_vector(17 downto 0) := "000000000000000000";
			ch2_rx_dl_rxbit_cntr_pma_atom                       : string                        := "";
			ch2_rx_dl_rxbit_rollover_atom                       : std_logic_vector(17 downto 0) := "000000000000000000";
			ch3_rx_dl_rx_lat_bit_for_async_atom                 : std_logic_vector(17 downto 0) := "000000000000000000";
			ch3_rx_dl_rxbit_cntr_pma_atom                       : string                        := "";
			ch3_rx_dl_rxbit_rollover_atom                       : std_logic_vector(17 downto 0) := "000000000000000000";
			ch0_tx_bond_size_atom                               : string                        := "";
			ch1_tx_bond_size_atom                               : string                        := "";
			ch2_tx_bond_size_atom                               : string                        := "";
			ch3_tx_bond_size_atom                               : string                        := "";
			ch0_rx_invert_pin_atom                              : string                        := "";
			ch1_rx_invert_pin_atom                              : string                        := "";
			ch2_rx_invert_pin_atom                              : string                        := "";
			ch3_rx_invert_pin_atom                              : string                        := "";
			ch0_tx_invert_pin_atom                              : string                        := "";
			ch1_tx_invert_pin_atom                              : string                        := "";
			ch2_tx_invert_pin_atom                              : string                        := "";
			ch3_tx_invert_pin_atom                              : string                        := "";
			ch0_vsr_mode_atom                                   : string                        := "";
			ch1_vsr_mode_atom                                   : string                        := "";
			ch2_vsr_mode_atom                                   : string                        := "";
			ch3_vsr_mode_atom                                   : string                        := "";
			pcie_parity_bypass                                  : string                        := "";
			rxbuf_limit_bypass                                  : integer                       := 0;
			maxpayload_size                                     : string                        := "";
			pldclk_rate                                         : string                        := "";
			port_type                                           : string                        := "";
			sris_enable                                         : string                        := "";
			link_num                                            : string                        := "";
			sris_mode                                           : string                        := "";
			sim_mode                                            : string                        := "";
			sup_mode                                            : string                        := "";
			cvp_enable                                          : string                        := "";
			cii_monitor_en                                      : string                        := "";
			pclk_clk_hz                                         : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_cap_link_surprise_down_err_cap                  : string                        := "";
			sys_clk_hz                                          : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			link_rate                                           : string                        := "";
			link_width                                          : string                        := "";
			num_of_lanes                                        : string                        := "";
			pf0_dsp_16g_tx_preset0                              : integer                       := 0;
			pf0_dsp_16g_tx_preset1                              : integer                       := 0;
			pf0_dsp_16g_tx_preset2                              : integer                       := 0;
			pf0_dsp_16g_tx_preset3                              : integer                       := 0;
			pf0_dsp_16g_tx_preset4                              : integer                       := 0;
			pf0_dsp_16g_tx_preset5                              : integer                       := 0;
			pf0_dsp_16g_tx_preset6                              : integer                       := 0;
			pf0_dsp_16g_tx_preset7                              : integer                       := 0;
			pf0_dsp_16g_tx_preset8                              : integer                       := 0;
			pf0_dsp_16g_tx_preset9                              : integer                       := 0;
			pf0_dsp_16g_tx_preset10                             : integer                       := 0;
			pf0_dsp_16g_tx_preset11                             : integer                       := 0;
			pf0_dsp_16g_tx_preset12                             : integer                       := 0;
			pf0_dsp_16g_tx_preset13                             : integer                       := 0;
			pf0_dsp_16g_tx_preset14                             : integer                       := 0;
			pf0_dsp_16g_tx_preset15                             : integer                       := 0;
			pf0_dsp_tx_preset0                                  : integer                       := 0;
			pf0_dsp_tx_preset1                                  : integer                       := 0;
			pf0_dsp_tx_preset2                                  : integer                       := 0;
			pf0_dsp_tx_preset3                                  : integer                       := 0;
			pf0_dsp_tx_preset4                                  : integer                       := 0;
			pf0_dsp_tx_preset5                                  : integer                       := 0;
			pf0_dsp_tx_preset6                                  : integer                       := 0;
			pf0_dsp_tx_preset7                                  : integer                       := 0;
			pf0_dsp_tx_preset8                                  : integer                       := 0;
			pf0_dsp_tx_preset9                                  : integer                       := 0;
			pf0_dsp_tx_preset10                                 : integer                       := 0;
			pf0_dsp_tx_preset11                                 : integer                       := 0;
			pf0_dsp_tx_preset12                                 : integer                       := 0;
			pf0_dsp_tx_preset13                                 : integer                       := 0;
			pf0_dsp_tx_preset14                                 : integer                       := 0;
			pf0_dsp_tx_preset15                                 : integer                       := 0;
			pf0_usp_16g_tx_preset0                              : integer                       := 0;
			pf0_usp_16g_tx_preset1                              : integer                       := 0;
			pf0_usp_16g_tx_preset2                              : integer                       := 0;
			pf0_usp_16g_tx_preset3                              : integer                       := 0;
			pf0_usp_16g_tx_preset4                              : integer                       := 0;
			pf0_usp_16g_tx_preset5                              : integer                       := 0;
			pf0_usp_16g_tx_preset6                              : integer                       := 0;
			pf0_usp_16g_tx_preset7                              : integer                       := 0;
			pf0_usp_16g_tx_preset8                              : integer                       := 0;
			pf0_usp_16g_tx_preset9                              : integer                       := 0;
			pf0_usp_16g_tx_preset10                             : integer                       := 0;
			pf0_usp_16g_tx_preset11                             : integer                       := 0;
			pf0_usp_16g_tx_preset12                             : integer                       := 0;
			pf0_usp_16g_tx_preset13                             : integer                       := 0;
			pf0_usp_16g_tx_preset14                             : integer                       := 0;
			pf0_usp_16g_tx_preset15                             : integer                       := 0;
			pf0_usp_tx_preset0                                  : integer                       := 0;
			pf0_usp_tx_preset1                                  : integer                       := 0;
			pf0_usp_tx_preset2                                  : integer                       := 0;
			pf0_usp_tx_preset3                                  : integer                       := 0;
			pf0_usp_tx_preset4                                  : integer                       := 0;
			pf0_usp_tx_preset5                                  : integer                       := 0;
			pf0_usp_tx_preset6                                  : integer                       := 0;
			pf0_usp_tx_preset7                                  : integer                       := 0;
			pf0_usp_tx_preset8                                  : integer                       := 0;
			pf0_usp_tx_preset9                                  : integer                       := 0;
			pf0_usp_tx_preset10                                 : integer                       := 0;
			pf0_usp_tx_preset11                                 : integer                       := 0;
			pf0_usp_tx_preset12                                 : integer                       := 0;
			pf0_usp_tx_preset13                                 : integer                       := 0;
			pf0_usp_tx_preset14                                 : integer                       := 0;
			pf0_usp_tx_preset15                                 : integer                       := 0;
			pf0_pci_type0_bar0_enabled                          : string                        := "";
			pf0_pci_type0_bar0_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_bar0_prefetch                                   : string                        := "";
			pf0_bar0_type                                       : string                        := "";
			pf0_pci_type0_bar1_enabled                          : string                        := "";
			pf0_pci_type0_bar1_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_bar1_prefetch                                   : string                        := "";
			pf0_pci_type0_bar2_enabled                          : string                        := "";
			pf0_pci_type0_bar2_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_bar2_prefetch                                   : string                        := "";
			pf0_bar2_type                                       : string                        := "";
			pf0_pci_type0_bar3_enabled                          : string                        := "";
			pf0_pci_type0_bar3_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_bar3_prefetch                                   : string                        := "";
			pf0_pci_type0_bar4_enabled                          : string                        := "";
			pf0_pci_type0_bar4_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_bar4_prefetch                                   : string                        := "";
			pf0_bar4_type                                       : string                        := "";
			pf0_pci_type0_bar5_enabled                          : string                        := "";
			pf0_pci_type0_bar5_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_bar5_prefetch                                   : string                        := "";
			pf0_rom_bar_enable                                  : string                        := "";
			pf0_rom_mask                                        : integer                       := 0;
			pf0_rom_bar_enabled                                 : string                        := "";
			pf0_rp_rom_bar_enabled                              : string                        := "";
			pf0_rp_rom_mask                                     : integer                       := 0;
			pf0_sriov_vf_bar0_enabled                           : string                        := "";
			pf0_sriov_vf_bar0_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_sriov_vf_bar0_prefetch                          : string                        := "";
			pf0_sriov_vf_bar0_type                              : string                        := "";
			pf0_sriov_vf_bar1_enabled                           : string                        := "";
			pf0_sriov_vf_bar1_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_sriov_vf_bar1_prefetch                          : string                        := "";
			pf0_sriov_vf_bar2_enabled                           : string                        := "";
			pf0_sriov_vf_bar2_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_sriov_vf_bar2_prefetch                          : string                        := "";
			pf0_sriov_vf_bar2_type                              : string                        := "";
			pf0_sriov_vf_bar3_enabled                           : string                        := "";
			pf0_sriov_vf_bar3_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_sriov_vf_bar3_prefetch                          : string                        := "";
			pf0_sriov_vf_bar4_enabled                           : string                        := "";
			pf0_sriov_vf_bar4_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_sriov_vf_bar4_prefetch                          : string                        := "";
			pf0_sriov_vf_bar4_type                              : string                        := "";
			pf0_sriov_vf_bar5_enabled                           : string                        := "";
			pf0_sriov_vf_bar5_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_sriov_vf_bar5_prefetch                          : string                        := "";
			pf1_pci_type0_bar0_enabled                          : string                        := "";
			pf1_pci_type0_bar0_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_bar0_prefetch                                   : string                        := "";
			pf1_bar0_type                                       : string                        := "";
			pf1_pci_type0_bar1_enabled                          : string                        := "";
			pf1_pci_type0_bar1_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_bar1_prefetch                                   : string                        := "";
			pf1_pci_type0_bar2_enabled                          : string                        := "";
			pf1_pci_type0_bar2_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_bar2_prefetch                                   : string                        := "";
			pf1_bar2_type                                       : string                        := "";
			pf1_pci_type0_bar3_enabled                          : string                        := "";
			pf1_pci_type0_bar3_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_bar3_prefetch                                   : string                        := "";
			pf1_pci_type0_bar4_enabled                          : string                        := "";
			pf1_pci_type0_bar4_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_bar4_prefetch                                   : string                        := "";
			pf1_bar4_type                                       : string                        := "";
			pf1_pci_type0_bar5_enabled                          : string                        := "";
			pf1_pci_type0_bar5_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_bar5_prefetch                                   : string                        := "";
			pf1_rom_bar_enable                                  : string                        := "";
			pf1_rom_mask                                        : integer                       := 0;
			pf1_rom_bar_enabled                                 : string                        := "";
			pf1_sriov_vf_bar0_enabled                           : string                        := "";
			pf1_sriov_vf_bar0_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_sriov_vf_bar0_prefetch                          : string                        := "";
			pf1_sriov_vf_bar0_type                              : string                        := "";
			pf1_sriov_vf_bar1_enabled                           : string                        := "";
			pf1_sriov_vf_bar1_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_sriov_vf_bar1_prefetch                          : string                        := "";
			pf1_sriov_vf_bar2_enabled                           : string                        := "";
			pf1_sriov_vf_bar2_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_sriov_vf_bar2_prefetch                          : string                        := "";
			pf1_sriov_vf_bar2_type                              : string                        := "";
			pf1_sriov_vf_bar3_enabled                           : string                        := "";
			pf1_sriov_vf_bar3_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_sriov_vf_bar3_prefetch                          : string                        := "";
			pf1_sriov_vf_bar4_enabled                           : string                        := "";
			pf1_sriov_vf_bar4_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_sriov_vf_bar4_prefetch                          : string                        := "";
			pf1_sriov_vf_bar4_type                              : string                        := "";
			pf1_sriov_vf_bar5_enabled                           : string                        := "";
			pf1_sriov_vf_bar5_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_sriov_vf_bar5_prefetch                          : string                        := "";
			pf2_pci_type0_bar0_enabled                          : string                        := "";
			pf2_pci_type0_bar0_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_bar0_prefetch                                   : string                        := "";
			pf2_bar0_type                                       : string                        := "";
			pf2_pci_type0_bar1_enabled                          : string                        := "";
			pf2_pci_type0_bar1_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_bar1_prefetch                                   : string                        := "";
			pf2_pci_type0_bar2_enabled                          : string                        := "";
			pf2_pci_type0_bar2_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_bar2_prefetch                                   : string                        := "";
			pf2_bar2_type                                       : string                        := "";
			pf2_pci_type0_bar3_enabled                          : string                        := "";
			pf2_pci_type0_bar3_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_bar3_prefetch                                   : string                        := "";
			pf2_pci_type0_bar4_enabled                          : string                        := "";
			pf2_pci_type0_bar4_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_bar4_prefetch                                   : string                        := "";
			pf2_bar4_type                                       : string                        := "";
			pf2_pci_type0_bar5_enabled                          : string                        := "";
			pf2_pci_type0_bar5_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_bar5_prefetch                                   : string                        := "";
			pf2_rom_bar_enable                                  : string                        := "";
			pf2_rom_mask                                        : integer                       := 0;
			pf2_rom_bar_enabled                                 : string                        := "";
			pf2_sriov_vf_bar0_enabled                           : string                        := "";
			pf2_sriov_vf_bar0_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_sriov_vf_bar0_prefetch                          : string                        := "";
			pf2_sriov_vf_bar0_type                              : string                        := "";
			pf2_sriov_vf_bar1_enabled                           : string                        := "";
			pf2_sriov_vf_bar1_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_sriov_vf_bar1_prefetch                          : string                        := "";
			pf2_sriov_vf_bar2_enabled                           : string                        := "";
			pf2_sriov_vf_bar2_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_sriov_vf_bar2_prefetch                          : string                        := "";
			pf2_sriov_vf_bar2_type                              : string                        := "";
			pf2_sriov_vf_bar3_enabled                           : string                        := "";
			pf2_sriov_vf_bar3_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_sriov_vf_bar3_prefetch                          : string                        := "";
			pf2_sriov_vf_bar4_enabled                           : string                        := "";
			pf2_sriov_vf_bar4_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_sriov_vf_bar4_prefetch                          : string                        := "";
			pf2_sriov_vf_bar4_type                              : string                        := "";
			pf2_sriov_vf_bar5_enabled                           : string                        := "";
			pf2_sriov_vf_bar5_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_sriov_vf_bar5_prefetch                          : string                        := "";
			pf3_pci_type0_bar0_enabled                          : string                        := "";
			pf3_pci_type0_bar0_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_bar0_prefetch                                   : string                        := "";
			pf3_bar0_type                                       : string                        := "";
			pf3_pci_type0_bar1_enabled                          : string                        := "";
			pf3_pci_type0_bar1_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_bar1_prefetch                                   : string                        := "";
			pf3_pci_type0_bar2_enabled                          : string                        := "";
			pf3_pci_type0_bar2_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_bar2_prefetch                                   : string                        := "";
			pf3_bar2_type                                       : string                        := "";
			pf3_pci_type0_bar3_enabled                          : string                        := "";
			pf3_pci_type0_bar3_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_bar3_prefetch                                   : string                        := "";
			pf3_pci_type0_bar4_enabled                          : string                        := "";
			pf3_pci_type0_bar4_mask_31_1                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_bar4_prefetch                                   : string                        := "";
			pf3_bar4_type                                       : string                        := "";
			pf3_pci_type0_bar5_enabled                          : string                        := "";
			pf3_pci_type0_bar5_mask_31_0                        : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_bar5_prefetch                                   : string                        := "";
			pf3_rom_bar_enable                                  : string                        := "";
			pf3_rom_mask                                        : integer                       := 0;
			pf3_rom_bar_enabled                                 : string                        := "";
			pf3_sriov_vf_bar0_enabled                           : string                        := "";
			pf3_sriov_vf_bar0_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_sriov_vf_bar0_prefetch                          : string                        := "";
			pf3_sriov_vf_bar0_type                              : string                        := "";
			pf3_sriov_vf_bar1_enabled                           : string                        := "";
			pf3_sriov_vf_bar1_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_sriov_vf_bar1_prefetch                          : string                        := "";
			pf3_sriov_vf_bar2_enabled                           : string                        := "";
			pf3_sriov_vf_bar2_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_sriov_vf_bar2_prefetch                          : string                        := "";
			pf3_sriov_vf_bar2_type                              : string                        := "";
			pf3_sriov_vf_bar3_enabled                           : string                        := "";
			pf3_sriov_vf_bar3_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_sriov_vf_bar3_prefetch                          : string                        := "";
			pf3_sriov_vf_bar4_enabled                           : string                        := "";
			pf3_sriov_vf_bar4_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_sriov_vf_bar4_prefetch                          : string                        := "";
			pf3_sriov_vf_bar4_type                              : string                        := "";
			pf3_sriov_vf_bar5_enabled                           : string                        := "";
			pf3_sriov_vf_bar5_mask                              : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_sriov_vf_bar5_prefetch                          : string                        := "";
			pf1_enable                                          : string                        := "";
			pf2_enable                                          : string                        := "";
			pf3_enable                                          : string                        := "";
			pf0_sriov_enable                                    : string                        := "";
			pf1_sriov_enable                                    : string                        := "";
			pf2_sriov_enable                                    : string                        := "";
			pf3_sriov_enable                                    : string                        := "";
			pf0_sriov_cap_sup_page_size                         : integer                       := 0;
			pf1_sriov_cap_sup_page_size                         : integer                       := 0;
			pf2_sriov_cap_sup_page_size                         : integer                       := 0;
			pf3_sriov_cap_sup_page_size                         : integer                       := 0;
			pf0_sriov_num_vf                                    : integer                       := 0;
			pf1_sriov_num_vf                                    : integer                       := 0;
			pf2_sriov_num_vf                                    : integer                       := 0;
			pf3_sriov_num_vf                                    : integer                       := 0;
			pf0_msi_enable                                      : string                        := "";
			pf0_pci_msi_ext_data_cap                            : string                        := "";
			pf0_pci_msi_ext_data_en                             : string                        := "";
			pf0_pci_msi_64_bit_addr_cap                         : string                        := "";
			pf0_pci_msi_multiple_msg_cap                        : string                        := "";
			pf0_msix_enable                                     : string                        := "";
			pf0_pci_msix_table_size                             : integer                       := 0;
			pf0_pci_msix_table_offset                           : integer                       := 0;
			pf0_pci_msix_bir                                    : integer                       := 0;
			pf0_pci_msix_pba                                    : integer                       := 0;
			pf0_pci_msix_pba_offset                             : integer                       := 0;
			pf0_pci_msix_table_size_vfcomm_cs2                  : integer                       := 0;
			pf0_exvf_msix_cap_enable                            : string                        := "";
			exvf_msix_tablesize_pf0                             : integer                       := 0;
			exvf_msixtable_offset_pf0                           : integer                       := 0;
			exvf_msixtable_bir_pf0                              : integer                       := 0;
			exvf_msixpba_offset_pf0                             : integer                       := 0;
			exvf_msixpba_bir_pf0                                : integer                       := 0;
			pf1_msi_enable                                      : string                        := "";
			pf1_pci_msi_ext_data_cap                            : string                        := "";
			pf1_pci_msi_ext_data_en                             : string                        := "";
			pf1_pci_msi_64_bit_addr_cap                         : string                        := "";
			pf1_pci_msi_multiple_msg_cap                        : string                        := "";
			pf1_msix_enable                                     : string                        := "";
			pf1_pci_msix_table_size                             : integer                       := 0;
			pf1_pci_msix_table_offset                           : integer                       := 0;
			pf1_pci_msix_bir                                    : integer                       := 0;
			pf1_pci_msix_pba                                    : integer                       := 0;
			pf1_pci_msix_pba_offset                             : integer                       := 0;
			pf1_pci_msix_table_size_vfcomm_cs2                  : integer                       := 0;
			pf1_exvf_msix_cap_enable                            : string                        := "";
			exvf_msix_tablesize_pf1                             : integer                       := 0;
			exvf_msixtable_offset_pf1                           : integer                       := 0;
			exvf_msixtable_bir_pf1                              : integer                       := 0;
			exvf_msixpba_offset_pf1                             : integer                       := 0;
			exvf_msixpba_bir_pf1                                : integer                       := 0;
			pf2_msi_enable                                      : string                        := "";
			pf2_pci_msi_ext_data_cap                            : string                        := "";
			pf2_pci_msi_ext_data_en                             : string                        := "";
			pf2_pci_msi_64_bit_addr_cap                         : string                        := "";
			pf2_pci_msi_multiple_msg_cap                        : string                        := "";
			pf2_msix_enable                                     : string                        := "";
			pf2_pci_msix_bir                                    : integer                       := 0;
			pf2_pci_msix_pba                                    : integer                       := 0;
			pf2_pci_msix_pba_offset                             : integer                       := 0;
			pf2_pci_msix_table_offset                           : integer                       := 0;
			pf2_pci_msix_table_size                             : integer                       := 0;
			pf2_pci_msix_table_size_vfcomm_cs2                  : integer                       := 0;
			pf2_exvf_msix_cap_enable                            : string                        := "";
			exvf_msix_tablesize_pf2                             : integer                       := 0;
			exvf_msixtable_offset_pf2                           : integer                       := 0;
			exvf_msixtable_bir_pf2                              : integer                       := 0;
			exvf_msixpba_offset_pf2                             : integer                       := 0;
			exvf_msixpba_bir_pf2                                : integer                       := 0;
			pf3_msi_enable                                      : string                        := "";
			pf3_pci_msi_ext_data_cap                            : string                        := "";
			pf3_pci_msi_ext_data_en                             : string                        := "";
			pf3_pci_msi_64_bit_addr_cap                         : string                        := "";
			pf3_pci_msi_multiple_msg_cap                        : string                        := "";
			pf3_msix_enable                                     : string                        := "";
			pf3_pci_msix_bir                                    : integer                       := 0;
			pf3_pci_msix_pba                                    : integer                       := 0;
			pf3_pci_msix_pba_offset                             : integer                       := 0;
			pf3_pci_msix_table_offset                           : integer                       := 0;
			pf3_pci_msix_table_size                             : integer                       := 0;
			pf3_pci_msix_table_size_vfcomm_cs2                  : integer                       := 0;
			pf3_exvf_msix_cap_enable                            : string                        := "";
			exvf_msix_tablesize_pf3                             : integer                       := 0;
			exvf_msixtable_offset_pf3                           : integer                       := 0;
			exvf_msixtable_bir_pf3                              : integer                       := 0;
			exvf_msixpba_offset_pf3                             : integer                       := 0;
			exvf_msixpba_bir_pf3                                : integer                       := 0;
			pf0_prs_ext_cap_enable                              : string                        := "";
			pf0_prs_ext_cap_outstanding_capacity                : integer                       := 0;
			pf1_prs_ext_cap_enable                              : string                        := "";
			pf1_prs_ext_cap_outstanding_capacity                : integer                       := 0;
			pf2_prs_ext_cap_enable                              : string                        := "";
			pf2_prs_ext_cap_outstanding_capacity                : integer                       := 0;
			pf3_prs_ext_cap_enable                              : string                        := "";
			pf3_prs_ext_cap_outstanding_capacity                : integer                       := 0;
			pf0_pasid_cap_enable                                : string                        := "";
			pf0_pasid_cap_execute_permission_supported          : string                        := "";
			pf0_pasid_cap_max_pasid_width                       : integer                       := 0;
			pf0_pasid_cap_privileged_mode_supported             : string                        := "";
			pf1_pasid_cap_enable                                : string                        := "";
			pf1_pasid_cap_execute_permission_supported          : string                        := "";
			pf1_pasid_cap_max_pasid_width                       : integer                       := 0;
			pf1_pasid_cap_privileged_mode_supported             : string                        := "";
			pf2_pasid_cap_enable                                : string                        := "";
			pf2_pasid_cap_execute_permission_supported          : string                        := "";
			pf2_pasid_cap_max_pasid_width                       : integer                       := 0;
			pf2_pasid_cap_privileged_mode_supported             : string                        := "";
			pf3_pasid_cap_enable                                : string                        := "";
			pf3_pasid_cap_execute_permission_supported          : string                        := "";
			pf3_pasid_cap_max_pasid_width                       : integer                       := 0;
			pf3_pasid_cap_privileged_mode_supported             : string                        := "";
			pf0_sn_cap_enable                                   : string                        := "";
			pf0_sn_ser_num_reg_1_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_sn_ser_num_reg_2_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_sn_cap_enable                                   : string                        := "";
			pf1_sn_ser_num_reg_1_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf1_sn_ser_num_reg_2_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_sn_cap_enable                                   : string                        := "";
			pf2_sn_ser_num_reg_1_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf2_sn_ser_num_reg_2_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_sn_cap_enable                                   : string                        := "";
			pf3_sn_ser_num_reg_1_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf3_sn_ser_num_reg_2_dw                             : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
			pf0_pcie_cap_ep_l0s_accpt_latency                   : integer                       := 0;
			pf0_pcie_cap_ep_l1_accpt_latency                    : integer                       := 0;
			pf0_pcie_cap_l0s_exit_latency_commclk_dis           : integer                       := 0;
			pf0_pcie_cap_l1_exit_latency_commclk_dis            : integer                       := 0;
			pf1_pcie_cap_ep_l0s_accpt_latency                   : integer                       := 0;
			pf1_pcie_cap_ep_l1_accpt_latency                    : integer                       := 0;
			pf1_pcie_cap_l0s_exit_latency_commclk_dis           : integer                       := 0;
			pf1_pcie_cap_l1_exit_latency_commclk_dis            : integer                       := 0;
			pf2_pcie_cap_ep_l0s_accpt_latency                   : integer                       := 0;
			pf2_pcie_cap_ep_l1_accpt_latency                    : integer                       := 0;
			pf2_pcie_cap_l0s_exit_latency_commclk_dis           : integer                       := 0;
			pf2_pcie_cap_l1_exit_latency_commclk_dis            : integer                       := 0;
			pf3_pcie_cap_ep_l0s_accpt_latency                   : integer                       := 0;
			pf3_pcie_cap_ep_l1_accpt_latency                    : integer                       := 0;
			pf3_pcie_cap_l0s_exit_latency_commclk_dis           : integer                       := 0;
			pf3_pcie_cap_l1_exit_latency_commclk_dis            : integer                       := 0;
			aspm_support                                        : string                        := "";
			dbi_ro_wr_disable                                   : string                        := "";
			pf0_gen3_eq_pset_req_vec                            : integer                       := 0;
			pf0_gen3_eq_pset_req_vec_atg4                       : integer                       := 0;
			pf0_pcie_cap_flr_cap                                : string                        := "";
			pf1_pcie_cap_flr_cap                                : string                        := "";
			pf2_pcie_cap_flr_cap                                : string                        := "";
			pf3_pcie_cap_flr_cap                                : string                        := "";
			pf0_pcie_cap_port_num                               : integer                       := 0;
			pf1_pcie_cap_port_num                               : integer                       := 0;
			pf2_pcie_cap_port_num                               : integer                       := 0;
			pf3_pcie_cap_port_num                               : integer                       := 0;
			pf0_pcie_cap_slot_clk_config                        : string                        := "";
			pf1_pcie_cap_slot_clk_config                        : string                        := "";
			pf2_pcie_cap_slot_clk_config                        : string                        := "";
			pf3_pcie_cap_slot_clk_config                        : string                        := "";
			pf0_ltr_cap_enable                                  : string                        := "";
			pf0_pcie_slot_imp                                   : string                        := "";
			pf0_pcie_cap_slot_power_limit_scale                 : integer                       := 0;
			pf0_pcie_cap_slot_power_limit_value                 : integer                       := 0;
			pf0_pcie_cap_phy_slot_num                           : integer                       := 0;
			pf0_pcie_cap_hot_plug_capable                       : string                        := "";
			pf0_pcie_cap_ext_tag_en                             : string                        := "";
			pf1_pcie_cap_ext_tag_en                             : string                        := "";
			pf2_pcie_cap_ext_tag_en                             : string                        := "";
			pf3_pcie_cap_ext_tag_en                             : string                        := "";
			cfg_ptm_auto_update_signal                          : string                        := "";
			ptm_autoupdate                                      : string                        := "";
			ptm_enable                                          : string                        := "";
			pf0_ats_cap_enable                                  : string                        := "";
			pf0_exvf_ats_cap_enable                             : string                        := "";
			pf0_ats_cap_invalidate_q_depth                      : integer                       := 0;
			pf0_ats_exvf_align_request                          : string                        := "";
			pf1_ats_cap_enable                                  : string                        := "";
			pf1_exvf_ats_cap_enable                             : string                        := "";
			pf1_ats_cap_invalidate_q_depth                      : integer                       := 0;
			pf1_ats_exvf_align_request                          : string                        := "";
			pf2_ats_cap_enable                                  : string                        := "";
			pf2_exvf_ats_cap_enable                             : string                        := "";
			pf2_ats_cap_invalidate_q_depth                      : integer                       := 0;
			pf2_ats_exvf_align_request                          : string                        := "";
			pf3_ats_cap_enable                                  : string                        := "";
			pf3_exvf_ats_cap_enable                             : string                        := "";
			pf3_ats_cap_invalidate_q_depth                      : integer                       := 0;
			pf3_ats_exvf_align_request                          : string                        := "";
			pf0_tph_cap_enable                                  : string                        := "";
			pf0_tph_req_cap_int_vec                             : string                        := "";
			pf0_tph_req_cap_int_vec_vfcomm_cs2                  : string                        := "";
			pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2           : string                        := "";
			pf0_tph_req_cap_st_table_loc_1                      : string                        := "";
			pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2           : string                        := "";
			pf0_tph_req_cap_st_table_size                       : integer                       := 0;
			pf0_tph_req_cap_st_table_size_vfcomm_cs2            : integer                       := 0;
			pf0_tph_req_device_spec                             : string                        := "";
			pf0_tph_req_device_spec_vfcomm_cs2                  : string                        := "";
			pf0_exvf_tph_cap_enable                             : string                        := "";
			exvf_tph_sttablelocation_pf0                        : integer                       := 0;
			exvf_tph_sttablesize_pf0                            : integer                       := 0;
			pf1_tph_cap_enable                                  : string                        := "";
			pf1_tph_req_cap_int_vec                             : string                        := "";
			pf1_tph_req_cap_int_vec_vfcomm_cs2                  : string                        := "";
			pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2           : string                        := "";
			pf1_tph_req_cap_st_table_loc_1                      : string                        := "";
			pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2           : string                        := "";
			pf1_tph_req_cap_st_table_size                       : integer                       := 0;
			pf1_tph_req_cap_st_table_size_vfcomm_cs2            : integer                       := 0;
			pf1_tph_req_device_spec                             : string                        := "";
			pf1_tph_req_device_spec_vfcomm_cs2                  : string                        := "";
			pf1_exvf_tph_cap_enable                             : string                        := "";
			exvf_tph_sttablelocation_pf1                        : integer                       := 0;
			exvf_tph_sttablesize_pf1                            : integer                       := 0;
			pf2_tph_cap_enable                                  : string                        := "";
			pf2_tph_req_cap_int_vec                             : string                        := "";
			pf2_tph_req_cap_int_vec_vfcomm_cs2                  : string                        := "";
			pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2           : string                        := "";
			pf2_tph_req_cap_st_table_loc_1                      : string                        := "";
			pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2           : string                        := "";
			pf2_tph_req_cap_st_table_size                       : integer                       := 0;
			pf2_tph_req_cap_st_table_size_vfcomm_cs2            : integer                       := 0;
			pf2_tph_req_device_spec                             : string                        := "";
			pf2_tph_req_device_spec_vfcomm_cs2                  : string                        := "";
			pf2_exvf_tph_cap_enable                             : string                        := "";
			exvf_tph_sttablelocation_pf2                        : integer                       := 0;
			exvf_tph_sttablesize_pf2                            : integer                       := 0;
			pf3_tph_cap_enable                                  : string                        := "";
			pf3_tph_req_cap_int_vec                             : string                        := "";
			pf3_tph_req_cap_int_vec_vfcomm_cs2                  : string                        := "";
			pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2           : string                        := "";
			pf3_tph_req_cap_st_table_loc_1                      : string                        := "";
			pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2           : string                        := "";
			pf3_tph_req_cap_st_table_size                       : integer                       := 0;
			pf3_tph_req_cap_st_table_size_vfcomm_cs2            : integer                       := 0;
			pf3_tph_req_device_spec                             : string                        := "";
			pf3_tph_req_device_spec_vfcomm_cs2                  : string                        := "";
			pf3_exvf_tph_cap_enable                             : string                        := "";
			exvf_tph_sttablelocation_pf3                        : integer                       := 0;
			exvf_tph_sttablesize_pf3                            : integer                       := 0;
			pf0_acs_cap_enable                                  : string                        := "";
			pf0_exvf_acs_cap_enable                             : string                        := "";
			pf0_acs_cap_acs_src_valid                           : string                        := "";
			pf0_acs_cap_acs_at_block                            : string                        := "";
			pf0_acs_cap_acs_p2p_req_redirect                    : string                        := "";
			pf0_acs_cap_acs_p2p_cpl_redirect                    : string                        := "";
			pf0_acs_cap_acs_usp_forwarding                      : string                        := "";
			pf0_acs_cap_acs_p2p_egress_control                  : string                        := "";
			pf0_acs_cap_acs_egress_ctrl_size                    : integer                       := 0;
			pf0_acs_cap_acs_direct_translated_p2p               : string                        := "";
			pf1_acs_cap_enable                                  : string                        := "";
			pf1_exvf_acs_cap_enable                             : string                        := "";
			pf1_acs_cap_acs_src_valid                           : string                        := "";
			pf1_acs_cap_acs_at_block                            : string                        := "";
			pf1_acs_cap_acs_p2p_req_redirect                    : string                        := "";
			pf1_acs_cap_acs_p2p_cpl_redirect                    : string                        := "";
			pf1_acs_cap_acs_usp_forwarding                      : string                        := "";
			pf1_acs_cap_acs_p2p_egress_control                  : string                        := "";
			pf1_acs_cap_acs_egress_ctrl_size                    : integer                       := 0;
			pf1_acs_cap_acs_direct_translated_p2p               : string                        := "";
			pf2_acs_cap_enable                                  : string                        := "";
			pf2_exvf_acs_cap_enable                             : string                        := "";
			pf2_acs_cap_acs_src_valid                           : string                        := "";
			pf2_acs_cap_acs_at_block                            : string                        := "";
			pf2_acs_cap_acs_p2p_req_redirect                    : string                        := "";
			pf2_acs_cap_acs_p2p_cpl_redirect                    : string                        := "";
			pf2_acs_cap_acs_usp_forwarding                      : string                        := "";
			pf2_acs_cap_acs_p2p_egress_control                  : string                        := "";
			pf2_acs_cap_acs_egress_ctrl_size                    : integer                       := 0;
			pf2_acs_cap_acs_direct_translated_p2p               : string                        := "";
			pf3_acs_cap_enable                                  : string                        := "";
			pf3_exvf_acs_cap_enable                             : string                        := "";
			pf3_acs_cap_acs_src_valid                           : string                        := "";
			pf3_acs_cap_acs_at_block                            : string                        := "";
			pf3_acs_cap_acs_p2p_req_redirect                    : string                        := "";
			pf3_acs_cap_acs_p2p_cpl_redirect                    : string                        := "";
			pf3_acs_cap_acs_usp_forwarding                      : string                        := "";
			pf3_acs_cap_acs_p2p_egress_control                  : string                        := "";
			pf3_acs_cap_acs_egress_ctrl_size                    : integer                       := 0;
			pf3_acs_cap_acs_direct_translated_p2p               : string                        := "";
			pf0_virtio_en                                       : string                        := "";
			pf1_virtio_en                                       : string                        := "";
			pf2_virtio_en                                       : string                        := "";
			pf3_virtio_en                                       : string                        := "";
			pf0_exvf_virtio_en                                  : string                        := "";
			pf1_exvf_virtio_en                                  : string                        := "";
			pf2_exvf_virtio_en                                  : string                        := "";
			pf3_exvf_virtio_en                                  : string                        := "";
			pf0_pci_type0_device_id                             : integer                       := 0;
			pf0_pci_type0_vendor_id                             : integer                       := 0;
			pf0_revision_id                                     : integer                       := 0;
			pf0_base_class_code                                 : integer                       := 0;
			pf0_subclass_code                                   : integer                       := 0;
			pf0_program_interface                               : integer                       := 0;
			pf0_subsys_vendor_id                                : integer                       := 0;
			pf0_subsys_dev_id                                   : integer                       := 0;
			pf0_sriov_vf_device_id                              : integer                       := 0;
			exvf_subsysid_pf0                                   : integer                       := 0;
			pf1_pci_type0_vendor_id                             : integer                       := 0;
			pf1_pci_type0_device_id                             : integer                       := 0;
			pf1_revision_id                                     : integer                       := 0;
			pf1_base_class_code                                 : integer                       := 0;
			pf1_subclass_code                                   : integer                       := 0;
			pf1_program_interface                               : integer                       := 0;
			pf1_subsys_vendor_id                                : integer                       := 0;
			pf1_subsys_dev_id                                   : integer                       := 0;
			pf1_sriov_vf_device_id                              : integer                       := 0;
			exvf_subsysid_pf1                                   : integer                       := 0;
			pf2_pci_type0_vendor_id                             : integer                       := 0;
			pf2_pci_type0_device_id                             : integer                       := 0;
			pf2_revision_id                                     : integer                       := 0;
			pf2_base_class_code                                 : integer                       := 0;
			pf2_subclass_code                                   : integer                       := 0;
			pf2_program_interface                               : integer                       := 0;
			pf2_subsys_vendor_id                                : integer                       := 0;
			pf2_subsys_dev_id                                   : integer                       := 0;
			pf2_sriov_vf_device_id                              : integer                       := 0;
			exvf_subsysid_pf2                                   : integer                       := 0;
			pf3_pci_type0_vendor_id                             : integer                       := 0;
			pf3_pci_type0_device_id                             : integer                       := 0;
			pf3_revision_id                                     : integer                       := 0;
			pf3_base_class_code                                 : integer                       := 0;
			pf3_subclass_code                                   : integer                       := 0;
			pf3_program_interface                               : integer                       := 0;
			pf3_subsys_vendor_id                                : integer                       := 0;
			pf3_subsys_dev_id                                   : integer                       := 0;
			pf3_sriov_vf_device_id                              : integer                       := 0;
			exvf_subsysid_pf3                                   : integer                       := 0;
			vsec_select                                         : string                        := "";
			pf0_user_vsec_cap_enable                            : string                        := "";
			pf1_user_vsec_cap_enable                            : string                        := "";
			pf2_user_vsec_cap_enable                            : string                        := "";
			pf3_user_vsec_cap_enable                            : string                        := "";
			vsec_next_offset                                    : integer                       := 0;
			pf1_user_vsec_offset                                : integer                       := 0;
			pf2_user_vsec_offset                                : integer                       := 0;
			pf3_user_vsec_offset                                : integer                       := 0;
			cvp_vendor_specific_header_id                       : integer                       := 0;
			drop_vendor0_msg                                    : string                        := "";
			drop_vendor1_msg                                    : string                        := "";
			pf0_int_pin                                         : string                        := "";
			pf1_int_pin                                         : string                        := "";
			pf2_int_pin                                         : string                        := "";
			pf3_int_pin                                         : string                        := "";
			dtk_mode_en                                         : string                        := "";
			ecrc_strip                                          : string                        := "";
			pf0_port_logic_fast_link_mode                       : string                        := "";
			pf0_prefetch_decode                                 : string                        := "";
			pcie_pcs_mode                                       : string                        := "";
			sm_hssi_pcie_pcs_clk_mux_0_sel                      : string                        := "";
			sm_hssi_pcie_pcs_clk_mux_1_sel                      : string                        := "";
			sm_hssi_pcie_pcs_clk_mux_2_sel                      : string                        := "";
			sm_hssi_pcie_pcs_clk_mux_3_sel                      : string                        := "";
			sm_hssi_pcie_pcs_hps_clkmux_0_sel                   : string                        := "";
			sm_hssi_pcie_pcs_rst_mux_0_sel                      : string                        := "";
			sm_hssi_pcie_pcs_rst_mux_1_sel                      : string                        := "";
			sm_hssi_pcie_pcs_rst_mux_2_sel                      : string                        := "";
			sm_hssi_pcie_pcs_rst_mux_3_sel                      : string                        := "";
			sm_hssi_pcie_pcs_tx_mux_0_sel                       : string                        := "";
			sm_hssi_pcie_pcs_tx_mux_1_sel                       : string                        := "";
			sm_hssi_pcie_pcs_tx_mux_2_sel                       : string                        := "";
			sm_hssi_pcie_pcs_tx_mux_3_sel                       : string                        := "";
			sm_hssi_pcie_pcs_hps_demux_0_sel                    : string                        := "";
			sm_hssi_pcie_pcs_hps_mux_0_sel                      : string                        := "";
			sm_hssi_pcie_pcs_rx_demux_0_sel                     : string                        := "";
			sm_hssi_pcie_pcs_rx_demux_1_sel                     : string                        := "";
			sm_hssi_pcie_pcs_rx_demux_2_sel                     : string                        := "";
			sm_hssi_pcie_pcs_rx_demux_3_sel                     : string                        := "";
			sm_hssi_pcie_clk_mux_0_sel                          : string                        := "";
			sm_hssi_pcie_data_mux_0_sel                         : string                        := "";
			sm_hssi_pld_chnl_dp_0_dr_enabled                    : string                        := "";
			sm_hssi_pld_chnl_dp_0_duplex_mode                   : string                        := "";
			sm_hssi_pld_chnl_dp_0_pld_channel_identifier        : string                        := "";
			sm_hssi_pld_chnl_dp_0_rx_clkout1_divider            : string                        := "";
			sm_hssi_pld_chnl_dp_0_rx_clkout2_divider            : string                        := "";
			sm_hssi_pld_chnl_dp_0_rx_en                         : string                        := "";
			sm_hssi_pld_chnl_dp_0_rx_fifo_mode                  : string                        := "";
			sm_hssi_pld_chnl_dp_0_rx_fifo_width                 : string                        := "";
			sm_hssi_pld_chnl_dp_0_rx_fifo_wr_clk_hz             : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			sm_hssi_pld_chnl_dp_0_rx_user1_clk_dynamic_mux      : string                        := "";
			sm_hssi_pld_chnl_dp_0_rx_user2_clk_dynamic_mux      : string                        := "";
			sm_hssi_pld_chnl_dp_0_sup_mode                      : string                        := "";
			sm_hssi_pld_chnl_dp_0_tx_clkout1_divider            : string                        := "";
			sm_hssi_pld_chnl_dp_0_tx_clkout2_divider            : string                        := "";
			sm_hssi_pld_chnl_dp_0_tx_en                         : string                        := "";
			sm_hssi_pld_chnl_dp_0_tx_fifo_mode                  : string                        := "";
			sm_hssi_pld_chnl_dp_0_tx_fifo_rd_clk_hz             : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			sm_hssi_pld_chnl_dp_0_tx_fifo_width                 : string                        := "";
			sm_hssi_pld_chnl_dp_0_tx_user1_clk_dynamic_mux      : string                        := "";
			sm_hssi_pld_chnl_dp_0_tx_user2_clk_dynamic_mux      : string                        := "";
			sm_hssi_pld_chnl_dp_0_vc_rx_pldif_wm_en             : string                        := "";
			sm_pld_rx_mux_0_sel                                 : string                        := "";
			sm_pld_tx_demux_0_sel                               : string                        := "";
			sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_sel           : string                        := "";
			sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_sel           : string                        := ""
		);
		port (
			i_hio_txdata                                         : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*80)-1 downto 0)  := (others => 'X'); -- data
			i_hio_txdata_extra                                   : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*10)-1 downto 0)  := (others => 'X'); -- data
			i_hio_txdata_fifo_wr_en                              : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- data
			i_hio_rxdata_fifo_rd_en                              : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- data
			i_hio_ptp_rst_n                                      : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_ehip_rx_rst_n                                  : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_ehip_tx_rst_n                                  : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_ehip_signal_ok                                 : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_sfreeze_2_r03f_rx_mac_srfz_n                   : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_sfreeze_3_c2f_tx_deskew_srfz_n                 : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n                   : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rstfec_fec_rx_rst_n                            : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rstfec_fec_tx_rst_n                            : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rstfec_fec_csr_ret                             : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rstfec_rx_fec_sfrz_n                           : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rstfec_tx_fec_sfrz_n                           : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rstxcvrif_xcvrif_rx_rst_n                      : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rstxcvrif_xcvrif_tx_rst_n                      : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rstxcvrif_xcvrif_signal_ok                     : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rstxcvrif_rx_xcvrif_sfrz_n                     : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rstxcvrif_tx_xcvrif_sfrz_n                     : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rst_pld_clrhip                                 : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rst_pld_clrpcs                                 : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rst_pld_perstn                                 : in  std_logic                                                     := 'X';             -- reset
			i_hio_rst_pld_ready                                  : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rst_pld_adapter_rx_pld_rst_n                   : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rst_pld_adapter_tx_pld_rst_n                   : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rst_ux_rx_pma_rst_n                            : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rst_ux_rx_sfrz                                 : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_rst_ux_tx_pma_rst_n                            : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_pld_reset_clk_row                              : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0)   := (others => 'X'); -- reset
			i_hio_uxquad_async                                   : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*80)-1 downto 0)  := (others => 'X'); -- data
			i_hio_uxquad_async_pcie_mux                          : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*80)-1 downto 0)  := (others => 'X'); -- data
			rx_serial_n                                          : in  std_logic_vector((hal_num_of_lanes_hwtcl*1)-1 downto 0)       := (others => 'X'); -- data
			rx_serial_p                                          : in  std_logic_vector((hal_num_of_lanes_hwtcl*1)-1 downto 0)       := (others => 'X'); -- data
			o_hio_txdata_fifo_wr_empty                           : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- data
			o_hio_txdata_fifo_wr_pempty                          : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- data
			o_hio_txdata_fifo_wr_full                            : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- data
			o_hio_txdata_fifo_wr_pfull                           : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- data
			o_hio_rxdata                                         : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*80)-1 downto 0);                     -- data
			o_hio_rxdata_extra                                   : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*10)-1 downto 0);                     -- data
			o_hio_rxdata_fifo_rd_empty                           : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- data
			o_hio_rxdata_fifo_rd_pempty                          : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- data
			o_hio_rxdata_fifo_rd_full                            : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- data
			o_hio_rxdata_fifo_rd_pfull                           : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- data
			o_hio_rstepcs_rx_pcs_fully_aligned                   : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- reset
			o_hio_rstfec_fec_rx_rdy_n                            : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- reset
			o_hio_rst_flux0_cpi_cmn_busy                         : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- reset
			o_hio_rst_oflux_rx_srds_rdy                          : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- reset
			o_hio_rst_ux_all_synthlockstatus                     : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- reset
			o_hio_rst_ux_octl_pcs_rxstatus                       : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- reset
			o_hio_rst_ux_octl_pcs_txstatus                       : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- reset
			o_hio_rst_ux_rxcdrlock2data                          : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- reset
			o_hio_rst_ux_rxcdrlockstatus                         : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*1)-1 downto 0);                      -- reset
			o_hio_uxquad_async                                   : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*50)-1 downto 0);                     -- data
			tx_serial_p                                          : out std_logic_vector((hal_num_of_lanes_hwtcl*1)-1 downto 0);                          -- data
			tx_serial_n                                          : out std_logic_vector((hal_num_of_lanes_hwtcl*1)-1 downto 0);                          -- data
			i_hio_txdata_async                                   : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*100)-1 downto 0) := (others => 'X'); -- data
			i_hio_txdata_direct                                  : in  std_logic_vector(((hal_num_of_lanes_hwtcl+1)*10)-1 downto 0)  := (others => 'X'); -- data
			o_hio_rxdata_async                                   : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*100)-1 downto 0);                    -- data
			o_hio_rxdata_direct                                  : out std_logic_vector(((hal_num_of_lanes_hwtcl+1)*10)-1 downto 0);                     -- data
			ioack_cdrdiv_left_ux_bidir_out                       : out std_logic_vector((hal_num_of_lanes_hwtcl*1)-1 downto 0);                          -- data
			i_refclk_tx_p                                        : in  std_logic                                                     := 'X';             -- clk
			i_syspll_c0_clk                                      : in  std_logic                                                     := 'X';             -- clk
			i_syspll_c1_clk                                      : in  std_logic                                                     := 'X';             -- clk
			i_syspll_c2_clk                                      : in  std_logic                                                     := 'X';             -- clk
			i_flux_clk                                           : in  std_logic                                                     := 'X';             -- clk
			i_flux_clk_1                                         : in  std_logic                                                     := 'X';             -- clk
			i_refclk_rx_p                                        : in  std_logic                                                     := 'X';             -- clk
			i_ss_vccl_syspll_locked                              : in  std_logic                                                     := 'X';             -- clk
			o_hio_pcie_user_rx_clk1_clk                          : out std_logic;                                                                        -- clk
			o_hio_pcie_user_rx_clk2_clk                          : out std_logic;                                                                        -- clk
			o_hio_pcie_user_tx_clk1_clk                          : out std_logic;                                                                        -- clk
			o_hio_pcie_user_tx_clk2_clk                          : out std_logic;                                                                        -- clk
			i_pin_perst_n                                        : in  std_logic                                                     := 'X';             -- i_pin_perst_n
			i_pin_perst_n_1                                      : in  std_logic                                                     := 'X';             -- i_pin_perst_n_1
			i_hio_ch0_lavmm_clk                                  : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch0_lavmm_rstn                                 : in  std_logic                                                     := 'X';             -- reset
			i_hio_ch0_lavmm_addr                                 : in  std_logic_vector(20 downto 0)                                 := (others => 'X'); -- address
			i_hio_ch0_lavmm_be                                   : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- byteenable
			o_hio_ch0_lavmm_rdata_valid                          : out std_logic;                                                                        -- readdatavalid
			i_hio_ch0_lavmm_read                                 : in  std_logic                                                     := 'X';             -- read
			i_hio_ch0_lavmm_write                                : in  std_logic                                                     := 'X';             -- write
			o_hio_ch0_lavmm_rdata                                : out std_logic_vector(31 downto 0);                                                    -- readdata
			i_hio_ch0_lavmm_wdata                                : in  std_logic_vector(31 downto 0)                                 := (others => 'X'); -- writedata
			o_hio_ch0_lavmm_waitreq                              : out std_logic;                                                                        -- waitrequest
			i_hio_ch0_pld_rx_clk_in_row_clk                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch0_pld_tx_clk_in_row_clk                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch0_det_lat_rx_dl_clk                          : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch0_det_lat_rx_mux_select                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch0_det_lat_rx_sclk_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch0_det_lat_rx_sclk_gen_clk                    : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch0_det_lat_rx_trig_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch0_det_lat_sampling_clk                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch0_det_lat_tx_dl_clk                          : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch0_det_lat_tx_mux_select                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch0_det_lat_tx_sclk_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch0_det_lat_tx_sclk_gen_clk                    : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch0_det_lat_tx_trig_flop                       : in  std_logic                                                     := 'X';             -- clk
			o_hio_ch0_user_rx_clk1_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch0_user_rx_clk2_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch0_user_tx_clk1_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch0_user_tx_clk2_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch0_ux_chnl_refclk_mux                         : out std_logic;                                                                        -- clk
			o_hio_ch0_det_lat_rx_async_dl_sync                   : out std_logic;                                                                        -- clk
			o_hio_ch0_det_lat_rx_async_pulse                     : out std_logic;                                                                        -- clk
			o_hio_ch0_det_lat_rx_async_sample_sync               : out std_logic;                                                                        -- clk
			o_hio_ch0_det_lat_rx_sclk_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch0_det_lat_rx_trig_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch0_det_lat_tx_async_dl_sync                   : out std_logic;                                                                        -- clk
			o_hio_ch0_det_lat_tx_async_pulse                     : out std_logic;                                                                        -- clk
			o_hio_ch0_det_lat_tx_async_sample_sync               : out std_logic;                                                                        -- clk
			o_hio_ch0_det_lat_tx_sclk_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch0_det_lat_tx_trig_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch0_xcvrif_rx_latency_pulse                    : out std_logic;                                                                        -- clk
			o_hio_ch0_xcvrif_tx_latency_pulse                    : out std_logic;                                                                        -- clk
			i_hio_ch1_lavmm_clk                                  : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch1_lavmm_rstn                                 : in  std_logic                                                     := 'X';             -- reset
			i_hio_ch1_lavmm_addr                                 : in  std_logic_vector(20 downto 0)                                 := (others => 'X'); -- address
			i_hio_ch1_lavmm_be                                   : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- byteenable
			o_hio_ch1_lavmm_rdata_valid                          : out std_logic;                                                                        -- readdatavalid
			i_hio_ch1_lavmm_read                                 : in  std_logic                                                     := 'X';             -- read
			i_hio_ch1_lavmm_write                                : in  std_logic                                                     := 'X';             -- write
			o_hio_ch1_lavmm_rdata                                : out std_logic_vector(31 downto 0);                                                    -- readdata
			i_hio_ch1_lavmm_wdata                                : in  std_logic_vector(31 downto 0)                                 := (others => 'X'); -- writedata
			o_hio_ch1_lavmm_waitreq                              : out std_logic;                                                                        -- waitrequest
			i_hio_ch1_pld_rx_clk_in_row_clk                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch1_pld_tx_clk_in_row_clk                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch1_det_lat_rx_dl_clk                          : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch1_det_lat_rx_mux_select                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch1_det_lat_rx_sclk_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch1_det_lat_rx_sclk_gen_clk                    : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch1_det_lat_rx_trig_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch1_det_lat_sampling_clk                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch1_det_lat_tx_dl_clk                          : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch1_det_lat_tx_mux_select                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch1_det_lat_tx_sclk_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch1_det_lat_tx_sclk_gen_clk                    : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch1_det_lat_tx_trig_flop                       : in  std_logic                                                     := 'X';             -- clk
			o_hio_ch1_user_rx_clk1_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch1_user_rx_clk2_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch1_user_tx_clk1_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch1_user_tx_clk2_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch1_ux_chnl_refclk_mux                         : out std_logic;                                                                        -- clk
			o_hio_ch1_det_lat_rx_async_dl_sync                   : out std_logic;                                                                        -- clk
			o_hio_ch1_det_lat_rx_async_pulse                     : out std_logic;                                                                        -- clk
			o_hio_ch1_det_lat_rx_async_sample_sync               : out std_logic;                                                                        -- clk
			o_hio_ch1_det_lat_rx_sclk_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch1_det_lat_rx_trig_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch1_det_lat_tx_async_dl_sync                   : out std_logic;                                                                        -- clk
			o_hio_ch1_det_lat_tx_async_pulse                     : out std_logic;                                                                        -- clk
			o_hio_ch1_det_lat_tx_async_sample_sync               : out std_logic;                                                                        -- clk
			o_hio_ch1_det_lat_tx_sclk_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch1_det_lat_tx_trig_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch1_xcvrif_rx_latency_pulse                    : out std_logic;                                                                        -- clk
			o_hio_ch1_xcvrif_tx_latency_pulse                    : out std_logic;                                                                        -- clk
			i_hio_ch2_lavmm_clk                                  : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch2_lavmm_rstn                                 : in  std_logic                                                     := 'X';             -- reset
			i_hio_ch2_lavmm_addr                                 : in  std_logic_vector(20 downto 0)                                 := (others => 'X'); -- address
			i_hio_ch2_lavmm_be                                   : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- byteenable
			o_hio_ch2_lavmm_rdata_valid                          : out std_logic;                                                                        -- readdatavalid
			i_hio_ch2_lavmm_read                                 : in  std_logic                                                     := 'X';             -- read
			i_hio_ch2_lavmm_write                                : in  std_logic                                                     := 'X';             -- write
			o_hio_ch2_lavmm_rdata                                : out std_logic_vector(31 downto 0);                                                    -- readdata
			i_hio_ch2_lavmm_wdata                                : in  std_logic_vector(31 downto 0)                                 := (others => 'X'); -- writedata
			o_hio_ch2_lavmm_waitreq                              : out std_logic;                                                                        -- waitrequest
			i_hio_ch2_pld_rx_clk_in_row_clk                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch2_pld_tx_clk_in_row_clk                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch2_det_lat_rx_dl_clk                          : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch2_det_lat_rx_mux_select                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch2_det_lat_rx_sclk_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch2_det_lat_rx_sclk_gen_clk                    : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch2_det_lat_rx_trig_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch2_det_lat_sampling_clk                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch2_det_lat_tx_dl_clk                          : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch2_det_lat_tx_mux_select                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch2_det_lat_tx_sclk_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch2_det_lat_tx_sclk_gen_clk                    : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch2_det_lat_tx_trig_flop                       : in  std_logic                                                     := 'X';             -- clk
			o_hio_ch2_user_rx_clk1_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch2_user_rx_clk2_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch2_user_tx_clk1_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch2_user_tx_clk2_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch2_ux_chnl_refclk_mux                         : out std_logic;                                                                        -- clk
			o_hio_ch2_det_lat_rx_async_dl_sync                   : out std_logic;                                                                        -- clk
			o_hio_ch2_det_lat_rx_async_pulse                     : out std_logic;                                                                        -- clk
			o_hio_ch2_det_lat_rx_async_sample_sync               : out std_logic;                                                                        -- clk
			o_hio_ch2_det_lat_rx_sclk_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch2_det_lat_rx_trig_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch2_det_lat_tx_async_dl_sync                   : out std_logic;                                                                        -- clk
			o_hio_ch2_det_lat_tx_async_pulse                     : out std_logic;                                                                        -- clk
			o_hio_ch2_det_lat_tx_async_sample_sync               : out std_logic;                                                                        -- clk
			o_hio_ch2_det_lat_tx_sclk_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch2_det_lat_tx_trig_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch2_xcvrif_rx_latency_pulse                    : out std_logic;                                                                        -- clk
			o_hio_ch2_xcvrif_tx_latency_pulse                    : out std_logic;                                                                        -- clk
			i_hio_ch3_lavmm_clk                                  : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch3_lavmm_rstn                                 : in  std_logic                                                     := 'X';             -- reset
			i_hio_ch3_lavmm_addr                                 : in  std_logic_vector(20 downto 0)                                 := (others => 'X'); -- address
			i_hio_ch3_lavmm_be                                   : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- byteenable
			o_hio_ch3_lavmm_rdata_valid                          : out std_logic;                                                                        -- readdatavalid
			i_hio_ch3_lavmm_read                                 : in  std_logic                                                     := 'X';             -- read
			i_hio_ch3_lavmm_write                                : in  std_logic                                                     := 'X';             -- write
			o_hio_ch3_lavmm_rdata                                : out std_logic_vector(31 downto 0);                                                    -- readdata
			i_hio_ch3_lavmm_wdata                                : in  std_logic_vector(31 downto 0)                                 := (others => 'X'); -- writedata
			o_hio_ch3_lavmm_waitreq                              : out std_logic;                                                                        -- waitrequest
			i_hio_ch3_pld_rx_clk_in_row_clk                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch3_pld_tx_clk_in_row_clk                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch3_det_lat_rx_dl_clk                          : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch3_det_lat_rx_mux_select                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch3_det_lat_rx_sclk_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch3_det_lat_rx_sclk_gen_clk                    : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch3_det_lat_rx_trig_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch3_det_lat_sampling_clk                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch3_det_lat_tx_dl_clk                          : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch3_det_lat_tx_mux_select                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch3_det_lat_tx_sclk_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch3_det_lat_tx_sclk_gen_clk                    : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch3_det_lat_tx_trig_flop                       : in  std_logic                                                     := 'X';             -- clk
			o_hio_ch3_user_rx_clk1_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch3_user_rx_clk2_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch3_user_tx_clk1_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch3_user_tx_clk2_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch3_ux_chnl_refclk_mux                         : out std_logic;                                                                        -- clk
			o_hio_ch3_det_lat_rx_async_dl_sync                   : out std_logic;                                                                        -- clk
			o_hio_ch3_det_lat_rx_async_pulse                     : out std_logic;                                                                        -- clk
			o_hio_ch3_det_lat_rx_async_sample_sync               : out std_logic;                                                                        -- clk
			o_hio_ch3_det_lat_rx_sclk_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch3_det_lat_rx_trig_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch3_det_lat_tx_async_dl_sync                   : out std_logic;                                                                        -- clk
			o_hio_ch3_det_lat_tx_async_pulse                     : out std_logic;                                                                        -- clk
			o_hio_ch3_det_lat_tx_async_sample_sync               : out std_logic;                                                                        -- clk
			o_hio_ch3_det_lat_tx_sclk_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch3_det_lat_tx_trig_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch3_xcvrif_rx_latency_pulse                    : out std_logic;                                                                        -- clk
			o_hio_ch3_xcvrif_tx_latency_pulse                    : out std_logic;                                                                        -- clk
			i_hio_ch4_lavmm_clk                                  : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch4_lavmm_rstn                                 : in  std_logic                                                     := 'X';             -- reset
			i_hio_ch4_lavmm_addr                                 : in  std_logic_vector(20 downto 0)                                 := (others => 'X'); -- address
			i_hio_ch4_lavmm_be                                   : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- byteenable
			o_hio_ch4_lavmm_rdata_valid                          : out std_logic;                                                                        -- readdatavalid
			i_hio_ch4_lavmm_read                                 : in  std_logic                                                     := 'X';             -- read
			i_hio_ch4_lavmm_write                                : in  std_logic                                                     := 'X';             -- write
			o_hio_ch4_lavmm_rdata                                : out std_logic_vector(31 downto 0);                                                    -- readdata
			i_hio_ch4_lavmm_wdata                                : in  std_logic_vector(31 downto 0)                                 := (others => 'X'); -- writedata
			o_hio_ch4_lavmm_waitreq                              : out std_logic;                                                                        -- waitrequest
			i_hio_ch4_pld_rx_clk_in_row_clk                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch4_pld_tx_clk_in_row_clk                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch4_det_lat_rx_dl_clk                          : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch4_det_lat_rx_mux_select                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch4_det_lat_rx_sclk_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch4_det_lat_rx_sclk_gen_clk                    : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch4_det_lat_rx_trig_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch4_det_lat_sampling_clk                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch4_det_lat_tx_dl_clk                          : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch4_det_lat_tx_mux_select                      : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch4_det_lat_tx_sclk_flop                       : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch4_det_lat_tx_sclk_gen_clk                    : in  std_logic                                                     := 'X';             -- clk
			i_hio_ch4_det_lat_tx_trig_flop                       : in  std_logic                                                     := 'X';             -- clk
			o_hio_ch4_user_rx_clk1_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch4_user_rx_clk2_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch4_user_tx_clk1_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch4_user_tx_clk2_clk                           : out std_logic;                                                                        -- clk
			o_hio_ch4_ux_chnl_refclk_mux                         : out std_logic;                                                                        -- clk
			o_hio_ch4_det_lat_rx_async_dl_sync                   : out std_logic;                                                                        -- clk
			o_hio_ch4_det_lat_rx_async_pulse                     : out std_logic;                                                                        -- clk
			o_hio_ch4_det_lat_rx_async_sample_sync               : out std_logic;                                                                        -- clk
			o_hio_ch4_det_lat_rx_sclk_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch4_det_lat_rx_trig_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch4_det_lat_tx_async_dl_sync                   : out std_logic;                                                                        -- clk
			o_hio_ch4_det_lat_tx_async_pulse                     : out std_logic;                                                                        -- clk
			o_hio_ch4_det_lat_tx_async_sample_sync               : out std_logic;                                                                        -- clk
			o_hio_ch4_det_lat_tx_sclk_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch4_det_lat_tx_trig_sample_sync                : out std_logic;                                                                        -- clk
			o_hio_ch4_xcvrif_rx_latency_pulse                    : out std_logic;                                                                        -- clk
			o_hio_ch4_xcvrif_tx_latency_pulse                    : out std_logic;                                                                        -- clk
			i_ch5_tx_data                                        : in  std_logic_vector(79 downto 0)                                 := (others => 'X'); -- i_ch5_tx_data
			i_ch6_tx_data                                        : in  std_logic_vector(79 downto 0)                                 := (others => 'X'); -- i_ch6_tx_data
			i_ch7_tx_data                                        : in  std_logic_vector(79 downto 0)                                 := (others => 'X'); -- i_ch7_tx_data
			i_ch8_tx_data                                        : in  std_logic_vector(79 downto 0)                                 := (others => 'X'); -- i_ch8_tx_data
			o_ch5_rx_data                                        : out std_logic_vector(79 downto 0);                                                    -- o_ch5_rx_data
			o_ch6_rx_data                                        : out std_logic_vector(79 downto 0);                                                    -- o_ch6_rx_data
			o_ch7_rx_data                                        : out std_logic_vector(79 downto 0);                                                    -- o_ch7_rx_data
			o_ch8_rx_data                                        : out std_logic_vector(79 downto 0);                                                    -- o_ch8_rx_data
			i_rxpipe0_pipemode_dirfeedback                       : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe0_pipemode_dirfeedback
			i_rxpipe0_pipemode_linkevaluationfeedbackfiguremerit : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe0_pipemode_linkevaluationfeedbackfiguremerit
			i_rxpipe0_pipemode_localfs                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe0_pipemode_localfs
			i_rxpipe0_pipemode_locallf                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe0_pipemode_locallf
			i_rxpipe0_pipemode_localtxcoefficientsvalid          : in  std_logic                                                     := 'X';             -- i_rxpipe0_pipemode_localtxcoefficientsvalid
			i_rxpipe0_pipemode_localtxpresetcoefficients         : in  std_logic_vector(17 downto 0)                                 := (others => 'X'); -- i_rxpipe0_pipemode_localtxpresetcoefficients
			i_rxpipe0_pipemode_p2m_bus                           : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe0_pipemode_p2m_bus
			i_rxpipe0_pipemode_pclkchangeok                      : in  std_logic                                                     := 'X';             -- i_rxpipe0_pipemode_pclkchangeok
			i_rxpipe0_pipemode_phystatus                         : in  std_logic                                                     := 'X';             -- i_rxpipe0_pipemode_phystatus
			i_rxpipe0_pipemode_rxdata                            : in  std_logic_vector(39 downto 0)                                 := (others => 'X'); -- i_rxpipe0_pipemode_rxdata
			i_rxpipe0_pipemode_rxdatak                           : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe0_pipemode_rxdatak
			i_rxpipe0_pipemode_rxdatavalid                       : in  std_logic                                                     := 'X';             -- i_rxpipe0_pipemode_rxdatavalid
			i_rxpipe0_pipemode_rxelecidlea                       : in  std_logic                                                     := 'X';             -- i_rxpipe0_pipemode_rxelecidlea
			i_rxpipe0_pipemode_rxstandbystatus                   : in  std_logic                                                     := 'X';             -- i_rxpipe0_pipemode_rxstandbystatus
			i_rxpipe0_pipemode_rxstartblock                      : in  std_logic                                                     := 'X';             -- i_rxpipe0_pipemode_rxstartblock
			i_rxpipe0_pipemode_rxstatus                          : in  std_logic_vector(2 downto 0)                                  := (others => 'X'); -- i_rxpipe0_pipemode_rxstatus
			i_rxpipe0_pipemode_rxsyncheader                      : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe0_pipemode_rxsyncheader
			i_rxpipe0_pipemode_rxvalid                           : in  std_logic                                                     := 'X';             -- i_rxpipe0_pipemode_rxvalid
			i_rxpipe1_pipemode_dirfeedback                       : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe1_pipemode_dirfeedback
			i_rxpipe1_pipemode_linkevaluationfeedbackfiguremerit : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe1_pipemode_linkevaluationfeedbackfiguremerit
			i_rxpipe1_pipemode_localfs                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe1_pipemode_localfs
			i_rxpipe1_pipemode_locallf                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe1_pipemode_locallf
			i_rxpipe1_pipemode_localtxcoefficientsvalid          : in  std_logic                                                     := 'X';             -- i_rxpipe1_pipemode_localtxcoefficientsvalid
			i_rxpipe1_pipemode_localtxpresetcoefficients         : in  std_logic_vector(17 downto 0)                                 := (others => 'X'); -- i_rxpipe1_pipemode_localtxpresetcoefficients
			i_rxpipe1_pipemode_p2m_bus                           : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe1_pipemode_p2m_bus
			i_rxpipe1_pipemode_pclkchangeok                      : in  std_logic                                                     := 'X';             -- i_rxpipe1_pipemode_pclkchangeok
			i_rxpipe1_pipemode_phystatus                         : in  std_logic                                                     := 'X';             -- i_rxpipe1_pipemode_phystatus
			i_rxpipe1_pipemode_rxdata                            : in  std_logic_vector(39 downto 0)                                 := (others => 'X'); -- i_rxpipe1_pipemode_rxdata
			i_rxpipe1_pipemode_rxdatak                           : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe1_pipemode_rxdatak
			i_rxpipe1_pipemode_rxdatavalid                       : in  std_logic                                                     := 'X';             -- i_rxpipe1_pipemode_rxdatavalid
			i_rxpipe1_pipemode_rxelecidlea                       : in  std_logic                                                     := 'X';             -- i_rxpipe1_pipemode_rxelecidlea
			i_rxpipe1_pipemode_rxstandbystatus                   : in  std_logic                                                     := 'X';             -- i_rxpipe1_pipemode_rxstandbystatus
			i_rxpipe1_pipemode_rxstartblock                      : in  std_logic                                                     := 'X';             -- i_rxpipe1_pipemode_rxstartblock
			i_rxpipe1_pipemode_rxstatus                          : in  std_logic_vector(2 downto 0)                                  := (others => 'X'); -- i_rxpipe1_pipemode_rxstatus
			i_rxpipe1_pipemode_rxsyncheader                      : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe1_pipemode_rxsyncheader
			i_rxpipe1_pipemode_rxvalid                           : in  std_logic                                                     := 'X';             -- i_rxpipe1_pipemode_rxvalid
			i_rxpipe2_pipemode_dirfeedback                       : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe2_pipemode_dirfeedback
			i_rxpipe2_pipemode_linkevaluationfeedbackfiguremerit : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe2_pipemode_linkevaluationfeedbackfiguremerit
			i_rxpipe2_pipemode_localfs                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe2_pipemode_localfs
			i_rxpipe2_pipemode_locallf                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe2_pipemode_locallf
			i_rxpipe2_pipemode_localtxcoefficientsvalid          : in  std_logic                                                     := 'X';             -- i_rxpipe2_pipemode_localtxcoefficientsvalid
			i_rxpipe2_pipemode_localtxpresetcoefficients         : in  std_logic_vector(17 downto 0)                                 := (others => 'X'); -- i_rxpipe2_pipemode_localtxpresetcoefficients
			i_rxpipe2_pipemode_p2m_bus                           : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe2_pipemode_p2m_bus
			i_rxpipe2_pipemode_pclkchangeok                      : in  std_logic                                                     := 'X';             -- i_rxpipe2_pipemode_pclkchangeok
			i_rxpipe2_pipemode_phystatus                         : in  std_logic                                                     := 'X';             -- i_rxpipe2_pipemode_phystatus
			i_rxpipe2_pipemode_rxdata                            : in  std_logic_vector(39 downto 0)                                 := (others => 'X'); -- i_rxpipe2_pipemode_rxdata
			i_rxpipe2_pipemode_rxdatak                           : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe2_pipemode_rxdatak
			i_rxpipe2_pipemode_rxdatavalid                       : in  std_logic                                                     := 'X';             -- i_rxpipe2_pipemode_rxdatavalid
			i_rxpipe2_pipemode_rxelecidlea                       : in  std_logic                                                     := 'X';             -- i_rxpipe2_pipemode_rxelecidlea
			i_rxpipe2_pipemode_rxstandbystatus                   : in  std_logic                                                     := 'X';             -- i_rxpipe2_pipemode_rxstandbystatus
			i_rxpipe2_pipemode_rxstartblock                      : in  std_logic                                                     := 'X';             -- i_rxpipe2_pipemode_rxstartblock
			i_rxpipe2_pipemode_rxstatus                          : in  std_logic_vector(2 downto 0)                                  := (others => 'X'); -- i_rxpipe2_pipemode_rxstatus
			i_rxpipe2_pipemode_rxsyncheader                      : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe2_pipemode_rxsyncheader
			i_rxpipe2_pipemode_rxvalid                           : in  std_logic                                                     := 'X';             -- i_rxpipe2_pipemode_rxvalid
			i_rxpipe3_pipemode_dirfeedback                       : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe3_pipemode_dirfeedback
			i_rxpipe3_pipemode_linkevaluationfeedbackfiguremerit : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe3_pipemode_linkevaluationfeedbackfiguremerit
			i_rxpipe3_pipemode_localfs                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe3_pipemode_localfs
			i_rxpipe3_pipemode_locallf                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe3_pipemode_locallf
			i_rxpipe3_pipemode_localtxcoefficientsvalid          : in  std_logic                                                     := 'X';             -- i_rxpipe3_pipemode_localtxcoefficientsvalid
			i_rxpipe3_pipemode_localtxpresetcoefficients         : in  std_logic_vector(17 downto 0)                                 := (others => 'X'); -- i_rxpipe3_pipemode_localtxpresetcoefficients
			i_rxpipe3_pipemode_p2m_bus                           : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe3_pipemode_p2m_bus
			i_rxpipe3_pipemode_pclkchangeok                      : in  std_logic                                                     := 'X';             -- i_rxpipe3_pipemode_pclkchangeok
			i_rxpipe3_pipemode_phystatus                         : in  std_logic                                                     := 'X';             -- i_rxpipe3_pipemode_phystatus
			i_rxpipe3_pipemode_rxdata                            : in  std_logic_vector(39 downto 0)                                 := (others => 'X'); -- i_rxpipe3_pipemode_rxdata
			i_rxpipe3_pipemode_rxdatak                           : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe3_pipemode_rxdatak
			i_rxpipe3_pipemode_rxdatavalid                       : in  std_logic                                                     := 'X';             -- i_rxpipe3_pipemode_rxdatavalid
			i_rxpipe3_pipemode_rxelecidlea                       : in  std_logic                                                     := 'X';             -- i_rxpipe3_pipemode_rxelecidlea
			i_rxpipe3_pipemode_rxstandbystatus                   : in  std_logic                                                     := 'X';             -- i_rxpipe3_pipemode_rxstandbystatus
			i_rxpipe3_pipemode_rxstartblock                      : in  std_logic                                                     := 'X';             -- i_rxpipe3_pipemode_rxstartblock
			i_rxpipe3_pipemode_rxstatus                          : in  std_logic_vector(2 downto 0)                                  := (others => 'X'); -- i_rxpipe3_pipemode_rxstatus
			i_rxpipe3_pipemode_rxsyncheader                      : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe3_pipemode_rxsyncheader
			i_rxpipe3_pipemode_rxvalid                           : in  std_logic                                                     := 'X';             -- i_rxpipe3_pipemode_rxvalid
			i_rxpipe4_pipemode_dirfeedback                       : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe4_pipemode_dirfeedback
			i_rxpipe4_pipemode_linkevaluationfeedbackfiguremerit : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe4_pipemode_linkevaluationfeedbackfiguremerit
			i_rxpipe4_pipemode_localfs                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe4_pipemode_localfs
			i_rxpipe4_pipemode_locallf                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe4_pipemode_locallf
			i_rxpipe4_pipemode_localtxcoefficientsvalid          : in  std_logic                                                     := 'X';             -- i_rxpipe4_pipemode_localtxcoefficientsvalid
			i_rxpipe4_pipemode_localtxpresetcoefficients         : in  std_logic_vector(17 downto 0)                                 := (others => 'X'); -- i_rxpipe4_pipemode_localtxpresetcoefficients
			i_rxpipe4_pipemode_p2m_bus                           : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe4_pipemode_p2m_bus
			i_rxpipe4_pipemode_pclkchangeok                      : in  std_logic                                                     := 'X';             -- i_rxpipe4_pipemode_pclkchangeok
			i_rxpipe4_pipemode_phystatus                         : in  std_logic                                                     := 'X';             -- i_rxpipe4_pipemode_phystatus
			i_rxpipe4_pipemode_rxdata                            : in  std_logic_vector(39 downto 0)                                 := (others => 'X'); -- i_rxpipe4_pipemode_rxdata
			i_rxpipe4_pipemode_rxdatak                           : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe4_pipemode_rxdatak
			i_rxpipe4_pipemode_rxdatavalid                       : in  std_logic                                                     := 'X';             -- i_rxpipe4_pipemode_rxdatavalid
			i_rxpipe4_pipemode_rxelecidlea                       : in  std_logic                                                     := 'X';             -- i_rxpipe4_pipemode_rxelecidlea
			i_rxpipe4_pipemode_rxstandbystatus                   : in  std_logic                                                     := 'X';             -- i_rxpipe4_pipemode_rxstandbystatus
			i_rxpipe4_pipemode_rxstartblock                      : in  std_logic                                                     := 'X';             -- i_rxpipe4_pipemode_rxstartblock
			i_rxpipe4_pipemode_rxstatus                          : in  std_logic_vector(2 downto 0)                                  := (others => 'X'); -- i_rxpipe4_pipemode_rxstatus
			i_rxpipe4_pipemode_rxsyncheader                      : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe4_pipemode_rxsyncheader
			i_rxpipe4_pipemode_rxvalid                           : in  std_logic                                                     := 'X';             -- i_rxpipe4_pipemode_rxvalid
			i_rxpipe5_pipemode_dirfeedback                       : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe5_pipemode_dirfeedback
			i_rxpipe5_pipemode_linkevaluationfeedbackfiguremerit : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe5_pipemode_linkevaluationfeedbackfiguremerit
			i_rxpipe5_pipemode_localfs                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe5_pipemode_localfs
			i_rxpipe5_pipemode_locallf                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe5_pipemode_locallf
			i_rxpipe5_pipemode_localtxcoefficientsvalid          : in  std_logic                                                     := 'X';             -- i_rxpipe5_pipemode_localtxcoefficientsvalid
			i_rxpipe5_pipemode_localtxpresetcoefficients         : in  std_logic_vector(17 downto 0)                                 := (others => 'X'); -- i_rxpipe5_pipemode_localtxpresetcoefficients
			i_rxpipe5_pipemode_p2m_bus                           : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe5_pipemode_p2m_bus
			i_rxpipe5_pipemode_pclkchangeok                      : in  std_logic                                                     := 'X';             -- i_rxpipe5_pipemode_pclkchangeok
			i_rxpipe5_pipemode_phystatus                         : in  std_logic                                                     := 'X';             -- i_rxpipe5_pipemode_phystatus
			i_rxpipe5_pipemode_rxdata                            : in  std_logic_vector(39 downto 0)                                 := (others => 'X'); -- i_rxpipe5_pipemode_rxdata
			i_rxpipe5_pipemode_rxdatak                           : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe5_pipemode_rxdatak
			i_rxpipe5_pipemode_rxdatavalid                       : in  std_logic                                                     := 'X';             -- i_rxpipe5_pipemode_rxdatavalid
			i_rxpipe5_pipemode_rxelecidlea                       : in  std_logic                                                     := 'X';             -- i_rxpipe5_pipemode_rxelecidlea
			i_rxpipe5_pipemode_rxstandbystatus                   : in  std_logic                                                     := 'X';             -- i_rxpipe5_pipemode_rxstandbystatus
			i_rxpipe5_pipemode_rxstartblock                      : in  std_logic                                                     := 'X';             -- i_rxpipe5_pipemode_rxstartblock
			i_rxpipe5_pipemode_rxstatus                          : in  std_logic_vector(2 downto 0)                                  := (others => 'X'); -- i_rxpipe5_pipemode_rxstatus
			i_rxpipe5_pipemode_rxsyncheader                      : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe5_pipemode_rxsyncheader
			i_rxpipe5_pipemode_rxvalid                           : in  std_logic                                                     := 'X';             -- i_rxpipe5_pipemode_rxvalid
			i_rxpipe6_pipemode_dirfeedback                       : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe6_pipemode_dirfeedback
			i_rxpipe6_pipemode_linkevaluationfeedbackfiguremerit : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe6_pipemode_linkevaluationfeedbackfiguremerit
			i_rxpipe6_pipemode_localfs                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe6_pipemode_localfs
			i_rxpipe6_pipemode_locallf                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe6_pipemode_locallf
			i_rxpipe6_pipemode_localtxcoefficientsvalid          : in  std_logic                                                     := 'X';             -- i_rxpipe6_pipemode_localtxcoefficientsvalid
			i_rxpipe6_pipemode_localtxpresetcoefficients         : in  std_logic_vector(17 downto 0)                                 := (others => 'X'); -- i_rxpipe6_pipemode_localtxpresetcoefficients
			i_rxpipe6_pipemode_p2m_bus                           : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe6_pipemode_p2m_bus
			i_rxpipe6_pipemode_pclkchangeok                      : in  std_logic                                                     := 'X';             -- i_rxpipe6_pipemode_pclkchangeok
			i_rxpipe6_pipemode_phystatus                         : in  std_logic                                                     := 'X';             -- i_rxpipe6_pipemode_phystatus
			i_rxpipe6_pipemode_rxdata                            : in  std_logic_vector(39 downto 0)                                 := (others => 'X'); -- i_rxpipe6_pipemode_rxdata
			i_rxpipe6_pipemode_rxdatak                           : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe6_pipemode_rxdatak
			i_rxpipe6_pipemode_rxdatavalid                       : in  std_logic                                                     := 'X';             -- i_rxpipe6_pipemode_rxdatavalid
			i_rxpipe6_pipemode_rxelecidlea                       : in  std_logic                                                     := 'X';             -- i_rxpipe6_pipemode_rxelecidlea
			i_rxpipe6_pipemode_rxstandbystatus                   : in  std_logic                                                     := 'X';             -- i_rxpipe6_pipemode_rxstandbystatus
			i_rxpipe6_pipemode_rxstartblock                      : in  std_logic                                                     := 'X';             -- i_rxpipe6_pipemode_rxstartblock
			i_rxpipe6_pipemode_rxstatus                          : in  std_logic_vector(2 downto 0)                                  := (others => 'X'); -- i_rxpipe6_pipemode_rxstatus
			i_rxpipe6_pipemode_rxsyncheader                      : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe6_pipemode_rxsyncheader
			i_rxpipe6_pipemode_rxvalid                           : in  std_logic                                                     := 'X';             -- i_rxpipe6_pipemode_rxvalid
			i_rxpipe7_pipemode_dirfeedback                       : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe7_pipemode_dirfeedback
			i_rxpipe7_pipemode_linkevaluationfeedbackfiguremerit : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe7_pipemode_linkevaluationfeedbackfiguremerit
			i_rxpipe7_pipemode_localfs                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe7_pipemode_localfs
			i_rxpipe7_pipemode_locallf                           : in  std_logic_vector(5 downto 0)                                  := (others => 'X'); -- i_rxpipe7_pipemode_locallf
			i_rxpipe7_pipemode_localtxcoefficientsvalid          : in  std_logic                                                     := 'X';             -- i_rxpipe7_pipemode_localtxcoefficientsvalid
			i_rxpipe7_pipemode_localtxpresetcoefficients         : in  std_logic_vector(17 downto 0)                                 := (others => 'X'); -- i_rxpipe7_pipemode_localtxpresetcoefficients
			i_rxpipe7_pipemode_p2m_bus                           : in  std_logic_vector(7 downto 0)                                  := (others => 'X'); -- i_rxpipe7_pipemode_p2m_bus
			i_rxpipe7_pipemode_pclkchangeok                      : in  std_logic                                                     := 'X';             -- i_rxpipe7_pipemode_pclkchangeok
			i_rxpipe7_pipemode_phystatus                         : in  std_logic                                                     := 'X';             -- i_rxpipe7_pipemode_phystatus
			i_rxpipe7_pipemode_rxdata                            : in  std_logic_vector(39 downto 0)                                 := (others => 'X'); -- i_rxpipe7_pipemode_rxdata
			i_rxpipe7_pipemode_rxdatak                           : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe7_pipemode_rxdatak
			i_rxpipe7_pipemode_rxdatavalid                       : in  std_logic                                                     := 'X';             -- i_rxpipe7_pipemode_rxdatavalid
			i_rxpipe7_pipemode_rxelecidlea                       : in  std_logic                                                     := 'X';             -- i_rxpipe7_pipemode_rxelecidlea
			i_rxpipe7_pipemode_rxstandbystatus                   : in  std_logic                                                     := 'X';             -- i_rxpipe7_pipemode_rxstandbystatus
			i_rxpipe7_pipemode_rxstartblock                      : in  std_logic                                                     := 'X';             -- i_rxpipe7_pipemode_rxstartblock
			i_rxpipe7_pipemode_rxstatus                          : in  std_logic_vector(2 downto 0)                                  := (others => 'X'); -- i_rxpipe7_pipemode_rxstatus
			i_rxpipe7_pipemode_rxsyncheader                      : in  std_logic_vector(3 downto 0)                                  := (others => 'X'); -- i_rxpipe7_pipemode_rxsyncheader
			i_rxpipe7_pipemode_rxvalid                           : in  std_logic                                                     := 'X';             -- i_rxpipe7_pipemode_rxvalid
			o_txpipe0_pipemode_asyncpowerchangeack               : out std_logic;                                                                        -- o_txpipe0_pipemode_asyncpowerchangeack
			o_txpipe0_pipemode_blockaligncontrol                 : out std_logic;                                                                        -- o_txpipe0_pipemode_blockaligncontrol
			o_txpipe0_pipemode_cfg_hw_auto_sp_dis                : out std_logic;                                                                        -- o_txpipe0_pipemode_cfg_hw_auto_sp_dis
			o_txpipe0_pipemode_dirchange                         : out std_logic;                                                                        -- o_txpipe0_pipemode_dirchange
			o_txpipe0_pipemode_ebuf_mode                         : out std_logic;                                                                        -- o_txpipe0_pipemode_ebuf_mode
			o_txpipe0_pipemode_encodedecodebypass                : out std_logic;                                                                        -- o_txpipe0_pipemode_encodedecodebypass
			o_txpipe0_pipemode_fs                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe0_pipemode_fs
			o_txpipe0_pipemode_getlocalpresetcoefficients        : out std_logic;                                                                        -- o_txpipe0_pipemode_getlocalpresetcoefficients
			o_txpipe0_pipemode_invalidrequest                    : out std_logic;                                                                        -- o_txpipe0_pipemode_invalidrequest
			o_txpipe0_pipemode_lf                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe0_pipemode_lf
			o_txpipe0_pipemode_localpresetindex                  : out std_logic_vector(4 downto 0);                                                     -- o_txpipe0_pipemode_localpresetindex
			o_txpipe0_pipemode_lowpin_nt                         : out std_logic;                                                                        -- o_txpipe0_pipemode_lowpin_nt
			o_txpipe0_pipemode_m2p_bus                           : out std_logic_vector(7 downto 0);                                                     -- o_txpipe0_pipemode_m2p_bus
			o_txpipe0_pipemode_pclk_rate                         : out std_logic_vector(2 downto 0);                                                     -- o_txpipe0_pipemode_pclk_rate
			o_txpipe0_pipemode_pclkchangeack                     : out std_logic;                                                                        -- o_txpipe0_pipemode_pclkchangeack
			o_txpipe0_pipemode_phy_mode_nt                       : out std_logic_vector(3 downto 0);                                                     -- o_txpipe0_pipemode_phy_mode_nt
			o_txpipe0_pipemode_powerdown                         : out std_logic_vector(3 downto 0);                                                     -- o_txpipe0_pipemode_powerdown
			o_txpipe0_pipemode_rate                              : out std_logic_vector(2 downto 0);                                                     -- o_txpipe0_pipemode_rate
			o_txpipe0_pipemode_rxelecidle_disable_a              : out std_logic;                                                                        -- o_txpipe0_pipemode_rxelecidle_disable_a
			o_txpipe0_pipemode_rxeqclr                           : out std_logic;                                                                        -- o_txpipe0_pipemode_rxeqclr
			o_txpipe0_pipemode_rxeqeval                          : out std_logic;                                                                        -- o_txpipe0_pipemode_rxeqeval
			o_txpipe0_pipemode_rxeqinprogress                    : out std_logic;                                                                        -- o_txpipe0_pipemode_rxeqinprogress
			o_txpipe0_pipemode_rxeqtraining                      : out std_logic;                                                                        -- o_txpipe0_pipemode_rxeqtraining
			o_txpipe0_pipemode_rxpolarity                        : out std_logic;                                                                        -- o_txpipe0_pipemode_rxpolarity
			o_txpipe0_pipemode_rxpresethint                      : out std_logic_vector(2 downto 0);                                                     -- o_txpipe0_pipemode_rxpresethint
			o_txpipe0_pipemode_rxstandby                         : out std_logic;                                                                        -- o_txpipe0_pipemode_rxstandby
			o_txpipe0_pipemode_rxtermination                     : out std_logic;                                                                        -- o_txpipe0_pipemode_rxtermination
			o_txpipe0_pipemode_srisenable                        : out std_logic;                                                                        -- o_txpipe0_pipemode_srisenable
			o_txpipe0_pipemode_txcmnmode_disable_a               : out std_logic;                                                                        -- o_txpipe0_pipemode_txcmnmode_disable_a
			o_txpipe0_pipemode_txcompliance                      : out std_logic;                                                                        -- o_txpipe0_pipemode_txcompliance
			o_txpipe0_pipemode_txdata                            : out std_logic_vector(39 downto 0);                                                    -- o_txpipe0_pipemode_txdata
			o_txpipe0_pipemode_txdatak                           : out std_logic_vector(3 downto 0);                                                     -- o_txpipe0_pipemode_txdatak
			o_txpipe0_pipemode_txdatavalid                       : out std_logic;                                                                        -- o_txpipe0_pipemode_txdatavalid
			o_txpipe0_pipemode_txdeemph                          : out std_logic_vector(17 downto 0);                                                    -- o_txpipe0_pipemode_txdeemph
			o_txpipe0_pipemode_txdtctrx_lb                       : out std_logic;                                                                        -- o_txpipe0_pipemode_txdtctrx_lb
			o_txpipe0_pipemode_txelecidle                        : out std_logic;                                                                        -- o_txpipe0_pipemode_txelecidle
			o_txpipe0_pipemode_txmargin                          : out std_logic_vector(2 downto 0);                                                     -- o_txpipe0_pipemode_txmargin
			o_txpipe0_pipemode_txoneszeros                       : out std_logic;                                                                        -- o_txpipe0_pipemode_txoneszeros
			o_txpipe0_pipemode_txstartblock                      : out std_logic;                                                                        -- o_txpipe0_pipemode_txstartblock
			o_txpipe0_pipemode_txswing                           : out std_logic;                                                                        -- o_txpipe0_pipemode_txswing
			o_txpipe0_pipemode_txsyncheader                      : out std_logic_vector(3 downto 0);                                                     -- o_txpipe0_pipemode_txsyncheader
			o_txpipe0_pipemode_width                             : out std_logic_vector(2 downto 0);                                                     -- o_txpipe0_pipemode_width
			o_txpipe1_pipemode_asyncpowerchangeack               : out std_logic;                                                                        -- o_txpipe1_pipemode_asyncpowerchangeack
			o_txpipe1_pipemode_blockaligncontrol                 : out std_logic;                                                                        -- o_txpipe1_pipemode_blockaligncontrol
			o_txpipe1_pipemode_cfg_hw_auto_sp_dis                : out std_logic;                                                                        -- o_txpipe1_pipemode_cfg_hw_auto_sp_dis
			o_txpipe1_pipemode_dirchange                         : out std_logic;                                                                        -- o_txpipe1_pipemode_dirchange
			o_txpipe1_pipemode_ebuf_mode                         : out std_logic;                                                                        -- o_txpipe1_pipemode_ebuf_mode
			o_txpipe1_pipemode_encodedecodebypass                : out std_logic;                                                                        -- o_txpipe1_pipemode_encodedecodebypass
			o_txpipe1_pipemode_fs                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe1_pipemode_fs
			o_txpipe1_pipemode_getlocalpresetcoefficients        : out std_logic;                                                                        -- o_txpipe1_pipemode_getlocalpresetcoefficients
			o_txpipe1_pipemode_invalidrequest                    : out std_logic;                                                                        -- o_txpipe1_pipemode_invalidrequest
			o_txpipe1_pipemode_lf                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe1_pipemode_lf
			o_txpipe1_pipemode_localpresetindex                  : out std_logic_vector(4 downto 0);                                                     -- o_txpipe1_pipemode_localpresetindex
			o_txpipe1_pipemode_lowpin_nt                         : out std_logic;                                                                        -- o_txpipe1_pipemode_lowpin_nt
			o_txpipe1_pipemode_m2p_bus                           : out std_logic_vector(7 downto 0);                                                     -- o_txpipe1_pipemode_m2p_bus
			o_txpipe1_pipemode_pclk_rate                         : out std_logic_vector(2 downto 0);                                                     -- o_txpipe1_pipemode_pclk_rate
			o_txpipe1_pipemode_pclkchangeack                     : out std_logic;                                                                        -- o_txpipe1_pipemode_pclkchangeack
			o_txpipe1_pipemode_phy_mode_nt                       : out std_logic_vector(3 downto 0);                                                     -- o_txpipe1_pipemode_phy_mode_nt
			o_txpipe1_pipemode_powerdown                         : out std_logic_vector(3 downto 0);                                                     -- o_txpipe1_pipemode_powerdown
			o_txpipe1_pipemode_rate                              : out std_logic_vector(2 downto 0);                                                     -- o_txpipe1_pipemode_rate
			o_txpipe1_pipemode_rxelecidle_disable_a              : out std_logic;                                                                        -- o_txpipe1_pipemode_rxelecidle_disable_a
			o_txpipe1_pipemode_rxeqclr                           : out std_logic;                                                                        -- o_txpipe1_pipemode_rxeqclr
			o_txpipe1_pipemode_rxeqeval                          : out std_logic;                                                                        -- o_txpipe1_pipemode_rxeqeval
			o_txpipe1_pipemode_rxeqinprogress                    : out std_logic;                                                                        -- o_txpipe1_pipemode_rxeqinprogress
			o_txpipe1_pipemode_rxeqtraining                      : out std_logic;                                                                        -- o_txpipe1_pipemode_rxeqtraining
			o_txpipe1_pipemode_rxpolarity                        : out std_logic;                                                                        -- o_txpipe1_pipemode_rxpolarity
			o_txpipe1_pipemode_rxpresethint                      : out std_logic_vector(2 downto 0);                                                     -- o_txpipe1_pipemode_rxpresethint
			o_txpipe1_pipemode_rxstandby                         : out std_logic;                                                                        -- o_txpipe1_pipemode_rxstandby
			o_txpipe1_pipemode_rxtermination                     : out std_logic;                                                                        -- o_txpipe1_pipemode_rxtermination
			o_txpipe1_pipemode_srisenable                        : out std_logic;                                                                        -- o_txpipe1_pipemode_srisenable
			o_txpipe1_pipemode_txcmnmode_disable_a               : out std_logic;                                                                        -- o_txpipe1_pipemode_txcmnmode_disable_a
			o_txpipe1_pipemode_txcompliance                      : out std_logic;                                                                        -- o_txpipe1_pipemode_txcompliance
			o_txpipe1_pipemode_txdata                            : out std_logic_vector(39 downto 0);                                                    -- o_txpipe1_pipemode_txdata
			o_txpipe1_pipemode_txdatak                           : out std_logic_vector(3 downto 0);                                                     -- o_txpipe1_pipemode_txdatak
			o_txpipe1_pipemode_txdatavalid                       : out std_logic;                                                                        -- o_txpipe1_pipemode_txdatavalid
			o_txpipe1_pipemode_txdeemph                          : out std_logic_vector(17 downto 0);                                                    -- o_txpipe1_pipemode_txdeemph
			o_txpipe1_pipemode_txdtctrx_lb                       : out std_logic;                                                                        -- o_txpipe1_pipemode_txdtctrx_lb
			o_txpipe1_pipemode_txelecidle                        : out std_logic;                                                                        -- o_txpipe1_pipemode_txelecidle
			o_txpipe1_pipemode_txmargin                          : out std_logic_vector(2 downto 0);                                                     -- o_txpipe1_pipemode_txmargin
			o_txpipe1_pipemode_txoneszeros                       : out std_logic;                                                                        -- o_txpipe1_pipemode_txoneszeros
			o_txpipe1_pipemode_txstartblock                      : out std_logic;                                                                        -- o_txpipe1_pipemode_txstartblock
			o_txpipe1_pipemode_txswing                           : out std_logic;                                                                        -- o_txpipe1_pipemode_txswing
			o_txpipe1_pipemode_txsyncheader                      : out std_logic_vector(3 downto 0);                                                     -- o_txpipe1_pipemode_txsyncheader
			o_txpipe1_pipemode_width                             : out std_logic_vector(2 downto 0);                                                     -- o_txpipe1_pipemode_width
			o_txpipe2_pipemode_asyncpowerchangeack               : out std_logic;                                                                        -- o_txpipe2_pipemode_asyncpowerchangeack
			o_txpipe2_pipemode_blockaligncontrol                 : out std_logic;                                                                        -- o_txpipe2_pipemode_blockaligncontrol
			o_txpipe2_pipemode_cfg_hw_auto_sp_dis                : out std_logic;                                                                        -- o_txpipe2_pipemode_cfg_hw_auto_sp_dis
			o_txpipe2_pipemode_dirchange                         : out std_logic;                                                                        -- o_txpipe2_pipemode_dirchange
			o_txpipe2_pipemode_ebuf_mode                         : out std_logic;                                                                        -- o_txpipe2_pipemode_ebuf_mode
			o_txpipe2_pipemode_encodedecodebypass                : out std_logic;                                                                        -- o_txpipe2_pipemode_encodedecodebypass
			o_txpipe2_pipemode_fs                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe2_pipemode_fs
			o_txpipe2_pipemode_getlocalpresetcoefficients        : out std_logic;                                                                        -- o_txpipe2_pipemode_getlocalpresetcoefficients
			o_txpipe2_pipemode_invalidrequest                    : out std_logic;                                                                        -- o_txpipe2_pipemode_invalidrequest
			o_txpipe2_pipemode_lf                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe2_pipemode_lf
			o_txpipe2_pipemode_localpresetindex                  : out std_logic_vector(4 downto 0);                                                     -- o_txpipe2_pipemode_localpresetindex
			o_txpipe2_pipemode_lowpin_nt                         : out std_logic;                                                                        -- o_txpipe2_pipemode_lowpin_nt
			o_txpipe2_pipemode_m2p_bus                           : out std_logic_vector(7 downto 0);                                                     -- o_txpipe2_pipemode_m2p_bus
			o_txpipe2_pipemode_pclk_rate                         : out std_logic_vector(2 downto 0);                                                     -- o_txpipe2_pipemode_pclk_rate
			o_txpipe2_pipemode_pclkchangeack                     : out std_logic;                                                                        -- o_txpipe2_pipemode_pclkchangeack
			o_txpipe2_pipemode_phy_mode_nt                       : out std_logic_vector(3 downto 0);                                                     -- o_txpipe2_pipemode_phy_mode_nt
			o_txpipe2_pipemode_powerdown                         : out std_logic_vector(3 downto 0);                                                     -- o_txpipe2_pipemode_powerdown
			o_txpipe2_pipemode_rate                              : out std_logic_vector(2 downto 0);                                                     -- o_txpipe2_pipemode_rate
			o_txpipe2_pipemode_rxelecidle_disable_a              : out std_logic;                                                                        -- o_txpipe2_pipemode_rxelecidle_disable_a
			o_txpipe2_pipemode_rxeqclr                           : out std_logic;                                                                        -- o_txpipe2_pipemode_rxeqclr
			o_txpipe2_pipemode_rxeqeval                          : out std_logic;                                                                        -- o_txpipe2_pipemode_rxeqeval
			o_txpipe2_pipemode_rxeqinprogress                    : out std_logic;                                                                        -- o_txpipe2_pipemode_rxeqinprogress
			o_txpipe2_pipemode_rxeqtraining                      : out std_logic;                                                                        -- o_txpipe2_pipemode_rxeqtraining
			o_txpipe2_pipemode_rxpolarity                        : out std_logic;                                                                        -- o_txpipe2_pipemode_rxpolarity
			o_txpipe2_pipemode_rxpresethint                      : out std_logic_vector(2 downto 0);                                                     -- o_txpipe2_pipemode_rxpresethint
			o_txpipe2_pipemode_rxstandby                         : out std_logic;                                                                        -- o_txpipe2_pipemode_rxstandby
			o_txpipe2_pipemode_rxtermination                     : out std_logic;                                                                        -- o_txpipe2_pipemode_rxtermination
			o_txpipe2_pipemode_srisenable                        : out std_logic;                                                                        -- o_txpipe2_pipemode_srisenable
			o_txpipe2_pipemode_txcmnmode_disable_a               : out std_logic;                                                                        -- o_txpipe2_pipemode_txcmnmode_disable_a
			o_txpipe2_pipemode_txcompliance                      : out std_logic;                                                                        -- o_txpipe2_pipemode_txcompliance
			o_txpipe2_pipemode_txdata                            : out std_logic_vector(39 downto 0);                                                    -- o_txpipe2_pipemode_txdata
			o_txpipe2_pipemode_txdatak                           : out std_logic_vector(3 downto 0);                                                     -- o_txpipe2_pipemode_txdatak
			o_txpipe2_pipemode_txdatavalid                       : out std_logic;                                                                        -- o_txpipe2_pipemode_txdatavalid
			o_txpipe2_pipemode_txdeemph                          : out std_logic_vector(17 downto 0);                                                    -- o_txpipe2_pipemode_txdeemph
			o_txpipe2_pipemode_txdtctrx_lb                       : out std_logic;                                                                        -- o_txpipe2_pipemode_txdtctrx_lb
			o_txpipe2_pipemode_txelecidle                        : out std_logic;                                                                        -- o_txpipe2_pipemode_txelecidle
			o_txpipe2_pipemode_txmargin                          : out std_logic_vector(2 downto 0);                                                     -- o_txpipe2_pipemode_txmargin
			o_txpipe2_pipemode_txoneszeros                       : out std_logic;                                                                        -- o_txpipe2_pipemode_txoneszeros
			o_txpipe2_pipemode_txstartblock                      : out std_logic;                                                                        -- o_txpipe2_pipemode_txstartblock
			o_txpipe2_pipemode_txswing                           : out std_logic;                                                                        -- o_txpipe2_pipemode_txswing
			o_txpipe2_pipemode_txsyncheader                      : out std_logic_vector(3 downto 0);                                                     -- o_txpipe2_pipemode_txsyncheader
			o_txpipe2_pipemode_width                             : out std_logic_vector(2 downto 0);                                                     -- o_txpipe2_pipemode_width
			o_txpipe3_pipemode_asyncpowerchangeack               : out std_logic;                                                                        -- o_txpipe3_pipemode_asyncpowerchangeack
			o_txpipe3_pipemode_blockaligncontrol                 : out std_logic;                                                                        -- o_txpipe3_pipemode_blockaligncontrol
			o_txpipe3_pipemode_cfg_hw_auto_sp_dis                : out std_logic;                                                                        -- o_txpipe3_pipemode_cfg_hw_auto_sp_dis
			o_txpipe3_pipemode_dirchange                         : out std_logic;                                                                        -- o_txpipe3_pipemode_dirchange
			o_txpipe3_pipemode_ebuf_mode                         : out std_logic;                                                                        -- o_txpipe3_pipemode_ebuf_mode
			o_txpipe3_pipemode_encodedecodebypass                : out std_logic;                                                                        -- o_txpipe3_pipemode_encodedecodebypass
			o_txpipe3_pipemode_fs                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe3_pipemode_fs
			o_txpipe3_pipemode_getlocalpresetcoefficients        : out std_logic;                                                                        -- o_txpipe3_pipemode_getlocalpresetcoefficients
			o_txpipe3_pipemode_invalidrequest                    : out std_logic;                                                                        -- o_txpipe3_pipemode_invalidrequest
			o_txpipe3_pipemode_lf                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe3_pipemode_lf
			o_txpipe3_pipemode_localpresetindex                  : out std_logic_vector(4 downto 0);                                                     -- o_txpipe3_pipemode_localpresetindex
			o_txpipe3_pipemode_lowpin_nt                         : out std_logic;                                                                        -- o_txpipe3_pipemode_lowpin_nt
			o_txpipe3_pipemode_m2p_bus                           : out std_logic_vector(7 downto 0);                                                     -- o_txpipe3_pipemode_m2p_bus
			o_txpipe3_pipemode_pclk_rate                         : out std_logic_vector(2 downto 0);                                                     -- o_txpipe3_pipemode_pclk_rate
			o_txpipe3_pipemode_pclkchangeack                     : out std_logic;                                                                        -- o_txpipe3_pipemode_pclkchangeack
			o_txpipe3_pipemode_phy_mode_nt                       : out std_logic_vector(3 downto 0);                                                     -- o_txpipe3_pipemode_phy_mode_nt
			o_txpipe3_pipemode_powerdown                         : out std_logic_vector(3 downto 0);                                                     -- o_txpipe3_pipemode_powerdown
			o_txpipe3_pipemode_rate                              : out std_logic_vector(2 downto 0);                                                     -- o_txpipe3_pipemode_rate
			o_txpipe3_pipemode_rxelecidle_disable_a              : out std_logic;                                                                        -- o_txpipe3_pipemode_rxelecidle_disable_a
			o_txpipe3_pipemode_rxeqclr                           : out std_logic;                                                                        -- o_txpipe3_pipemode_rxeqclr
			o_txpipe3_pipemode_rxeqeval                          : out std_logic;                                                                        -- o_txpipe3_pipemode_rxeqeval
			o_txpipe3_pipemode_rxeqinprogress                    : out std_logic;                                                                        -- o_txpipe3_pipemode_rxeqinprogress
			o_txpipe3_pipemode_rxeqtraining                      : out std_logic;                                                                        -- o_txpipe3_pipemode_rxeqtraining
			o_txpipe3_pipemode_rxpolarity                        : out std_logic;                                                                        -- o_txpipe3_pipemode_rxpolarity
			o_txpipe3_pipemode_rxpresethint                      : out std_logic_vector(2 downto 0);                                                     -- o_txpipe3_pipemode_rxpresethint
			o_txpipe3_pipemode_rxstandby                         : out std_logic;                                                                        -- o_txpipe3_pipemode_rxstandby
			o_txpipe3_pipemode_rxtermination                     : out std_logic;                                                                        -- o_txpipe3_pipemode_rxtermination
			o_txpipe3_pipemode_srisenable                        : out std_logic;                                                                        -- o_txpipe3_pipemode_srisenable
			o_txpipe3_pipemode_txcmnmode_disable_a               : out std_logic;                                                                        -- o_txpipe3_pipemode_txcmnmode_disable_a
			o_txpipe3_pipemode_txcompliance                      : out std_logic;                                                                        -- o_txpipe3_pipemode_txcompliance
			o_txpipe3_pipemode_txdata                            : out std_logic_vector(39 downto 0);                                                    -- o_txpipe3_pipemode_txdata
			o_txpipe3_pipemode_txdatak                           : out std_logic_vector(3 downto 0);                                                     -- o_txpipe3_pipemode_txdatak
			o_txpipe3_pipemode_txdatavalid                       : out std_logic;                                                                        -- o_txpipe3_pipemode_txdatavalid
			o_txpipe3_pipemode_txdeemph                          : out std_logic_vector(17 downto 0);                                                    -- o_txpipe3_pipemode_txdeemph
			o_txpipe3_pipemode_txdtctrx_lb                       : out std_logic;                                                                        -- o_txpipe3_pipemode_txdtctrx_lb
			o_txpipe3_pipemode_txelecidle                        : out std_logic;                                                                        -- o_txpipe3_pipemode_txelecidle
			o_txpipe3_pipemode_txmargin                          : out std_logic_vector(2 downto 0);                                                     -- o_txpipe3_pipemode_txmargin
			o_txpipe3_pipemode_txoneszeros                       : out std_logic;                                                                        -- o_txpipe3_pipemode_txoneszeros
			o_txpipe3_pipemode_txstartblock                      : out std_logic;                                                                        -- o_txpipe3_pipemode_txstartblock
			o_txpipe3_pipemode_txswing                           : out std_logic;                                                                        -- o_txpipe3_pipemode_txswing
			o_txpipe3_pipemode_txsyncheader                      : out std_logic_vector(3 downto 0);                                                     -- o_txpipe3_pipemode_txsyncheader
			o_txpipe3_pipemode_width                             : out std_logic_vector(2 downto 0);                                                     -- o_txpipe3_pipemode_width
			o_txpipe4_pipemode_asyncpowerchangeack               : out std_logic;                                                                        -- o_txpipe4_pipemode_asyncpowerchangeack
			o_txpipe4_pipemode_blockaligncontrol                 : out std_logic;                                                                        -- o_txpipe4_pipemode_blockaligncontrol
			o_txpipe4_pipemode_cfg_hw_auto_sp_dis                : out std_logic;                                                                        -- o_txpipe4_pipemode_cfg_hw_auto_sp_dis
			o_txpipe4_pipemode_dirchange                         : out std_logic;                                                                        -- o_txpipe4_pipemode_dirchange
			o_txpipe4_pipemode_ebuf_mode                         : out std_logic;                                                                        -- o_txpipe4_pipemode_ebuf_mode
			o_txpipe4_pipemode_encodedecodebypass                : out std_logic;                                                                        -- o_txpipe4_pipemode_encodedecodebypass
			o_txpipe4_pipemode_fs                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe4_pipemode_fs
			o_txpipe4_pipemode_getlocalpresetcoefficients        : out std_logic;                                                                        -- o_txpipe4_pipemode_getlocalpresetcoefficients
			o_txpipe4_pipemode_invalidrequest                    : out std_logic;                                                                        -- o_txpipe4_pipemode_invalidrequest
			o_txpipe4_pipemode_lf                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe4_pipemode_lf
			o_txpipe4_pipemode_localpresetindex                  : out std_logic_vector(4 downto 0);                                                     -- o_txpipe4_pipemode_localpresetindex
			o_txpipe4_pipemode_lowpin_nt                         : out std_logic;                                                                        -- o_txpipe4_pipemode_lowpin_nt
			o_txpipe4_pipemode_m2p_bus                           : out std_logic_vector(7 downto 0);                                                     -- o_txpipe4_pipemode_m2p_bus
			o_txpipe4_pipemode_pclk_rate                         : out std_logic_vector(2 downto 0);                                                     -- o_txpipe4_pipemode_pclk_rate
			o_txpipe4_pipemode_pclkchangeack                     : out std_logic;                                                                        -- o_txpipe4_pipemode_pclkchangeack
			o_txpipe4_pipemode_phy_mode_nt                       : out std_logic_vector(3 downto 0);                                                     -- o_txpipe4_pipemode_phy_mode_nt
			o_txpipe4_pipemode_powerdown                         : out std_logic_vector(3 downto 0);                                                     -- o_txpipe4_pipemode_powerdown
			o_txpipe4_pipemode_rate                              : out std_logic_vector(2 downto 0);                                                     -- o_txpipe4_pipemode_rate
			o_txpipe4_pipemode_rxelecidle_disable_a              : out std_logic;                                                                        -- o_txpipe4_pipemode_rxelecidle_disable_a
			o_txpipe4_pipemode_rxeqclr                           : out std_logic;                                                                        -- o_txpipe4_pipemode_rxeqclr
			o_txpipe4_pipemode_rxeqeval                          : out std_logic;                                                                        -- o_txpipe4_pipemode_rxeqeval
			o_txpipe4_pipemode_rxeqinprogress                    : out std_logic;                                                                        -- o_txpipe4_pipemode_rxeqinprogress
			o_txpipe4_pipemode_rxeqtraining                      : out std_logic;                                                                        -- o_txpipe4_pipemode_rxeqtraining
			o_txpipe4_pipemode_rxpolarity                        : out std_logic;                                                                        -- o_txpipe4_pipemode_rxpolarity
			o_txpipe4_pipemode_rxpresethint                      : out std_logic_vector(2 downto 0);                                                     -- o_txpipe4_pipemode_rxpresethint
			o_txpipe4_pipemode_rxstandby                         : out std_logic;                                                                        -- o_txpipe4_pipemode_rxstandby
			o_txpipe4_pipemode_rxtermination                     : out std_logic;                                                                        -- o_txpipe4_pipemode_rxtermination
			o_txpipe4_pipemode_srisenable                        : out std_logic;                                                                        -- o_txpipe4_pipemode_srisenable
			o_txpipe4_pipemode_txcmnmode_disable_a               : out std_logic;                                                                        -- o_txpipe4_pipemode_txcmnmode_disable_a
			o_txpipe4_pipemode_txcompliance                      : out std_logic;                                                                        -- o_txpipe4_pipemode_txcompliance
			o_txpipe4_pipemode_txdata                            : out std_logic_vector(39 downto 0);                                                    -- o_txpipe4_pipemode_txdata
			o_txpipe4_pipemode_txdatak                           : out std_logic_vector(3 downto 0);                                                     -- o_txpipe4_pipemode_txdatak
			o_txpipe4_pipemode_txdatavalid                       : out std_logic;                                                                        -- o_txpipe4_pipemode_txdatavalid
			o_txpipe4_pipemode_txdeemph                          : out std_logic_vector(17 downto 0);                                                    -- o_txpipe4_pipemode_txdeemph
			o_txpipe4_pipemode_txdtctrx_lb                       : out std_logic;                                                                        -- o_txpipe4_pipemode_txdtctrx_lb
			o_txpipe4_pipemode_txelecidle                        : out std_logic;                                                                        -- o_txpipe4_pipemode_txelecidle
			o_txpipe4_pipemode_txmargin                          : out std_logic_vector(2 downto 0);                                                     -- o_txpipe4_pipemode_txmargin
			o_txpipe4_pipemode_txoneszeros                       : out std_logic;                                                                        -- o_txpipe4_pipemode_txoneszeros
			o_txpipe4_pipemode_txstartblock                      : out std_logic;                                                                        -- o_txpipe4_pipemode_txstartblock
			o_txpipe4_pipemode_txswing                           : out std_logic;                                                                        -- o_txpipe4_pipemode_txswing
			o_txpipe4_pipemode_txsyncheader                      : out std_logic_vector(3 downto 0);                                                     -- o_txpipe4_pipemode_txsyncheader
			o_txpipe4_pipemode_width                             : out std_logic_vector(2 downto 0);                                                     -- o_txpipe4_pipemode_width
			o_txpipe5_pipemode_asyncpowerchangeack               : out std_logic;                                                                        -- o_txpipe5_pipemode_asyncpowerchangeack
			o_txpipe5_pipemode_blockaligncontrol                 : out std_logic;                                                                        -- o_txpipe5_pipemode_blockaligncontrol
			o_txpipe5_pipemode_cfg_hw_auto_sp_dis                : out std_logic;                                                                        -- o_txpipe5_pipemode_cfg_hw_auto_sp_dis
			o_txpipe5_pipemode_dirchange                         : out std_logic;                                                                        -- o_txpipe5_pipemode_dirchange
			o_txpipe5_pipemode_ebuf_mode                         : out std_logic;                                                                        -- o_txpipe5_pipemode_ebuf_mode
			o_txpipe5_pipemode_encodedecodebypass                : out std_logic;                                                                        -- o_txpipe5_pipemode_encodedecodebypass
			o_txpipe5_pipemode_fs                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe5_pipemode_fs
			o_txpipe5_pipemode_getlocalpresetcoefficients        : out std_logic;                                                                        -- o_txpipe5_pipemode_getlocalpresetcoefficients
			o_txpipe5_pipemode_invalidrequest                    : out std_logic;                                                                        -- o_txpipe5_pipemode_invalidrequest
			o_txpipe5_pipemode_lf                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe5_pipemode_lf
			o_txpipe5_pipemode_localpresetindex                  : out std_logic_vector(4 downto 0);                                                     -- o_txpipe5_pipemode_localpresetindex
			o_txpipe5_pipemode_lowpin_nt                         : out std_logic;                                                                        -- o_txpipe5_pipemode_lowpin_nt
			o_txpipe5_pipemode_m2p_bus                           : out std_logic_vector(7 downto 0);                                                     -- o_txpipe5_pipemode_m2p_bus
			o_txpipe5_pipemode_pclk_rate                         : out std_logic_vector(2 downto 0);                                                     -- o_txpipe5_pipemode_pclk_rate
			o_txpipe5_pipemode_pclkchangeack                     : out std_logic;                                                                        -- o_txpipe5_pipemode_pclkchangeack
			o_txpipe5_pipemode_phy_mode_nt                       : out std_logic_vector(3 downto 0);                                                     -- o_txpipe5_pipemode_phy_mode_nt
			o_txpipe5_pipemode_powerdown                         : out std_logic_vector(3 downto 0);                                                     -- o_txpipe5_pipemode_powerdown
			o_txpipe5_pipemode_rate                              : out std_logic_vector(2 downto 0);                                                     -- o_txpipe5_pipemode_rate
			o_txpipe5_pipemode_rxelecidle_disable_a              : out std_logic;                                                                        -- o_txpipe5_pipemode_rxelecidle_disable_a
			o_txpipe5_pipemode_rxeqclr                           : out std_logic;                                                                        -- o_txpipe5_pipemode_rxeqclr
			o_txpipe5_pipemode_rxeqeval                          : out std_logic;                                                                        -- o_txpipe5_pipemode_rxeqeval
			o_txpipe5_pipemode_rxeqinprogress                    : out std_logic;                                                                        -- o_txpipe5_pipemode_rxeqinprogress
			o_txpipe5_pipemode_rxeqtraining                      : out std_logic;                                                                        -- o_txpipe5_pipemode_rxeqtraining
			o_txpipe5_pipemode_rxpolarity                        : out std_logic;                                                                        -- o_txpipe5_pipemode_rxpolarity
			o_txpipe5_pipemode_rxpresethint                      : out std_logic_vector(2 downto 0);                                                     -- o_txpipe5_pipemode_rxpresethint
			o_txpipe5_pipemode_rxstandby                         : out std_logic;                                                                        -- o_txpipe5_pipemode_rxstandby
			o_txpipe5_pipemode_rxtermination                     : out std_logic;                                                                        -- o_txpipe5_pipemode_rxtermination
			o_txpipe5_pipemode_srisenable                        : out std_logic;                                                                        -- o_txpipe5_pipemode_srisenable
			o_txpipe5_pipemode_txcmnmode_disable_a               : out std_logic;                                                                        -- o_txpipe5_pipemode_txcmnmode_disable_a
			o_txpipe5_pipemode_txcompliance                      : out std_logic;                                                                        -- o_txpipe5_pipemode_txcompliance
			o_txpipe5_pipemode_txdata                            : out std_logic_vector(39 downto 0);                                                    -- o_txpipe5_pipemode_txdata
			o_txpipe5_pipemode_txdatak                           : out std_logic_vector(3 downto 0);                                                     -- o_txpipe5_pipemode_txdatak
			o_txpipe5_pipemode_txdatavalid                       : out std_logic;                                                                        -- o_txpipe5_pipemode_txdatavalid
			o_txpipe5_pipemode_txdeemph                          : out std_logic_vector(17 downto 0);                                                    -- o_txpipe5_pipemode_txdeemph
			o_txpipe5_pipemode_txdtctrx_lb                       : out std_logic;                                                                        -- o_txpipe5_pipemode_txdtctrx_lb
			o_txpipe5_pipemode_txelecidle                        : out std_logic;                                                                        -- o_txpipe5_pipemode_txelecidle
			o_txpipe5_pipemode_txmargin                          : out std_logic_vector(2 downto 0);                                                     -- o_txpipe5_pipemode_txmargin
			o_txpipe5_pipemode_txoneszeros                       : out std_logic;                                                                        -- o_txpipe5_pipemode_txoneszeros
			o_txpipe5_pipemode_txstartblock                      : out std_logic;                                                                        -- o_txpipe5_pipemode_txstartblock
			o_txpipe5_pipemode_txswing                           : out std_logic;                                                                        -- o_txpipe5_pipemode_txswing
			o_txpipe5_pipemode_txsyncheader                      : out std_logic_vector(3 downto 0);                                                     -- o_txpipe5_pipemode_txsyncheader
			o_txpipe5_pipemode_width                             : out std_logic_vector(2 downto 0);                                                     -- o_txpipe5_pipemode_width
			o_txpipe6_pipemode_asyncpowerchangeack               : out std_logic;                                                                        -- o_txpipe6_pipemode_asyncpowerchangeack
			o_txpipe6_pipemode_blockaligncontrol                 : out std_logic;                                                                        -- o_txpipe6_pipemode_blockaligncontrol
			o_txpipe6_pipemode_cfg_hw_auto_sp_dis                : out std_logic;                                                                        -- o_txpipe6_pipemode_cfg_hw_auto_sp_dis
			o_txpipe6_pipemode_dirchange                         : out std_logic;                                                                        -- o_txpipe6_pipemode_dirchange
			o_txpipe6_pipemode_ebuf_mode                         : out std_logic;                                                                        -- o_txpipe6_pipemode_ebuf_mode
			o_txpipe6_pipemode_encodedecodebypass                : out std_logic;                                                                        -- o_txpipe6_pipemode_encodedecodebypass
			o_txpipe6_pipemode_fs                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe6_pipemode_fs
			o_txpipe6_pipemode_getlocalpresetcoefficients        : out std_logic;                                                                        -- o_txpipe6_pipemode_getlocalpresetcoefficients
			o_txpipe6_pipemode_invalidrequest                    : out std_logic;                                                                        -- o_txpipe6_pipemode_invalidrequest
			o_txpipe6_pipemode_lf                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe6_pipemode_lf
			o_txpipe6_pipemode_localpresetindex                  : out std_logic_vector(4 downto 0);                                                     -- o_txpipe6_pipemode_localpresetindex
			o_txpipe6_pipemode_lowpin_nt                         : out std_logic;                                                                        -- o_txpipe6_pipemode_lowpin_nt
			o_txpipe6_pipemode_m2p_bus                           : out std_logic_vector(7 downto 0);                                                     -- o_txpipe6_pipemode_m2p_bus
			o_txpipe6_pipemode_pclk_rate                         : out std_logic_vector(2 downto 0);                                                     -- o_txpipe6_pipemode_pclk_rate
			o_txpipe6_pipemode_pclkchangeack                     : out std_logic;                                                                        -- o_txpipe6_pipemode_pclkchangeack
			o_txpipe6_pipemode_phy_mode_nt                       : out std_logic_vector(3 downto 0);                                                     -- o_txpipe6_pipemode_phy_mode_nt
			o_txpipe6_pipemode_powerdown                         : out std_logic_vector(3 downto 0);                                                     -- o_txpipe6_pipemode_powerdown
			o_txpipe6_pipemode_rate                              : out std_logic_vector(2 downto 0);                                                     -- o_txpipe6_pipemode_rate
			o_txpipe6_pipemode_rxelecidle_disable_a              : out std_logic;                                                                        -- o_txpipe6_pipemode_rxelecidle_disable_a
			o_txpipe6_pipemode_rxeqclr                           : out std_logic;                                                                        -- o_txpipe6_pipemode_rxeqclr
			o_txpipe6_pipemode_rxeqeval                          : out std_logic;                                                                        -- o_txpipe6_pipemode_rxeqeval
			o_txpipe6_pipemode_rxeqinprogress                    : out std_logic;                                                                        -- o_txpipe6_pipemode_rxeqinprogress
			o_txpipe6_pipemode_rxeqtraining                      : out std_logic;                                                                        -- o_txpipe6_pipemode_rxeqtraining
			o_txpipe6_pipemode_rxpolarity                        : out std_logic;                                                                        -- o_txpipe6_pipemode_rxpolarity
			o_txpipe6_pipemode_rxpresethint                      : out std_logic_vector(2 downto 0);                                                     -- o_txpipe6_pipemode_rxpresethint
			o_txpipe6_pipemode_rxstandby                         : out std_logic;                                                                        -- o_txpipe6_pipemode_rxstandby
			o_txpipe6_pipemode_rxtermination                     : out std_logic;                                                                        -- o_txpipe6_pipemode_rxtermination
			o_txpipe6_pipemode_srisenable                        : out std_logic;                                                                        -- o_txpipe6_pipemode_srisenable
			o_txpipe6_pipemode_txcmnmode_disable_a               : out std_logic;                                                                        -- o_txpipe6_pipemode_txcmnmode_disable_a
			o_txpipe6_pipemode_txcompliance                      : out std_logic;                                                                        -- o_txpipe6_pipemode_txcompliance
			o_txpipe6_pipemode_txdata                            : out std_logic_vector(39 downto 0);                                                    -- o_txpipe6_pipemode_txdata
			o_txpipe6_pipemode_txdatak                           : out std_logic_vector(3 downto 0);                                                     -- o_txpipe6_pipemode_txdatak
			o_txpipe6_pipemode_txdatavalid                       : out std_logic;                                                                        -- o_txpipe6_pipemode_txdatavalid
			o_txpipe6_pipemode_txdeemph                          : out std_logic_vector(17 downto 0);                                                    -- o_txpipe6_pipemode_txdeemph
			o_txpipe6_pipemode_txdtctrx_lb                       : out std_logic;                                                                        -- o_txpipe6_pipemode_txdtctrx_lb
			o_txpipe6_pipemode_txelecidle                        : out std_logic;                                                                        -- o_txpipe6_pipemode_txelecidle
			o_txpipe6_pipemode_txmargin                          : out std_logic_vector(2 downto 0);                                                     -- o_txpipe6_pipemode_txmargin
			o_txpipe6_pipemode_txoneszeros                       : out std_logic;                                                                        -- o_txpipe6_pipemode_txoneszeros
			o_txpipe6_pipemode_txstartblock                      : out std_logic;                                                                        -- o_txpipe6_pipemode_txstartblock
			o_txpipe6_pipemode_txswing                           : out std_logic;                                                                        -- o_txpipe6_pipemode_txswing
			o_txpipe6_pipemode_txsyncheader                      : out std_logic_vector(3 downto 0);                                                     -- o_txpipe6_pipemode_txsyncheader
			o_txpipe6_pipemode_width                             : out std_logic_vector(2 downto 0);                                                     -- o_txpipe6_pipemode_width
			o_txpipe7_pipemode_asyncpowerchangeack               : out std_logic;                                                                        -- o_txpipe7_pipemode_asyncpowerchangeack
			o_txpipe7_pipemode_blockaligncontrol                 : out std_logic;                                                                        -- o_txpipe7_pipemode_blockaligncontrol
			o_txpipe7_pipemode_cfg_hw_auto_sp_dis                : out std_logic;                                                                        -- o_txpipe7_pipemode_cfg_hw_auto_sp_dis
			o_txpipe7_pipemode_dirchange                         : out std_logic;                                                                        -- o_txpipe7_pipemode_dirchange
			o_txpipe7_pipemode_ebuf_mode                         : out std_logic;                                                                        -- o_txpipe7_pipemode_ebuf_mode
			o_txpipe7_pipemode_encodedecodebypass                : out std_logic;                                                                        -- o_txpipe7_pipemode_encodedecodebypass
			o_txpipe7_pipemode_fs                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe7_pipemode_fs
			o_txpipe7_pipemode_getlocalpresetcoefficients        : out std_logic;                                                                        -- o_txpipe7_pipemode_getlocalpresetcoefficients
			o_txpipe7_pipemode_invalidrequest                    : out std_logic;                                                                        -- o_txpipe7_pipemode_invalidrequest
			o_txpipe7_pipemode_lf                                : out std_logic_vector(5 downto 0);                                                     -- o_txpipe7_pipemode_lf
			o_txpipe7_pipemode_localpresetindex                  : out std_logic_vector(4 downto 0);                                                     -- o_txpipe7_pipemode_localpresetindex
			o_txpipe7_pipemode_lowpin_nt                         : out std_logic;                                                                        -- o_txpipe7_pipemode_lowpin_nt
			o_txpipe7_pipemode_m2p_bus                           : out std_logic_vector(7 downto 0);                                                     -- o_txpipe7_pipemode_m2p_bus
			o_txpipe7_pipemode_pclk_rate                         : out std_logic_vector(2 downto 0);                                                     -- o_txpipe7_pipemode_pclk_rate
			o_txpipe7_pipemode_pclkchangeack                     : out std_logic;                                                                        -- o_txpipe7_pipemode_pclkchangeack
			o_txpipe7_pipemode_phy_mode_nt                       : out std_logic_vector(3 downto 0);                                                     -- o_txpipe7_pipemode_phy_mode_nt
			o_txpipe7_pipemode_powerdown                         : out std_logic_vector(3 downto 0);                                                     -- o_txpipe7_pipemode_powerdown
			o_txpipe7_pipemode_rate                              : out std_logic_vector(2 downto 0);                                                     -- o_txpipe7_pipemode_rate
			o_txpipe7_pipemode_rxelecidle_disable_a              : out std_logic;                                                                        -- o_txpipe7_pipemode_rxelecidle_disable_a
			o_txpipe7_pipemode_rxeqclr                           : out std_logic;                                                                        -- o_txpipe7_pipemode_rxeqclr
			o_txpipe7_pipemode_rxeqeval                          : out std_logic;                                                                        -- o_txpipe7_pipemode_rxeqeval
			o_txpipe7_pipemode_rxeqinprogress                    : out std_logic;                                                                        -- o_txpipe7_pipemode_rxeqinprogress
			o_txpipe7_pipemode_rxeqtraining                      : out std_logic;                                                                        -- o_txpipe7_pipemode_rxeqtraining
			o_txpipe7_pipemode_rxpolarity                        : out std_logic;                                                                        -- o_txpipe7_pipemode_rxpolarity
			o_txpipe7_pipemode_rxpresethint                      : out std_logic_vector(2 downto 0);                                                     -- o_txpipe7_pipemode_rxpresethint
			o_txpipe7_pipemode_rxstandby                         : out std_logic;                                                                        -- o_txpipe7_pipemode_rxstandby
			o_txpipe7_pipemode_rxtermination                     : out std_logic;                                                                        -- o_txpipe7_pipemode_rxtermination
			o_txpipe7_pipemode_srisenable                        : out std_logic;                                                                        -- o_txpipe7_pipemode_srisenable
			o_txpipe7_pipemode_txcmnmode_disable_a               : out std_logic;                                                                        -- o_txpipe7_pipemode_txcmnmode_disable_a
			o_txpipe7_pipemode_txcompliance                      : out std_logic;                                                                        -- o_txpipe7_pipemode_txcompliance
			o_txpipe7_pipemode_txdata                            : out std_logic_vector(39 downto 0);                                                    -- o_txpipe7_pipemode_txdata
			o_txpipe7_pipemode_txdatak                           : out std_logic_vector(3 downto 0);                                                     -- o_txpipe7_pipemode_txdatak
			o_txpipe7_pipemode_txdatavalid                       : out std_logic;                                                                        -- o_txpipe7_pipemode_txdatavalid
			o_txpipe7_pipemode_txdeemph                          : out std_logic_vector(17 downto 0);                                                    -- o_txpipe7_pipemode_txdeemph
			o_txpipe7_pipemode_txdtctrx_lb                       : out std_logic;                                                                        -- o_txpipe7_pipemode_txdtctrx_lb
			o_txpipe7_pipemode_txelecidle                        : out std_logic;                                                                        -- o_txpipe7_pipemode_txelecidle
			o_txpipe7_pipemode_txmargin                          : out std_logic_vector(2 downto 0);                                                     -- o_txpipe7_pipemode_txmargin
			o_txpipe7_pipemode_txoneszeros                       : out std_logic;                                                                        -- o_txpipe7_pipemode_txoneszeros
			o_txpipe7_pipemode_txstartblock                      : out std_logic;                                                                        -- o_txpipe7_pipemode_txstartblock
			o_txpipe7_pipemode_txswing                           : out std_logic;                                                                        -- o_txpipe7_pipemode_txswing
			o_txpipe7_pipemode_txsyncheader                      : out std_logic_vector(3 downto 0);                                                     -- o_txpipe7_pipemode_txsyncheader
			o_txpipe7_pipemode_width                             : out std_logic_vector(2 downto 0);                                                     -- o_txpipe7_pipemode_width
			o_pcs0_pipemode_pipe_rst_n                           : out std_logic;                                                                        -- o_pcs0_pipemode_pipe_rst_n
			o_pcs1_pipemode_pipe_rst_n                           : out std_logic;                                                                        -- o_pcs1_pipemode_pipe_rst_n
			o_pcs2_pipemode_pipe_rst_n                           : out std_logic;                                                                        -- o_pcs2_pipemode_pipe_rst_n
			o_pcs3_pipemode_pipe_rst_n                           : out std_logic;                                                                        -- o_pcs3_pipemode_pipe_rst_n
			o_pcs4_pipemode_pipe_rst_n                           : out std_logic;                                                                        -- o_pcs4_pipemode_pipe_rst_n
			o_pcs5_pipemode_pipe_rst_n                           : out std_logic;                                                                        -- o_pcs5_pipemode_pipe_rst_n
			o_pcs6_pipemode_pipe_rst_n                           : out std_logic;                                                                        -- o_pcs6_pipemode_pipe_rst_n
			o_pcs7_pipemode_pipe_rst_n                           : out std_logic;                                                                        -- o_pcs7_pipemode_pipe_rst_n
			i_pcs0_pipemode_pclk                                 : in  std_logic                                                     := 'X'              -- i_pcs0_pipemode_pclk
		);
	end component gts_axi_streaming_pcie_hal_top_2100_jipcchq_cmp;

	for pcie_hal_top : gts_axi_streaming_pcie_hal_top_2100_jipcchq_cmp
		use entity pcie_hal_top_2100.gts_axi_streaming_pcie_hal_top_2100_jipcchq;
begin

	ch0_pcs_l_tx_en_atom_check : if ch0_pcs_l_tx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_pcs_l_rx_en_atom_check : if ch0_pcs_l_rx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_fec_loopback_mode_atom_check : if ch0_fec_loopback_mode_atom /= "CH0_LOOPBACK_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_fec_dyn_tx_mux_atom_check : if ch0_fec_dyn_tx_mux_atom /= "CH0_DYN_TX_MUX_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_fec_error_atom_check : if ch0_fec_error_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_fec_rx_en_atom_check : if ch0_fec_rx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_fec_tx_en_atom_check : if ch0_fec_tx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_fec_mode_atom_check : if ch0_fec_mode_atom /= "CH0_FEC_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_pcs_l_tx_en_atom_check : if ch1_pcs_l_tx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_pcs_l_rx_en_atom_check : if ch1_pcs_l_rx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_fec_loopback_mode_atom_check : if ch1_fec_loopback_mode_atom /= "CH1_LOOPBACK_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_fec_dyn_tx_mux_atom_check : if ch1_fec_dyn_tx_mux_atom /= "CH1_DYN_TX_MUX_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_fec_error_atom_check : if ch1_fec_error_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_fec_rx_en_atom_check : if ch1_fec_rx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_fec_tx_en_atom_check : if ch1_fec_tx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_fec_mode_atom_check : if ch1_fec_mode_atom /= "CH1_FEC_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_pcs_l_tx_en_atom_check : if ch2_pcs_l_tx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_pcs_l_rx_en_atom_check : if ch2_pcs_l_rx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_fec_loopback_mode_atom_check : if ch2_fec_loopback_mode_atom /= "CH2_LOOPBACK_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_fec_dyn_tx_mux_atom_check : if ch2_fec_dyn_tx_mux_atom /= "CH2_DYN_TX_MUX_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_fec_error_atom_check : if ch2_fec_error_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_fec_rx_en_atom_check : if ch2_fec_rx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_fec_tx_en_atom_check : if ch2_fec_tx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_fec_mode_atom_check : if ch2_fec_mode_atom /= "CH2_FEC_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_pcs_l_tx_en_atom_check : if ch3_pcs_l_tx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_pcs_l_rx_en_atom_check : if ch3_pcs_l_rx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_fec_loopback_mode_atom_check : if ch3_fec_loopback_mode_atom /= "CH3_LOOPBACK_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_fec_dyn_tx_mux_atom_check : if ch3_fec_dyn_tx_mux_atom /= "CH3_DYN_TX_MUX_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_fec_error_atom_check : if ch3_fec_error_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_fec_rx_en_atom_check : if ch3_fec_rx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_fec_tx_en_atom_check : if ch3_fec_tx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_fec_mode_atom_check : if ch3_fec_mode_atom /= "CH3_FEC_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_xcvr_rx_prbs_monitor_en_atom_check : if ch0_xcvr_rx_prbs_monitor_en_atom /= "CH0_RX_PRBS_MONITOR_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_xcvr_rx_prbs_monitor_en_atom_check : if ch1_xcvr_rx_prbs_monitor_en_atom /= "CH1_RX_PRBS_MONITOR_EN_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_xcvr_rx_prbs_monitor_en_atom_check : if ch2_xcvr_rx_prbs_monitor_en_atom /= "CH2_RX_PRBS_MONITOR_EN_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_xcvr_rx_prbs_monitor_en_atom_check : if ch3_xcvr_rx_prbs_monitor_en_atom /= "CH3_RX_PRBS_MONITOR_EN_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_tx_prbs_gen_en_atom_check : if ch0_tx_prbs_gen_en_atom /= "CH0_TX_PRBS_GEN_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_tx_prbs_gen_en_atom_check : if ch1_tx_prbs_gen_en_atom /= "CH1_TX_PRBS_GEN_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_tx_prbs_gen_en_atom_check : if ch2_tx_prbs_gen_en_atom /= "CH2_TX_PRBS_GEN_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_tx_prbs_gen_en_atom_check : if ch3_tx_prbs_gen_en_atom /= "CH3_TX_PRBS_GEN_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_rx_user1_clk_mux_dynamic_sel_atom_check : if ch0_rx_user1_clk_mux_dynamic_sel_atom /= "CH0_RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_rx_user2_clk_mux_dynamic_sel_atom_check : if ch0_rx_user2_clk_mux_dynamic_sel_atom /= "CH0_RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_tx_user1_clk_mux_dynamic_sel_atom_check : if ch0_tx_user1_clk_mux_dynamic_sel_atom /= "CH0_TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_tx_user2_clk_mux_dynamic_sel_atom_check : if ch0_tx_user2_clk_mux_dynamic_sel_atom /= "CH0_TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_rx_user1_clk_mux_dynamic_sel_atom_check : if ch1_rx_user1_clk_mux_dynamic_sel_atom /= "CH1_RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_rx_user2_clk_mux_dynamic_sel_atom_check : if ch1_rx_user2_clk_mux_dynamic_sel_atom /= "CH1_RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_tx_user1_clk_mux_dynamic_sel_atom_check : if ch1_tx_user1_clk_mux_dynamic_sel_atom /= "CH1_TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_tx_user2_clk_mux_dynamic_sel_atom_check : if ch1_tx_user2_clk_mux_dynamic_sel_atom /= "CH1_TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_rx_user1_clk_mux_dynamic_sel_atom_check : if ch2_rx_user1_clk_mux_dynamic_sel_atom /= "CH2_RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_rx_user2_clk_mux_dynamic_sel_atom_check : if ch2_rx_user2_clk_mux_dynamic_sel_atom /= "CH2_RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_tx_user1_clk_mux_dynamic_sel_atom_check : if ch2_tx_user1_clk_mux_dynamic_sel_atom /= "CH2_TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_tx_user2_clk_mux_dynamic_sel_atom_check : if ch2_tx_user2_clk_mux_dynamic_sel_atom /= "CH2_TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_rx_user1_clk_mux_dynamic_sel_atom_check : if ch3_rx_user1_clk_mux_dynamic_sel_atom /= "CH3_RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_rx_user2_clk_mux_dynamic_sel_atom_check : if ch3_rx_user2_clk_mux_dynamic_sel_atom /= "CH3_RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_tx_user1_clk_mux_dynamic_sel_atom_check : if ch3_tx_user1_clk_mux_dynamic_sel_atom /= "CH3_TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_tx_user2_clk_mux_dynamic_sel_atom_check : if ch3_tx_user2_clk_mux_dynamic_sel_atom /= "CH3_TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_pcie_mode_atom_check : if ch0_pcie_mode_atom /= "CH0_PCIE_MODE_GEN3" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_pcie_mode_atom_check : if ch1_pcie_mode_atom /= "CH1_PCIE_MODE_GEN3" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_pcie_mode_atom_check : if ch2_pcie_mode_atom /= "CH2_PCIE_MODE_GEN3" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_pcie_mode_atom_check : if ch3_pcie_mode_atom /= "CH3_PCIE_MODE_GEN3" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_xcvr_rx_protocol_hint_atom_check : if ch0_xcvr_rx_protocol_hint_atom /= "CH0_RX_PROTOCOL_HINT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_xcvr_rx_protocol_hint_atom_check : if ch1_xcvr_rx_protocol_hint_atom /= "CH1_RX_PROTOCOL_HINT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_xcvr_rx_protocol_hint_atom_check : if ch2_xcvr_rx_protocol_hint_atom /= "CH2_RX_PROTOCOL_HINT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_xcvr_rx_protocol_hint_atom_check : if ch3_xcvr_rx_protocol_hint_atom /= "CH3_RX_PROTOCOL_HINT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_clkrx_refclk_cssm_fw_control_atom_check : if ch0_clkrx_refclk_cssm_fw_control_atom /= "CH0_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_clkrx_refclk_cssm_fw_control_atom_check : if ch1_clkrx_refclk_cssm_fw_control_atom /= "CH1_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_clkrx_refclk_cssm_fw_control_atom_check : if ch2_clkrx_refclk_cssm_fw_control_atom /= "CH2_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_clkrx_refclk_cssm_fw_control_atom_check : if ch3_clkrx_refclk_cssm_fw_control_atom /= "CH3_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_clkrx_refclk_sector_specifies_refclk_ready_atom_check : if ch0_clkrx_refclk_sector_specifies_refclk_ready_atom /= "CH0_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_clkrx_refclk_sector_specifies_refclk_ready_atom_check : if ch1_clkrx_refclk_sector_specifies_refclk_ready_atom /= "CH1_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_clkrx_refclk_sector_specifies_refclk_ready_atom_check : if ch2_clkrx_refclk_sector_specifies_refclk_ready_atom /= "CH2_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_clkrx_refclk_sector_specifies_refclk_ready_atom_check : if ch3_clkrx_refclk_sector_specifies_refclk_ready_atom /= "CH3_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_local_refclk_cssm_fw_control_atom_check : if ch0_local_refclk_cssm_fw_control_atom /= "CH0_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_local_refclk_cssm_fw_control_atom_check : if ch1_local_refclk_cssm_fw_control_atom /= "CH1_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_local_refclk_cssm_fw_control_atom_check : if ch2_local_refclk_cssm_fw_control_atom /= "CH2_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_local_refclk_cssm_fw_control_atom_check : if ch3_local_refclk_cssm_fw_control_atom /= "CH3_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_local_refclk_sector_specifies_refclk_ready_atom_check : if ch0_local_refclk_sector_specifies_refclk_ready_atom /= "CH0_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_local_refclk_sector_specifies_refclk_ready_atom_check : if ch1_local_refclk_sector_specifies_refclk_ready_atom /= "CH1_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_local_refclk_sector_specifies_refclk_ready_atom_check : if ch2_local_refclk_sector_specifies_refclk_ready_atom /= "CH2_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_local_refclk_sector_specifies_refclk_ready_atom_check : if ch3_local_refclk_sector_specifies_refclk_ready_atom /= "CH3_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_tx_bonding_category_atom_check : if ch0_tx_bonding_category_atom /= "CH0_TX_BONDING_CATEGORY_BONDING_LEADER" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_tx_bonding_category_atom_check : if ch1_tx_bonding_category_atom /= "CH1_TX_BONDING_CATEGORY_BONDING_FOLLOWER" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_tx_bonding_category_atom_check : if ch2_tx_bonding_category_atom /= "CH2_TX_BONDING_CATEGORY_BONDING_FOLLOWER" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_tx_bonding_category_atom_check : if ch3_tx_bonding_category_atom /= "CH3_TX_BONDING_CATEGORY_BONDING_FOLLOWER" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	hal_num_of_lanes_hwtcl_check : if hal_num_of_lanes_hwtcl /= 4 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	is_sm4_sm7_reva_check : if is_sm4_sm7_revA /= 1 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_duplex_mode_atom_check : if ch0_duplex_mode_atom /= "CH0_DUPLEX_MODE_DUPLEX" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_fec_spec_atom_check : if ch0_fec_spec_atom /= "CH0_FEC_SPEC_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_fracture_atom_check : if ch0_fracture_atom /= "CH0_FRACTURE_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_dr_enabled_atom_check : if ch0_dr_enabled_atom /= "CH0_DR_ENABLED_DR_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_sup_mode_atom_check : if ch0_sup_mode_atom /= "CH0_SUP_MODE_USER_MODE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_sim_mode_atom_check : if ch0_sim_mode_atom /= "CH0_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_duplex_mode_atom_check : if ch1_duplex_mode_atom /= "CH1_DUPLEX_MODE_DUPLEX" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_fec_spec_atom_check : if ch1_fec_spec_atom /= "CH1_FEC_SPEC_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_fracture_atom_check : if ch1_fracture_atom /= "CH1_FRACTURE_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_dr_enabled_atom_check : if ch1_dr_enabled_atom /= "CH1_DR_ENABLED_DR_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_sup_mode_atom_check : if ch1_sup_mode_atom /= "CH1_SUP_MODE_USER_MODE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_sim_mode_atom_check : if ch1_sim_mode_atom /= "CH1_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_duplex_mode_atom_check : if ch2_duplex_mode_atom /= "CH2_DUPLEX_MODE_DUPLEX" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_fec_spec_atom_check : if ch2_fec_spec_atom /= "CH2_FEC_SPEC_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_fracture_atom_check : if ch2_fracture_atom /= "CH2_FRACTURE_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_dr_enabled_atom_check : if ch2_dr_enabled_atom /= "CH2_DR_ENABLED_DR_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_sup_mode_atom_check : if ch2_sup_mode_atom /= "CH2_SUP_MODE_USER_MODE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_sim_mode_atom_check : if ch2_sim_mode_atom /= "CH2_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_duplex_mode_atom_check : if ch3_duplex_mode_atom /= "CH3_DUPLEX_MODE_DUPLEX" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_fec_spec_atom_check : if ch3_fec_spec_atom /= "CH3_FEC_SPEC_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_fracture_atom_check : if ch3_fracture_atom /= "CH3_FRACTURE_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_dr_enabled_atom_check : if ch3_dr_enabled_atom /= "CH3_DR_ENABLED_DR_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_sup_mode_atom_check : if ch3_sup_mode_atom /= "CH3_SUP_MODE_USER_MODE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_sim_mode_atom_check : if ch3_sim_mode_atom /= "CH3_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_xcvr_tx_preloaded_hardware_configs_atom_check : if ch0_xcvr_tx_preloaded_hardware_configs_atom /= "CH0_TX_PRELOADED_HARDWARE_CONFIGS_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_xcvr_rx_preloaded_hardware_configs_atom_check : if ch0_xcvr_rx_preloaded_hardware_configs_atom /= "CH0_RX_PRELOADED_HARDWARE_CONFIGS_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_lc_postdiv_sel_atom_check : if ch0_lc_postdiv_sel_atom /= "CH0_LC_POSTDIV_SEL_SYNTH2" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_sequencer_reg_en_atom_check : if ch0_sequencer_reg_en_atom /= "CH0_SEQUENCER_REG_EN_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_rst_mux_static_sel_atom_check : if ch0_rst_mux_static_sel_atom /= "CH0_RST_MUX_STATIC_SEL_HRC" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_xcvr_tx_prbs_pattern_atom_check : if ch0_xcvr_tx_prbs_pattern_atom /= "0000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_xcvr_rx_prbs_pattern_atom_check : if ch0_xcvr_rx_prbs_pattern_atom /= "0000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_xcvr_tx_user_clk_only_mode_atom_check : if ch0_xcvr_tx_user_clk_only_mode_atom /= "CH0_TX_USER_CLK_ONLY_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_xcvr_tx_width_atom_check : if ch0_xcvr_tx_width_atom /= "CH0_TX_WIDTH_X16" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_xcvr_rx_width_atom_check : if ch0_xcvr_rx_width_atom /= "CH0_RX_WIDTH_X16" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_phy_loopback_mode_atom_check : if ch0_phy_loopback_mode_atom /= "CH0_LOOPBACK_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_flux_mode_atom_check : if ch0_flux_mode_atom /= "CH0_FLUX_MODE_FLUX_MODE_BYPASS" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_flux_mode_hw_atom_check : if ch0_flux_mode_hw_atom /= "CH0_FLUX_MODE_FLUX_MODE_BYPASS" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_tx_sim_mode_atom_check : if ch0_tx_sim_mode_atom /= "CH0_TX_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_rx_sim_mode_atom_check : if ch0_rx_sim_mode_atom /= "CH0_RX_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_tx_dl_enable_atom_check : if ch0_tx_dl_enable_atom /= "CH0_TX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_rx_dl_enable_atom_check : if ch0_rx_dl_enable_atom /= "CH0_RX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_rx_fec_type_used_atom_check : if ch0_rx_fec_type_used_atom /= "CH0_RX_FEC_TYPE_USED_NONE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_xcvr_tx_preloaded_hardware_configs_atom_check : if ch1_xcvr_tx_preloaded_hardware_configs_atom /= "CH1_TX_PRELOADED_HARDWARE_CONFIGS_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_xcvr_rx_preloaded_hardware_configs_atom_check : if ch1_xcvr_rx_preloaded_hardware_configs_atom /= "CH1_RX_PRELOADED_HARDWARE_CONFIGS_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_lc_postdiv_sel_atom_check : if ch1_lc_postdiv_sel_atom /= "CH1_LC_POSTDIV_SEL_SYNTH2" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_sequencer_reg_en_atom_check : if ch1_sequencer_reg_en_atom /= "CH1_SEQUENCER_REG_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_rst_mux_static_sel_atom_check : if ch1_rst_mux_static_sel_atom /= "CH1_RST_MUX_STATIC_SEL_HRC" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_xcvr_tx_prbs_pattern_atom_check : if ch1_xcvr_tx_prbs_pattern_atom /= "0000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_xcvr_rx_prbs_pattern_atom_check : if ch1_xcvr_rx_prbs_pattern_atom /= "0001" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_xcvr_tx_user_clk_only_mode_atom_check : if ch1_xcvr_tx_user_clk_only_mode_atom /= "CH1_TX_USER_CLK_ONLY_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_xcvr_tx_width_atom_check : if ch1_xcvr_tx_width_atom /= "CH1_TX_WIDTH_X16" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_xcvr_rx_width_atom_check : if ch1_xcvr_rx_width_atom /= "CH1_RX_WIDTH_X16" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_phy_loopback_mode_atom_check : if ch1_phy_loopback_mode_atom /= "CH1_LOOPBACK_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_flux_mode_atom_check : if ch1_flux_mode_atom /= "CH1_FLUX_MODE_FLUX_MODE_BYPASS" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_flux_mode_hw_atom_check : if ch1_flux_mode_hw_atom /= "CH1_FLUX_MODE_FLUX_MODE_BYPASS" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_tx_sim_mode_atom_check : if ch1_tx_sim_mode_atom /= "CH1_TX_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_rx_sim_mode_atom_check : if ch1_rx_sim_mode_atom /= "CH1_RX_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_tx_dl_enable_atom_check : if ch1_tx_dl_enable_atom /= "CH1_TX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_rx_dl_enable_atom_check : if ch1_rx_dl_enable_atom /= "CH1_RX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_rx_fec_type_used_atom_check : if ch1_rx_fec_type_used_atom /= "CH1_RX_FEC_TYPE_USED_NONE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_xcvr_tx_preloaded_hardware_configs_atom_check : if ch2_xcvr_tx_preloaded_hardware_configs_atom /= "CH2_TX_PRELOADED_HARDWARE_CONFIGS_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_xcvr_rx_preloaded_hardware_configs_atom_check : if ch2_xcvr_rx_preloaded_hardware_configs_atom /= "CH2_RX_PRELOADED_HARDWARE_CONFIGS_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_lc_postdiv_sel_atom_check : if ch2_lc_postdiv_sel_atom /= "CH2_LC_POSTDIV_SEL_SYNTH2" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_sequencer_reg_en_atom_check : if ch2_sequencer_reg_en_atom /= "CH2_SEQUENCER_REG_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_rst_mux_static_sel_atom_check : if ch2_rst_mux_static_sel_atom /= "CH2_RST_MUX_STATIC_SEL_HRC" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_xcvr_tx_prbs_pattern_atom_check : if ch2_xcvr_tx_prbs_pattern_atom /= "0000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_xcvr_rx_prbs_pattern_atom_check : if ch2_xcvr_rx_prbs_pattern_atom /= "0011" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_xcvr_tx_user_clk_only_mode_atom_check : if ch2_xcvr_tx_user_clk_only_mode_atom /= "CH2_TX_USER_CLK_ONLY_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_xcvr_tx_width_atom_check : if ch2_xcvr_tx_width_atom /= "CH2_TX_WIDTH_X16" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_xcvr_rx_width_atom_check : if ch2_xcvr_rx_width_atom /= "CH2_RX_WIDTH_X16" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_phy_loopback_mode_atom_check : if ch2_phy_loopback_mode_atom /= "CH2_LOOPBACK_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_flux_mode_atom_check : if ch2_flux_mode_atom /= "CH2_FLUX_MODE_FLUX_MODE_BYPASS" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_flux_mode_hw_atom_check : if ch2_flux_mode_hw_atom /= "CH2_FLUX_MODE_FLUX_MODE_BYPASS" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_tx_sim_mode_atom_check : if ch2_tx_sim_mode_atom /= "CH2_TX_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_rx_sim_mode_atom_check : if ch2_rx_sim_mode_atom /= "CH2_RX_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_tx_dl_enable_atom_check : if ch2_tx_dl_enable_atom /= "CH2_TX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_rx_dl_enable_atom_check : if ch2_rx_dl_enable_atom /= "CH2_RX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_rx_fec_type_used_atom_check : if ch2_rx_fec_type_used_atom /= "CH2_RX_FEC_TYPE_USED_NONE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_xcvr_tx_preloaded_hardware_configs_atom_check : if ch3_xcvr_tx_preloaded_hardware_configs_atom /= "CH3_TX_PRELOADED_HARDWARE_CONFIGS_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_xcvr_rx_preloaded_hardware_configs_atom_check : if ch3_xcvr_rx_preloaded_hardware_configs_atom /= "CH3_RX_PRELOADED_HARDWARE_CONFIGS_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_lc_postdiv_sel_atom_check : if ch3_lc_postdiv_sel_atom /= "CH3_LC_POSTDIV_SEL_SYNTH2" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_sequencer_reg_en_atom_check : if ch3_sequencer_reg_en_atom /= "CH3_SEQUENCER_REG_EN_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_rst_mux_static_sel_atom_check : if ch3_rst_mux_static_sel_atom /= "CH3_RST_MUX_STATIC_SEL_HRC" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_xcvr_tx_prbs_pattern_atom_check : if ch3_xcvr_tx_prbs_pattern_atom /= "0000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_xcvr_rx_prbs_pattern_atom_check : if ch3_xcvr_rx_prbs_pattern_atom /= "0111" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_xcvr_tx_user_clk_only_mode_atom_check : if ch3_xcvr_tx_user_clk_only_mode_atom /= "CH3_TX_USER_CLK_ONLY_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_xcvr_tx_width_atom_check : if ch3_xcvr_tx_width_atom /= "CH3_TX_WIDTH_X16" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_xcvr_rx_width_atom_check : if ch3_xcvr_rx_width_atom /= "CH3_RX_WIDTH_X16" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_phy_loopback_mode_atom_check : if ch3_phy_loopback_mode_atom /= "CH3_LOOPBACK_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_flux_mode_atom_check : if ch3_flux_mode_atom /= "CH3_FLUX_MODE_FLUX_MODE_BYPASS" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_flux_mode_hw_atom_check : if ch3_flux_mode_hw_atom /= "CH3_FLUX_MODE_FLUX_MODE_BYPASS" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_tx_sim_mode_atom_check : if ch3_tx_sim_mode_atom /= "CH3_TX_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_rx_sim_mode_atom_check : if ch3_rx_sim_mode_atom /= "CH3_RX_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_tx_dl_enable_atom_check : if ch3_tx_dl_enable_atom /= "CH3_TX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_rx_dl_enable_atom_check : if ch3_rx_dl_enable_atom /= "CH3_RX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_rx_fec_type_used_atom_check : if ch3_rx_fec_type_used_atom /= "CH3_RX_FEC_TYPE_USED_NONE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_tx_pll_l_counter_atom_check : if ch0_tx_pll_l_counter_atom /= "000010" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_cdr_l_counter_atom_check : if ch0_cdr_l_counter_atom /= "000010" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_tx_pll_refclk_select_atom_check : if ch0_tx_pll_refclk_select_atom /= "CH0_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_cdr_refclk_select_atom_check : if ch0_cdr_refclk_select_atom /= "CH0_CDR_REFCLK_SELECT_GLOBAL_REFCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_tx_pll_l_counter_atom_check : if ch1_tx_pll_l_counter_atom /= "000010" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_cdr_l_counter_atom_check : if ch1_cdr_l_counter_atom /= "000010" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_tx_pll_refclk_select_atom_check : if ch1_tx_pll_refclk_select_atom /= "CH1_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_cdr_refclk_select_atom_check : if ch1_cdr_refclk_select_atom /= "CH1_CDR_REFCLK_SELECT_GLOBAL_REFCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_tx_pll_l_counter_atom_check : if ch2_tx_pll_l_counter_atom /= "000010" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_cdr_l_counter_atom_check : if ch2_cdr_l_counter_atom /= "000010" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_tx_pll_refclk_select_atom_check : if ch2_tx_pll_refclk_select_atom /= "CH2_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_cdr_refclk_select_atom_check : if ch2_cdr_refclk_select_atom /= "CH2_CDR_REFCLK_SELECT_GLOBAL_REFCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_tx_pll_l_counter_atom_check : if ch3_tx_pll_l_counter_atom /= "000010" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_cdr_l_counter_atom_check : if ch3_cdr_l_counter_atom /= "000010" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_tx_pll_refclk_select_atom_check : if ch3_tx_pll_refclk_select_atom /= "CH3_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_cdr_refclk_select_atom_check : if ch3_cdr_refclk_select_atom /= "CH3_CDR_REFCLK_SELECT_GLOBAL_REFCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_rx_dl_rx_lat_bit_for_async_atom_check : if ch0_rx_dl_rx_lat_bit_for_async_atom /= "010100000100010011" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_rx_dl_rxbit_cntr_pma_atom_check : if ch0_rx_dl_rxbit_cntr_pma_atom /= "CH0_RX_DL_RXBIT_CNTR_PMA_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_rx_dl_rxbit_rollover_atom_check : if ch0_rx_dl_rxbit_rollover_atom /= "111110100100001111" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_rx_dl_rx_lat_bit_for_async_atom_check : if ch1_rx_dl_rx_lat_bit_for_async_atom /= "111110100110100101" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_rx_dl_rxbit_cntr_pma_atom_check : if ch1_rx_dl_rxbit_cntr_pma_atom /= "CH1_RX_DL_RXBIT_CNTR_PMA_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_rx_dl_rxbit_rollover_atom_check : if ch1_rx_dl_rxbit_rollover_atom /= "001001111001000101" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_rx_dl_rx_lat_bit_for_async_atom_check : if ch2_rx_dl_rx_lat_bit_for_async_atom /= "111010100000111101" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_rx_dl_rxbit_cntr_pma_atom_check : if ch2_rx_dl_rxbit_cntr_pma_atom /= "CH2_RX_DL_RXBIT_CNTR_PMA_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_rx_dl_rxbit_rollover_atom_check : if ch2_rx_dl_rxbit_rollover_atom /= "111000111110011110" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_rx_dl_rx_lat_bit_for_async_atom_check : if ch3_rx_dl_rx_lat_bit_for_async_atom /= "100000100111100001" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_rx_dl_rxbit_cntr_pma_atom_check : if ch3_rx_dl_rxbit_cntr_pma_atom /= "CH3_RX_DL_RXBIT_CNTR_PMA_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_rx_dl_rxbit_rollover_atom_check : if ch3_rx_dl_rxbit_rollover_atom /= "001101111001101011" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_tx_bond_size_atom_check : if ch0_tx_bond_size_atom /= "CH0_TX_BOND_SIZE_X4" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_tx_bond_size_atom_check : if ch1_tx_bond_size_atom /= "CH1_TX_BOND_SIZE_X4" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_tx_bond_size_atom_check : if ch2_tx_bond_size_atom /= "CH2_TX_BOND_SIZE_X4" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_tx_bond_size_atom_check : if ch3_tx_bond_size_atom /= "CH3_TX_BOND_SIZE_X4" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_rx_invert_pin_atom_check : if ch0_rx_invert_pin_atom /= "CH0_RX_INVERT_PIN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_rx_invert_pin_atom_check : if ch1_rx_invert_pin_atom /= "CH1_RX_INVERT_PIN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_rx_invert_pin_atom_check : if ch2_rx_invert_pin_atom /= "CH2_RX_INVERT_PIN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_rx_invert_pin_atom_check : if ch3_rx_invert_pin_atom /= "CH3_RX_INVERT_PIN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_tx_invert_pin_atom_check : if ch0_tx_invert_pin_atom /= "CH0_TX_INVERT_PIN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_tx_invert_pin_atom_check : if ch1_tx_invert_pin_atom /= "CH1_TX_INVERT_PIN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_tx_invert_pin_atom_check : if ch2_tx_invert_pin_atom /= "CH2_TX_INVERT_PIN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_tx_invert_pin_atom_check : if ch3_tx_invert_pin_atom /= "CH3_TX_INVERT_PIN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch0_vsr_mode_atom_check : if ch0_vsr_mode_atom /= "CH0_VSR_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch1_vsr_mode_atom_check : if ch1_vsr_mode_atom /= "CH1_VSR_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch2_vsr_mode_atom_check : if ch2_vsr_mode_atom /= "CH2_VSR_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch3_vsr_mode_atom_check : if ch3_vsr_mode_atom /= "CH3_VSR_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pcie_parity_bypass_check : if pcie_parity_bypass /= "true" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	rxbuf_limit_bypass_check : if rxbuf_limit_bypass /= 7 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	maxpayload_size_check : if maxpayload_size /= "MAXPAYLOAD_SIZE_MAX_PAYLOAD_512" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pldclk_rate_check : if pldclk_rate /= "PLDCLK_RATE_FAST" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	port_type_check : if port_type /= "PORT_TYPE_RP" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sris_enable_check : if sris_enable /= "SRIS_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	link_num_check : if link_num /= "SRIS_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sris_mode_check : if sris_mode /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sim_mode_check : if sim_mode /= "SIM_MODE_DISABLE_VSIM_MODE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sup_mode_check : if sup_mode /= "SUP_MODE_USER_MODE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	cvp_enable_check : if cvp_enable /= "CVP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	cii_monitor_en_check : if cii_monitor_en /= "CII_MONITOR_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pclk_clk_hz_check : if pclk_clk_hz /= "00011101110011010110010100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_cap_link_surprise_down_err_cap_check : if pf0_cap_link_surprise_down_err_cap /= "PF0_CAP_LINK_SURPRISE_DOWN_ERR_CAP_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_clk_hz_check : if sys_clk_hz /= "00010001111000011010001100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	link_rate_check : if link_rate /= "LINK_RATE_GEN3" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	link_width_check : if link_width /= "LINK_WIDTH_X4" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	num_of_lanes_check : if num_of_lanes /= "NUM_OF_LANES_NUM_4" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset0_check : if pf0_dsp_16g_tx_preset0 /= 7 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset1_check : if pf0_dsp_16g_tx_preset1 /= 7 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset2_check : if pf0_dsp_16g_tx_preset2 /= 7 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset3_check : if pf0_dsp_16g_tx_preset3 /= 7 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset4_check : if pf0_dsp_16g_tx_preset4 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset5_check : if pf0_dsp_16g_tx_preset5 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset6_check : if pf0_dsp_16g_tx_preset6 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset7_check : if pf0_dsp_16g_tx_preset7 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset8_check : if pf0_dsp_16g_tx_preset8 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset9_check : if pf0_dsp_16g_tx_preset9 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset10_check : if pf0_dsp_16g_tx_preset10 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset11_check : if pf0_dsp_16g_tx_preset11 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset12_check : if pf0_dsp_16g_tx_preset12 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset13_check : if pf0_dsp_16g_tx_preset13 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset14_check : if pf0_dsp_16g_tx_preset14 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_16g_tx_preset15_check : if pf0_dsp_16g_tx_preset15 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset0_check : if pf0_dsp_tx_preset0 /= 9 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset1_check : if pf0_dsp_tx_preset1 /= 9 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset2_check : if pf0_dsp_tx_preset2 /= 9 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset3_check : if pf0_dsp_tx_preset3 /= 9 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset4_check : if pf0_dsp_tx_preset4 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset5_check : if pf0_dsp_tx_preset5 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset6_check : if pf0_dsp_tx_preset6 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset7_check : if pf0_dsp_tx_preset7 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset8_check : if pf0_dsp_tx_preset8 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset9_check : if pf0_dsp_tx_preset9 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset10_check : if pf0_dsp_tx_preset10 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset11_check : if pf0_dsp_tx_preset11 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset12_check : if pf0_dsp_tx_preset12 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset13_check : if pf0_dsp_tx_preset13 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset14_check : if pf0_dsp_tx_preset14 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_dsp_tx_preset15_check : if pf0_dsp_tx_preset15 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset0_check : if pf0_usp_16g_tx_preset0 /= 7 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset1_check : if pf0_usp_16g_tx_preset1 /= 7 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset2_check : if pf0_usp_16g_tx_preset2 /= 7 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset3_check : if pf0_usp_16g_tx_preset3 /= 7 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset4_check : if pf0_usp_16g_tx_preset4 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset5_check : if pf0_usp_16g_tx_preset5 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset6_check : if pf0_usp_16g_tx_preset6 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset7_check : if pf0_usp_16g_tx_preset7 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset8_check : if pf0_usp_16g_tx_preset8 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset9_check : if pf0_usp_16g_tx_preset9 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset10_check : if pf0_usp_16g_tx_preset10 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset11_check : if pf0_usp_16g_tx_preset11 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset12_check : if pf0_usp_16g_tx_preset12 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset13_check : if pf0_usp_16g_tx_preset13 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset14_check : if pf0_usp_16g_tx_preset14 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_16g_tx_preset15_check : if pf0_usp_16g_tx_preset15 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset0_check : if pf0_usp_tx_preset0 /= 9 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset1_check : if pf0_usp_tx_preset1 /= 9 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset2_check : if pf0_usp_tx_preset2 /= 9 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset3_check : if pf0_usp_tx_preset3 /= 9 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset4_check : if pf0_usp_tx_preset4 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset5_check : if pf0_usp_tx_preset5 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset6_check : if pf0_usp_tx_preset6 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset7_check : if pf0_usp_tx_preset7 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset8_check : if pf0_usp_tx_preset8 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset9_check : if pf0_usp_tx_preset9 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset10_check : if pf0_usp_tx_preset10 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset11_check : if pf0_usp_tx_preset11 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset12_check : if pf0_usp_tx_preset12 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset13_check : if pf0_usp_tx_preset13 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset14_check : if pf0_usp_tx_preset14 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_usp_tx_preset15_check : if pf0_usp_tx_preset15 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_bar0_enabled_check : if pf0_pci_type0_bar0_enabled /= "PF0_PCI_TYPE0_BAR0_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_bar0_mask_31_1_check : if pf0_pci_type0_bar0_mask_31_1 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_bar0_prefetch_check : if pf0_bar0_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_bar0_type_check : if pf0_bar0_type /= "PF0_BAR0_TYPE_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_bar1_enabled_check : if pf0_pci_type0_bar1_enabled /= "PF0_PCI_TYPE0_BAR1_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_bar1_mask_31_0_check : if pf0_pci_type0_bar1_mask_31_0 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_bar1_prefetch_check : if pf0_bar1_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_bar2_enabled_check : if pf0_pci_type0_bar2_enabled /= "PF0_PCI_TYPE0_BAR2_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_bar2_mask_31_1_check : if pf0_pci_type0_bar2_mask_31_1 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_bar2_prefetch_check : if pf0_bar2_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_bar2_type_check : if pf0_bar2_type /= "PF0_BAR2_TYPE_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_bar3_enabled_check : if pf0_pci_type0_bar3_enabled /= "PF0_PCI_TYPE0_BAR3_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_bar3_mask_31_0_check : if pf0_pci_type0_bar3_mask_31_0 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_bar3_prefetch_check : if pf0_bar3_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_bar4_enabled_check : if pf0_pci_type0_bar4_enabled /= "PF0_PCI_TYPE0_BAR4_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_bar4_mask_31_1_check : if pf0_pci_type0_bar4_mask_31_1 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_bar4_prefetch_check : if pf0_bar4_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_bar4_type_check : if pf0_bar4_type /= "PF0_BAR4_TYPE_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_bar5_enabled_check : if pf0_pci_type0_bar5_enabled /= "PF0_PCI_TYPE0_BAR5_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_bar5_mask_31_0_check : if pf0_pci_type0_bar5_mask_31_0 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_bar5_prefetch_check : if pf0_bar5_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_rom_bar_enable_check : if pf0_rom_bar_enable /= "PF0_ROM_BAR_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_rom_mask_check : if pf0_rom_mask /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_rom_bar_enabled_check : if pf0_rom_bar_enabled /= "PF0_ROM_BAR_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_rp_rom_bar_enabled_check : if pf0_rp_rom_bar_enabled /= "PF0_RP_ROM_BAR_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_rp_rom_mask_check : if pf0_rp_rom_mask /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar0_enabled_check : if pf0_sriov_vf_bar0_enabled /= "PF0_SRIOV_VF_BAR0_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar0_mask_check : if pf0_sriov_vf_bar0_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar0_prefetch_check : if pf0_sriov_vf_bar0_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar0_type_check : if pf0_sriov_vf_bar0_type /= "PF0_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar1_enabled_check : if pf0_sriov_vf_bar1_enabled /= "PF0_SRIOV_VF_BAR1_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar1_mask_check : if pf0_sriov_vf_bar1_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar1_prefetch_check : if pf0_sriov_vf_bar1_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar2_enabled_check : if pf0_sriov_vf_bar2_enabled /= "PF0_SRIOV_VF_BAR2_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar2_mask_check : if pf0_sriov_vf_bar2_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar2_prefetch_check : if pf0_sriov_vf_bar2_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar2_type_check : if pf0_sriov_vf_bar2_type /= "PF0_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar3_enabled_check : if pf0_sriov_vf_bar3_enabled /= "PF0_SRIOV_VF_BAR3_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar3_mask_check : if pf0_sriov_vf_bar3_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar3_prefetch_check : if pf0_sriov_vf_bar3_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar4_enabled_check : if pf0_sriov_vf_bar4_enabled /= "PF0_SRIOV_VF_BAR4_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar4_mask_check : if pf0_sriov_vf_bar4_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar4_prefetch_check : if pf0_sriov_vf_bar4_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar4_type_check : if pf0_sriov_vf_bar4_type /= "PF0_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar5_enabled_check : if pf0_sriov_vf_bar5_enabled /= "PF0_SRIOV_VF_BAR5_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar5_mask_check : if pf0_sriov_vf_bar5_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_bar5_prefetch_check : if pf0_sriov_vf_bar5_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_bar0_enabled_check : if pf1_pci_type0_bar0_enabled /= "PF1_PCI_TYPE0_BAR0_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_bar0_mask_31_1_check : if pf1_pci_type0_bar0_mask_31_1 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_bar0_prefetch_check : if pf1_bar0_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_bar0_type_check : if pf1_bar0_type /= "PF1_BAR0_TYPE_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_bar1_enabled_check : if pf1_pci_type0_bar1_enabled /= "PF1_PCI_TYPE0_BAR1_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_bar1_mask_31_0_check : if pf1_pci_type0_bar1_mask_31_0 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_bar1_prefetch_check : if pf1_bar1_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_bar2_enabled_check : if pf1_pci_type0_bar2_enabled /= "PF1_PCI_TYPE0_BAR2_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_bar2_mask_31_1_check : if pf1_pci_type0_bar2_mask_31_1 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_bar2_prefetch_check : if pf1_bar2_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_bar2_type_check : if pf1_bar2_type /= "PF1_BAR2_TYPE_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_bar3_enabled_check : if pf1_pci_type0_bar3_enabled /= "PF1_PCI_TYPE0_BAR3_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_bar3_mask_31_0_check : if pf1_pci_type0_bar3_mask_31_0 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_bar3_prefetch_check : if pf1_bar3_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_bar4_enabled_check : if pf1_pci_type0_bar4_enabled /= "PF1_PCI_TYPE0_BAR4_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_bar4_mask_31_1_check : if pf1_pci_type0_bar4_mask_31_1 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_bar4_prefetch_check : if pf1_bar4_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_bar4_type_check : if pf1_bar4_type /= "PF1_BAR4_TYPE_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_bar5_enabled_check : if pf1_pci_type0_bar5_enabled /= "PF1_PCI_TYPE0_BAR5_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_bar5_mask_31_0_check : if pf1_pci_type0_bar5_mask_31_0 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_bar5_prefetch_check : if pf1_bar5_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_rom_bar_enable_check : if pf1_rom_bar_enable /= "PF1_ROM_BAR_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_rom_mask_check : if pf1_rom_mask /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_rom_bar_enabled_check : if pf1_rom_bar_enabled /= "PF1_ROM_BAR_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar0_enabled_check : if pf1_sriov_vf_bar0_enabled /= "PF1_SRIOV_VF_BAR0_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar0_mask_check : if pf1_sriov_vf_bar0_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar0_prefetch_check : if pf1_sriov_vf_bar0_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar0_type_check : if pf1_sriov_vf_bar0_type /= "PF1_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar1_enabled_check : if pf1_sriov_vf_bar1_enabled /= "PF1_SRIOV_VF_BAR1_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar1_mask_check : if pf1_sriov_vf_bar1_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar1_prefetch_check : if pf1_sriov_vf_bar1_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar2_enabled_check : if pf1_sriov_vf_bar2_enabled /= "PF1_SRIOV_VF_BAR2_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar2_mask_check : if pf1_sriov_vf_bar2_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar2_prefetch_check : if pf1_sriov_vf_bar2_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar2_type_check : if pf1_sriov_vf_bar2_type /= "PF1_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar3_enabled_check : if pf1_sriov_vf_bar3_enabled /= "PF1_SRIOV_VF_BAR3_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar3_mask_check : if pf1_sriov_vf_bar3_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar3_prefetch_check : if pf1_sriov_vf_bar3_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar4_enabled_check : if pf1_sriov_vf_bar4_enabled /= "PF1_SRIOV_VF_BAR4_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar4_mask_check : if pf1_sriov_vf_bar4_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar4_prefetch_check : if pf1_sriov_vf_bar4_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar4_type_check : if pf1_sriov_vf_bar4_type /= "PF1_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar5_enabled_check : if pf1_sriov_vf_bar5_enabled /= "PF1_SRIOV_VF_BAR5_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar5_mask_check : if pf1_sriov_vf_bar5_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_bar5_prefetch_check : if pf1_sriov_vf_bar5_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_bar0_enabled_check : if pf2_pci_type0_bar0_enabled /= "PF2_PCI_TYPE0_BAR0_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_bar0_mask_31_1_check : if pf2_pci_type0_bar0_mask_31_1 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_bar0_prefetch_check : if pf2_bar0_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_bar0_type_check : if pf2_bar0_type /= "PF2_BAR0_TYPE_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_bar1_enabled_check : if pf2_pci_type0_bar1_enabled /= "PF2_PCI_TYPE0_BAR1_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_bar1_mask_31_0_check : if pf2_pci_type0_bar1_mask_31_0 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_bar1_prefetch_check : if pf2_bar1_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_bar2_enabled_check : if pf2_pci_type0_bar2_enabled /= "PF2_PCI_TYPE0_BAR2_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_bar2_mask_31_1_check : if pf2_pci_type0_bar2_mask_31_1 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_bar2_prefetch_check : if pf2_bar2_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_bar2_type_check : if pf2_bar2_type /= "PF2_BAR2_TYPE_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_bar3_enabled_check : if pf2_pci_type0_bar3_enabled /= "PF2_PCI_TYPE0_BAR3_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_bar3_mask_31_0_check : if pf2_pci_type0_bar3_mask_31_0 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_bar3_prefetch_check : if pf2_bar3_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_bar4_enabled_check : if pf2_pci_type0_bar4_enabled /= "PF2_PCI_TYPE0_BAR4_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_bar4_mask_31_1_check : if pf2_pci_type0_bar4_mask_31_1 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_bar4_prefetch_check : if pf2_bar4_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_bar4_type_check : if pf2_bar4_type /= "PF2_BAR4_TYPE_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_bar5_enabled_check : if pf2_pci_type0_bar5_enabled /= "PF2_PCI_TYPE0_BAR5_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_bar5_mask_31_0_check : if pf2_pci_type0_bar5_mask_31_0 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_bar5_prefetch_check : if pf2_bar5_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_rom_bar_enable_check : if pf2_rom_bar_enable /= "PF2_ROM_BAR_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_rom_mask_check : if pf2_rom_mask /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_rom_bar_enabled_check : if pf2_rom_bar_enabled /= "PF2_ROM_BAR_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar0_enabled_check : if pf2_sriov_vf_bar0_enabled /= "PF2_SRIOV_VF_BAR0_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar0_mask_check : if pf2_sriov_vf_bar0_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar0_prefetch_check : if pf2_sriov_vf_bar0_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar0_type_check : if pf2_sriov_vf_bar0_type /= "PF2_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar1_enabled_check : if pf2_sriov_vf_bar1_enabled /= "PF2_SRIOV_VF_BAR1_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar1_mask_check : if pf2_sriov_vf_bar1_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar1_prefetch_check : if pf2_sriov_vf_bar1_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar2_enabled_check : if pf2_sriov_vf_bar2_enabled /= "PF2_SRIOV_VF_BAR2_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar2_mask_check : if pf2_sriov_vf_bar2_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar2_prefetch_check : if pf2_sriov_vf_bar2_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar2_type_check : if pf2_sriov_vf_bar2_type /= "PF2_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar3_enabled_check : if pf2_sriov_vf_bar3_enabled /= "PF2_SRIOV_VF_BAR3_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar3_mask_check : if pf2_sriov_vf_bar3_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar3_prefetch_check : if pf2_sriov_vf_bar3_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar4_enabled_check : if pf2_sriov_vf_bar4_enabled /= "PF2_SRIOV_VF_BAR4_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar4_mask_check : if pf2_sriov_vf_bar4_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar4_prefetch_check : if pf2_sriov_vf_bar4_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar4_type_check : if pf2_sriov_vf_bar4_type /= "PF2_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar5_enabled_check : if pf2_sriov_vf_bar5_enabled /= "PF2_SRIOV_VF_BAR5_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar5_mask_check : if pf2_sriov_vf_bar5_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_bar5_prefetch_check : if pf2_sriov_vf_bar5_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_bar0_enabled_check : if pf3_pci_type0_bar0_enabled /= "PF3_PCI_TYPE0_BAR0_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_bar0_mask_31_1_check : if pf3_pci_type0_bar0_mask_31_1 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_bar0_prefetch_check : if pf3_bar0_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_bar0_type_check : if pf3_bar0_type /= "PF3_BAR0_TYPE_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_bar1_enabled_check : if pf3_pci_type0_bar1_enabled /= "PF3_PCI_TYPE0_BAR1_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_bar1_mask_31_0_check : if pf3_pci_type0_bar1_mask_31_0 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_bar1_prefetch_check : if pf3_bar1_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_bar2_enabled_check : if pf3_pci_type0_bar2_enabled /= "PF3_PCI_TYPE0_BAR2_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_bar2_mask_31_1_check : if pf3_pci_type0_bar2_mask_31_1 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_bar2_prefetch_check : if pf3_bar2_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_bar2_type_check : if pf3_bar2_type /= "PF3_BAR2_TYPE_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_bar3_enabled_check : if pf3_pci_type0_bar3_enabled /= "PF3_PCI_TYPE0_BAR3_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_bar3_mask_31_0_check : if pf3_pci_type0_bar3_mask_31_0 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_bar3_prefetch_check : if pf3_bar3_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_bar4_enabled_check : if pf3_pci_type0_bar4_enabled /= "PF3_PCI_TYPE0_BAR4_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_bar4_mask_31_1_check : if pf3_pci_type0_bar4_mask_31_1 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_bar4_prefetch_check : if pf3_bar4_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_bar4_type_check : if pf3_bar4_type /= "PF3_BAR4_TYPE_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_bar5_enabled_check : if pf3_pci_type0_bar5_enabled /= "PF3_PCI_TYPE0_BAR5_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_bar5_mask_31_0_check : if pf3_pci_type0_bar5_mask_31_0 /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_bar5_prefetch_check : if pf3_bar5_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_rom_bar_enable_check : if pf3_rom_bar_enable /= "PF3_ROM_BAR_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_rom_mask_check : if pf3_rom_mask /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_rom_bar_enabled_check : if pf3_rom_bar_enabled /= "PF3_ROM_BAR_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar0_enabled_check : if pf3_sriov_vf_bar0_enabled /= "PF3_SRIOV_VF_BAR0_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar0_mask_check : if pf3_sriov_vf_bar0_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar0_prefetch_check : if pf3_sriov_vf_bar0_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar0_type_check : if pf3_sriov_vf_bar0_type /= "PF3_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar1_enabled_check : if pf3_sriov_vf_bar1_enabled /= "PF3_SRIOV_VF_BAR1_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar1_mask_check : if pf3_sriov_vf_bar1_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar1_prefetch_check : if pf3_sriov_vf_bar1_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar2_enabled_check : if pf3_sriov_vf_bar2_enabled /= "PF3_SRIOV_VF_BAR2_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar2_mask_check : if pf3_sriov_vf_bar2_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar2_prefetch_check : if pf3_sriov_vf_bar2_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar2_type_check : if pf3_sriov_vf_bar2_type /= "PF3_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar3_enabled_check : if pf3_sriov_vf_bar3_enabled /= "PF3_SRIOV_VF_BAR3_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar3_mask_check : if pf3_sriov_vf_bar3_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar3_prefetch_check : if pf3_sriov_vf_bar3_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar4_enabled_check : if pf3_sriov_vf_bar4_enabled /= "PF3_SRIOV_VF_BAR4_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar4_mask_check : if pf3_sriov_vf_bar4_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar4_prefetch_check : if pf3_sriov_vf_bar4_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar4_type_check : if pf3_sriov_vf_bar4_type /= "PF3_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar5_enabled_check : if pf3_sriov_vf_bar5_enabled /= "PF3_SRIOV_VF_BAR5_ENABLED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar5_mask_check : if pf3_sriov_vf_bar5_mask /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_bar5_prefetch_check : if pf3_sriov_vf_bar5_prefetch /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_enable_check : if pf1_enable /= "PF1_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_enable_check : if pf2_enable /= "PF2_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_enable_check : if pf3_enable /= "PF3_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_enable_check : if pf0_sriov_enable /= "PF0_SRIOV_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_enable_check : if pf1_sriov_enable /= "PF1_SRIOV_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_enable_check : if pf2_sriov_enable /= "PF2_SRIOV_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_enable_check : if pf3_sriov_enable /= "PF3_SRIOV_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_cap_sup_page_size_check : if pf0_sriov_cap_sup_page_size /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_cap_sup_page_size_check : if pf1_sriov_cap_sup_page_size /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_cap_sup_page_size_check : if pf2_sriov_cap_sup_page_size /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_cap_sup_page_size_check : if pf3_sriov_cap_sup_page_size /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_num_vf_check : if pf0_sriov_num_vf /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_num_vf_check : if pf1_sriov_num_vf /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_num_vf_check : if pf2_sriov_num_vf /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_num_vf_check : if pf3_sriov_num_vf /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_msi_enable_check : if pf0_msi_enable /= "PF0_MSI_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_msi_ext_data_cap_check : if pf0_pci_msi_ext_data_cap /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_msi_ext_data_en_check : if pf0_pci_msi_ext_data_en /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_msi_64_bit_addr_cap_check : if pf0_pci_msi_64_bit_addr_cap /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_msi_multiple_msg_cap_check : if pf0_pci_msi_multiple_msg_cap /= "PF0_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_msix_enable_check : if pf0_msix_enable /= "PF0_MSIX_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_msix_table_size_check : if pf0_pci_msix_table_size /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_msix_table_offset_check : if pf0_pci_msix_table_offset /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_msix_bir_check : if pf0_pci_msix_bir /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_msix_pba_check : if pf0_pci_msix_pba /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_msix_pba_offset_check : if pf0_pci_msix_pba_offset /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_msix_table_size_vfcomm_cs2_check : if pf0_pci_msix_table_size_vfcomm_cs2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_exvf_msix_cap_enable_check : if pf0_exvf_msix_cap_enable /= "PF0_EXVF_MSIX_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msix_tablesize_pf0_check : if exvf_msix_tablesize_pf0 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixtable_offset_pf0_check : if exvf_msixtable_offset_pf0 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixtable_bir_pf0_check : if exvf_msixtable_bir_pf0 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixpba_offset_pf0_check : if exvf_msixpba_offset_pf0 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixpba_bir_pf0_check : if exvf_msixpba_bir_pf0 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_msi_enable_check : if pf1_msi_enable /= "PF1_MSI_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_msi_ext_data_cap_check : if pf1_pci_msi_ext_data_cap /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_msi_ext_data_en_check : if pf1_pci_msi_ext_data_en /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_msi_64_bit_addr_cap_check : if pf1_pci_msi_64_bit_addr_cap /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_msi_multiple_msg_cap_check : if pf1_pci_msi_multiple_msg_cap /= "PF1_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_msix_enable_check : if pf1_msix_enable /= "PF1_MSIX_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_msix_table_size_check : if pf1_pci_msix_table_size /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_msix_table_offset_check : if pf1_pci_msix_table_offset /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_msix_bir_check : if pf1_pci_msix_bir /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_msix_pba_check : if pf1_pci_msix_pba /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_msix_pba_offset_check : if pf1_pci_msix_pba_offset /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_msix_table_size_vfcomm_cs2_check : if pf1_pci_msix_table_size_vfcomm_cs2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_exvf_msix_cap_enable_check : if pf1_exvf_msix_cap_enable /= "PF1_EXVF_MSIX_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msix_tablesize_pf1_check : if exvf_msix_tablesize_pf1 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixtable_offset_pf1_check : if exvf_msixtable_offset_pf1 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixtable_bir_pf1_check : if exvf_msixtable_bir_pf1 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixpba_offset_pf1_check : if exvf_msixpba_offset_pf1 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixpba_bir_pf1_check : if exvf_msixpba_bir_pf1 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_msi_enable_check : if pf2_msi_enable /= "PF2_MSI_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_msi_ext_data_cap_check : if pf2_pci_msi_ext_data_cap /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_msi_ext_data_en_check : if pf2_pci_msi_ext_data_en /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_msi_64_bit_addr_cap_check : if pf2_pci_msi_64_bit_addr_cap /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_msi_multiple_msg_cap_check : if pf2_pci_msi_multiple_msg_cap /= "PF2_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_msix_enable_check : if pf2_msix_enable /= "PF2_MSIX_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_msix_bir_check : if pf2_pci_msix_bir /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_msix_pba_check : if pf2_pci_msix_pba /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_msix_pba_offset_check : if pf2_pci_msix_pba_offset /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_msix_table_offset_check : if pf2_pci_msix_table_offset /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_msix_table_size_check : if pf2_pci_msix_table_size /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_msix_table_size_vfcomm_cs2_check : if pf2_pci_msix_table_size_vfcomm_cs2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_exvf_msix_cap_enable_check : if pf2_exvf_msix_cap_enable /= "PF2_EXVF_MSIX_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msix_tablesize_pf2_check : if exvf_msix_tablesize_pf2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixtable_offset_pf2_check : if exvf_msixtable_offset_pf2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixtable_bir_pf2_check : if exvf_msixtable_bir_pf2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixpba_offset_pf2_check : if exvf_msixpba_offset_pf2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixpba_bir_pf2_check : if exvf_msixpba_bir_pf2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_msi_enable_check : if pf3_msi_enable /= "PF3_MSI_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_msi_ext_data_cap_check : if pf3_pci_msi_ext_data_cap /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_msi_ext_data_en_check : if pf3_pci_msi_ext_data_en /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_msi_64_bit_addr_cap_check : if pf3_pci_msi_64_bit_addr_cap /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_msi_multiple_msg_cap_check : if pf3_pci_msi_multiple_msg_cap /= "PF3_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_msix_enable_check : if pf3_msix_enable /= "PF3_MSIX_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_msix_bir_check : if pf3_pci_msix_bir /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_msix_pba_check : if pf3_pci_msix_pba /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_msix_pba_offset_check : if pf3_pci_msix_pba_offset /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_msix_table_offset_check : if pf3_pci_msix_table_offset /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_msix_table_size_check : if pf3_pci_msix_table_size /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_msix_table_size_vfcomm_cs2_check : if pf3_pci_msix_table_size_vfcomm_cs2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_exvf_msix_cap_enable_check : if pf3_exvf_msix_cap_enable /= "PF3_EXVF_MSIX_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msix_tablesize_pf3_check : if exvf_msix_tablesize_pf3 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixtable_offset_pf3_check : if exvf_msixtable_offset_pf3 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixtable_bir_pf3_check : if exvf_msixtable_bir_pf3 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixpba_offset_pf3_check : if exvf_msixpba_offset_pf3 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_msixpba_bir_pf3_check : if exvf_msixpba_bir_pf3 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_prs_ext_cap_enable_check : if pf0_prs_ext_cap_enable /= "PF0_PRS_EXT_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_prs_ext_cap_outstanding_capacity_check : if pf0_prs_ext_cap_outstanding_capacity /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_prs_ext_cap_enable_check : if pf1_prs_ext_cap_enable /= "PF1_PRS_EXT_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_prs_ext_cap_outstanding_capacity_check : if pf1_prs_ext_cap_outstanding_capacity /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_prs_ext_cap_enable_check : if pf2_prs_ext_cap_enable /= "PF2_PRS_EXT_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_prs_ext_cap_outstanding_capacity_check : if pf2_prs_ext_cap_outstanding_capacity /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_prs_ext_cap_enable_check : if pf3_prs_ext_cap_enable /= "PF3_PRS_EXT_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_prs_ext_cap_outstanding_capacity_check : if pf3_prs_ext_cap_outstanding_capacity /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pasid_cap_enable_check : if pf0_pasid_cap_enable /= "PF0_PASID_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pasid_cap_execute_permission_supported_check : if pf0_pasid_cap_execute_permission_supported /= "PF0_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pasid_cap_max_pasid_width_check : if pf0_pasid_cap_max_pasid_width /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pasid_cap_privileged_mode_supported_check : if pf0_pasid_cap_privileged_mode_supported /= "PF0_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pasid_cap_enable_check : if pf1_pasid_cap_enable /= "PF1_PASID_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pasid_cap_execute_permission_supported_check : if pf1_pasid_cap_execute_permission_supported /= "PF1_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pasid_cap_max_pasid_width_check : if pf1_pasid_cap_max_pasid_width /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pasid_cap_privileged_mode_supported_check : if pf1_pasid_cap_privileged_mode_supported /= "PF1_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pasid_cap_enable_check : if pf2_pasid_cap_enable /= "PF2_PASID_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pasid_cap_execute_permission_supported_check : if pf2_pasid_cap_execute_permission_supported /= "PF2_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pasid_cap_max_pasid_width_check : if pf2_pasid_cap_max_pasid_width /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pasid_cap_privileged_mode_supported_check : if pf2_pasid_cap_privileged_mode_supported /= "PF2_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pasid_cap_enable_check : if pf3_pasid_cap_enable /= "PF3_PASID_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pasid_cap_execute_permission_supported_check : if pf3_pasid_cap_execute_permission_supported /= "PF3_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pasid_cap_max_pasid_width_check : if pf3_pasid_cap_max_pasid_width /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pasid_cap_privileged_mode_supported_check : if pf3_pasid_cap_privileged_mode_supported /= "PF3_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sn_cap_enable_check : if pf0_sn_cap_enable /= "PF0_SN_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sn_ser_num_reg_1_dw_check : if pf0_sn_ser_num_reg_1_dw /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sn_ser_num_reg_2_dw_check : if pf0_sn_ser_num_reg_2_dw /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sn_cap_enable_check : if pf1_sn_cap_enable /= "PF1_SN_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sn_ser_num_reg_1_dw_check : if pf1_sn_ser_num_reg_1_dw /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sn_ser_num_reg_2_dw_check : if pf1_sn_ser_num_reg_2_dw /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sn_cap_enable_check : if pf2_sn_cap_enable /= "PF2_SN_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sn_ser_num_reg_1_dw_check : if pf2_sn_ser_num_reg_1_dw /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sn_ser_num_reg_2_dw_check : if pf2_sn_ser_num_reg_2_dw /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sn_cap_enable_check : if pf3_sn_cap_enable /= "PF3_SN_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sn_ser_num_reg_1_dw_check : if pf3_sn_ser_num_reg_1_dw /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sn_ser_num_reg_2_dw_check : if pf3_sn_ser_num_reg_2_dw /= "00000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pcie_cap_ep_l0s_accpt_latency_check : if pf0_pcie_cap_ep_l0s_accpt_latency /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pcie_cap_ep_l1_accpt_latency_check : if pf0_pcie_cap_ep_l1_accpt_latency /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pcie_cap_l0s_exit_latency_commclk_dis_check : if pf0_pcie_cap_l0s_exit_latency_commclk_dis /= 7 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pcie_cap_l1_exit_latency_commclk_dis_check : if pf0_pcie_cap_l1_exit_latency_commclk_dis /= 7 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pcie_cap_ep_l0s_accpt_latency_check : if pf1_pcie_cap_ep_l0s_accpt_latency /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pcie_cap_ep_l1_accpt_latency_check : if pf1_pcie_cap_ep_l1_accpt_latency /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pcie_cap_l0s_exit_latency_commclk_dis_check : if pf1_pcie_cap_l0s_exit_latency_commclk_dis /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pcie_cap_l1_exit_latency_commclk_dis_check : if pf1_pcie_cap_l1_exit_latency_commclk_dis /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pcie_cap_ep_l0s_accpt_latency_check : if pf2_pcie_cap_ep_l0s_accpt_latency /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pcie_cap_ep_l1_accpt_latency_check : if pf2_pcie_cap_ep_l1_accpt_latency /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pcie_cap_l0s_exit_latency_commclk_dis_check : if pf2_pcie_cap_l0s_exit_latency_commclk_dis /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pcie_cap_l1_exit_latency_commclk_dis_check : if pf2_pcie_cap_l1_exit_latency_commclk_dis /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pcie_cap_ep_l0s_accpt_latency_check : if pf3_pcie_cap_ep_l0s_accpt_latency /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pcie_cap_ep_l1_accpt_latency_check : if pf3_pcie_cap_ep_l1_accpt_latency /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pcie_cap_l0s_exit_latency_commclk_dis_check : if pf3_pcie_cap_l0s_exit_latency_commclk_dis /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pcie_cap_l1_exit_latency_commclk_dis_check : if pf3_pcie_cap_l1_exit_latency_commclk_dis /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	aspm_support_check : if aspm_support /= "ASPM_SUPPORT_L0S_L1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	dbi_ro_wr_disable_check : if dbi_ro_wr_disable /= "DBI_RO_WR_DISABLE_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_gen3_eq_pset_req_vec_check : if pf0_gen3_eq_pset_req_vec /= 292 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_gen3_eq_pset_req_vec_atg4_check : if pf0_gen3_eq_pset_req_vec_atg4 /= 352 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pcie_cap_flr_cap_check : if pf0_pcie_cap_flr_cap /= "PF0_PCIE_CAP_FLR_CAP_NOT_CAPABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pcie_cap_flr_cap_check : if pf1_pcie_cap_flr_cap /= "PF1_PCIE_CAP_FLR_CAP_NOT_CAPABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pcie_cap_flr_cap_check : if pf2_pcie_cap_flr_cap /= "PF2_PCIE_CAP_FLR_CAP_NOT_CAPABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pcie_cap_flr_cap_check : if pf3_pcie_cap_flr_cap /= "PF3_PCIE_CAP_FLR_CAP_NOT_CAPABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pcie_cap_port_num_check : if pf0_pcie_cap_port_num /= 1 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pcie_cap_port_num_check : if pf1_pcie_cap_port_num /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pcie_cap_port_num_check : if pf2_pcie_cap_port_num /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pcie_cap_port_num_check : if pf3_pcie_cap_port_num /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pcie_cap_slot_clk_config_check : if pf0_pcie_cap_slot_clk_config /= "true" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pcie_cap_slot_clk_config_check : if pf1_pcie_cap_slot_clk_config /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pcie_cap_slot_clk_config_check : if pf2_pcie_cap_slot_clk_config /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pcie_cap_slot_clk_config_check : if pf3_pcie_cap_slot_clk_config /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_ltr_cap_enable_check : if pf0_ltr_cap_enable /= "PF0_LTR_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pcie_slot_imp_check : if pf0_pcie_slot_imp /= "PF0_PCIE_SLOT_IMP_NOT_IMPLEMENTED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pcie_cap_slot_power_limit_scale_check : if pf0_pcie_cap_slot_power_limit_scale /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pcie_cap_slot_power_limit_value_check : if pf0_pcie_cap_slot_power_limit_value /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pcie_cap_phy_slot_num_check : if pf0_pcie_cap_phy_slot_num /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pcie_cap_hot_plug_capable_check : if pf0_pcie_cap_hot_plug_capable /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pcie_cap_ext_tag_en_check : if pf0_pcie_cap_ext_tag_en /= "true" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pcie_cap_ext_tag_en_check : if pf1_pcie_cap_ext_tag_en /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pcie_cap_ext_tag_en_check : if pf2_pcie_cap_ext_tag_en /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pcie_cap_ext_tag_en_check : if pf3_pcie_cap_ext_tag_en /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	cfg_ptm_auto_update_signal_check : if cfg_ptm_auto_update_signal /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ptm_autoupdate_check : if ptm_autoupdate /= "PTM_AUTOUPDATE_AUTOUPDATE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ptm_enable_check : if ptm_enable /= "PTM_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_ats_cap_enable_check : if pf0_ats_cap_enable /= "PF0_ATS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_exvf_ats_cap_enable_check : if pf0_exvf_ats_cap_enable /= "PF0_EXVF_ATS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_ats_cap_invalidate_q_depth_check : if pf0_ats_cap_invalidate_q_depth /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_ats_exvf_align_request_check : if pf0_ats_exvf_align_request /= "PF0_ATS_EXVF_ALIGN_REQUEST_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_ats_cap_enable_check : if pf1_ats_cap_enable /= "PF1_ATS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_exvf_ats_cap_enable_check : if pf1_exvf_ats_cap_enable /= "PF1_EXVF_ATS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_ats_cap_invalidate_q_depth_check : if pf1_ats_cap_invalidate_q_depth /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_ats_exvf_align_request_check : if pf1_ats_exvf_align_request /= "PF1_ATS_EXVF_ALIGN_REQUEST_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_ats_cap_enable_check : if pf2_ats_cap_enable /= "PF2_ATS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_exvf_ats_cap_enable_check : if pf2_exvf_ats_cap_enable /= "PF2_EXVF_ATS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_ats_cap_invalidate_q_depth_check : if pf2_ats_cap_invalidate_q_depth /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_ats_exvf_align_request_check : if pf2_ats_exvf_align_request /= "PF2_ATS_EXVF_ALIGN_REQUEST_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_ats_cap_enable_check : if pf3_ats_cap_enable /= "PF3_ATS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_exvf_ats_cap_enable_check : if pf3_exvf_ats_cap_enable /= "PF3_EXVF_ATS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_ats_cap_invalidate_q_depth_check : if pf3_ats_cap_invalidate_q_depth /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_ats_exvf_align_request_check : if pf3_ats_exvf_align_request /= "PF3_ATS_EXVF_ALIGN_REQUEST_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_tph_cap_enable_check : if pf0_tph_cap_enable /= "PF0_TPH_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_tph_req_cap_int_vec_check : if pf0_tph_req_cap_int_vec /= "PF0_TPH_REQ_CAP_INT_VEC_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_tph_req_cap_int_vec_vfcomm_cs2_check : if pf0_tph_req_cap_int_vec_vfcomm_cs2 /= "PF0_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2_check : if pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 /= "PF0_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_tph_req_cap_st_table_loc_1_check : if pf0_tph_req_cap_st_table_loc_1 /= "PF0_TPH_REQ_CAP_ST_TABLE_LOC_1_NOT_IN_MSIX_TABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2_check : if pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 /= "PF0_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_tph_req_cap_st_table_size_check : if pf0_tph_req_cap_st_table_size /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_tph_req_cap_st_table_size_vfcomm_cs2_check : if pf0_tph_req_cap_st_table_size_vfcomm_cs2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_tph_req_device_spec_check : if pf0_tph_req_device_spec /= "PF0_TPH_REQ_DEVICE_SPEC_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_tph_req_device_spec_vfcomm_cs2_check : if pf0_tph_req_device_spec_vfcomm_cs2 /= "PF0_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_exvf_tph_cap_enable_check : if pf0_exvf_tph_cap_enable /= "PF0_EXVF_TPH_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_tph_sttablelocation_pf0_check : if exvf_tph_sttablelocation_pf0 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_tph_sttablesize_pf0_check : if exvf_tph_sttablesize_pf0 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_tph_cap_enable_check : if pf1_tph_cap_enable /= "PF1_TPH_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_tph_req_cap_int_vec_check : if pf1_tph_req_cap_int_vec /= "PF1_TPH_REQ_CAP_INT_VEC_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_tph_req_cap_int_vec_vfcomm_cs2_check : if pf1_tph_req_cap_int_vec_vfcomm_cs2 /= "PF1_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2_check : if pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2 /= "PF1_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_tph_req_cap_st_table_loc_1_check : if pf1_tph_req_cap_st_table_loc_1 /= "PF1_TPH_REQ_CAP_ST_TABLE_LOC_1_NOT_IN_MSIX_TABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2_check : if pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2 /= "PF1_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_tph_req_cap_st_table_size_check : if pf1_tph_req_cap_st_table_size /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_tph_req_cap_st_table_size_vfcomm_cs2_check : if pf1_tph_req_cap_st_table_size_vfcomm_cs2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_tph_req_device_spec_check : if pf1_tph_req_device_spec /= "PF1_TPH_REQ_DEVICE_SPEC_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_tph_req_device_spec_vfcomm_cs2_check : if pf1_tph_req_device_spec_vfcomm_cs2 /= "PF1_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_exvf_tph_cap_enable_check : if pf1_exvf_tph_cap_enable /= "PF1_EXVF_TPH_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_tph_sttablelocation_pf1_check : if exvf_tph_sttablelocation_pf1 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_tph_sttablesize_pf1_check : if exvf_tph_sttablesize_pf1 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_tph_cap_enable_check : if pf2_tph_cap_enable /= "PF2_TPH_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_tph_req_cap_int_vec_check : if pf2_tph_req_cap_int_vec /= "PF2_TPH_REQ_CAP_INT_VEC_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_tph_req_cap_int_vec_vfcomm_cs2_check : if pf2_tph_req_cap_int_vec_vfcomm_cs2 /= "PF2_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2_check : if pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2 /= "PF2_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_tph_req_cap_st_table_loc_1_check : if pf2_tph_req_cap_st_table_loc_1 /= "PF2_TPH_REQ_CAP_ST_TABLE_LOC_1_NOT_IN_MSIX_TABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2_check : if pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2 /= "PF2_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_tph_req_cap_st_table_size_check : if pf2_tph_req_cap_st_table_size /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_tph_req_cap_st_table_size_vfcomm_cs2_check : if pf2_tph_req_cap_st_table_size_vfcomm_cs2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_tph_req_device_spec_check : if pf2_tph_req_device_spec /= "PF2_TPH_REQ_DEVICE_SPEC_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_tph_req_device_spec_vfcomm_cs2_check : if pf2_tph_req_device_spec_vfcomm_cs2 /= "PF2_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_exvf_tph_cap_enable_check : if pf2_exvf_tph_cap_enable /= "PF2_EXVF_TPH_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_tph_sttablelocation_pf2_check : if exvf_tph_sttablelocation_pf2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_tph_sttablesize_pf2_check : if exvf_tph_sttablesize_pf2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_tph_cap_enable_check : if pf3_tph_cap_enable /= "PF3_TPH_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_tph_req_cap_int_vec_check : if pf3_tph_req_cap_int_vec /= "PF3_TPH_REQ_CAP_INT_VEC_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_tph_req_cap_int_vec_vfcomm_cs2_check : if pf3_tph_req_cap_int_vec_vfcomm_cs2 /= "PF3_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2_check : if pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2 /= "PF3_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_tph_req_cap_st_table_loc_1_check : if pf3_tph_req_cap_st_table_loc_1 /= "PF3_TPH_REQ_CAP_ST_TABLE_LOC_1_NOT_IN_MSIX_TABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2_check : if pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2 /= "PF3_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_tph_req_cap_st_table_size_check : if pf3_tph_req_cap_st_table_size /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_tph_req_cap_st_table_size_vfcomm_cs2_check : if pf3_tph_req_cap_st_table_size_vfcomm_cs2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_tph_req_device_spec_check : if pf3_tph_req_device_spec /= "PF3_TPH_REQ_DEVICE_SPEC_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_tph_req_device_spec_vfcomm_cs2_check : if pf3_tph_req_device_spec_vfcomm_cs2 /= "PF3_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_exvf_tph_cap_enable_check : if pf3_exvf_tph_cap_enable /= "PF3_EXVF_TPH_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_tph_sttablelocation_pf3_check : if exvf_tph_sttablelocation_pf3 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_tph_sttablesize_pf3_check : if exvf_tph_sttablesize_pf3 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_acs_cap_enable_check : if pf0_acs_cap_enable /= "PF0_ACS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_exvf_acs_cap_enable_check : if pf0_exvf_acs_cap_enable /= "PF0_EXVF_ACS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_acs_cap_acs_src_valid_check : if pf0_acs_cap_acs_src_valid /= "PF0_ACS_CAP_ACS_SRC_VALID_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_acs_cap_acs_at_block_check : if pf0_acs_cap_acs_at_block /= "PF0_ACS_CAP_ACS_AT_BLOCK_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_acs_cap_acs_p2p_req_redirect_check : if pf0_acs_cap_acs_p2p_req_redirect /= "PF0_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_acs_cap_acs_p2p_cpl_redirect_check : if pf0_acs_cap_acs_p2p_cpl_redirect /= "PF0_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_acs_cap_acs_usp_forwarding_check : if pf0_acs_cap_acs_usp_forwarding /= "PF0_ACS_CAP_ACS_USP_FORWARDING_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_acs_cap_acs_p2p_egress_control_check : if pf0_acs_cap_acs_p2p_egress_control /= "PF0_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_acs_cap_acs_egress_ctrl_size_check : if pf0_acs_cap_acs_egress_ctrl_size /= 8 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_acs_cap_acs_direct_translated_p2p_check : if pf0_acs_cap_acs_direct_translated_p2p /= "PF0_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_acs_cap_enable_check : if pf1_acs_cap_enable /= "PF1_ACS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_exvf_acs_cap_enable_check : if pf1_exvf_acs_cap_enable /= "PF1_EXVF_ACS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_acs_cap_acs_src_valid_check : if pf1_acs_cap_acs_src_valid /= "PF1_ACS_CAP_ACS_SRC_VALID_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_acs_cap_acs_at_block_check : if pf1_acs_cap_acs_at_block /= "PF1_ACS_CAP_ACS_AT_BLOCK_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_acs_cap_acs_p2p_req_redirect_check : if pf1_acs_cap_acs_p2p_req_redirect /= "PF1_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_acs_cap_acs_p2p_cpl_redirect_check : if pf1_acs_cap_acs_p2p_cpl_redirect /= "PF1_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_acs_cap_acs_usp_forwarding_check : if pf1_acs_cap_acs_usp_forwarding /= "PF1_ACS_CAP_ACS_USP_FORWARDING_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_acs_cap_acs_p2p_egress_control_check : if pf1_acs_cap_acs_p2p_egress_control /= "PF1_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_acs_cap_acs_egress_ctrl_size_check : if pf1_acs_cap_acs_egress_ctrl_size /= 8 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_acs_cap_acs_direct_translated_p2p_check : if pf1_acs_cap_acs_direct_translated_p2p /= "PF1_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_acs_cap_enable_check : if pf2_acs_cap_enable /= "PF2_ACS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_exvf_acs_cap_enable_check : if pf2_exvf_acs_cap_enable /= "PF2_EXVF_ACS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_acs_cap_acs_src_valid_check : if pf2_acs_cap_acs_src_valid /= "PF2_ACS_CAP_ACS_SRC_VALID_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_acs_cap_acs_at_block_check : if pf2_acs_cap_acs_at_block /= "PF2_ACS_CAP_ACS_AT_BLOCK_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_acs_cap_acs_p2p_req_redirect_check : if pf2_acs_cap_acs_p2p_req_redirect /= "PF2_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_acs_cap_acs_p2p_cpl_redirect_check : if pf2_acs_cap_acs_p2p_cpl_redirect /= "PF2_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_acs_cap_acs_usp_forwarding_check : if pf2_acs_cap_acs_usp_forwarding /= "PF2_ACS_CAP_ACS_USP_FORWARDING_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_acs_cap_acs_p2p_egress_control_check : if pf2_acs_cap_acs_p2p_egress_control /= "PF2_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_acs_cap_acs_egress_ctrl_size_check : if pf2_acs_cap_acs_egress_ctrl_size /= 8 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_acs_cap_acs_direct_translated_p2p_check : if pf2_acs_cap_acs_direct_translated_p2p /= "PF2_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_acs_cap_enable_check : if pf3_acs_cap_enable /= "PF3_ACS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_exvf_acs_cap_enable_check : if pf3_exvf_acs_cap_enable /= "PF3_EXVF_ACS_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_acs_cap_acs_src_valid_check : if pf3_acs_cap_acs_src_valid /= "PF3_ACS_CAP_ACS_SRC_VALID_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_acs_cap_acs_at_block_check : if pf3_acs_cap_acs_at_block /= "PF3_ACS_CAP_ACS_AT_BLOCK_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_acs_cap_acs_p2p_req_redirect_check : if pf3_acs_cap_acs_p2p_req_redirect /= "PF3_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_acs_cap_acs_p2p_cpl_redirect_check : if pf3_acs_cap_acs_p2p_cpl_redirect /= "PF3_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_acs_cap_acs_usp_forwarding_check : if pf3_acs_cap_acs_usp_forwarding /= "PF3_ACS_CAP_ACS_USP_FORWARDING_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_acs_cap_acs_p2p_egress_control_check : if pf3_acs_cap_acs_p2p_egress_control /= "PF3_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_acs_cap_acs_egress_ctrl_size_check : if pf3_acs_cap_acs_egress_ctrl_size /= 8 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_acs_cap_acs_direct_translated_p2p_check : if pf3_acs_cap_acs_direct_translated_p2p /= "PF3_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_virtio_en_check : if pf0_virtio_en /= "PF0_VIRTIO_EN_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_virtio_en_check : if pf1_virtio_en /= "PF1_VIRTIO_EN_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_virtio_en_check : if pf2_virtio_en /= "PF2_VIRTIO_EN_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_virtio_en_check : if pf3_virtio_en /= "PF3_VIRTIO_EN_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_exvf_virtio_en_check : if pf0_exvf_virtio_en /= "PF0_EXVF_VIRTIO_EN_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_exvf_virtio_en_check : if pf1_exvf_virtio_en /= "PF1_EXVF_VIRTIO_EN_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_exvf_virtio_en_check : if pf2_exvf_virtio_en /= "PF2_EXVF_VIRTIO_EN_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_exvf_virtio_en_check : if pf3_exvf_virtio_en /= "PF3_EXVF_VIRTIO_EN_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_device_id_check : if pf0_pci_type0_device_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_pci_type0_vendor_id_check : if pf0_pci_type0_vendor_id /= 4466 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_revision_id_check : if pf0_revision_id /= 1 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_base_class_code_check : if pf0_base_class_code /= 255 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_subclass_code_check : if pf0_subclass_code /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_program_interface_check : if pf0_program_interface /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_subsys_vendor_id_check : if pf0_subsys_vendor_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_subsys_dev_id_check : if pf0_subsys_dev_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_sriov_vf_device_id_check : if pf0_sriov_vf_device_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_subsysid_pf0_check : if exvf_subsysid_pf0 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_vendor_id_check : if pf1_pci_type0_vendor_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_pci_type0_device_id_check : if pf1_pci_type0_device_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_revision_id_check : if pf1_revision_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_base_class_code_check : if pf1_base_class_code /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_subclass_code_check : if pf1_subclass_code /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_program_interface_check : if pf1_program_interface /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_subsys_vendor_id_check : if pf1_subsys_vendor_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_subsys_dev_id_check : if pf1_subsys_dev_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_sriov_vf_device_id_check : if pf1_sriov_vf_device_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_subsysid_pf1_check : if exvf_subsysid_pf1 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_vendor_id_check : if pf2_pci_type0_vendor_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_pci_type0_device_id_check : if pf2_pci_type0_device_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_revision_id_check : if pf2_revision_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_base_class_code_check : if pf2_base_class_code /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_subclass_code_check : if pf2_subclass_code /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_program_interface_check : if pf2_program_interface /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_subsys_vendor_id_check : if pf2_subsys_vendor_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_subsys_dev_id_check : if pf2_subsys_dev_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_sriov_vf_device_id_check : if pf2_sriov_vf_device_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_subsysid_pf2_check : if exvf_subsysid_pf2 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_vendor_id_check : if pf3_pci_type0_vendor_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_pci_type0_device_id_check : if pf3_pci_type0_device_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_revision_id_check : if pf3_revision_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_base_class_code_check : if pf3_base_class_code /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_subclass_code_check : if pf3_subclass_code /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_program_interface_check : if pf3_program_interface /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_subsys_vendor_id_check : if pf3_subsys_vendor_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_subsys_dev_id_check : if pf3_subsys_dev_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_sriov_vf_device_id_check : if pf3_sriov_vf_device_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	exvf_subsysid_pf3_check : if exvf_subsysid_pf3 /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	vsec_select_check : if vsec_select /= "false" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_user_vsec_cap_enable_check : if pf0_user_vsec_cap_enable /= "PF0_USER_VSEC_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_user_vsec_cap_enable_check : if pf1_user_vsec_cap_enable /= "PF1_USER_VSEC_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_user_vsec_cap_enable_check : if pf2_user_vsec_cap_enable /= "PF2_USER_VSEC_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_user_vsec_cap_enable_check : if pf3_user_vsec_cap_enable /= "PF3_USER_VSEC_CAP_ENABLE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	vsec_next_offset_check : if vsec_next_offset /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_user_vsec_offset_check : if pf1_user_vsec_offset /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_user_vsec_offset_check : if pf2_user_vsec_offset /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_user_vsec_offset_check : if pf3_user_vsec_offset /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	cvp_vendor_specific_header_id_check : if cvp_vendor_specific_header_id /= 0 generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	drop_vendor0_msg_check : if drop_vendor0_msg /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	drop_vendor1_msg_check : if drop_vendor1_msg /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_int_pin_check : if pf0_int_pin /= "PF0_INT_PIN_NO_INT" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf1_int_pin_check : if pf1_int_pin /= "PF1_INT_PIN_NO_INT" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf2_int_pin_check : if pf2_int_pin /= "PF2_INT_PIN_NO_INT" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf3_int_pin_check : if pf3_int_pin /= "PF3_INT_PIN_NO_INT" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	dtk_mode_en_check : if dtk_mode_en /= "DTK_MODE_EN_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ecrc_strip_check : if ecrc_strip /= "ECRC_STRIP_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_port_logic_fast_link_mode_check : if pf0_port_logic_fast_link_mode /= "PF0_PORT_LOGIC_FAST_LINK_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pf0_prefetch_decode_check : if pf0_prefetch_decode /= "PF0_PREFETCH_DECODE_PREF32" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pcie_pcs_mode_check : if pcie_pcs_mode /= "PCIE_PCS_MODE_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_clk_mux_0_sel_check : if sm_hssi_pcie_pcs_clk_mux_0_sel /= "SEL_SAME_QUAD_PCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_clk_mux_1_sel_check : if sm_hssi_pcie_pcs_clk_mux_1_sel /= "SEL_SAME_QUAD_PCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_clk_mux_2_sel_check : if sm_hssi_pcie_pcs_clk_mux_2_sel /= "SEL_SAME_QUAD_PCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_clk_mux_3_sel_check : if sm_hssi_pcie_pcs_clk_mux_3_sel /= "SEL_SAME_QUAD_PCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_hps_clkmux_0_sel_check : if sm_hssi_pcie_pcs_hps_clkmux_0_sel /= "SEL_HPS_PCS1_ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_rst_mux_0_sel_check : if sm_hssi_pcie_pcs_rst_mux_0_sel /= "SEL_SAME_QUAD_PCS_RST" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_rst_mux_1_sel_check : if sm_hssi_pcie_pcs_rst_mux_1_sel /= "SEL_SAME_QUAD_PCS_RST" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_rst_mux_2_sel_check : if sm_hssi_pcie_pcs_rst_mux_2_sel /= "SEL_SAME_QUAD_PCS_RST" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_rst_mux_3_sel_check : if sm_hssi_pcie_pcs_rst_mux_3_sel /= "SEL_SAME_QUAD_PCS_RST" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_tx_mux_0_sel_check : if sm_hssi_pcie_pcs_tx_mux_0_sel /= "SEL_SAME_QUAD_PCIE_CTRL" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_tx_mux_1_sel_check : if sm_hssi_pcie_pcs_tx_mux_1_sel /= "SEL_SAME_QUAD_PCIE_CTRL" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_tx_mux_2_sel_check : if sm_hssi_pcie_pcs_tx_mux_2_sel /= "SEL_SAME_QUAD_PCIE_CTRL" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_tx_mux_3_sel_check : if sm_hssi_pcie_pcs_tx_mux_3_sel /= "SEL_SAME_QUAD_PCIE_CTRL" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_hps_demux_0_sel_check : if sm_hssi_pcie_pcs_hps_demux_0_sel /= "SEL_HPS_PCS1_ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_hps_mux_0_sel_check : if sm_hssi_pcie_pcs_hps_mux_0_sel /= "SEL_HPS_PCS1_ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_rx_demux_0_sel_check : if sm_hssi_pcie_pcs_rx_demux_0_sel /= "SEL_SAME_QUAD_PCIE_CTRL" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_rx_demux_1_sel_check : if sm_hssi_pcie_pcs_rx_demux_1_sel /= "SEL_SAME_QUAD_PCIE_CTRL" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_rx_demux_2_sel_check : if sm_hssi_pcie_pcs_rx_demux_2_sel /= "SEL_SAME_QUAD_PCIE_CTRL" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_pcs_rx_demux_3_sel_check : if sm_hssi_pcie_pcs_rx_demux_3_sel /= "SEL_SAME_QUAD_PCIE_CTRL" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_clk_mux_0_sel_check : if sm_hssi_pcie_clk_mux_0_sel /= "SEL_MIDDLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pcie_data_mux_0_sel_check : if sm_hssi_pcie_data_mux_0_sel /= "SEL_MIDDLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_dr_enabled_check : if sm_hssi_pld_chnl_dp_0_dr_enabled /= "DR_ENABLED_DR_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_duplex_mode_check : if sm_hssi_pld_chnl_dp_0_duplex_mode /= "DUPLEX_MODE_DUPLEX" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_pld_channel_identifier_check : if sm_hssi_pld_chnl_dp_0_pld_channel_identifier /= "PLD_CHANNEL_IDENTIFIER_PHIP" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_rx_clkout1_divider_check : if sm_hssi_pld_chnl_dp_0_rx_clkout1_divider /= "RX_CLKOUT1_DIVIDER_DIV1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_rx_clkout2_divider_check : if sm_hssi_pld_chnl_dp_0_rx_clkout2_divider /= "RX_CLKOUT2_DIVIDER_DIV1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_rx_en_check : if sm_hssi_pld_chnl_dp_0_rx_en /= "TRUE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_rx_fifo_mode_check : if sm_hssi_pld_chnl_dp_0_rx_fifo_mode /= "RX_FIFO_MODE_PHASE_COMP" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_rx_fifo_width_check : if sm_hssi_pld_chnl_dp_0_rx_fifo_width /= "RX_FIFO_WIDTH_DOUBLE_DOUBLE_WIDTH" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_rx_fifo_wr_clk_hz_check : if sm_hssi_pld_chnl_dp_0_rx_fifo_wr_clk_hz /= "000000011101110011010110010100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_rx_user1_clk_dynamic_mux_check : if sm_hssi_pld_chnl_dp_0_rx_user1_clk_dynamic_mux /= "RX_USER1_CLK_DYNAMIC_MUX_C2" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_rx_user2_clk_dynamic_mux_check : if sm_hssi_pld_chnl_dp_0_rx_user2_clk_dynamic_mux /= "RX_USER2_CLK_DYNAMIC_MUX_UX" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_sup_mode_check : if sm_hssi_pld_chnl_dp_0_sup_mode /= "SUP_MODE_USER_MODE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_tx_clkout1_divider_check : if sm_hssi_pld_chnl_dp_0_tx_clkout1_divider /= "TX_CLKOUT1_DIVIDER_DIV1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_tx_clkout2_divider_check : if sm_hssi_pld_chnl_dp_0_tx_clkout2_divider /= "TX_CLKOUT2_DIVIDER_DIV1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_tx_en_check : if sm_hssi_pld_chnl_dp_0_tx_en /= "TRUE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_tx_fifo_mode_check : if sm_hssi_pld_chnl_dp_0_tx_fifo_mode /= "TX_FIFO_MODE_PHASE_COMP" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_tx_fifo_rd_clk_hz_check : if sm_hssi_pld_chnl_dp_0_tx_fifo_rd_clk_hz /= "000000011101110011010110010100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_tx_fifo_width_check : if sm_hssi_pld_chnl_dp_0_tx_fifo_width /= "TX_FIFO_WIDTH_DOUBLE_DOUBLE_WIDTH" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_tx_user1_clk_dynamic_mux_check : if sm_hssi_pld_chnl_dp_0_tx_user1_clk_dynamic_mux /= "TX_USER1_CLK_DYNAMIC_MUX_C1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_tx_user2_clk_dynamic_mux_check : if sm_hssi_pld_chnl_dp_0_tx_user2_clk_dynamic_mux /= "TX_USER2_CLK_DYNAMIC_MUX_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_dp_0_vc_rx_pldif_wm_en_check : if sm_hssi_pld_chnl_dp_0_vc_rx_pldif_wm_en /= "VC_RX_PLDIF_WM_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_pld_rx_mux_0_sel_check : if sm_pld_rx_mux_0_sel /= "SEL_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_pld_tx_demux_0_sel_check : if sm_pld_tx_demux_0_sel /= "SEL_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_sel_check : if sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_sel /= "SEL_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_sel_check : if sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_sel /= "SEL_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pcie_hal_top : component gts_axi_streaming_pcie_hal_top_2100_jipcchq_cmp
		generic map (
			ch0_pcs_l_tx_en_atom                                => "FALSE",
			ch0_pcs_l_rx_en_atom                                => "FALSE",
			ch0_fec_loopback_mode_atom                          => "CH0_LOOPBACK_MODE_DISABLE",
			ch0_fec_dyn_tx_mux_atom                             => "CH0_DYN_TX_MUX_UNUSED",
			ch0_fec_error_atom                                  => "FALSE",
			ch0_fec_rx_en_atom                                  => "FALSE",
			ch0_fec_tx_en_atom                                  => "FALSE",
			ch0_fec_mode_atom                                   => "CH0_FEC_MODE_DISABLED",
			ch1_pcs_l_tx_en_atom                                => "FALSE",
			ch1_pcs_l_rx_en_atom                                => "FALSE",
			ch1_fec_loopback_mode_atom                          => "CH1_LOOPBACK_MODE_DISABLE",
			ch1_fec_dyn_tx_mux_atom                             => "CH1_DYN_TX_MUX_UNUSED",
			ch1_fec_error_atom                                  => "FALSE",
			ch1_fec_rx_en_atom                                  => "FALSE",
			ch1_fec_tx_en_atom                                  => "FALSE",
			ch1_fec_mode_atom                                   => "CH1_FEC_MODE_DISABLED",
			ch2_pcs_l_tx_en_atom                                => "FALSE",
			ch2_pcs_l_rx_en_atom                                => "FALSE",
			ch2_fec_loopback_mode_atom                          => "CH2_LOOPBACK_MODE_DISABLE",
			ch2_fec_dyn_tx_mux_atom                             => "CH2_DYN_TX_MUX_UNUSED",
			ch2_fec_error_atom                                  => "FALSE",
			ch2_fec_rx_en_atom                                  => "FALSE",
			ch2_fec_tx_en_atom                                  => "FALSE",
			ch2_fec_mode_atom                                   => "CH2_FEC_MODE_DISABLED",
			ch3_pcs_l_tx_en_atom                                => "FALSE",
			ch3_pcs_l_rx_en_atom                                => "FALSE",
			ch3_fec_loopback_mode_atom                          => "CH3_LOOPBACK_MODE_DISABLE",
			ch3_fec_dyn_tx_mux_atom                             => "CH3_DYN_TX_MUX_UNUSED",
			ch3_fec_error_atom                                  => "FALSE",
			ch3_fec_rx_en_atom                                  => "FALSE",
			ch3_fec_tx_en_atom                                  => "FALSE",
			ch3_fec_mode_atom                                   => "CH3_FEC_MODE_DISABLED",
			ch0_xcvr_rx_prbs_monitor_en_atom                    => "CH0_RX_PRBS_MONITOR_EN_DISABLE",
			ch1_xcvr_rx_prbs_monitor_en_atom                    => "CH1_RX_PRBS_MONITOR_EN_ENABLE",
			ch2_xcvr_rx_prbs_monitor_en_atom                    => "CH2_RX_PRBS_MONITOR_EN_ENABLE",
			ch3_xcvr_rx_prbs_monitor_en_atom                    => "CH3_RX_PRBS_MONITOR_EN_ENABLE",
			ch0_tx_prbs_gen_en_atom                             => "CH0_TX_PRBS_GEN_EN_DISABLE",
			ch1_tx_prbs_gen_en_atom                             => "CH1_TX_PRBS_GEN_EN_DISABLE",
			ch2_tx_prbs_gen_en_atom                             => "CH2_TX_PRBS_GEN_EN_DISABLE",
			ch3_tx_prbs_gen_en_atom                             => "CH3_TX_PRBS_GEN_EN_DISABLE",
			ch0_rx_user1_clk_mux_dynamic_sel_atom               => "CH0_RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD",
			ch0_rx_user2_clk_mux_dynamic_sel_atom               => "CH0_RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD",
			ch0_tx_user1_clk_mux_dynamic_sel_atom               => "CH0_TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK",
			ch0_tx_user2_clk_mux_dynamic_sel_atom               => "CH0_TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK",
			ch1_rx_user1_clk_mux_dynamic_sel_atom               => "CH1_RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD",
			ch1_rx_user2_clk_mux_dynamic_sel_atom               => "CH1_RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD",
			ch1_tx_user1_clk_mux_dynamic_sel_atom               => "CH1_TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK",
			ch1_tx_user2_clk_mux_dynamic_sel_atom               => "CH1_TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK",
			ch2_rx_user1_clk_mux_dynamic_sel_atom               => "CH2_RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD",
			ch2_rx_user2_clk_mux_dynamic_sel_atom               => "CH2_RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD",
			ch2_tx_user1_clk_mux_dynamic_sel_atom               => "CH2_TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK",
			ch2_tx_user2_clk_mux_dynamic_sel_atom               => "CH2_TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK",
			ch3_rx_user1_clk_mux_dynamic_sel_atom               => "CH3_RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD",
			ch3_rx_user2_clk_mux_dynamic_sel_atom               => "CH3_RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD",
			ch3_tx_user1_clk_mux_dynamic_sel_atom               => "CH3_TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK",
			ch3_tx_user2_clk_mux_dynamic_sel_atom               => "CH3_TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK",
			ch0_pcie_mode_atom                                  => "CH0_PCIE_MODE_GEN3",
			ch1_pcie_mode_atom                                  => "CH1_PCIE_MODE_GEN3",
			ch2_pcie_mode_atom                                  => "CH2_PCIE_MODE_GEN3",
			ch3_pcie_mode_atom                                  => "CH3_PCIE_MODE_GEN3",
			ch0_xcvr_rx_protocol_hint_atom                      => "CH0_RX_PROTOCOL_HINT_DISABLED",
			ch1_xcvr_rx_protocol_hint_atom                      => "CH1_RX_PROTOCOL_HINT_DISABLED",
			ch2_xcvr_rx_protocol_hint_atom                      => "CH2_RX_PROTOCOL_HINT_DISABLED",
			ch3_xcvr_rx_protocol_hint_atom                      => "CH3_RX_PROTOCOL_HINT_DISABLED",
			ch0_clkrx_refclk_cssm_fw_control_atom               => "CH0_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE",
			ch1_clkrx_refclk_cssm_fw_control_atom               => "CH1_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE",
			ch2_clkrx_refclk_cssm_fw_control_atom               => "CH2_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE",
			ch3_clkrx_refclk_cssm_fw_control_atom               => "CH3_CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE",
			ch0_clkrx_refclk_sector_specifies_refclk_ready_atom => "CH0_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE",
			ch1_clkrx_refclk_sector_specifies_refclk_ready_atom => "CH1_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE",
			ch2_clkrx_refclk_sector_specifies_refclk_ready_atom => "CH2_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE",
			ch3_clkrx_refclk_sector_specifies_refclk_ready_atom => "CH3_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE",
			ch0_local_refclk_cssm_fw_control_atom               => "CH0_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE",
			ch1_local_refclk_cssm_fw_control_atom               => "CH1_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE",
			ch2_local_refclk_cssm_fw_control_atom               => "CH2_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE",
			ch3_local_refclk_cssm_fw_control_atom               => "CH3_LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE",
			ch0_local_refclk_sector_specifies_refclk_ready_atom => "CH0_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE",
			ch1_local_refclk_sector_specifies_refclk_ready_atom => "CH1_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE",
			ch2_local_refclk_sector_specifies_refclk_ready_atom => "CH2_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE",
			ch3_local_refclk_sector_specifies_refclk_ready_atom => "CH3_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE",
			ch0_tx_bonding_category_atom                        => "CH0_TX_BONDING_CATEGORY_BONDING_LEADER",
			ch1_tx_bonding_category_atom                        => "CH1_TX_BONDING_CATEGORY_BONDING_FOLLOWER",
			ch2_tx_bonding_category_atom                        => "CH2_TX_BONDING_CATEGORY_BONDING_FOLLOWER",
			ch3_tx_bonding_category_atom                        => "CH3_TX_BONDING_CATEGORY_BONDING_FOLLOWER",
			hal_num_of_lanes_hwtcl                              => 4,
			is_sm4_sm7_revA                                     => 1,
			ch0_duplex_mode_atom                                => "CH0_DUPLEX_MODE_DUPLEX",
			ch0_fec_spec_atom                                   => "CH0_FEC_SPEC_DISABLED",
			ch0_fracture_atom                                   => "CH0_FRACTURE_UNUSED",
			ch0_dr_enabled_atom                                 => "CH0_DR_ENABLED_DR_DISABLED",
			ch0_sup_mode_atom                                   => "CH0_SUP_MODE_USER_MODE",
			ch0_sim_mode_atom                                   => "CH0_SIM_MODE_DISABLE",
			ch1_duplex_mode_atom                                => "CH1_DUPLEX_MODE_DUPLEX",
			ch1_fec_spec_atom                                   => "CH1_FEC_SPEC_DISABLED",
			ch1_fracture_atom                                   => "CH1_FRACTURE_UNUSED",
			ch1_dr_enabled_atom                                 => "CH1_DR_ENABLED_DR_DISABLED",
			ch1_sup_mode_atom                                   => "CH1_SUP_MODE_USER_MODE",
			ch1_sim_mode_atom                                   => "CH1_SIM_MODE_DISABLE",
			ch2_duplex_mode_atom                                => "CH2_DUPLEX_MODE_DUPLEX",
			ch2_fec_spec_atom                                   => "CH2_FEC_SPEC_DISABLED",
			ch2_fracture_atom                                   => "CH2_FRACTURE_UNUSED",
			ch2_dr_enabled_atom                                 => "CH2_DR_ENABLED_DR_DISABLED",
			ch2_sup_mode_atom                                   => "CH2_SUP_MODE_USER_MODE",
			ch2_sim_mode_atom                                   => "CH2_SIM_MODE_DISABLE",
			ch3_duplex_mode_atom                                => "CH3_DUPLEX_MODE_DUPLEX",
			ch3_fec_spec_atom                                   => "CH3_FEC_SPEC_DISABLED",
			ch3_fracture_atom                                   => "CH3_FRACTURE_UNUSED",
			ch3_dr_enabled_atom                                 => "CH3_DR_ENABLED_DR_DISABLED",
			ch3_sup_mode_atom                                   => "CH3_SUP_MODE_USER_MODE",
			ch3_sim_mode_atom                                   => "CH3_SIM_MODE_DISABLE",
			ch0_xcvr_tx_preloaded_hardware_configs_atom         => "CH0_TX_PRELOADED_HARDWARE_CONFIGS_PCIE",
			ch0_xcvr_rx_preloaded_hardware_configs_atom         => "CH0_RX_PRELOADED_HARDWARE_CONFIGS_PCIE",
			ch0_lc_postdiv_sel_atom                             => "CH0_LC_POSTDIV_SEL_SYNTH2",
			ch0_sequencer_reg_en_atom                           => "CH0_SEQUENCER_REG_EN_ENABLE",
			ch0_rst_mux_static_sel_atom                         => "CH0_RST_MUX_STATIC_SEL_HRC",
			ch0_xcvr_tx_prbs_pattern_atom                       => "0000",
			ch0_xcvr_rx_prbs_pattern_atom                       => "0000",
			ch0_xcvr_tx_user_clk_only_mode_atom                 => "CH0_TX_USER_CLK_ONLY_MODE_DISABLE",
			ch0_xcvr_tx_width_atom                              => "CH0_TX_WIDTH_X16",
			ch0_xcvr_rx_width_atom                              => "CH0_RX_WIDTH_X16",
			ch0_phy_loopback_mode_atom                          => "CH0_LOOPBACK_MODE_DISABLED",
			ch0_flux_mode_atom                                  => "CH0_FLUX_MODE_FLUX_MODE_BYPASS",
			ch0_flux_mode_hw_atom                               => "CH0_FLUX_MODE_FLUX_MODE_BYPASS",
			ch0_tx_sim_mode_atom                                => "CH0_TX_SIM_MODE_DISABLE",
			ch0_rx_sim_mode_atom                                => "CH0_RX_SIM_MODE_DISABLE",
			ch0_tx_dl_enable_atom                               => "CH0_TX_DL_ENABLE_DISABLE",
			ch0_rx_dl_enable_atom                               => "CH0_RX_DL_ENABLE_DISABLE",
			ch0_rx_fec_type_used_atom                           => "CH0_RX_FEC_TYPE_USED_NONE",
			ch1_xcvr_tx_preloaded_hardware_configs_atom         => "CH1_TX_PRELOADED_HARDWARE_CONFIGS_PCIE",
			ch1_xcvr_rx_preloaded_hardware_configs_atom         => "CH1_RX_PRELOADED_HARDWARE_CONFIGS_PCIE",
			ch1_lc_postdiv_sel_atom                             => "CH1_LC_POSTDIV_SEL_SYNTH2",
			ch1_sequencer_reg_en_atom                           => "CH1_SEQUENCER_REG_EN_DISABLE",
			ch1_rst_mux_static_sel_atom                         => "CH1_RST_MUX_STATIC_SEL_HRC",
			ch1_xcvr_tx_prbs_pattern_atom                       => "0000",
			ch1_xcvr_rx_prbs_pattern_atom                       => "0001",
			ch1_xcvr_tx_user_clk_only_mode_atom                 => "CH1_TX_USER_CLK_ONLY_MODE_DISABLE",
			ch1_xcvr_tx_width_atom                              => "CH1_TX_WIDTH_X16",
			ch1_xcvr_rx_width_atom                              => "CH1_RX_WIDTH_X16",
			ch1_phy_loopback_mode_atom                          => "CH1_LOOPBACK_MODE_DISABLED",
			ch1_flux_mode_atom                                  => "CH1_FLUX_MODE_FLUX_MODE_BYPASS",
			ch1_flux_mode_hw_atom                               => "CH1_FLUX_MODE_FLUX_MODE_BYPASS",
			ch1_tx_sim_mode_atom                                => "CH1_TX_SIM_MODE_DISABLE",
			ch1_rx_sim_mode_atom                                => "CH1_RX_SIM_MODE_DISABLE",
			ch1_tx_dl_enable_atom                               => "CH1_TX_DL_ENABLE_DISABLE",
			ch1_rx_dl_enable_atom                               => "CH1_RX_DL_ENABLE_DISABLE",
			ch1_rx_fec_type_used_atom                           => "CH1_RX_FEC_TYPE_USED_NONE",
			ch2_xcvr_tx_preloaded_hardware_configs_atom         => "CH2_TX_PRELOADED_HARDWARE_CONFIGS_PCIE",
			ch2_xcvr_rx_preloaded_hardware_configs_atom         => "CH2_RX_PRELOADED_HARDWARE_CONFIGS_PCIE",
			ch2_lc_postdiv_sel_atom                             => "CH2_LC_POSTDIV_SEL_SYNTH2",
			ch2_sequencer_reg_en_atom                           => "CH2_SEQUENCER_REG_EN_DISABLE",
			ch2_rst_mux_static_sel_atom                         => "CH2_RST_MUX_STATIC_SEL_HRC",
			ch2_xcvr_tx_prbs_pattern_atom                       => "0000",
			ch2_xcvr_rx_prbs_pattern_atom                       => "0011",
			ch2_xcvr_tx_user_clk_only_mode_atom                 => "CH2_TX_USER_CLK_ONLY_MODE_DISABLE",
			ch2_xcvr_tx_width_atom                              => "CH2_TX_WIDTH_X16",
			ch2_xcvr_rx_width_atom                              => "CH2_RX_WIDTH_X16",
			ch2_phy_loopback_mode_atom                          => "CH2_LOOPBACK_MODE_DISABLED",
			ch2_flux_mode_atom                                  => "CH2_FLUX_MODE_FLUX_MODE_BYPASS",
			ch2_flux_mode_hw_atom                               => "CH2_FLUX_MODE_FLUX_MODE_BYPASS",
			ch2_tx_sim_mode_atom                                => "CH2_TX_SIM_MODE_DISABLE",
			ch2_rx_sim_mode_atom                                => "CH2_RX_SIM_MODE_DISABLE",
			ch2_tx_dl_enable_atom                               => "CH2_TX_DL_ENABLE_DISABLE",
			ch2_rx_dl_enable_atom                               => "CH2_RX_DL_ENABLE_DISABLE",
			ch2_rx_fec_type_used_atom                           => "CH2_RX_FEC_TYPE_USED_NONE",
			ch3_xcvr_tx_preloaded_hardware_configs_atom         => "CH3_TX_PRELOADED_HARDWARE_CONFIGS_PCIE",
			ch3_xcvr_rx_preloaded_hardware_configs_atom         => "CH3_RX_PRELOADED_HARDWARE_CONFIGS_PCIE",
			ch3_lc_postdiv_sel_atom                             => "CH3_LC_POSTDIV_SEL_SYNTH2",
			ch3_sequencer_reg_en_atom                           => "CH3_SEQUENCER_REG_EN_ENABLE",
			ch3_rst_mux_static_sel_atom                         => "CH3_RST_MUX_STATIC_SEL_HRC",
			ch3_xcvr_tx_prbs_pattern_atom                       => "0000",
			ch3_xcvr_rx_prbs_pattern_atom                       => "0111",
			ch3_xcvr_tx_user_clk_only_mode_atom                 => "CH3_TX_USER_CLK_ONLY_MODE_DISABLE",
			ch3_xcvr_tx_width_atom                              => "CH3_TX_WIDTH_X16",
			ch3_xcvr_rx_width_atom                              => "CH3_RX_WIDTH_X16",
			ch3_phy_loopback_mode_atom                          => "CH3_LOOPBACK_MODE_DISABLED",
			ch3_flux_mode_atom                                  => "CH3_FLUX_MODE_FLUX_MODE_BYPASS",
			ch3_flux_mode_hw_atom                               => "CH3_FLUX_MODE_FLUX_MODE_BYPASS",
			ch3_tx_sim_mode_atom                                => "CH3_TX_SIM_MODE_DISABLE",
			ch3_rx_sim_mode_atom                                => "CH3_RX_SIM_MODE_DISABLE",
			ch3_tx_dl_enable_atom                               => "CH3_TX_DL_ENABLE_DISABLE",
			ch3_rx_dl_enable_atom                               => "CH3_RX_DL_ENABLE_DISABLE",
			ch3_rx_fec_type_used_atom                           => "CH3_RX_FEC_TYPE_USED_NONE",
			ch0_tx_pll_l_counter_atom                           => "000010",
			ch0_cdr_l_counter_atom                              => "000010",
			ch0_tx_pll_refclk_select_atom                       => "CH0_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0",
			ch0_cdr_refclk_select_atom                          => "CH0_CDR_REFCLK_SELECT_GLOBAL_REFCLK0",
			ch1_tx_pll_l_counter_atom                           => "000010",
			ch1_cdr_l_counter_atom                              => "000010",
			ch1_tx_pll_refclk_select_atom                       => "CH1_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0",
			ch1_cdr_refclk_select_atom                          => "CH1_CDR_REFCLK_SELECT_GLOBAL_REFCLK0",
			ch2_tx_pll_l_counter_atom                           => "000010",
			ch2_cdr_l_counter_atom                              => "000010",
			ch2_tx_pll_refclk_select_atom                       => "CH2_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0",
			ch2_cdr_refclk_select_atom                          => "CH2_CDR_REFCLK_SELECT_GLOBAL_REFCLK0",
			ch3_tx_pll_l_counter_atom                           => "000010",
			ch3_cdr_l_counter_atom                              => "000010",
			ch3_tx_pll_refclk_select_atom                       => "CH3_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0",
			ch3_cdr_refclk_select_atom                          => "CH3_CDR_REFCLK_SELECT_GLOBAL_REFCLK0",
			ch0_rx_dl_rx_lat_bit_for_async_atom                 => "010100000100010011",
			ch0_rx_dl_rxbit_cntr_pma_atom                       => "CH0_RX_DL_RXBIT_CNTR_PMA_DISABLE",
			ch0_rx_dl_rxbit_rollover_atom                       => "111110100100001111",
			ch1_rx_dl_rx_lat_bit_for_async_atom                 => "111110100110100101",
			ch1_rx_dl_rxbit_cntr_pma_atom                       => "CH1_RX_DL_RXBIT_CNTR_PMA_DISABLE",
			ch1_rx_dl_rxbit_rollover_atom                       => "001001111001000101",
			ch2_rx_dl_rx_lat_bit_for_async_atom                 => "111010100000111101",
			ch2_rx_dl_rxbit_cntr_pma_atom                       => "CH2_RX_DL_RXBIT_CNTR_PMA_DISABLE",
			ch2_rx_dl_rxbit_rollover_atom                       => "111000111110011110",
			ch3_rx_dl_rx_lat_bit_for_async_atom                 => "100000100111100001",
			ch3_rx_dl_rxbit_cntr_pma_atom                       => "CH3_RX_DL_RXBIT_CNTR_PMA_DISABLE",
			ch3_rx_dl_rxbit_rollover_atom                       => "001101111001101011",
			ch0_tx_bond_size_atom                               => "CH0_TX_BOND_SIZE_X4",
			ch1_tx_bond_size_atom                               => "CH1_TX_BOND_SIZE_X4",
			ch2_tx_bond_size_atom                               => "CH2_TX_BOND_SIZE_X4",
			ch3_tx_bond_size_atom                               => "CH3_TX_BOND_SIZE_X4",
			ch0_rx_invert_pin_atom                              => "CH0_RX_INVERT_PIN_DISABLE",
			ch1_rx_invert_pin_atom                              => "CH1_RX_INVERT_PIN_DISABLE",
			ch2_rx_invert_pin_atom                              => "CH2_RX_INVERT_PIN_DISABLE",
			ch3_rx_invert_pin_atom                              => "CH3_RX_INVERT_PIN_DISABLE",
			ch0_tx_invert_pin_atom                              => "CH0_TX_INVERT_PIN_DISABLE",
			ch1_tx_invert_pin_atom                              => "CH1_TX_INVERT_PIN_DISABLE",
			ch2_tx_invert_pin_atom                              => "CH2_TX_INVERT_PIN_DISABLE",
			ch3_tx_invert_pin_atom                              => "CH3_TX_INVERT_PIN_DISABLE",
			ch0_vsr_mode_atom                                   => "CH0_VSR_MODE_DISABLED",
			ch1_vsr_mode_atom                                   => "CH1_VSR_MODE_DISABLED",
			ch2_vsr_mode_atom                                   => "CH2_VSR_MODE_DISABLED",
			ch3_vsr_mode_atom                                   => "CH3_VSR_MODE_DISABLED",
			pcie_parity_bypass                                  => "true",
			rxbuf_limit_bypass                                  => 7,
			maxpayload_size                                     => "MAXPAYLOAD_SIZE_MAX_PAYLOAD_512",
			pldclk_rate                                         => "PLDCLK_RATE_FAST",
			port_type                                           => "PORT_TYPE_RP",
			sris_enable                                         => "SRIS_ENABLE_DISABLED",
			link_num                                            => "SRIS_ENABLE_DISABLED",
			sris_mode                                           => "false",
			sim_mode                                            => "SIM_MODE_DISABLE_VSIM_MODE",
			sup_mode                                            => "SUP_MODE_USER_MODE",
			cvp_enable                                          => "CVP_ENABLE_DISABLED",
			cii_monitor_en                                      => "CII_MONITOR_EN_DISABLE",
			pclk_clk_hz                                         => "00011101110011010110010100000000",
			pf0_cap_link_surprise_down_err_cap                  => "PF0_CAP_LINK_SURPRISE_DOWN_ERR_CAP_DISABLE",
			sys_clk_hz                                          => "00010001111000011010001100000000",
			link_rate                                           => "LINK_RATE_GEN3",
			link_width                                          => "LINK_WIDTH_X4",
			num_of_lanes                                        => "NUM_OF_LANES_NUM_4",
			pf0_dsp_16g_tx_preset0                              => 7,
			pf0_dsp_16g_tx_preset1                              => 7,
			pf0_dsp_16g_tx_preset2                              => 7,
			pf0_dsp_16g_tx_preset3                              => 7,
			pf0_dsp_16g_tx_preset4                              => 0,
			pf0_dsp_16g_tx_preset5                              => 0,
			pf0_dsp_16g_tx_preset6                              => 0,
			pf0_dsp_16g_tx_preset7                              => 0,
			pf0_dsp_16g_tx_preset8                              => 0,
			pf0_dsp_16g_tx_preset9                              => 0,
			pf0_dsp_16g_tx_preset10                             => 0,
			pf0_dsp_16g_tx_preset11                             => 0,
			pf0_dsp_16g_tx_preset12                             => 0,
			pf0_dsp_16g_tx_preset13                             => 0,
			pf0_dsp_16g_tx_preset14                             => 0,
			pf0_dsp_16g_tx_preset15                             => 0,
			pf0_dsp_tx_preset0                                  => 9,
			pf0_dsp_tx_preset1                                  => 9,
			pf0_dsp_tx_preset2                                  => 9,
			pf0_dsp_tx_preset3                                  => 9,
			pf0_dsp_tx_preset4                                  => 0,
			pf0_dsp_tx_preset5                                  => 0,
			pf0_dsp_tx_preset6                                  => 0,
			pf0_dsp_tx_preset7                                  => 0,
			pf0_dsp_tx_preset8                                  => 0,
			pf0_dsp_tx_preset9                                  => 0,
			pf0_dsp_tx_preset10                                 => 0,
			pf0_dsp_tx_preset11                                 => 0,
			pf0_dsp_tx_preset12                                 => 0,
			pf0_dsp_tx_preset13                                 => 0,
			pf0_dsp_tx_preset14                                 => 0,
			pf0_dsp_tx_preset15                                 => 0,
			pf0_usp_16g_tx_preset0                              => 7,
			pf0_usp_16g_tx_preset1                              => 7,
			pf0_usp_16g_tx_preset2                              => 7,
			pf0_usp_16g_tx_preset3                              => 7,
			pf0_usp_16g_tx_preset4                              => 0,
			pf0_usp_16g_tx_preset5                              => 0,
			pf0_usp_16g_tx_preset6                              => 0,
			pf0_usp_16g_tx_preset7                              => 0,
			pf0_usp_16g_tx_preset8                              => 0,
			pf0_usp_16g_tx_preset9                              => 0,
			pf0_usp_16g_tx_preset10                             => 0,
			pf0_usp_16g_tx_preset11                             => 0,
			pf0_usp_16g_tx_preset12                             => 0,
			pf0_usp_16g_tx_preset13                             => 0,
			pf0_usp_16g_tx_preset14                             => 0,
			pf0_usp_16g_tx_preset15                             => 0,
			pf0_usp_tx_preset0                                  => 9,
			pf0_usp_tx_preset1                                  => 9,
			pf0_usp_tx_preset2                                  => 9,
			pf0_usp_tx_preset3                                  => 9,
			pf0_usp_tx_preset4                                  => 0,
			pf0_usp_tx_preset5                                  => 0,
			pf0_usp_tx_preset6                                  => 0,
			pf0_usp_tx_preset7                                  => 0,
			pf0_usp_tx_preset8                                  => 0,
			pf0_usp_tx_preset9                                  => 0,
			pf0_usp_tx_preset10                                 => 0,
			pf0_usp_tx_preset11                                 => 0,
			pf0_usp_tx_preset12                                 => 0,
			pf0_usp_tx_preset13                                 => 0,
			pf0_usp_tx_preset14                                 => 0,
			pf0_usp_tx_preset15                                 => 0,
			pf0_pci_type0_bar0_enabled                          => "PF0_PCI_TYPE0_BAR0_ENABLED_DISABLED",
			pf0_pci_type0_bar0_mask_31_1                        => "00000000000000000000000000000000",
			pf0_bar0_prefetch                                   => "false",
			pf0_bar0_type                                       => "PF0_BAR0_TYPE_BAR_MEM32",
			pf0_pci_type0_bar1_enabled                          => "PF0_PCI_TYPE0_BAR1_ENABLED_DISABLED",
			pf0_pci_type0_bar1_mask_31_0                        => "00000000000000000000000000000000",
			pf0_bar1_prefetch                                   => "false",
			pf0_pci_type0_bar2_enabled                          => "PF0_PCI_TYPE0_BAR2_ENABLED_DISABLED",
			pf0_pci_type0_bar2_mask_31_1                        => "00000000000000000000000000000000",
			pf0_bar2_prefetch                                   => "false",
			pf0_bar2_type                                       => "PF0_BAR2_TYPE_BAR_MEM32",
			pf0_pci_type0_bar3_enabled                          => "PF0_PCI_TYPE0_BAR3_ENABLED_DISABLED",
			pf0_pci_type0_bar3_mask_31_0                        => "00000000000000000000000000000000",
			pf0_bar3_prefetch                                   => "false",
			pf0_pci_type0_bar4_enabled                          => "PF0_PCI_TYPE0_BAR4_ENABLED_DISABLED",
			pf0_pci_type0_bar4_mask_31_1                        => "00000000000000000000000000000000",
			pf0_bar4_prefetch                                   => "false",
			pf0_bar4_type                                       => "PF0_BAR4_TYPE_BAR_MEM32",
			pf0_pci_type0_bar5_enabled                          => "PF0_PCI_TYPE0_BAR5_ENABLED_DISABLED",
			pf0_pci_type0_bar5_mask_31_0                        => "00000000000000000000000000000000",
			pf0_bar5_prefetch                                   => "false",
			pf0_rom_bar_enable                                  => "PF0_ROM_BAR_ENABLE_DISABLED",
			pf0_rom_mask                                        => 0,
			pf0_rom_bar_enabled                                 => "PF0_ROM_BAR_ENABLED_DISABLED",
			pf0_rp_rom_bar_enabled                              => "PF0_RP_ROM_BAR_ENABLED_DISABLED",
			pf0_rp_rom_mask                                     => 0,
			pf0_sriov_vf_bar0_enabled                           => "PF0_SRIOV_VF_BAR0_ENABLED_DISABLED",
			pf0_sriov_vf_bar0_mask                              => "00000000000000000000000000000000",
			pf0_sriov_vf_bar0_prefetch                          => "false",
			pf0_sriov_vf_bar0_type                              => "PF0_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32",
			pf0_sriov_vf_bar1_enabled                           => "PF0_SRIOV_VF_BAR1_ENABLED_DISABLED",
			pf0_sriov_vf_bar1_mask                              => "00000000000000000000000000000000",
			pf0_sriov_vf_bar1_prefetch                          => "false",
			pf0_sriov_vf_bar2_enabled                           => "PF0_SRIOV_VF_BAR2_ENABLED_DISABLED",
			pf0_sriov_vf_bar2_mask                              => "00000000000000000000000000000000",
			pf0_sriov_vf_bar2_prefetch                          => "false",
			pf0_sriov_vf_bar2_type                              => "PF0_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32",
			pf0_sriov_vf_bar3_enabled                           => "PF0_SRIOV_VF_BAR3_ENABLED_DISABLED",
			pf0_sriov_vf_bar3_mask                              => "00000000000000000000000000000000",
			pf0_sriov_vf_bar3_prefetch                          => "false",
			pf0_sriov_vf_bar4_enabled                           => "PF0_SRIOV_VF_BAR4_ENABLED_DISABLED",
			pf0_sriov_vf_bar4_mask                              => "00000000000000000000000000000000",
			pf0_sriov_vf_bar4_prefetch                          => "false",
			pf0_sriov_vf_bar4_type                              => "PF0_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32",
			pf0_sriov_vf_bar5_enabled                           => "PF0_SRIOV_VF_BAR5_ENABLED_DISABLED",
			pf0_sriov_vf_bar5_mask                              => "00000000000000000000000000000000",
			pf0_sriov_vf_bar5_prefetch                          => "false",
			pf1_pci_type0_bar0_enabled                          => "PF1_PCI_TYPE0_BAR0_ENABLED_DISABLED",
			pf1_pci_type0_bar0_mask_31_1                        => "00000000000000000000000000000000",
			pf1_bar0_prefetch                                   => "false",
			pf1_bar0_type                                       => "PF1_BAR0_TYPE_BAR_MEM32",
			pf1_pci_type0_bar1_enabled                          => "PF1_PCI_TYPE0_BAR1_ENABLED_DISABLED",
			pf1_pci_type0_bar1_mask_31_0                        => "00000000000000000000000000000000",
			pf1_bar1_prefetch                                   => "false",
			pf1_pci_type0_bar2_enabled                          => "PF1_PCI_TYPE0_BAR2_ENABLED_DISABLED",
			pf1_pci_type0_bar2_mask_31_1                        => "00000000000000000000000000000000",
			pf1_bar2_prefetch                                   => "false",
			pf1_bar2_type                                       => "PF1_BAR2_TYPE_BAR_MEM32",
			pf1_pci_type0_bar3_enabled                          => "PF1_PCI_TYPE0_BAR3_ENABLED_DISABLED",
			pf1_pci_type0_bar3_mask_31_0                        => "00000000000000000000000000000000",
			pf1_bar3_prefetch                                   => "false",
			pf1_pci_type0_bar4_enabled                          => "PF1_PCI_TYPE0_BAR4_ENABLED_DISABLED",
			pf1_pci_type0_bar4_mask_31_1                        => "00000000000000000000000000000000",
			pf1_bar4_prefetch                                   => "false",
			pf1_bar4_type                                       => "PF1_BAR4_TYPE_BAR_MEM32",
			pf1_pci_type0_bar5_enabled                          => "PF1_PCI_TYPE0_BAR5_ENABLED_DISABLED",
			pf1_pci_type0_bar5_mask_31_0                        => "00000000000000000000000000000000",
			pf1_bar5_prefetch                                   => "false",
			pf1_rom_bar_enable                                  => "PF1_ROM_BAR_ENABLE_DISABLED",
			pf1_rom_mask                                        => 0,
			pf1_rom_bar_enabled                                 => "PF1_ROM_BAR_ENABLED_DISABLED",
			pf1_sriov_vf_bar0_enabled                           => "PF1_SRIOV_VF_BAR0_ENABLED_DISABLED",
			pf1_sriov_vf_bar0_mask                              => "00000000000000000000000000000000",
			pf1_sriov_vf_bar0_prefetch                          => "false",
			pf1_sriov_vf_bar0_type                              => "PF1_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32",
			pf1_sriov_vf_bar1_enabled                           => "PF1_SRIOV_VF_BAR1_ENABLED_DISABLED",
			pf1_sriov_vf_bar1_mask                              => "00000000000000000000000000000000",
			pf1_sriov_vf_bar1_prefetch                          => "false",
			pf1_sriov_vf_bar2_enabled                           => "PF1_SRIOV_VF_BAR2_ENABLED_DISABLED",
			pf1_sriov_vf_bar2_mask                              => "00000000000000000000000000000000",
			pf1_sriov_vf_bar2_prefetch                          => "false",
			pf1_sriov_vf_bar2_type                              => "PF1_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32",
			pf1_sriov_vf_bar3_enabled                           => "PF1_SRIOV_VF_BAR3_ENABLED_DISABLED",
			pf1_sriov_vf_bar3_mask                              => "00000000000000000000000000000000",
			pf1_sriov_vf_bar3_prefetch                          => "false",
			pf1_sriov_vf_bar4_enabled                           => "PF1_SRIOV_VF_BAR4_ENABLED_DISABLED",
			pf1_sriov_vf_bar4_mask                              => "00000000000000000000000000000000",
			pf1_sriov_vf_bar4_prefetch                          => "false",
			pf1_sriov_vf_bar4_type                              => "PF1_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32",
			pf1_sriov_vf_bar5_enabled                           => "PF1_SRIOV_VF_BAR5_ENABLED_DISABLED",
			pf1_sriov_vf_bar5_mask                              => "00000000000000000000000000000000",
			pf1_sriov_vf_bar5_prefetch                          => "false",
			pf2_pci_type0_bar0_enabled                          => "PF2_PCI_TYPE0_BAR0_ENABLED_DISABLED",
			pf2_pci_type0_bar0_mask_31_1                        => "00000000000000000000000000000000",
			pf2_bar0_prefetch                                   => "false",
			pf2_bar0_type                                       => "PF2_BAR0_TYPE_BAR_MEM32",
			pf2_pci_type0_bar1_enabled                          => "PF2_PCI_TYPE0_BAR1_ENABLED_DISABLED",
			pf2_pci_type0_bar1_mask_31_0                        => "00000000000000000000000000000000",
			pf2_bar1_prefetch                                   => "false",
			pf2_pci_type0_bar2_enabled                          => "PF2_PCI_TYPE0_BAR2_ENABLED_DISABLED",
			pf2_pci_type0_bar2_mask_31_1                        => "00000000000000000000000000000000",
			pf2_bar2_prefetch                                   => "false",
			pf2_bar2_type                                       => "PF2_BAR2_TYPE_BAR_MEM32",
			pf2_pci_type0_bar3_enabled                          => "PF2_PCI_TYPE0_BAR3_ENABLED_DISABLED",
			pf2_pci_type0_bar3_mask_31_0                        => "00000000000000000000000000000000",
			pf2_bar3_prefetch                                   => "false",
			pf2_pci_type0_bar4_enabled                          => "PF2_PCI_TYPE0_BAR4_ENABLED_DISABLED",
			pf2_pci_type0_bar4_mask_31_1                        => "00000000000000000000000000000000",
			pf2_bar4_prefetch                                   => "false",
			pf2_bar4_type                                       => "PF2_BAR4_TYPE_BAR_MEM32",
			pf2_pci_type0_bar5_enabled                          => "PF2_PCI_TYPE0_BAR5_ENABLED_DISABLED",
			pf2_pci_type0_bar5_mask_31_0                        => "00000000000000000000000000000000",
			pf2_bar5_prefetch                                   => "false",
			pf2_rom_bar_enable                                  => "PF2_ROM_BAR_ENABLE_DISABLED",
			pf2_rom_mask                                        => 0,
			pf2_rom_bar_enabled                                 => "PF2_ROM_BAR_ENABLED_DISABLED",
			pf2_sriov_vf_bar0_enabled                           => "PF2_SRIOV_VF_BAR0_ENABLED_DISABLED",
			pf2_sriov_vf_bar0_mask                              => "00000000000000000000000000000000",
			pf2_sriov_vf_bar0_prefetch                          => "false",
			pf2_sriov_vf_bar0_type                              => "PF2_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32",
			pf2_sriov_vf_bar1_enabled                           => "PF2_SRIOV_VF_BAR1_ENABLED_DISABLED",
			pf2_sriov_vf_bar1_mask                              => "00000000000000000000000000000000",
			pf2_sriov_vf_bar1_prefetch                          => "false",
			pf2_sriov_vf_bar2_enabled                           => "PF2_SRIOV_VF_BAR2_ENABLED_DISABLED",
			pf2_sriov_vf_bar2_mask                              => "00000000000000000000000000000000",
			pf2_sriov_vf_bar2_prefetch                          => "false",
			pf2_sriov_vf_bar2_type                              => "PF2_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32",
			pf2_sriov_vf_bar3_enabled                           => "PF2_SRIOV_VF_BAR3_ENABLED_DISABLED",
			pf2_sriov_vf_bar3_mask                              => "00000000000000000000000000000000",
			pf2_sriov_vf_bar3_prefetch                          => "false",
			pf2_sriov_vf_bar4_enabled                           => "PF2_SRIOV_VF_BAR4_ENABLED_DISABLED",
			pf2_sriov_vf_bar4_mask                              => "00000000000000000000000000000000",
			pf2_sriov_vf_bar4_prefetch                          => "false",
			pf2_sriov_vf_bar4_type                              => "PF2_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32",
			pf2_sriov_vf_bar5_enabled                           => "PF2_SRIOV_VF_BAR5_ENABLED_DISABLED",
			pf2_sriov_vf_bar5_mask                              => "00000000000000000000000000000000",
			pf2_sriov_vf_bar5_prefetch                          => "false",
			pf3_pci_type0_bar0_enabled                          => "PF3_PCI_TYPE0_BAR0_ENABLED_DISABLED",
			pf3_pci_type0_bar0_mask_31_1                        => "00000000000000000000000000000000",
			pf3_bar0_prefetch                                   => "false",
			pf3_bar0_type                                       => "PF3_BAR0_TYPE_BAR_MEM32",
			pf3_pci_type0_bar1_enabled                          => "PF3_PCI_TYPE0_BAR1_ENABLED_DISABLED",
			pf3_pci_type0_bar1_mask_31_0                        => "00000000000000000000000000000000",
			pf3_bar1_prefetch                                   => "false",
			pf3_pci_type0_bar2_enabled                          => "PF3_PCI_TYPE0_BAR2_ENABLED_DISABLED",
			pf3_pci_type0_bar2_mask_31_1                        => "00000000000000000000000000000000",
			pf3_bar2_prefetch                                   => "false",
			pf3_bar2_type                                       => "PF3_BAR2_TYPE_BAR_MEM32",
			pf3_pci_type0_bar3_enabled                          => "PF3_PCI_TYPE0_BAR3_ENABLED_DISABLED",
			pf3_pci_type0_bar3_mask_31_0                        => "00000000000000000000000000000000",
			pf3_bar3_prefetch                                   => "false",
			pf3_pci_type0_bar4_enabled                          => "PF3_PCI_TYPE0_BAR4_ENABLED_DISABLED",
			pf3_pci_type0_bar4_mask_31_1                        => "00000000000000000000000000000000",
			pf3_bar4_prefetch                                   => "false",
			pf3_bar4_type                                       => "PF3_BAR4_TYPE_BAR_MEM32",
			pf3_pci_type0_bar5_enabled                          => "PF3_PCI_TYPE0_BAR5_ENABLED_DISABLED",
			pf3_pci_type0_bar5_mask_31_0                        => "00000000000000000000000000000000",
			pf3_bar5_prefetch                                   => "false",
			pf3_rom_bar_enable                                  => "PF3_ROM_BAR_ENABLE_DISABLED",
			pf3_rom_mask                                        => 0,
			pf3_rom_bar_enabled                                 => "PF3_ROM_BAR_ENABLED_DISABLED",
			pf3_sriov_vf_bar0_enabled                           => "PF3_SRIOV_VF_BAR0_ENABLED_DISABLED",
			pf3_sriov_vf_bar0_mask                              => "00000000000000000000000000000000",
			pf3_sriov_vf_bar0_prefetch                          => "false",
			pf3_sriov_vf_bar0_type                              => "PF3_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32",
			pf3_sriov_vf_bar1_enabled                           => "PF3_SRIOV_VF_BAR1_ENABLED_DISABLED",
			pf3_sriov_vf_bar1_mask                              => "00000000000000000000000000000000",
			pf3_sriov_vf_bar1_prefetch                          => "false",
			pf3_sriov_vf_bar2_enabled                           => "PF3_SRIOV_VF_BAR2_ENABLED_DISABLED",
			pf3_sriov_vf_bar2_mask                              => "00000000000000000000000000000000",
			pf3_sriov_vf_bar2_prefetch                          => "false",
			pf3_sriov_vf_bar2_type                              => "PF3_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32",
			pf3_sriov_vf_bar3_enabled                           => "PF3_SRIOV_VF_BAR3_ENABLED_DISABLED",
			pf3_sriov_vf_bar3_mask                              => "00000000000000000000000000000000",
			pf3_sriov_vf_bar3_prefetch                          => "false",
			pf3_sriov_vf_bar4_enabled                           => "PF3_SRIOV_VF_BAR4_ENABLED_DISABLED",
			pf3_sriov_vf_bar4_mask                              => "00000000000000000000000000000000",
			pf3_sriov_vf_bar4_prefetch                          => "false",
			pf3_sriov_vf_bar4_type                              => "PF3_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32",
			pf3_sriov_vf_bar5_enabled                           => "PF3_SRIOV_VF_BAR5_ENABLED_DISABLED",
			pf3_sriov_vf_bar5_mask                              => "00000000000000000000000000000000",
			pf3_sriov_vf_bar5_prefetch                          => "false",
			pf1_enable                                          => "PF1_ENABLE_DISABLED",
			pf2_enable                                          => "PF2_ENABLE_DISABLED",
			pf3_enable                                          => "PF3_ENABLE_DISABLED",
			pf0_sriov_enable                                    => "PF0_SRIOV_ENABLE_DISABLED",
			pf1_sriov_enable                                    => "PF1_SRIOV_ENABLE_DISABLED",
			pf2_sriov_enable                                    => "PF2_SRIOV_ENABLE_DISABLED",
			pf3_sriov_enable                                    => "PF3_SRIOV_ENABLE_DISABLED",
			pf0_sriov_cap_sup_page_size                         => 0,
			pf1_sriov_cap_sup_page_size                         => 0,
			pf2_sriov_cap_sup_page_size                         => 0,
			pf3_sriov_cap_sup_page_size                         => 0,
			pf0_sriov_num_vf                                    => 0,
			pf1_sriov_num_vf                                    => 0,
			pf2_sriov_num_vf                                    => 0,
			pf3_sriov_num_vf                                    => 0,
			pf0_msi_enable                                      => "PF0_MSI_ENABLE_DISABLED",
			pf0_pci_msi_ext_data_cap                            => "false",
			pf0_pci_msi_ext_data_en                             => "false",
			pf0_pci_msi_64_bit_addr_cap                         => "false",
			pf0_pci_msi_multiple_msg_cap                        => "PF0_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1",
			pf0_msix_enable                                     => "PF0_MSIX_ENABLE_DISABLED",
			pf0_pci_msix_table_size                             => 0,
			pf0_pci_msix_table_offset                           => 0,
			pf0_pci_msix_bir                                    => 0,
			pf0_pci_msix_pba                                    => 0,
			pf0_pci_msix_pba_offset                             => 0,
			pf0_pci_msix_table_size_vfcomm_cs2                  => 0,
			pf0_exvf_msix_cap_enable                            => "PF0_EXVF_MSIX_CAP_ENABLE_DISABLED",
			exvf_msix_tablesize_pf0                             => 0,
			exvf_msixtable_offset_pf0                           => 0,
			exvf_msixtable_bir_pf0                              => 0,
			exvf_msixpba_offset_pf0                             => 0,
			exvf_msixpba_bir_pf0                                => 0,
			pf1_msi_enable                                      => "PF1_MSI_ENABLE_DISABLED",
			pf1_pci_msi_ext_data_cap                            => "false",
			pf1_pci_msi_ext_data_en                             => "false",
			pf1_pci_msi_64_bit_addr_cap                         => "false",
			pf1_pci_msi_multiple_msg_cap                        => "PF1_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1",
			pf1_msix_enable                                     => "PF1_MSIX_ENABLE_DISABLED",
			pf1_pci_msix_table_size                             => 0,
			pf1_pci_msix_table_offset                           => 0,
			pf1_pci_msix_bir                                    => 0,
			pf1_pci_msix_pba                                    => 0,
			pf1_pci_msix_pba_offset                             => 0,
			pf1_pci_msix_table_size_vfcomm_cs2                  => 0,
			pf1_exvf_msix_cap_enable                            => "PF1_EXVF_MSIX_CAP_ENABLE_DISABLED",
			exvf_msix_tablesize_pf1                             => 0,
			exvf_msixtable_offset_pf1                           => 0,
			exvf_msixtable_bir_pf1                              => 0,
			exvf_msixpba_offset_pf1                             => 0,
			exvf_msixpba_bir_pf1                                => 0,
			pf2_msi_enable                                      => "PF2_MSI_ENABLE_DISABLED",
			pf2_pci_msi_ext_data_cap                            => "false",
			pf2_pci_msi_ext_data_en                             => "false",
			pf2_pci_msi_64_bit_addr_cap                         => "false",
			pf2_pci_msi_multiple_msg_cap                        => "PF2_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1",
			pf2_msix_enable                                     => "PF2_MSIX_ENABLE_DISABLED",
			pf2_pci_msix_bir                                    => 0,
			pf2_pci_msix_pba                                    => 0,
			pf2_pci_msix_pba_offset                             => 0,
			pf2_pci_msix_table_offset                           => 0,
			pf2_pci_msix_table_size                             => 0,
			pf2_pci_msix_table_size_vfcomm_cs2                  => 0,
			pf2_exvf_msix_cap_enable                            => "PF2_EXVF_MSIX_CAP_ENABLE_DISABLED",
			exvf_msix_tablesize_pf2                             => 0,
			exvf_msixtable_offset_pf2                           => 0,
			exvf_msixtable_bir_pf2                              => 0,
			exvf_msixpba_offset_pf2                             => 0,
			exvf_msixpba_bir_pf2                                => 0,
			pf3_msi_enable                                      => "PF3_MSI_ENABLE_DISABLED",
			pf3_pci_msi_ext_data_cap                            => "false",
			pf3_pci_msi_ext_data_en                             => "false",
			pf3_pci_msi_64_bit_addr_cap                         => "false",
			pf3_pci_msi_multiple_msg_cap                        => "PF3_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1",
			pf3_msix_enable                                     => "PF3_MSIX_ENABLE_DISABLED",
			pf3_pci_msix_bir                                    => 0,
			pf3_pci_msix_pba                                    => 0,
			pf3_pci_msix_pba_offset                             => 0,
			pf3_pci_msix_table_offset                           => 0,
			pf3_pci_msix_table_size                             => 0,
			pf3_pci_msix_table_size_vfcomm_cs2                  => 0,
			pf3_exvf_msix_cap_enable                            => "PF3_EXVF_MSIX_CAP_ENABLE_DISABLED",
			exvf_msix_tablesize_pf3                             => 0,
			exvf_msixtable_offset_pf3                           => 0,
			exvf_msixtable_bir_pf3                              => 0,
			exvf_msixpba_offset_pf3                             => 0,
			exvf_msixpba_bir_pf3                                => 0,
			pf0_prs_ext_cap_enable                              => "PF0_PRS_EXT_CAP_ENABLE_DISABLED",
			pf0_prs_ext_cap_outstanding_capacity                => 0,
			pf1_prs_ext_cap_enable                              => "PF1_PRS_EXT_CAP_ENABLE_DISABLED",
			pf1_prs_ext_cap_outstanding_capacity                => 0,
			pf2_prs_ext_cap_enable                              => "PF2_PRS_EXT_CAP_ENABLE_DISABLED",
			pf2_prs_ext_cap_outstanding_capacity                => 0,
			pf3_prs_ext_cap_enable                              => "PF3_PRS_EXT_CAP_ENABLE_DISABLED",
			pf3_prs_ext_cap_outstanding_capacity                => 0,
			pf0_pasid_cap_enable                                => "PF0_PASID_CAP_ENABLE_DISABLED",
			pf0_pasid_cap_execute_permission_supported          => "PF0_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED",
			pf0_pasid_cap_max_pasid_width                       => 0,
			pf0_pasid_cap_privileged_mode_supported             => "PF0_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED",
			pf1_pasid_cap_enable                                => "PF1_PASID_CAP_ENABLE_DISABLED",
			pf1_pasid_cap_execute_permission_supported          => "PF1_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED",
			pf1_pasid_cap_max_pasid_width                       => 0,
			pf1_pasid_cap_privileged_mode_supported             => "PF1_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED",
			pf2_pasid_cap_enable                                => "PF2_PASID_CAP_ENABLE_DISABLED",
			pf2_pasid_cap_execute_permission_supported          => "PF2_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED",
			pf2_pasid_cap_max_pasid_width                       => 0,
			pf2_pasid_cap_privileged_mode_supported             => "PF2_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED",
			pf3_pasid_cap_enable                                => "PF3_PASID_CAP_ENABLE_DISABLED",
			pf3_pasid_cap_execute_permission_supported          => "PF3_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED",
			pf3_pasid_cap_max_pasid_width                       => 0,
			pf3_pasid_cap_privileged_mode_supported             => "PF3_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED",
			pf0_sn_cap_enable                                   => "PF0_SN_CAP_ENABLE_DISABLED",
			pf0_sn_ser_num_reg_1_dw                             => "00000000000000000000000000000000",
			pf0_sn_ser_num_reg_2_dw                             => "00000000000000000000000000000000",
			pf1_sn_cap_enable                                   => "PF1_SN_CAP_ENABLE_DISABLED",
			pf1_sn_ser_num_reg_1_dw                             => "00000000000000000000000000000000",
			pf1_sn_ser_num_reg_2_dw                             => "00000000000000000000000000000000",
			pf2_sn_cap_enable                                   => "PF2_SN_CAP_ENABLE_DISABLED",
			pf2_sn_ser_num_reg_1_dw                             => "00000000000000000000000000000000",
			pf2_sn_ser_num_reg_2_dw                             => "00000000000000000000000000000000",
			pf3_sn_cap_enable                                   => "PF3_SN_CAP_ENABLE_DISABLED",
			pf3_sn_ser_num_reg_1_dw                             => "00000000000000000000000000000000",
			pf3_sn_ser_num_reg_2_dw                             => "00000000000000000000000000000000",
			pf0_pcie_cap_ep_l0s_accpt_latency                   => 0,
			pf0_pcie_cap_ep_l1_accpt_latency                    => 0,
			pf0_pcie_cap_l0s_exit_latency_commclk_dis           => 7,
			pf0_pcie_cap_l1_exit_latency_commclk_dis            => 7,
			pf1_pcie_cap_ep_l0s_accpt_latency                   => 0,
			pf1_pcie_cap_ep_l1_accpt_latency                    => 0,
			pf1_pcie_cap_l0s_exit_latency_commclk_dis           => 0,
			pf1_pcie_cap_l1_exit_latency_commclk_dis            => 0,
			pf2_pcie_cap_ep_l0s_accpt_latency                   => 0,
			pf2_pcie_cap_ep_l1_accpt_latency                    => 0,
			pf2_pcie_cap_l0s_exit_latency_commclk_dis           => 0,
			pf2_pcie_cap_l1_exit_latency_commclk_dis            => 0,
			pf3_pcie_cap_ep_l0s_accpt_latency                   => 0,
			pf3_pcie_cap_ep_l1_accpt_latency                    => 0,
			pf3_pcie_cap_l0s_exit_latency_commclk_dis           => 0,
			pf3_pcie_cap_l1_exit_latency_commclk_dis            => 0,
			aspm_support                                        => "ASPM_SUPPORT_L0S_L1",
			dbi_ro_wr_disable                                   => "DBI_RO_WR_DISABLE_ENABLE",
			pf0_gen3_eq_pset_req_vec                            => 292,
			pf0_gen3_eq_pset_req_vec_atg4                       => 352,
			pf0_pcie_cap_flr_cap                                => "PF0_PCIE_CAP_FLR_CAP_NOT_CAPABLE",
			pf1_pcie_cap_flr_cap                                => "PF1_PCIE_CAP_FLR_CAP_NOT_CAPABLE",
			pf2_pcie_cap_flr_cap                                => "PF2_PCIE_CAP_FLR_CAP_NOT_CAPABLE",
			pf3_pcie_cap_flr_cap                                => "PF3_PCIE_CAP_FLR_CAP_NOT_CAPABLE",
			pf0_pcie_cap_port_num                               => 1,
			pf1_pcie_cap_port_num                               => 0,
			pf2_pcie_cap_port_num                               => 0,
			pf3_pcie_cap_port_num                               => 0,
			pf0_pcie_cap_slot_clk_config                        => "true",
			pf1_pcie_cap_slot_clk_config                        => "false",
			pf2_pcie_cap_slot_clk_config                        => "false",
			pf3_pcie_cap_slot_clk_config                        => "false",
			pf0_ltr_cap_enable                                  => "PF0_LTR_CAP_ENABLE_DISABLED",
			pf0_pcie_slot_imp                                   => "PF0_PCIE_SLOT_IMP_NOT_IMPLEMENTED",
			pf0_pcie_cap_slot_power_limit_scale                 => 0,
			pf0_pcie_cap_slot_power_limit_value                 => 0,
			pf0_pcie_cap_phy_slot_num                           => 0,
			pf0_pcie_cap_hot_plug_capable                       => "false",
			pf0_pcie_cap_ext_tag_en                             => "true",
			pf1_pcie_cap_ext_tag_en                             => "false",
			pf2_pcie_cap_ext_tag_en                             => "false",
			pf3_pcie_cap_ext_tag_en                             => "false",
			cfg_ptm_auto_update_signal                          => "false",
			ptm_autoupdate                                      => "PTM_AUTOUPDATE_AUTOUPDATE_DISABLE",
			ptm_enable                                          => "PTM_ENABLE_DISABLE",
			pf0_ats_cap_enable                                  => "PF0_ATS_CAP_ENABLE_DISABLED",
			pf0_exvf_ats_cap_enable                             => "PF0_EXVF_ATS_CAP_ENABLE_DISABLED",
			pf0_ats_cap_invalidate_q_depth                      => 0,
			pf0_ats_exvf_align_request                          => "PF0_ATS_EXVF_ALIGN_REQUEST_DISABLE",
			pf1_ats_cap_enable                                  => "PF1_ATS_CAP_ENABLE_DISABLED",
			pf1_exvf_ats_cap_enable                             => "PF1_EXVF_ATS_CAP_ENABLE_DISABLED",
			pf1_ats_cap_invalidate_q_depth                      => 0,
			pf1_ats_exvf_align_request                          => "PF1_ATS_EXVF_ALIGN_REQUEST_DISABLE",
			pf2_ats_cap_enable                                  => "PF2_ATS_CAP_ENABLE_DISABLED",
			pf2_exvf_ats_cap_enable                             => "PF2_EXVF_ATS_CAP_ENABLE_DISABLED",
			pf2_ats_cap_invalidate_q_depth                      => 0,
			pf2_ats_exvf_align_request                          => "PF2_ATS_EXVF_ALIGN_REQUEST_DISABLE",
			pf3_ats_cap_enable                                  => "PF3_ATS_CAP_ENABLE_DISABLED",
			pf3_exvf_ats_cap_enable                             => "PF3_EXVF_ATS_CAP_ENABLE_DISABLED",
			pf3_ats_cap_invalidate_q_depth                      => 0,
			pf3_ats_exvf_align_request                          => "PF3_ATS_EXVF_ALIGN_REQUEST_DISABLE",
			pf0_tph_cap_enable                                  => "PF0_TPH_CAP_ENABLE_DISABLED",
			pf0_tph_req_cap_int_vec                             => "PF0_TPH_REQ_CAP_INT_VEC_DISABLED",
			pf0_tph_req_cap_int_vec_vfcomm_cs2                  => "PF0_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED",
			pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2           => "PF0_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF",
			pf0_tph_req_cap_st_table_loc_1                      => "PF0_TPH_REQ_CAP_ST_TABLE_LOC_1_NOT_IN_MSIX_TABLE",
			pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2           => "PF0_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF",
			pf0_tph_req_cap_st_table_size                       => 0,
			pf0_tph_req_cap_st_table_size_vfcomm_cs2            => 0,
			pf0_tph_req_device_spec                             => "PF0_TPH_REQ_DEVICE_SPEC_DISABLED",
			pf0_tph_req_device_spec_vfcomm_cs2                  => "PF0_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED",
			pf0_exvf_tph_cap_enable                             => "PF0_EXVF_TPH_CAP_ENABLE_DISABLED",
			exvf_tph_sttablelocation_pf0                        => 0,
			exvf_tph_sttablesize_pf0                            => 0,
			pf1_tph_cap_enable                                  => "PF1_TPH_CAP_ENABLE_DISABLED",
			pf1_tph_req_cap_int_vec                             => "PF1_TPH_REQ_CAP_INT_VEC_DISABLED",
			pf1_tph_req_cap_int_vec_vfcomm_cs2                  => "PF1_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED",
			pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2           => "PF1_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF",
			pf1_tph_req_cap_st_table_loc_1                      => "PF1_TPH_REQ_CAP_ST_TABLE_LOC_1_NOT_IN_MSIX_TABLE",
			pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2           => "PF1_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF",
			pf1_tph_req_cap_st_table_size                       => 0,
			pf1_tph_req_cap_st_table_size_vfcomm_cs2            => 0,
			pf1_tph_req_device_spec                             => "PF1_TPH_REQ_DEVICE_SPEC_DISABLED",
			pf1_tph_req_device_spec_vfcomm_cs2                  => "PF1_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED",
			pf1_exvf_tph_cap_enable                             => "PF1_EXVF_TPH_CAP_ENABLE_DISABLED",
			exvf_tph_sttablelocation_pf1                        => 0,
			exvf_tph_sttablesize_pf1                            => 0,
			pf2_tph_cap_enable                                  => "PF2_TPH_CAP_ENABLE_DISABLED",
			pf2_tph_req_cap_int_vec                             => "PF2_TPH_REQ_CAP_INT_VEC_DISABLED",
			pf2_tph_req_cap_int_vec_vfcomm_cs2                  => "PF2_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED",
			pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2           => "PF2_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF",
			pf2_tph_req_cap_st_table_loc_1                      => "PF2_TPH_REQ_CAP_ST_TABLE_LOC_1_NOT_IN_MSIX_TABLE",
			pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2           => "PF2_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF",
			pf2_tph_req_cap_st_table_size                       => 0,
			pf2_tph_req_cap_st_table_size_vfcomm_cs2            => 0,
			pf2_tph_req_device_spec                             => "PF2_TPH_REQ_DEVICE_SPEC_DISABLED",
			pf2_tph_req_device_spec_vfcomm_cs2                  => "PF2_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED",
			pf2_exvf_tph_cap_enable                             => "PF2_EXVF_TPH_CAP_ENABLE_DISABLED",
			exvf_tph_sttablelocation_pf2                        => 0,
			exvf_tph_sttablesize_pf2                            => 0,
			pf3_tph_cap_enable                                  => "PF3_TPH_CAP_ENABLE_DISABLED",
			pf3_tph_req_cap_int_vec                             => "PF3_TPH_REQ_CAP_INT_VEC_DISABLED",
			pf3_tph_req_cap_int_vec_vfcomm_cs2                  => "PF3_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED",
			pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2           => "PF3_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF",
			pf3_tph_req_cap_st_table_loc_1                      => "PF3_TPH_REQ_CAP_ST_TABLE_LOC_1_NOT_IN_MSIX_TABLE",
			pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2           => "PF3_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF",
			pf3_tph_req_cap_st_table_size                       => 0,
			pf3_tph_req_cap_st_table_size_vfcomm_cs2            => 0,
			pf3_tph_req_device_spec                             => "PF3_TPH_REQ_DEVICE_SPEC_DISABLED",
			pf3_tph_req_device_spec_vfcomm_cs2                  => "PF3_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED",
			pf3_exvf_tph_cap_enable                             => "PF3_EXVF_TPH_CAP_ENABLE_DISABLED",
			exvf_tph_sttablelocation_pf3                        => 0,
			exvf_tph_sttablesize_pf3                            => 0,
			pf0_acs_cap_enable                                  => "PF0_ACS_CAP_ENABLE_DISABLED",
			pf0_exvf_acs_cap_enable                             => "PF0_EXVF_ACS_CAP_ENABLE_DISABLED",
			pf0_acs_cap_acs_src_valid                           => "PF0_ACS_CAP_ACS_SRC_VALID_DISABLED",
			pf0_acs_cap_acs_at_block                            => "PF0_ACS_CAP_ACS_AT_BLOCK_DISABLED",
			pf0_acs_cap_acs_p2p_req_redirect                    => "PF0_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED",
			pf0_acs_cap_acs_p2p_cpl_redirect                    => "PF0_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED",
			pf0_acs_cap_acs_usp_forwarding                      => "PF0_ACS_CAP_ACS_USP_FORWARDING_DISABLED",
			pf0_acs_cap_acs_p2p_egress_control                  => "PF0_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED",
			pf0_acs_cap_acs_egress_ctrl_size                    => 8,
			pf0_acs_cap_acs_direct_translated_p2p               => "PF0_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED",
			pf1_acs_cap_enable                                  => "PF1_ACS_CAP_ENABLE_DISABLED",
			pf1_exvf_acs_cap_enable                             => "PF1_EXVF_ACS_CAP_ENABLE_DISABLED",
			pf1_acs_cap_acs_src_valid                           => "PF1_ACS_CAP_ACS_SRC_VALID_DISABLED",
			pf1_acs_cap_acs_at_block                            => "PF1_ACS_CAP_ACS_AT_BLOCK_DISABLED",
			pf1_acs_cap_acs_p2p_req_redirect                    => "PF1_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED",
			pf1_acs_cap_acs_p2p_cpl_redirect                    => "PF1_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED",
			pf1_acs_cap_acs_usp_forwarding                      => "PF1_ACS_CAP_ACS_USP_FORWARDING_DISABLED",
			pf1_acs_cap_acs_p2p_egress_control                  => "PF1_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED",
			pf1_acs_cap_acs_egress_ctrl_size                    => 8,
			pf1_acs_cap_acs_direct_translated_p2p               => "PF1_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED",
			pf2_acs_cap_enable                                  => "PF2_ACS_CAP_ENABLE_DISABLED",
			pf2_exvf_acs_cap_enable                             => "PF2_EXVF_ACS_CAP_ENABLE_DISABLED",
			pf2_acs_cap_acs_src_valid                           => "PF2_ACS_CAP_ACS_SRC_VALID_DISABLED",
			pf2_acs_cap_acs_at_block                            => "PF2_ACS_CAP_ACS_AT_BLOCK_DISABLED",
			pf2_acs_cap_acs_p2p_req_redirect                    => "PF2_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED",
			pf2_acs_cap_acs_p2p_cpl_redirect                    => "PF2_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED",
			pf2_acs_cap_acs_usp_forwarding                      => "PF2_ACS_CAP_ACS_USP_FORWARDING_DISABLED",
			pf2_acs_cap_acs_p2p_egress_control                  => "PF2_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED",
			pf2_acs_cap_acs_egress_ctrl_size                    => 8,
			pf2_acs_cap_acs_direct_translated_p2p               => "PF2_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED",
			pf3_acs_cap_enable                                  => "PF3_ACS_CAP_ENABLE_DISABLED",
			pf3_exvf_acs_cap_enable                             => "PF3_EXVF_ACS_CAP_ENABLE_DISABLED",
			pf3_acs_cap_acs_src_valid                           => "PF3_ACS_CAP_ACS_SRC_VALID_DISABLED",
			pf3_acs_cap_acs_at_block                            => "PF3_ACS_CAP_ACS_AT_BLOCK_DISABLED",
			pf3_acs_cap_acs_p2p_req_redirect                    => "PF3_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED",
			pf3_acs_cap_acs_p2p_cpl_redirect                    => "PF3_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED",
			pf3_acs_cap_acs_usp_forwarding                      => "PF3_ACS_CAP_ACS_USP_FORWARDING_DISABLED",
			pf3_acs_cap_acs_p2p_egress_control                  => "PF3_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED",
			pf3_acs_cap_acs_egress_ctrl_size                    => 8,
			pf3_acs_cap_acs_direct_translated_p2p               => "PF3_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED",
			pf0_virtio_en                                       => "PF0_VIRTIO_EN_DISABLED",
			pf1_virtio_en                                       => "PF1_VIRTIO_EN_DISABLED",
			pf2_virtio_en                                       => "PF2_VIRTIO_EN_DISABLED",
			pf3_virtio_en                                       => "PF3_VIRTIO_EN_DISABLED",
			pf0_exvf_virtio_en                                  => "PF0_EXVF_VIRTIO_EN_DISABLED",
			pf1_exvf_virtio_en                                  => "PF1_EXVF_VIRTIO_EN_DISABLED",
			pf2_exvf_virtio_en                                  => "PF2_EXVF_VIRTIO_EN_DISABLED",
			pf3_exvf_virtio_en                                  => "PF3_EXVF_VIRTIO_EN_DISABLED",
			pf0_pci_type0_device_id                             => 0,
			pf0_pci_type0_vendor_id                             => 4466,
			pf0_revision_id                                     => 1,
			pf0_base_class_code                                 => 255,
			pf0_subclass_code                                   => 0,
			pf0_program_interface                               => 0,
			pf0_subsys_vendor_id                                => 0,
			pf0_subsys_dev_id                                   => 0,
			pf0_sriov_vf_device_id                              => 0,
			exvf_subsysid_pf0                                   => 0,
			pf1_pci_type0_vendor_id                             => 0,
			pf1_pci_type0_device_id                             => 0,
			pf1_revision_id                                     => 0,
			pf1_base_class_code                                 => 0,
			pf1_subclass_code                                   => 0,
			pf1_program_interface                               => 0,
			pf1_subsys_vendor_id                                => 0,
			pf1_subsys_dev_id                                   => 0,
			pf1_sriov_vf_device_id                              => 0,
			exvf_subsysid_pf1                                   => 0,
			pf2_pci_type0_vendor_id                             => 0,
			pf2_pci_type0_device_id                             => 0,
			pf2_revision_id                                     => 0,
			pf2_base_class_code                                 => 0,
			pf2_subclass_code                                   => 0,
			pf2_program_interface                               => 0,
			pf2_subsys_vendor_id                                => 0,
			pf2_subsys_dev_id                                   => 0,
			pf2_sriov_vf_device_id                              => 0,
			exvf_subsysid_pf2                                   => 0,
			pf3_pci_type0_vendor_id                             => 0,
			pf3_pci_type0_device_id                             => 0,
			pf3_revision_id                                     => 0,
			pf3_base_class_code                                 => 0,
			pf3_subclass_code                                   => 0,
			pf3_program_interface                               => 0,
			pf3_subsys_vendor_id                                => 0,
			pf3_subsys_dev_id                                   => 0,
			pf3_sriov_vf_device_id                              => 0,
			exvf_subsysid_pf3                                   => 0,
			vsec_select                                         => "false",
			pf0_user_vsec_cap_enable                            => "PF0_USER_VSEC_CAP_ENABLE_DISABLED",
			pf1_user_vsec_cap_enable                            => "PF1_USER_VSEC_CAP_ENABLE_DISABLED",
			pf2_user_vsec_cap_enable                            => "PF2_USER_VSEC_CAP_ENABLE_DISABLED",
			pf3_user_vsec_cap_enable                            => "PF3_USER_VSEC_CAP_ENABLE_DISABLED",
			vsec_next_offset                                    => 0,
			pf1_user_vsec_offset                                => 0,
			pf2_user_vsec_offset                                => 0,
			pf3_user_vsec_offset                                => 0,
			cvp_vendor_specific_header_id                       => 0,
			drop_vendor0_msg                                    => "FALSE",
			drop_vendor1_msg                                    => "FALSE",
			pf0_int_pin                                         => "PF0_INT_PIN_NO_INT",
			pf1_int_pin                                         => "PF1_INT_PIN_NO_INT",
			pf2_int_pin                                         => "PF2_INT_PIN_NO_INT",
			pf3_int_pin                                         => "PF3_INT_PIN_NO_INT",
			dtk_mode_en                                         => "DTK_MODE_EN_ENABLE",
			ecrc_strip                                          => "ECRC_STRIP_ENABLE",
			pf0_port_logic_fast_link_mode                       => "PF0_PORT_LOGIC_FAST_LINK_MODE_DISABLE",
			pf0_prefetch_decode                                 => "PF0_PREFETCH_DECODE_PREF32",
			pcie_pcs_mode                                       => "PCIE_PCS_MODE_PCIE",
			sm_hssi_pcie_pcs_clk_mux_0_sel                      => "SEL_SAME_QUAD_PCLK0",
			sm_hssi_pcie_pcs_clk_mux_1_sel                      => "SEL_SAME_QUAD_PCLK0",
			sm_hssi_pcie_pcs_clk_mux_2_sel                      => "SEL_SAME_QUAD_PCLK0",
			sm_hssi_pcie_pcs_clk_mux_3_sel                      => "SEL_SAME_QUAD_PCLK0",
			sm_hssi_pcie_pcs_hps_clkmux_0_sel                   => "SEL_HPS_PCS1_ENABLED",
			sm_hssi_pcie_pcs_rst_mux_0_sel                      => "SEL_SAME_QUAD_PCS_RST",
			sm_hssi_pcie_pcs_rst_mux_1_sel                      => "SEL_SAME_QUAD_PCS_RST",
			sm_hssi_pcie_pcs_rst_mux_2_sel                      => "SEL_SAME_QUAD_PCS_RST",
			sm_hssi_pcie_pcs_rst_mux_3_sel                      => "SEL_SAME_QUAD_PCS_RST",
			sm_hssi_pcie_pcs_tx_mux_0_sel                       => "SEL_SAME_QUAD_PCIE_CTRL",
			sm_hssi_pcie_pcs_tx_mux_1_sel                       => "SEL_SAME_QUAD_PCIE_CTRL",
			sm_hssi_pcie_pcs_tx_mux_2_sel                       => "SEL_SAME_QUAD_PCIE_CTRL",
			sm_hssi_pcie_pcs_tx_mux_3_sel                       => "SEL_SAME_QUAD_PCIE_CTRL",
			sm_hssi_pcie_pcs_hps_demux_0_sel                    => "SEL_HPS_PCS1_ENABLED",
			sm_hssi_pcie_pcs_hps_mux_0_sel                      => "SEL_HPS_PCS1_ENABLED",
			sm_hssi_pcie_pcs_rx_demux_0_sel                     => "SEL_SAME_QUAD_PCIE_CTRL",
			sm_hssi_pcie_pcs_rx_demux_1_sel                     => "SEL_SAME_QUAD_PCIE_CTRL",
			sm_hssi_pcie_pcs_rx_demux_2_sel                     => "SEL_SAME_QUAD_PCIE_CTRL",
			sm_hssi_pcie_pcs_rx_demux_3_sel                     => "SEL_SAME_QUAD_PCIE_CTRL",
			sm_hssi_pcie_clk_mux_0_sel                          => "SEL_MIDDLE",
			sm_hssi_pcie_data_mux_0_sel                         => "SEL_MIDDLE",
			sm_hssi_pld_chnl_dp_0_dr_enabled                    => "DR_ENABLED_DR_DISABLED",
			sm_hssi_pld_chnl_dp_0_duplex_mode                   => "DUPLEX_MODE_DUPLEX",
			sm_hssi_pld_chnl_dp_0_pld_channel_identifier        => "PLD_CHANNEL_IDENTIFIER_PHIP",
			sm_hssi_pld_chnl_dp_0_rx_clkout1_divider            => "RX_CLKOUT1_DIVIDER_DIV1",
			sm_hssi_pld_chnl_dp_0_rx_clkout2_divider            => "RX_CLKOUT2_DIVIDER_DIV1",
			sm_hssi_pld_chnl_dp_0_rx_en                         => "TRUE",
			sm_hssi_pld_chnl_dp_0_rx_fifo_mode                  => "RX_FIFO_MODE_PHASE_COMP",
			sm_hssi_pld_chnl_dp_0_rx_fifo_width                 => "RX_FIFO_WIDTH_DOUBLE_DOUBLE_WIDTH",
			sm_hssi_pld_chnl_dp_0_rx_fifo_wr_clk_hz             => "000000011101110011010110010100000000",
			sm_hssi_pld_chnl_dp_0_rx_user1_clk_dynamic_mux      => "RX_USER1_CLK_DYNAMIC_MUX_C2",
			sm_hssi_pld_chnl_dp_0_rx_user2_clk_dynamic_mux      => "RX_USER2_CLK_DYNAMIC_MUX_UX",
			sm_hssi_pld_chnl_dp_0_sup_mode                      => "SUP_MODE_USER_MODE",
			sm_hssi_pld_chnl_dp_0_tx_clkout1_divider            => "TX_CLKOUT1_DIVIDER_DIV1",
			sm_hssi_pld_chnl_dp_0_tx_clkout2_divider            => "TX_CLKOUT2_DIVIDER_DIV1",
			sm_hssi_pld_chnl_dp_0_tx_en                         => "TRUE",
			sm_hssi_pld_chnl_dp_0_tx_fifo_mode                  => "TX_FIFO_MODE_PHASE_COMP",
			sm_hssi_pld_chnl_dp_0_tx_fifo_rd_clk_hz             => "000000011101110011010110010100000000",
			sm_hssi_pld_chnl_dp_0_tx_fifo_width                 => "TX_FIFO_WIDTH_DOUBLE_DOUBLE_WIDTH",
			sm_hssi_pld_chnl_dp_0_tx_user1_clk_dynamic_mux      => "TX_USER1_CLK_DYNAMIC_MUX_C1",
			sm_hssi_pld_chnl_dp_0_tx_user2_clk_dynamic_mux      => "TX_USER2_CLK_DYNAMIC_MUX_UNUSED",
			sm_hssi_pld_chnl_dp_0_vc_rx_pldif_wm_en             => "VC_RX_PLDIF_WM_EN_DISABLE",
			sm_pld_rx_mux_0_sel                                 => "SEL_PCIE",
			sm_pld_tx_demux_0_sel                               => "SEL_PCIE",
			sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_sel           => "SEL_PCIE",
			sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_sel           => "SEL_PCIE"
		)
		port map (
			i_hio_txdata                                         => i_hio_txdata,                                                                       --                           i_hio_txdata.data
			i_hio_txdata_extra                                   => i_hio_txdata_extra,                                                                 --                     i_hio_txdata_extra.data
			i_hio_txdata_fifo_wr_en                              => i_hio_txdata_fifo_wr_en,                                                            --                i_hio_txdata_fifo_wr_en.data
			i_hio_rxdata_fifo_rd_en                              => i_hio_rxdata_fifo_rd_en,                                                            --                i_hio_rxdata_fifo_rd_en.data
			i_hio_ptp_rst_n                                      => i_hio_ptp_rst_n,                                                                    --                        i_hio_ptp_rst_n.reset
			i_hio_ehip_rx_rst_n                                  => i_hio_ehip_rx_rst_n,                                                                --                    i_hio_ehip_rx_rst_n.reset
			i_hio_ehip_tx_rst_n                                  => i_hio_ehip_tx_rst_n,                                                                --                    i_hio_ehip_tx_rst_n.reset
			i_hio_ehip_signal_ok                                 => i_hio_ehip_signal_ok,                                                               --                   i_hio_ehip_signal_ok.reset
			i_hio_sfreeze_2_r03f_rx_mac_srfz_n                   => i_hio_sfreeze_2_r03f_rx_mac_srfz_n,                                                 --     i_hio_sfreeze_2_r03f_rx_mac_srfz_n.reset
			i_hio_sfreeze_3_c2f_tx_deskew_srfz_n                 => i_hio_sfreeze_3_c2f_tx_deskew_srfz_n,                                               --   i_hio_sfreeze_3_c2f_tx_deskew_srfz_n.reset
			i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n                   => i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n,                                                 --     i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n.reset
			i_hio_rstfec_fec_rx_rst_n                            => i_hio_rstfec_fec_rx_rst_n,                                                          --              i_hio_rstfec_fec_rx_rst_n.reset
			i_hio_rstfec_fec_tx_rst_n                            => i_hio_rstfec_fec_tx_rst_n,                                                          --              i_hio_rstfec_fec_tx_rst_n.reset
			i_hio_rstfec_fec_csr_ret                             => i_hio_rstfec_fec_csr_ret,                                                           --               i_hio_rstfec_fec_csr_ret.reset
			i_hio_rstfec_rx_fec_sfrz_n                           => i_hio_rstfec_rx_fec_sfrz_n,                                                         --             i_hio_rstfec_rx_fec_sfrz_n.reset
			i_hio_rstfec_tx_fec_sfrz_n                           => i_hio_rstfec_tx_fec_sfrz_n,                                                         --             i_hio_rstfec_tx_fec_sfrz_n.reset
			i_hio_rstxcvrif_xcvrif_rx_rst_n                      => i_hio_rstxcvrif_xcvrif_rx_rst_n,                                                    --        i_hio_rstxcvrif_xcvrif_rx_rst_n.reset
			i_hio_rstxcvrif_xcvrif_tx_rst_n                      => i_hio_rstxcvrif_xcvrif_tx_rst_n,                                                    --        i_hio_rstxcvrif_xcvrif_tx_rst_n.reset
			i_hio_rstxcvrif_xcvrif_signal_ok                     => i_hio_rstxcvrif_xcvrif_signal_ok,                                                   --       i_hio_rstxcvrif_xcvrif_signal_ok.reset
			i_hio_rstxcvrif_rx_xcvrif_sfrz_n                     => i_hio_rstxcvrif_rx_xcvrif_sfrz_n,                                                   --       i_hio_rstxcvrif_rx_xcvrif_sfrz_n.reset
			i_hio_rstxcvrif_tx_xcvrif_sfrz_n                     => i_hio_rstxcvrif_tx_xcvrif_sfrz_n,                                                   --       i_hio_rstxcvrif_tx_xcvrif_sfrz_n.reset
			i_hio_rst_pld_clrhip                                 => i_hio_rst_pld_clrhip,                                                               --                   i_hio_rst_pld_clrhip.reset
			i_hio_rst_pld_clrpcs                                 => i_hio_rst_pld_clrpcs,                                                               --                   i_hio_rst_pld_clrpcs.reset
			i_hio_rst_pld_perstn                                 => i_hio_rst_pld_perstn,                                                               --                   i_hio_rst_pld_perstn.reset
			i_hio_rst_pld_ready                                  => i_hio_rst_pld_ready,                                                                --                    i_hio_rst_pld_ready.reset
			i_hio_rst_pld_adapter_rx_pld_rst_n                   => i_hio_rst_pld_adapter_rx_pld_rst_n,                                                 --     i_hio_rst_pld_adapter_rx_pld_rst_n.reset
			i_hio_rst_pld_adapter_tx_pld_rst_n                   => i_hio_rst_pld_adapter_tx_pld_rst_n,                                                 --     i_hio_rst_pld_adapter_tx_pld_rst_n.reset
			i_hio_rst_ux_rx_pma_rst_n                            => i_hio_rst_ux_rx_pma_rst_n,                                                          --              i_hio_rst_ux_rx_pma_rst_n.reset
			i_hio_rst_ux_rx_sfrz                                 => i_hio_rst_ux_rx_sfrz,                                                               --                   i_hio_rst_ux_rx_sfrz.reset
			i_hio_rst_ux_tx_pma_rst_n                            => i_hio_rst_ux_tx_pma_rst_n,                                                          --              i_hio_rst_ux_tx_pma_rst_n.reset
			i_hio_pld_reset_clk_row                              => i_hio_pld_reset_clk_row,                                                            --                i_hio_pld_reset_clk_row.reset
			i_hio_uxquad_async                                   => i_hio_uxquad_async,                                                                 --                     i_hio_uxquad_async.data
			i_hio_uxquad_async_pcie_mux                          => i_hio_uxquad_async_pcie_mux,                                                        --            i_hio_uxquad_async_pcie_mux.data
			rx_serial_n                                          => rx_serial_n,                                                                        --                            rx_serial_n.data
			rx_serial_p                                          => rx_serial_p,                                                                        --                            rx_serial_p.data
			o_hio_txdata_fifo_wr_empty                           => o_hio_txdata_fifo_wr_empty,                                                         --             o_hio_txdata_fifo_wr_empty.data
			o_hio_txdata_fifo_wr_pempty                          => o_hio_txdata_fifo_wr_pempty,                                                        --            o_hio_txdata_fifo_wr_pempty.data
			o_hio_txdata_fifo_wr_full                            => o_hio_txdata_fifo_wr_full,                                                          --              o_hio_txdata_fifo_wr_full.data
			o_hio_txdata_fifo_wr_pfull                           => o_hio_txdata_fifo_wr_pfull,                                                         --             o_hio_txdata_fifo_wr_pfull.data
			o_hio_rxdata                                         => o_hio_rxdata,                                                                       --                           o_hio_rxdata.data
			o_hio_rxdata_extra                                   => o_hio_rxdata_extra,                                                                 --                     o_hio_rxdata_extra.data
			o_hio_rxdata_fifo_rd_empty                           => o_hio_rxdata_fifo_rd_empty,                                                         --             o_hio_rxdata_fifo_rd_empty.data
			o_hio_rxdata_fifo_rd_pempty                          => o_hio_rxdata_fifo_rd_pempty,                                                        --            o_hio_rxdata_fifo_rd_pempty.data
			o_hio_rxdata_fifo_rd_full                            => o_hio_rxdata_fifo_rd_full,                                                          --              o_hio_rxdata_fifo_rd_full.data
			o_hio_rxdata_fifo_rd_pfull                           => o_hio_rxdata_fifo_rd_pfull,                                                         --             o_hio_rxdata_fifo_rd_pfull.data
			o_hio_rstepcs_rx_pcs_fully_aligned                   => o_hio_rstepcs_rx_pcs_fully_aligned,                                                 --     o_hio_rstepcs_rx_pcs_fully_aligned.reset
			o_hio_rstfec_fec_rx_rdy_n                            => o_hio_rstfec_fec_rx_rdy_n,                                                          --              o_hio_rstfec_fec_rx_rdy_n.reset
			o_hio_rst_flux0_cpi_cmn_busy                         => o_hio_rst_flux0_cpi_cmn_busy,                                                       --           o_hio_rst_flux0_cpi_cmn_busy.reset
			o_hio_rst_oflux_rx_srds_rdy                          => o_hio_rst_oflux_rx_srds_rdy,                                                        --            o_hio_rst_oflux_rx_srds_rdy.reset
			o_hio_rst_ux_all_synthlockstatus                     => o_hio_rst_ux_all_synthlockstatus,                                                   --       o_hio_rst_ux_all_synthlockstatus.reset
			o_hio_rst_ux_octl_pcs_rxstatus                       => o_hio_rst_ux_octl_pcs_rxstatus,                                                     --         o_hio_rst_ux_octl_pcs_rxstatus.reset
			o_hio_rst_ux_octl_pcs_txstatus                       => o_hio_rst_ux_octl_pcs_txstatus,                                                     --         o_hio_rst_ux_octl_pcs_txstatus.reset
			o_hio_rst_ux_rxcdrlock2data                          => o_hio_rst_ux_rxcdrlock2data,                                                        --            o_hio_rst_ux_rxcdrlock2data.reset
			o_hio_rst_ux_rxcdrlockstatus                         => o_hio_rst_ux_rxcdrlockstatus,                                                       --           o_hio_rst_ux_rxcdrlockstatus.reset
			o_hio_uxquad_async                                   => o_hio_uxquad_async,                                                                 --                     o_hio_uxquad_async.data
			tx_serial_p                                          => tx_serial_p,                                                                        --                            tx_serial_p.data
			tx_serial_n                                          => tx_serial_n,                                                                        --                            tx_serial_n.data
			i_hio_txdata_async                                   => i_hio_txdata_async,                                                                 --                     i_hio_txdata_async.data
			i_hio_txdata_direct                                  => i_hio_txdata_direct,                                                                --                    i_hio_txdata_direct.data
			o_hio_rxdata_async                                   => o_hio_rxdata_async,                                                                 --                     o_hio_rxdata_async.data
			o_hio_rxdata_direct                                  => o_hio_rxdata_direct,                                                                --                    o_hio_rxdata_direct.data
			ioack_cdrdiv_left_ux_bidir_out                       => ioack_cdrdiv_left_ux_bidir_out,                                                     --         ioack_cdrdiv_left_ux_bidir_out.data
			i_refclk_tx_p                                        => i_refclk_tx_p,                                                                      --                          i_refclk_tx_p.clk
			i_syspll_c0_clk                                      => i_syspll_c0_clk,                                                                    --                        i_syspll_c0_clk.clk
			i_syspll_c1_clk                                      => i_syspll_c1_clk,                                                                    --                        i_syspll_c1_clk.clk
			i_syspll_c2_clk                                      => i_syspll_c2_clk,                                                                    --                        i_syspll_c2_clk.clk
			i_flux_clk                                           => i_flux_clk,                                                                         --                             i_flux_clk.clk
			i_flux_clk_1                                         => i_flux_clk_1,                                                                       --                           i_flux_clk_1.clk
			i_refclk_rx_p                                        => i_refclk_rx_p,                                                                      --                          i_refclk_rx_p.clk
			i_ss_vccl_syspll_locked                              => i_ss_vccl_syspll_locked,                                                            --                i_ss_vccl_syspll_locked.clk
			o_hio_pcie_user_rx_clk1_clk                          => o_hio_pcie_user_rx_clk1_clk,                                                        --            o_hio_pcie_user_rx_clk1_clk.clk
			o_hio_pcie_user_rx_clk2_clk                          => o_hio_pcie_user_rx_clk2_clk,                                                        --            o_hio_pcie_user_rx_clk2_clk.clk
			o_hio_pcie_user_tx_clk1_clk                          => o_hio_pcie_user_tx_clk1_clk,                                                        --            o_hio_pcie_user_tx_clk1_clk.clk
			o_hio_pcie_user_tx_clk2_clk                          => o_hio_pcie_user_tx_clk2_clk,                                                        --            o_hio_pcie_user_tx_clk2_clk.clk
			i_pin_perst_n                                        => i_pin_perst_n,                                                                      --                               phip_hal.i_pin_perst_n
			i_pin_perst_n_1                                      => i_pin_perst_n_1,                                                                    --                                       .i_pin_perst_n_1
			i_hio_ch0_lavmm_clk                                  => i_hio_ch0_lavmm_clk,                                                                --                    i_hio_ch0_lavmm_clk.clk
			i_hio_ch0_lavmm_rstn                                 => i_hio_ch0_lavmm_rstn,                                                               --                   i_hio_ch0_lavmm_rstn.reset
			i_hio_ch0_lavmm_addr                                 => i_hio_ch0_lavmm_addr,                                                               --                          hio_ch0_lavmm.address
			i_hio_ch0_lavmm_be                                   => i_hio_ch0_lavmm_be,                                                                 --                                       .byteenable
			o_hio_ch0_lavmm_rdata_valid                          => o_hio_ch0_lavmm_rdata_valid,                                                        --                                       .readdatavalid
			i_hio_ch0_lavmm_read                                 => i_hio_ch0_lavmm_read,                                                               --                                       .read
			i_hio_ch0_lavmm_write                                => i_hio_ch0_lavmm_write,                                                              --                                       .write
			o_hio_ch0_lavmm_rdata                                => o_hio_ch0_lavmm_rdata,                                                              --                                       .readdata
			i_hio_ch0_lavmm_wdata                                => i_hio_ch0_lavmm_wdata,                                                              --                                       .writedata
			o_hio_ch0_lavmm_waitreq                              => o_hio_ch0_lavmm_waitreq,                                                            --                                       .waitrequest
			i_hio_ch0_pld_rx_clk_in_row_clk                      => i_hio_ch0_pld_rx_clk_in_row_clk,                                                    --        i_hio_ch0_pld_rx_clk_in_row_clk.clk
			i_hio_ch0_pld_tx_clk_in_row_clk                      => i_hio_ch0_pld_tx_clk_in_row_clk,                                                    --        i_hio_ch0_pld_tx_clk_in_row_clk.clk
			i_hio_ch0_det_lat_rx_dl_clk                          => i_hio_ch0_det_lat_rx_dl_clk,                                                        --            i_hio_ch0_det_lat_rx_dl_clk.clk
			i_hio_ch0_det_lat_rx_mux_select                      => i_hio_ch0_det_lat_rx_mux_select,                                                    --        i_hio_ch0_det_lat_rx_mux_select.clk
			i_hio_ch0_det_lat_rx_sclk_flop                       => i_hio_ch0_det_lat_rx_sclk_flop,                                                     --         i_hio_ch0_det_lat_rx_sclk_flop.clk
			i_hio_ch0_det_lat_rx_sclk_gen_clk                    => i_hio_ch0_det_lat_rx_sclk_gen_clk,                                                  --      i_hio_ch0_det_lat_rx_sclk_gen_clk.clk
			i_hio_ch0_det_lat_rx_trig_flop                       => i_hio_ch0_det_lat_rx_trig_flop,                                                     --         i_hio_ch0_det_lat_rx_trig_flop.clk
			i_hio_ch0_det_lat_sampling_clk                       => i_hio_ch0_det_lat_sampling_clk,                                                     --         i_hio_ch0_det_lat_sampling_clk.clk
			i_hio_ch0_det_lat_tx_dl_clk                          => i_hio_ch0_det_lat_tx_dl_clk,                                                        --            i_hio_ch0_det_lat_tx_dl_clk.clk
			i_hio_ch0_det_lat_tx_mux_select                      => i_hio_ch0_det_lat_tx_mux_select,                                                    --        i_hio_ch0_det_lat_tx_mux_select.clk
			i_hio_ch0_det_lat_tx_sclk_flop                       => i_hio_ch0_det_lat_tx_sclk_flop,                                                     --         i_hio_ch0_det_lat_tx_sclk_flop.clk
			i_hio_ch0_det_lat_tx_sclk_gen_clk                    => i_hio_ch0_det_lat_tx_sclk_gen_clk,                                                  --      i_hio_ch0_det_lat_tx_sclk_gen_clk.clk
			i_hio_ch0_det_lat_tx_trig_flop                       => i_hio_ch0_det_lat_tx_trig_flop,                                                     --         i_hio_ch0_det_lat_tx_trig_flop.clk
			o_hio_ch0_user_rx_clk1_clk                           => o_hio_ch0_user_rx_clk1_clk,                                                         --             o_hio_ch0_user_rx_clk1_clk.clk
			o_hio_ch0_user_rx_clk2_clk                           => o_hio_ch0_user_rx_clk2_clk,                                                         --             o_hio_ch0_user_rx_clk2_clk.clk
			o_hio_ch0_user_tx_clk1_clk                           => o_hio_ch0_user_tx_clk1_clk,                                                         --             o_hio_ch0_user_tx_clk1_clk.clk
			o_hio_ch0_user_tx_clk2_clk                           => o_hio_ch0_user_tx_clk2_clk,                                                         --             o_hio_ch0_user_tx_clk2_clk.clk
			o_hio_ch0_ux_chnl_refclk_mux                         => o_hio_ch0_ux_chnl_refclk_mux,                                                       --           o_hio_ch0_ux_chnl_refclk_mux.clk
			o_hio_ch0_det_lat_rx_async_dl_sync                   => o_hio_ch0_det_lat_rx_async_dl_sync,                                                 --     o_hio_ch0_det_lat_rx_async_dl_sync.clk
			o_hio_ch0_det_lat_rx_async_pulse                     => o_hio_ch0_det_lat_rx_async_pulse,                                                   --       o_hio_ch0_det_lat_rx_async_pulse.clk
			o_hio_ch0_det_lat_rx_async_sample_sync               => o_hio_ch0_det_lat_rx_async_sample_sync,                                             -- o_hio_ch0_det_lat_rx_async_sample_sync.clk
			o_hio_ch0_det_lat_rx_sclk_sample_sync                => o_hio_ch0_det_lat_rx_sclk_sample_sync,                                              --  o_hio_ch0_det_lat_rx_sclk_sample_sync.clk
			o_hio_ch0_det_lat_rx_trig_sample_sync                => o_hio_ch0_det_lat_rx_trig_sample_sync,                                              --  o_hio_ch0_det_lat_rx_trig_sample_sync.clk
			o_hio_ch0_det_lat_tx_async_dl_sync                   => o_hio_ch0_det_lat_tx_async_dl_sync,                                                 --     o_hio_ch0_det_lat_tx_async_dl_sync.clk
			o_hio_ch0_det_lat_tx_async_pulse                     => o_hio_ch0_det_lat_tx_async_pulse,                                                   --       o_hio_ch0_det_lat_tx_async_pulse.clk
			o_hio_ch0_det_lat_tx_async_sample_sync               => o_hio_ch0_det_lat_tx_async_sample_sync,                                             -- o_hio_ch0_det_lat_tx_async_sample_sync.clk
			o_hio_ch0_det_lat_tx_sclk_sample_sync                => o_hio_ch0_det_lat_tx_sclk_sample_sync,                                              --  o_hio_ch0_det_lat_tx_sclk_sample_sync.clk
			o_hio_ch0_det_lat_tx_trig_sample_sync                => o_hio_ch0_det_lat_tx_trig_sample_sync,                                              --  o_hio_ch0_det_lat_tx_trig_sample_sync.clk
			o_hio_ch0_xcvrif_rx_latency_pulse                    => o_hio_ch0_xcvrif_rx_latency_pulse,                                                  --      o_hio_ch0_xcvrif_rx_latency_pulse.clk
			o_hio_ch0_xcvrif_tx_latency_pulse                    => o_hio_ch0_xcvrif_tx_latency_pulse,                                                  --      o_hio_ch0_xcvrif_tx_latency_pulse.clk
			i_hio_ch1_lavmm_clk                                  => i_hio_ch1_lavmm_clk,                                                                --                    i_hio_ch1_lavmm_clk.clk
			i_hio_ch1_lavmm_rstn                                 => i_hio_ch1_lavmm_rstn,                                                               --                   i_hio_ch1_lavmm_rstn.reset
			i_hio_ch1_lavmm_addr                                 => i_hio_ch1_lavmm_addr,                                                               --                          hio_ch1_lavmm.address
			i_hio_ch1_lavmm_be                                   => i_hio_ch1_lavmm_be,                                                                 --                                       .byteenable
			o_hio_ch1_lavmm_rdata_valid                          => o_hio_ch1_lavmm_rdata_valid,                                                        --                                       .readdatavalid
			i_hio_ch1_lavmm_read                                 => i_hio_ch1_lavmm_read,                                                               --                                       .read
			i_hio_ch1_lavmm_write                                => i_hio_ch1_lavmm_write,                                                              --                                       .write
			o_hio_ch1_lavmm_rdata                                => o_hio_ch1_lavmm_rdata,                                                              --                                       .readdata
			i_hio_ch1_lavmm_wdata                                => i_hio_ch1_lavmm_wdata,                                                              --                                       .writedata
			o_hio_ch1_lavmm_waitreq                              => o_hio_ch1_lavmm_waitreq,                                                            --                                       .waitrequest
			i_hio_ch1_pld_rx_clk_in_row_clk                      => i_hio_ch1_pld_rx_clk_in_row_clk,                                                    --        i_hio_ch1_pld_rx_clk_in_row_clk.clk
			i_hio_ch1_pld_tx_clk_in_row_clk                      => i_hio_ch1_pld_tx_clk_in_row_clk,                                                    --        i_hio_ch1_pld_tx_clk_in_row_clk.clk
			i_hio_ch1_det_lat_rx_dl_clk                          => i_hio_ch1_det_lat_rx_dl_clk,                                                        --            i_hio_ch1_det_lat_rx_dl_clk.clk
			i_hio_ch1_det_lat_rx_mux_select                      => i_hio_ch1_det_lat_rx_mux_select,                                                    --        i_hio_ch1_det_lat_rx_mux_select.clk
			i_hio_ch1_det_lat_rx_sclk_flop                       => i_hio_ch1_det_lat_rx_sclk_flop,                                                     --         i_hio_ch1_det_lat_rx_sclk_flop.clk
			i_hio_ch1_det_lat_rx_sclk_gen_clk                    => i_hio_ch1_det_lat_rx_sclk_gen_clk,                                                  --      i_hio_ch1_det_lat_rx_sclk_gen_clk.clk
			i_hio_ch1_det_lat_rx_trig_flop                       => i_hio_ch1_det_lat_rx_trig_flop,                                                     --         i_hio_ch1_det_lat_rx_trig_flop.clk
			i_hio_ch1_det_lat_sampling_clk                       => i_hio_ch1_det_lat_sampling_clk,                                                     --         i_hio_ch1_det_lat_sampling_clk.clk
			i_hio_ch1_det_lat_tx_dl_clk                          => i_hio_ch1_det_lat_tx_dl_clk,                                                        --            i_hio_ch1_det_lat_tx_dl_clk.clk
			i_hio_ch1_det_lat_tx_mux_select                      => i_hio_ch1_det_lat_tx_mux_select,                                                    --        i_hio_ch1_det_lat_tx_mux_select.clk
			i_hio_ch1_det_lat_tx_sclk_flop                       => i_hio_ch1_det_lat_tx_sclk_flop,                                                     --         i_hio_ch1_det_lat_tx_sclk_flop.clk
			i_hio_ch1_det_lat_tx_sclk_gen_clk                    => i_hio_ch1_det_lat_tx_sclk_gen_clk,                                                  --      i_hio_ch1_det_lat_tx_sclk_gen_clk.clk
			i_hio_ch1_det_lat_tx_trig_flop                       => i_hio_ch1_det_lat_tx_trig_flop,                                                     --         i_hio_ch1_det_lat_tx_trig_flop.clk
			o_hio_ch1_user_rx_clk1_clk                           => o_hio_ch1_user_rx_clk1_clk,                                                         --             o_hio_ch1_user_rx_clk1_clk.clk
			o_hio_ch1_user_rx_clk2_clk                           => o_hio_ch1_user_rx_clk2_clk,                                                         --             o_hio_ch1_user_rx_clk2_clk.clk
			o_hio_ch1_user_tx_clk1_clk                           => o_hio_ch1_user_tx_clk1_clk,                                                         --             o_hio_ch1_user_tx_clk1_clk.clk
			o_hio_ch1_user_tx_clk2_clk                           => o_hio_ch1_user_tx_clk2_clk,                                                         --             o_hio_ch1_user_tx_clk2_clk.clk
			o_hio_ch1_ux_chnl_refclk_mux                         => o_hio_ch1_ux_chnl_refclk_mux,                                                       --           o_hio_ch1_ux_chnl_refclk_mux.clk
			o_hio_ch1_det_lat_rx_async_dl_sync                   => o_hio_ch1_det_lat_rx_async_dl_sync,                                                 --     o_hio_ch1_det_lat_rx_async_dl_sync.clk
			o_hio_ch1_det_lat_rx_async_pulse                     => o_hio_ch1_det_lat_rx_async_pulse,                                                   --       o_hio_ch1_det_lat_rx_async_pulse.clk
			o_hio_ch1_det_lat_rx_async_sample_sync               => o_hio_ch1_det_lat_rx_async_sample_sync,                                             -- o_hio_ch1_det_lat_rx_async_sample_sync.clk
			o_hio_ch1_det_lat_rx_sclk_sample_sync                => o_hio_ch1_det_lat_rx_sclk_sample_sync,                                              --  o_hio_ch1_det_lat_rx_sclk_sample_sync.clk
			o_hio_ch1_det_lat_rx_trig_sample_sync                => o_hio_ch1_det_lat_rx_trig_sample_sync,                                              --  o_hio_ch1_det_lat_rx_trig_sample_sync.clk
			o_hio_ch1_det_lat_tx_async_dl_sync                   => o_hio_ch1_det_lat_tx_async_dl_sync,                                                 --     o_hio_ch1_det_lat_tx_async_dl_sync.clk
			o_hio_ch1_det_lat_tx_async_pulse                     => o_hio_ch1_det_lat_tx_async_pulse,                                                   --       o_hio_ch1_det_lat_tx_async_pulse.clk
			o_hio_ch1_det_lat_tx_async_sample_sync               => o_hio_ch1_det_lat_tx_async_sample_sync,                                             -- o_hio_ch1_det_lat_tx_async_sample_sync.clk
			o_hio_ch1_det_lat_tx_sclk_sample_sync                => o_hio_ch1_det_lat_tx_sclk_sample_sync,                                              --  o_hio_ch1_det_lat_tx_sclk_sample_sync.clk
			o_hio_ch1_det_lat_tx_trig_sample_sync                => o_hio_ch1_det_lat_tx_trig_sample_sync,                                              --  o_hio_ch1_det_lat_tx_trig_sample_sync.clk
			o_hio_ch1_xcvrif_rx_latency_pulse                    => o_hio_ch1_xcvrif_rx_latency_pulse,                                                  --      o_hio_ch1_xcvrif_rx_latency_pulse.clk
			o_hio_ch1_xcvrif_tx_latency_pulse                    => o_hio_ch1_xcvrif_tx_latency_pulse,                                                  --      o_hio_ch1_xcvrif_tx_latency_pulse.clk
			i_hio_ch2_lavmm_clk                                  => i_hio_ch2_lavmm_clk,                                                                --                    i_hio_ch2_lavmm_clk.clk
			i_hio_ch2_lavmm_rstn                                 => i_hio_ch2_lavmm_rstn,                                                               --                   i_hio_ch2_lavmm_rstn.reset
			i_hio_ch2_lavmm_addr                                 => i_hio_ch2_lavmm_addr,                                                               --                          hio_ch2_lavmm.address
			i_hio_ch2_lavmm_be                                   => i_hio_ch2_lavmm_be,                                                                 --                                       .byteenable
			o_hio_ch2_lavmm_rdata_valid                          => o_hio_ch2_lavmm_rdata_valid,                                                        --                                       .readdatavalid
			i_hio_ch2_lavmm_read                                 => i_hio_ch2_lavmm_read,                                                               --                                       .read
			i_hio_ch2_lavmm_write                                => i_hio_ch2_lavmm_write,                                                              --                                       .write
			o_hio_ch2_lavmm_rdata                                => o_hio_ch2_lavmm_rdata,                                                              --                                       .readdata
			i_hio_ch2_lavmm_wdata                                => i_hio_ch2_lavmm_wdata,                                                              --                                       .writedata
			o_hio_ch2_lavmm_waitreq                              => o_hio_ch2_lavmm_waitreq,                                                            --                                       .waitrequest
			i_hio_ch2_pld_rx_clk_in_row_clk                      => i_hio_ch2_pld_rx_clk_in_row_clk,                                                    --        i_hio_ch2_pld_rx_clk_in_row_clk.clk
			i_hio_ch2_pld_tx_clk_in_row_clk                      => i_hio_ch2_pld_tx_clk_in_row_clk,                                                    --        i_hio_ch2_pld_tx_clk_in_row_clk.clk
			i_hio_ch2_det_lat_rx_dl_clk                          => i_hio_ch2_det_lat_rx_dl_clk,                                                        --            i_hio_ch2_det_lat_rx_dl_clk.clk
			i_hio_ch2_det_lat_rx_mux_select                      => i_hio_ch2_det_lat_rx_mux_select,                                                    --        i_hio_ch2_det_lat_rx_mux_select.clk
			i_hio_ch2_det_lat_rx_sclk_flop                       => i_hio_ch2_det_lat_rx_sclk_flop,                                                     --         i_hio_ch2_det_lat_rx_sclk_flop.clk
			i_hio_ch2_det_lat_rx_sclk_gen_clk                    => i_hio_ch2_det_lat_rx_sclk_gen_clk,                                                  --      i_hio_ch2_det_lat_rx_sclk_gen_clk.clk
			i_hio_ch2_det_lat_rx_trig_flop                       => i_hio_ch2_det_lat_rx_trig_flop,                                                     --         i_hio_ch2_det_lat_rx_trig_flop.clk
			i_hio_ch2_det_lat_sampling_clk                       => i_hio_ch2_det_lat_sampling_clk,                                                     --         i_hio_ch2_det_lat_sampling_clk.clk
			i_hio_ch2_det_lat_tx_dl_clk                          => i_hio_ch2_det_lat_tx_dl_clk,                                                        --            i_hio_ch2_det_lat_tx_dl_clk.clk
			i_hio_ch2_det_lat_tx_mux_select                      => i_hio_ch2_det_lat_tx_mux_select,                                                    --        i_hio_ch2_det_lat_tx_mux_select.clk
			i_hio_ch2_det_lat_tx_sclk_flop                       => i_hio_ch2_det_lat_tx_sclk_flop,                                                     --         i_hio_ch2_det_lat_tx_sclk_flop.clk
			i_hio_ch2_det_lat_tx_sclk_gen_clk                    => i_hio_ch2_det_lat_tx_sclk_gen_clk,                                                  --      i_hio_ch2_det_lat_tx_sclk_gen_clk.clk
			i_hio_ch2_det_lat_tx_trig_flop                       => i_hio_ch2_det_lat_tx_trig_flop,                                                     --         i_hio_ch2_det_lat_tx_trig_flop.clk
			o_hio_ch2_user_rx_clk1_clk                           => o_hio_ch2_user_rx_clk1_clk,                                                         --             o_hio_ch2_user_rx_clk1_clk.clk
			o_hio_ch2_user_rx_clk2_clk                           => o_hio_ch2_user_rx_clk2_clk,                                                         --             o_hio_ch2_user_rx_clk2_clk.clk
			o_hio_ch2_user_tx_clk1_clk                           => o_hio_ch2_user_tx_clk1_clk,                                                         --             o_hio_ch2_user_tx_clk1_clk.clk
			o_hio_ch2_user_tx_clk2_clk                           => o_hio_ch2_user_tx_clk2_clk,                                                         --             o_hio_ch2_user_tx_clk2_clk.clk
			o_hio_ch2_ux_chnl_refclk_mux                         => o_hio_ch2_ux_chnl_refclk_mux,                                                       --           o_hio_ch2_ux_chnl_refclk_mux.clk
			o_hio_ch2_det_lat_rx_async_dl_sync                   => o_hio_ch2_det_lat_rx_async_dl_sync,                                                 --     o_hio_ch2_det_lat_rx_async_dl_sync.clk
			o_hio_ch2_det_lat_rx_async_pulse                     => o_hio_ch2_det_lat_rx_async_pulse,                                                   --       o_hio_ch2_det_lat_rx_async_pulse.clk
			o_hio_ch2_det_lat_rx_async_sample_sync               => o_hio_ch2_det_lat_rx_async_sample_sync,                                             -- o_hio_ch2_det_lat_rx_async_sample_sync.clk
			o_hio_ch2_det_lat_rx_sclk_sample_sync                => o_hio_ch2_det_lat_rx_sclk_sample_sync,                                              --  o_hio_ch2_det_lat_rx_sclk_sample_sync.clk
			o_hio_ch2_det_lat_rx_trig_sample_sync                => o_hio_ch2_det_lat_rx_trig_sample_sync,                                              --  o_hio_ch2_det_lat_rx_trig_sample_sync.clk
			o_hio_ch2_det_lat_tx_async_dl_sync                   => o_hio_ch2_det_lat_tx_async_dl_sync,                                                 --     o_hio_ch2_det_lat_tx_async_dl_sync.clk
			o_hio_ch2_det_lat_tx_async_pulse                     => o_hio_ch2_det_lat_tx_async_pulse,                                                   --       o_hio_ch2_det_lat_tx_async_pulse.clk
			o_hio_ch2_det_lat_tx_async_sample_sync               => o_hio_ch2_det_lat_tx_async_sample_sync,                                             -- o_hio_ch2_det_lat_tx_async_sample_sync.clk
			o_hio_ch2_det_lat_tx_sclk_sample_sync                => o_hio_ch2_det_lat_tx_sclk_sample_sync,                                              --  o_hio_ch2_det_lat_tx_sclk_sample_sync.clk
			o_hio_ch2_det_lat_tx_trig_sample_sync                => o_hio_ch2_det_lat_tx_trig_sample_sync,                                              --  o_hio_ch2_det_lat_tx_trig_sample_sync.clk
			o_hio_ch2_xcvrif_rx_latency_pulse                    => o_hio_ch2_xcvrif_rx_latency_pulse,                                                  --      o_hio_ch2_xcvrif_rx_latency_pulse.clk
			o_hio_ch2_xcvrif_tx_latency_pulse                    => o_hio_ch2_xcvrif_tx_latency_pulse,                                                  --      o_hio_ch2_xcvrif_tx_latency_pulse.clk
			i_hio_ch3_lavmm_clk                                  => i_hio_ch3_lavmm_clk,                                                                --                    i_hio_ch3_lavmm_clk.clk
			i_hio_ch3_lavmm_rstn                                 => i_hio_ch3_lavmm_rstn,                                                               --                   i_hio_ch3_lavmm_rstn.reset
			i_hio_ch3_lavmm_addr                                 => i_hio_ch3_lavmm_addr,                                                               --                          hio_ch3_lavmm.address
			i_hio_ch3_lavmm_be                                   => i_hio_ch3_lavmm_be,                                                                 --                                       .byteenable
			o_hio_ch3_lavmm_rdata_valid                          => o_hio_ch3_lavmm_rdata_valid,                                                        --                                       .readdatavalid
			i_hio_ch3_lavmm_read                                 => i_hio_ch3_lavmm_read,                                                               --                                       .read
			i_hio_ch3_lavmm_write                                => i_hio_ch3_lavmm_write,                                                              --                                       .write
			o_hio_ch3_lavmm_rdata                                => o_hio_ch3_lavmm_rdata,                                                              --                                       .readdata
			i_hio_ch3_lavmm_wdata                                => i_hio_ch3_lavmm_wdata,                                                              --                                       .writedata
			o_hio_ch3_lavmm_waitreq                              => o_hio_ch3_lavmm_waitreq,                                                            --                                       .waitrequest
			i_hio_ch3_pld_rx_clk_in_row_clk                      => i_hio_ch3_pld_rx_clk_in_row_clk,                                                    --        i_hio_ch3_pld_rx_clk_in_row_clk.clk
			i_hio_ch3_pld_tx_clk_in_row_clk                      => i_hio_ch3_pld_tx_clk_in_row_clk,                                                    --        i_hio_ch3_pld_tx_clk_in_row_clk.clk
			i_hio_ch3_det_lat_rx_dl_clk                          => i_hio_ch3_det_lat_rx_dl_clk,                                                        --            i_hio_ch3_det_lat_rx_dl_clk.clk
			i_hio_ch3_det_lat_rx_mux_select                      => i_hio_ch3_det_lat_rx_mux_select,                                                    --        i_hio_ch3_det_lat_rx_mux_select.clk
			i_hio_ch3_det_lat_rx_sclk_flop                       => i_hio_ch3_det_lat_rx_sclk_flop,                                                     --         i_hio_ch3_det_lat_rx_sclk_flop.clk
			i_hio_ch3_det_lat_rx_sclk_gen_clk                    => i_hio_ch3_det_lat_rx_sclk_gen_clk,                                                  --      i_hio_ch3_det_lat_rx_sclk_gen_clk.clk
			i_hio_ch3_det_lat_rx_trig_flop                       => i_hio_ch3_det_lat_rx_trig_flop,                                                     --         i_hio_ch3_det_lat_rx_trig_flop.clk
			i_hio_ch3_det_lat_sampling_clk                       => i_hio_ch3_det_lat_sampling_clk,                                                     --         i_hio_ch3_det_lat_sampling_clk.clk
			i_hio_ch3_det_lat_tx_dl_clk                          => i_hio_ch3_det_lat_tx_dl_clk,                                                        --            i_hio_ch3_det_lat_tx_dl_clk.clk
			i_hio_ch3_det_lat_tx_mux_select                      => i_hio_ch3_det_lat_tx_mux_select,                                                    --        i_hio_ch3_det_lat_tx_mux_select.clk
			i_hio_ch3_det_lat_tx_sclk_flop                       => i_hio_ch3_det_lat_tx_sclk_flop,                                                     --         i_hio_ch3_det_lat_tx_sclk_flop.clk
			i_hio_ch3_det_lat_tx_sclk_gen_clk                    => i_hio_ch3_det_lat_tx_sclk_gen_clk,                                                  --      i_hio_ch3_det_lat_tx_sclk_gen_clk.clk
			i_hio_ch3_det_lat_tx_trig_flop                       => i_hio_ch3_det_lat_tx_trig_flop,                                                     --         i_hio_ch3_det_lat_tx_trig_flop.clk
			o_hio_ch3_user_rx_clk1_clk                           => o_hio_ch3_user_rx_clk1_clk,                                                         --             o_hio_ch3_user_rx_clk1_clk.clk
			o_hio_ch3_user_rx_clk2_clk                           => o_hio_ch3_user_rx_clk2_clk,                                                         --             o_hio_ch3_user_rx_clk2_clk.clk
			o_hio_ch3_user_tx_clk1_clk                           => o_hio_ch3_user_tx_clk1_clk,                                                         --             o_hio_ch3_user_tx_clk1_clk.clk
			o_hio_ch3_user_tx_clk2_clk                           => o_hio_ch3_user_tx_clk2_clk,                                                         --             o_hio_ch3_user_tx_clk2_clk.clk
			o_hio_ch3_ux_chnl_refclk_mux                         => o_hio_ch3_ux_chnl_refclk_mux,                                                       --           o_hio_ch3_ux_chnl_refclk_mux.clk
			o_hio_ch3_det_lat_rx_async_dl_sync                   => o_hio_ch3_det_lat_rx_async_dl_sync,                                                 --     o_hio_ch3_det_lat_rx_async_dl_sync.clk
			o_hio_ch3_det_lat_rx_async_pulse                     => o_hio_ch3_det_lat_rx_async_pulse,                                                   --       o_hio_ch3_det_lat_rx_async_pulse.clk
			o_hio_ch3_det_lat_rx_async_sample_sync               => o_hio_ch3_det_lat_rx_async_sample_sync,                                             -- o_hio_ch3_det_lat_rx_async_sample_sync.clk
			o_hio_ch3_det_lat_rx_sclk_sample_sync                => o_hio_ch3_det_lat_rx_sclk_sample_sync,                                              --  o_hio_ch3_det_lat_rx_sclk_sample_sync.clk
			o_hio_ch3_det_lat_rx_trig_sample_sync                => o_hio_ch3_det_lat_rx_trig_sample_sync,                                              --  o_hio_ch3_det_lat_rx_trig_sample_sync.clk
			o_hio_ch3_det_lat_tx_async_dl_sync                   => o_hio_ch3_det_lat_tx_async_dl_sync,                                                 --     o_hio_ch3_det_lat_tx_async_dl_sync.clk
			o_hio_ch3_det_lat_tx_async_pulse                     => o_hio_ch3_det_lat_tx_async_pulse,                                                   --       o_hio_ch3_det_lat_tx_async_pulse.clk
			o_hio_ch3_det_lat_tx_async_sample_sync               => o_hio_ch3_det_lat_tx_async_sample_sync,                                             -- o_hio_ch3_det_lat_tx_async_sample_sync.clk
			o_hio_ch3_det_lat_tx_sclk_sample_sync                => o_hio_ch3_det_lat_tx_sclk_sample_sync,                                              --  o_hio_ch3_det_lat_tx_sclk_sample_sync.clk
			o_hio_ch3_det_lat_tx_trig_sample_sync                => o_hio_ch3_det_lat_tx_trig_sample_sync,                                              --  o_hio_ch3_det_lat_tx_trig_sample_sync.clk
			o_hio_ch3_xcvrif_rx_latency_pulse                    => o_hio_ch3_xcvrif_rx_latency_pulse,                                                  --      o_hio_ch3_xcvrif_rx_latency_pulse.clk
			o_hio_ch3_xcvrif_tx_latency_pulse                    => o_hio_ch3_xcvrif_tx_latency_pulse,                                                  --      o_hio_ch3_xcvrif_tx_latency_pulse.clk
			i_hio_ch4_lavmm_clk                                  => i_hio_ch4_lavmm_clk,                                                                --                    i_hio_ch4_lavmm_clk.clk
			i_hio_ch4_lavmm_rstn                                 => i_hio_ch4_lavmm_rstn,                                                               --                   i_hio_ch4_lavmm_rstn.reset
			i_hio_ch4_lavmm_addr                                 => i_hio_ch4_lavmm_addr,                                                               --                          hio_ch4_lavmm.address
			i_hio_ch4_lavmm_be                                   => i_hio_ch4_lavmm_be,                                                                 --                                       .byteenable
			o_hio_ch4_lavmm_rdata_valid                          => o_hio_ch4_lavmm_rdata_valid,                                                        --                                       .readdatavalid
			i_hio_ch4_lavmm_read                                 => i_hio_ch4_lavmm_read,                                                               --                                       .read
			i_hio_ch4_lavmm_write                                => i_hio_ch4_lavmm_write,                                                              --                                       .write
			o_hio_ch4_lavmm_rdata                                => o_hio_ch4_lavmm_rdata,                                                              --                                       .readdata
			i_hio_ch4_lavmm_wdata                                => i_hio_ch4_lavmm_wdata,                                                              --                                       .writedata
			o_hio_ch4_lavmm_waitreq                              => o_hio_ch4_lavmm_waitreq,                                                            --                                       .waitrequest
			i_hio_ch4_pld_rx_clk_in_row_clk                      => i_hio_ch4_pld_rx_clk_in_row_clk,                                                    --        i_hio_ch4_pld_rx_clk_in_row_clk.clk
			i_hio_ch4_pld_tx_clk_in_row_clk                      => i_hio_ch4_pld_tx_clk_in_row_clk,                                                    --        i_hio_ch4_pld_tx_clk_in_row_clk.clk
			i_hio_ch4_det_lat_rx_dl_clk                          => i_hio_ch4_det_lat_rx_dl_clk,                                                        --            i_hio_ch4_det_lat_rx_dl_clk.clk
			i_hio_ch4_det_lat_rx_mux_select                      => i_hio_ch4_det_lat_rx_mux_select,                                                    --        i_hio_ch4_det_lat_rx_mux_select.clk
			i_hio_ch4_det_lat_rx_sclk_flop                       => i_hio_ch4_det_lat_rx_sclk_flop,                                                     --         i_hio_ch4_det_lat_rx_sclk_flop.clk
			i_hio_ch4_det_lat_rx_sclk_gen_clk                    => i_hio_ch4_det_lat_rx_sclk_gen_clk,                                                  --      i_hio_ch4_det_lat_rx_sclk_gen_clk.clk
			i_hio_ch4_det_lat_rx_trig_flop                       => i_hio_ch4_det_lat_rx_trig_flop,                                                     --         i_hio_ch4_det_lat_rx_trig_flop.clk
			i_hio_ch4_det_lat_sampling_clk                       => i_hio_ch4_det_lat_sampling_clk,                                                     --         i_hio_ch4_det_lat_sampling_clk.clk
			i_hio_ch4_det_lat_tx_dl_clk                          => i_hio_ch4_det_lat_tx_dl_clk,                                                        --            i_hio_ch4_det_lat_tx_dl_clk.clk
			i_hio_ch4_det_lat_tx_mux_select                      => i_hio_ch4_det_lat_tx_mux_select,                                                    --        i_hio_ch4_det_lat_tx_mux_select.clk
			i_hio_ch4_det_lat_tx_sclk_flop                       => i_hio_ch4_det_lat_tx_sclk_flop,                                                     --         i_hio_ch4_det_lat_tx_sclk_flop.clk
			i_hio_ch4_det_lat_tx_sclk_gen_clk                    => i_hio_ch4_det_lat_tx_sclk_gen_clk,                                                  --      i_hio_ch4_det_lat_tx_sclk_gen_clk.clk
			i_hio_ch4_det_lat_tx_trig_flop                       => i_hio_ch4_det_lat_tx_trig_flop,                                                     --         i_hio_ch4_det_lat_tx_trig_flop.clk
			o_hio_ch4_user_rx_clk1_clk                           => o_hio_ch4_user_rx_clk1_clk,                                                         --             o_hio_ch4_user_rx_clk1_clk.clk
			o_hio_ch4_user_rx_clk2_clk                           => o_hio_ch4_user_rx_clk2_clk,                                                         --             o_hio_ch4_user_rx_clk2_clk.clk
			o_hio_ch4_user_tx_clk1_clk                           => o_hio_ch4_user_tx_clk1_clk,                                                         --             o_hio_ch4_user_tx_clk1_clk.clk
			o_hio_ch4_user_tx_clk2_clk                           => o_hio_ch4_user_tx_clk2_clk,                                                         --             o_hio_ch4_user_tx_clk2_clk.clk
			o_hio_ch4_ux_chnl_refclk_mux                         => o_hio_ch4_ux_chnl_refclk_mux,                                                       --           o_hio_ch4_ux_chnl_refclk_mux.clk
			o_hio_ch4_det_lat_rx_async_dl_sync                   => o_hio_ch4_det_lat_rx_async_dl_sync,                                                 --     o_hio_ch4_det_lat_rx_async_dl_sync.clk
			o_hio_ch4_det_lat_rx_async_pulse                     => o_hio_ch4_det_lat_rx_async_pulse,                                                   --       o_hio_ch4_det_lat_rx_async_pulse.clk
			o_hio_ch4_det_lat_rx_async_sample_sync               => o_hio_ch4_det_lat_rx_async_sample_sync,                                             -- o_hio_ch4_det_lat_rx_async_sample_sync.clk
			o_hio_ch4_det_lat_rx_sclk_sample_sync                => o_hio_ch4_det_lat_rx_sclk_sample_sync,                                              --  o_hio_ch4_det_lat_rx_sclk_sample_sync.clk
			o_hio_ch4_det_lat_rx_trig_sample_sync                => o_hio_ch4_det_lat_rx_trig_sample_sync,                                              --  o_hio_ch4_det_lat_rx_trig_sample_sync.clk
			o_hio_ch4_det_lat_tx_async_dl_sync                   => o_hio_ch4_det_lat_tx_async_dl_sync,                                                 --     o_hio_ch4_det_lat_tx_async_dl_sync.clk
			o_hio_ch4_det_lat_tx_async_pulse                     => o_hio_ch4_det_lat_tx_async_pulse,                                                   --       o_hio_ch4_det_lat_tx_async_pulse.clk
			o_hio_ch4_det_lat_tx_async_sample_sync               => o_hio_ch4_det_lat_tx_async_sample_sync,                                             -- o_hio_ch4_det_lat_tx_async_sample_sync.clk
			o_hio_ch4_det_lat_tx_sclk_sample_sync                => o_hio_ch4_det_lat_tx_sclk_sample_sync,                                              --  o_hio_ch4_det_lat_tx_sclk_sample_sync.clk
			o_hio_ch4_det_lat_tx_trig_sample_sync                => o_hio_ch4_det_lat_tx_trig_sample_sync,                                              --  o_hio_ch4_det_lat_tx_trig_sample_sync.clk
			o_hio_ch4_xcvrif_rx_latency_pulse                    => o_hio_ch4_xcvrif_rx_latency_pulse,                                                  --      o_hio_ch4_xcvrif_rx_latency_pulse.clk
			o_hio_ch4_xcvrif_tx_latency_pulse                    => o_hio_ch4_xcvrif_tx_latency_pulse,                                                  --      o_hio_ch4_xcvrif_tx_latency_pulse.clk
			i_ch5_tx_data                                        => "00000000000000000000000000000000000000000000000000000000000000000000000000000000", --                            (terminated)
			i_ch6_tx_data                                        => "00000000000000000000000000000000000000000000000000000000000000000000000000000000", --                            (terminated)
			i_ch7_tx_data                                        => "00000000000000000000000000000000000000000000000000000000000000000000000000000000", --                            (terminated)
			i_ch8_tx_data                                        => "00000000000000000000000000000000000000000000000000000000000000000000000000000000", --                            (terminated)
			o_ch5_rx_data                                        => open,                                                                               --                            (terminated)
			o_ch6_rx_data                                        => open,                                                                               --                            (terminated)
			o_ch7_rx_data                                        => open,                                                                               --                            (terminated)
			o_ch8_rx_data                                        => open,                                                                               --                            (terminated)
			i_rxpipe0_pipemode_dirfeedback                       => "000000",                                                                           --                            (terminated)
			i_rxpipe0_pipemode_linkevaluationfeedbackfiguremerit => "00000000",                                                                         --                            (terminated)
			i_rxpipe0_pipemode_localfs                           => "000000",                                                                           --                            (terminated)
			i_rxpipe0_pipemode_locallf                           => "000000",                                                                           --                            (terminated)
			i_rxpipe0_pipemode_localtxcoefficientsvalid          => '0',                                                                                --                            (terminated)
			i_rxpipe0_pipemode_localtxpresetcoefficients         => "000000000000000000",                                                               --                            (terminated)
			i_rxpipe0_pipemode_p2m_bus                           => "00000000",                                                                         --                            (terminated)
			i_rxpipe0_pipemode_pclkchangeok                      => '0',                                                                                --                            (terminated)
			i_rxpipe0_pipemode_phystatus                         => '0',                                                                                --                            (terminated)
			i_rxpipe0_pipemode_rxdata                            => "0000000000000000000000000000000000000000",                                         --                            (terminated)
			i_rxpipe0_pipemode_rxdatak                           => "0000",                                                                             --                            (terminated)
			i_rxpipe0_pipemode_rxdatavalid                       => '0',                                                                                --                            (terminated)
			i_rxpipe0_pipemode_rxelecidlea                       => '0',                                                                                --                            (terminated)
			i_rxpipe0_pipemode_rxstandbystatus                   => '0',                                                                                --                            (terminated)
			i_rxpipe0_pipemode_rxstartblock                      => '0',                                                                                --                            (terminated)
			i_rxpipe0_pipemode_rxstatus                          => "000",                                                                              --                            (terminated)
			i_rxpipe0_pipemode_rxsyncheader                      => "0000",                                                                             --                            (terminated)
			i_rxpipe0_pipemode_rxvalid                           => '0',                                                                                --                            (terminated)
			i_rxpipe1_pipemode_dirfeedback                       => "000000",                                                                           --                            (terminated)
			i_rxpipe1_pipemode_linkevaluationfeedbackfiguremerit => "00000000",                                                                         --                            (terminated)
			i_rxpipe1_pipemode_localfs                           => "000000",                                                                           --                            (terminated)
			i_rxpipe1_pipemode_locallf                           => "000000",                                                                           --                            (terminated)
			i_rxpipe1_pipemode_localtxcoefficientsvalid          => '0',                                                                                --                            (terminated)
			i_rxpipe1_pipemode_localtxpresetcoefficients         => "000000000000000000",                                                               --                            (terminated)
			i_rxpipe1_pipemode_p2m_bus                           => "00000000",                                                                         --                            (terminated)
			i_rxpipe1_pipemode_pclkchangeok                      => '0',                                                                                --                            (terminated)
			i_rxpipe1_pipemode_phystatus                         => '0',                                                                                --                            (terminated)
			i_rxpipe1_pipemode_rxdata                            => "0000000000000000000000000000000000000000",                                         --                            (terminated)
			i_rxpipe1_pipemode_rxdatak                           => "0000",                                                                             --                            (terminated)
			i_rxpipe1_pipemode_rxdatavalid                       => '0',                                                                                --                            (terminated)
			i_rxpipe1_pipemode_rxelecidlea                       => '0',                                                                                --                            (terminated)
			i_rxpipe1_pipemode_rxstandbystatus                   => '0',                                                                                --                            (terminated)
			i_rxpipe1_pipemode_rxstartblock                      => '0',                                                                                --                            (terminated)
			i_rxpipe1_pipemode_rxstatus                          => "000",                                                                              --                            (terminated)
			i_rxpipe1_pipemode_rxsyncheader                      => "0000",                                                                             --                            (terminated)
			i_rxpipe1_pipemode_rxvalid                           => '0',                                                                                --                            (terminated)
			i_rxpipe2_pipemode_dirfeedback                       => "000000",                                                                           --                            (terminated)
			i_rxpipe2_pipemode_linkevaluationfeedbackfiguremerit => "00000000",                                                                         --                            (terminated)
			i_rxpipe2_pipemode_localfs                           => "000000",                                                                           --                            (terminated)
			i_rxpipe2_pipemode_locallf                           => "000000",                                                                           --                            (terminated)
			i_rxpipe2_pipemode_localtxcoefficientsvalid          => '0',                                                                                --                            (terminated)
			i_rxpipe2_pipemode_localtxpresetcoefficients         => "000000000000000000",                                                               --                            (terminated)
			i_rxpipe2_pipemode_p2m_bus                           => "00000000",                                                                         --                            (terminated)
			i_rxpipe2_pipemode_pclkchangeok                      => '0',                                                                                --                            (terminated)
			i_rxpipe2_pipemode_phystatus                         => '0',                                                                                --                            (terminated)
			i_rxpipe2_pipemode_rxdata                            => "0000000000000000000000000000000000000000",                                         --                            (terminated)
			i_rxpipe2_pipemode_rxdatak                           => "0000",                                                                             --                            (terminated)
			i_rxpipe2_pipemode_rxdatavalid                       => '0',                                                                                --                            (terminated)
			i_rxpipe2_pipemode_rxelecidlea                       => '0',                                                                                --                            (terminated)
			i_rxpipe2_pipemode_rxstandbystatus                   => '0',                                                                                --                            (terminated)
			i_rxpipe2_pipemode_rxstartblock                      => '0',                                                                                --                            (terminated)
			i_rxpipe2_pipemode_rxstatus                          => "000",                                                                              --                            (terminated)
			i_rxpipe2_pipemode_rxsyncheader                      => "0000",                                                                             --                            (terminated)
			i_rxpipe2_pipemode_rxvalid                           => '0',                                                                                --                            (terminated)
			i_rxpipe3_pipemode_dirfeedback                       => "000000",                                                                           --                            (terminated)
			i_rxpipe3_pipemode_linkevaluationfeedbackfiguremerit => "00000000",                                                                         --                            (terminated)
			i_rxpipe3_pipemode_localfs                           => "000000",                                                                           --                            (terminated)
			i_rxpipe3_pipemode_locallf                           => "000000",                                                                           --                            (terminated)
			i_rxpipe3_pipemode_localtxcoefficientsvalid          => '0',                                                                                --                            (terminated)
			i_rxpipe3_pipemode_localtxpresetcoefficients         => "000000000000000000",                                                               --                            (terminated)
			i_rxpipe3_pipemode_p2m_bus                           => "00000000",                                                                         --                            (terminated)
			i_rxpipe3_pipemode_pclkchangeok                      => '0',                                                                                --                            (terminated)
			i_rxpipe3_pipemode_phystatus                         => '0',                                                                                --                            (terminated)
			i_rxpipe3_pipemode_rxdata                            => "0000000000000000000000000000000000000000",                                         --                            (terminated)
			i_rxpipe3_pipemode_rxdatak                           => "0000",                                                                             --                            (terminated)
			i_rxpipe3_pipemode_rxdatavalid                       => '0',                                                                                --                            (terminated)
			i_rxpipe3_pipemode_rxelecidlea                       => '0',                                                                                --                            (terminated)
			i_rxpipe3_pipemode_rxstandbystatus                   => '0',                                                                                --                            (terminated)
			i_rxpipe3_pipemode_rxstartblock                      => '0',                                                                                --                            (terminated)
			i_rxpipe3_pipemode_rxstatus                          => "000",                                                                              --                            (terminated)
			i_rxpipe3_pipemode_rxsyncheader                      => "0000",                                                                             --                            (terminated)
			i_rxpipe3_pipemode_rxvalid                           => '0',                                                                                --                            (terminated)
			i_rxpipe4_pipemode_dirfeedback                       => "000000",                                                                           --                            (terminated)
			i_rxpipe4_pipemode_linkevaluationfeedbackfiguremerit => "00000000",                                                                         --                            (terminated)
			i_rxpipe4_pipemode_localfs                           => "000000",                                                                           --                            (terminated)
			i_rxpipe4_pipemode_locallf                           => "000000",                                                                           --                            (terminated)
			i_rxpipe4_pipemode_localtxcoefficientsvalid          => '0',                                                                                --                            (terminated)
			i_rxpipe4_pipemode_localtxpresetcoefficients         => "000000000000000000",                                                               --                            (terminated)
			i_rxpipe4_pipemode_p2m_bus                           => "00000000",                                                                         --                            (terminated)
			i_rxpipe4_pipemode_pclkchangeok                      => '0',                                                                                --                            (terminated)
			i_rxpipe4_pipemode_phystatus                         => '0',                                                                                --                            (terminated)
			i_rxpipe4_pipemode_rxdata                            => "0000000000000000000000000000000000000000",                                         --                            (terminated)
			i_rxpipe4_pipemode_rxdatak                           => "0000",                                                                             --                            (terminated)
			i_rxpipe4_pipemode_rxdatavalid                       => '0',                                                                                --                            (terminated)
			i_rxpipe4_pipemode_rxelecidlea                       => '0',                                                                                --                            (terminated)
			i_rxpipe4_pipemode_rxstandbystatus                   => '0',                                                                                --                            (terminated)
			i_rxpipe4_pipemode_rxstartblock                      => '0',                                                                                --                            (terminated)
			i_rxpipe4_pipemode_rxstatus                          => "000",                                                                              --                            (terminated)
			i_rxpipe4_pipemode_rxsyncheader                      => "0000",                                                                             --                            (terminated)
			i_rxpipe4_pipemode_rxvalid                           => '0',                                                                                --                            (terminated)
			i_rxpipe5_pipemode_dirfeedback                       => "000000",                                                                           --                            (terminated)
			i_rxpipe5_pipemode_linkevaluationfeedbackfiguremerit => "00000000",                                                                         --                            (terminated)
			i_rxpipe5_pipemode_localfs                           => "000000",                                                                           --                            (terminated)
			i_rxpipe5_pipemode_locallf                           => "000000",                                                                           --                            (terminated)
			i_rxpipe5_pipemode_localtxcoefficientsvalid          => '0',                                                                                --                            (terminated)
			i_rxpipe5_pipemode_localtxpresetcoefficients         => "000000000000000000",                                                               --                            (terminated)
			i_rxpipe5_pipemode_p2m_bus                           => "00000000",                                                                         --                            (terminated)
			i_rxpipe5_pipemode_pclkchangeok                      => '0',                                                                                --                            (terminated)
			i_rxpipe5_pipemode_phystatus                         => '0',                                                                                --                            (terminated)
			i_rxpipe5_pipemode_rxdata                            => "0000000000000000000000000000000000000000",                                         --                            (terminated)
			i_rxpipe5_pipemode_rxdatak                           => "0000",                                                                             --                            (terminated)
			i_rxpipe5_pipemode_rxdatavalid                       => '0',                                                                                --                            (terminated)
			i_rxpipe5_pipemode_rxelecidlea                       => '0',                                                                                --                            (terminated)
			i_rxpipe5_pipemode_rxstandbystatus                   => '0',                                                                                --                            (terminated)
			i_rxpipe5_pipemode_rxstartblock                      => '0',                                                                                --                            (terminated)
			i_rxpipe5_pipemode_rxstatus                          => "000",                                                                              --                            (terminated)
			i_rxpipe5_pipemode_rxsyncheader                      => "0000",                                                                             --                            (terminated)
			i_rxpipe5_pipemode_rxvalid                           => '0',                                                                                --                            (terminated)
			i_rxpipe6_pipemode_dirfeedback                       => "000000",                                                                           --                            (terminated)
			i_rxpipe6_pipemode_linkevaluationfeedbackfiguremerit => "00000000",                                                                         --                            (terminated)
			i_rxpipe6_pipemode_localfs                           => "000000",                                                                           --                            (terminated)
			i_rxpipe6_pipemode_locallf                           => "000000",                                                                           --                            (terminated)
			i_rxpipe6_pipemode_localtxcoefficientsvalid          => '0',                                                                                --                            (terminated)
			i_rxpipe6_pipemode_localtxpresetcoefficients         => "000000000000000000",                                                               --                            (terminated)
			i_rxpipe6_pipemode_p2m_bus                           => "00000000",                                                                         --                            (terminated)
			i_rxpipe6_pipemode_pclkchangeok                      => '0',                                                                                --                            (terminated)
			i_rxpipe6_pipemode_phystatus                         => '0',                                                                                --                            (terminated)
			i_rxpipe6_pipemode_rxdata                            => "0000000000000000000000000000000000000000",                                         --                            (terminated)
			i_rxpipe6_pipemode_rxdatak                           => "0000",                                                                             --                            (terminated)
			i_rxpipe6_pipemode_rxdatavalid                       => '0',                                                                                --                            (terminated)
			i_rxpipe6_pipemode_rxelecidlea                       => '0',                                                                                --                            (terminated)
			i_rxpipe6_pipemode_rxstandbystatus                   => '0',                                                                                --                            (terminated)
			i_rxpipe6_pipemode_rxstartblock                      => '0',                                                                                --                            (terminated)
			i_rxpipe6_pipemode_rxstatus                          => "000",                                                                              --                            (terminated)
			i_rxpipe6_pipemode_rxsyncheader                      => "0000",                                                                             --                            (terminated)
			i_rxpipe6_pipemode_rxvalid                           => '0',                                                                                --                            (terminated)
			i_rxpipe7_pipemode_dirfeedback                       => "000000",                                                                           --                            (terminated)
			i_rxpipe7_pipemode_linkevaluationfeedbackfiguremerit => "00000000",                                                                         --                            (terminated)
			i_rxpipe7_pipemode_localfs                           => "000000",                                                                           --                            (terminated)
			i_rxpipe7_pipemode_locallf                           => "000000",                                                                           --                            (terminated)
			i_rxpipe7_pipemode_localtxcoefficientsvalid          => '0',                                                                                --                            (terminated)
			i_rxpipe7_pipemode_localtxpresetcoefficients         => "000000000000000000",                                                               --                            (terminated)
			i_rxpipe7_pipemode_p2m_bus                           => "00000000",                                                                         --                            (terminated)
			i_rxpipe7_pipemode_pclkchangeok                      => '0',                                                                                --                            (terminated)
			i_rxpipe7_pipemode_phystatus                         => '0',                                                                                --                            (terminated)
			i_rxpipe7_pipemode_rxdata                            => "0000000000000000000000000000000000000000",                                         --                            (terminated)
			i_rxpipe7_pipemode_rxdatak                           => "0000",                                                                             --                            (terminated)
			i_rxpipe7_pipemode_rxdatavalid                       => '0',                                                                                --                            (terminated)
			i_rxpipe7_pipemode_rxelecidlea                       => '0',                                                                                --                            (terminated)
			i_rxpipe7_pipemode_rxstandbystatus                   => '0',                                                                                --                            (terminated)
			i_rxpipe7_pipemode_rxstartblock                      => '0',                                                                                --                            (terminated)
			i_rxpipe7_pipemode_rxstatus                          => "000",                                                                              --                            (terminated)
			i_rxpipe7_pipemode_rxsyncheader                      => "0000",                                                                             --                            (terminated)
			i_rxpipe7_pipemode_rxvalid                           => '0',                                                                                --                            (terminated)
			o_txpipe0_pipemode_asyncpowerchangeack               => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_blockaligncontrol                 => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_cfg_hw_auto_sp_dis                => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_dirchange                         => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_ebuf_mode                         => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_encodedecodebypass                => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_fs                                => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_getlocalpresetcoefficients        => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_invalidrequest                    => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_lf                                => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_localpresetindex                  => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_lowpin_nt                         => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_m2p_bus                           => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_pclk_rate                         => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_pclkchangeack                     => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_phy_mode_nt                       => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_powerdown                         => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_rate                              => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_rxelecidle_disable_a              => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_rxeqclr                           => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_rxeqeval                          => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_rxeqinprogress                    => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_rxeqtraining                      => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_rxpolarity                        => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_rxpresethint                      => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_rxstandby                         => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_rxtermination                     => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_srisenable                        => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_txcmnmode_disable_a               => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_txcompliance                      => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_txdata                            => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_txdatak                           => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_txdatavalid                       => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_txdeemph                          => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_txdtctrx_lb                       => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_txelecidle                        => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_txmargin                          => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_txoneszeros                       => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_txstartblock                      => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_txswing                           => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_txsyncheader                      => open,                                                                               --                            (terminated)
			o_txpipe0_pipemode_width                             => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_asyncpowerchangeack               => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_blockaligncontrol                 => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_cfg_hw_auto_sp_dis                => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_dirchange                         => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_ebuf_mode                         => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_encodedecodebypass                => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_fs                                => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_getlocalpresetcoefficients        => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_invalidrequest                    => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_lf                                => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_localpresetindex                  => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_lowpin_nt                         => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_m2p_bus                           => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_pclk_rate                         => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_pclkchangeack                     => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_phy_mode_nt                       => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_powerdown                         => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_rate                              => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_rxelecidle_disable_a              => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_rxeqclr                           => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_rxeqeval                          => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_rxeqinprogress                    => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_rxeqtraining                      => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_rxpolarity                        => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_rxpresethint                      => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_rxstandby                         => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_rxtermination                     => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_srisenable                        => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_txcmnmode_disable_a               => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_txcompliance                      => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_txdata                            => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_txdatak                           => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_txdatavalid                       => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_txdeemph                          => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_txdtctrx_lb                       => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_txelecidle                        => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_txmargin                          => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_txoneszeros                       => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_txstartblock                      => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_txswing                           => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_txsyncheader                      => open,                                                                               --                            (terminated)
			o_txpipe1_pipemode_width                             => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_asyncpowerchangeack               => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_blockaligncontrol                 => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_cfg_hw_auto_sp_dis                => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_dirchange                         => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_ebuf_mode                         => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_encodedecodebypass                => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_fs                                => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_getlocalpresetcoefficients        => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_invalidrequest                    => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_lf                                => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_localpresetindex                  => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_lowpin_nt                         => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_m2p_bus                           => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_pclk_rate                         => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_pclkchangeack                     => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_phy_mode_nt                       => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_powerdown                         => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_rate                              => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_rxelecidle_disable_a              => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_rxeqclr                           => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_rxeqeval                          => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_rxeqinprogress                    => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_rxeqtraining                      => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_rxpolarity                        => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_rxpresethint                      => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_rxstandby                         => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_rxtermination                     => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_srisenable                        => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_txcmnmode_disable_a               => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_txcompliance                      => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_txdata                            => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_txdatak                           => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_txdatavalid                       => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_txdeemph                          => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_txdtctrx_lb                       => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_txelecidle                        => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_txmargin                          => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_txoneszeros                       => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_txstartblock                      => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_txswing                           => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_txsyncheader                      => open,                                                                               --                            (terminated)
			o_txpipe2_pipemode_width                             => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_asyncpowerchangeack               => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_blockaligncontrol                 => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_cfg_hw_auto_sp_dis                => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_dirchange                         => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_ebuf_mode                         => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_encodedecodebypass                => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_fs                                => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_getlocalpresetcoefficients        => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_invalidrequest                    => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_lf                                => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_localpresetindex                  => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_lowpin_nt                         => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_m2p_bus                           => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_pclk_rate                         => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_pclkchangeack                     => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_phy_mode_nt                       => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_powerdown                         => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_rate                              => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_rxelecidle_disable_a              => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_rxeqclr                           => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_rxeqeval                          => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_rxeqinprogress                    => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_rxeqtraining                      => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_rxpolarity                        => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_rxpresethint                      => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_rxstandby                         => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_rxtermination                     => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_srisenable                        => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_txcmnmode_disable_a               => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_txcompliance                      => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_txdata                            => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_txdatak                           => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_txdatavalid                       => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_txdeemph                          => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_txdtctrx_lb                       => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_txelecidle                        => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_txmargin                          => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_txoneszeros                       => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_txstartblock                      => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_txswing                           => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_txsyncheader                      => open,                                                                               --                            (terminated)
			o_txpipe3_pipemode_width                             => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_asyncpowerchangeack               => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_blockaligncontrol                 => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_cfg_hw_auto_sp_dis                => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_dirchange                         => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_ebuf_mode                         => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_encodedecodebypass                => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_fs                                => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_getlocalpresetcoefficients        => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_invalidrequest                    => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_lf                                => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_localpresetindex                  => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_lowpin_nt                         => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_m2p_bus                           => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_pclk_rate                         => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_pclkchangeack                     => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_phy_mode_nt                       => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_powerdown                         => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_rate                              => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_rxelecidle_disable_a              => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_rxeqclr                           => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_rxeqeval                          => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_rxeqinprogress                    => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_rxeqtraining                      => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_rxpolarity                        => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_rxpresethint                      => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_rxstandby                         => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_rxtermination                     => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_srisenable                        => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_txcmnmode_disable_a               => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_txcompliance                      => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_txdata                            => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_txdatak                           => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_txdatavalid                       => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_txdeemph                          => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_txdtctrx_lb                       => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_txelecidle                        => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_txmargin                          => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_txoneszeros                       => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_txstartblock                      => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_txswing                           => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_txsyncheader                      => open,                                                                               --                            (terminated)
			o_txpipe4_pipemode_width                             => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_asyncpowerchangeack               => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_blockaligncontrol                 => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_cfg_hw_auto_sp_dis                => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_dirchange                         => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_ebuf_mode                         => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_encodedecodebypass                => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_fs                                => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_getlocalpresetcoefficients        => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_invalidrequest                    => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_lf                                => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_localpresetindex                  => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_lowpin_nt                         => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_m2p_bus                           => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_pclk_rate                         => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_pclkchangeack                     => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_phy_mode_nt                       => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_powerdown                         => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_rate                              => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_rxelecidle_disable_a              => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_rxeqclr                           => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_rxeqeval                          => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_rxeqinprogress                    => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_rxeqtraining                      => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_rxpolarity                        => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_rxpresethint                      => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_rxstandby                         => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_rxtermination                     => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_srisenable                        => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_txcmnmode_disable_a               => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_txcompliance                      => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_txdata                            => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_txdatak                           => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_txdatavalid                       => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_txdeemph                          => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_txdtctrx_lb                       => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_txelecidle                        => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_txmargin                          => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_txoneszeros                       => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_txstartblock                      => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_txswing                           => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_txsyncheader                      => open,                                                                               --                            (terminated)
			o_txpipe5_pipemode_width                             => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_asyncpowerchangeack               => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_blockaligncontrol                 => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_cfg_hw_auto_sp_dis                => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_dirchange                         => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_ebuf_mode                         => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_encodedecodebypass                => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_fs                                => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_getlocalpresetcoefficients        => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_invalidrequest                    => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_lf                                => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_localpresetindex                  => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_lowpin_nt                         => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_m2p_bus                           => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_pclk_rate                         => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_pclkchangeack                     => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_phy_mode_nt                       => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_powerdown                         => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_rate                              => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_rxelecidle_disable_a              => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_rxeqclr                           => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_rxeqeval                          => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_rxeqinprogress                    => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_rxeqtraining                      => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_rxpolarity                        => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_rxpresethint                      => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_rxstandby                         => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_rxtermination                     => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_srisenable                        => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_txcmnmode_disable_a               => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_txcompliance                      => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_txdata                            => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_txdatak                           => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_txdatavalid                       => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_txdeemph                          => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_txdtctrx_lb                       => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_txelecidle                        => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_txmargin                          => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_txoneszeros                       => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_txstartblock                      => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_txswing                           => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_txsyncheader                      => open,                                                                               --                            (terminated)
			o_txpipe6_pipemode_width                             => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_asyncpowerchangeack               => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_blockaligncontrol                 => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_cfg_hw_auto_sp_dis                => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_dirchange                         => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_ebuf_mode                         => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_encodedecodebypass                => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_fs                                => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_getlocalpresetcoefficients        => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_invalidrequest                    => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_lf                                => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_localpresetindex                  => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_lowpin_nt                         => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_m2p_bus                           => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_pclk_rate                         => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_pclkchangeack                     => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_phy_mode_nt                       => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_powerdown                         => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_rate                              => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_rxelecidle_disable_a              => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_rxeqclr                           => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_rxeqeval                          => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_rxeqinprogress                    => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_rxeqtraining                      => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_rxpolarity                        => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_rxpresethint                      => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_rxstandby                         => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_rxtermination                     => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_srisenable                        => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_txcmnmode_disable_a               => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_txcompliance                      => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_txdata                            => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_txdatak                           => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_txdatavalid                       => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_txdeemph                          => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_txdtctrx_lb                       => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_txelecidle                        => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_txmargin                          => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_txoneszeros                       => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_txstartblock                      => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_txswing                           => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_txsyncheader                      => open,                                                                               --                            (terminated)
			o_txpipe7_pipemode_width                             => open,                                                                               --                            (terminated)
			o_pcs0_pipemode_pipe_rst_n                           => open,                                                                               --                            (terminated)
			o_pcs1_pipemode_pipe_rst_n                           => open,                                                                               --                            (terminated)
			o_pcs2_pipemode_pipe_rst_n                           => open,                                                                               --                            (terminated)
			o_pcs3_pipemode_pipe_rst_n                           => open,                                                                               --                            (terminated)
			o_pcs4_pipemode_pipe_rst_n                           => open,                                                                               --                            (terminated)
			o_pcs5_pipemode_pipe_rst_n                           => open,                                                                               --                            (terminated)
			o_pcs6_pipemode_pipe_rst_n                           => open,                                                                               --                            (terminated)
			o_pcs7_pipemode_pipe_rst_n                           => open,                                                                               --                            (terminated)
			i_pcs0_pipemode_pclk                                 => '0'                                                                                 --                            (terminated)
		);

end architecture rtl; -- of gts_axi_streaming_intel_pcie_gts_pcie_hal_top_800_a4pwunq
