-- gts_axi_streaming_one_lane_pcie_hal_phy_hal_2100_dek3pgy.vhd

-- Generated using ACDS version 25.1 129

library IEEE;
library phy_hal_2100;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity gts_axi_streaming_one_lane_pcie_hal_phy_hal_2100_dek3pgy is
	generic (
		device_die_type                                    : string                        := "MAIN_SM7";
		device_die_revisions                               : string                        := "MAIN_SM7_REVA";
		ch_xcvrif_l_loopback_mode_atom                     : string                        := "LOOPBACK_MODE_DISABLE";
		ch_flux_l_stmux_rx_demux_sel                       : string                        := "SEL_PCIE_PCS";
		ch_flux_l_stmux_rx_rxword_clk_demux_sel            : string                        := "SEL_PCIE_RXWORD_CLK";
		ch_flux_l_stmux_tx_txword_clk_demux_sel            : string                        := "SEL_PCIE_TXWORD_CLK";
		ch_flux_l_stmux_tx_mux_sel                         : string                        := "SEL_PCIE_PCS";
		ch_flux_l_stmux_tx_txword_clk_mux_sel              : string                        := "SEL_UX_OCK_PMA_CLK";
		ch_xcvrif_rx_ch_clk_static_mux                     : string                        := "SEL_UNUSED";
		ch_xcvrif_tx_ch_clk_static_mux                     : string                        := "SEL_UNUSED";
		ch_flux_l_tx_bond_size_atom                        : string                        := "TX_BOND_SIZE_X4";
		ch_l_xcvr_tx_bond_size_atom                        : string                        := "TX_BOND_SIZE_X4";
		ch_xcvrif_l_tx_bond_size_atom                      : string                        := "TX_BOND_SIZE_UNUSED";
		ch_xcvrif_l_rx_bond_size_atom                      : string                        := "RX_BOND_SIZE_UNUSED";
		ch_clkrx_refclk_cssm_fw_control_atom               : string                        := "CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE";
		ch_clkrx_refclk_sector_specifies_refclk_ready_atom : string                        := "CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
		ch_local_refclk_cssm_fw_control_atom               : string                        := "LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE";
		ch_local_refclk_sector_specifies_refclk_ready_atom : string                        := "LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
		ch_l_xcvr_cdr_f_out_hz_atom                        : std_logic_vector(35 downto 0) := "000011101110011010110010100000000000";
		ch_l_xcvr_cdr_f_vco_hz_atom                        : std_logic_vector(35 downto 0) := "001001010100000010111110010000000000";
		ch_l_xcvr_cdr_f_pfd_hz_atom                        : std_logic_vector(35 downto 0) := "000000000101111101011110000100000000";
		ch_l_xcvr_cdr_f_ref_hz_atom                        : std_logic_vector(35 downto 0) := "000000000101111101011110000100000000";
		ch_l_cdr_l_counter_atom                            : std_logic_vector(5 downto 0)  := "000010";
		ch_l_cdr_m_counter_atom                            : std_logic_vector(8 downto 0)  := "000110010";
		ch_l_cdr_n_counter_atom                            : std_logic_vector(5 downto 0)  := "000001";
		ch_l_tx_pll_postdiv_sel_sm4_atom                   : string                        := "TX_PLL_POSTDIV_SEL_SYNTH2";
		ch_l_tx_pll_postdiv_sel_sm7_atom                   : string                        := "TX_PLL_POSTDIV_SEL_SYNTH2";
		ch_l_tx_pll_bw_sel_atom                            : string                        := "TX_PLL_BW_SEL_LOW";
		ch_l_tx_pll_f_out_hz_atom                          : std_logic_vector(35 downto 0) := "000011101110011010110010100000000000";
		ch_l_tx_pll_f_vco_hz_atom                          : std_logic_vector(35 downto 0) := "001001010100000010111110010000000000";
		ch_l_tx_pll_f_pfd_hz_atom                          : std_logic_vector(35 downto 0) := "000000000101111101011110000100000000";
		ch_l_tx_pll_f_ref_hz_atom                          : std_logic_vector(35 downto 0) := "000000000101111101011110000100000000";
		ch_l_tx_pll_k_counter_atom                         : std_logic_vector(21 downto 0) := "0000000000000000000000";
		ch_l_tx_pll_l_counter_atom                         : std_logic_vector(5 downto 0)  := "000010";
		ch_l_tx_pll_m_counter_atom                         : std_logic_vector(8 downto 0)  := "001100100";
		ch_l_tx_pll_n_counter_atom                         : std_logic_vector(5 downto 0)  := "000001";
		ch_l_tx_pll_fb_counter_atom                        : std_logic_vector(1 downto 0)  := "01";
		ch_l_tx_postdiv_cdr_refclk_hz_atom                 : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
		ch_l_tx_postdiv_cdr_refclk_divider_atom            : std_logic_vector(7 downto 0)  := "00001100";
		ch_l_tx_synthdiv_out_divider_atom                  : std_logic_vector(7 downto 0)  := "00001100";
		ch_l_tx_synthdiv_out_hz_atom                       : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
		ch_l_xcvr_tx_preloaded_hardware_configs_atom       : string                        := "TX_PRELOADED_HARDWARE_CONFIGS_PCIE";
		ch_l_xcvr_tx_protocol_hint_atom                    : string                        := "TX_PROTOCOL_HINT_DISABLED";
		ch_l_xcvr_tx_datarate_bps_atom                     : std_logic_vector(36 downto 0) := "0000111011100110101100101000000000000";
		ch_l_xcvr_tx_prbs_gen_en_atom                      : string                        := "TX_PRBS_GEN_EN_DISABLE";
		ch_l_xcvr_tx_prbs_pattern_atom                     : std_logic_vector(3 downto 0)  := "0000";
		ch_l_xcvr_tx_user_clk_only_mode_atom               : string                        := "TX_USER_CLK_ONLY_MODE_DISABLE";
		ch_l_xcvr_tx_width_atom                            : string                        := "TX_WIDTH_X16";
		ch_l_xcvr_tx_word_clk_hz_atom                      : std_logic_vector(35 downto 0) := "000000011101110011010110010100000000";
		ch_l_xcvr_tx_dl_enable_atom                        : string                        := "TX_DL_ENABLE_DISABLE";
		ch_l_xcvr_rx_preloaded_hardware_configs_atom       : string                        := "RX_PRELOADED_HARDWARE_CONFIGS_PCIE";
		ch_l_xcvr_rx_protocol_hint_atom                    : string                        := "RX_PROTOCOL_HINT_DISABLED";
		ch_l_xcvr_rx_datarate_bps_atom                     : std_logic_vector(36 downto 0) := "0000111011100110101100101000000000000";
		ch_l_xcvr_rx_prbs_monitor_en_atom                  : string                        := "RX_PRBS_MONITOR_EN_DISABLE";
		ch_l_xcvr_rx_prbs_pattern_atom                     : std_logic_vector(3 downto 0)  := "0001";
		ch_l_xcvr_rx_width_atom                            : string                        := "RX_WIDTH_X16";
		ch_l_xcvr_rx_force_cdr_ltr_atom                    : string                        := "TRUE";
		ch_l_xcvr_rx_adaptation_mode_atom                  : string                        := "RX_ADAPTATION_MODE_UX_NATIVE_ADAPTATION";
		ch_l_xcvr_rx_adaptation_mode_hw_atom               : string                        := "RX_ADAPTATION_MODE_UX_NATIVE_ADAPTATION";
		ch_l_xcvr_rx_word_clk_hz_atom                      : std_logic_vector(35 downto 0) := "000000011101110011010110010100000000";
		ch_l_xcvr_rx_dl_enable_atom                        : string                        := "RX_DL_ENABLE_DISABLE";
		ch_l_rx_postdiv_clk_en_atom                        : string                        := "RX_POSTDIV_CLK_EN_ENABLE";
		ch_l_rx_postdiv_clk_divider_atom                   : std_logic_vector(7 downto 0)  := "00001100";
		ch_l_tx_postdiv_clk_divider_atom                   : std_logic_vector(7 downto 0)  := "10001001";
		ch_l_tx_pll_refclk_select_atom                     : string                        := "TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0";
		ch_l_loopback_mode_atom                            : string                        := "LOOPBACK_MODE_DISABLED";
		ch_flux_l_flux_mode_atom                           : string                        := "FLUX_MODE_FLUX_MODE_BYPASS";
		ch_flux_l_flux_mode_hw_atom                        : string                        := "FLUX_MODE_FLUX_MODE_BYPASS";
		ch_flux_l_rx_protocol_hint_atom                    : string                        := "RX_PROTOCOL_HINT_DISABLED";
		ch_flux_l_tx_dl_enable_atom                        : string                        := "TX_DL_ENABLE_DISABLE";
		ch_flux_l_rx_dl_enable_atom                        : string                        := "RX_DL_ENABLE_DISABLE";
		ch_xcvrif_l_tx_dl_enable_atom                      : string                        := "TX_DL_ENABLE_DISABLE";
		ch_xcvrif_l_rx_dl_enable_atom                      : string                        := "RX_DL_ENABLE_DISABLE";
		ch_xcvrif_l_tx_fifo_mode_atom                      : string                        := "TX_FIFO_MODE_DISABLED";
		ch_xcvrif_l_rx_fifo_mode_atom                      : string                        := "RX_FIFO_MODE_DISABLED";
		ch_l_xcvr_tx_en_atom                               : string                        := "TRUE";
		ch_l_xcvr_rx_en_atom                               : string                        := "TRUE";
		ch_l_duplex_mode_atom                              : string                        := "DUPLEX_MODE_DUPLEX";
		ch_xcvrif_l_tx_en_atom                             : string                        := "FALSE";
		ch_xcvrif_l_rx_en_atom                             : string                        := "FALSE";
		ch_xcvrif_l_duplex_mode_atom                       : string                        := "DUPLEX_MODE_DUPLEX";
		ch_flux_l_rx_fec_type_used_atom                    : string                        := "RX_FEC_TYPE_USED_NONE";
		ch_l_sim_mode_atom                                 : string                        := "SIM_MODE_DISABLE";
		ch_flux_l_rx_sim_mode_atom                         : string                        := "RX_SIM_MODE_DISABLE";
		ch_flux_l_tx_sim_mode_atom                         : string                        := "TX_SIM_MODE_DISABLE";
		ch_flux_l_dr_enabled_atom                          : string                        := "DR_ENABLED_DR_DISABLED";
		ch_xcvrif_l_sup_mode_atom                          : string                        := "SUP_MODE_USER_MODE";
		ch_xcvrif_l_sim_mode_atom                          : string                        := "SIM_MODE_ENABLE";
		ch_xcvrif_l_dr_enabled_atom                        : string                        := "DR_ENABLED_DR_DISABLED";
		ch_l_xcvr_tx_spread_spectrum_en_atom               : string                        := "TX_SPREAD_SPECTRUM_EN_ENABLE";
		ch_l_rx_postdiv_clk_hz_atom                        : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
		ch_l_rx_postdiv_clk_fractional_en_atom             : string                        := "RX_POSTDIV_CLK_FRACTIONAL_EN_DISABLE";
		ch_l_cdr_refclk_select_atom                        : string                        := "CDR_REFCLK_SELECT_GLOBAL_REFCLK0";
		ch_l_tx_postdiv_clk_hz_atom                        : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
		ch_l_tx_postdiv_clk_fractional_en_atom             : string                        := "TX_POSTDIV_CLK_FRACTIONAL_EN_DISABLE";
		ch_flux_l_lc_postdiv_sel_atom                      : string                        := "LC_POSTDIV_SEL_SYNTH2";
		ch_flux_l_tx_user1_clk_mux_dynamic_sel_atom        : string                        := "TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK";
		ch_flux_l_tx_user2_clk_mux_dynamic_sel_atom        : string                        := "TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK";
		ch_flux_l_rx_user1_clk_mux_dynamic_sel_atom        : string                        := "RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD";
		ch_flux_l_rx_user2_clk_mux_dynamic_sel_atom        : string                        := "RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD";
		ch_xcvrif_l_tx_gb_width_atom                       : string                        := "TX_GB_WIDTH_DISABLED";
		ch_xcvrif_l_rx_gb_width_atom                       : string                        := "RX_GB_WIDTH_DISABLED";
		ch_xcvrif_l_tx_dynamic_mux_atom                    : string                        := "TX_DYNAMIC_MUX_UNUSED";
		ch_xcvrif_l_tx_word_clk_dynamic_mux_atom           : string                        := "TX_WORD_CLK_DYNAMIC_MUX_X4";
		ch_xcvrif_l_rx_word_clk_dynamic_mux_atom           : string                        := "RX_WORD_CLK_DYNAMIC_MUX_UNUSED";
		ch_xcvrif_l_tx_fifo_rd_en_dynamic_mux_atom         : string                        := "TX_FIFO_RD_EN_DYNAMIC_MUX_X4";
		ch_xcvrif_l_rx_fifo_rd_en_dynamic_mux_atom         : string                        := "RX_FIFO_RD_EN_DYNAMIC_MUX_UNUSED";
		ch_xcvrif_l_tx_rst_dynamic_mux_atom                : string                        := "TX_RST_DYNAMIC_MUX_X4";
		ch_l_clk_debug_select_0_enable_atom                : string                        := "CLK_DEBUG_SELECT_0_ENABLE_DISABLE";
		ch_l_clk_debug_select_0_setting_atom               : string                        := "CLK_DEBUG_SELECT_0_SETTING_DISABLED";
		ch_l_clk_debug_select_1_enable_atom                : string                        := "CLK_DEBUG_SELECT_1_ENABLE_DISABLE";
		ch_l_clk_debug_select_1_setting_atom               : string                        := "CLK_DEBUG_SELECT_1_SETTING_DISABLED";
		ch_l_xcvr_tx_eq_main_tap_atom                      : std_logic_vector(5 downto 0)  := "000000";
		ch_l_xcvr_tx_eq_post_tap_1_atom                    : std_logic_vector(4 downto 0)  := "00000";
		ch_l_xcvr_tx_eq_pre_tap_1_atom                     : std_logic_vector(4 downto 0)  := "00000";
		ch_l_xcvr_tx_eq_pre_tap_2_atom                     : std_logic_vector(2 downto 0)  := "000";
		ch_l_tx_pll_feed_forward_gain_atom                 : std_logic_vector(7 downto 0)  := "01000011";
		ch_l_xcvr_rx_termination_mode_atom                 : string                        := "RX_TERMINATION_MODE_GROUNDED";
		ch_l_xcvr_rx_onchip_termination_setting_atom       : string                        := "RX_ONCHIP_TERMINATION_SETTING_R_1";
		ch_l_xcvr_rx_eq_vga_gain_atom                      : std_logic_vector(6 downto 0)  := "0100000";
		ch_l_xcvr_x_eq_hf_boost_atom                       : std_logic_vector(5 downto 0)  := "100000";
		ch_l_xcvr_rx_eq_dfe_tap_1_atom                     : std_logic_vector(5 downto 0)  := "000000";
		ch_l_xcvr_rx_external_couple_type_atom             : string                        := "RX_EXTERNAL_COUPLE_TYPE_AC";
		ch_l_xcvr_tx_bonding_category_atom                 : string                        := "TX_BONDING_CATEGORY_BONDING_FOLLOWER";
		ch_l_xcvr_tx_master_pll_mode_atom                  : string                        := "TX_MASTER_PLL_MODE_DISABLED";
		ch_l_xcvr_rx_cdrdivout_en_atom                     : string                        := "RX_CDRDIVOUT_EN_DISABLE";
		ch_xcvrif_l_tx_bonding_mode_atom                   : string                        := "TX_BONDING_MODE_UNUSED";
		ch_xcvrif_l_rx_bonding_mode_atom                   : string                        := "RX_BONDING_MODE_UNUSED";
		ch_flux_l_sequencer_reg_en_atom                    : string                        := "SEQUENCER_REG_EN_DISABLE";
		ch_l_speed_grade_atom                              : string                        := "SPEED_GRADE_DASH_1";
		ch_usb_mode_atom                                   : string                        := "USB_MODE_DISABLED";
		ch_pcie_mode_atom                                  : string                        := "PCIE_MODE_GEN3";
		ch_l_ick_tx_word_clk_hz_atom                       : std_logic_vector(35 downto 0) := "100101011100000111110010100001110010";
		ch_l_pcs_ref_clk_hz_atom                           : std_logic_vector(35 downto 0) := "101001111010110110010111101111110101";
		ch_l_lane_common_ref_clk_hz_atom                   : std_logic_vector(35 downto 0) := "111110010011110101111111101000101001";
		ch_rx_invert_pin_atom                              : string                        := "RX_INVERT_PIN_DISABLE";
		ch_tx_invert_pin_atom                              : string                        := "TX_INVERT_PIN_DISABLE";
		ch_vsr_mode_atom                                   : string                        := "VSR_MODE_DISABLED";
		ch_rx_dl_rx_lat_bit_for_async_atom                 : std_logic_vector(17 downto 0) := "111110100110100101";
		ch_rx_dl_rxbit_cntr_pma_atom                       : string                        := "RX_DL_RXBIT_CNTR_PMA_DISABLE";
		ch_rx_dl_rxbit_rollover_atom                       : std_logic_vector(17 downto 0) := "001001111001000101";
		ch_eth_rx_clk_hz_atom                              : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
		ch_eth_tx_clk_hz_atom                              : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000"
	);
	port (
		oflux_xoa_tx_n_l0_ux              : out std_logic;                                         --              oflux_xoa_tx_n_l0_ux.data,          Stats Snapshot
		oflux_xoa_tx_p_l0_ux              : out std_logic;                                         --              oflux_xoa_tx_p_l0_ux.data,          RX PFC
		iflux_xia_rx_n_l0_ux              : in  std_logic                      := '0';             --              iflux_xia_rx_n_l0_ux.data,          CSR access address
		iflux_xia_rx_p_l0_ux              : in  std_logic                      := '0';             --              iflux_xia_rx_p_l0_ux.data,          RX error bits asserted on the EOP cycle
		i_ss_async_pldif                  : in  std_logic_vector(79 downto 0)  := (others => '0'); --                       asyncdata_0.data,          Stats Snapshot
		o_ss_async_pldif                  : out std_logic_vector(49 downto 0);                     --                       asyncdata_1.data,          RX PFC
		i_ss_async_pldif_pcie_mux         : in  std_logic_vector(79 downto 0)  := (others => '0'); --                       asyncdata_2.data,          CSR access address
		i_lavmm_addr                      : in  std_logic_vector(19 downto 0)  := (others => '0'); --                          reconfig.address,       RX error bits asserted on the EOP cycle
		i_lavmm_be                        : in  std_logic_vector(3 downto 0)   := (others => '0'); --                                  .byteenable,    Stats Snapshot
		i_lavmm_read                      : in  std_logic                      := '0';             --                                  .read,          CSR access address
		i_lavmm_wdata                     : in  std_logic_vector(31 downto 0)  := (others => '0'); --                                  .writedata,     RX error bits asserted on the EOP cycle
		i_lavmm_write                     : in  std_logic                      := '0';             --                                  .write,         Stats Snapshot
		o_lavmm_rdata                     : out std_logic_vector(31 downto 0);                     --                                  .readdata,      RX PFC
		o_lavmm_rdata_valid               : out std_logic;                                         --                                  .readdatavalid, CSR access address
		o_lavmm_waitreq                   : out std_logic;                                         --                                  .waitrequest
		i_lavmm_clk                       : in  std_logic                      := '0';             --                      reconfig_clk.clk,           RX PFC
		i_lavmm_rstn                      : in  std_logic                      := '0';             --                      reconfig_rst.reset,         RX error bits asserted on the EOP cycle
		i_ft_rx_sclk_sync_ch              : in  std_logic                      := '0';             --              i_ft_rx_sclk_sync_ch.clk,           Stats Snapshot
		i_ft_tx_sclk_sync_ch              : in  std_logic                      := '0';             --              i_ft_tx_sclk_sync_ch.clk,           RX PFC
		o_ft_rx_async_pulse_ch            : out std_logic;                                         --            o_ft_rx_async_pulse_ch.clk,           CSR access address
		o_ft_tx_async_pulse_ch            : out std_logic;                                         --            o_ft_tx_async_pulse_ch.clk
		o_rxcdrlock2dataa                 : out std_logic;                                         --                 o_rxcdrlock2dataa.lockdata,      Stats Snapshot
		i_rst_ux_rx_sfrz                  : in  std_logic                      := '0';             --                  i_rst_ux_rx_sfrz.data
		o_rst_flux0_cpi_cmn_busy          : out std_logic;                                         --          o_rst_flux0_cpi_cmn_busy.busy,          CSR access address
		o_rst_oflux_rx_srds_rdy           : out std_logic;                                         --           o_rst_oflux_rx_srds_rdy.ready
		o_rst_ux_all_synthlockstatus      : out std_logic;                                         --      o_rst_ux_all_synthlockstatus.status
		o_rst_ux_rxcdrlockstatus          : out std_logic;                                         --          o_rst_ux_rxcdrlockstatus.rxstatus
		i_ick_sclk_tx                     : in  std_logic                      := '0';             --                     i_ick_sclk_tx.clk
		i_ick_sclk_rx                     : in  std_logic                      := '0';             --                     i_ick_sclk_rx.clk
		i_rst_pld_ux_tx_pma_rst_n         : in  std_logic                      := '0';             --         i_rst_pld_ux_tx_pma_rst_n.reset
		i_rst_pld_ux_rx_pma_rst_n         : in  std_logic                      := '0';             --         i_rst_pld_ux_rx_pma_rst_n.reset
		o_ch_lavmm_xcvrif_rdata           : out std_logic_vector(31 downto 0);                     --                     reconfig_xcvr.readdata
		o_ch_lavmm_xcvrif_rdata_valid     : out std_logic;                                         --                                  .readdatavalid
		o_ch_lavmm_xcvrif_waitreq         : out std_logic;                                         --                                  .waitrequest
		i_ch_lavmm_xcvrif_addr            : in  std_logic_vector(19 downto 0)  := (others => '0'); --                                  .address
		i_ch_lavmm_xcvrif_be              : in  std_logic_vector(3 downto 0)   := (others => '0'); --                                  .byteenable
		i_ch_lavmm_xcvrif_read            : in  std_logic                      := '0';             --                                  .read
		i_ch_lavmm_xcvrif_wdata           : in  std_logic_vector(31 downto 0)  := (others => '0'); --                                  .writedata,     RX error bits asserted on the EOP cycle
		i_ch_lavmm_xcvrif_write           : in  std_logic                      := '0';             --                                  .write,         RX error bits asserted on the EOP cycle
		i_ch_lavmm_xcvrif_clk             : in  std_logic                      := '0';             --                 reconfig_clk_xcvr.clk
		i_ch_lavmm_xcvrif_rstn            : in  std_logic                      := '0';             --                 reconfig_rst_xcvr.reset,         RX error bits asserted on the EOP cycle
		o_rx_latency_pulse                : out std_logic;                                         --                o_rx_latency_pulse.clk,           RX error bits asserted on the EOP cycle
		o_tx_latency_pulse                : out std_logic;                                         --                o_tx_latency_pulse.clk,           RX error bits asserted on the EOP cycle
		i_ch_eth_xcvrif_tx_async          : in  std_logic_vector(6 downto 0)   := (others => '0'); --                       asyncdata_3.data,          RX error bits asserted on the EOP cycle
		i_ch_eth_xcvrif_tx_direct         : in  std_logic                      := '0';             --                       asyncdata_4.data
		o_ch_eth_xcvrif_rx_async          : out std_logic_vector(13 downto 0);                     --                       asyncdata_5.data
		o_ch_eth_xcvrif_rx_direct         : out std_logic;                                         --                       asyncdata_6.data
		i_rstxcvrif_xcvrif_signal_ok      : in  std_logic                      := '0';             --      i_rstxcvrif_xcvrif_signal_ok.data
		i_rstxcvrif_rx_xcvrif_sfrz_n      : in  std_logic                      := '0';             --      i_rstxcvrif_rx_xcvrif_sfrz_n.data
		i_rstxcvrif_xcvrif_rx_rst_n       : in  std_logic                      := '0';             --       i_rstxcvrif_xcvrif_rx_rst_n.data
		i_rstxcvrif_tx_xcvrif_sfrz_n      : in  std_logic                      := '0';             --      i_rstxcvrif_tx_xcvrif_sfrz_n.data
		i_rstxcvrif_xcvrif_tx_rst_n       : in  std_logic                      := '0';             --       i_rstxcvrif_xcvrif_tx_rst_n.data
		o_pma_rx_sf                       : out std_logic;                                         --                       o_pma_rx_sf.data
		i_xcvrif_tx_mux_data              : in  std_logic_vector(42 downto 0)  := (others => '0'); --              i_xcvrif_tx_mux_data.data
		o_rx_data                         : out std_logic_vector(42 downto 0);                     --                         o_rx_data.data
		o_tx_source_sel                   : out std_logic_vector(1 downto 0);                      --                   o_tx_source_sel.data
		o_rx_fifo_en_sel                  : out std_logic_vector(2 downto 0);                      --                  o_rx_fifo_en_sel.data
		o_tx_rst_source_sel               : out std_logic_vector(2 downto 0);                      --               o_tx_rst_source_sel.data
		i_ch_xcvrif_rx_fifo_rd_en         : in  std_logic                      := '0';             --         i_ch_xcvrif_rx_fifo_rd_en.data
		o_ch_xcvrif_rx_fifo_rd_en         : out std_logic;                                         --         o_ch_xcvrif_rx_fifo_rd_en.data
		i_ch_xcvrif_tx_fifo_rd_en         : in  std_logic                      := '0';             --         i_ch_xcvrif_tx_fifo_rd_en.data
		o_ch_xcvrif_tx_fifo_rd_en         : out std_logic;                                         --         o_ch_xcvrif_tx_fifo_rd_en.data
		o_ux_rxuser1_sel                  : out std_logic_vector(1 downto 0);                      --                  o_ux_rxuser1_sel.data
		o_ux_rxuser2_sel                  : out std_logic_vector(1 downto 0);                      --                  o_ux_rxuser2_sel.data
		o_ux_txuser1_sel                  : out std_logic_vector(1 downto 0);                      --                  o_ux_txuser1_sel.data
		o_ux_txuser2_sel                  : out std_logic_vector(1 downto 0);                      --                  o_ux_txuser2_sel.data
		o_pcs_rxpostdiv                   : out std_logic;                                         --                   o_pcs_rxpostdiv.data
		o_pcs_rxword                      : out std_logic;                                         --                      o_pcs_rxword.data
		o_ux_txlc_clk                     : out std_logic;                                         --                     o_ux_txlc_clk.clk
		o_tx_xcvr_wordclk_sel             : out std_logic_vector(2 downto 0);                      --             o_tx_xcvr_wordclk_sel.data
		o_rx_xcvr_wordclk_sel             : out std_logic_vector(1 downto 0);                      --             o_rx_xcvr_wordclk_sel.data
		i_eth_rx_ch_clk                   : in  std_logic                      := '0';             --                   i_eth_rx_ch_clk.clk
		uxwrap_bus_in                     : in  std_logic_vector(767 downto 0) := (others => '0'); --                     uxwrap_bus_in.data
		uxwrap_bus_out                    : out std_logic_vector(703 downto 0);                    --                    uxwrap_bus_out.data
		o_lavmm_addr                      : out std_logic_vector(19 downto 0);                     --               reconfig_phy_shared.address
		o_lavmm_be                        : out std_logic_vector(3 downto 0);                      --                                  .byteenable
		o_lavmm_read                      : out std_logic;                                         --                                  .read
		o_lavmm_wdata                     : out std_logic_vector(31 downto 0);                     --                                  .writedata
		o_lavmm_write                     : out std_logic;                                         --                                  .write
		i_lavmm_rdata                     : in  std_logic_vector(31 downto 0)  := (others => '0'); --                                  .readdata
		i_lavmm_rdata_valid               : in  std_logic                      := '0';             --                                  .readdatavalid
		i_lavmm_waitreq                   : in  std_logic                      := '0';             --                                  .waitrequest
		o_lavmm_clk                       : out std_logic;                                         --           reconfig_clk_phy_shared.clk
		o_lavmm_rstn                      : out std_logic;                                         --           reconfig_rst_phy_shared.reset
		o_sclk_return_sel_rx              : out std_logic;                                         --              o_sclk_return_sel_rx.data
		o_sclk_return_sel_tx              : out std_logic;                                         --              o_sclk_return_sel_tx.data
		o_ick_sclk_rx                     : out std_logic;                                         --                     o_ick_sclk_rx.clk
		i_sync_common_control             : in  std_logic_vector(4 downto 0)   := (others => '0'); --             i_sync_common_control.data
		o_ft_rx_sclk_sync_ch              : out std_logic;                                         --              o_ft_rx_sclk_sync_ch.data
		o_ft_tx_sclk_sync_ch              : out std_logic;                                         --              o_ft_tx_sclk_sync_ch.data
		o_rst_ux_rx_pma_rst_n             : out std_logic;                                         --             o_rst_ux_rx_pma_rst_n.reset
		o_rst_ux_tx_pma_rst_n             : out std_logic;                                         --             o_rst_ux_tx_pma_rst_n.reset
		o_ick_pcs_txword                  : out std_logic;                                         --                  o_ick_pcs_txword.data
		o_tx_dl_ch_bit                    : out std_logic;                                         --                    o_tx_dl_ch_bit.data
		i_dat_pcs_measlatbit              : in  std_logic                      := '0';             --              i_dat_pcs_measlatbit.data
		i_ft_rx_async_pulse_ch            : in  std_logic                      := '0';             --            i_ft_rx_async_pulse_ch.data
		i_ft_tx_async_pulse_ch            : in  std_logic                      := '0';             --            i_ft_tx_async_pulse_ch.data
		i_rx_dl_ch_bit                    : in  std_logic                      := '0';             --                    i_rx_dl_ch_bit.data
		i_ux_rxuser1_sel                  : in  std_logic_vector(1 downto 0)   := (others => '0'); --                  i_ux_rxuser1_sel.data
		i_ux_rxuser2_sel                  : in  std_logic_vector(1 downto 0)   := (others => '0'); --                  i_ux_rxuser2_sel.data
		i_ux_txuser1_sel                  : in  std_logic_vector(1 downto 0)   := (others => '0'); --                  i_ux_txuser1_sel.data
		i_ux_txuser2_sel                  : in  std_logic_vector(1 downto 0)   := (others => '0'); --                  i_ux_txuser2_sel.data
		o_octl_pcs_txstatus_a             : out std_logic;                                         --             o_octl_pcs_txstatus_a.data
		i_ictl_pcs_txenable_a             : in  std_logic                      := '0';             --             i_ictl_pcs_txenable_a.data
		i_sync_cfg_data                   : in  std_logic_vector(124 downto 0) := (others => '0'); --                   i_sync_cfg_data.data
		i_sync_interface_control          : in  std_logic_vector(249 downto 0) := (others => '0'); --          i_sync_interface_control.data
		o_tx_data                         : out std_logic_vector(79 downto 0);                     --                         o_tx_data.data
		i_rx_data                         : in  std_logic_vector(79 downto 0)  := (others => '0'); --                         i_rx_data.data
		o_sm_flux_ingress                 : out std_logic_vector(319 downto 0);                    --                 o_sm_flux_ingress.data
		i_sm_flux_egress                  : in  std_logic_vector(256 downto 0) := (others => '0'); --                  i_sm_flux_egress.data
		i_flux_cpi_int                    : in  std_logic                      := '0';             --                    i_flux_cpi_int.data
		i_flux_int                        : in  std_logic                      := '0';             --                        i_flux_int.data
		i_oflux_octl_pcs_txptr_smpl_lane  : in  std_logic                      := '0';             --  i_oflux_octl_pcs_txptr_smpl_lane.data
		o_ick_sclk_tx                     : out std_logic;                                         --                     o_ick_sclk_tx.clk
		i_flux_srds_rdy                   : in  std_logic                      := '0';             --                   i_flux_srds_rdy.data
		i_pcs_rxword                      : in  std_logic                      := '0';             --                      i_pcs_rxword.data
		i_pcs_rxpostdiv                   : in  std_logic                      := '0';             --                   i_pcs_rxpostdiv.data
		i_ock_pcs_txword                  : in  std_logic                      := '0';             --                  i_ock_pcs_txword.data
		o_dat_pcs_measlatrndtripbit       : out std_logic;                                         --       o_dat_pcs_measlatrndtripbit.data
		o_ock_pcs_cdrfbclk                : out std_logic;                                         --                o_ock_pcs_cdrfbclk.data
		o_ock_pcs_ref                     : out std_logic;                                         --                     o_ock_pcs_ref.data
		o_pcie_pcs                        : out std_logic_vector(39 downto 0);                     --                        o_pcie_pcs.data
		i_pcie_pcs                        : in  std_logic_vector(39 downto 0)  := (others => '0'); --                        i_pcie_pcs.data
		i_sel_rxword_clk                  : in  std_logic                      := '0';             --                  i_sel_rxword_clk.clk
		i_xcvr_txword_clk                 : in  std_logic                      := '0';             --                 i_xcvr_txword_clk.clk
		o_pcie_rxword_clk                 : out std_logic;                                         --                 o_pcie_rxword_clk.clk
		o_eth_rxword_clk                  : out std_logic;                                         --                  o_eth_rxword_clk.clk
		o_pcie_txword_clk                 : out std_logic;                                         --                 o_pcie_txword_clk.clk
		o_eth_txword_clk                  : out std_logic;                                         --                  o_eth_txword_clk.clk
		o_ock_pcs_txword                  : out std_logic;                                         --                  o_ock_pcs_txword.clk
		o_eth_rx_ch_clk                   : out std_logic;                                         --                   o_eth_rx_ch_clk.clk
		o_eth_tx_ch_clk                   : out std_logic;                                         --                   o_eth_tx_ch_clk.clk
		ioack_ref_left_p_ux_bidir_in      : in  std_logic_vector(5 downto 0)   := (others => '0'); --      ioack_ref_left_p_ux_bidir_in.data
		ioack_hsref_left_p_ux_bidir_in    : in  std_logic                      := '0';             --    ioack_hsref_left_p_ux_bidir_in.clk
		ioack_cdrdiv_left_ux_bidir_in     : in  std_logic                      := '0';             --     ioack_cdrdiv_left_ux_bidir_in.clk
		ioack_synthdiv1_left_ux_bidir_in  : in  std_logic                      := '0';             --  ioack_synthdiv1_left_ux_bidir_in.clk
		ioack_synthdiv2_left_ux_bidir_in  : in  std_logic                      := '0';             --  ioack_synthdiv2_left_ux_bidir_in.clk
		ioack_cdrdiv_left_ux_bidir_out    : out std_logic;                                         --    ioack_cdrdiv_left_ux_bidir_out.clk
		ioack_synthdiv1_left_ux_bidir_out : out std_logic;                                         -- ioack_synthdiv1_left_ux_bidir_out.clk
		ioack_synthdiv2_left_ux_bidir_out : out std_logic;                                         -- ioack_synthdiv2_left_ux_bidir_out.clk
		o_rxeq_best_eye_vala              : out std_logic_vector(13 downto 0);                     --              o_rxeq_best_eye_vala.data
		o_rxeq_donea                      : out std_logic;                                         --                      o_rxeq_donea.data
		o_rxmargin_nacka                  : out std_logic;                                         --                  o_rxmargin_nacka.data
		o_rxmargin_statusa                : out std_logic;                                         --                o_rxmargin_statusa.data
		o_rxsignaldetect_lfpsa            : out std_logic;                                         --            o_rxsignaldetect_lfpsa.data
		o_rxsignaldetecta                 : out std_logic;                                         --                 o_rxsignaldetecta.data
		o_rxmargin_status_gray            : out std_logic_vector(1 downto 0);                      --            o_rxmargin_status_gray.data
		o_rxstatusa                       : out std_logic;                                         --                       o_rxstatusa.data
		o_synthlcfast_postdiv             : out std_logic;                                         --             o_synthlcfast_postdiv.data
		o_synthlcmed_postdiv              : out std_logic;                                         --              o_synthlcmed_postdiv.data
		o_synthlcslow_postdiv             : out std_logic;                                         --             o_synthlcslow_postdiv.data
		o_txdetectrx_acka                 : out std_logic;                                         --                 o_txdetectrx_acka.data
		o_txdetectrx_statct               : out std_logic;                                         --               o_txdetectrx_statct.data
		o_txstatusa                       : out std_logic;                                         --                       o_txstatusa.data
		i_quartus_flux_s_to_ingress       : in  std_logic                      := '0';             --       i_quartus_flux_s_to_ingress.data
		i_pcs_pipe_rstn                   : in  std_logic                      := '0';             --                   i_pcs_pipe_rstn.data
		i_ux_ock_pma_clk                  : in  std_logic                      := '0';             --                  i_ux_ock_pma_clk.data
		i_lfps_ennt                       : in  std_logic                      := '0';             --                       i_lfps_ennt.data
		i_pcie_l1ctrla                    : in  std_logic_vector(1 downto 0)   := (others => '0'); --                    i_pcie_l1ctrla.data
		i_pma_cmn_ctrl                    : in  std_logic                      := '0';             --                    i_pma_cmn_ctrl.data
		i_pma_ctrl                        : in  std_logic                      := '0';             --                        i_pma_ctrl.data
		i_pcie_pcs_rx_rst                 : in  std_logic                      := '0';             --                 i_pcie_pcs_rx_rst.data
		i_pcie_pcs_tx_rst                 : in  std_logic                      := '0';             --                 i_pcie_pcs_tx_rst.data
		i_rxeiosdetectstata               : in  std_logic                      := '0';             --               i_rxeiosdetectstata.data
		i_rxeq_precal_code_selnt          : in  std_logic_vector(2 downto 0)   := (others => '0'); --          i_rxeq_precal_code_selnt.data
		i_rxeq_starta                     : in  std_logic                      := '0';             --                     i_rxeq_starta.data
		i_rxeq_static_ena                 : in  std_logic                      := '0';             --                 i_rxeq_static_ena.data
		i_rxmargin_direction_nt           : in  std_logic                      := '0';             --           i_rxmargin_direction_nt.data
		i_rxmargin_mode_nt                : in  std_logic                      := '0';             --                i_rxmargin_mode_nt.data
		i_rxmargin_offset_change_a        : in  std_logic                      := '0';             --        i_rxmargin_offset_change_a.data
		i_rxmargin_offset_nt              : in  std_logic_vector(6 downto 0)   := (others => '0'); --              i_rxmargin_offset_nt.data
		i_rxmargin_start_a                : in  std_logic                      := '0';             --                i_rxmargin_start_a.data
		i_rxpstate                        : in  std_logic_vector(2 downto 0)   := (others => '0'); --                        i_rxpstate.data
		i_rxrate                          : in  std_logic_vector(3 downto 0)   := (others => '0'); --                          i_rxrate.data
		i_rxterm_hiz_ena                  : in  std_logic                      := '0';             --                  i_rxterm_hiz_ena.data
		i_rxwidth                         : in  std_logic_vector(2 downto 0)   := (others => '0'); --                         i_rxwidth.data
		i_tstbus_lane                     : in  std_logic                      := '0';             --                     i_tstbus_lane.data
		i_txbeacona                       : in  std_logic                      := '0';             --                       i_txbeacona.data
		i_txclkdivrate                    : in  std_logic_vector(2 downto 0)   := (others => '0'); --                    i_txclkdivrate.data
		i_txdetectrx_reqa                 : in  std_logic                      := '0';             --                 i_txdetectrx_reqa.data
		i_txdrv_levn                      : in  std_logic_vector(5 downto 0)   := (others => '0'); --                      i_txdrv_levn.data
		i_txdrv_levnm1                    : in  std_logic_vector(4 downto 0)   := (others => '0'); --                    i_txdrv_levnm1.data
		i_txdrv_levnm2                    : in  std_logic_vector(2 downto 0)   := (others => '0'); --                    i_txdrv_levnm2.data
		i_txdrv_levnp1                    : in  std_logic_vector(4 downto 0)   := (others => '0'); --                    i_txdrv_levnp1.data
		i_txdrv_slew                      : in  std_logic_vector(3 downto 0)   := (others => '0'); --                      i_txdrv_slew.data
		i_txelecidle                      : in  std_logic_vector(3 downto 0)   := (others => '0'); --                      i_txelecidle.data
		i_txpstate                        : in  std_logic_vector(2 downto 0)   := (others => '0'); --                        i_txpstate.data
		i_txrate                          : in  std_logic_vector(3 downto 0)   := (others => '0'); --                          i_txrate.data
		i_txwidth                         : in  std_logic_vector(2 downto 0)   := (others => '0'); --                         i_txwidth.data
		i_rstxcvrif_xcvrif_tx_rd_rst_n    : in  std_logic                      := '0';             --    i_rstxcvrif_xcvrif_tx_rd_rst_n.data
		i_rstxcvrif_xcvrif_tx_wr_rst_n    : in  std_logic                      := '0';             --    i_rstxcvrif_xcvrif_tx_wr_rst_n.data
		o_tx_rst_rd_sync_rst_n            : out std_logic;                                         --            o_tx_rst_rd_sync_rst_n.data
		o_tx_rst_wr_sync_rst_n            : out std_logic                                          --            o_tx_rst_wr_sync_rst_n.data
	);
end entity gts_axi_streaming_one_lane_pcie_hal_phy_hal_2100_dek3pgy;

architecture rtl of gts_axi_streaming_one_lane_pcie_hal_phy_hal_2100_dek3pgy is
	component gts_axi_streaming_phy_hal_2100_jhh6v6q_cmp is
		generic (
			device_die_type                                    : string                        := "MAIN_SM7";
			device_die_revisions                               : string                        := "MAIN_SM7_REVA";
			ch_xcvrif_l_loopback_mode_atom                     : string                        := "LOOPBACK_MODE_DISABLE";
			ch_flux_l_stmux_rx_demux_sel                       : string                        := "SEL_XCVRIF";
			ch_flux_l_stmux_rx_rxword_clk_demux_sel            : string                        := "SEL_ETH_RXWORD_CLK";
			ch_flux_l_stmux_tx_txword_clk_demux_sel            : string                        := "SEL_ETH_TXWORD_CLK";
			ch_flux_l_stmux_tx_mux_sel                         : string                        := "SEL_XCVRIF";
			ch_flux_l_stmux_tx_txword_clk_mux_sel              : string                        := "SEL_XCVR_TXWORD_CLK";
			ch_xcvrif_rx_ch_clk_static_mux                     : string                        := "SEL_SYS_CLK";
			ch_xcvrif_tx_ch_clk_static_mux                     : string                        := "SEL_SYS_CLK";
			ch_flux_l_tx_bond_size_atom                        : string                        := "TX_BOND_SIZE_UNUSED";
			ch_l_xcvr_tx_bond_size_atom                        : string                        := "TX_BOND_SIZE_UNUSED";
			ch_xcvrif_l_tx_bond_size_atom                      : string                        := "TX_BOND_SIZE_UNUSED";
			ch_xcvrif_l_rx_bond_size_atom                      : string                        := "RX_BOND_SIZE_UNUSED";
			ch_clkrx_refclk_cssm_fw_control_atom               : string                        := "CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE";
			ch_clkrx_refclk_sector_specifies_refclk_ready_atom : string                        := "CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
			ch_local_refclk_cssm_fw_control_atom               : string                        := "LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE";
			ch_local_refclk_sector_specifies_refclk_ready_atom : string                        := "LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE";
			ch_l_xcvr_cdr_f_out_hz_atom                        : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_xcvr_cdr_f_vco_hz_atom                        : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_xcvr_cdr_f_pfd_hz_atom                        : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_xcvr_cdr_f_ref_hz_atom                        : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_cdr_l_counter_atom                            : std_logic_vector(5 downto 0)  := "000000";
			ch_l_cdr_m_counter_atom                            : std_logic_vector(8 downto 0)  := "000000000";
			ch_l_cdr_n_counter_atom                            : std_logic_vector(5 downto 0)  := "000000";
			ch_l_tx_pll_postdiv_sel_sm4_atom                   : string                        := "";
			ch_l_tx_pll_postdiv_sel_sm7_atom                   : string                        := "";
			ch_l_tx_pll_bw_sel_atom                            : string                        := "";
			ch_l_tx_pll_f_out_hz_atom                          : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_tx_pll_f_vco_hz_atom                          : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_tx_pll_f_pfd_hz_atom                          : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_tx_pll_f_ref_hz_atom                          : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_tx_pll_k_counter_atom                         : std_logic_vector(21 downto 0) := "0000000000000000000000";
			ch_l_tx_pll_l_counter_atom                         : std_logic_vector(5 downto 0)  := "000000";
			ch_l_tx_pll_m_counter_atom                         : std_logic_vector(8 downto 0)  := "000000000";
			ch_l_tx_pll_n_counter_atom                         : std_logic_vector(5 downto 0)  := "000000";
			ch_l_tx_pll_fb_counter_atom                        : std_logic_vector(1 downto 0)  := "00";
			ch_l_tx_postdiv_cdr_refclk_hz_atom                 : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_tx_postdiv_cdr_refclk_divider_atom            : std_logic_vector(7 downto 0)  := "00000000";
			ch_l_tx_synthdiv_out_divider_atom                  : std_logic_vector(7 downto 0)  := "00000000";
			ch_l_tx_synthdiv_out_hz_atom                       : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_xcvr_tx_preloaded_hardware_configs_atom       : string                        := "";
			ch_l_xcvr_tx_protocol_hint_atom                    : string                        := "";
			ch_l_xcvr_tx_datarate_bps_atom                     : std_logic_vector(36 downto 0) := "0000000000000000000000000000000000000";
			ch_l_xcvr_tx_prbs_gen_en_atom                      : string                        := "";
			ch_l_xcvr_tx_prbs_pattern_atom                     : std_logic_vector(3 downto 0)  := "0000";
			ch_l_xcvr_tx_user_clk_only_mode_atom               : string                        := "";
			ch_l_xcvr_tx_width_atom                            : string                        := "";
			ch_l_xcvr_tx_word_clk_hz_atom                      : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_xcvr_tx_dl_enable_atom                        : string                        := "";
			ch_l_xcvr_rx_preloaded_hardware_configs_atom       : string                        := "";
			ch_l_xcvr_rx_protocol_hint_atom                    : string                        := "";
			ch_l_xcvr_rx_datarate_bps_atom                     : std_logic_vector(36 downto 0) := "0000000000000000000000000000000000000";
			ch_l_xcvr_rx_prbs_monitor_en_atom                  : string                        := "";
			ch_l_xcvr_rx_prbs_pattern_atom                     : std_logic_vector(3 downto 0)  := "0000";
			ch_l_xcvr_rx_width_atom                            : string                        := "";
			ch_l_xcvr_rx_force_cdr_ltr_atom                    : string                        := "";
			ch_l_xcvr_rx_adaptation_mode_atom                  : string                        := "";
			ch_l_xcvr_rx_adaptation_mode_hw_atom               : string                        := "";
			ch_l_xcvr_rx_word_clk_hz_atom                      : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_xcvr_rx_dl_enable_atom                        : string                        := "";
			ch_l_rx_postdiv_clk_en_atom                        : string                        := "";
			ch_l_rx_postdiv_clk_divider_atom                   : std_logic_vector(7 downto 0)  := "00000000";
			ch_l_tx_postdiv_clk_divider_atom                   : std_logic_vector(7 downto 0)  := "00000000";
			ch_l_tx_pll_refclk_select_atom                     : string                        := "";
			ch_l_loopback_mode_atom                            : string                        := "";
			ch_flux_l_flux_mode_atom                           : string                        := "";
			ch_flux_l_flux_mode_hw_atom                        : string                        := "";
			ch_flux_l_rx_protocol_hint_atom                    : string                        := "";
			ch_flux_l_tx_dl_enable_atom                        : string                        := "";
			ch_flux_l_rx_dl_enable_atom                        : string                        := "";
			ch_xcvrif_l_tx_dl_enable_atom                      : string                        := "";
			ch_xcvrif_l_rx_dl_enable_atom                      : string                        := "";
			ch_xcvrif_l_tx_fifo_mode_atom                      : string                        := "";
			ch_xcvrif_l_rx_fifo_mode_atom                      : string                        := "";
			ch_l_xcvr_tx_en_atom                               : string                        := "";
			ch_l_xcvr_rx_en_atom                               : string                        := "";
			ch_l_duplex_mode_atom                              : string                        := "";
			ch_xcvrif_l_tx_en_atom                             : string                        := "";
			ch_xcvrif_l_rx_en_atom                             : string                        := "";
			ch_xcvrif_l_duplex_mode_atom                       : string                        := "";
			ch_flux_l_rx_fec_type_used_atom                    : string                        := "";
			ch_l_sim_mode_atom                                 : string                        := "";
			ch_flux_l_rx_sim_mode_atom                         : string                        := "";
			ch_flux_l_tx_sim_mode_atom                         : string                        := "";
			ch_flux_l_dr_enabled_atom                          : string                        := "";
			ch_xcvrif_l_sup_mode_atom                          : string                        := "";
			ch_xcvrif_l_sim_mode_atom                          : string                        := "";
			ch_xcvrif_l_dr_enabled_atom                        : string                        := "";
			ch_l_xcvr_tx_spread_spectrum_en_atom               : string                        := "";
			ch_l_rx_postdiv_clk_hz_atom                        : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_rx_postdiv_clk_fractional_en_atom             : string                        := "";
			ch_l_cdr_refclk_select_atom                        : string                        := "";
			ch_l_tx_postdiv_clk_hz_atom                        : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_tx_postdiv_clk_fractional_en_atom             : string                        := "";
			ch_flux_l_lc_postdiv_sel_atom                      : string                        := "";
			ch_flux_l_tx_user1_clk_mux_dynamic_sel_atom        : string                        := "";
			ch_flux_l_tx_user2_clk_mux_dynamic_sel_atom        : string                        := "";
			ch_flux_l_rx_user1_clk_mux_dynamic_sel_atom        : string                        := "";
			ch_flux_l_rx_user2_clk_mux_dynamic_sel_atom        : string                        := "";
			ch_xcvrif_l_tx_gb_width_atom                       : string                        := "";
			ch_xcvrif_l_rx_gb_width_atom                       : string                        := "";
			ch_xcvrif_l_tx_dynamic_mux_atom                    : string                        := "";
			ch_xcvrif_l_tx_word_clk_dynamic_mux_atom           : string                        := "";
			ch_xcvrif_l_rx_word_clk_dynamic_mux_atom           : string                        := "";
			ch_xcvrif_l_tx_fifo_rd_en_dynamic_mux_atom         : string                        := "";
			ch_xcvrif_l_rx_fifo_rd_en_dynamic_mux_atom         : string                        := "";
			ch_xcvrif_l_tx_rst_dynamic_mux_atom                : string                        := "";
			ch_l_clk_debug_select_0_enable_atom                : string                        := "";
			ch_l_clk_debug_select_0_setting_atom               : string                        := "";
			ch_l_clk_debug_select_1_enable_atom                : string                        := "";
			ch_l_clk_debug_select_1_setting_atom               : string                        := "";
			ch_l_xcvr_tx_eq_main_tap_atom                      : std_logic_vector(5 downto 0)  := "000000";
			ch_l_xcvr_tx_eq_post_tap_1_atom                    : std_logic_vector(4 downto 0)  := "00000";
			ch_l_xcvr_tx_eq_pre_tap_1_atom                     : std_logic_vector(4 downto 0)  := "00000";
			ch_l_xcvr_tx_eq_pre_tap_2_atom                     : std_logic_vector(2 downto 0)  := "000";
			ch_l_tx_pll_feed_forward_gain_atom                 : std_logic_vector(7 downto 0)  := "00000000";
			ch_l_xcvr_rx_termination_mode_atom                 : string                        := "";
			ch_l_xcvr_rx_onchip_termination_setting_atom       : string                        := "";
			ch_l_xcvr_rx_eq_vga_gain_atom                      : std_logic_vector(6 downto 0)  := "0000000";
			ch_l_xcvr_x_eq_hf_boost_atom                       : std_logic_vector(5 downto 0)  := "000000";
			ch_l_xcvr_rx_eq_dfe_tap_1_atom                     : std_logic_vector(5 downto 0)  := "000000";
			ch_l_xcvr_rx_external_couple_type_atom             : string                        := "";
			ch_l_xcvr_tx_bonding_category_atom                 : string                        := "";
			ch_l_xcvr_tx_master_pll_mode_atom                  : string                        := "";
			ch_l_xcvr_rx_cdrdivout_en_atom                     : string                        := "";
			ch_xcvrif_l_tx_bonding_mode_atom                   : string                        := "";
			ch_xcvrif_l_rx_bonding_mode_atom                   : string                        := "";
			ch_flux_l_sequencer_reg_en_atom                    : string                        := "";
			ch_l_speed_grade_atom                              : string                        := "";
			ch_usb_mode_atom                                   : string                        := "";
			ch_pcie_mode_atom                                  : string                        := "";
			ch_l_ick_tx_word_clk_hz_atom                       : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_pcs_ref_clk_hz_atom                           : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_l_lane_common_ref_clk_hz_atom                   : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_rx_invert_pin_atom                              : string                        := "";
			ch_tx_invert_pin_atom                              : string                        := "";
			ch_vsr_mode_atom                                   : string                        := "";
			ch_rx_dl_rx_lat_bit_for_async_atom                 : std_logic_vector(17 downto 0) := "000000000000000000";
			ch_rx_dl_rxbit_cntr_pma_atom                       : string                        := "";
			ch_rx_dl_rxbit_rollover_atom                       : std_logic_vector(17 downto 0) := "000000000000000000";
			ch_eth_rx_clk_hz_atom                              : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_eth_tx_clk_hz_atom                              : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000"
		);
		port (
			oflux_xoa_tx_n_l0_ux              : out std_logic;                                         -- data
			oflux_xoa_tx_p_l0_ux              : out std_logic;                                         -- data
			iflux_xia_rx_n_l0_ux              : in  std_logic                      := 'X';             -- data
			iflux_xia_rx_p_l0_ux              : in  std_logic                      := 'X';             -- data
			i_ss_async_pldif                  : in  std_logic_vector(79 downto 0)  := (others => 'X'); -- data
			o_ss_async_pldif                  : out std_logic_vector(49 downto 0);                     -- data
			i_ss_async_pldif_pcie_mux         : in  std_logic_vector(79 downto 0)  := (others => 'X'); -- data
			i_lavmm_addr                      : in  std_logic_vector(19 downto 0)  := (others => 'X'); -- address
			i_lavmm_be                        : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- byteenable
			i_lavmm_read                      : in  std_logic                      := 'X';             -- read
			i_lavmm_wdata                     : in  std_logic_vector(31 downto 0)  := (others => 'X'); -- writedata
			i_lavmm_write                     : in  std_logic                      := 'X';             -- write
			o_lavmm_rdata                     : out std_logic_vector(31 downto 0);                     -- readdata
			o_lavmm_rdata_valid               : out std_logic;                                         -- readdatavalid
			o_lavmm_waitreq                   : out std_logic;                                         -- waitrequest
			i_lavmm_clk                       : in  std_logic                      := 'X';             -- clk
			i_lavmm_rstn                      : in  std_logic                      := 'X';             -- reset
			i_ft_rx_sclk_sync_ch              : in  std_logic                      := 'X';             -- clk
			i_ft_tx_sclk_sync_ch              : in  std_logic                      := 'X';             -- clk
			o_ft_rx_async_pulse_ch            : out std_logic;                                         -- clk
			o_ft_tx_async_pulse_ch            : out std_logic;                                         -- clk
			o_rxcdrlock2dataa                 : out std_logic;                                         -- lockdata
			i_rst_ux_rx_sfrz                  : in  std_logic                      := 'X';             -- data
			o_rst_flux0_cpi_cmn_busy          : out std_logic;                                         -- busy
			o_rst_oflux_rx_srds_rdy           : out std_logic;                                         -- ready
			o_rst_ux_all_synthlockstatus      : out std_logic;                                         -- status
			o_rst_ux_rxcdrlockstatus          : out std_logic;                                         -- rxstatus
			i_ick_sclk_tx                     : in  std_logic                      := 'X';             -- clk
			i_ick_sclk_rx                     : in  std_logic                      := 'X';             -- clk
			i_rst_pld_ux_tx_pma_rst_n         : in  std_logic                      := 'X';             -- reset
			i_rst_pld_ux_rx_pma_rst_n         : in  std_logic                      := 'X';             -- reset
			o_ch_lavmm_xcvrif_rdata           : out std_logic_vector(31 downto 0);                     -- readdata
			o_ch_lavmm_xcvrif_rdata_valid     : out std_logic;                                         -- readdatavalid
			o_ch_lavmm_xcvrif_waitreq         : out std_logic;                                         -- waitrequest
			i_ch_lavmm_xcvrif_addr            : in  std_logic_vector(19 downto 0)  := (others => 'X'); -- address
			i_ch_lavmm_xcvrif_be              : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- byteenable
			i_ch_lavmm_xcvrif_read            : in  std_logic                      := 'X';             -- read
			i_ch_lavmm_xcvrif_wdata           : in  std_logic_vector(31 downto 0)  := (others => 'X'); -- writedata
			i_ch_lavmm_xcvrif_write           : in  std_logic                      := 'X';             -- write
			i_ch_lavmm_xcvrif_clk             : in  std_logic                      := 'X';             -- clk
			i_ch_lavmm_xcvrif_rstn            : in  std_logic                      := 'X';             -- reset
			o_rx_latency_pulse                : out std_logic;                                         -- clk
			o_tx_latency_pulse                : out std_logic;                                         -- clk
			i_ch_eth_xcvrif_tx_async          : in  std_logic_vector(6 downto 0)   := (others => 'X'); -- data
			i_ch_eth_xcvrif_tx_direct         : in  std_logic                      := 'X';             -- data
			o_ch_eth_xcvrif_rx_async          : out std_logic_vector(13 downto 0);                     -- data
			o_ch_eth_xcvrif_rx_direct         : out std_logic;                                         -- data
			i_rstxcvrif_xcvrif_signal_ok      : in  std_logic                      := 'X';             -- data
			i_rstxcvrif_rx_xcvrif_sfrz_n      : in  std_logic                      := 'X';             -- data
			i_rstxcvrif_xcvrif_rx_rst_n       : in  std_logic                      := 'X';             -- data
			i_rstxcvrif_tx_xcvrif_sfrz_n      : in  std_logic                      := 'X';             -- data
			i_rstxcvrif_xcvrif_tx_rst_n       : in  std_logic                      := 'X';             -- data
			o_pma_rx_sf                       : out std_logic;                                         -- data
			i_xcvrif_tx_mux_data              : in  std_logic_vector(42 downto 0)  := (others => 'X'); -- data
			o_rx_data                         : out std_logic_vector(42 downto 0);                     -- data
			o_tx_source_sel                   : out std_logic_vector(1 downto 0);                      -- data
			o_rx_fifo_en_sel                  : out std_logic_vector(2 downto 0);                      -- data
			o_tx_rst_source_sel               : out std_logic_vector(2 downto 0);                      -- data
			i_ch_xcvrif_rx_fifo_rd_en         : in  std_logic                      := 'X';             -- data
			o_ch_xcvrif_rx_fifo_rd_en         : out std_logic;                                         -- data
			i_ch_xcvrif_tx_fifo_rd_en         : in  std_logic                      := 'X';             -- data
			o_ch_xcvrif_tx_fifo_rd_en         : out std_logic;                                         -- data
			o_ux_rxuser1_sel                  : out std_logic_vector(1 downto 0);                      -- data
			o_ux_rxuser2_sel                  : out std_logic_vector(1 downto 0);                      -- data
			o_ux_txuser1_sel                  : out std_logic_vector(1 downto 0);                      -- data
			o_ux_txuser2_sel                  : out std_logic_vector(1 downto 0);                      -- data
			o_pcs_rxpostdiv                   : out std_logic;                                         -- data
			o_pcs_rxword                      : out std_logic;                                         -- data
			o_ux_txlc_clk                     : out std_logic;                                         -- clk
			o_tx_xcvr_wordclk_sel             : out std_logic_vector(2 downto 0);                      -- data
			o_rx_xcvr_wordclk_sel             : out std_logic_vector(1 downto 0);                      -- data
			i_eth_rx_ch_clk                   : in  std_logic                      := 'X';             -- clk
			uxwrap_bus_in                     : in  std_logic_vector(767 downto 0) := (others => 'X'); -- data
			uxwrap_bus_out                    : out std_logic_vector(703 downto 0);                    -- data
			o_lavmm_addr                      : out std_logic_vector(19 downto 0);                     -- address
			o_lavmm_be                        : out std_logic_vector(3 downto 0);                      -- byteenable
			o_lavmm_read                      : out std_logic;                                         -- read
			o_lavmm_wdata                     : out std_logic_vector(31 downto 0);                     -- writedata
			o_lavmm_write                     : out std_logic;                                         -- write
			i_lavmm_rdata                     : in  std_logic_vector(31 downto 0)  := (others => 'X'); -- readdata
			i_lavmm_rdata_valid               : in  std_logic                      := 'X';             -- readdatavalid
			i_lavmm_waitreq                   : in  std_logic                      := 'X';             -- waitrequest
			o_lavmm_clk                       : out std_logic;                                         -- clk
			o_lavmm_rstn                      : out std_logic;                                         -- reset
			o_sclk_return_sel_rx              : out std_logic;                                         -- data
			o_sclk_return_sel_tx              : out std_logic;                                         -- data
			o_ick_sclk_rx                     : out std_logic;                                         -- clk
			i_sync_common_control             : in  std_logic_vector(4 downto 0)   := (others => 'X'); -- data
			o_ft_rx_sclk_sync_ch              : out std_logic;                                         -- data
			o_ft_tx_sclk_sync_ch              : out std_logic;                                         -- data
			o_rst_ux_rx_pma_rst_n             : out std_logic;                                         -- reset
			o_rst_ux_tx_pma_rst_n             : out std_logic;                                         -- reset
			o_ick_pcs_txword                  : out std_logic;                                         -- data
			o_tx_dl_ch_bit                    : out std_logic;                                         -- data
			i_dat_pcs_measlatbit              : in  std_logic                      := 'X';             -- data
			i_ft_rx_async_pulse_ch            : in  std_logic                      := 'X';             -- data
			i_ft_tx_async_pulse_ch            : in  std_logic                      := 'X';             -- data
			i_rx_dl_ch_bit                    : in  std_logic                      := 'X';             -- data
			i_ux_rxuser1_sel                  : in  std_logic_vector(1 downto 0)   := (others => 'X'); -- data
			i_ux_rxuser2_sel                  : in  std_logic_vector(1 downto 0)   := (others => 'X'); -- data
			i_ux_txuser1_sel                  : in  std_logic_vector(1 downto 0)   := (others => 'X'); -- data
			i_ux_txuser2_sel                  : in  std_logic_vector(1 downto 0)   := (others => 'X'); -- data
			o_octl_pcs_txstatus_a             : out std_logic;                                         -- data
			i_ictl_pcs_txenable_a             : in  std_logic                      := 'X';             -- data
			i_sync_cfg_data                   : in  std_logic_vector(124 downto 0) := (others => 'X'); -- data
			i_sync_interface_control          : in  std_logic_vector(249 downto 0) := (others => 'X'); -- data
			o_tx_data                         : out std_logic_vector(79 downto 0);                     -- data
			i_rx_data                         : in  std_logic_vector(79 downto 0)  := (others => 'X'); -- data
			o_sm_flux_ingress                 : out std_logic_vector(319 downto 0);                    -- data
			i_sm_flux_egress                  : in  std_logic_vector(256 downto 0) := (others => 'X'); -- data
			i_flux_cpi_int                    : in  std_logic                      := 'X';             -- data
			i_flux_int                        : in  std_logic                      := 'X';             -- data
			i_oflux_octl_pcs_txptr_smpl_lane  : in  std_logic                      := 'X';             -- data
			o_ick_sclk_tx                     : out std_logic;                                         -- clk
			i_flux_srds_rdy                   : in  std_logic                      := 'X';             -- data
			i_pcs_rxword                      : in  std_logic                      := 'X';             -- data
			i_pcs_rxpostdiv                   : in  std_logic                      := 'X';             -- data
			i_ock_pcs_txword                  : in  std_logic                      := 'X';             -- data
			o_dat_pcs_measlatrndtripbit       : out std_logic;                                         -- data
			o_ock_pcs_cdrfbclk                : out std_logic;                                         -- data
			o_ock_pcs_ref                     : out std_logic;                                         -- data
			o_pcie_pcs                        : out std_logic_vector(39 downto 0);                     -- data
			i_pcie_pcs                        : in  std_logic_vector(39 downto 0)  := (others => 'X'); -- data
			i_sel_rxword_clk                  : in  std_logic                      := 'X';             -- clk
			i_xcvr_txword_clk                 : in  std_logic                      := 'X';             -- clk
			o_pcie_rxword_clk                 : out std_logic;                                         -- clk
			o_eth_rxword_clk                  : out std_logic;                                         -- clk
			o_pcie_txword_clk                 : out std_logic;                                         -- clk
			o_eth_txword_clk                  : out std_logic;                                         -- clk
			o_ock_pcs_txword                  : out std_logic;                                         -- clk
			o_eth_rx_ch_clk                   : out std_logic;                                         -- clk
			o_eth_tx_ch_clk                   : out std_logic;                                         -- clk
			ioack_ref_left_p_ux_bidir_in      : in  std_logic_vector(5 downto 0)   := (others => 'X'); -- data
			ioack_hsref_left_p_ux_bidir_in    : in  std_logic                      := 'X';             -- clk
			ioack_cdrdiv_left_ux_bidir_in     : in  std_logic                      := 'X';             -- clk
			ioack_synthdiv1_left_ux_bidir_in  : in  std_logic                      := 'X';             -- clk
			ioack_synthdiv2_left_ux_bidir_in  : in  std_logic                      := 'X';             -- clk
			ioack_cdrdiv_left_ux_bidir_out    : out std_logic;                                         -- clk
			ioack_synthdiv1_left_ux_bidir_out : out std_logic;                                         -- clk
			ioack_synthdiv2_left_ux_bidir_out : out std_logic;                                         -- clk
			o_rxeq_best_eye_vala              : out std_logic_vector(13 downto 0);                     -- data
			o_rxeq_donea                      : out std_logic;                                         -- data
			o_rxmargin_nacka                  : out std_logic;                                         -- data
			o_rxmargin_statusa                : out std_logic;                                         -- data
			o_rxsignaldetect_lfpsa            : out std_logic;                                         -- data
			o_rxsignaldetecta                 : out std_logic;                                         -- data
			o_rxmargin_status_gray            : out std_logic_vector(1 downto 0);                      -- data
			o_rxstatusa                       : out std_logic;                                         -- data
			o_synthlcfast_postdiv             : out std_logic;                                         -- data
			o_synthlcmed_postdiv              : out std_logic;                                         -- data
			o_synthlcslow_postdiv             : out std_logic;                                         -- data
			o_txdetectrx_acka                 : out std_logic;                                         -- data
			o_txdetectrx_statct               : out std_logic;                                         -- data
			o_txstatusa                       : out std_logic;                                         -- data
			i_quartus_flux_s_to_ingress       : in  std_logic                      := 'X';             -- data
			i_pcs_pipe_rstn                   : in  std_logic                      := 'X';             -- data
			i_ux_ock_pma_clk                  : in  std_logic                      := 'X';             -- data
			i_lfps_ennt                       : in  std_logic                      := 'X';             -- data
			i_pcie_l1ctrla                    : in  std_logic_vector(1 downto 0)   := (others => 'X'); -- data
			i_pma_cmn_ctrl                    : in  std_logic                      := 'X';             -- data
			i_pma_ctrl                        : in  std_logic                      := 'X';             -- data
			i_pcie_pcs_rx_rst                 : in  std_logic                      := 'X';             -- data
			i_pcie_pcs_tx_rst                 : in  std_logic                      := 'X';             -- data
			i_rxeiosdetectstata               : in  std_logic                      := 'X';             -- data
			i_rxeq_precal_code_selnt          : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_rxeq_starta                     : in  std_logic                      := 'X';             -- data
			i_rxeq_static_ena                 : in  std_logic                      := 'X';             -- data
			i_rxmargin_direction_nt           : in  std_logic                      := 'X';             -- data
			i_rxmargin_mode_nt                : in  std_logic                      := 'X';             -- data
			i_rxmargin_offset_change_a        : in  std_logic                      := 'X';             -- data
			i_rxmargin_offset_nt              : in  std_logic_vector(6 downto 0)   := (others => 'X'); -- data
			i_rxmargin_start_a                : in  std_logic                      := 'X';             -- data
			i_rxpstate                        : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_rxrate                          : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- data
			i_rxterm_hiz_ena                  : in  std_logic                      := 'X';             -- data
			i_rxwidth                         : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_tstbus_lane                     : in  std_logic                      := 'X';             -- data
			i_txbeacona                       : in  std_logic                      := 'X';             -- data
			i_txclkdivrate                    : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_txdetectrx_reqa                 : in  std_logic                      := 'X';             -- data
			i_txdrv_levn                      : in  std_logic_vector(5 downto 0)   := (others => 'X'); -- data
			i_txdrv_levnm1                    : in  std_logic_vector(4 downto 0)   := (others => 'X'); -- data
			i_txdrv_levnm2                    : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_txdrv_levnp1                    : in  std_logic_vector(4 downto 0)   := (others => 'X'); -- data
			i_txdrv_slew                      : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- data
			i_txelecidle                      : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- data
			i_txpstate                        : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_txrate                          : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- data
			i_txwidth                         : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_rstxcvrif_xcvrif_tx_rd_rst_n    : in  std_logic                      := 'X';             -- data
			i_rstxcvrif_xcvrif_tx_wr_rst_n    : in  std_logic                      := 'X';             -- data
			o_tx_rst_rd_sync_rst_n            : out std_logic;                                         -- data
			o_tx_rst_wr_sync_rst_n            : out std_logic                                          -- data
		);
	end component gts_axi_streaming_phy_hal_2100_jhh6v6q_cmp;

	for phy_hal_top : gts_axi_streaming_phy_hal_2100_jhh6v6q_cmp
		use entity phy_hal_2100.gts_axi_streaming_phy_hal_2100_jhh6v6q;
begin

	device_die_type_check : if device_die_type /= "MAIN_SM7" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	device_die_revisions_check : if device_die_revisions /= "MAIN_SM7_REVA" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_loopback_mode_atom_check : if ch_xcvrif_l_loopback_mode_atom /= "LOOPBACK_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_stmux_rx_demux_sel_check : if ch_flux_l_stmux_rx_demux_sel /= "SEL_PCIE_PCS" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_stmux_rx_rxword_clk_demux_sel_check : if ch_flux_l_stmux_rx_rxword_clk_demux_sel /= "SEL_PCIE_RXWORD_CLK" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_stmux_tx_txword_clk_demux_sel_check : if ch_flux_l_stmux_tx_txword_clk_demux_sel /= "SEL_PCIE_TXWORD_CLK" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_stmux_tx_mux_sel_check : if ch_flux_l_stmux_tx_mux_sel /= "SEL_PCIE_PCS" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_stmux_tx_txword_clk_mux_sel_check : if ch_flux_l_stmux_tx_txword_clk_mux_sel /= "SEL_UX_OCK_PMA_CLK" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_rx_ch_clk_static_mux_check : if ch_xcvrif_rx_ch_clk_static_mux /= "SEL_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_tx_ch_clk_static_mux_check : if ch_xcvrif_tx_ch_clk_static_mux /= "SEL_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_tx_bond_size_atom_check : if ch_flux_l_tx_bond_size_atom /= "TX_BOND_SIZE_X4" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_bond_size_atom_check : if ch_l_xcvr_tx_bond_size_atom /= "TX_BOND_SIZE_X4" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_tx_bond_size_atom_check : if ch_xcvrif_l_tx_bond_size_atom /= "TX_BOND_SIZE_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_rx_bond_size_atom_check : if ch_xcvrif_l_rx_bond_size_atom /= "RX_BOND_SIZE_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_clkrx_refclk_cssm_fw_control_atom_check : if ch_clkrx_refclk_cssm_fw_control_atom /= "CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_clkrx_refclk_sector_specifies_refclk_ready_atom_check : if ch_clkrx_refclk_sector_specifies_refclk_ready_atom /= "CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_local_refclk_cssm_fw_control_atom_check : if ch_local_refclk_cssm_fw_control_atom /= "LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_local_refclk_sector_specifies_refclk_ready_atom_check : if ch_local_refclk_sector_specifies_refclk_ready_atom /= "LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_cdr_f_out_hz_atom_check : if ch_l_xcvr_cdr_f_out_hz_atom /= "000011101110011010110010100000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_cdr_f_vco_hz_atom_check : if ch_l_xcvr_cdr_f_vco_hz_atom /= "001001010100000010111110010000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_cdr_f_pfd_hz_atom_check : if ch_l_xcvr_cdr_f_pfd_hz_atom /= "000000000101111101011110000100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_cdr_f_ref_hz_atom_check : if ch_l_xcvr_cdr_f_ref_hz_atom /= "000000000101111101011110000100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_cdr_l_counter_atom_check : if ch_l_cdr_l_counter_atom /= "000010" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_cdr_m_counter_atom_check : if ch_l_cdr_m_counter_atom /= "000110010" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_cdr_n_counter_atom_check : if ch_l_cdr_n_counter_atom /= "000001" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_postdiv_sel_sm4_atom_check : if ch_l_tx_pll_postdiv_sel_sm4_atom /= "TX_PLL_POSTDIV_SEL_SYNTH2" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_postdiv_sel_sm7_atom_check : if ch_l_tx_pll_postdiv_sel_sm7_atom /= "TX_PLL_POSTDIV_SEL_SYNTH2" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_bw_sel_atom_check : if ch_l_tx_pll_bw_sel_atom /= "TX_PLL_BW_SEL_LOW" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_f_out_hz_atom_check : if ch_l_tx_pll_f_out_hz_atom /= "000011101110011010110010100000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_f_vco_hz_atom_check : if ch_l_tx_pll_f_vco_hz_atom /= "001001010100000010111110010000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_f_pfd_hz_atom_check : if ch_l_tx_pll_f_pfd_hz_atom /= "000000000101111101011110000100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_f_ref_hz_atom_check : if ch_l_tx_pll_f_ref_hz_atom /= "000000000101111101011110000100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_k_counter_atom_check : if ch_l_tx_pll_k_counter_atom /= "0000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_l_counter_atom_check : if ch_l_tx_pll_l_counter_atom /= "000010" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_m_counter_atom_check : if ch_l_tx_pll_m_counter_atom /= "001100100" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_n_counter_atom_check : if ch_l_tx_pll_n_counter_atom /= "000001" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_fb_counter_atom_check : if ch_l_tx_pll_fb_counter_atom /= "01" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_postdiv_cdr_refclk_hz_atom_check : if ch_l_tx_postdiv_cdr_refclk_hz_atom /= "000000000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_postdiv_cdr_refclk_divider_atom_check : if ch_l_tx_postdiv_cdr_refclk_divider_atom /= "00001100" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_synthdiv_out_divider_atom_check : if ch_l_tx_synthdiv_out_divider_atom /= "00001100" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_synthdiv_out_hz_atom_check : if ch_l_tx_synthdiv_out_hz_atom /= "000000000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_preloaded_hardware_configs_atom_check : if ch_l_xcvr_tx_preloaded_hardware_configs_atom /= "TX_PRELOADED_HARDWARE_CONFIGS_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_protocol_hint_atom_check : if ch_l_xcvr_tx_protocol_hint_atom /= "TX_PROTOCOL_HINT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_datarate_bps_atom_check : if ch_l_xcvr_tx_datarate_bps_atom /= "0000111011100110101100101000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_prbs_gen_en_atom_check : if ch_l_xcvr_tx_prbs_gen_en_atom /= "TX_PRBS_GEN_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_prbs_pattern_atom_check : if ch_l_xcvr_tx_prbs_pattern_atom /= "0000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_user_clk_only_mode_atom_check : if ch_l_xcvr_tx_user_clk_only_mode_atom /= "TX_USER_CLK_ONLY_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_width_atom_check : if ch_l_xcvr_tx_width_atom /= "TX_WIDTH_X16" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_word_clk_hz_atom_check : if ch_l_xcvr_tx_word_clk_hz_atom /= "000000011101110011010110010100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_dl_enable_atom_check : if ch_l_xcvr_tx_dl_enable_atom /= "TX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_preloaded_hardware_configs_atom_check : if ch_l_xcvr_rx_preloaded_hardware_configs_atom /= "RX_PRELOADED_HARDWARE_CONFIGS_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_protocol_hint_atom_check : if ch_l_xcvr_rx_protocol_hint_atom /= "RX_PROTOCOL_HINT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_datarate_bps_atom_check : if ch_l_xcvr_rx_datarate_bps_atom /= "0000111011100110101100101000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_prbs_monitor_en_atom_check : if ch_l_xcvr_rx_prbs_monitor_en_atom /= "RX_PRBS_MONITOR_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_prbs_pattern_atom_check : if ch_l_xcvr_rx_prbs_pattern_atom /= "0001" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_width_atom_check : if ch_l_xcvr_rx_width_atom /= "RX_WIDTH_X16" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_force_cdr_ltr_atom_check : if ch_l_xcvr_rx_force_cdr_ltr_atom /= "TRUE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_adaptation_mode_atom_check : if ch_l_xcvr_rx_adaptation_mode_atom /= "RX_ADAPTATION_MODE_UX_NATIVE_ADAPTATION" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_adaptation_mode_hw_atom_check : if ch_l_xcvr_rx_adaptation_mode_hw_atom /= "RX_ADAPTATION_MODE_UX_NATIVE_ADAPTATION" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_word_clk_hz_atom_check : if ch_l_xcvr_rx_word_clk_hz_atom /= "000000011101110011010110010100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_dl_enable_atom_check : if ch_l_xcvr_rx_dl_enable_atom /= "RX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_rx_postdiv_clk_en_atom_check : if ch_l_rx_postdiv_clk_en_atom /= "RX_POSTDIV_CLK_EN_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_rx_postdiv_clk_divider_atom_check : if ch_l_rx_postdiv_clk_divider_atom /= "00001100" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_postdiv_clk_divider_atom_check : if ch_l_tx_postdiv_clk_divider_atom /= "10001001" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_refclk_select_atom_check : if ch_l_tx_pll_refclk_select_atom /= "TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_loopback_mode_atom_check : if ch_l_loopback_mode_atom /= "LOOPBACK_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_flux_mode_atom_check : if ch_flux_l_flux_mode_atom /= "FLUX_MODE_FLUX_MODE_BYPASS" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_flux_mode_hw_atom_check : if ch_flux_l_flux_mode_hw_atom /= "FLUX_MODE_FLUX_MODE_BYPASS" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_rx_protocol_hint_atom_check : if ch_flux_l_rx_protocol_hint_atom /= "RX_PROTOCOL_HINT_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_tx_dl_enable_atom_check : if ch_flux_l_tx_dl_enable_atom /= "TX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_rx_dl_enable_atom_check : if ch_flux_l_rx_dl_enable_atom /= "RX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_tx_dl_enable_atom_check : if ch_xcvrif_l_tx_dl_enable_atom /= "TX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_rx_dl_enable_atom_check : if ch_xcvrif_l_rx_dl_enable_atom /= "RX_DL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_tx_fifo_mode_atom_check : if ch_xcvrif_l_tx_fifo_mode_atom /= "TX_FIFO_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_rx_fifo_mode_atom_check : if ch_xcvrif_l_rx_fifo_mode_atom /= "RX_FIFO_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_en_atom_check : if ch_l_xcvr_tx_en_atom /= "TRUE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_en_atom_check : if ch_l_xcvr_rx_en_atom /= "TRUE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_duplex_mode_atom_check : if ch_l_duplex_mode_atom /= "DUPLEX_MODE_DUPLEX" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_tx_en_atom_check : if ch_xcvrif_l_tx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_rx_en_atom_check : if ch_xcvrif_l_rx_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_duplex_mode_atom_check : if ch_xcvrif_l_duplex_mode_atom /= "DUPLEX_MODE_DUPLEX" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_rx_fec_type_used_atom_check : if ch_flux_l_rx_fec_type_used_atom /= "RX_FEC_TYPE_USED_NONE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_sim_mode_atom_check : if ch_l_sim_mode_atom /= "SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_rx_sim_mode_atom_check : if ch_flux_l_rx_sim_mode_atom /= "RX_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_tx_sim_mode_atom_check : if ch_flux_l_tx_sim_mode_atom /= "TX_SIM_MODE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_dr_enabled_atom_check : if ch_flux_l_dr_enabled_atom /= "DR_ENABLED_DR_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_sup_mode_atom_check : if ch_xcvrif_l_sup_mode_atom /= "SUP_MODE_USER_MODE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_sim_mode_atom_check : if ch_xcvrif_l_sim_mode_atom /= "SIM_MODE_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_dr_enabled_atom_check : if ch_xcvrif_l_dr_enabled_atom /= "DR_ENABLED_DR_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_spread_spectrum_en_atom_check : if ch_l_xcvr_tx_spread_spectrum_en_atom /= "TX_SPREAD_SPECTRUM_EN_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_rx_postdiv_clk_hz_atom_check : if ch_l_rx_postdiv_clk_hz_atom /= "000000000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_rx_postdiv_clk_fractional_en_atom_check : if ch_l_rx_postdiv_clk_fractional_en_atom /= "RX_POSTDIV_CLK_FRACTIONAL_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_cdr_refclk_select_atom_check : if ch_l_cdr_refclk_select_atom /= "CDR_REFCLK_SELECT_GLOBAL_REFCLK0" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_postdiv_clk_hz_atom_check : if ch_l_tx_postdiv_clk_hz_atom /= "000000000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_postdiv_clk_fractional_en_atom_check : if ch_l_tx_postdiv_clk_fractional_en_atom /= "TX_POSTDIV_CLK_FRACTIONAL_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_lc_postdiv_sel_atom_check : if ch_flux_l_lc_postdiv_sel_atom /= "LC_POSTDIV_SEL_SYNTH2" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_tx_user1_clk_mux_dynamic_sel_atom_check : if ch_flux_l_tx_user1_clk_mux_dynamic_sel_atom /= "TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_tx_user2_clk_mux_dynamic_sel_atom_check : if ch_flux_l_tx_user2_clk_mux_dynamic_sel_atom /= "TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_rx_user1_clk_mux_dynamic_sel_atom_check : if ch_flux_l_rx_user1_clk_mux_dynamic_sel_atom /= "RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_rx_user2_clk_mux_dynamic_sel_atom_check : if ch_flux_l_rx_user2_clk_mux_dynamic_sel_atom /= "RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_tx_gb_width_atom_check : if ch_xcvrif_l_tx_gb_width_atom /= "TX_GB_WIDTH_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_rx_gb_width_atom_check : if ch_xcvrif_l_rx_gb_width_atom /= "RX_GB_WIDTH_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_tx_dynamic_mux_atom_check : if ch_xcvrif_l_tx_dynamic_mux_atom /= "TX_DYNAMIC_MUX_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_tx_word_clk_dynamic_mux_atom_check : if ch_xcvrif_l_tx_word_clk_dynamic_mux_atom /= "TX_WORD_CLK_DYNAMIC_MUX_X4" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_rx_word_clk_dynamic_mux_atom_check : if ch_xcvrif_l_rx_word_clk_dynamic_mux_atom /= "RX_WORD_CLK_DYNAMIC_MUX_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_tx_fifo_rd_en_dynamic_mux_atom_check : if ch_xcvrif_l_tx_fifo_rd_en_dynamic_mux_atom /= "TX_FIFO_RD_EN_DYNAMIC_MUX_X4" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_rx_fifo_rd_en_dynamic_mux_atom_check : if ch_xcvrif_l_rx_fifo_rd_en_dynamic_mux_atom /= "RX_FIFO_RD_EN_DYNAMIC_MUX_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_tx_rst_dynamic_mux_atom_check : if ch_xcvrif_l_tx_rst_dynamic_mux_atom /= "TX_RST_DYNAMIC_MUX_X4" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_clk_debug_select_0_enable_atom_check : if ch_l_clk_debug_select_0_enable_atom /= "CLK_DEBUG_SELECT_0_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_clk_debug_select_0_setting_atom_check : if ch_l_clk_debug_select_0_setting_atom /= "CLK_DEBUG_SELECT_0_SETTING_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_clk_debug_select_1_enable_atom_check : if ch_l_clk_debug_select_1_enable_atom /= "CLK_DEBUG_SELECT_1_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_clk_debug_select_1_setting_atom_check : if ch_l_clk_debug_select_1_setting_atom /= "CLK_DEBUG_SELECT_1_SETTING_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_eq_main_tap_atom_check : if ch_l_xcvr_tx_eq_main_tap_atom /= "000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_eq_post_tap_1_atom_check : if ch_l_xcvr_tx_eq_post_tap_1_atom /= "00000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_eq_pre_tap_1_atom_check : if ch_l_xcvr_tx_eq_pre_tap_1_atom /= "00000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_eq_pre_tap_2_atom_check : if ch_l_xcvr_tx_eq_pre_tap_2_atom /= "000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_tx_pll_feed_forward_gain_atom_check : if ch_l_tx_pll_feed_forward_gain_atom /= "01000011" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_termination_mode_atom_check : if ch_l_xcvr_rx_termination_mode_atom /= "RX_TERMINATION_MODE_GROUNDED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_onchip_termination_setting_atom_check : if ch_l_xcvr_rx_onchip_termination_setting_atom /= "RX_ONCHIP_TERMINATION_SETTING_R_1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_eq_vga_gain_atom_check : if ch_l_xcvr_rx_eq_vga_gain_atom /= "0100000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_x_eq_hf_boost_atom_check : if ch_l_xcvr_x_eq_hf_boost_atom /= "100000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_eq_dfe_tap_1_atom_check : if ch_l_xcvr_rx_eq_dfe_tap_1_atom /= "000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_external_couple_type_atom_check : if ch_l_xcvr_rx_external_couple_type_atom /= "RX_EXTERNAL_COUPLE_TYPE_AC" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_bonding_category_atom_check : if ch_l_xcvr_tx_bonding_category_atom /= "TX_BONDING_CATEGORY_BONDING_FOLLOWER" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_master_pll_mode_atom_check : if ch_l_xcvr_tx_master_pll_mode_atom /= "TX_MASTER_PLL_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_cdrdivout_en_atom_check : if ch_l_xcvr_rx_cdrdivout_en_atom /= "RX_CDRDIVOUT_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_tx_bonding_mode_atom_check : if ch_xcvrif_l_tx_bonding_mode_atom /= "TX_BONDING_MODE_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_xcvrif_l_rx_bonding_mode_atom_check : if ch_xcvrif_l_rx_bonding_mode_atom /= "RX_BONDING_MODE_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_flux_l_sequencer_reg_en_atom_check : if ch_flux_l_sequencer_reg_en_atom /= "SEQUENCER_REG_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_speed_grade_atom_check : if ch_l_speed_grade_atom /= "SPEED_GRADE_DASH_1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_usb_mode_atom_check : if ch_usb_mode_atom /= "USB_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pcie_mode_atom_check : if ch_pcie_mode_atom /= "PCIE_MODE_GEN3" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_ick_tx_word_clk_hz_atom_check : if ch_l_ick_tx_word_clk_hz_atom /= "100101011100000111110010100001110010" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_pcs_ref_clk_hz_atom_check : if ch_l_pcs_ref_clk_hz_atom /= "101001111010110110010111101111110101" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_lane_common_ref_clk_hz_atom_check : if ch_l_lane_common_ref_clk_hz_atom /= "111110010011110101111111101000101001" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_rx_invert_pin_atom_check : if ch_rx_invert_pin_atom /= "RX_INVERT_PIN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_tx_invert_pin_atom_check : if ch_tx_invert_pin_atom /= "TX_INVERT_PIN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_vsr_mode_atom_check : if ch_vsr_mode_atom /= "VSR_MODE_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_rx_dl_rx_lat_bit_for_async_atom_check : if ch_rx_dl_rx_lat_bit_for_async_atom /= "111110100110100101" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_rx_dl_rxbit_cntr_pma_atom_check : if ch_rx_dl_rxbit_cntr_pma_atom /= "RX_DL_RXBIT_CNTR_PMA_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_rx_dl_rxbit_rollover_atom_check : if ch_rx_dl_rxbit_rollover_atom /= "001001111001000101" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_eth_rx_clk_hz_atom_check : if ch_eth_rx_clk_hz_atom /= "000000000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_eth_tx_clk_hz_atom_check : if ch_eth_tx_clk_hz_atom /= "000000000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	phy_hal_top : component gts_axi_streaming_phy_hal_2100_jhh6v6q_cmp
		generic map (
			device_die_type                                    => "MAIN_SM7",
			device_die_revisions                               => "MAIN_SM7_REVA",
			ch_xcvrif_l_loopback_mode_atom                     => "LOOPBACK_MODE_DISABLE",
			ch_flux_l_stmux_rx_demux_sel                       => "SEL_PCIE_PCS",
			ch_flux_l_stmux_rx_rxword_clk_demux_sel            => "SEL_PCIE_RXWORD_CLK",
			ch_flux_l_stmux_tx_txword_clk_demux_sel            => "SEL_PCIE_TXWORD_CLK",
			ch_flux_l_stmux_tx_mux_sel                         => "SEL_PCIE_PCS",
			ch_flux_l_stmux_tx_txword_clk_mux_sel              => "SEL_UX_OCK_PMA_CLK",
			ch_xcvrif_rx_ch_clk_static_mux                     => "SEL_UNUSED",
			ch_xcvrif_tx_ch_clk_static_mux                     => "SEL_UNUSED",
			ch_flux_l_tx_bond_size_atom                        => "TX_BOND_SIZE_X4",
			ch_l_xcvr_tx_bond_size_atom                        => "TX_BOND_SIZE_X4",
			ch_xcvrif_l_tx_bond_size_atom                      => "TX_BOND_SIZE_UNUSED",
			ch_xcvrif_l_rx_bond_size_atom                      => "RX_BOND_SIZE_UNUSED",
			ch_clkrx_refclk_cssm_fw_control_atom               => "CLKRX_REFCLK_CSSM_FW_CONTROL_DISABLE",
			ch_clkrx_refclk_sector_specifies_refclk_ready_atom => "CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE",
			ch_local_refclk_cssm_fw_control_atom               => "LOCAL_REFCLK_CSSM_FW_CONTROL_DISABLE",
			ch_local_refclk_sector_specifies_refclk_ready_atom => "LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_DISABLE",
			ch_l_xcvr_cdr_f_out_hz_atom                        => "000011101110011010110010100000000000",
			ch_l_xcvr_cdr_f_vco_hz_atom                        => "001001010100000010111110010000000000",
			ch_l_xcvr_cdr_f_pfd_hz_atom                        => "000000000101111101011110000100000000",
			ch_l_xcvr_cdr_f_ref_hz_atom                        => "000000000101111101011110000100000000",
			ch_l_cdr_l_counter_atom                            => "000010",
			ch_l_cdr_m_counter_atom                            => "000110010",
			ch_l_cdr_n_counter_atom                            => "000001",
			ch_l_tx_pll_postdiv_sel_sm4_atom                   => "TX_PLL_POSTDIV_SEL_SYNTH2",
			ch_l_tx_pll_postdiv_sel_sm7_atom                   => "TX_PLL_POSTDIV_SEL_SYNTH2",
			ch_l_tx_pll_bw_sel_atom                            => "TX_PLL_BW_SEL_LOW",
			ch_l_tx_pll_f_out_hz_atom                          => "000011101110011010110010100000000000",
			ch_l_tx_pll_f_vco_hz_atom                          => "001001010100000010111110010000000000",
			ch_l_tx_pll_f_pfd_hz_atom                          => "000000000101111101011110000100000000",
			ch_l_tx_pll_f_ref_hz_atom                          => "000000000101111101011110000100000000",
			ch_l_tx_pll_k_counter_atom                         => "0000000000000000000000",
			ch_l_tx_pll_l_counter_atom                         => "000010",
			ch_l_tx_pll_m_counter_atom                         => "001100100",
			ch_l_tx_pll_n_counter_atom                         => "000001",
			ch_l_tx_pll_fb_counter_atom                        => "01",
			ch_l_tx_postdiv_cdr_refclk_hz_atom                 => "000000000000000000000000000000000000",
			ch_l_tx_postdiv_cdr_refclk_divider_atom            => "00001100",
			ch_l_tx_synthdiv_out_divider_atom                  => "00001100",
			ch_l_tx_synthdiv_out_hz_atom                       => "000000000000000000000000000000000000",
			ch_l_xcvr_tx_preloaded_hardware_configs_atom       => "TX_PRELOADED_HARDWARE_CONFIGS_PCIE",
			ch_l_xcvr_tx_protocol_hint_atom                    => "TX_PROTOCOL_HINT_DISABLED",
			ch_l_xcvr_tx_datarate_bps_atom                     => "0000111011100110101100101000000000000",
			ch_l_xcvr_tx_prbs_gen_en_atom                      => "TX_PRBS_GEN_EN_DISABLE",
			ch_l_xcvr_tx_prbs_pattern_atom                     => "0000",
			ch_l_xcvr_tx_user_clk_only_mode_atom               => "TX_USER_CLK_ONLY_MODE_DISABLE",
			ch_l_xcvr_tx_width_atom                            => "TX_WIDTH_X16",
			ch_l_xcvr_tx_word_clk_hz_atom                      => "000000011101110011010110010100000000",
			ch_l_xcvr_tx_dl_enable_atom                        => "TX_DL_ENABLE_DISABLE",
			ch_l_xcvr_rx_preloaded_hardware_configs_atom       => "RX_PRELOADED_HARDWARE_CONFIGS_PCIE",
			ch_l_xcvr_rx_protocol_hint_atom                    => "RX_PROTOCOL_HINT_DISABLED",
			ch_l_xcvr_rx_datarate_bps_atom                     => "0000111011100110101100101000000000000",
			ch_l_xcvr_rx_prbs_monitor_en_atom                  => "RX_PRBS_MONITOR_EN_DISABLE",
			ch_l_xcvr_rx_prbs_pattern_atom                     => "0001",
			ch_l_xcvr_rx_width_atom                            => "RX_WIDTH_X16",
			ch_l_xcvr_rx_force_cdr_ltr_atom                    => "TRUE",
			ch_l_xcvr_rx_adaptation_mode_atom                  => "RX_ADAPTATION_MODE_UX_NATIVE_ADAPTATION",
			ch_l_xcvr_rx_adaptation_mode_hw_atom               => "RX_ADAPTATION_MODE_UX_NATIVE_ADAPTATION",
			ch_l_xcvr_rx_word_clk_hz_atom                      => "000000011101110011010110010100000000",
			ch_l_xcvr_rx_dl_enable_atom                        => "RX_DL_ENABLE_DISABLE",
			ch_l_rx_postdiv_clk_en_atom                        => "RX_POSTDIV_CLK_EN_ENABLE",
			ch_l_rx_postdiv_clk_divider_atom                   => "00001100",
			ch_l_tx_postdiv_clk_divider_atom                   => "10001001",
			ch_l_tx_pll_refclk_select_atom                     => "TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0",
			ch_l_loopback_mode_atom                            => "LOOPBACK_MODE_DISABLED",
			ch_flux_l_flux_mode_atom                           => "FLUX_MODE_FLUX_MODE_BYPASS",
			ch_flux_l_flux_mode_hw_atom                        => "FLUX_MODE_FLUX_MODE_BYPASS",
			ch_flux_l_rx_protocol_hint_atom                    => "RX_PROTOCOL_HINT_DISABLED",
			ch_flux_l_tx_dl_enable_atom                        => "TX_DL_ENABLE_DISABLE",
			ch_flux_l_rx_dl_enable_atom                        => "RX_DL_ENABLE_DISABLE",
			ch_xcvrif_l_tx_dl_enable_atom                      => "TX_DL_ENABLE_DISABLE",
			ch_xcvrif_l_rx_dl_enable_atom                      => "RX_DL_ENABLE_DISABLE",
			ch_xcvrif_l_tx_fifo_mode_atom                      => "TX_FIFO_MODE_DISABLED",
			ch_xcvrif_l_rx_fifo_mode_atom                      => "RX_FIFO_MODE_DISABLED",
			ch_l_xcvr_tx_en_atom                               => "TRUE",
			ch_l_xcvr_rx_en_atom                               => "TRUE",
			ch_l_duplex_mode_atom                              => "DUPLEX_MODE_DUPLEX",
			ch_xcvrif_l_tx_en_atom                             => "FALSE",
			ch_xcvrif_l_rx_en_atom                             => "FALSE",
			ch_xcvrif_l_duplex_mode_atom                       => "DUPLEX_MODE_DUPLEX",
			ch_flux_l_rx_fec_type_used_atom                    => "RX_FEC_TYPE_USED_NONE",
			ch_l_sim_mode_atom                                 => "SIM_MODE_DISABLE",
			ch_flux_l_rx_sim_mode_atom                         => "RX_SIM_MODE_DISABLE",
			ch_flux_l_tx_sim_mode_atom                         => "TX_SIM_MODE_DISABLE",
			ch_flux_l_dr_enabled_atom                          => "DR_ENABLED_DR_DISABLED",
			ch_xcvrif_l_sup_mode_atom                          => "SUP_MODE_USER_MODE",
			ch_xcvrif_l_sim_mode_atom                          => "SIM_MODE_ENABLE",
			ch_xcvrif_l_dr_enabled_atom                        => "DR_ENABLED_DR_DISABLED",
			ch_l_xcvr_tx_spread_spectrum_en_atom               => "TX_SPREAD_SPECTRUM_EN_ENABLE",
			ch_l_rx_postdiv_clk_hz_atom                        => "000000000000000000000000000000000000",
			ch_l_rx_postdiv_clk_fractional_en_atom             => "RX_POSTDIV_CLK_FRACTIONAL_EN_DISABLE",
			ch_l_cdr_refclk_select_atom                        => "CDR_REFCLK_SELECT_GLOBAL_REFCLK0",
			ch_l_tx_postdiv_clk_hz_atom                        => "000000000000000000000000000000000000",
			ch_l_tx_postdiv_clk_fractional_en_atom             => "TX_POSTDIV_CLK_FRACTIONAL_EN_DISABLE",
			ch_flux_l_lc_postdiv_sel_atom                      => "LC_POSTDIV_SEL_SYNTH2",
			ch_flux_l_tx_user1_clk_mux_dynamic_sel_atom        => "TX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK",
			ch_flux_l_tx_user2_clk_mux_dynamic_sel_atom        => "TX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_TXWORD_CLK",
			ch_flux_l_rx_user1_clk_mux_dynamic_sel_atom        => "RX_USER1_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD",
			ch_flux_l_rx_user2_clk_mux_dynamic_sel_atom        => "RX_USER2_CLK_MUX_DYNAMIC_SEL_OCK_PCS_RXWORD",
			ch_xcvrif_l_tx_gb_width_atom                       => "TX_GB_WIDTH_DISABLED",
			ch_xcvrif_l_rx_gb_width_atom                       => "RX_GB_WIDTH_DISABLED",
			ch_xcvrif_l_tx_dynamic_mux_atom                    => "TX_DYNAMIC_MUX_UNUSED",
			ch_xcvrif_l_tx_word_clk_dynamic_mux_atom           => "TX_WORD_CLK_DYNAMIC_MUX_X4",
			ch_xcvrif_l_rx_word_clk_dynamic_mux_atom           => "RX_WORD_CLK_DYNAMIC_MUX_UNUSED",
			ch_xcvrif_l_tx_fifo_rd_en_dynamic_mux_atom         => "TX_FIFO_RD_EN_DYNAMIC_MUX_X4",
			ch_xcvrif_l_rx_fifo_rd_en_dynamic_mux_atom         => "RX_FIFO_RD_EN_DYNAMIC_MUX_UNUSED",
			ch_xcvrif_l_tx_rst_dynamic_mux_atom                => "TX_RST_DYNAMIC_MUX_X4",
			ch_l_clk_debug_select_0_enable_atom                => "CLK_DEBUG_SELECT_0_ENABLE_DISABLE",
			ch_l_clk_debug_select_0_setting_atom               => "CLK_DEBUG_SELECT_0_SETTING_DISABLED",
			ch_l_clk_debug_select_1_enable_atom                => "CLK_DEBUG_SELECT_1_ENABLE_DISABLE",
			ch_l_clk_debug_select_1_setting_atom               => "CLK_DEBUG_SELECT_1_SETTING_DISABLED",
			ch_l_xcvr_tx_eq_main_tap_atom                      => "000000",
			ch_l_xcvr_tx_eq_post_tap_1_atom                    => "00000",
			ch_l_xcvr_tx_eq_pre_tap_1_atom                     => "00000",
			ch_l_xcvr_tx_eq_pre_tap_2_atom                     => "000",
			ch_l_tx_pll_feed_forward_gain_atom                 => "01000011",
			ch_l_xcvr_rx_termination_mode_atom                 => "RX_TERMINATION_MODE_GROUNDED",
			ch_l_xcvr_rx_onchip_termination_setting_atom       => "RX_ONCHIP_TERMINATION_SETTING_R_1",
			ch_l_xcvr_rx_eq_vga_gain_atom                      => "0100000",
			ch_l_xcvr_x_eq_hf_boost_atom                       => "100000",
			ch_l_xcvr_rx_eq_dfe_tap_1_atom                     => "000000",
			ch_l_xcvr_rx_external_couple_type_atom             => "RX_EXTERNAL_COUPLE_TYPE_AC",
			ch_l_xcvr_tx_bonding_category_atom                 => "TX_BONDING_CATEGORY_BONDING_FOLLOWER",
			ch_l_xcvr_tx_master_pll_mode_atom                  => "TX_MASTER_PLL_MODE_DISABLED",
			ch_l_xcvr_rx_cdrdivout_en_atom                     => "RX_CDRDIVOUT_EN_DISABLE",
			ch_xcvrif_l_tx_bonding_mode_atom                   => "TX_BONDING_MODE_UNUSED",
			ch_xcvrif_l_rx_bonding_mode_atom                   => "RX_BONDING_MODE_UNUSED",
			ch_flux_l_sequencer_reg_en_atom                    => "SEQUENCER_REG_EN_DISABLE",
			ch_l_speed_grade_atom                              => "SPEED_GRADE_DASH_1",
			ch_usb_mode_atom                                   => "USB_MODE_DISABLED",
			ch_pcie_mode_atom                                  => "PCIE_MODE_GEN3",
			ch_l_ick_tx_word_clk_hz_atom                       => "100101011100000111110010100001110010",
			ch_l_pcs_ref_clk_hz_atom                           => "101001111010110110010111101111110101",
			ch_l_lane_common_ref_clk_hz_atom                   => "111110010011110101111111101000101001",
			ch_rx_invert_pin_atom                              => "RX_INVERT_PIN_DISABLE",
			ch_tx_invert_pin_atom                              => "TX_INVERT_PIN_DISABLE",
			ch_vsr_mode_atom                                   => "VSR_MODE_DISABLED",
			ch_rx_dl_rx_lat_bit_for_async_atom                 => "111110100110100101",
			ch_rx_dl_rxbit_cntr_pma_atom                       => "RX_DL_RXBIT_CNTR_PMA_DISABLE",
			ch_rx_dl_rxbit_rollover_atom                       => "001001111001000101",
			ch_eth_rx_clk_hz_atom                              => "000000000000000000000000000000000000",
			ch_eth_tx_clk_hz_atom                              => "000000000000000000000000000000000000"
		)
		port map (
			oflux_xoa_tx_n_l0_ux              => oflux_xoa_tx_n_l0_ux,              --              oflux_xoa_tx_n_l0_ux.data
			oflux_xoa_tx_p_l0_ux              => oflux_xoa_tx_p_l0_ux,              --              oflux_xoa_tx_p_l0_ux.data
			iflux_xia_rx_n_l0_ux              => iflux_xia_rx_n_l0_ux,              --              iflux_xia_rx_n_l0_ux.data
			iflux_xia_rx_p_l0_ux              => iflux_xia_rx_p_l0_ux,              --              iflux_xia_rx_p_l0_ux.data
			i_ss_async_pldif                  => i_ss_async_pldif,                  --                       asyncdata_0.data
			o_ss_async_pldif                  => o_ss_async_pldif,                  --                       asyncdata_1.data
			i_ss_async_pldif_pcie_mux         => i_ss_async_pldif_pcie_mux,         --                       asyncdata_2.data
			i_lavmm_addr                      => i_lavmm_addr,                      --                          reconfig.address
			i_lavmm_be                        => i_lavmm_be,                        --                                  .byteenable
			i_lavmm_read                      => i_lavmm_read,                      --                                  .read
			i_lavmm_wdata                     => i_lavmm_wdata,                     --                                  .writedata
			i_lavmm_write                     => i_lavmm_write,                     --                                  .write
			o_lavmm_rdata                     => o_lavmm_rdata,                     --                                  .readdata
			o_lavmm_rdata_valid               => o_lavmm_rdata_valid,               --                                  .readdatavalid
			o_lavmm_waitreq                   => o_lavmm_waitreq,                   --                                  .waitrequest
			i_lavmm_clk                       => i_lavmm_clk,                       --                      reconfig_clk.clk
			i_lavmm_rstn                      => i_lavmm_rstn,                      --                      reconfig_rst.reset
			i_ft_rx_sclk_sync_ch              => i_ft_rx_sclk_sync_ch,              --              i_ft_rx_sclk_sync_ch.clk
			i_ft_tx_sclk_sync_ch              => i_ft_tx_sclk_sync_ch,              --              i_ft_tx_sclk_sync_ch.clk
			o_ft_rx_async_pulse_ch            => o_ft_rx_async_pulse_ch,            --            o_ft_rx_async_pulse_ch.clk
			o_ft_tx_async_pulse_ch            => o_ft_tx_async_pulse_ch,            --            o_ft_tx_async_pulse_ch.clk
			o_rxcdrlock2dataa                 => o_rxcdrlock2dataa,                 --                 o_rxcdrlock2dataa.lockdata
			i_rst_ux_rx_sfrz                  => i_rst_ux_rx_sfrz,                  --                  i_rst_ux_rx_sfrz.data
			o_rst_flux0_cpi_cmn_busy          => o_rst_flux0_cpi_cmn_busy,          --          o_rst_flux0_cpi_cmn_busy.busy
			o_rst_oflux_rx_srds_rdy           => o_rst_oflux_rx_srds_rdy,           --           o_rst_oflux_rx_srds_rdy.ready
			o_rst_ux_all_synthlockstatus      => o_rst_ux_all_synthlockstatus,      --      o_rst_ux_all_synthlockstatus.status
			o_rst_ux_rxcdrlockstatus          => o_rst_ux_rxcdrlockstatus,          --          o_rst_ux_rxcdrlockstatus.rxstatus
			i_ick_sclk_tx                     => i_ick_sclk_tx,                     --                     i_ick_sclk_tx.clk
			i_ick_sclk_rx                     => i_ick_sclk_rx,                     --                     i_ick_sclk_rx.clk
			i_rst_pld_ux_tx_pma_rst_n         => i_rst_pld_ux_tx_pma_rst_n,         --         i_rst_pld_ux_tx_pma_rst_n.reset
			i_rst_pld_ux_rx_pma_rst_n         => i_rst_pld_ux_rx_pma_rst_n,         --         i_rst_pld_ux_rx_pma_rst_n.reset
			o_ch_lavmm_xcvrif_rdata           => o_ch_lavmm_xcvrif_rdata,           --                     reconfig_xcvr.readdata
			o_ch_lavmm_xcvrif_rdata_valid     => o_ch_lavmm_xcvrif_rdata_valid,     --                                  .readdatavalid
			o_ch_lavmm_xcvrif_waitreq         => o_ch_lavmm_xcvrif_waitreq,         --                                  .waitrequest
			i_ch_lavmm_xcvrif_addr            => i_ch_lavmm_xcvrif_addr,            --                                  .address
			i_ch_lavmm_xcvrif_be              => i_ch_lavmm_xcvrif_be,              --                                  .byteenable
			i_ch_lavmm_xcvrif_read            => i_ch_lavmm_xcvrif_read,            --                                  .read
			i_ch_lavmm_xcvrif_wdata           => i_ch_lavmm_xcvrif_wdata,           --                                  .writedata
			i_ch_lavmm_xcvrif_write           => i_ch_lavmm_xcvrif_write,           --                                  .write
			i_ch_lavmm_xcvrif_clk             => i_ch_lavmm_xcvrif_clk,             --                 reconfig_clk_xcvr.clk
			i_ch_lavmm_xcvrif_rstn            => i_ch_lavmm_xcvrif_rstn,            --                 reconfig_rst_xcvr.reset
			o_rx_latency_pulse                => o_rx_latency_pulse,                --                o_rx_latency_pulse.clk
			o_tx_latency_pulse                => o_tx_latency_pulse,                --                o_tx_latency_pulse.clk
			i_ch_eth_xcvrif_tx_async          => i_ch_eth_xcvrif_tx_async,          --                       asyncdata_3.data
			i_ch_eth_xcvrif_tx_direct         => i_ch_eth_xcvrif_tx_direct,         --                       asyncdata_4.data
			o_ch_eth_xcvrif_rx_async          => o_ch_eth_xcvrif_rx_async,          --                       asyncdata_5.data
			o_ch_eth_xcvrif_rx_direct         => o_ch_eth_xcvrif_rx_direct,         --                       asyncdata_6.data
			i_rstxcvrif_xcvrif_signal_ok      => i_rstxcvrif_xcvrif_signal_ok,      --      i_rstxcvrif_xcvrif_signal_ok.data
			i_rstxcvrif_rx_xcvrif_sfrz_n      => i_rstxcvrif_rx_xcvrif_sfrz_n,      --      i_rstxcvrif_rx_xcvrif_sfrz_n.data
			i_rstxcvrif_xcvrif_rx_rst_n       => i_rstxcvrif_xcvrif_rx_rst_n,       --       i_rstxcvrif_xcvrif_rx_rst_n.data
			i_rstxcvrif_tx_xcvrif_sfrz_n      => i_rstxcvrif_tx_xcvrif_sfrz_n,      --      i_rstxcvrif_tx_xcvrif_sfrz_n.data
			i_rstxcvrif_xcvrif_tx_rst_n       => i_rstxcvrif_xcvrif_tx_rst_n,       --       i_rstxcvrif_xcvrif_tx_rst_n.data
			o_pma_rx_sf                       => o_pma_rx_sf,                       --                       o_pma_rx_sf.data
			i_xcvrif_tx_mux_data              => i_xcvrif_tx_mux_data,              --              i_xcvrif_tx_mux_data.data
			o_rx_data                         => o_rx_data,                         --                         o_rx_data.data
			o_tx_source_sel                   => o_tx_source_sel,                   --                   o_tx_source_sel.data
			o_rx_fifo_en_sel                  => o_rx_fifo_en_sel,                  --                  o_rx_fifo_en_sel.data
			o_tx_rst_source_sel               => o_tx_rst_source_sel,               --               o_tx_rst_source_sel.data
			i_ch_xcvrif_rx_fifo_rd_en         => i_ch_xcvrif_rx_fifo_rd_en,         --         i_ch_xcvrif_rx_fifo_rd_en.data
			o_ch_xcvrif_rx_fifo_rd_en         => o_ch_xcvrif_rx_fifo_rd_en,         --         o_ch_xcvrif_rx_fifo_rd_en.data
			i_ch_xcvrif_tx_fifo_rd_en         => i_ch_xcvrif_tx_fifo_rd_en,         --         i_ch_xcvrif_tx_fifo_rd_en.data
			o_ch_xcvrif_tx_fifo_rd_en         => o_ch_xcvrif_tx_fifo_rd_en,         --         o_ch_xcvrif_tx_fifo_rd_en.data
			o_ux_rxuser1_sel                  => o_ux_rxuser1_sel,                  --                  o_ux_rxuser1_sel.data
			o_ux_rxuser2_sel                  => o_ux_rxuser2_sel,                  --                  o_ux_rxuser2_sel.data
			o_ux_txuser1_sel                  => o_ux_txuser1_sel,                  --                  o_ux_txuser1_sel.data
			o_ux_txuser2_sel                  => o_ux_txuser2_sel,                  --                  o_ux_txuser2_sel.data
			o_pcs_rxpostdiv                   => o_pcs_rxpostdiv,                   --                   o_pcs_rxpostdiv.data
			o_pcs_rxword                      => o_pcs_rxword,                      --                      o_pcs_rxword.data
			o_ux_txlc_clk                     => o_ux_txlc_clk,                     --                     o_ux_txlc_clk.clk
			o_tx_xcvr_wordclk_sel             => o_tx_xcvr_wordclk_sel,             --             o_tx_xcvr_wordclk_sel.data
			o_rx_xcvr_wordclk_sel             => o_rx_xcvr_wordclk_sel,             --             o_rx_xcvr_wordclk_sel.data
			i_eth_rx_ch_clk                   => i_eth_rx_ch_clk,                   --                   i_eth_rx_ch_clk.clk
			uxwrap_bus_in                     => uxwrap_bus_in,                     --                     uxwrap_bus_in.data
			uxwrap_bus_out                    => uxwrap_bus_out,                    --                    uxwrap_bus_out.data
			o_lavmm_addr                      => o_lavmm_addr,                      --               reconfig_phy_shared.address
			o_lavmm_be                        => o_lavmm_be,                        --                                  .byteenable
			o_lavmm_read                      => o_lavmm_read,                      --                                  .read
			o_lavmm_wdata                     => o_lavmm_wdata,                     --                                  .writedata
			o_lavmm_write                     => o_lavmm_write,                     --                                  .write
			i_lavmm_rdata                     => i_lavmm_rdata,                     --                                  .readdata
			i_lavmm_rdata_valid               => i_lavmm_rdata_valid,               --                                  .readdatavalid
			i_lavmm_waitreq                   => i_lavmm_waitreq,                   --                                  .waitrequest
			o_lavmm_clk                       => o_lavmm_clk,                       --           reconfig_clk_phy_shared.clk
			o_lavmm_rstn                      => o_lavmm_rstn,                      --           reconfig_rst_phy_shared.reset
			o_sclk_return_sel_rx              => o_sclk_return_sel_rx,              --              o_sclk_return_sel_rx.data
			o_sclk_return_sel_tx              => o_sclk_return_sel_tx,              --              o_sclk_return_sel_tx.data
			o_ick_sclk_rx                     => o_ick_sclk_rx,                     --                     o_ick_sclk_rx.clk
			i_sync_common_control             => i_sync_common_control,             --             i_sync_common_control.data
			o_ft_rx_sclk_sync_ch              => o_ft_rx_sclk_sync_ch,              --              o_ft_rx_sclk_sync_ch.data
			o_ft_tx_sclk_sync_ch              => o_ft_tx_sclk_sync_ch,              --              o_ft_tx_sclk_sync_ch.data
			o_rst_ux_rx_pma_rst_n             => o_rst_ux_rx_pma_rst_n,             --             o_rst_ux_rx_pma_rst_n.reset
			o_rst_ux_tx_pma_rst_n             => o_rst_ux_tx_pma_rst_n,             --             o_rst_ux_tx_pma_rst_n.reset
			o_ick_pcs_txword                  => o_ick_pcs_txword,                  --                  o_ick_pcs_txword.data
			o_tx_dl_ch_bit                    => o_tx_dl_ch_bit,                    --                    o_tx_dl_ch_bit.data
			i_dat_pcs_measlatbit              => i_dat_pcs_measlatbit,              --              i_dat_pcs_measlatbit.data
			i_ft_rx_async_pulse_ch            => i_ft_rx_async_pulse_ch,            --            i_ft_rx_async_pulse_ch.data
			i_ft_tx_async_pulse_ch            => i_ft_tx_async_pulse_ch,            --            i_ft_tx_async_pulse_ch.data
			i_rx_dl_ch_bit                    => i_rx_dl_ch_bit,                    --                    i_rx_dl_ch_bit.data
			i_ux_rxuser1_sel                  => i_ux_rxuser1_sel,                  --                  i_ux_rxuser1_sel.data
			i_ux_rxuser2_sel                  => i_ux_rxuser2_sel,                  --                  i_ux_rxuser2_sel.data
			i_ux_txuser1_sel                  => i_ux_txuser1_sel,                  --                  i_ux_txuser1_sel.data
			i_ux_txuser2_sel                  => i_ux_txuser2_sel,                  --                  i_ux_txuser2_sel.data
			o_octl_pcs_txstatus_a             => o_octl_pcs_txstatus_a,             --             o_octl_pcs_txstatus_a.data
			i_ictl_pcs_txenable_a             => i_ictl_pcs_txenable_a,             --             i_ictl_pcs_txenable_a.data
			i_sync_cfg_data                   => i_sync_cfg_data,                   --                   i_sync_cfg_data.data
			i_sync_interface_control          => i_sync_interface_control,          --          i_sync_interface_control.data
			o_tx_data                         => o_tx_data,                         --                         o_tx_data.data
			i_rx_data                         => i_rx_data,                         --                         i_rx_data.data
			o_sm_flux_ingress                 => o_sm_flux_ingress,                 --                 o_sm_flux_ingress.data
			i_sm_flux_egress                  => i_sm_flux_egress,                  --                  i_sm_flux_egress.data
			i_flux_cpi_int                    => i_flux_cpi_int,                    --                    i_flux_cpi_int.data
			i_flux_int                        => i_flux_int,                        --                        i_flux_int.data
			i_oflux_octl_pcs_txptr_smpl_lane  => i_oflux_octl_pcs_txptr_smpl_lane,  --  i_oflux_octl_pcs_txptr_smpl_lane.data
			o_ick_sclk_tx                     => o_ick_sclk_tx,                     --                     o_ick_sclk_tx.clk
			i_flux_srds_rdy                   => i_flux_srds_rdy,                   --                   i_flux_srds_rdy.data
			i_pcs_rxword                      => i_pcs_rxword,                      --                      i_pcs_rxword.data
			i_pcs_rxpostdiv                   => i_pcs_rxpostdiv,                   --                   i_pcs_rxpostdiv.data
			i_ock_pcs_txword                  => i_ock_pcs_txword,                  --                  i_ock_pcs_txword.data
			o_dat_pcs_measlatrndtripbit       => o_dat_pcs_measlatrndtripbit,       --       o_dat_pcs_measlatrndtripbit.data
			o_ock_pcs_cdrfbclk                => o_ock_pcs_cdrfbclk,                --                o_ock_pcs_cdrfbclk.data
			o_ock_pcs_ref                     => o_ock_pcs_ref,                     --                     o_ock_pcs_ref.data
			o_pcie_pcs                        => o_pcie_pcs,                        --                        o_pcie_pcs.data
			i_pcie_pcs                        => i_pcie_pcs,                        --                        i_pcie_pcs.data
			i_sel_rxword_clk                  => i_sel_rxword_clk,                  --                  i_sel_rxword_clk.clk
			i_xcvr_txword_clk                 => i_xcvr_txword_clk,                 --                 i_xcvr_txword_clk.clk
			o_pcie_rxword_clk                 => o_pcie_rxword_clk,                 --                 o_pcie_rxword_clk.clk
			o_eth_rxword_clk                  => o_eth_rxword_clk,                  --                  o_eth_rxword_clk.clk
			o_pcie_txword_clk                 => o_pcie_txword_clk,                 --                 o_pcie_txword_clk.clk
			o_eth_txword_clk                  => o_eth_txword_clk,                  --                  o_eth_txword_clk.clk
			o_ock_pcs_txword                  => o_ock_pcs_txword,                  --                  o_ock_pcs_txword.clk
			o_eth_rx_ch_clk                   => o_eth_rx_ch_clk,                   --                   o_eth_rx_ch_clk.clk
			o_eth_tx_ch_clk                   => o_eth_tx_ch_clk,                   --                   o_eth_tx_ch_clk.clk
			ioack_ref_left_p_ux_bidir_in      => ioack_ref_left_p_ux_bidir_in,      --      ioack_ref_left_p_ux_bidir_in.data
			ioack_hsref_left_p_ux_bidir_in    => ioack_hsref_left_p_ux_bidir_in,    --    ioack_hsref_left_p_ux_bidir_in.clk
			ioack_cdrdiv_left_ux_bidir_in     => ioack_cdrdiv_left_ux_bidir_in,     --     ioack_cdrdiv_left_ux_bidir_in.clk
			ioack_synthdiv1_left_ux_bidir_in  => ioack_synthdiv1_left_ux_bidir_in,  --  ioack_synthdiv1_left_ux_bidir_in.clk
			ioack_synthdiv2_left_ux_bidir_in  => ioack_synthdiv2_left_ux_bidir_in,  --  ioack_synthdiv2_left_ux_bidir_in.clk
			ioack_cdrdiv_left_ux_bidir_out    => ioack_cdrdiv_left_ux_bidir_out,    --    ioack_cdrdiv_left_ux_bidir_out.clk
			ioack_synthdiv1_left_ux_bidir_out => ioack_synthdiv1_left_ux_bidir_out, -- ioack_synthdiv1_left_ux_bidir_out.clk
			ioack_synthdiv2_left_ux_bidir_out => ioack_synthdiv2_left_ux_bidir_out, -- ioack_synthdiv2_left_ux_bidir_out.clk
			o_rxeq_best_eye_vala              => o_rxeq_best_eye_vala,              --              o_rxeq_best_eye_vala.data
			o_rxeq_donea                      => o_rxeq_donea,                      --                      o_rxeq_donea.data
			o_rxmargin_nacka                  => o_rxmargin_nacka,                  --                  o_rxmargin_nacka.data
			o_rxmargin_statusa                => o_rxmargin_statusa,                --                o_rxmargin_statusa.data
			o_rxsignaldetect_lfpsa            => o_rxsignaldetect_lfpsa,            --            o_rxsignaldetect_lfpsa.data
			o_rxsignaldetecta                 => o_rxsignaldetecta,                 --                 o_rxsignaldetecta.data
			o_rxmargin_status_gray            => o_rxmargin_status_gray,            --            o_rxmargin_status_gray.data
			o_rxstatusa                       => o_rxstatusa,                       --                       o_rxstatusa.data
			o_synthlcfast_postdiv             => o_synthlcfast_postdiv,             --             o_synthlcfast_postdiv.data
			o_synthlcmed_postdiv              => o_synthlcmed_postdiv,              --              o_synthlcmed_postdiv.data
			o_synthlcslow_postdiv             => o_synthlcslow_postdiv,             --             o_synthlcslow_postdiv.data
			o_txdetectrx_acka                 => o_txdetectrx_acka,                 --                 o_txdetectrx_acka.data
			o_txdetectrx_statct               => o_txdetectrx_statct,               --               o_txdetectrx_statct.data
			o_txstatusa                       => o_txstatusa,                       --                       o_txstatusa.data
			i_quartus_flux_s_to_ingress       => i_quartus_flux_s_to_ingress,       --       i_quartus_flux_s_to_ingress.data
			i_pcs_pipe_rstn                   => i_pcs_pipe_rstn,                   --                   i_pcs_pipe_rstn.data
			i_ux_ock_pma_clk                  => i_ux_ock_pma_clk,                  --                  i_ux_ock_pma_clk.data
			i_lfps_ennt                       => i_lfps_ennt,                       --                       i_lfps_ennt.data
			i_pcie_l1ctrla                    => i_pcie_l1ctrla,                    --                    i_pcie_l1ctrla.data
			i_pma_cmn_ctrl                    => i_pma_cmn_ctrl,                    --                    i_pma_cmn_ctrl.data
			i_pma_ctrl                        => i_pma_ctrl,                        --                        i_pma_ctrl.data
			i_pcie_pcs_rx_rst                 => i_pcie_pcs_rx_rst,                 --                 i_pcie_pcs_rx_rst.data
			i_pcie_pcs_tx_rst                 => i_pcie_pcs_tx_rst,                 --                 i_pcie_pcs_tx_rst.data
			i_rxeiosdetectstata               => i_rxeiosdetectstata,               --               i_rxeiosdetectstata.data
			i_rxeq_precal_code_selnt          => i_rxeq_precal_code_selnt,          --          i_rxeq_precal_code_selnt.data
			i_rxeq_starta                     => i_rxeq_starta,                     --                     i_rxeq_starta.data
			i_rxeq_static_ena                 => i_rxeq_static_ena,                 --                 i_rxeq_static_ena.data
			i_rxmargin_direction_nt           => i_rxmargin_direction_nt,           --           i_rxmargin_direction_nt.data
			i_rxmargin_mode_nt                => i_rxmargin_mode_nt,                --                i_rxmargin_mode_nt.data
			i_rxmargin_offset_change_a        => i_rxmargin_offset_change_a,        --        i_rxmargin_offset_change_a.data
			i_rxmargin_offset_nt              => i_rxmargin_offset_nt,              --              i_rxmargin_offset_nt.data
			i_rxmargin_start_a                => i_rxmargin_start_a,                --                i_rxmargin_start_a.data
			i_rxpstate                        => i_rxpstate,                        --                        i_rxpstate.data
			i_rxrate                          => i_rxrate,                          --                          i_rxrate.data
			i_rxterm_hiz_ena                  => i_rxterm_hiz_ena,                  --                  i_rxterm_hiz_ena.data
			i_rxwidth                         => i_rxwidth,                         --                         i_rxwidth.data
			i_tstbus_lane                     => i_tstbus_lane,                     --                     i_tstbus_lane.data
			i_txbeacona                       => i_txbeacona,                       --                       i_txbeacona.data
			i_txclkdivrate                    => i_txclkdivrate,                    --                    i_txclkdivrate.data
			i_txdetectrx_reqa                 => i_txdetectrx_reqa,                 --                 i_txdetectrx_reqa.data
			i_txdrv_levn                      => i_txdrv_levn,                      --                      i_txdrv_levn.data
			i_txdrv_levnm1                    => i_txdrv_levnm1,                    --                    i_txdrv_levnm1.data
			i_txdrv_levnm2                    => i_txdrv_levnm2,                    --                    i_txdrv_levnm2.data
			i_txdrv_levnp1                    => i_txdrv_levnp1,                    --                    i_txdrv_levnp1.data
			i_txdrv_slew                      => i_txdrv_slew,                      --                      i_txdrv_slew.data
			i_txelecidle                      => i_txelecidle,                      --                      i_txelecidle.data
			i_txpstate                        => i_txpstate,                        --                        i_txpstate.data
			i_txrate                          => i_txrate,                          --                          i_txrate.data
			i_txwidth                         => i_txwidth,                         --                         i_txwidth.data
			i_rstxcvrif_xcvrif_tx_rd_rst_n    => i_rstxcvrif_xcvrif_tx_rd_rst_n,    --    i_rstxcvrif_xcvrif_tx_rd_rst_n.data
			i_rstxcvrif_xcvrif_tx_wr_rst_n    => i_rstxcvrif_xcvrif_tx_wr_rst_n,    --    i_rstxcvrif_xcvrif_tx_wr_rst_n.data
			o_tx_rst_rd_sync_rst_n            => o_tx_rst_rd_sync_rst_n,            --            o_tx_rst_rd_sync_rst_n.data
			o_tx_rst_wr_sync_rst_n            => o_tx_rst_wr_sync_rst_n             --            o_tx_rst_wr_sync_rst_n.data
		);

end architecture rtl; -- of gts_axi_streaming_one_lane_pcie_hal_phy_hal_2100_dek3pgy
