-- gts_axi_streaming_one_lane_pcie_hal_pldif_hal_2100_4s3i5ci.vhd

-- Generated using ACDS version 25.1 129

library IEEE;
library pldif_hal_2100;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity gts_axi_streaming_one_lane_pcie_hal_pldif_hal_2100_4s3i5ci is
	generic (
		device_die_type                          : string                        := "MAIN_SM7";
		ch_pldif_l_tx_en_atom                    : string                        := "TRUE";
		ch_pldif_l_rx_en_atom                    : string                        := "TRUE";
		ch_pldif_l_duplex_mode_atom              : string                        := "DUPLEX_MODE_DUPLEX";
		ch_pldif_l_tx_fifo_mode_atom             : string                        := "TX_FIFO_MODE_PHASE_COMP";
		ch_pldif_l_tx_fifo_width_atom            : string                        := "TX_FIFO_WIDTH_DOUBLE_DOUBLE_WIDTH";
		ch_pldif_l_rx_fifo_mode_atom             : string                        := "RX_FIFO_MODE_PHASE_COMP";
		ch_pldif_l_rx_fifo_width_atom            : string                        := "RX_FIFO_WIDTH_DOUBLE_DOUBLE_WIDTH";
		ch_pldif_l_tx_clkout1_divider_atom       : string                        := "TX_CLKOUT1_DIVIDER_DIV1";
		ch_pldif_l_tx_clkout2_divider_atom       : string                        := "TX_CLKOUT2_DIVIDER_DIV1";
		ch_pldif_l_rx_clkout1_divider_atom       : string                        := "RX_CLKOUT1_DIVIDER_DIV1";
		ch_pldif_l_rx_clkout2_divider_atom       : string                        := "RX_CLKOUT2_DIVIDER_DIV1";
		ch_pldif_l_dr_enabled_atom               : string                        := "DR_ENABLED_DR_DISABLED";
		ch_pldif_l_ptp_enable_atom               : string                        := "PTP_ENABLE_DISABLE";
		ch_pldif_l_tx_user1_clk_dynamic_mux_atom : string                        := "TX_USER1_CLK_DYNAMIC_MUX_UX";
		ch_pldif_l_tx_user2_clk_dynamic_mux_atom : string                        := "TX_USER2_CLK_DYNAMIC_MUX_UX";
		ch_pldif_l_rx_user1_clk_dynamic_mux_atom : string                        := "RX_USER1_CLK_DYNAMIC_MUX_UX";
		ch_pldif_l_rx_user2_clk_dynamic_mux_atom : string                        := "RX_USER2_CLK_DYNAMIC_MUX_UX";
		ch_pldif_l_sup_mode_atom                 : string                        := "SUP_MODE_USER_MODE";
		ch_pldif_l_tx_mac_en_atom                : string                        := "FALSE";
		ch_pldif_l_pld_channel_identifier_atom   : string                        := "PLD_CHANNEL_IDENTIFIER_PHIP";
		ch_pldif_rx_fifo_wr_clk_hz_atom          : std_logic_vector(35 downto 0) := "000000011101110011010110010100000000";
		ch_pldif_tx_fifo_rd_clk_hz_atom          : std_logic_vector(35 downto 0) := "000000011101110011010110010100000000";
		ch_pldif_l_rx_dyn_mux_atom               : string                        := "RX_DYN_MUX_XCVRIF";
		ch_pldif_l_tx_bond_location_atom         : string                        := "TX_BOND_LOCATION_MIDDLE";
		ch_pldif_l_rx_bond_location_atom         : string                        := "RX_BOND_LOCATION_UNUSED";
		ch_pldif_l_ehip_lb_tx_rx_atom            : string                        := "EHIP_LB_TX_RX_DISABLE";
		ch_pldif_l_ehip_lb_txmac_rx_atom         : string                        := "EHIP_LB_TXMAC_RX_DISABLE";
		ch_pldif_l_rx_pmadir_singlewidth_en_atom : string                        := "RX_PMADIR_SINGLEWIDTH_EN_DISABLE";
		ch_pldif_l_tx_pmadir_singlewidth_en_atom : string                        := "TX_PMADIR_SINGLEWIDTH_EN_DISABLE";
		ch_pldif_l_ehip_lb_txpcs_rx_atom         : string                        := "EHIP_LB_TXPCS_RX_DISABLE";
		ch_pcs_l_tx_bond_size_atom               : string                        := "TX_BOND_SIZE_X4";
		ch_pcs_l_rx_bond_size_atom               : string                        := "RX_BOND_SIZE_UNUSED";
		ch_vc_rx_pldif_wm_en_atom                : string                        := "VC_RX_PLDIF_WM_EN_DISABLE";
		ch_pldif_l_stmux_tx_demux_sel            : string                        := "SEL_PCIE";
		ch_pldif_l_stmux_rx_fifo_wr_clk_mux_sel  : string                        := "SEL_PCIE";
		ch_pldif_l_stmux_tx_fifo_rd_clk_mux_sel  : string                        := "SEL_PCIE";
		ch_pldif_l_stmux_rx_mux_sel              : string                        := "SEL_PCIE";
		ch_l_xcvr_rx_preloaded_hardware_configs  : string                        := "PCIE_GEN3";
		ch_l_xcvr_tx_preloaded_hardware_configs  : string                        := "PCIE_GEN3"
	);
	port (
		i_hio_txdata                                       : in  std_logic_vector(79 downto 0) := (others => '0'); --                                       i_hio_txdata.data
		i_hio_txdata_extra                                 : in  std_logic_vector(9 downto 0)  := (others => '0'); --                                 i_hio_txdata_extra.data
		i_hio_txdata_fifo_wr_en                            : in  std_logic                     := '0';             --                            i_hio_txdata_fifo_wr_en.fifowriteenable
		o_hio_txdata_fifo_wr_empty                         : out std_logic;                                        --                         o_hio_txdata_fifo_wr_empty.fifowritestatus
		o_hio_txdata_fifo_wr_pempty                        : out std_logic;                                        --                        o_hio_txdata_fifo_wr_pempty.fifowritestatus
		o_hio_txdata_fifo_wr_full                          : out std_logic;                                        --                          o_hio_txdata_fifo_wr_full.fifowritestatus
		o_hio_txdata_fifo_wr_pfull                         : out std_logic;                                        --                         o_hio_txdata_fifo_wr_pfull.fifowritestatus
		o_hio_rxdata                                       : out std_logic_vector(79 downto 0);                    --                                       o_hio_rxdata.data
		o_hio_rxdata_extra                                 : out std_logic_vector(9 downto 0);                     --                                 o_hio_rxdata_extra.data
		o_hio_rxdata_fifo_rd_empty                         : out std_logic;                                        --                         o_hio_rxdata_fifo_rd_empty.fiforeadenable
		o_hio_rxdata_fifo_rd_pempty                        : out std_logic;                                        --                        o_hio_rxdata_fifo_rd_pempty.fiforeadstatus
		o_hio_rxdata_fifo_rd_full                          : out std_logic;                                        --                          o_hio_rxdata_fifo_rd_full.fiforeadstatus
		o_hio_rxdata_fifo_rd_pfull                         : out std_logic;                                        --                         o_hio_rxdata_fifo_rd_pfull.fiforeadstatus
		i_hio_rxdata_fifo_rd_en                            : in  std_logic                     := '0';             --                            i_hio_rxdata_fifo_rd_en.fiforeadstatus
		i_hio_ptp_rst_n                                    : in  std_logic                     := '0';             --                                    i_hio_ptp_rst_n.data
		i_hio_ehip_rx_rst_n                                : in  std_logic                     := '0';             --                                i_hio_ehip_rx_rst_n.data
		i_hio_ehip_tx_rst_n                                : in  std_logic                     := '0';             --                                i_hio_ehip_tx_rst_n.data
		i_hio_ehip_signal_ok                               : in  std_logic                     := '0';             --                               i_hio_ehip_signal_ok.data
		i_hio_sfreeze_2_r03f_rx_mac_srfz_n                 : in  std_logic                     := '0';             --                 i_hio_sfreeze_2_r03f_rx_mac_srfz_n.data
		i_hio_sfreeze_3_c2f_tx_deskew_srfz_n               : in  std_logic                     := '0';             --               i_hio_sfreeze_3_c2f_tx_deskew_srfz_n.data
		i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n                 : in  std_logic                     := '0';             --                 i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n.data
		o_hio_rstepcs_rx_pcs_fully_aligned                 : out std_logic;                                        --                 o_hio_rstepcs_rx_pcs_fully_aligned.status
		i_hio_rstfec_fec_rx_rst_n                          : in  std_logic                     := '0';             --                          i_hio_rstfec_fec_rx_rst_n.data
		i_hio_rstfec_fec_tx_rst_n                          : in  std_logic                     := '0';             --                          i_hio_rstfec_fec_tx_rst_n.data
		i_hio_rstfec_fec_csr_ret                           : in  std_logic                     := '0';             --                           i_hio_rstfec_fec_csr_ret.data
		o_hio_rstfec_fec_rx_rdy_n                          : out std_logic;                                        --                          o_hio_rstfec_fec_rx_rdy_n.status
		i_hio_rstfec_rx_fec_sfrz_n                         : in  std_logic                     := '0';             --                         i_hio_rstfec_rx_fec_sfrz_n.data
		i_hio_rstfec_tx_fec_sfrz_n                         : in  std_logic                     := '0';             --                         i_hio_rstfec_tx_fec_sfrz_n.data
		i_hio_rstxcvrif_xcvrif_rx_rst_n                    : in  std_logic                     := '0';             --                    i_hio_rstxcvrif_xcvrif_rx_rst_n.data
		i_hio_rstxcvrif_xcvrif_tx_rst_n                    : in  std_logic                     := '0';             --                    i_hio_rstxcvrif_xcvrif_tx_rst_n.data
		i_hio_rstxcvrif_xcvrif_signal_ok                   : in  std_logic                     := '0';             --                   i_hio_rstxcvrif_xcvrif_signal_ok.data
		i_hio_rstxcvrif_rx_xcvrif_sfrz_n                   : in  std_logic                     := '0';             --                   i_hio_rstxcvrif_rx_xcvrif_sfrz_n.data
		i_hio_rstxcvrif_tx_xcvrif_sfrz_n                   : in  std_logic                     := '0';             --                   i_hio_rstxcvrif_tx_xcvrif_sfrz_n.data
		i_hio_rst_pld_clrhip                               : in  std_logic                     := '0';             --                               i_hio_rst_pld_clrhip.data
		i_hio_rst_pld_clrpcs                               : in  std_logic                     := '0';             --                               i_hio_rst_pld_clrpcs.data
		i_hio_rst_pld_perstn                               : in  std_logic                     := '0';             --                               i_hio_rst_pld_perstn.data
		i_hio_rst_pld_ready                                : in  std_logic                     := '0';             --                                i_hio_rst_pld_ready.status
		i_hio_rst_pld_adapter_rx_pld_rst_n                 : in  std_logic                     := '0';             --                 i_hio_rst_pld_adapter_rx_pld_rst_n.data
		i_hio_rst_pld_adapter_tx_pld_rst_n                 : in  std_logic                     := '0';             --                 i_hio_rst_pld_adapter_tx_pld_rst_n.data
		i_hio_rst_ux_rx_pma_rst_n                          : in  std_logic                     := '0';             --                          i_hio_rst_ux_rx_pma_rst_n.data
		i_hio_rst_ux_rx_sfrz                               : in  std_logic                     := '0';             --                               i_hio_rst_ux_rx_sfrz.data
		i_hio_rst_ux_tx_pma_rst_n                          : in  std_logic                     := '0';             --                          i_hio_rst_ux_tx_pma_rst_n.data
		o_hio_rst_flux0_cpi_cmn_busy                       : out std_logic;                                        --                       o_hio_rst_flux0_cpi_cmn_busy.status
		o_hio_rst_oflux_rx_srds_rdy                        : out std_logic;                                        --                        o_hio_rst_oflux_rx_srds_rdy.status
		o_hio_rst_ux_all_synthlockstatus                   : out std_logic;                                        --                   o_hio_rst_ux_all_synthlockstatus.status
		o_hio_rst_ux_octl_pcs_rxstatus                     : out std_logic;                                        --                     o_hio_rst_ux_octl_pcs_rxstatus.status
		o_hio_rst_ux_octl_pcs_txstatus                     : out std_logic;                                        --                     o_hio_rst_ux_octl_pcs_txstatus.status
		o_hio_rst_ux_rxcdrlock2data                        : out std_logic;                                        --                        o_hio_rst_ux_rxcdrlock2data.data
		o_hio_rst_ux_rxcdrlockstatus                       : out std_logic;                                        --                       o_hio_rst_ux_rxcdrlockstatus.status
		o_ss_ehip_rx_rst_n                                 : out std_logic;                                        --                                 o_ss_ehip_rx_rst_n.data
		o_ss_ehip_tx_rst_n                                 : out std_logic;                                        --                                 o_ss_ehip_tx_rst_n.data
		o_ss_ehip_signal_ok                                : out std_logic;                                        --                                o_ss_ehip_signal_ok.data
		o_ss_sfreeze_2_r03f_rx_mac_srfz_n                  : out std_logic;                                        --                  o_ss_sfreeze_2_r03f_rx_mac_srfz_n.data
		o_ss_sfreeze_3_c2f_tx_deskew_srfz_n                : out std_logic;                                        --                o_ss_sfreeze_3_c2f_tx_deskew_srfz_n.data
		i_ss_rstepcs_rx_pcs_fully_aligned                  : in  std_logic                     := '0';             --                  i_ss_rstepcs_rx_pcs_fully_aligned.status
		o_ss_t03f_sfreeze_1_tx_pcs_sfrz_n                  : out std_logic;                                        --                  o_ss_t03f_sfreeze_1_tx_pcs_sfrz_n.data
		o_ss_rstfec_fec_rx_rst_n                           : out std_logic;                                        --                           o_ss_rstfec_fec_rx_rst_n.data
		o_ss_rstfec_fec_tx_rst_n                           : out std_logic;                                        --                           o_ss_rstfec_fec_tx_rst_n.data
		o_ss_rstfec_fec_csr_ret                            : out std_logic;                                        --                            o_ss_rstfec_fec_csr_ret.data
		i_ss_rstfec_fec_rx_rdy_n                           : in  std_logic                     := '0';             --                           i_ss_rstfec_fec_rx_rdy_n.status
		o_ss_rstfec_rx_fec_sfrz_n                          : out std_logic;                                        --                          o_ss_rstfec_rx_fec_sfrz_n.data
		o_ss_rstfec_tx_fec_sfrz_n                          : out std_logic;                                        --                          o_ss_rstfec_tx_fec_sfrz_n.data
		o_ss_rstxcvrif_xcvrif_rx_rst_n                     : out std_logic;                                        --                     o_ss_rstxcvrif_xcvrif_rx_rst_n.data
		o_ss_rstxcvrif_xcvrif_tx_rst_n                     : out std_logic;                                        --                     o_ss_rstxcvrif_xcvrif_tx_rst_n.data
		o_ss_rstxcvrif_xcvrif_signal_ok                    : out std_logic;                                        --                    o_ss_rstxcvrif_xcvrif_signal_ok.data
		o_ss_rstxcvrif_rx_xcvrif_sfrz_n                    : out std_logic;                                        --                    o_ss_rstxcvrif_rx_xcvrif_sfrz_n.data
		o_ss_rstxcvrif_tx_xcvrif_sfrz_n                    : out std_logic;                                        --                    o_ss_rstxcvrif_tx_xcvrif_sfrz_n.data
		o_ss_rst_ux_rx_pma_rst_n                           : out std_logic;                                        --                           o_ss_rst_ux_rx_pma_rst_n.data
		o_ss_rst_ux_rx_sfrz                                : out std_logic;                                        --                                o_ss_rst_ux_rx_sfrz.data
		o_ss_rst_ux_tx_pma_rst_n                           : out std_logic;                                        --                           o_ss_rst_ux_tx_pma_rst_n.data
		i_ss_rst_flux0_cpi_cmn_busy                        : in  std_logic                     := '0';             --                        i_ss_rst_flux0_cpi_cmn_busy.status
		i_ss_rst_oflux_rx_srds_rdy                         : in  std_logic                     := '0';             --                         i_ss_rst_oflux_rx_srds_rdy.status
		i_ss_rst_ux_all_synthlockstatus                    : in  std_logic                     := '0';             --                    i_ss_rst_ux_all_synthlockstatus.status
		i_ss_rst_ux_octl_pcs_rxstatus                      : in  std_logic                     := '0';             --                      i_ss_rst_ux_octl_pcs_rxstatus.status
		i_ss_rst_ux_octl_pcs_txstatus                      : in  std_logic                     := '0';             --                      i_ss_rst_ux_octl_pcs_txstatus.status
		i_ss_rst_ux_rxcdrlock2data                         : in  std_logic                     := '0';             --                         i_ss_rst_ux_rxcdrlock2data.data
		i_ss_rst_ux_rxcdrlockstatus                        : in  std_logic                     := '0';             --                        i_ss_rst_ux_rxcdrlockstatus.status
		i_hio_pld_reset_clk_row                            : in  std_logic                     := '0';             --                            i_hio_pld_reset_clk_row.status
		i_ss_eth_fec_rx_async                              : in  std_logic_vector(11 downto 0) := (others => '0'); --                                        asyncdata_0.data
		i_ss_eth_fec_rx_direct                             : in  std_logic                     := '0';             --                                        asyncdata_1.data
		o_ss_eth_fec_tx_async                              : out std_logic_vector(6 downto 0);                     --                                        asyncdata_2.data
		o_ss_eth_fec_tx_direct                             : out std_logic;                                        --                                        asyncdata_3.data
		i_ss_eth_mac_rx_async                              : in  std_logic_vector(13 downto 0) := (others => '0'); --                                        asyncdata_4.data
		i_ss_eth_mac_rx_direct                             : in  std_logic                     := '0';             --                                        asyncdata_5.data
		o_ss_eth_mac_tx_async                              : out std_logic_vector(13 downto 0);                    --                                        asyncdata_6.data
		o_ss_eth_mac_tx_direct                             : out std_logic;                                        --                                        asyncdata_7.data
		i_ss_eth_pcs_rx_async                              : in  std_logic_vector(13 downto 0) := (others => '0'); --                                        asyncdata_8.data
		i_ss_eth_pcs_rx_direct                             : in  std_logic                     := '0';             --                                        asyncdata_9.data
		o_ss_eth_pcs_tx_async                              : out std_logic_vector(7 downto 0);                     --                                       asyncdata_10.data
		o_ss_eth_pcs_tx_direct                             : out std_logic;                                        --                                       asyncdata_11.data
		i_ss_eth_xcvrif_rx_async                           : in  std_logic_vector(13 downto 0) := (others => '0'); --                                       asyncdata_12.data
		i_ss_eth_xcvrif_rx_direct                          : in  std_logic                     := '0';             --                                       asyncdata_13.data
		o_ss_eth_xcvrif_tx_async                           : out std_logic_vector(6 downto 0);                     --                                       asyncdata_14.data
		o_ss_eth_xcvrif_tx_direct                          : out std_logic;                                        --                                       asyncdata_15.data
		i_ss_pcie_ctrl_rx_async                            : in  std_logic_vector(87 downto 0) := (others => '0'); --                                       asyncdata_16.data
		i_ss_pcie_ctrl_rx_direct                           : in  std_logic_vector(7 downto 0)  := (others => '0'); --                                       asyncdata_17.data
		o_ss_uxquad_async                                  : out std_logic_vector(79 downto 0);                    --                                       asyncdata_20.data
		o_ss_uxquad_async_pcie_mux                         : out std_logic_vector(79 downto 0);                    --                                       asyncdata_21.data
		i_ss_uxquad_async                                  : in  std_logic_vector(49 downto 0) := (others => '0'); --                                       asyncdata_22.data
		i_hio_uxquad_async                                 : in  std_logic_vector(79 downto 0) := (others => '0'); --                                       asyncdata_23.data
		i_hio_uxquad_async_pcie_mux                        : in  std_logic_vector(79 downto 0) := (others => '0'); --                                       asyncdata_24.data
		o_hio_uxquad_async                                 : out std_logic_vector(49 downto 0);                    --                                       asyncdata_25.data
		i_hio_txdata_async                                 : in  std_logic_vector(99 downto 0) := (others => '0'); --                                       asyncdata_26.data
		i_hio_txdata_direct                                : in  std_logic_vector(9 downto 0)  := (others => '0'); --                                       asyncdata_27.data
		o_hio_rxdata_async                                 : out std_logic_vector(99 downto 0);                    --                                       asyncdata_28.data
		o_hio_rxdata_direct                                : out std_logic_vector(9 downto 0);                     --                                       asyncdata_29.data
		o_hio_lavmm_rdata                                  : out std_logic_vector(31 downto 0);                    --                                     reconfig_lavmm.readdata
		o_hio_lavmm_rdata_valid                            : out std_logic;                                        --                                                   .readdatavalid
		o_hio_lavmm_waitreq                                : out std_logic;                                        --                                                   .waitrequest
		i_hio_lavmm_addr                                   : in  std_logic_vector(20 downto 0) := (others => '0'); --                                                   .address
		i_hio_lavmm_be                                     : in  std_logic_vector(3 downto 0)  := (others => '0'); --                                                   .byteenable
		i_hio_lavmm_read                                   : in  std_logic                     := '0';             --                                                   .read
		i_hio_lavmm_wdata                                  : in  std_logic_vector(31 downto 0) := (others => '0'); --                                                   .writedata
		i_hio_lavmm_write                                  : in  std_logic                     := '0';             --                                                   .write
		i_hio_lavmm_clk                                    : in  std_logic                     := '0';             --                                 reconfig_lavmm_clk.clk
		i_hio_lavmm_rstn                                   : in  std_logic                     := '0';             --                                 reconfig_lavmm_rst.reset
		i_ss_lavmm_pcie_rdata                              : in  std_logic_vector(31 downto 0) := (others => '0'); --                                      reconfig_pcie.readdata
		i_ss_lavmm_pcie_rdata_valid                        : in  std_logic                     := '0';             --                                                   .readdatavalid
		i_ss_lavmm_pcie_waitreq                            : in  std_logic                     := '0';             --                                                   .waitrequest
		o_ss_lavmm_pcie_addr                               : out std_logic_vector(16 downto 0);                    --                                                   .address
		o_ss_lavmm_pcie_be                                 : out std_logic_vector(3 downto 0);                     --                                                   .byteenable
		o_ss_lavmm_pcie_read                               : out std_logic;                                        --                                                   .read
		o_ss_lavmm_pcie_wdata                              : out std_logic_vector(31 downto 0);                    --                                                   .writedata
		o_ss_lavmm_pcie_write                              : out std_logic;                                        --                                                   .write
		o_ss_lavmm_pcie_clk                                : out std_logic;                                        --                                  reconfig_pcie_clk.clk
		o_ss_lavmm_pcie_rstn                               : out std_logic;                                        --                                  reconfig_pcie_rst.reset
		o_hio_user_rx_clk1_clk                             : out std_logic;                                        --                             o_hio_user_rx_clk1_clk.clk
		o_hio_user_rx_clk2_clk                             : out std_logic;                                        --                             o_hio_user_rx_clk2_clk.clk
		o_hio_user_tx_clk1_clk                             : out std_logic;                                        --                             o_hio_user_tx_clk1_clk.clk
		o_hio_user_tx_clk2_clk                             : out std_logic;                                        --                             o_hio_user_tx_clk2_clk.clk
		i_ux_chnl_refclk_mux                               : in  std_logic                     := '0';             --                               i_ux_chnl_refclk_mux.clk
		o_hio_ux_chnl_refclk_mux                           : out std_logic;                                        --                           o_hio_ux_chnl_refclk_mux.data
		i_hio_pld_rx_clk_in_row_clk                        : in  std_logic                     := '0';             --                        i_hio_pld_rx_clk_in_row_clk.clk
		i_hio_pld_tx_clk_in_row_clk                        : in  std_logic                     := '0';             --                        i_hio_pld_tx_clk_in_row_clk.clk
		i_hio_det_lat_rx_dl_clk                            : in  std_logic                     := '0';             --                            i_hio_det_lat_rx_dl_clk.clk
		i_hio_det_lat_rx_mux_select                        : in  std_logic                     := '0';             --                        i_hio_det_lat_rx_mux_select.muxsel
		i_hio_det_lat_rx_sclk_flop                         : in  std_logic                     := '0';             --                         i_hio_det_lat_rx_sclk_flop.clk
		i_hio_det_lat_rx_sclk_gen_clk                      : in  std_logic                     := '0';             --                      i_hio_det_lat_rx_sclk_gen_clk.clk
		i_hio_det_lat_rx_trig_flop                         : in  std_logic                     := '0';             --                         i_hio_det_lat_rx_trig_flop.clk
		i_hio_det_lat_sampling_clk                         : in  std_logic                     := '0';             --                         i_hio_det_lat_sampling_clk.clk
		i_hio_det_lat_tx_dl_clk                            : in  std_logic                     := '0';             --                            i_hio_det_lat_tx_dl_clk.clk
		i_hio_det_lat_tx_mux_select                        : in  std_logic                     := '0';             --                        i_hio_det_lat_tx_mux_select.muxsel
		i_hio_det_lat_tx_sclk_flop                         : in  std_logic                     := '0';             --                         i_hio_det_lat_tx_sclk_flop.clk
		i_hio_det_lat_tx_sclk_gen_clk                      : in  std_logic                     := '0';             --                      i_hio_det_lat_tx_sclk_gen_clk.clk
		i_hio_det_lat_tx_trig_flop                         : in  std_logic                     := '0';             --                         i_hio_det_lat_tx_trig_flop.clk
		o_hio_det_lat_rx_async_dl_sync                     : out std_logic;                                        --                     o_hio_det_lat_rx_async_dl_sync.syncsignal
		o_hio_det_lat_rx_async_pulse                       : out std_logic;                                        --                       o_hio_det_lat_rx_async_pulse.syncsignal
		o_hio_det_lat_rx_async_sample_sync                 : out std_logic;                                        --                 o_hio_det_lat_rx_async_sample_sync.syncsignal
		o_hio_det_lat_rx_sclk_sample_sync                  : out std_logic;                                        --                  o_hio_det_lat_rx_sclk_sample_sync.syncsignal
		o_hio_det_lat_rx_trig_sample_sync                  : out std_logic;                                        --                  o_hio_det_lat_rx_trig_sample_sync.syncsignal
		o_hio_det_lat_tx_async_dl_sync                     : out std_logic;                                        --                     o_hio_det_lat_tx_async_dl_sync.syncsignal
		o_hio_det_lat_tx_async_pulse                       : out std_logic;                                        --                       o_hio_det_lat_tx_async_pulse.syncsignal
		o_hio_det_lat_tx_async_sample_sync                 : out std_logic;                                        --                 o_hio_det_lat_tx_async_sample_sync.syncsignal
		o_hio_det_lat_tx_sclk_sample_sync                  : out std_logic;                                        --                  o_hio_det_lat_tx_sclk_sample_sync.syncsignal
		o_hio_det_lat_tx_trig_sample_sync                  : out std_logic;                                        --                  o_hio_det_lat_tx_trig_sample_sync.syncsignal
		o_hio_xcvrif_rx_latency_pulse                      : out std_logic;                                        --                      o_hio_xcvrif_rx_latency_pulse.syncsignal
		o_hio_xcvrif_tx_latency_pulse                      : out std_logic;                                        --                      o_hio_xcvrif_tx_latency_pulse.syncsignal
		o_ss_det_lat_rx_sclk_clk                           : out std_logic;                                        --                           o_ss_det_lat_rx_sclk_clk.clk
		o_ss_det_lat_rx_sclk_sync                          : out std_logic;                                        --                          o_ss_det_lat_rx_sclk_sync.syncsignal
		o_ss_det_lat_tx_sclk_clk                           : out std_logic;                                        --                           o_ss_det_lat_tx_sclk_clk.clk
		o_ss_det_lat_tx_sclk_sync                          : out std_logic;                                        --                          o_ss_det_lat_tx_sclk_sync.syncsignal
		i_ss_det_lat_rx_async_pulse                        : in  std_logic                     := '0';             --                        i_ss_det_lat_rx_async_pulse.syncsignal
		i_ss_det_lat_tx_async_pulse                        : in  std_logic                     := '0';             --                        i_ss_det_lat_tx_async_pulse.syncsignal
		i_ss_xcvrif_rx_latency_pulse                       : in  std_logic                     := '0';             --                       i_ss_xcvrif_rx_latency_pulse.syncsignal
		i_ss_xcvrif_tx_latency_pulse                       : in  std_logic                     := '0';             --                       i_ss_xcvrif_tx_latency_pulse.syncsignal
		i_ux_tx_ch_ptr_smpl                                : in  std_logic                     := '0';             --                                i_ux_tx_ch_ptr_smpl.syncsignal
		o_hio_ux_tx_ch_ptr_smpl                            : out std_logic;                                        --                            o_hio_ux_tx_ch_ptr_smpl.syncsignal
		i_deskew_rx_ch_clk                                 : in  std_logic                     := '0';             --                                 i_deskew_rx_ch_clk.clk
		i_deskew_tx_ch_clk                                 : in  std_logic                     := '0';             --                                 i_deskew_tx_ch_clk.clk
		o_marker_found                                     : out std_logic;                                        --                                     o_marker_found.status
		i_marker_found_up                                  : in  std_logic                     := '0';             --                                  i_marker_found_up.status
		i_marker_found_dn                                  : in  std_logic                     := '0';             --                                  i_marker_found_dn.status
		o_ch_pld_tx_deskewed_data                          : out std_logic_vector(42 downto 0);                    --                          o_ch_pld_tx_deskewed_data.data
		o_ch_ptp_tx_deskewed_data                          : out std_logic_vector(8 downto 0);                     --                          o_ch_ptp_tx_deskewed_data.data
		i_ch_ptp_rx_data                                   : in  std_logic_vector(7 downto 0)  := (others => '0'); --                                   i_ch_ptp_rx_data.data
		i_ch_tx_mac_ready                                  : in  std_logic                     := '0';             --                                  i_ch_tx_mac_ready.status
		i_ch_rx_mac_inframe                                : in  std_logic                     := '0';             --                                i_ch_rx_mac_inframe.status
		o_ch_tx_mac_valid                                  : out std_logic;                                        --                                  o_ch_tx_mac_valid.status
		i_ptp_rx_dsk_marker                                : in  std_logic                     := '0';             --                                i_ptp_rx_dsk_marker.status
		i_ptp_mas_wm                                       : in  std_logic                     := '0';             --                                       i_ptp_mas_wm.status
		i_tx_pcs_data                                      : in  std_logic_vector(42 downto 0) := (others => '0'); --                                      i_tx_pcs_data.data
		i_tx_mac_data                                      : in  std_logic_vector(42 downto 0) := (others => '0'); --                                      i_tx_mac_data.data
		o_lavmm_xcvrif_addr                                : out std_logic_vector(19 downto 0);                    --                                    reconfig_xcvrif.address
		o_lavmm_xcvrif_be                                  : out std_logic_vector(3 downto 0);                     --                                                   .byteenable
		o_lavmm_xcvrif_read                                : out std_logic;                                        --                                                   .read
		o_lavmm_xcvrif_wdata                               : out std_logic_vector(31 downto 0);                    --                                                   .writedata
		o_lavmm_xcvrif_write                               : out std_logic;                                        --                                                   .write
		i_lavmm_xcvrif_rdata                               : in  std_logic_vector(31 downto 0) := (others => '0'); --                                                   .readdata
		i_lavmm_xcvrif_rdata_valid                         : in  std_logic                     := '0';             --                                                   .readdatavalid
		i_lavmm_xcvrif_waitreq                             : in  std_logic                     := '0';             --                                                   .waitrequest
		o_lavmm_xcvrif_clk                                 : out std_logic;                                        --                                reconfig_xcvrif_clk.clk
		o_lavmm_xcvrif_rstn                                : out std_logic;                                        --                                reconfig_xcvrif_rst.reset
		o_lavmm_emac_addr                                  : out std_logic_vector(19 downto 0);                    --                                      reconfig_emac.address
		o_lavmm_emac_be                                    : out std_logic_vector(3 downto 0);                     --                                                   .byteenable
		o_lavmm_emac_read                                  : out std_logic;                                        --                                                   .read
		o_lavmm_emac_wdata                                 : out std_logic_vector(31 downto 0);                    --                                                   .writedata
		o_lavmm_emac_write                                 : out std_logic;                                        --                                                   .write
		i_lavmm_emac_rdata                                 : in  std_logic_vector(31 downto 0) := (others => '0'); --                                                   .readdata
		i_lavmm_emac_rdata_valid                           : in  std_logic                     := '0';             --                                                   .readdatavalid
		i_lavmm_emac_waitreq                               : in  std_logic                     := '0';             --                                                   .waitrequest
		o_lavmm_emac_clk                                   : out std_logic;                                        --                                  reconfig_emac_clk.clk
		o_lavmm_emac_rstn                                  : out std_logic;                                        --                                  reconfig_emac_rst.reset
		o_lavmm_epcs_addr                                  : out std_logic_vector(19 downto 0);                    --                                      reconfig_epcs.address
		o_lavmm_epcs_be                                    : out std_logic_vector(3 downto 0);                     --                                                   .byteenable
		o_lavmm_epcs_read                                  : out std_logic;                                        --                                                   .read
		o_lavmm_epcs_wdata                                 : out std_logic_vector(31 downto 0);                    --                                                   .writedata
		o_lavmm_epcs_write                                 : out std_logic;                                        --                                                   .write
		i_lavmm_epcs_rdata                                 : in  std_logic_vector(31 downto 0) := (others => '0'); --                                                   .readdata
		i_lavmm_epcs_rdata_valid                           : in  std_logic                     := '0';             --                                                   .readdatavalid
		i_lavmm_epcs_waitreq                               : in  std_logic                     := '0';             --                                                   .waitrequest
		o_lavmm_epcs_clk                                   : out std_logic;                                        --                                  reconfig_epcs_clk.clk
		o_lavmm_epcs_rstn                                  : out std_logic;                                        --                                  reconfig_epcs_rst.reset
		o_lavmm_fec_addr                                   : out std_logic_vector(19 downto 0);                    --                                       reconfig_fec.address
		o_lavmm_fec_be                                     : out std_logic_vector(3 downto 0);                     --                                                   .byteenable
		o_lavmm_fec_read                                   : out std_logic;                                        --                                                   .read
		o_lavmm_fec_wdata                                  : out std_logic_vector(31 downto 0);                    --                                                   .writedata
		o_lavmm_fec_write                                  : out std_logic;                                        --                                                   .write
		i_lavmm_fec_rdata                                  : in  std_logic_vector(31 downto 0) := (others => '0'); --                                                   .readdata
		i_lavmm_fec_rdata_valid                            : in  std_logic                     := '0';             --                                                   .readdatavalid
		i_lavmm_fec_waitreq                                : in  std_logic                     := '0';             --                                                   .waitrequest
		o_lavmm_fec_clk                                    : out std_logic;                                        --                                   reconfig_fec_clk.clk
		o_lavmm_fec_rstn                                   : out std_logic;                                        --                                   reconfig_fec_rst.reset
		o_lavmm_ux_addr                                    : out std_logic_vector(19 downto 0);                    --                                        reconfig_ux.address
		o_lavmm_ux_be                                      : out std_logic_vector(3 downto 0);                     --                                                   .byteenable
		o_lavmm_ux_read                                    : out std_logic;                                        --                                                   .read
		o_lavmm_ux_wdata                                   : out std_logic_vector(31 downto 0);                    --                                                   .writedata
		o_lavmm_ux_write                                   : out std_logic;                                        --                                                   .write
		i_lavmm_ux_rdata                                   : in  std_logic_vector(31 downto 0) := (others => '0'); --                                                   .readdata
		i_lavmm_ux_rdata_valid                             : in  std_logic                     := '0';             --                                                   .readdatavalid
		i_lavmm_ux_waitreq                                 : in  std_logic                     := '0';             --                                                   .waitrequest
		o_lavmm_ux_clk                                     : out std_logic;                                        --                                    reconfig_ux_clk.clk
		o_lavmm_ux_rstn                                    : out std_logic;                                        --                                    reconfig_ux_rst.reset
		i_ptp_tx_data                                      : in  std_logic_vector(10 downto 0) := (others => '0'); --                                      i_ptp_tx_data.data
		o_ch_ptp_rx_data                                   : out std_logic_vector(9 downto 0);                     --                                   o_ch_ptp_rx_data.data
		sm_pld_tx_demux_0_o_pcie                           : out std_logic_vector(79 downto 0);                    --                           sm_pld_tx_demux_0_o_pcie.data
		sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_eth_or_ptp : in  std_logic                     := '0';             -- sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_eth_or_ptp.clk
		sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_eth_or_ptp : in  std_logic                     := '0';             -- sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_eth_or_ptp.clk
		sm_pld_rx_mux_0_i_pcie                             : in  std_logic_vector(79 downto 0) := (others => '0'); --                             sm_pld_rx_mux_0_i_pcie.data
		sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_pcie       : in  std_logic                     := '0';             --       sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_pcie.clk
		sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_pcie       : in  std_logic                     := '0';             --       sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_pcie.clk
		sm_pld_rx_mux_0_i_pcie_bond                        : in  std_logic_vector(79 downto 0) := (others => '0'); --                        sm_pld_rx_mux_0_i_pcie_bond.data
		sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_pcie_top   : in  std_logic                     := '0';             --   sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_pcie_top.clk
		sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_pcie_top   : in  std_logic                     := '0';             --   sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_pcie_top.clk
		k_user_rx_clk1_c0c1c2_sel                          : out std_logic_vector(2 downto 0);                     --                          k_user_rx_clk1_c0c1c2_sel.data
		k_user_rx_clk2_c0c1c2_sel                          : out std_logic_vector(2 downto 0);                     --                          k_user_rx_clk2_c0c1c2_sel.data
		k_user_tx_clk1_c0c1c2_sel                          : out std_logic_vector(2 downto 0);                     --                          k_user_tx_clk1_c0c1c2_sel.data
		k_user_tx_clk2_c0c1c2_sel                          : out std_logic_vector(2 downto 0);                     --                          k_user_tx_clk2_c0c1c2_sel.data
		i_ss_user_rx_clk1_clk                              : in  std_logic                     := '0';             --                              i_ss_user_rx_clk1_clk.clk
		i_ss_user_rx_clk2_clk                              : in  std_logic                     := '0';             --                              i_ss_user_rx_clk2_clk.clk
		i_ss_user_tx_clk1_clk                              : in  std_logic                     := '0';             --                              i_ss_user_tx_clk1_clk.clk
		i_ss_user_tx_clk2_clk                              : in  std_logic                     := '0';             --                              i_ss_user_tx_clk2_clk.clk
		i_ch_muxed_rx_data                                 : in  std_logic_vector(42 downto 0) := (others => '0'); --                                 i_ch_muxed_rx_data.data
		o_deskew_rx_source_sel                             : out std_logic_vector(2 downto 0)                      --                             o_deskew_rx_source_sel.data
	);
end entity gts_axi_streaming_one_lane_pcie_hal_pldif_hal_2100_4s3i5ci;

architecture rtl of gts_axi_streaming_one_lane_pcie_hal_pldif_hal_2100_4s3i5ci is
	component gts_axi_streaming_pldif_hal_2100_umi6mva_cmp is
		generic (
			device_die_type                          : string                        := "MAIN_SM7";
			ch_pldif_l_tx_en_atom                    : string                        := "";
			ch_pldif_l_rx_en_atom                    : string                        := "";
			ch_pldif_l_duplex_mode_atom              : string                        := "";
			ch_pldif_l_tx_fifo_mode_atom             : string                        := "";
			ch_pldif_l_tx_fifo_width_atom            : string                        := "";
			ch_pldif_l_rx_fifo_mode_atom             : string                        := "";
			ch_pldif_l_rx_fifo_width_atom            : string                        := "";
			ch_pldif_l_tx_clkout1_divider_atom       : string                        := "";
			ch_pldif_l_tx_clkout2_divider_atom       : string                        := "";
			ch_pldif_l_rx_clkout1_divider_atom       : string                        := "";
			ch_pldif_l_rx_clkout2_divider_atom       : string                        := "";
			ch_pldif_l_dr_enabled_atom               : string                        := "";
			ch_pldif_l_ptp_enable_atom               : string                        := "";
			ch_pldif_l_tx_user1_clk_dynamic_mux_atom : string                        := "";
			ch_pldif_l_tx_user2_clk_dynamic_mux_atom : string                        := "";
			ch_pldif_l_rx_user1_clk_dynamic_mux_atom : string                        := "";
			ch_pldif_l_rx_user2_clk_dynamic_mux_atom : string                        := "";
			ch_pldif_l_sup_mode_atom                 : string                        := "";
			ch_pldif_l_tx_mac_en_atom                : string                        := "";
			ch_pldif_l_pld_channel_identifier_atom   : string                        := "";
			ch_pldif_rx_fifo_wr_clk_hz_atom          : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_pldif_tx_fifo_rd_clk_hz_atom          : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			ch_pldif_l_rx_dyn_mux_atom               : string                        := "RX_DYN_MUX_UNUSED";
			ch_pldif_l_tx_bond_location_atom         : string                        := "TX_BOND_LOCATION_FIRST";
			ch_pldif_l_rx_bond_location_atom         : string                        := "RX_BOND_LOCATION_FIRST";
			ch_pldif_l_ehip_lb_tx_rx_atom            : string                        := "EHIP_LB_TX_RX_ENABLE";
			ch_pldif_l_ehip_lb_txmac_rx_atom         : string                        := "EHIP_LB_TXMAC_RX_ENABLE";
			ch_pldif_l_rx_pmadir_singlewidth_en_atom : string                        := "RX_PMADIR_SINGLEWIDTH_EN_ENABLE";
			ch_pldif_l_tx_pmadir_singlewidth_en_atom : string                        := "TX_PMADIR_SINGLEWIDTH_EN_ENABLE";
			ch_pldif_l_ehip_lb_txpcs_rx_atom         : string                        := "EHIP_LB_TXPCS_RX_ENABLE";
			ch_pcs_l_tx_bond_size_atom               : string                        := "TX_BOND_SIZE_UNUSED";
			ch_pcs_l_rx_bond_size_atom               : string                        := "RX_BOND_SIZE_UNUSED";
			ch_vc_rx_pldif_wm_en_atom                : string                        := "VC_RX_PLDIF_WM_EN_ENABLE";
			ch_pldif_l_stmux_tx_demux_sel            : string                        := "SEL_ETH";
			ch_pldif_l_stmux_rx_fifo_wr_clk_mux_sel  : string                        := "SEL_ETH_OR_PTP";
			ch_pldif_l_stmux_tx_fifo_rd_clk_mux_sel  : string                        := "SEL_ETH_OR_PTP";
			ch_pldif_l_stmux_rx_mux_sel              : string                        := "SEL_ETH";
			ch_l_xcvr_rx_preloaded_hardware_configs  : string                        := "NONE";
			ch_l_xcvr_tx_preloaded_hardware_configs  : string                        := "NONE"
		);
		port (
			i_hio_txdata                                       : in  std_logic_vector(79 downto 0) := (others => 'X'); -- data
			i_hio_txdata_extra                                 : in  std_logic_vector(9 downto 0)  := (others => 'X'); -- data
			i_hio_txdata_fifo_wr_en                            : in  std_logic                     := 'X';             -- fifowriteenable
			o_hio_txdata_fifo_wr_empty                         : out std_logic;                                        -- fifowritestatus
			o_hio_txdata_fifo_wr_pempty                        : out std_logic;                                        -- fifowritestatus
			o_hio_txdata_fifo_wr_full                          : out std_logic;                                        -- fifowritestatus
			o_hio_txdata_fifo_wr_pfull                         : out std_logic;                                        -- fifowritestatus
			o_hio_rxdata                                       : out std_logic_vector(79 downto 0);                    -- data
			o_hio_rxdata_extra                                 : out std_logic_vector(9 downto 0);                     -- data
			o_hio_rxdata_fifo_rd_empty                         : out std_logic;                                        -- fiforeadenable
			o_hio_rxdata_fifo_rd_pempty                        : out std_logic;                                        -- fiforeadstatus
			o_hio_rxdata_fifo_rd_full                          : out std_logic;                                        -- fiforeadstatus
			o_hio_rxdata_fifo_rd_pfull                         : out std_logic;                                        -- fiforeadstatus
			i_hio_rxdata_fifo_rd_en                            : in  std_logic                     := 'X';             -- fiforeadstatus
			i_hio_ptp_rst_n                                    : in  std_logic                     := 'X';             -- data
			i_hio_ehip_rx_rst_n                                : in  std_logic                     := 'X';             -- data
			i_hio_ehip_tx_rst_n                                : in  std_logic                     := 'X';             -- data
			i_hio_ehip_signal_ok                               : in  std_logic                     := 'X';             -- data
			i_hio_sfreeze_2_r03f_rx_mac_srfz_n                 : in  std_logic                     := 'X';             -- data
			i_hio_sfreeze_3_c2f_tx_deskew_srfz_n               : in  std_logic                     := 'X';             -- data
			i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n                 : in  std_logic                     := 'X';             -- data
			o_hio_rstepcs_rx_pcs_fully_aligned                 : out std_logic;                                        -- status
			i_hio_rstfec_fec_rx_rst_n                          : in  std_logic                     := 'X';             -- data
			i_hio_rstfec_fec_tx_rst_n                          : in  std_logic                     := 'X';             -- data
			i_hio_rstfec_fec_csr_ret                           : in  std_logic                     := 'X';             -- data
			o_hio_rstfec_fec_rx_rdy_n                          : out std_logic;                                        -- status
			i_hio_rstfec_rx_fec_sfrz_n                         : in  std_logic                     := 'X';             -- data
			i_hio_rstfec_tx_fec_sfrz_n                         : in  std_logic                     := 'X';             -- data
			i_hio_rstxcvrif_xcvrif_rx_rst_n                    : in  std_logic                     := 'X';             -- data
			i_hio_rstxcvrif_xcvrif_tx_rst_n                    : in  std_logic                     := 'X';             -- data
			i_hio_rstxcvrif_xcvrif_signal_ok                   : in  std_logic                     := 'X';             -- data
			i_hio_rstxcvrif_rx_xcvrif_sfrz_n                   : in  std_logic                     := 'X';             -- data
			i_hio_rstxcvrif_tx_xcvrif_sfrz_n                   : in  std_logic                     := 'X';             -- data
			i_hio_rst_pld_clrhip                               : in  std_logic                     := 'X';             -- data
			i_hio_rst_pld_clrpcs                               : in  std_logic                     := 'X';             -- data
			i_hio_rst_pld_perstn                               : in  std_logic                     := 'X';             -- data
			i_hio_rst_pld_ready                                : in  std_logic                     := 'X';             -- status
			i_hio_rst_pld_adapter_rx_pld_rst_n                 : in  std_logic                     := 'X';             -- data
			i_hio_rst_pld_adapter_tx_pld_rst_n                 : in  std_logic                     := 'X';             -- data
			i_hio_rst_ux_rx_pma_rst_n                          : in  std_logic                     := 'X';             -- data
			i_hio_rst_ux_rx_sfrz                               : in  std_logic                     := 'X';             -- data
			i_hio_rst_ux_tx_pma_rst_n                          : in  std_logic                     := 'X';             -- data
			o_hio_rst_flux0_cpi_cmn_busy                       : out std_logic;                                        -- status
			o_hio_rst_oflux_rx_srds_rdy                        : out std_logic;                                        -- status
			o_hio_rst_ux_all_synthlockstatus                   : out std_logic;                                        -- status
			o_hio_rst_ux_octl_pcs_rxstatus                     : out std_logic;                                        -- status
			o_hio_rst_ux_octl_pcs_txstatus                     : out std_logic;                                        -- status
			o_hio_rst_ux_rxcdrlock2data                        : out std_logic;                                        -- data
			o_hio_rst_ux_rxcdrlockstatus                       : out std_logic;                                        -- status
			o_ss_ehip_rx_rst_n                                 : out std_logic;                                        -- data
			o_ss_ehip_tx_rst_n                                 : out std_logic;                                        -- data
			o_ss_ehip_signal_ok                                : out std_logic;                                        -- data
			o_ss_sfreeze_2_r03f_rx_mac_srfz_n                  : out std_logic;                                        -- data
			o_ss_sfreeze_3_c2f_tx_deskew_srfz_n                : out std_logic;                                        -- data
			i_ss_rstepcs_rx_pcs_fully_aligned                  : in  std_logic                     := 'X';             -- status
			o_ss_t03f_sfreeze_1_tx_pcs_sfrz_n                  : out std_logic;                                        -- data
			o_ss_rstfec_fec_rx_rst_n                           : out std_logic;                                        -- data
			o_ss_rstfec_fec_tx_rst_n                           : out std_logic;                                        -- data
			o_ss_rstfec_fec_csr_ret                            : out std_logic;                                        -- data
			i_ss_rstfec_fec_rx_rdy_n                           : in  std_logic                     := 'X';             -- status
			o_ss_rstfec_rx_fec_sfrz_n                          : out std_logic;                                        -- data
			o_ss_rstfec_tx_fec_sfrz_n                          : out std_logic;                                        -- data
			o_ss_rstxcvrif_xcvrif_rx_rst_n                     : out std_logic;                                        -- data
			o_ss_rstxcvrif_xcvrif_tx_rst_n                     : out std_logic;                                        -- data
			o_ss_rstxcvrif_xcvrif_signal_ok                    : out std_logic;                                        -- data
			o_ss_rstxcvrif_rx_xcvrif_sfrz_n                    : out std_logic;                                        -- data
			o_ss_rstxcvrif_tx_xcvrif_sfrz_n                    : out std_logic;                                        -- data
			o_ss_rst_ux_rx_pma_rst_n                           : out std_logic;                                        -- data
			o_ss_rst_ux_rx_sfrz                                : out std_logic;                                        -- data
			o_ss_rst_ux_tx_pma_rst_n                           : out std_logic;                                        -- data
			i_ss_rst_flux0_cpi_cmn_busy                        : in  std_logic                     := 'X';             -- status
			i_ss_rst_oflux_rx_srds_rdy                         : in  std_logic                     := 'X';             -- status
			i_ss_rst_ux_all_synthlockstatus                    : in  std_logic                     := 'X';             -- status
			i_ss_rst_ux_octl_pcs_rxstatus                      : in  std_logic                     := 'X';             -- status
			i_ss_rst_ux_octl_pcs_txstatus                      : in  std_logic                     := 'X';             -- status
			i_ss_rst_ux_rxcdrlock2data                         : in  std_logic                     := 'X';             -- data
			i_ss_rst_ux_rxcdrlockstatus                        : in  std_logic                     := 'X';             -- status
			i_hio_pld_reset_clk_row                            : in  std_logic                     := 'X';             -- status
			i_ss_eth_fec_rx_async                              : in  std_logic_vector(11 downto 0) := (others => 'X'); -- data
			i_ss_eth_fec_rx_direct                             : in  std_logic                     := 'X';             -- data
			o_ss_eth_fec_tx_async                              : out std_logic_vector(6 downto 0);                     -- data
			o_ss_eth_fec_tx_direct                             : out std_logic;                                        -- data
			i_ss_eth_mac_rx_async                              : in  std_logic_vector(13 downto 0) := (others => 'X'); -- data
			i_ss_eth_mac_rx_direct                             : in  std_logic                     := 'X';             -- data
			o_ss_eth_mac_tx_async                              : out std_logic_vector(13 downto 0);                    -- data
			o_ss_eth_mac_tx_direct                             : out std_logic;                                        -- data
			i_ss_eth_pcs_rx_async                              : in  std_logic_vector(13 downto 0) := (others => 'X'); -- data
			i_ss_eth_pcs_rx_direct                             : in  std_logic                     := 'X';             -- data
			o_ss_eth_pcs_tx_async                              : out std_logic_vector(7 downto 0);                     -- data
			o_ss_eth_pcs_tx_direct                             : out std_logic;                                        -- data
			i_ss_eth_xcvrif_rx_async                           : in  std_logic_vector(13 downto 0) := (others => 'X'); -- data
			i_ss_eth_xcvrif_rx_direct                          : in  std_logic                     := 'X';             -- data
			o_ss_eth_xcvrif_tx_async                           : out std_logic_vector(6 downto 0);                     -- data
			o_ss_eth_xcvrif_tx_direct                          : out std_logic;                                        -- data
			i_ss_pcie_ctrl_rx_async                            : in  std_logic_vector(87 downto 0) := (others => 'X'); -- data
			i_ss_pcie_ctrl_rx_direct                           : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- data
			o_ss_uxquad_async                                  : out std_logic_vector(79 downto 0);                    -- data
			o_ss_uxquad_async_pcie_mux                         : out std_logic_vector(79 downto 0);                    -- data
			i_ss_uxquad_async                                  : in  std_logic_vector(49 downto 0) := (others => 'X'); -- data
			i_hio_uxquad_async                                 : in  std_logic_vector(79 downto 0) := (others => 'X'); -- data
			i_hio_uxquad_async_pcie_mux                        : in  std_logic_vector(79 downto 0) := (others => 'X'); -- data
			o_hio_uxquad_async                                 : out std_logic_vector(49 downto 0);                    -- data
			i_hio_txdata_async                                 : in  std_logic_vector(99 downto 0) := (others => 'X'); -- data
			i_hio_txdata_direct                                : in  std_logic_vector(9 downto 0)  := (others => 'X'); -- data
			o_hio_rxdata_async                                 : out std_logic_vector(99 downto 0);                    -- data
			o_hio_rxdata_direct                                : out std_logic_vector(9 downto 0);                     -- data
			o_hio_lavmm_rdata                                  : out std_logic_vector(31 downto 0);                    -- readdata
			o_hio_lavmm_rdata_valid                            : out std_logic;                                        -- readdatavalid
			o_hio_lavmm_waitreq                                : out std_logic;                                        -- waitrequest
			i_hio_lavmm_addr                                   : in  std_logic_vector(20 downto 0) := (others => 'X'); -- address
			i_hio_lavmm_be                                     : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			i_hio_lavmm_read                                   : in  std_logic                     := 'X';             -- read
			i_hio_lavmm_wdata                                  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			i_hio_lavmm_write                                  : in  std_logic                     := 'X';             -- write
			i_hio_lavmm_clk                                    : in  std_logic                     := 'X';             -- clk
			i_hio_lavmm_rstn                                   : in  std_logic                     := 'X';             -- reset
			i_ss_lavmm_pcie_rdata                              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			i_ss_lavmm_pcie_rdata_valid                        : in  std_logic                     := 'X';             -- readdatavalid
			i_ss_lavmm_pcie_waitreq                            : in  std_logic                     := 'X';             -- waitrequest
			o_ss_lavmm_pcie_addr                               : out std_logic_vector(16 downto 0);                    -- address
			o_ss_lavmm_pcie_be                                 : out std_logic_vector(3 downto 0);                     -- byteenable
			o_ss_lavmm_pcie_read                               : out std_logic;                                        -- read
			o_ss_lavmm_pcie_wdata                              : out std_logic_vector(31 downto 0);                    -- writedata
			o_ss_lavmm_pcie_write                              : out std_logic;                                        -- write
			o_ss_lavmm_pcie_clk                                : out std_logic;                                        -- clk
			o_ss_lavmm_pcie_rstn                               : out std_logic;                                        -- reset
			o_hio_user_rx_clk1_clk                             : out std_logic;                                        -- clk
			o_hio_user_rx_clk2_clk                             : out std_logic;                                        -- clk
			o_hio_user_tx_clk1_clk                             : out std_logic;                                        -- clk
			o_hio_user_tx_clk2_clk                             : out std_logic;                                        -- clk
			i_ux_chnl_refclk_mux                               : in  std_logic                     := 'X';             -- clk
			o_hio_ux_chnl_refclk_mux                           : out std_logic;                                        -- data
			i_hio_pld_rx_clk_in_row_clk                        : in  std_logic                     := 'X';             -- clk
			i_hio_pld_tx_clk_in_row_clk                        : in  std_logic                     := 'X';             -- clk
			i_hio_det_lat_rx_dl_clk                            : in  std_logic                     := 'X';             -- clk
			i_hio_det_lat_rx_mux_select                        : in  std_logic                     := 'X';             -- muxsel
			i_hio_det_lat_rx_sclk_flop                         : in  std_logic                     := 'X';             -- clk
			i_hio_det_lat_rx_sclk_gen_clk                      : in  std_logic                     := 'X';             -- clk
			i_hio_det_lat_rx_trig_flop                         : in  std_logic                     := 'X';             -- clk
			i_hio_det_lat_sampling_clk                         : in  std_logic                     := 'X';             -- clk
			i_hio_det_lat_tx_dl_clk                            : in  std_logic                     := 'X';             -- clk
			i_hio_det_lat_tx_mux_select                        : in  std_logic                     := 'X';             -- muxsel
			i_hio_det_lat_tx_sclk_flop                         : in  std_logic                     := 'X';             -- clk
			i_hio_det_lat_tx_sclk_gen_clk                      : in  std_logic                     := 'X';             -- clk
			i_hio_det_lat_tx_trig_flop                         : in  std_logic                     := 'X';             -- clk
			o_hio_det_lat_rx_async_dl_sync                     : out std_logic;                                        -- syncsignal
			o_hio_det_lat_rx_async_pulse                       : out std_logic;                                        -- syncsignal
			o_hio_det_lat_rx_async_sample_sync                 : out std_logic;                                        -- syncsignal
			o_hio_det_lat_rx_sclk_sample_sync                  : out std_logic;                                        -- syncsignal
			o_hio_det_lat_rx_trig_sample_sync                  : out std_logic;                                        -- syncsignal
			o_hio_det_lat_tx_async_dl_sync                     : out std_logic;                                        -- syncsignal
			o_hio_det_lat_tx_async_pulse                       : out std_logic;                                        -- syncsignal
			o_hio_det_lat_tx_async_sample_sync                 : out std_logic;                                        -- syncsignal
			o_hio_det_lat_tx_sclk_sample_sync                  : out std_logic;                                        -- syncsignal
			o_hio_det_lat_tx_trig_sample_sync                  : out std_logic;                                        -- syncsignal
			o_hio_xcvrif_rx_latency_pulse                      : out std_logic;                                        -- syncsignal
			o_hio_xcvrif_tx_latency_pulse                      : out std_logic;                                        -- syncsignal
			o_ss_det_lat_rx_sclk_clk                           : out std_logic;                                        -- clk
			o_ss_det_lat_rx_sclk_sync                          : out std_logic;                                        -- syncsignal
			o_ss_det_lat_tx_sclk_clk                           : out std_logic;                                        -- clk
			o_ss_det_lat_tx_sclk_sync                          : out std_logic;                                        -- syncsignal
			i_ss_det_lat_rx_async_pulse                        : in  std_logic                     := 'X';             -- syncsignal
			i_ss_det_lat_tx_async_pulse                        : in  std_logic                     := 'X';             -- syncsignal
			i_ss_xcvrif_rx_latency_pulse                       : in  std_logic                     := 'X';             -- syncsignal
			i_ss_xcvrif_tx_latency_pulse                       : in  std_logic                     := 'X';             -- syncsignal
			i_ux_tx_ch_ptr_smpl                                : in  std_logic                     := 'X';             -- syncsignal
			o_hio_ux_tx_ch_ptr_smpl                            : out std_logic;                                        -- syncsignal
			i_deskew_rx_ch_clk                                 : in  std_logic                     := 'X';             -- clk
			i_deskew_tx_ch_clk                                 : in  std_logic                     := 'X';             -- clk
			o_marker_found                                     : out std_logic;                                        -- status
			i_marker_found_up                                  : in  std_logic                     := 'X';             -- status
			i_marker_found_dn                                  : in  std_logic                     := 'X';             -- status
			o_ch_pld_tx_deskewed_data                          : out std_logic_vector(42 downto 0);                    -- data
			o_ch_ptp_tx_deskewed_data                          : out std_logic_vector(8 downto 0);                     -- data
			i_ch_ptp_rx_data                                   : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- data
			i_ch_tx_mac_ready                                  : in  std_logic                     := 'X';             -- status
			i_ch_rx_mac_inframe                                : in  std_logic                     := 'X';             -- status
			o_ch_tx_mac_valid                                  : out std_logic;                                        -- status
			i_ptp_rx_dsk_marker                                : in  std_logic                     := 'X';             -- status
			i_ptp_mas_wm                                       : in  std_logic                     := 'X';             -- status
			i_tx_pcs_data                                      : in  std_logic_vector(42 downto 0) := (others => 'X'); -- data
			i_tx_mac_data                                      : in  std_logic_vector(42 downto 0) := (others => 'X'); -- data
			o_lavmm_xcvrif_addr                                : out std_logic_vector(19 downto 0);                    -- address
			o_lavmm_xcvrif_be                                  : out std_logic_vector(3 downto 0);                     -- byteenable
			o_lavmm_xcvrif_read                                : out std_logic;                                        -- read
			o_lavmm_xcvrif_wdata                               : out std_logic_vector(31 downto 0);                    -- writedata
			o_lavmm_xcvrif_write                               : out std_logic;                                        -- write
			i_lavmm_xcvrif_rdata                               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			i_lavmm_xcvrif_rdata_valid                         : in  std_logic                     := 'X';             -- readdatavalid
			i_lavmm_xcvrif_waitreq                             : in  std_logic                     := 'X';             -- waitrequest
			o_lavmm_xcvrif_clk                                 : out std_logic;                                        -- clk
			o_lavmm_xcvrif_rstn                                : out std_logic;                                        -- reset
			o_lavmm_emac_addr                                  : out std_logic_vector(19 downto 0);                    -- address
			o_lavmm_emac_be                                    : out std_logic_vector(3 downto 0);                     -- byteenable
			o_lavmm_emac_read                                  : out std_logic;                                        -- read
			o_lavmm_emac_wdata                                 : out std_logic_vector(31 downto 0);                    -- writedata
			o_lavmm_emac_write                                 : out std_logic;                                        -- write
			i_lavmm_emac_rdata                                 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			i_lavmm_emac_rdata_valid                           : in  std_logic                     := 'X';             -- readdatavalid
			i_lavmm_emac_waitreq                               : in  std_logic                     := 'X';             -- waitrequest
			o_lavmm_emac_clk                                   : out std_logic;                                        -- clk
			o_lavmm_emac_rstn                                  : out std_logic;                                        -- reset
			o_lavmm_epcs_addr                                  : out std_logic_vector(19 downto 0);                    -- address
			o_lavmm_epcs_be                                    : out std_logic_vector(3 downto 0);                     -- byteenable
			o_lavmm_epcs_read                                  : out std_logic;                                        -- read
			o_lavmm_epcs_wdata                                 : out std_logic_vector(31 downto 0);                    -- writedata
			o_lavmm_epcs_write                                 : out std_logic;                                        -- write
			i_lavmm_epcs_rdata                                 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			i_lavmm_epcs_rdata_valid                           : in  std_logic                     := 'X';             -- readdatavalid
			i_lavmm_epcs_waitreq                               : in  std_logic                     := 'X';             -- waitrequest
			o_lavmm_epcs_clk                                   : out std_logic;                                        -- clk
			o_lavmm_epcs_rstn                                  : out std_logic;                                        -- reset
			o_lavmm_fec_addr                                   : out std_logic_vector(19 downto 0);                    -- address
			o_lavmm_fec_be                                     : out std_logic_vector(3 downto 0);                     -- byteenable
			o_lavmm_fec_read                                   : out std_logic;                                        -- read
			o_lavmm_fec_wdata                                  : out std_logic_vector(31 downto 0);                    -- writedata
			o_lavmm_fec_write                                  : out std_logic;                                        -- write
			i_lavmm_fec_rdata                                  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			i_lavmm_fec_rdata_valid                            : in  std_logic                     := 'X';             -- readdatavalid
			i_lavmm_fec_waitreq                                : in  std_logic                     := 'X';             -- waitrequest
			o_lavmm_fec_clk                                    : out std_logic;                                        -- clk
			o_lavmm_fec_rstn                                   : out std_logic;                                        -- reset
			o_lavmm_ux_addr                                    : out std_logic_vector(19 downto 0);                    -- address
			o_lavmm_ux_be                                      : out std_logic_vector(3 downto 0);                     -- byteenable
			o_lavmm_ux_read                                    : out std_logic;                                        -- read
			o_lavmm_ux_wdata                                   : out std_logic_vector(31 downto 0);                    -- writedata
			o_lavmm_ux_write                                   : out std_logic;                                        -- write
			i_lavmm_ux_rdata                                   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			i_lavmm_ux_rdata_valid                             : in  std_logic                     := 'X';             -- readdatavalid
			i_lavmm_ux_waitreq                                 : in  std_logic                     := 'X';             -- waitrequest
			o_lavmm_ux_clk                                     : out std_logic;                                        -- clk
			o_lavmm_ux_rstn                                    : out std_logic;                                        -- reset
			i_ptp_tx_data                                      : in  std_logic_vector(10 downto 0) := (others => 'X'); -- data
			o_ch_ptp_rx_data                                   : out std_logic_vector(9 downto 0);                     -- data
			sm_pld_tx_demux_0_o_pcie                           : out std_logic_vector(79 downto 0);                    -- data
			sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_eth_or_ptp : in  std_logic                     := 'X';             -- clk
			sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_eth_or_ptp : in  std_logic                     := 'X';             -- clk
			sm_pld_rx_mux_0_i_pcie                             : in  std_logic_vector(79 downto 0) := (others => 'X'); -- data
			sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_pcie       : in  std_logic                     := 'X';             -- clk
			sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_pcie       : in  std_logic                     := 'X';             -- clk
			sm_pld_rx_mux_0_i_pcie_bond                        : in  std_logic_vector(79 downto 0) := (others => 'X'); -- data
			sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_pcie_top   : in  std_logic                     := 'X';             -- clk
			sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_pcie_top   : in  std_logic                     := 'X';             -- clk
			k_user_rx_clk1_c0c1c2_sel                          : out std_logic_vector(2 downto 0);                     -- data
			k_user_rx_clk2_c0c1c2_sel                          : out std_logic_vector(2 downto 0);                     -- data
			k_user_tx_clk1_c0c1c2_sel                          : out std_logic_vector(2 downto 0);                     -- data
			k_user_tx_clk2_c0c1c2_sel                          : out std_logic_vector(2 downto 0);                     -- data
			i_ss_user_rx_clk1_clk                              : in  std_logic                     := 'X';             -- clk
			i_ss_user_rx_clk2_clk                              : in  std_logic                     := 'X';             -- clk
			i_ss_user_tx_clk1_clk                              : in  std_logic                     := 'X';             -- clk
			i_ss_user_tx_clk2_clk                              : in  std_logic                     := 'X';             -- clk
			i_ch_muxed_rx_data                                 : in  std_logic_vector(42 downto 0) := (others => 'X'); -- data
			o_deskew_rx_source_sel                             : out std_logic_vector(2 downto 0)                      -- data
		);
	end component gts_axi_streaming_pldif_hal_2100_umi6mva_cmp;

	for pldif_hal_top : gts_axi_streaming_pldif_hal_2100_umi6mva_cmp
		use entity pldif_hal_2100.gts_axi_streaming_pldif_hal_2100_umi6mva;
begin

	device_die_type_check : if device_die_type /= "MAIN_SM7" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_tx_en_atom_check : if ch_pldif_l_tx_en_atom /= "TRUE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_rx_en_atom_check : if ch_pldif_l_rx_en_atom /= "TRUE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_duplex_mode_atom_check : if ch_pldif_l_duplex_mode_atom /= "DUPLEX_MODE_DUPLEX" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_tx_fifo_mode_atom_check : if ch_pldif_l_tx_fifo_mode_atom /= "TX_FIFO_MODE_PHASE_COMP" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_tx_fifo_width_atom_check : if ch_pldif_l_tx_fifo_width_atom /= "TX_FIFO_WIDTH_DOUBLE_DOUBLE_WIDTH" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_rx_fifo_mode_atom_check : if ch_pldif_l_rx_fifo_mode_atom /= "RX_FIFO_MODE_PHASE_COMP" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_rx_fifo_width_atom_check : if ch_pldif_l_rx_fifo_width_atom /= "RX_FIFO_WIDTH_DOUBLE_DOUBLE_WIDTH" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_tx_clkout1_divider_atom_check : if ch_pldif_l_tx_clkout1_divider_atom /= "TX_CLKOUT1_DIVIDER_DIV1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_tx_clkout2_divider_atom_check : if ch_pldif_l_tx_clkout2_divider_atom /= "TX_CLKOUT2_DIVIDER_DIV1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_rx_clkout1_divider_atom_check : if ch_pldif_l_rx_clkout1_divider_atom /= "RX_CLKOUT1_DIVIDER_DIV1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_rx_clkout2_divider_atom_check : if ch_pldif_l_rx_clkout2_divider_atom /= "RX_CLKOUT2_DIVIDER_DIV1" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_dr_enabled_atom_check : if ch_pldif_l_dr_enabled_atom /= "DR_ENABLED_DR_DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_ptp_enable_atom_check : if ch_pldif_l_ptp_enable_atom /= "PTP_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_tx_user1_clk_dynamic_mux_atom_check : if ch_pldif_l_tx_user1_clk_dynamic_mux_atom /= "TX_USER1_CLK_DYNAMIC_MUX_UX" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_tx_user2_clk_dynamic_mux_atom_check : if ch_pldif_l_tx_user2_clk_dynamic_mux_atom /= "TX_USER2_CLK_DYNAMIC_MUX_UX" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_rx_user1_clk_dynamic_mux_atom_check : if ch_pldif_l_rx_user1_clk_dynamic_mux_atom /= "RX_USER1_CLK_DYNAMIC_MUX_UX" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_rx_user2_clk_dynamic_mux_atom_check : if ch_pldif_l_rx_user2_clk_dynamic_mux_atom /= "RX_USER2_CLK_DYNAMIC_MUX_UX" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_sup_mode_atom_check : if ch_pldif_l_sup_mode_atom /= "SUP_MODE_USER_MODE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_tx_mac_en_atom_check : if ch_pldif_l_tx_mac_en_atom /= "FALSE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_pld_channel_identifier_atom_check : if ch_pldif_l_pld_channel_identifier_atom /= "PLD_CHANNEL_IDENTIFIER_PHIP" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_rx_fifo_wr_clk_hz_atom_check : if ch_pldif_rx_fifo_wr_clk_hz_atom /= "000000011101110011010110010100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_tx_fifo_rd_clk_hz_atom_check : if ch_pldif_tx_fifo_rd_clk_hz_atom /= "000000011101110011010110010100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_rx_dyn_mux_atom_check : if ch_pldif_l_rx_dyn_mux_atom /= "RX_DYN_MUX_XCVRIF" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_tx_bond_location_atom_check : if ch_pldif_l_tx_bond_location_atom /= "TX_BOND_LOCATION_MIDDLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_rx_bond_location_atom_check : if ch_pldif_l_rx_bond_location_atom /= "RX_BOND_LOCATION_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_ehip_lb_tx_rx_atom_check : if ch_pldif_l_ehip_lb_tx_rx_atom /= "EHIP_LB_TX_RX_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_ehip_lb_txmac_rx_atom_check : if ch_pldif_l_ehip_lb_txmac_rx_atom /= "EHIP_LB_TXMAC_RX_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_rx_pmadir_singlewidth_en_atom_check : if ch_pldif_l_rx_pmadir_singlewidth_en_atom /= "RX_PMADIR_SINGLEWIDTH_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_tx_pmadir_singlewidth_en_atom_check : if ch_pldif_l_tx_pmadir_singlewidth_en_atom /= "TX_PMADIR_SINGLEWIDTH_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_ehip_lb_txpcs_rx_atom_check : if ch_pldif_l_ehip_lb_txpcs_rx_atom /= "EHIP_LB_TXPCS_RX_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pcs_l_tx_bond_size_atom_check : if ch_pcs_l_tx_bond_size_atom /= "TX_BOND_SIZE_X4" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pcs_l_rx_bond_size_atom_check : if ch_pcs_l_rx_bond_size_atom /= "RX_BOND_SIZE_UNUSED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_vc_rx_pldif_wm_en_atom_check : if ch_vc_rx_pldif_wm_en_atom /= "VC_RX_PLDIF_WM_EN_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_stmux_tx_demux_sel_check : if ch_pldif_l_stmux_tx_demux_sel /= "SEL_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_stmux_rx_fifo_wr_clk_mux_sel_check : if ch_pldif_l_stmux_rx_fifo_wr_clk_mux_sel /= "SEL_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_stmux_tx_fifo_rd_clk_mux_sel_check : if ch_pldif_l_stmux_tx_fifo_rd_clk_mux_sel /= "SEL_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_l_stmux_rx_mux_sel_check : if ch_pldif_l_stmux_rx_mux_sel /= "SEL_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_rx_preloaded_hardware_configs_check : if ch_l_xcvr_rx_preloaded_hardware_configs /= "PCIE_GEN3" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_l_xcvr_tx_preloaded_hardware_configs_check : if ch_l_xcvr_tx_preloaded_hardware_configs /= "PCIE_GEN3" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pldif_hal_top : component gts_axi_streaming_pldif_hal_2100_umi6mva_cmp
		generic map (
			device_die_type                          => "MAIN_SM7",
			ch_pldif_l_tx_en_atom                    => "TRUE",
			ch_pldif_l_rx_en_atom                    => "TRUE",
			ch_pldif_l_duplex_mode_atom              => "DUPLEX_MODE_DUPLEX",
			ch_pldif_l_tx_fifo_mode_atom             => "TX_FIFO_MODE_PHASE_COMP",
			ch_pldif_l_tx_fifo_width_atom            => "TX_FIFO_WIDTH_DOUBLE_DOUBLE_WIDTH",
			ch_pldif_l_rx_fifo_mode_atom             => "RX_FIFO_MODE_PHASE_COMP",
			ch_pldif_l_rx_fifo_width_atom            => "RX_FIFO_WIDTH_DOUBLE_DOUBLE_WIDTH",
			ch_pldif_l_tx_clkout1_divider_atom       => "TX_CLKOUT1_DIVIDER_DIV1",
			ch_pldif_l_tx_clkout2_divider_atom       => "TX_CLKOUT2_DIVIDER_DIV1",
			ch_pldif_l_rx_clkout1_divider_atom       => "RX_CLKOUT1_DIVIDER_DIV1",
			ch_pldif_l_rx_clkout2_divider_atom       => "RX_CLKOUT2_DIVIDER_DIV1",
			ch_pldif_l_dr_enabled_atom               => "DR_ENABLED_DR_DISABLED",
			ch_pldif_l_ptp_enable_atom               => "PTP_ENABLE_DISABLE",
			ch_pldif_l_tx_user1_clk_dynamic_mux_atom => "TX_USER1_CLK_DYNAMIC_MUX_UX",
			ch_pldif_l_tx_user2_clk_dynamic_mux_atom => "TX_USER2_CLK_DYNAMIC_MUX_UX",
			ch_pldif_l_rx_user1_clk_dynamic_mux_atom => "RX_USER1_CLK_DYNAMIC_MUX_UX",
			ch_pldif_l_rx_user2_clk_dynamic_mux_atom => "RX_USER2_CLK_DYNAMIC_MUX_UX",
			ch_pldif_l_sup_mode_atom                 => "SUP_MODE_USER_MODE",
			ch_pldif_l_tx_mac_en_atom                => "FALSE",
			ch_pldif_l_pld_channel_identifier_atom   => "PLD_CHANNEL_IDENTIFIER_PHIP",
			ch_pldif_rx_fifo_wr_clk_hz_atom          => "000000011101110011010110010100000000",
			ch_pldif_tx_fifo_rd_clk_hz_atom          => "000000011101110011010110010100000000",
			ch_pldif_l_rx_dyn_mux_atom               => "RX_DYN_MUX_XCVRIF",
			ch_pldif_l_tx_bond_location_atom         => "TX_BOND_LOCATION_MIDDLE",
			ch_pldif_l_rx_bond_location_atom         => "RX_BOND_LOCATION_UNUSED",
			ch_pldif_l_ehip_lb_tx_rx_atom            => "EHIP_LB_TX_RX_DISABLE",
			ch_pldif_l_ehip_lb_txmac_rx_atom         => "EHIP_LB_TXMAC_RX_DISABLE",
			ch_pldif_l_rx_pmadir_singlewidth_en_atom => "RX_PMADIR_SINGLEWIDTH_EN_DISABLE",
			ch_pldif_l_tx_pmadir_singlewidth_en_atom => "TX_PMADIR_SINGLEWIDTH_EN_DISABLE",
			ch_pldif_l_ehip_lb_txpcs_rx_atom         => "EHIP_LB_TXPCS_RX_DISABLE",
			ch_pcs_l_tx_bond_size_atom               => "TX_BOND_SIZE_X4",
			ch_pcs_l_rx_bond_size_atom               => "RX_BOND_SIZE_UNUSED",
			ch_vc_rx_pldif_wm_en_atom                => "VC_RX_PLDIF_WM_EN_DISABLE",
			ch_pldif_l_stmux_tx_demux_sel            => "SEL_PCIE",
			ch_pldif_l_stmux_rx_fifo_wr_clk_mux_sel  => "SEL_PCIE",
			ch_pldif_l_stmux_tx_fifo_rd_clk_mux_sel  => "SEL_PCIE",
			ch_pldif_l_stmux_rx_mux_sel              => "SEL_PCIE",
			ch_l_xcvr_rx_preloaded_hardware_configs  => "PCIE_GEN3",
			ch_l_xcvr_tx_preloaded_hardware_configs  => "PCIE_GEN3"
		)
		port map (
			i_hio_txdata                                       => i_hio_txdata,                                       --                                       i_hio_txdata.data
			i_hio_txdata_extra                                 => i_hio_txdata_extra,                                 --                                 i_hio_txdata_extra.data
			i_hio_txdata_fifo_wr_en                            => i_hio_txdata_fifo_wr_en,                            --                            i_hio_txdata_fifo_wr_en.fifowriteenable
			o_hio_txdata_fifo_wr_empty                         => o_hio_txdata_fifo_wr_empty,                         --                         o_hio_txdata_fifo_wr_empty.fifowritestatus
			o_hio_txdata_fifo_wr_pempty                        => o_hio_txdata_fifo_wr_pempty,                        --                        o_hio_txdata_fifo_wr_pempty.fifowritestatus
			o_hio_txdata_fifo_wr_full                          => o_hio_txdata_fifo_wr_full,                          --                          o_hio_txdata_fifo_wr_full.fifowritestatus
			o_hio_txdata_fifo_wr_pfull                         => o_hio_txdata_fifo_wr_pfull,                         --                         o_hio_txdata_fifo_wr_pfull.fifowritestatus
			o_hio_rxdata                                       => o_hio_rxdata,                                       --                                       o_hio_rxdata.data
			o_hio_rxdata_extra                                 => o_hio_rxdata_extra,                                 --                                 o_hio_rxdata_extra.data
			o_hio_rxdata_fifo_rd_empty                         => o_hio_rxdata_fifo_rd_empty,                         --                         o_hio_rxdata_fifo_rd_empty.fiforeadenable
			o_hio_rxdata_fifo_rd_pempty                        => o_hio_rxdata_fifo_rd_pempty,                        --                        o_hio_rxdata_fifo_rd_pempty.fiforeadstatus
			o_hio_rxdata_fifo_rd_full                          => o_hio_rxdata_fifo_rd_full,                          --                          o_hio_rxdata_fifo_rd_full.fiforeadstatus
			o_hio_rxdata_fifo_rd_pfull                         => o_hio_rxdata_fifo_rd_pfull,                         --                         o_hio_rxdata_fifo_rd_pfull.fiforeadstatus
			i_hio_rxdata_fifo_rd_en                            => i_hio_rxdata_fifo_rd_en,                            --                            i_hio_rxdata_fifo_rd_en.fiforeadstatus
			i_hio_ptp_rst_n                                    => i_hio_ptp_rst_n,                                    --                                    i_hio_ptp_rst_n.data
			i_hio_ehip_rx_rst_n                                => i_hio_ehip_rx_rst_n,                                --                                i_hio_ehip_rx_rst_n.data
			i_hio_ehip_tx_rst_n                                => i_hio_ehip_tx_rst_n,                                --                                i_hio_ehip_tx_rst_n.data
			i_hio_ehip_signal_ok                               => i_hio_ehip_signal_ok,                               --                               i_hio_ehip_signal_ok.data
			i_hio_sfreeze_2_r03f_rx_mac_srfz_n                 => i_hio_sfreeze_2_r03f_rx_mac_srfz_n,                 --                 i_hio_sfreeze_2_r03f_rx_mac_srfz_n.data
			i_hio_sfreeze_3_c2f_tx_deskew_srfz_n               => i_hio_sfreeze_3_c2f_tx_deskew_srfz_n,               --               i_hio_sfreeze_3_c2f_tx_deskew_srfz_n.data
			i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n                 => i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n,                 --                 i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n.data
			o_hio_rstepcs_rx_pcs_fully_aligned                 => o_hio_rstepcs_rx_pcs_fully_aligned,                 --                 o_hio_rstepcs_rx_pcs_fully_aligned.status
			i_hio_rstfec_fec_rx_rst_n                          => i_hio_rstfec_fec_rx_rst_n,                          --                          i_hio_rstfec_fec_rx_rst_n.data
			i_hio_rstfec_fec_tx_rst_n                          => i_hio_rstfec_fec_tx_rst_n,                          --                          i_hio_rstfec_fec_tx_rst_n.data
			i_hio_rstfec_fec_csr_ret                           => i_hio_rstfec_fec_csr_ret,                           --                           i_hio_rstfec_fec_csr_ret.data
			o_hio_rstfec_fec_rx_rdy_n                          => o_hio_rstfec_fec_rx_rdy_n,                          --                          o_hio_rstfec_fec_rx_rdy_n.status
			i_hio_rstfec_rx_fec_sfrz_n                         => i_hio_rstfec_rx_fec_sfrz_n,                         --                         i_hio_rstfec_rx_fec_sfrz_n.data
			i_hio_rstfec_tx_fec_sfrz_n                         => i_hio_rstfec_tx_fec_sfrz_n,                         --                         i_hio_rstfec_tx_fec_sfrz_n.data
			i_hio_rstxcvrif_xcvrif_rx_rst_n                    => i_hio_rstxcvrif_xcvrif_rx_rst_n,                    --                    i_hio_rstxcvrif_xcvrif_rx_rst_n.data
			i_hio_rstxcvrif_xcvrif_tx_rst_n                    => i_hio_rstxcvrif_xcvrif_tx_rst_n,                    --                    i_hio_rstxcvrif_xcvrif_tx_rst_n.data
			i_hio_rstxcvrif_xcvrif_signal_ok                   => i_hio_rstxcvrif_xcvrif_signal_ok,                   --                   i_hio_rstxcvrif_xcvrif_signal_ok.data
			i_hio_rstxcvrif_rx_xcvrif_sfrz_n                   => i_hio_rstxcvrif_rx_xcvrif_sfrz_n,                   --                   i_hio_rstxcvrif_rx_xcvrif_sfrz_n.data
			i_hio_rstxcvrif_tx_xcvrif_sfrz_n                   => i_hio_rstxcvrif_tx_xcvrif_sfrz_n,                   --                   i_hio_rstxcvrif_tx_xcvrif_sfrz_n.data
			i_hio_rst_pld_clrhip                               => i_hio_rst_pld_clrhip,                               --                               i_hio_rst_pld_clrhip.data
			i_hio_rst_pld_clrpcs                               => i_hio_rst_pld_clrpcs,                               --                               i_hio_rst_pld_clrpcs.data
			i_hio_rst_pld_perstn                               => i_hio_rst_pld_perstn,                               --                               i_hio_rst_pld_perstn.data
			i_hio_rst_pld_ready                                => i_hio_rst_pld_ready,                                --                                i_hio_rst_pld_ready.status
			i_hio_rst_pld_adapter_rx_pld_rst_n                 => i_hio_rst_pld_adapter_rx_pld_rst_n,                 --                 i_hio_rst_pld_adapter_rx_pld_rst_n.data
			i_hio_rst_pld_adapter_tx_pld_rst_n                 => i_hio_rst_pld_adapter_tx_pld_rst_n,                 --                 i_hio_rst_pld_adapter_tx_pld_rst_n.data
			i_hio_rst_ux_rx_pma_rst_n                          => i_hio_rst_ux_rx_pma_rst_n,                          --                          i_hio_rst_ux_rx_pma_rst_n.data
			i_hio_rst_ux_rx_sfrz                               => i_hio_rst_ux_rx_sfrz,                               --                               i_hio_rst_ux_rx_sfrz.data
			i_hio_rst_ux_tx_pma_rst_n                          => i_hio_rst_ux_tx_pma_rst_n,                          --                          i_hio_rst_ux_tx_pma_rst_n.data
			o_hio_rst_flux0_cpi_cmn_busy                       => o_hio_rst_flux0_cpi_cmn_busy,                       --                       o_hio_rst_flux0_cpi_cmn_busy.status
			o_hio_rst_oflux_rx_srds_rdy                        => o_hio_rst_oflux_rx_srds_rdy,                        --                        o_hio_rst_oflux_rx_srds_rdy.status
			o_hio_rst_ux_all_synthlockstatus                   => o_hio_rst_ux_all_synthlockstatus,                   --                   o_hio_rst_ux_all_synthlockstatus.status
			o_hio_rst_ux_octl_pcs_rxstatus                     => o_hio_rst_ux_octl_pcs_rxstatus,                     --                     o_hio_rst_ux_octl_pcs_rxstatus.status
			o_hio_rst_ux_octl_pcs_txstatus                     => o_hio_rst_ux_octl_pcs_txstatus,                     --                     o_hio_rst_ux_octl_pcs_txstatus.status
			o_hio_rst_ux_rxcdrlock2data                        => o_hio_rst_ux_rxcdrlock2data,                        --                        o_hio_rst_ux_rxcdrlock2data.data
			o_hio_rst_ux_rxcdrlockstatus                       => o_hio_rst_ux_rxcdrlockstatus,                       --                       o_hio_rst_ux_rxcdrlockstatus.status
			o_ss_ehip_rx_rst_n                                 => o_ss_ehip_rx_rst_n,                                 --                                 o_ss_ehip_rx_rst_n.data
			o_ss_ehip_tx_rst_n                                 => o_ss_ehip_tx_rst_n,                                 --                                 o_ss_ehip_tx_rst_n.data
			o_ss_ehip_signal_ok                                => o_ss_ehip_signal_ok,                                --                                o_ss_ehip_signal_ok.data
			o_ss_sfreeze_2_r03f_rx_mac_srfz_n                  => o_ss_sfreeze_2_r03f_rx_mac_srfz_n,                  --                  o_ss_sfreeze_2_r03f_rx_mac_srfz_n.data
			o_ss_sfreeze_3_c2f_tx_deskew_srfz_n                => o_ss_sfreeze_3_c2f_tx_deskew_srfz_n,                --                o_ss_sfreeze_3_c2f_tx_deskew_srfz_n.data
			i_ss_rstepcs_rx_pcs_fully_aligned                  => i_ss_rstepcs_rx_pcs_fully_aligned,                  --                  i_ss_rstepcs_rx_pcs_fully_aligned.status
			o_ss_t03f_sfreeze_1_tx_pcs_sfrz_n                  => o_ss_t03f_sfreeze_1_tx_pcs_sfrz_n,                  --                  o_ss_t03f_sfreeze_1_tx_pcs_sfrz_n.data
			o_ss_rstfec_fec_rx_rst_n                           => o_ss_rstfec_fec_rx_rst_n,                           --                           o_ss_rstfec_fec_rx_rst_n.data
			o_ss_rstfec_fec_tx_rst_n                           => o_ss_rstfec_fec_tx_rst_n,                           --                           o_ss_rstfec_fec_tx_rst_n.data
			o_ss_rstfec_fec_csr_ret                            => o_ss_rstfec_fec_csr_ret,                            --                            o_ss_rstfec_fec_csr_ret.data
			i_ss_rstfec_fec_rx_rdy_n                           => i_ss_rstfec_fec_rx_rdy_n,                           --                           i_ss_rstfec_fec_rx_rdy_n.status
			o_ss_rstfec_rx_fec_sfrz_n                          => o_ss_rstfec_rx_fec_sfrz_n,                          --                          o_ss_rstfec_rx_fec_sfrz_n.data
			o_ss_rstfec_tx_fec_sfrz_n                          => o_ss_rstfec_tx_fec_sfrz_n,                          --                          o_ss_rstfec_tx_fec_sfrz_n.data
			o_ss_rstxcvrif_xcvrif_rx_rst_n                     => o_ss_rstxcvrif_xcvrif_rx_rst_n,                     --                     o_ss_rstxcvrif_xcvrif_rx_rst_n.data
			o_ss_rstxcvrif_xcvrif_tx_rst_n                     => o_ss_rstxcvrif_xcvrif_tx_rst_n,                     --                     o_ss_rstxcvrif_xcvrif_tx_rst_n.data
			o_ss_rstxcvrif_xcvrif_signal_ok                    => o_ss_rstxcvrif_xcvrif_signal_ok,                    --                    o_ss_rstxcvrif_xcvrif_signal_ok.data
			o_ss_rstxcvrif_rx_xcvrif_sfrz_n                    => o_ss_rstxcvrif_rx_xcvrif_sfrz_n,                    --                    o_ss_rstxcvrif_rx_xcvrif_sfrz_n.data
			o_ss_rstxcvrif_tx_xcvrif_sfrz_n                    => o_ss_rstxcvrif_tx_xcvrif_sfrz_n,                    --                    o_ss_rstxcvrif_tx_xcvrif_sfrz_n.data
			o_ss_rst_ux_rx_pma_rst_n                           => o_ss_rst_ux_rx_pma_rst_n,                           --                           o_ss_rst_ux_rx_pma_rst_n.data
			o_ss_rst_ux_rx_sfrz                                => o_ss_rst_ux_rx_sfrz,                                --                                o_ss_rst_ux_rx_sfrz.data
			o_ss_rst_ux_tx_pma_rst_n                           => o_ss_rst_ux_tx_pma_rst_n,                           --                           o_ss_rst_ux_tx_pma_rst_n.data
			i_ss_rst_flux0_cpi_cmn_busy                        => i_ss_rst_flux0_cpi_cmn_busy,                        --                        i_ss_rst_flux0_cpi_cmn_busy.status
			i_ss_rst_oflux_rx_srds_rdy                         => i_ss_rst_oflux_rx_srds_rdy,                         --                         i_ss_rst_oflux_rx_srds_rdy.status
			i_ss_rst_ux_all_synthlockstatus                    => i_ss_rst_ux_all_synthlockstatus,                    --                    i_ss_rst_ux_all_synthlockstatus.status
			i_ss_rst_ux_octl_pcs_rxstatus                      => i_ss_rst_ux_octl_pcs_rxstatus,                      --                      i_ss_rst_ux_octl_pcs_rxstatus.status
			i_ss_rst_ux_octl_pcs_txstatus                      => i_ss_rst_ux_octl_pcs_txstatus,                      --                      i_ss_rst_ux_octl_pcs_txstatus.status
			i_ss_rst_ux_rxcdrlock2data                         => i_ss_rst_ux_rxcdrlock2data,                         --                         i_ss_rst_ux_rxcdrlock2data.data
			i_ss_rst_ux_rxcdrlockstatus                        => i_ss_rst_ux_rxcdrlockstatus,                        --                        i_ss_rst_ux_rxcdrlockstatus.status
			i_hio_pld_reset_clk_row                            => i_hio_pld_reset_clk_row,                            --                            i_hio_pld_reset_clk_row.status
			i_ss_eth_fec_rx_async                              => i_ss_eth_fec_rx_async,                              --                                        asyncdata_0.data
			i_ss_eth_fec_rx_direct                             => i_ss_eth_fec_rx_direct,                             --                                        asyncdata_1.data
			o_ss_eth_fec_tx_async                              => o_ss_eth_fec_tx_async,                              --                                        asyncdata_2.data
			o_ss_eth_fec_tx_direct                             => o_ss_eth_fec_tx_direct,                             --                                        asyncdata_3.data
			i_ss_eth_mac_rx_async                              => i_ss_eth_mac_rx_async,                              --                                        asyncdata_4.data
			i_ss_eth_mac_rx_direct                             => i_ss_eth_mac_rx_direct,                             --                                        asyncdata_5.data
			o_ss_eth_mac_tx_async                              => o_ss_eth_mac_tx_async,                              --                                        asyncdata_6.data
			o_ss_eth_mac_tx_direct                             => o_ss_eth_mac_tx_direct,                             --                                        asyncdata_7.data
			i_ss_eth_pcs_rx_async                              => i_ss_eth_pcs_rx_async,                              --                                        asyncdata_8.data
			i_ss_eth_pcs_rx_direct                             => i_ss_eth_pcs_rx_direct,                             --                                        asyncdata_9.data
			o_ss_eth_pcs_tx_async                              => o_ss_eth_pcs_tx_async,                              --                                       asyncdata_10.data
			o_ss_eth_pcs_tx_direct                             => o_ss_eth_pcs_tx_direct,                             --                                       asyncdata_11.data
			i_ss_eth_xcvrif_rx_async                           => i_ss_eth_xcvrif_rx_async,                           --                                       asyncdata_12.data
			i_ss_eth_xcvrif_rx_direct                          => i_ss_eth_xcvrif_rx_direct,                          --                                       asyncdata_13.data
			o_ss_eth_xcvrif_tx_async                           => o_ss_eth_xcvrif_tx_async,                           --                                       asyncdata_14.data
			o_ss_eth_xcvrif_tx_direct                          => o_ss_eth_xcvrif_tx_direct,                          --                                       asyncdata_15.data
			i_ss_pcie_ctrl_rx_async                            => i_ss_pcie_ctrl_rx_async,                            --                                       asyncdata_16.data
			i_ss_pcie_ctrl_rx_direct                           => i_ss_pcie_ctrl_rx_direct,                           --                                       asyncdata_17.data
			o_ss_uxquad_async                                  => o_ss_uxquad_async,                                  --                                       asyncdata_20.data
			o_ss_uxquad_async_pcie_mux                         => o_ss_uxquad_async_pcie_mux,                         --                                       asyncdata_21.data
			i_ss_uxquad_async                                  => i_ss_uxquad_async,                                  --                                       asyncdata_22.data
			i_hio_uxquad_async                                 => i_hio_uxquad_async,                                 --                                       asyncdata_23.data
			i_hio_uxquad_async_pcie_mux                        => i_hio_uxquad_async_pcie_mux,                        --                                       asyncdata_24.data
			o_hio_uxquad_async                                 => o_hio_uxquad_async,                                 --                                       asyncdata_25.data
			i_hio_txdata_async                                 => i_hio_txdata_async,                                 --                                       asyncdata_26.data
			i_hio_txdata_direct                                => i_hio_txdata_direct,                                --                                       asyncdata_27.data
			o_hio_rxdata_async                                 => o_hio_rxdata_async,                                 --                                       asyncdata_28.data
			o_hio_rxdata_direct                                => o_hio_rxdata_direct,                                --                                       asyncdata_29.data
			o_hio_lavmm_rdata                                  => o_hio_lavmm_rdata,                                  --                                     reconfig_lavmm.readdata
			o_hio_lavmm_rdata_valid                            => o_hio_lavmm_rdata_valid,                            --                                                   .readdatavalid
			o_hio_lavmm_waitreq                                => o_hio_lavmm_waitreq,                                --                                                   .waitrequest
			i_hio_lavmm_addr                                   => i_hio_lavmm_addr,                                   --                                                   .address
			i_hio_lavmm_be                                     => i_hio_lavmm_be,                                     --                                                   .byteenable
			i_hio_lavmm_read                                   => i_hio_lavmm_read,                                   --                                                   .read
			i_hio_lavmm_wdata                                  => i_hio_lavmm_wdata,                                  --                                                   .writedata
			i_hio_lavmm_write                                  => i_hio_lavmm_write,                                  --                                                   .write
			i_hio_lavmm_clk                                    => i_hio_lavmm_clk,                                    --                                 reconfig_lavmm_clk.clk
			i_hio_lavmm_rstn                                   => i_hio_lavmm_rstn,                                   --                                 reconfig_lavmm_rst.reset
			i_ss_lavmm_pcie_rdata                              => i_ss_lavmm_pcie_rdata,                              --                                      reconfig_pcie.readdata
			i_ss_lavmm_pcie_rdata_valid                        => i_ss_lavmm_pcie_rdata_valid,                        --                                                   .readdatavalid
			i_ss_lavmm_pcie_waitreq                            => i_ss_lavmm_pcie_waitreq,                            --                                                   .waitrequest
			o_ss_lavmm_pcie_addr                               => o_ss_lavmm_pcie_addr,                               --                                                   .address
			o_ss_lavmm_pcie_be                                 => o_ss_lavmm_pcie_be,                                 --                                                   .byteenable
			o_ss_lavmm_pcie_read                               => o_ss_lavmm_pcie_read,                               --                                                   .read
			o_ss_lavmm_pcie_wdata                              => o_ss_lavmm_pcie_wdata,                              --                                                   .writedata
			o_ss_lavmm_pcie_write                              => o_ss_lavmm_pcie_write,                              --                                                   .write
			o_ss_lavmm_pcie_clk                                => o_ss_lavmm_pcie_clk,                                --                                  reconfig_pcie_clk.clk
			o_ss_lavmm_pcie_rstn                               => o_ss_lavmm_pcie_rstn,                               --                                  reconfig_pcie_rst.reset
			o_hio_user_rx_clk1_clk                             => o_hio_user_rx_clk1_clk,                             --                             o_hio_user_rx_clk1_clk.clk
			o_hio_user_rx_clk2_clk                             => o_hio_user_rx_clk2_clk,                             --                             o_hio_user_rx_clk2_clk.clk
			o_hio_user_tx_clk1_clk                             => o_hio_user_tx_clk1_clk,                             --                             o_hio_user_tx_clk1_clk.clk
			o_hio_user_tx_clk2_clk                             => o_hio_user_tx_clk2_clk,                             --                             o_hio_user_tx_clk2_clk.clk
			i_ux_chnl_refclk_mux                               => i_ux_chnl_refclk_mux,                               --                               i_ux_chnl_refclk_mux.clk
			o_hio_ux_chnl_refclk_mux                           => o_hio_ux_chnl_refclk_mux,                           --                           o_hio_ux_chnl_refclk_mux.data
			i_hio_pld_rx_clk_in_row_clk                        => i_hio_pld_rx_clk_in_row_clk,                        --                        i_hio_pld_rx_clk_in_row_clk.clk
			i_hio_pld_tx_clk_in_row_clk                        => i_hio_pld_tx_clk_in_row_clk,                        --                        i_hio_pld_tx_clk_in_row_clk.clk
			i_hio_det_lat_rx_dl_clk                            => i_hio_det_lat_rx_dl_clk,                            --                            i_hio_det_lat_rx_dl_clk.clk
			i_hio_det_lat_rx_mux_select                        => i_hio_det_lat_rx_mux_select,                        --                        i_hio_det_lat_rx_mux_select.muxsel
			i_hio_det_lat_rx_sclk_flop                         => i_hio_det_lat_rx_sclk_flop,                         --                         i_hio_det_lat_rx_sclk_flop.clk
			i_hio_det_lat_rx_sclk_gen_clk                      => i_hio_det_lat_rx_sclk_gen_clk,                      --                      i_hio_det_lat_rx_sclk_gen_clk.clk
			i_hio_det_lat_rx_trig_flop                         => i_hio_det_lat_rx_trig_flop,                         --                         i_hio_det_lat_rx_trig_flop.clk
			i_hio_det_lat_sampling_clk                         => i_hio_det_lat_sampling_clk,                         --                         i_hio_det_lat_sampling_clk.clk
			i_hio_det_lat_tx_dl_clk                            => i_hio_det_lat_tx_dl_clk,                            --                            i_hio_det_lat_tx_dl_clk.clk
			i_hio_det_lat_tx_mux_select                        => i_hio_det_lat_tx_mux_select,                        --                        i_hio_det_lat_tx_mux_select.muxsel
			i_hio_det_lat_tx_sclk_flop                         => i_hio_det_lat_tx_sclk_flop,                         --                         i_hio_det_lat_tx_sclk_flop.clk
			i_hio_det_lat_tx_sclk_gen_clk                      => i_hio_det_lat_tx_sclk_gen_clk,                      --                      i_hio_det_lat_tx_sclk_gen_clk.clk
			i_hio_det_lat_tx_trig_flop                         => i_hio_det_lat_tx_trig_flop,                         --                         i_hio_det_lat_tx_trig_flop.clk
			o_hio_det_lat_rx_async_dl_sync                     => o_hio_det_lat_rx_async_dl_sync,                     --                     o_hio_det_lat_rx_async_dl_sync.syncsignal
			o_hio_det_lat_rx_async_pulse                       => o_hio_det_lat_rx_async_pulse,                       --                       o_hio_det_lat_rx_async_pulse.syncsignal
			o_hio_det_lat_rx_async_sample_sync                 => o_hio_det_lat_rx_async_sample_sync,                 --                 o_hio_det_lat_rx_async_sample_sync.syncsignal
			o_hio_det_lat_rx_sclk_sample_sync                  => o_hio_det_lat_rx_sclk_sample_sync,                  --                  o_hio_det_lat_rx_sclk_sample_sync.syncsignal
			o_hio_det_lat_rx_trig_sample_sync                  => o_hio_det_lat_rx_trig_sample_sync,                  --                  o_hio_det_lat_rx_trig_sample_sync.syncsignal
			o_hio_det_lat_tx_async_dl_sync                     => o_hio_det_lat_tx_async_dl_sync,                     --                     o_hio_det_lat_tx_async_dl_sync.syncsignal
			o_hio_det_lat_tx_async_pulse                       => o_hio_det_lat_tx_async_pulse,                       --                       o_hio_det_lat_tx_async_pulse.syncsignal
			o_hio_det_lat_tx_async_sample_sync                 => o_hio_det_lat_tx_async_sample_sync,                 --                 o_hio_det_lat_tx_async_sample_sync.syncsignal
			o_hio_det_lat_tx_sclk_sample_sync                  => o_hio_det_lat_tx_sclk_sample_sync,                  --                  o_hio_det_lat_tx_sclk_sample_sync.syncsignal
			o_hio_det_lat_tx_trig_sample_sync                  => o_hio_det_lat_tx_trig_sample_sync,                  --                  o_hio_det_lat_tx_trig_sample_sync.syncsignal
			o_hio_xcvrif_rx_latency_pulse                      => o_hio_xcvrif_rx_latency_pulse,                      --                      o_hio_xcvrif_rx_latency_pulse.syncsignal
			o_hio_xcvrif_tx_latency_pulse                      => o_hio_xcvrif_tx_latency_pulse,                      --                      o_hio_xcvrif_tx_latency_pulse.syncsignal
			o_ss_det_lat_rx_sclk_clk                           => o_ss_det_lat_rx_sclk_clk,                           --                           o_ss_det_lat_rx_sclk_clk.clk
			o_ss_det_lat_rx_sclk_sync                          => o_ss_det_lat_rx_sclk_sync,                          --                          o_ss_det_lat_rx_sclk_sync.syncsignal
			o_ss_det_lat_tx_sclk_clk                           => o_ss_det_lat_tx_sclk_clk,                           --                           o_ss_det_lat_tx_sclk_clk.clk
			o_ss_det_lat_tx_sclk_sync                          => o_ss_det_lat_tx_sclk_sync,                          --                          o_ss_det_lat_tx_sclk_sync.syncsignal
			i_ss_det_lat_rx_async_pulse                        => i_ss_det_lat_rx_async_pulse,                        --                        i_ss_det_lat_rx_async_pulse.syncsignal
			i_ss_det_lat_tx_async_pulse                        => i_ss_det_lat_tx_async_pulse,                        --                        i_ss_det_lat_tx_async_pulse.syncsignal
			i_ss_xcvrif_rx_latency_pulse                       => i_ss_xcvrif_rx_latency_pulse,                       --                       i_ss_xcvrif_rx_latency_pulse.syncsignal
			i_ss_xcvrif_tx_latency_pulse                       => i_ss_xcvrif_tx_latency_pulse,                       --                       i_ss_xcvrif_tx_latency_pulse.syncsignal
			i_ux_tx_ch_ptr_smpl                                => i_ux_tx_ch_ptr_smpl,                                --                                i_ux_tx_ch_ptr_smpl.syncsignal
			o_hio_ux_tx_ch_ptr_smpl                            => o_hio_ux_tx_ch_ptr_smpl,                            --                            o_hio_ux_tx_ch_ptr_smpl.syncsignal
			i_deskew_rx_ch_clk                                 => i_deskew_rx_ch_clk,                                 --                                 i_deskew_rx_ch_clk.clk
			i_deskew_tx_ch_clk                                 => i_deskew_tx_ch_clk,                                 --                                 i_deskew_tx_ch_clk.clk
			o_marker_found                                     => o_marker_found,                                     --                                     o_marker_found.status
			i_marker_found_up                                  => i_marker_found_up,                                  --                                  i_marker_found_up.status
			i_marker_found_dn                                  => i_marker_found_dn,                                  --                                  i_marker_found_dn.status
			o_ch_pld_tx_deskewed_data                          => o_ch_pld_tx_deskewed_data,                          --                          o_ch_pld_tx_deskewed_data.data
			o_ch_ptp_tx_deskewed_data                          => o_ch_ptp_tx_deskewed_data,                          --                          o_ch_ptp_tx_deskewed_data.data
			i_ch_ptp_rx_data                                   => i_ch_ptp_rx_data,                                   --                                   i_ch_ptp_rx_data.data
			i_ch_tx_mac_ready                                  => i_ch_tx_mac_ready,                                  --                                  i_ch_tx_mac_ready.status
			i_ch_rx_mac_inframe                                => i_ch_rx_mac_inframe,                                --                                i_ch_rx_mac_inframe.status
			o_ch_tx_mac_valid                                  => o_ch_tx_mac_valid,                                  --                                  o_ch_tx_mac_valid.status
			i_ptp_rx_dsk_marker                                => i_ptp_rx_dsk_marker,                                --                                i_ptp_rx_dsk_marker.status
			i_ptp_mas_wm                                       => i_ptp_mas_wm,                                       --                                       i_ptp_mas_wm.status
			i_tx_pcs_data                                      => i_tx_pcs_data,                                      --                                      i_tx_pcs_data.data
			i_tx_mac_data                                      => i_tx_mac_data,                                      --                                      i_tx_mac_data.data
			o_lavmm_xcvrif_addr                                => o_lavmm_xcvrif_addr,                                --                                    reconfig_xcvrif.address
			o_lavmm_xcvrif_be                                  => o_lavmm_xcvrif_be,                                  --                                                   .byteenable
			o_lavmm_xcvrif_read                                => o_lavmm_xcvrif_read,                                --                                                   .read
			o_lavmm_xcvrif_wdata                               => o_lavmm_xcvrif_wdata,                               --                                                   .writedata
			o_lavmm_xcvrif_write                               => o_lavmm_xcvrif_write,                               --                                                   .write
			i_lavmm_xcvrif_rdata                               => i_lavmm_xcvrif_rdata,                               --                                                   .readdata
			i_lavmm_xcvrif_rdata_valid                         => i_lavmm_xcvrif_rdata_valid,                         --                                                   .readdatavalid
			i_lavmm_xcvrif_waitreq                             => i_lavmm_xcvrif_waitreq,                             --                                                   .waitrequest
			o_lavmm_xcvrif_clk                                 => o_lavmm_xcvrif_clk,                                 --                                reconfig_xcvrif_clk.clk
			o_lavmm_xcvrif_rstn                                => o_lavmm_xcvrif_rstn,                                --                                reconfig_xcvrif_rst.reset
			o_lavmm_emac_addr                                  => o_lavmm_emac_addr,                                  --                                      reconfig_emac.address
			o_lavmm_emac_be                                    => o_lavmm_emac_be,                                    --                                                   .byteenable
			o_lavmm_emac_read                                  => o_lavmm_emac_read,                                  --                                                   .read
			o_lavmm_emac_wdata                                 => o_lavmm_emac_wdata,                                 --                                                   .writedata
			o_lavmm_emac_write                                 => o_lavmm_emac_write,                                 --                                                   .write
			i_lavmm_emac_rdata                                 => i_lavmm_emac_rdata,                                 --                                                   .readdata
			i_lavmm_emac_rdata_valid                           => i_lavmm_emac_rdata_valid,                           --                                                   .readdatavalid
			i_lavmm_emac_waitreq                               => i_lavmm_emac_waitreq,                               --                                                   .waitrequest
			o_lavmm_emac_clk                                   => o_lavmm_emac_clk,                                   --                                  reconfig_emac_clk.clk
			o_lavmm_emac_rstn                                  => o_lavmm_emac_rstn,                                  --                                  reconfig_emac_rst.reset
			o_lavmm_epcs_addr                                  => o_lavmm_epcs_addr,                                  --                                      reconfig_epcs.address
			o_lavmm_epcs_be                                    => o_lavmm_epcs_be,                                    --                                                   .byteenable
			o_lavmm_epcs_read                                  => o_lavmm_epcs_read,                                  --                                                   .read
			o_lavmm_epcs_wdata                                 => o_lavmm_epcs_wdata,                                 --                                                   .writedata
			o_lavmm_epcs_write                                 => o_lavmm_epcs_write,                                 --                                                   .write
			i_lavmm_epcs_rdata                                 => i_lavmm_epcs_rdata,                                 --                                                   .readdata
			i_lavmm_epcs_rdata_valid                           => i_lavmm_epcs_rdata_valid,                           --                                                   .readdatavalid
			i_lavmm_epcs_waitreq                               => i_lavmm_epcs_waitreq,                               --                                                   .waitrequest
			o_lavmm_epcs_clk                                   => o_lavmm_epcs_clk,                                   --                                  reconfig_epcs_clk.clk
			o_lavmm_epcs_rstn                                  => o_lavmm_epcs_rstn,                                  --                                  reconfig_epcs_rst.reset
			o_lavmm_fec_addr                                   => o_lavmm_fec_addr,                                   --                                       reconfig_fec.address
			o_lavmm_fec_be                                     => o_lavmm_fec_be,                                     --                                                   .byteenable
			o_lavmm_fec_read                                   => o_lavmm_fec_read,                                   --                                                   .read
			o_lavmm_fec_wdata                                  => o_lavmm_fec_wdata,                                  --                                                   .writedata
			o_lavmm_fec_write                                  => o_lavmm_fec_write,                                  --                                                   .write
			i_lavmm_fec_rdata                                  => i_lavmm_fec_rdata,                                  --                                                   .readdata
			i_lavmm_fec_rdata_valid                            => i_lavmm_fec_rdata_valid,                            --                                                   .readdatavalid
			i_lavmm_fec_waitreq                                => i_lavmm_fec_waitreq,                                --                                                   .waitrequest
			o_lavmm_fec_clk                                    => o_lavmm_fec_clk,                                    --                                   reconfig_fec_clk.clk
			o_lavmm_fec_rstn                                   => o_lavmm_fec_rstn,                                   --                                   reconfig_fec_rst.reset
			o_lavmm_ux_addr                                    => o_lavmm_ux_addr,                                    --                                        reconfig_ux.address
			o_lavmm_ux_be                                      => o_lavmm_ux_be,                                      --                                                   .byteenable
			o_lavmm_ux_read                                    => o_lavmm_ux_read,                                    --                                                   .read
			o_lavmm_ux_wdata                                   => o_lavmm_ux_wdata,                                   --                                                   .writedata
			o_lavmm_ux_write                                   => o_lavmm_ux_write,                                   --                                                   .write
			i_lavmm_ux_rdata                                   => i_lavmm_ux_rdata,                                   --                                                   .readdata
			i_lavmm_ux_rdata_valid                             => i_lavmm_ux_rdata_valid,                             --                                                   .readdatavalid
			i_lavmm_ux_waitreq                                 => i_lavmm_ux_waitreq,                                 --                                                   .waitrequest
			o_lavmm_ux_clk                                     => o_lavmm_ux_clk,                                     --                                    reconfig_ux_clk.clk
			o_lavmm_ux_rstn                                    => o_lavmm_ux_rstn,                                    --                                    reconfig_ux_rst.reset
			i_ptp_tx_data                                      => i_ptp_tx_data,                                      --                                      i_ptp_tx_data.data
			o_ch_ptp_rx_data                                   => o_ch_ptp_rx_data,                                   --                                   o_ch_ptp_rx_data.data
			sm_pld_tx_demux_0_o_pcie                           => sm_pld_tx_demux_0_o_pcie,                           --                           sm_pld_tx_demux_0_o_pcie.data
			sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_eth_or_ptp => sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_eth_or_ptp, -- sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_eth_or_ptp.clk
			sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_eth_or_ptp => sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_eth_or_ptp, -- sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_eth_or_ptp.clk
			sm_pld_rx_mux_0_i_pcie                             => sm_pld_rx_mux_0_i_pcie,                             --                             sm_pld_rx_mux_0_i_pcie.data
			sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_pcie       => sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_pcie,       --       sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_pcie.clk
			sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_pcie       => sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_pcie,       --       sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_pcie.clk
			sm_pld_rx_mux_0_i_pcie_bond                        => sm_pld_rx_mux_0_i_pcie_bond,                        --                        sm_pld_rx_mux_0_i_pcie_bond.data
			sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_pcie_top   => sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_pcie_top,   --   sm_hssi_pld_chnl_rx_fifo_wr_clk_mux_0_i_pcie_top.clk
			sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_pcie_top   => sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_pcie_top,   --   sm_hssi_pld_chnl_tx_fifo_rd_clk_mux_0_i_pcie_top.clk
			k_user_rx_clk1_c0c1c2_sel                          => k_user_rx_clk1_c0c1c2_sel,                          --                          k_user_rx_clk1_c0c1c2_sel.data
			k_user_rx_clk2_c0c1c2_sel                          => k_user_rx_clk2_c0c1c2_sel,                          --                          k_user_rx_clk2_c0c1c2_sel.data
			k_user_tx_clk1_c0c1c2_sel                          => k_user_tx_clk1_c0c1c2_sel,                          --                          k_user_tx_clk1_c0c1c2_sel.data
			k_user_tx_clk2_c0c1c2_sel                          => k_user_tx_clk2_c0c1c2_sel,                          --                          k_user_tx_clk2_c0c1c2_sel.data
			i_ss_user_rx_clk1_clk                              => i_ss_user_rx_clk1_clk,                              --                              i_ss_user_rx_clk1_clk.clk
			i_ss_user_rx_clk2_clk                              => i_ss_user_rx_clk2_clk,                              --                              i_ss_user_rx_clk2_clk.clk
			i_ss_user_tx_clk1_clk                              => i_ss_user_tx_clk1_clk,                              --                              i_ss_user_tx_clk1_clk.clk
			i_ss_user_tx_clk2_clk                              => i_ss_user_tx_clk2_clk,                              --                              i_ss_user_tx_clk2_clk.clk
			i_ch_muxed_rx_data                                 => i_ch_muxed_rx_data,                                 --                                 i_ch_muxed_rx_data.data
			o_deskew_rx_source_sel                             => o_deskew_rx_source_sel                              --                             o_deskew_rx_source_sel.data
		);

end architecture rtl; -- of gts_axi_streaming_one_lane_pcie_hal_pldif_hal_2100_4s3i5ci
