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// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
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module mc #(
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_cdr_l_counter	= 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_cdr_refclk_select	= "CH0_CDR_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_flux_mode	= "CH0_FLUX_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_loopback_mode	= "CH0_LOOPBACK_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_pcie_mode	= "CH0_PCIE_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_prbs_monitor_en	= "CH0_RX_PRBS_MONITOR_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_prbs_pattern	= 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_preloaded_hardware_configs	= "CH0_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_sim_mode	= "CH0_RX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_width	= "CH0_RX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_bonding_category	= "CH0_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_pll_l_counter	= 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_pll_refclk_select	= "CH0_TX_PLL_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_prbs_gen_en	= "CH0_TX_PRBS_GEN_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_prbs_pattern	= 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_preloaded_hardware_configs	= "CH0_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_sim_mode	= "CH0_TX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_user_clk_only_mode	= "CH0_TX_USER_CLK_ONLY_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_width	= "CH0_TX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_cdr_l_counter	= 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_cdr_refclk_select	= "CH1_CDR_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_flux_mode	= "CH1_FLUX_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_loopback_mode	= "CH1_LOOPBACK_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_pcie_mode	= "CH1_PCIE_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_prbs_monitor_en	= "CH1_RX_PRBS_MONITOR_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_prbs_pattern	= 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_preloaded_hardware_configs	= "CH1_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_sim_mode	= "CH1_RX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_width	= "CH1_RX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_bonding_category	= "CH1_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_pll_l_counter	= 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_pll_refclk_select	= "CH1_TX_PLL_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_prbs_gen_en	= "CH1_TX_PRBS_GEN_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_prbs_pattern	= 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_preloaded_hardware_configs	= "CH1_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_sim_mode	= "CH1_TX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_user_clk_only_mode	= "CH1_TX_USER_CLK_ONLY_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_width	= "CH1_TX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_cdr_l_counter	= 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_cdr_refclk_select	= "CH2_CDR_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_flux_mode	= "CH2_FLUX_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_loopback_mode	= "CH2_LOOPBACK_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_pcie_mode	= "CH2_PCIE_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_prbs_monitor_en	= "CH2_RX_PRBS_MONITOR_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_prbs_pattern	= 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_preloaded_hardware_configs	= "CH2_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_sim_mode	= "CH2_RX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_width	= "CH2_RX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_bonding_category	= "CH2_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_pll_l_counter	= 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_pll_refclk_select	= "CH2_TX_PLL_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_prbs_gen_en	= "CH2_TX_PRBS_GEN_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_prbs_pattern	= 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_preloaded_hardware_configs	= "CH2_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_sim_mode	= "CH2_TX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_user_clk_only_mode	= "CH2_TX_USER_CLK_ONLY_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_width	= "CH2_TX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_cdr_l_counter	= 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_cdr_refclk_select	= "CH3_CDR_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_flux_mode	= "CH3_FLUX_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_loopback_mode	= "CH3_LOOPBACK_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_pcie_mode	= "CH3_PCIE_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_prbs_monitor_en	= "CH3_RX_PRBS_MONITOR_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_prbs_pattern	= 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_preloaded_hardware_configs	= "CH3_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_sim_mode	= "CH3_RX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_width	= "CH3_RX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_bonding_category	= "CH3_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_pll_l_counter	= 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_pll_refclk_select	= "CH3_TX_PLL_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_prbs_gen_en	= "CH3_TX_PRBS_GEN_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_prbs_pattern	= 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_preloaded_hardware_configs	= "CH3_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_sim_mode	= "CH3_TX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_user_clk_only_mode	= "CH3_TX_USER_CLK_ONLY_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_width	= "CH3_TX_WIDTH_DISABLED",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_dr_enabled	= "CH0_DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_duplex_mode	= "CH0_DUPLEX_MODE_DUPLEX",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_dyn_tx_mux	= "CH0_DYN_TX_MUX_UNUSED",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_fec_error	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_fec_mode	= "CH0_FEC_MODE_RSFEC",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_fec_spec	= "CH0_FEC_SPEC_DISABLED",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_fracture	= "CH0_FRACTURE_F25G",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_loopback_mode	= "CH0_LOOPBACK_MODE_ENABLE",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_pcs_rx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_pcs_tx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_rx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_sim_mode	= "CH0_SIM_MODE_ENABLE",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_sup_mode	= "CH0_SUP_MODE_USER_MODE",
	parameter x_std_sm_hssi_fec_wrap_0__ch0_tx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_dr_enabled	= "CH1_DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_duplex_mode	= "CH1_DUPLEX_MODE_DUPLEX",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_dyn_tx_mux	= "CH1_DYN_TX_MUX_UNUSED",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_fec_error	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_fec_mode	= "CH1_FEC_MODE_RSFEC",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_fec_spec	= "CH1_FEC_SPEC_DISABLED",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_fracture	= "CH1_FRACTURE_F25G",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_loopback_mode	= "CH1_LOOPBACK_MODE_ENABLE",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_pcs_rx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_pcs_tx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_rx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_sim_mode	= "CH1_SIM_MODE_ENABLE",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_sup_mode	= "CH1_SUP_MODE_USER_MODE",
	parameter x_std_sm_hssi_fec_wrap_0__ch1_tx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_dr_enabled	= "CH2_DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_duplex_mode	= "CH2_DUPLEX_MODE_DUPLEX",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_dyn_tx_mux	= "CH2_DYN_TX_MUX_UNUSED",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_fec_error	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_fec_mode	= "CH2_FEC_MODE_RSFEC",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_fec_spec	= "CH2_FEC_SPEC_DISABLED",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_fracture	= "CH2_FRACTURE_F25G",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_loopback_mode	= "CH2_LOOPBACK_MODE_ENABLE",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_pcs_rx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_pcs_tx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_rx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_sim_mode	= "CH2_SIM_MODE_ENABLE",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_sup_mode	= "CH2_SUP_MODE_USER_MODE",
	parameter x_std_sm_hssi_fec_wrap_0__ch2_tx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_dr_enabled	= "CH3_DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_duplex_mode	= "CH3_DUPLEX_MODE_DUPLEX",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_dyn_tx_mux	= "CH3_DYN_TX_MUX_UNUSED",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_fec_error	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_fec_mode	= "CH3_FEC_MODE_RSFEC",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_fec_spec	= "CH3_FEC_SPEC_DISABLED",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_fracture	= "CH3_FRACTURE_F25G",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_loopback_mode	= "CH3_LOOPBACK_MODE_ENABLE",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_pcs_rx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_pcs_tx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_rx_en	= "FALSE",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_sim_mode	= "CH3_SIM_MODE_ENABLE",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_sup_mode	= "CH3_SUP_MODE_USER_MODE",
	parameter x_std_sm_hssi_fec_wrap_0__ch3_tx_en	= "FALSE",
	parameter x_std_sm_ux_toolbox_0__ch0_clkrx_refclk_cssm_fw_control	= "CH0_CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_clkrx_refclk_sector_specifies_refclk_ready	= "CH0_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_dr_enabled	= "CH0_DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch0_flux_mode	= "CH0_FLUX_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch0_lc_postdiv_sel	= "CH0_LC_POSTDIV_SEL_SYNTH_FAST",
	parameter x_std_sm_ux_toolbox_0__ch0_local_refclk_cssm_fw_control	= "CH0_LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_local_refclk_sector_specifies_refclk_ready	= "CH0_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_loopback_mode	= "CH0_LOOPBACK_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch0_rst_mux_static_sel	= "CH0_RST_MUX_STATIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_dl_enable	= "CH0_RX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_dl_rx_lat_bit_for_async	= 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch0_rx_dl_rxbit_cntr_pma	= "CH0_RX_DL_RXBIT_CNTR_PMA_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_dl_rxbit_rollover	= 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch0_rx_fec_type_used	= "CH0_RX_FEC_TYPE_USED_NONE",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_preloaded_hardware_configs	= "CH0_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_protocol_hint	= "CH0_RX_PROTOCOL_HINT_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_user1_clk_mux_dynamic_sel	= "CH0_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_user2_clk_mux_dynamic_sel	= "CH0_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_width	= "CH0_RX_WIDTH_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch0_sequencer_reg_en	= "CH0_SEQUENCER_REG_EN_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_tx_bond_size	= "CH0_TX_BOND_SIZE_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch0_tx_bonding_category	= "CH0_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch0_tx_dl_enable	= "CH0_TX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_tx_preloaded_hardware_configs	= "CH0_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch0_tx_user1_clk_mux_dynamic_sel	= "CH0_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch0_tx_user2_clk_mux_dynamic_sel	= "CH0_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_clkrx_refclk_cssm_fw_control	= "CH1_CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_clkrx_refclk_sector_specifies_refclk_ready	= "CH1_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_dr_enabled	= "CH1_DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch1_flux_mode	= "CH1_FLUX_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch1_lc_postdiv_sel	= "CH1_LC_POSTDIV_SEL_SYNTH_FAST",
	parameter x_std_sm_ux_toolbox_0__ch1_local_refclk_cssm_fw_control	= "CH1_LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_local_refclk_sector_specifies_refclk_ready	= "CH1_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_loopback_mode	= "CH1_LOOPBACK_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch1_rst_mux_static_sel	= "CH1_RST_MUX_STATIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_dl_enable	= "CH1_RX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_dl_rx_lat_bit_for_async	= 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch1_rx_dl_rxbit_cntr_pma	= "CH1_RX_DL_RXBIT_CNTR_PMA_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_dl_rxbit_rollover	= 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch1_rx_fec_type_used	= "CH1_RX_FEC_TYPE_USED_NONE",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_preloaded_hardware_configs	= "CH1_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_protocol_hint	= "CH1_RX_PROTOCOL_HINT_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_user1_clk_mux_dynamic_sel	= "CH1_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_user2_clk_mux_dynamic_sel	= "CH1_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_width	= "CH1_RX_WIDTH_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch1_sequencer_reg_en	= "CH1_SEQUENCER_REG_EN_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_tx_bond_size	= "CH1_TX_BOND_SIZE_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_tx_bonding_category	= "CH1_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_tx_dl_enable	= "CH1_TX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_tx_preloaded_hardware_configs	= "CH1_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch1_tx_user1_clk_mux_dynamic_sel	= "CH1_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_tx_user2_clk_mux_dynamic_sel	= "CH1_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_clkrx_refclk_cssm_fw_control	= "CH2_CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_clkrx_refclk_sector_specifies_refclk_ready	= "CH2_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_dr_enabled	= "CH2_DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch2_flux_mode	= "CH2_FLUX_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch2_lc_postdiv_sel	= "CH2_LC_POSTDIV_SEL_SYNTH_FAST",
	parameter x_std_sm_ux_toolbox_0__ch2_local_refclk_cssm_fw_control	= "CH2_LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_local_refclk_sector_specifies_refclk_ready	= "CH2_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_loopback_mode	= "CH2_LOOPBACK_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch2_rst_mux_static_sel	= "CH2_RST_MUX_STATIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_dl_enable	= "CH2_RX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_dl_rx_lat_bit_for_async	= 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch2_rx_dl_rxbit_cntr_pma	= "CH2_RX_DL_RXBIT_CNTR_PMA_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_dl_rxbit_rollover	= 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch2_rx_fec_type_used	= "CH2_RX_FEC_TYPE_USED_NONE",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_preloaded_hardware_configs	= "CH2_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_protocol_hint	= "CH2_RX_PROTOCOL_HINT_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_user1_clk_mux_dynamic_sel	= "CH2_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_user2_clk_mux_dynamic_sel	= "CH2_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_width	= "CH2_RX_WIDTH_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch2_sequencer_reg_en	= "CH2_SEQUENCER_REG_EN_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_tx_bond_size	= "CH2_TX_BOND_SIZE_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_tx_bonding_category	= "CH2_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_tx_dl_enable	= "CH2_TX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_tx_preloaded_hardware_configs	= "CH2_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch2_tx_user1_clk_mux_dynamic_sel	= "CH2_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_tx_user2_clk_mux_dynamic_sel	= "CH2_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_clkrx_refclk_cssm_fw_control	= "CH3_CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_clkrx_refclk_sector_specifies_refclk_ready	= "CH3_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_dr_enabled	= "CH3_DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch3_flux_mode	= "CH3_FLUX_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch3_lc_postdiv_sel	= "CH3_LC_POSTDIV_SEL_SYNTH_FAST",
	parameter x_std_sm_ux_toolbox_0__ch3_local_refclk_cssm_fw_control	= "CH3_LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_local_refclk_sector_specifies_refclk_ready	= "CH3_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_loopback_mode	= "CH3_LOOPBACK_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch3_rst_mux_static_sel	= "CH3_RST_MUX_STATIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_dl_enable	= "CH3_RX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_dl_rx_lat_bit_for_async	= 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch3_rx_dl_rxbit_cntr_pma	= "CH3_RX_DL_RXBIT_CNTR_PMA_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_dl_rxbit_rollover	= 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch3_rx_fec_type_used	= "CH3_RX_FEC_TYPE_USED_NONE",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_preloaded_hardware_configs	= "CH3_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_protocol_hint	= "CH3_RX_PROTOCOL_HINT_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_user1_clk_mux_dynamic_sel	= "CH3_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_user2_clk_mux_dynamic_sel	= "CH3_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_width	= "CH3_RX_WIDTH_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch3_sequencer_reg_en	= "CH3_SEQUENCER_REG_EN_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_tx_bond_size	= "CH3_TX_BOND_SIZE_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_tx_bonding_category	= "CH3_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_tx_dl_enable	= "CH3_TX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_tx_preloaded_hardware_configs	= "CH3_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch3_tx_user1_clk_mux_dynamic_sel	= "CH3_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_tx_user2_clk_mux_dynamic_sel	= "CH3_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_invert_pin_atom             = "CH0_RX_INVERT_PIN_DISABLE",
    parameter x_std_sm_ux_toolbox_0__ch1_rx_invert_pin_atom             = "CH1_RX_INVERT_PIN_DISABLE",
    parameter x_std_sm_ux_toolbox_0__ch2_rx_invert_pin_atom             = "CH2_RX_INVERT_PIN_DISABLE",
    parameter x_std_sm_ux_toolbox_0__ch3_rx_invert_pin_atom             = "CH3_RX_INVERT_PIN_DISABLE",
    parameter x_std_sm_ux_toolbox_0__ch0_tx_invert_pin_atom             = "CH0_TX_INVERT_PIN_DISABLE",
    parameter x_std_sm_ux_toolbox_0__ch1_tx_invert_pin_atom             = "CH1_TX_INVERT_PIN_DISABLE",
    parameter x_std_sm_ux_toolbox_0__ch2_tx_invert_pin_atom             = "CH2_TX_INVERT_PIN_DISABLE",
    parameter x_std_sm_ux_toolbox_0__ch3_tx_invert_pin_atom             = "CH3_TX_INVERT_PIN_DISABLE",
    parameter x_std_sm_ux_toolbox_0__ch0_vsr_mode_atom                  = "CH0_VSR_MODE_DISABLED"    ,
    parameter x_std_sm_ux_toolbox_0__ch1_vsr_mode_atom                  = "CH1_VSR_MODE_DISABLED"    ,
    parameter x_std_sm_ux_toolbox_0__ch2_vsr_mode_atom                  = "CH2_VSR_MODE_DISABLED"    ,
    parameter x_std_sm_ux_toolbox_0__ch3_vsr_mode_atom                  = "CH3_VSR_MODE_DISABLED"     
)
 (
	input [19:0] x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr,
	input [19:0] x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr,
	input [19:0] x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr,
	input [19:0] x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr,
	input [19:0] x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr,
	input [19:0] x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr,
	input [19:0] x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr,
	input [19:0] x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr,
	input [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0,
	input [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1,
	input [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2,
	input [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3,
	input [31:0] x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata,
	input [31:0] x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata,
	input [31:0] x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata,
	input [31:0] x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata,
	input [31:0] x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata,
	input [31:0] x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata,
	input [31:0] x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata,
	input [31:0] x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata,
	input [3:0] x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be,
	input [3:0] x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be,
	input [3:0] x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be,
	input [3:0] x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be,
	input [3:0] x_std_sm_ux_toolbox_0__i_ch0_lavmm_be,
	input [3:0] x_std_sm_ux_toolbox_0__i_ch1_lavmm_be,
	input [3:0] x_std_sm_ux_toolbox_0__i_ch2_lavmm_be,
	input [3:0] x_std_sm_ux_toolbox_0__i_ch3_lavmm_be,
	input [3:0] x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux,
	input [42:0] x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data,
	input [42:0] x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data,
	input [42:0] x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data,
	input [42:0] x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data,
	input [42:0] x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data,
	input [42:0] x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data,
	input [42:0] x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data,
	input [42:0] x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data,
	input [6:0] x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async,
	input [6:0] x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async,
	input [6:0] x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async,
	input [6:0] x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async,
	input [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0,
	input [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1,
	input [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2,
	input [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3,
	input [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0,
	input [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1,
	input [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2,
	input [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ext_cpu_fast_clk,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane0,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane1,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane2,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane3,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane0,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane1,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane2,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane3,
	input x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_direct,
	input x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_clk,
	input x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_read,
	input x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_rstn,
	input x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_write,
	input x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_csr_ret,
	input x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_rx_rst_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_tx_rst_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_rx_fec_sfrz_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_tx_fec_sfrz_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_direct,
	input x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_clk,
	input x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_read,
	input x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_rstn,
	input x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_write,
	input x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_csr_ret,
	input x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_rx_rst_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_tx_rst_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_rx_fec_sfrz_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_tx_fec_sfrz_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_direct,
	input x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_clk,
	input x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_read,
	input x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_rstn,
	input x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_write,
	input x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_csr_ret,
	input x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_rx_rst_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_tx_rst_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_rx_fec_sfrz_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_tx_fec_sfrz_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_direct,
	input x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_clk,
	input x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_read,
	input x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_rstn,
	input x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_write,
	input x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_csr_ret,
	input x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_rx_rst_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_tx_rst_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_rx_fec_sfrz_n,
	input x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_tx_fec_sfrz_n,
	input x_std_sm_hssi_fec_wrap_0__i_fec_clk,
	input x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch0,
	input x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch1,
	input x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch2,
	input x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch3,
	input x_std_sm_ux_toolbox_0__i_ch0_lavmm_clk,
	input x_std_sm_ux_toolbox_0__i_ch0_lavmm_read,
	input x_std_sm_ux_toolbox_0__i_ch0_lavmm_rstn,
	input x_std_sm_ux_toolbox_0__i_ch0_lavmm_write,
	input x_std_sm_ux_toolbox_0__i_ch1_lavmm_clk,
	input x_std_sm_ux_toolbox_0__i_ch1_lavmm_read,
	input x_std_sm_ux_toolbox_0__i_ch1_lavmm_rstn,
	input x_std_sm_ux_toolbox_0__i_ch1_lavmm_write,
	input x_std_sm_ux_toolbox_0__i_ch2_lavmm_clk,
	input x_std_sm_ux_toolbox_0__i_ch2_lavmm_read,
	input x_std_sm_ux_toolbox_0__i_ch2_lavmm_rstn,
	input x_std_sm_ux_toolbox_0__i_ch2_lavmm_write,
	input x_std_sm_ux_toolbox_0__i_ch3_lavmm_clk,
	input x_std_sm_ux_toolbox_0__i_ch3_lavmm_read,
	input x_std_sm_ux_toolbox_0__i_ch3_lavmm_rstn,
	input x_std_sm_ux_toolbox_0__i_ch3_lavmm_write,
	input x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch0,
	input x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch1,
	input x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch2,
	input x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch3,
	input x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch0,
	input x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch1,
	input x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch2,
	input x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch3,
	input x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch0,
	input x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch1,
	input x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch2,
	input x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch3,
	input x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch0,
	input x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch1,
	input x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch2,
	input x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch3,
	input x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch0_a,
	input x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch1_a,
	input x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch2_a,
	input x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch3_a,
	input x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch0,
	input x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch1,
	input x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch2,
	input x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch3,
	input x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch0,
	input x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch1,
	input x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch2,
	input x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch3,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch0,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch1,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch2,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch3,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch0,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch1,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch2,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch3,
	input x_std_sm_ux_toolbox_0__i_tx_dl_ch0_bit,
	input x_std_sm_ux_toolbox_0__i_tx_dl_ch1_bit,
	input x_std_sm_ux_toolbox_0__i_tx_dl_ch2_bit,
	input x_std_sm_ux_toolbox_0__i_tx_dl_ch3_bit,
	output [11:0] x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async,
	output [11:0] x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async,
	output [11:0] x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async,
	output [11:0] x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async,
	output [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0,
	output [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1,
	output [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2,
	output [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux2_rxuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux2_rxuser2_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux2_txuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux2_txuser2_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel,
	output [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0,
	output [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1,
	output [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2,
	output [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3,
	output [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0,
	output [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1,
	output [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2,
	output [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3,
	output [31:0] x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata,
	output [31:0] x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata,
	output [31:0] x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata,
	output [31:0] x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata,
	output [31:0] x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata,
	output [31:0] x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata,
	output [31:0] x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata,
	output [31:0] x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata,
	output [3:0] x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc,
	output [42:0] x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data,
	output [42:0] x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data,
	output [42:0] x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data,
	output [42:0] x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data,
	output [42:0] x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data,
	output [42:0] x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data,
	output [42:0] x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data,
	output [42:0] x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data,
	output [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch0,
	output [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch1,
	output [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch2,
	output [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch3,
	output [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0,
	output [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1,
	output [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2,
	output [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3,
	output [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0,
	output [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1,
	output [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2,
	output [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_cpi_int,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int0,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int1,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int2,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int3,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane0,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane1,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane2,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane3,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy0,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy1,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy2,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy3,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane0,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane1,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane2,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane3,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane0,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane1,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane2,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane3,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane0,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane1,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane2,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane3,
	output x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_direct,
	output x_std_sm_hssi_fec_wrap_0__o_ch0_fec_rx_rdy_n,
	output x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_valid,
	output x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_waitreq,
	output x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_direct,
	output x_std_sm_hssi_fec_wrap_0__o_ch1_fec_rx_rdy_n,
	output x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_valid,
	output x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_waitreq,
	output x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_direct,
	output x_std_sm_hssi_fec_wrap_0__o_ch2_fec_rx_rdy_n,
	output x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_valid,
	output x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_waitreq,
	output x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_direct,
	output x_std_sm_hssi_fec_wrap_0__o_ch3_fec_rx_rdy_n,
	output x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_valid,
	output x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_waitreq,
	output x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch0,
	output x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch1,
	output x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch2,
	output x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch3,
	output x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_valid,
	output x_std_sm_ux_toolbox_0__o_ch0_lavmm_waitreq,
	output x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_valid,
	output x_std_sm_ux_toolbox_0__o_ch1_lavmm_waitreq,
	output x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_valid,
	output x_std_sm_ux_toolbox_0__o_ch2_lavmm_waitreq,
	output x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_valid,
	output x_std_sm_ux_toolbox_0__o_ch3_lavmm_waitreq,
	output x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch0,
	output x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch1,
	output x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch2,
	output x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch3,
	output x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch0,
	output x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch1,
	output x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch2,
	output x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch3,
	output x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch0,
	output x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch1,
	output x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch2,
	output x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch3,
	output x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch0_a,
	output x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch1_a,
	output x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch2_a,
	output x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch3_a,
	output x_std_sm_ux_toolbox_0__o_rx_dl_ch0_bit,
	output x_std_sm_ux_toolbox_0__o_rx_dl_ch1_bit,
	output x_std_sm_ux_toolbox_0__o_rx_dl_ch2_bit,
	output x_std_sm_ux_toolbox_0__o_rx_dl_ch3_bit
);
	wire [11:0] x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0;
	wire [11:0] x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0;
	wire [11:0] x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0;
	wire [11:0] x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0;
	wire [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0;
	wire [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0;
	wire [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0;
	wire [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0;
	wire [15:2] oflux_mem_DRam0Addr_1;
	wire [16:2] oflux_mem_IRam0Addr_1;
	wire [19:0] iflux_mem_DRam0CheckData_0;
	wire [19:0] oflux_mem_DRam0CheckWrData_1;
	wire [19:0] x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0;
	wire [19:0] x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0;
	wire [19:0] x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0;
	wire [19:0] x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0;
	wire [19:0] x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0;
	wire [19:0] x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0;
	wire [19:0] x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0;
	wire [19:0] x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux2_rxuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux2_rxuser2_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux2_txuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux2_txuser2_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel_0;
	wire [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0;
	wire [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0;
	wire [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0;
	wire [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0;
	wire [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0;
	wire [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0;
	wire [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0;
	wire [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0;
	wire [2:0] o_flux_apb_pprot_0;
	wire [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0;
	wire [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0;
	wire [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0;
	wire [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0;
	wire [31:0] iflux_mem_DRam0Data_0;
	wire [31:0] iflux_mem_IRam0Data_0;
	wire [31:0] iflux_mem_TraceMemData_0;
	wire [31:0] iflux_mem_qfifo_rd_data_0;
	wire [31:0] o_flux_apb_paddr_0;
	wire [31:0] o_flux_apb_pwdata_0;
	wire [31:0] oflux_ext_pcs_prdata_1;
	wire [31:0] oflux_mem_DRam0WrData_1;
	wire [31:0] oflux_mem_IRam0WrData_1;
	wire [31:0] oflux_mem_TraceMemWrData_1;
	wire [31:0] oflux_mem_qfifo_wr_data_1;
	wire [31:0] x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0;
	wire [31:0] x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0;
	wire [31:0] x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0;
	wire [31:0] x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0;
	wire [31:0] x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0;
	wire [31:0] x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0;
	wire [31:0] x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0;
	wire [31:0] x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0;
	wire [3:0] o_flux_apb_pstrb_0;
	wire [3:0] oflux_mem_DRam0ByteEn_1;
	wire [3:0] x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be_0;
	wire [3:0] x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be_0;
	wire [3:0] x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be_0;
	wire [3:0] x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be_0;
	wire [3:0] x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0;
	wire [3:0] x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0;
	wire [3:0] x_std_sm_ux_toolbox_0__i_ch2_lavmm_be_0;
	wire [3:0] x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0;
	wire [3:0] x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0;
	wire [3:0] x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0;
	wire [42:0] x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0;
	wire [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0;
	wire [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0;
	wire [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch2_0;
	wire [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0;
	wire [6:0] iflux_mem_IRam0CheckData_0;
	wire [6:0] oflux_mem_IRam0CheckWrData_1;
	wire [6:0] x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0;
	wire [6:0] x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0;
	wire [6:0] x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0;
	wire [6:0] x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0;
	wire [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0;
	wire [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0;
	wire [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0;
	wire [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0;
	wire [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0;
	wire [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0;
	wire [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0;
	wire [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0;
	wire [8:0] oflux_mem_TraceMemAddr_1;
	wire [8:0] oflux_mem_qfifo_rd_addr_1;
	wire [8:0] oflux_mem_qfifo_wr_addr_1;
	wire car_cpu_bresetn_1;
	wire car_cpu_clk_1;
	wire o_flux_apb_clk_0;
	wire o_flux_apb_penable_0;
	wire o_flux_apb_psel_0;
	wire o_flux_apb_pwrite_0;
	wire o_flux_apb_rst_n_0;
	wire o_pcs_txword_ch0_0;
	wire o_pcs_txword_ch1_0;
	wire o_pcs_txword_ch2_0;
	wire o_pcs_txword_ch3_0;
	wire oflux_cpi_int_1;
	wire oflux_ext_pcs_pready_1;
	wire oflux_ext_pcs_pslverr_1;
	wire oflux_int0_1;
	wire oflux_int1_1;
	wire oflux_int2_1;
	wire oflux_int3_1;
	wire oflux_mem_DRam0En_1;
	wire oflux_mem_DRam0Wr_1;
	wire oflux_mem_IRam0En_1;
	wire oflux_mem_IRam0Wr_1;
	wire oflux_mem_TraceMemEn_1;
	wire oflux_mem_TraceMemWr_1;
	wire oflux_mem_qfifo_rd_en_1;
	wire oflux_mem_qfifo_wr_en_1;
	wire oflux_srds_rdy0_1;
	wire oflux_srds_rdy1_1;
	wire oflux_srds_rdy2_1;
	wire oflux_srds_rdy3_1;
	wire oflux_srds_rx_clk_lane0_1;
	wire oflux_srds_rx_clk_lane1_1;
	wire oflux_srds_rx_clk_lane2_1;
	wire oflux_srds_rx_clk_lane3_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ext_cpu_fast_clk_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane0_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane1_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane2_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane3_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane0_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane1_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane2_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane3_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane0_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane1_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane2_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane3_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane0_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane1_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane2_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane3_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_direct_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_clk_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_read_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_rstn_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_write_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_csr_ret_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_rx_rst_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_tx_rst_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_rx_fec_sfrz_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_tx_fec_sfrz_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_direct_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_clk_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_read_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_rstn_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_write_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_csr_ret_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_rx_rst_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_tx_rst_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_rx_fec_sfrz_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_tx_fec_sfrz_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_direct_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_clk_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_read_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_rstn_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_write_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_csr_ret_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_rx_rst_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_tx_rst_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_rx_fec_sfrz_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_tx_fec_sfrz_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_direct_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_clk_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_read_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_rstn_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_write_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_csr_ret_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_rx_rst_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_tx_rst_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_rx_fec_sfrz_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_tx_fec_sfrz_n_1;
	wire x_std_sm_hssi_fec_wrap_0__i_fec_clk_1;
	wire x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch0_1;
	wire x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch1_1;
	wire x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch2_1;
	wire x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch3_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_direct_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch0_fec_rx_rdy_n_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_valid_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_waitreq_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_direct_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch1_fec_rx_rdy_n_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_valid_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_waitreq_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_direct_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch2_fec_rx_rdy_n_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_valid_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_waitreq_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_direct_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch3_fec_rx_rdy_n_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_valid_1;
	wire x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_waitreq_1;
	wire x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch0_1;
	wire x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch1_1;
	wire x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch2_1;
	wire x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_ch0_lavmm_clk_1;
	wire x_std_sm_ux_toolbox_0__i_ch0_lavmm_read_1;
	wire x_std_sm_ux_toolbox_0__i_ch0_lavmm_rstn_1;
	wire x_std_sm_ux_toolbox_0__i_ch0_lavmm_write_1;
	wire x_std_sm_ux_toolbox_0__i_ch1_lavmm_clk_1;
	wire x_std_sm_ux_toolbox_0__i_ch1_lavmm_read_1;
	wire x_std_sm_ux_toolbox_0__i_ch1_lavmm_rstn_1;
	wire x_std_sm_ux_toolbox_0__i_ch1_lavmm_write_1;
	wire x_std_sm_ux_toolbox_0__i_ch2_lavmm_clk_1;
	wire x_std_sm_ux_toolbox_0__i_ch2_lavmm_read_1;
	wire x_std_sm_ux_toolbox_0__i_ch2_lavmm_rstn_1;
	wire x_std_sm_ux_toolbox_0__i_ch2_lavmm_write_1;
	wire x_std_sm_ux_toolbox_0__i_ch3_lavmm_clk_1;
	wire x_std_sm_ux_toolbox_0__i_ch3_lavmm_read_1;
	wire x_std_sm_ux_toolbox_0__i_ch3_lavmm_rstn_1;
	wire x_std_sm_ux_toolbox_0__i_ch3_lavmm_write_1;
	wire x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch2_1;
	wire x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch2_1;
	wire x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch2_1;
	wire x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch2_1;
	wire x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch0_a_1;
	wire x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch1_a_1;
	wire x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch2_a_1;
	wire x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch3_a_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch2_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch2_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch2_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch2_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_tx_dl_ch0_bit_1;
	wire x_std_sm_ux_toolbox_0__i_tx_dl_ch1_bit_1;
	wire x_std_sm_ux_toolbox_0__i_tx_dl_ch2_bit_1;
	wire x_std_sm_ux_toolbox_0__i_tx_dl_ch3_bit_1;
	wire x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_valid_1;
	wire x_std_sm_ux_toolbox_0__o_ch0_lavmm_waitreq_1;
	wire x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_valid_1;
	wire x_std_sm_ux_toolbox_0__o_ch1_lavmm_waitreq_1;
	wire x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_valid_1;
	wire x_std_sm_ux_toolbox_0__o_ch2_lavmm_waitreq_1;
	wire x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_valid_1;
	wire x_std_sm_ux_toolbox_0__o_ch3_lavmm_waitreq_1;
	wire x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch0_1;
	wire x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch1_1;
	wire x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch2_1;
	wire x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch3_1;
	wire x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch0_1;
	wire x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch1_1;
	wire x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch2_1;
	wire x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch3_1;
	wire x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch0_1;
	wire x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch1_1;
	wire x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch2_1;
	wire x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch3_1;
	wire x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch0_a_1;
	wire x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch1_a_1;
	wire x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch2_a_1;
	wire x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch3_a_1;
	wire x_std_sm_ux_toolbox_0__o_rx_dl_ch0_bit_1;
	wire x_std_sm_ux_toolbox_0__o_rx_dl_ch1_bit_1;
	wire x_std_sm_ux_toolbox_0__o_rx_dl_ch2_bit_1;
	wire x_std_sm_ux_toolbox_0__o_rx_dl_ch3_bit_1;
	assign o_pcs_txword_ch0_0 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane0;
	assign o_pcs_txword_ch1_0 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane1;
	assign o_pcs_txword_ch2_0 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane2;
	assign o_pcs_txword_ch3_0 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane3;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ext_cpu_fast_clk_1 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ext_cpu_fast_clk;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane0_1 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane0;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane1_1 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane2_1 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane2;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane3_1 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane3;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_cpi_int = oflux_cpi_int_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int0 = oflux_int0_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int1 = oflux_int1_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int2 = oflux_int2_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int3 = oflux_int3_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane0 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane0_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane1 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane1_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane2 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane2_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane3 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane3_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy0 = oflux_srds_rdy0_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy1 = oflux_srds_rdy1_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy2 = oflux_srds_rdy2_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy3 = oflux_srds_rdy3_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane0 = oflux_srds_rx_clk_lane0_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane1 = oflux_srds_rx_clk_lane1_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane2 = oflux_srds_rx_clk_lane2_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane3 = oflux_srds_rx_clk_lane3_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane0 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane0_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane1 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane1_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane2 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane2_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane3 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane3_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane0 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane0_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane1 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane1_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane2 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane2_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane3 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane3_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[704] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[704];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[705] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[705];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[706] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[706];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[707] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[707];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[708] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[708];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[709] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[709];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[710] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[710];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[711] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[711];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[712] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[712];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[713] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[713];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[714] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[714];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[715] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[715];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[716] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[716];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[717] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[717];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[718] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[718];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[719] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[719];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[720] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[720];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[721] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[721];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[722] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[722];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[723] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[723];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[724] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[724];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[725] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[725];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[726] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[726];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[727] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[727];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[728] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[728];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[729] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[729];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[730] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[730];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[731] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[731];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[732] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[732];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[733] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[733];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[734] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[734];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[735] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[735];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[736] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[736];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[737] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[737];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[738] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[738];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[739] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[739];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[740] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[740];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[741] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[741];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[742] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[742];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[743] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[743];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[744] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[744];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[745] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[745];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[746] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[746];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[747] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[747];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[748] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[748];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[749] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[749];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[750] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[750];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[751] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[751];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[752] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[752];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[753] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[753];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[754] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[754];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[755] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[755];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[756] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[756];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[757] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[757];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[758] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[758];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[759] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[759];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[760] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[760];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[761] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[761];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[762] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[762];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[763] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[763];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[764] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[764];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[765] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[765];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[766] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[766];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[767] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[767];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[704] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[704];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[705] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[705];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[706] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[706];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[707] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[707];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[708] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[708];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[709] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[709];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[710] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[710];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[711] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[711];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[712] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[712];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[713] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[713];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[714] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[714];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[715] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[715];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[716] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[716];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[717] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[717];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[718] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[718];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[719] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[719];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[720] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[720];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[721] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[721];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[722] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[722];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[723] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[723];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[724] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[724];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[725] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[725];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[726] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[726];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[727] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[727];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[728] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[728];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[729] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[729];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[730] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[730];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[731] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[731];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[732] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[732];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[733] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[733];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[734] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[734];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[735] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[735];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[736] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[736];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[737] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[737];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[738] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[738];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[739] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[739];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[740] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[740];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[741] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[741];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[742] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[742];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[743] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[743];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[744] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[744];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[745] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[745];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[746] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[746];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[747] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[747];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[748] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[748];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[749] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[749];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[750] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[750];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[751] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[751];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[752] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[752];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[753] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[753];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[754] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[754];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[755] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[755];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[756] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[756];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[757] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[757];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[758] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[758];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[759] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[759];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[760] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[760];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[761] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[761];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[762] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[762];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[763] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[763];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[764] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[764];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[765] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[765];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[766] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[766];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[767] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[767];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[704] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[704];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[705] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[705];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[706] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[706];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[707] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[707];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[708] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[708];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[709] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[709];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[710] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[710];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[711] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[711];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[712] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[712];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[713] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[713];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[714] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[714];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[715] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[715];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[716] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[716];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[717] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[717];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[718] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[718];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[719] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[719];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[720] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[720];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[721] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[721];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[722] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[722];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[723] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[723];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[724] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[724];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[725] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[725];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[726] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[726];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[727] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[727];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[728] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[728];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[729] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[729];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[730] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[730];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[731] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[731];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[732] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[732];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[733] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[733];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[734] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[734];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[735] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[735];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[736] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[736];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[737] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[737];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[738] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[738];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[739] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[739];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[740] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[740];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[741] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[741];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[742] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[742];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[743] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[743];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[744] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[744];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[745] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[745];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[746] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[746];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[747] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[747];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[748] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[748];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[749] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[749];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[750] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[750];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[751] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[751];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[752] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[752];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[753] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[753];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[754] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[754];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[755] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[755];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[756] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[756];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[757] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[757];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[758] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[758];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[759] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[759];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[760] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[760];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[761] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[761];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[762] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[762];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[763] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[763];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[764] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[764];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[765] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[765];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[766] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[766];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[767] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[767];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[704] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[704];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[705] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[705];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[706] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[706];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[707] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[707];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[708] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[708];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[709] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[709];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[710] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[710];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[711] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[711];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[712] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[712];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[713] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[713];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[714] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[714];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[715] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[715];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[716] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[716];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[717] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[717];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[718] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[718];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[719] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[719];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[720] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[720];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[721] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[721];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[722] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[722];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[723] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[723];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[724] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[724];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[725] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[725];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[726] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[726];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[727] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[727];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[728] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[728];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[729] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[729];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[730] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[730];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[731] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[731];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[732] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[732];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[733] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[733];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[734] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[734];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[735] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[735];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[736] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[736];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[737] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[737];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[738] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[738];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[739] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[739];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[740] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[740];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[741] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[741];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[742] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[742];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[743] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[743];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[744] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[744];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[745] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[745];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[746] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[746];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[747] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[747];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[748] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[748];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[749] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[749];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[750] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[750];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[751] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[751];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[752] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[752];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[753] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[753];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[754] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[754];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[755] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[755];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[756] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[756];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[757] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[757];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[758] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[758];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[759] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[759];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[760] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[760];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[761] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[761];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[762] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[762];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[763] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[763];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[764] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[764];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[765] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[765];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[766] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[766];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[767] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[767];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[9];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[4] = x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async[4];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[5] = x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async[5];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[6] = x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async[6];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_direct_1 = x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_direct;
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[10] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[10];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[11] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[11];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[12] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[12];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[13] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[13];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[14] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[14];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[15] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[15];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[16] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[16];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[17] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[17];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[18] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[18];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[19] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[19];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[4] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[4];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[5] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[5];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[6] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[6];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[7] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[7];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[8] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[8];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[9] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr[9];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_clk_1 = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_clk;
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_read_1 = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_read;
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_rstn_1 = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_rstn;
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[10] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[10];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[11] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[11];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[12] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[12];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[13] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[13];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[14] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[14];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[15] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[15];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[16] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[16];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[17] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[17];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[18] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[18];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[19] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[19];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[20] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[20];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[21] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[21];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[22] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[22];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[23] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[23];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[24] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[24];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[25] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[25];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[26] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[26];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[27] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[27];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[28] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[28];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[29] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[29];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[30] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[30];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[31] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[31];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[4] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[4];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[5] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[5];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[6] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[6];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[7] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[7];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[8] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[8];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[9] = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata[9];
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_write_1 = x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_write;
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_csr_ret_1 = x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_csr_ret;
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_rx_rst_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_rx_rst_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_tx_rst_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_tx_rst_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_rx_fec_sfrz_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_rx_fec_sfrz_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_tx_fec_sfrz_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_tx_fec_sfrz_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[4] = x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async[4];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[5] = x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async[5];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[6] = x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async[6];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_direct_1 = x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_direct;
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[10] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[10];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[11] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[11];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[12] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[12];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[13] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[13];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[14] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[14];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[15] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[15];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[16] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[16];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[17] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[17];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[18] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[18];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[19] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[19];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[4] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[4];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[5] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[5];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[6] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[6];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[7] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[7];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[8] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[8];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[9] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr[9];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_clk_1 = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_clk;
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_read_1 = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_read;
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_rstn_1 = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_rstn;
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[10] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[10];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[11] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[11];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[12] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[12];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[13] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[13];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[14] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[14];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[15] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[15];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[16] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[16];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[17] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[17];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[18] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[18];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[19] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[19];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[20] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[20];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[21] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[21];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[22] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[22];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[23] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[23];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[24] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[24];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[25] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[25];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[26] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[26];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[27] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[27];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[28] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[28];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[29] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[29];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[30] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[30];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[31] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[31];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[4] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[4];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[5] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[5];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[6] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[6];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[7] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[7];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[8] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[8];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[9] = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata[9];
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_write_1 = x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_write;
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_csr_ret_1 = x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_csr_ret;
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_rx_rst_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_rx_rst_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_tx_rst_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_tx_rst_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_rx_fec_sfrz_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_rx_fec_sfrz_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_tx_fec_sfrz_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_tx_fec_sfrz_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[4] = x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async[4];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[5] = x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async[5];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[6] = x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async[6];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_direct_1 = x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_direct;
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[10] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[10];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[11] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[11];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[12] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[12];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[13] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[13];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[14] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[14];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[15] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[15];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[16] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[16];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[17] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[17];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[18] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[18];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[19] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[19];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[4] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[4];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[5] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[5];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[6] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[6];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[7] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[7];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[8] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[8];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[9] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr[9];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_clk_1 = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_clk;
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_read_1 = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_read;
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_rstn_1 = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_rstn;
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[10] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[10];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[11] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[11];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[12] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[12];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[13] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[13];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[14] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[14];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[15] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[15];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[16] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[16];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[17] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[17];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[18] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[18];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[19] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[19];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[20] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[20];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[21] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[21];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[22] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[22];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[23] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[23];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[24] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[24];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[25] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[25];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[26] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[26];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[27] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[27];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[28] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[28];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[29] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[29];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[30] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[30];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[31] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[31];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[4] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[4];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[5] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[5];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[6] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[6];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[7] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[7];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[8] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[8];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[9] = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata[9];
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_write_1 = x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_write;
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_csr_ret_1 = x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_csr_ret;
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_rx_rst_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_rx_rst_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_tx_rst_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_tx_rst_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_rx_fec_sfrz_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_rx_fec_sfrz_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_tx_fec_sfrz_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_tx_fec_sfrz_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[4] = x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async[4];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[5] = x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async[5];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[6] = x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async[6];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_direct_1 = x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_direct;
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[10] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[10];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[11] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[11];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[12] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[12];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[13] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[13];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[14] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[14];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[15] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[15];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[16] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[16];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[17] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[17];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[18] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[18];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[19] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[19];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[4] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[4];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[5] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[5];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[6] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[6];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[7] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[7];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[8] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[8];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[9] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr[9];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_clk_1 = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_clk;
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_read_1 = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_read;
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_rstn_1 = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_rstn;
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[0] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[0];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[10] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[10];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[11] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[11];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[12] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[12];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[13] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[13];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[14] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[14];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[15] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[15];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[16] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[16];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[17] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[17];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[18] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[18];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[19] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[19];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[1] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[1];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[20] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[20];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[21] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[21];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[22] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[22];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[23] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[23];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[24] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[24];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[25] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[25];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[26] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[26];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[27] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[27];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[28] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[28];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[29] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[29];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[2] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[2];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[30] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[30];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[31] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[31];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[3] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[3];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[4] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[4];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[5] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[5];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[6] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[6];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[7] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[7];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[8] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[8];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[9] = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata[9];
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_write_1 = x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_write;
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_csr_ret_1 = x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_csr_ret;
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_rx_rst_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_rx_rst_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_tx_rst_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_tx_rst_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_rx_fec_sfrz_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_rx_fec_sfrz_n;
	assign x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_tx_fec_sfrz_n_1 = x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_tx_fec_sfrz_n;
	assign x_std_sm_hssi_fec_wrap_0__i_fec_clk_1 = x_std_sm_hssi_fec_wrap_0__i_fec_clk;
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[0] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[0];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[10] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[10];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[11] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[11];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[12] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[12];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[13] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[13];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[14] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[14];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[15] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[15];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[16] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[16];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[17] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[17];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[18] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[18];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[19] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[19];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[1] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[1];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[20] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[20];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[21] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[21];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[22] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[22];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[23] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[23];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[24] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[24];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[25] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[25];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[26] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[26];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[27] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[27];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[28] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[28];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[29] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[29];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[2] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[2];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[30] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[30];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[31] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[31];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[32] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[32];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[33] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[33];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[34] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[34];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[35] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[35];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[36] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[36];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[37] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[37];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[38] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[38];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[39] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[39];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[3] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[3];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[40] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[40];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[41] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[41];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[42] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[42];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[4] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[4];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[5] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[5];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[6] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[6];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[7] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[7];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[8] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[8];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[9] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data[9];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[0] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[0];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[10] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[10];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[11] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[11];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[12] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[12];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[13] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[13];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[14] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[14];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[15] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[15];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[16] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[16];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[17] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[17];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[18] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[18];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[19] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[19];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[1] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[1];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[20] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[20];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[21] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[21];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[22] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[22];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[23] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[23];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[24] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[24];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[25] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[25];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[26] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[26];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[27] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[27];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[28] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[28];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[29] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[29];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[2] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[2];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[30] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[30];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[31] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[31];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[32] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[32];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[33] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[33];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[34] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[34];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[35] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[35];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[36] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[36];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[37] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[37];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[38] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[38];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[39] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[39];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[3] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[3];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[40] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[40];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[41] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[41];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[42] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[42];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[4] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[4];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[5] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[5];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[6] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[6];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[7] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[7];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[8] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[8];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[9] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data[9];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[0] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[0];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[10] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[10];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[11] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[11];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[12] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[12];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[13] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[13];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[14] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[14];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[15] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[15];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[16] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[16];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[17] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[17];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[18] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[18];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[19] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[19];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[1] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[1];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[20] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[20];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[21] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[21];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[22] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[22];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[23] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[23];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[24] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[24];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[25] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[25];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[26] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[26];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[27] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[27];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[28] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[28];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[29] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[29];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[2] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[2];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[30] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[30];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[31] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[31];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[32] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[32];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[33] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[33];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[34] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[34];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[35] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[35];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[36] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[36];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[37] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[37];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[38] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[38];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[39] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[39];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[3] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[3];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[40] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[40];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[41] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[41];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[42] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[42];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[4] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[4];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[5] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[5];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[6] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[6];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[7] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[7];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[8] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[8];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[9] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data[9];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[0] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[0];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[10] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[10];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[11] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[11];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[12] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[12];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[13] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[13];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[14] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[14];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[15] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[15];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[16] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[16];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[17] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[17];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[18] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[18];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[19] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[19];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[1] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[1];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[20] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[20];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[21] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[21];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[22] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[22];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[23] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[23];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[24] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[24];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[25] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[25];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[26] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[26];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[27] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[27];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[28] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[28];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[29] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[29];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[2] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[2];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[30] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[30];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[31] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[31];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[32] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[32];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[33] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[33];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[34] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[34];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[35] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[35];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[36] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[36];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[37] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[37];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[38] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[38];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[39] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[39];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[3] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[3];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[40] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[40];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[41] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[41];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[42] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[42];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[4] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[4];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[5] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[5];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[6] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[6];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[7] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[7];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[8] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[8];
	assign x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[9] = x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data[9];
	assign x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch0_1 = x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch0;
	assign x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch1_1 = x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch1;
	assign x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch2_1 = x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch2;
	assign x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch3_1 = x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch3;
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[0] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[0];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[10] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[10];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[11] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[11];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[12] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[12];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[13] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[13];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[14] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[14];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[15] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[15];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[16] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[16];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[17] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[17];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[18] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[18];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[19] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[19];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[1] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[1];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[20] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[20];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[21] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[21];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[22] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[22];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[23] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[23];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[24] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[24];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[25] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[25];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[26] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[26];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[27] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[27];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[28] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[28];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[29] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[29];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[2] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[2];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[30] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[30];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[31] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[31];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[32] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[32];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[33] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[33];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[34] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[34];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[35] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[35];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[36] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[36];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[37] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[37];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[38] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[38];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[39] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[39];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[3] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[3];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[40] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[40];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[41] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[41];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[42] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[42];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[4] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[4];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[5] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[5];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[6] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[6];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[7] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[7];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[8] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[8];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[9] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data[9];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[0] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[0];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[10] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[10];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[11] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[11];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[12] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[12];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[13] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[13];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[14] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[14];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[15] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[15];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[16] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[16];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[17] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[17];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[18] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[18];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[19] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[19];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[1] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[1];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[20] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[20];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[21] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[21];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[22] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[22];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[23] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[23];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[24] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[24];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[25] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[25];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[26] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[26];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[27] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[27];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[28] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[28];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[29] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[29];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[2] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[2];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[30] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[30];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[31] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[31];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[32] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[32];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[33] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[33];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[34] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[34];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[35] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[35];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[36] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[36];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[37] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[37];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[38] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[38];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[39] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[39];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[3] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[3];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[40] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[40];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[41] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[41];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[42] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[42];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[4] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[4];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[5] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[5];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[6] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[6];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[7] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[7];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[8] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[8];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[9] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data[9];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[0] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[0];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[10] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[10];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[11] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[11];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[12] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[12];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[13] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[13];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[14] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[14];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[15] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[15];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[16] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[16];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[17] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[17];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[18] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[18];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[19] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[19];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[1] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[1];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[20] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[20];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[21] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[21];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[22] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[22];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[23] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[23];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[24] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[24];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[25] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[25];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[26] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[26];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[27] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[27];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[28] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[28];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[29] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[29];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[2] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[2];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[30] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[30];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[31] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[31];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[32] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[32];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[33] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[33];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[34] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[34];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[35] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[35];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[36] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[36];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[37] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[37];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[38] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[38];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[39] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[39];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[3] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[3];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[40] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[40];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[41] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[41];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[42] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[42];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[4] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[4];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[5] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[5];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[6] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[6];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[7] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[7];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[8] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[8];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[9] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data[9];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[0] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[0];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[10] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[10];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[11] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[11];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[12] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[12];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[13] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[13];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[14] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[14];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[15] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[15];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[16] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[16];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[17] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[17];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[18] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[18];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[19] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[19];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[1] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[1];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[20] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[20];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[21] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[21];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[22] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[22];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[23] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[23];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[24] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[24];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[25] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[25];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[26] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[26];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[27] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[27];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[28] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[28];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[29] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[29];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[2] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[2];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[30] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[30];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[31] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[31];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[32] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[32];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[33] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[33];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[34] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[34];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[35] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[35];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[36] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[36];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[37] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[37];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[38] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[38];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[39] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[39];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[3] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[3];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[40] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[40];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[41] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[41];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[42] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[42];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[4] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[4];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[5] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[5];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[6] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[6];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[7] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[7];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[8] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[8];
	assign x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[9] = x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data[9];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async[0] = x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async[10] = x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async[11] = x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async[1] = x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async[2] = x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async[3] = x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async[4] = x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async[5] = x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async[6] = x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async[7] = x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async[8] = x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async[9] = x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_direct = x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_direct_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_fec_rx_rdy_n = x_std_sm_hssi_fec_wrap_0__o_ch0_fec_rx_rdy_n_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[0] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[10] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[11] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[12] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[12];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[13] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[13];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[14] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[14];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[15] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[15];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[16] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[16];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[17] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[17];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[18] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[18];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[19] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[19];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[1] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[20] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[20];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[21] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[21];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[22] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[22];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[23] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[23];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[24] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[24];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[25] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[25];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[26] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[26];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[27] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[27];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[28] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[28];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[29] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[29];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[2] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[30] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[30];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[31] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[31];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[3] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[4] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[5] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[6] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[7] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[8] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata[9] = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_valid = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_valid_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_waitreq = x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_waitreq_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async[0] = x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async[10] = x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async[11] = x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async[1] = x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async[2] = x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async[3] = x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async[4] = x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async[5] = x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async[6] = x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async[7] = x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async[8] = x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async[9] = x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_direct = x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_direct_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_fec_rx_rdy_n = x_std_sm_hssi_fec_wrap_0__o_ch1_fec_rx_rdy_n_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[0] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[10] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[11] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[12] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[12];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[13] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[13];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[14] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[14];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[15] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[15];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[16] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[16];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[17] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[17];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[18] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[18];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[19] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[19];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[1] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[20] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[20];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[21] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[21];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[22] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[22];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[23] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[23];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[24] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[24];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[25] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[25];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[26] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[26];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[27] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[27];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[28] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[28];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[29] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[29];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[2] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[30] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[30];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[31] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[31];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[3] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[4] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[5] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[6] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[7] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[8] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata[9] = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_valid = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_valid_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_waitreq = x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_waitreq_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async[0] = x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async[10] = x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async[11] = x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async[1] = x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async[2] = x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async[3] = x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async[4] = x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async[5] = x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async[6] = x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async[7] = x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async[8] = x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async[9] = x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_direct = x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_direct_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_fec_rx_rdy_n = x_std_sm_hssi_fec_wrap_0__o_ch2_fec_rx_rdy_n_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[0] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[10] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[11] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[12] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[12];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[13] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[13];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[14] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[14];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[15] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[15];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[16] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[16];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[17] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[17];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[18] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[18];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[19] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[19];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[1] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[20] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[20];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[21] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[21];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[22] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[22];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[23] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[23];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[24] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[24];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[25] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[25];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[26] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[26];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[27] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[27];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[28] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[28];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[29] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[29];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[2] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[30] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[30];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[31] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[31];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[3] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[4] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[5] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[6] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[7] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[8] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata[9] = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_valid = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_valid_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_waitreq = x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_waitreq_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async[0] = x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async[10] = x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async[11] = x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async[1] = x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async[2] = x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async[3] = x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async[4] = x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async[5] = x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async[6] = x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async[7] = x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async[8] = x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async[9] = x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_direct = x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_direct_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_fec_rx_rdy_n = x_std_sm_hssi_fec_wrap_0__o_ch3_fec_rx_rdy_n_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[0] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[10] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[11] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[12] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[12];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[13] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[13];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[14] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[14];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[15] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[15];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[16] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[16];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[17] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[17];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[18] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[18];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[19] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[19];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[1] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[20] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[20];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[21] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[21];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[22] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[22];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[23] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[23];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[24] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[24];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[25] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[25];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[26] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[26];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[27] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[27];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[28] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[28];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[29] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[29];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[2] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[30] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[30];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[31] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[31];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[3] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[4] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[5] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[6] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[7] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[8] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata[9] = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_valid = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_valid_1;
	assign x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_waitreq = x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_waitreq_1;
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[0] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[10] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[11] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[12] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[12];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[13] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[13];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[14] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[14];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[15] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[15];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[16] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[16];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[17] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[17];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[18] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[18];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[19] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[19];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[1] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[20] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[20];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[21] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[21];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[22] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[22];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[23] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[23];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[24] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[24];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[25] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[25];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[26] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[26];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[27] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[27];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[28] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[28];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[29] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[29];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[2] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[30] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[30];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[31] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[31];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[32] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[32];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[33] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[33];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[34] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[34];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[35] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[35];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[36] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[36];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[37] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[37];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[38] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[38];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[39] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[39];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[3] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[40] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[40];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[41] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[41];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[42] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[42];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[4] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[5] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[6] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[7] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[8] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data[9] = x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[0] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[10] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[11] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[12] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[12];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[13] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[13];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[14] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[14];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[15] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[15];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[16] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[16];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[17] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[17];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[18] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[18];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[19] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[19];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[1] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[20] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[20];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[21] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[21];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[22] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[22];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[23] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[23];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[24] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[24];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[25] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[25];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[26] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[26];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[27] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[27];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[28] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[28];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[29] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[29];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[2] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[30] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[30];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[31] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[31];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[32] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[32];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[33] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[33];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[34] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[34];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[35] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[35];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[36] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[36];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[37] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[37];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[38] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[38];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[39] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[39];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[3] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[40] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[40];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[41] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[41];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[42] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[42];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[4] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[5] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[6] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[7] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[8] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data[9] = x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[0] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[10] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[11] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[12] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[12];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[13] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[13];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[14] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[14];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[15] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[15];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[16] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[16];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[17] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[17];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[18] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[18];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[19] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[19];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[1] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[20] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[20];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[21] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[21];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[22] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[22];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[23] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[23];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[24] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[24];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[25] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[25];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[26] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[26];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[27] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[27];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[28] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[28];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[29] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[29];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[2] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[30] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[30];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[31] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[31];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[32] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[32];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[33] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[33];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[34] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[34];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[35] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[35];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[36] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[36];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[37] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[37];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[38] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[38];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[39] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[39];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[3] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[40] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[40];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[41] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[41];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[42] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[42];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[4] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[5] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[6] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[7] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[8] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data[9] = x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[0] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[10] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[11] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[12] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[12];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[13] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[13];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[14] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[14];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[15] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[15];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[16] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[16];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[17] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[17];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[18] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[18];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[19] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[19];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[1] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[20] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[20];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[21] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[21];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[22] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[22];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[23] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[23];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[24] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[24];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[25] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[25];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[26] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[26];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[27] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[27];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[28] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[28];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[29] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[29];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[2] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[30] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[30];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[31] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[31];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[32] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[32];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[33] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[33];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[34] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[34];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[35] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[35];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[36] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[36];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[37] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[37];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[38] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[38];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[39] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[39];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[3] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[40] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[40];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[41] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[41];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[42] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[42];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[4] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[5] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[6] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[7] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[8] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data[9] = x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch0 = x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch0_1;
	assign x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch1 = x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch1_1;
	assign x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch2 = x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch2_1;
	assign x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch3 = x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch3_1;
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[0] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[10] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[11] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[12] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[12];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[13] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[13];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[14] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[14];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[15] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[15];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[16] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[16];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[17] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[17];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[18] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[18];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[19] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[19];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[1] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[20] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[20];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[21] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[21];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[22] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[22];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[23] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[23];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[24] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[24];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[25] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[25];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[26] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[26];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[27] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[27];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[28] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[28];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[29] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[29];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[2] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[30] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[30];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[31] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[31];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[32] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[32];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[33] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[33];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[34] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[34];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[35] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[35];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[36] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[36];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[37] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[37];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[38] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[38];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[39] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[39];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[3] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[40] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[40];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[41] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[41];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[42] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[42];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[4] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[5] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[6] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[7] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[8] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data[9] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[0] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[10] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[11] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[12] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[12];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[13] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[13];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[14] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[14];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[15] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[15];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[16] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[16];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[17] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[17];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[18] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[18];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[19] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[19];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[1] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[20] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[20];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[21] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[21];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[22] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[22];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[23] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[23];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[24] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[24];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[25] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[25];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[26] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[26];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[27] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[27];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[28] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[28];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[29] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[29];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[2] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[30] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[30];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[31] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[31];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[32] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[32];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[33] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[33];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[34] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[34];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[35] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[35];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[36] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[36];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[37] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[37];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[38] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[38];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[39] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[39];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[3] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[40] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[40];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[41] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[41];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[42] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[42];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[4] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[5] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[6] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[7] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[8] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data[9] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[0] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[10] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[11] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[12] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[12];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[13] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[13];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[14] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[14];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[15] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[15];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[16] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[16];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[17] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[17];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[18] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[18];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[19] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[19];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[1] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[20] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[20];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[21] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[21];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[22] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[22];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[23] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[23];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[24] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[24];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[25] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[25];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[26] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[26];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[27] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[27];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[28] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[28];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[29] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[29];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[2] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[30] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[30];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[31] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[31];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[32] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[32];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[33] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[33];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[34] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[34];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[35] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[35];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[36] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[36];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[37] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[37];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[38] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[38];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[39] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[39];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[3] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[40] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[40];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[41] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[41];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[42] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[42];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[4] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[5] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[6] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[7] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[8] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data[9] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[9];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[0] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[0];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[10] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[10];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[11] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[11];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[12] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[12];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[13] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[13];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[14] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[14];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[15] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[15];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[16] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[16];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[17] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[17];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[18] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[18];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[19] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[19];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[1] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[1];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[20] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[20];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[21] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[21];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[22] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[22];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[23] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[23];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[24] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[24];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[25] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[25];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[26] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[26];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[27] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[27];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[28] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[28];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[29] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[29];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[2] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[2];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[30] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[30];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[31] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[31];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[32] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[32];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[33] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[33];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[34] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[34];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[35] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[35];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[36] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[36];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[37] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[37];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[38] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[38];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[39] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[39];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[3] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[3];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[40] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[40];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[41] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[41];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[42] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[42];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[4] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[4];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[5] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[5];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[6] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[6];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[7] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[7];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[8] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[8];
	assign x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data[9] = x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[9];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[0] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[0];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[10] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[10];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[11] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[11];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[12] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[12];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[13] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[13];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[14] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[14];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[15] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[15];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[16] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[16];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[17] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[17];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[18] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[18];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[19] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[19];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[1] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[1];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[2] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[2];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[3] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[3];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[4] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[4];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[5] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[5];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[6] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[6];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[7] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[7];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[8] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[8];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[9] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[9];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[0] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_be[0];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[1] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_be[1];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[2] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_be[2];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[3] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_be[3];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_clk_1 = x_std_sm_ux_toolbox_0__i_ch0_lavmm_clk;
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_read_1 = x_std_sm_ux_toolbox_0__i_ch0_lavmm_read;
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_rstn_1 = x_std_sm_ux_toolbox_0__i_ch0_lavmm_rstn;
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[0] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[0];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[10] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[10];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[11] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[11];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[12] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[12];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[13] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[13];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[14] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[14];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[15] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[15];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[16] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[16];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[17] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[17];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[18] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[18];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[19] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[19];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[1] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[1];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[20] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[20];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[21] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[21];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[22] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[22];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[23] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[23];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[24] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[24];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[25] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[25];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[26] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[26];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[27] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[27];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[28] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[28];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[29] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[29];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[2] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[2];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[30] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[30];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[31] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[31];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[3] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[3];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[4] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[4];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[5] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[5];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[6] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[6];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[7] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[7];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[8] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[8];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[9] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[9];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_write_1 = x_std_sm_ux_toolbox_0__i_ch0_lavmm_write;
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[0] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[0];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[10] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[10];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[11] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[11];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[12] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[12];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[13] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[13];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[14] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[14];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[15] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[15];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[16] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[16];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[17] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[17];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[18] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[18];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[19] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[19];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[1] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[1];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[2] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[2];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[3] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[3];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[4] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[4];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[5] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[5];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[6] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[6];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[7] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[7];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[8] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[8];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[9] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[9];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[0] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_be[0];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[1] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_be[1];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[2] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_be[2];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[3] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_be[3];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_clk_1 = x_std_sm_ux_toolbox_0__i_ch1_lavmm_clk;
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_read_1 = x_std_sm_ux_toolbox_0__i_ch1_lavmm_read;
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_rstn_1 = x_std_sm_ux_toolbox_0__i_ch1_lavmm_rstn;
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[0] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[0];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[10] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[10];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[11] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[11];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[12] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[12];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[13] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[13];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[14] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[14];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[15] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[15];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[16] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[16];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[17] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[17];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[18] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[18];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[19] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[19];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[1] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[1];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[20] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[20];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[21] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[21];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[22] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[22];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[23] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[23];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[24] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[24];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[25] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[25];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[26] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[26];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[27] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[27];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[28] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[28];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[29] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[29];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[2] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[2];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[30] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[30];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[31] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[31];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[3] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[3];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[4] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[4];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[5] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[5];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[6] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[6];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[7] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[7];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[8] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[8];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[9] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[9];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_write_1 = x_std_sm_ux_toolbox_0__i_ch1_lavmm_write;
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[0] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[0];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[10] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[10];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[11] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[11];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[12] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[12];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[13] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[13];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[14] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[14];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[15] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[15];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[16] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[16];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[17] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[17];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[18] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[18];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[19] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[19];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[1] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[1];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[2] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[2];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[3] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[3];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[4] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[4];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[5] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[5];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[6] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[6];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[7] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[7];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[8] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[8];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[9] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr[9];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_be_0[0] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_be[0];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_be_0[1] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_be[1];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_be_0[2] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_be[2];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_be_0[3] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_be[3];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_clk_1 = x_std_sm_ux_toolbox_0__i_ch2_lavmm_clk;
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_read_1 = x_std_sm_ux_toolbox_0__i_ch2_lavmm_read;
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_rstn_1 = x_std_sm_ux_toolbox_0__i_ch2_lavmm_rstn;
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[0] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[0];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[10] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[10];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[11] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[11];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[12] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[12];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[13] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[13];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[14] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[14];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[15] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[15];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[16] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[16];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[17] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[17];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[18] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[18];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[19] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[19];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[1] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[1];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[20] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[20];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[21] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[21];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[22] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[22];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[23] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[23];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[24] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[24];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[25] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[25];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[26] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[26];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[27] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[27];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[28] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[28];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[29] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[29];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[2] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[2];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[30] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[30];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[31] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[31];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[3] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[3];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[4] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[4];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[5] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[5];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[6] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[6];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[7] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[7];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[8] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[8];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[9] = x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata[9];
	assign x_std_sm_ux_toolbox_0__i_ch2_lavmm_write_1 = x_std_sm_ux_toolbox_0__i_ch2_lavmm_write;
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[0] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[0];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[10] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[10];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[11] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[11];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[12] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[12];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[13] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[13];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[14] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[14];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[15] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[15];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[16] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[16];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[17] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[17];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[18] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[18];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[19] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[19];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[1] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[1];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[2] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[2];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[3] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[3];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[4] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[4];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[5] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[5];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[6] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[6];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[7] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[7];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[8] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[8];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[9] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[9];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[0] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_be[0];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[1] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_be[1];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[2] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_be[2];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[3] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_be[3];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_clk_1 = x_std_sm_ux_toolbox_0__i_ch3_lavmm_clk;
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_read_1 = x_std_sm_ux_toolbox_0__i_ch3_lavmm_read;
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_rstn_1 = x_std_sm_ux_toolbox_0__i_ch3_lavmm_rstn;
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[0] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[0];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[10] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[10];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[11] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[11];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[12] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[12];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[13] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[13];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[14] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[14];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[15] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[15];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[16] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[16];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[17] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[17];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[18] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[18];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[19] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[19];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[1] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[1];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[20] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[20];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[21] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[21];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[22] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[22];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[23] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[23];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[24] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[24];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[25] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[25];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[26] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[26];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[27] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[27];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[28] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[28];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[29] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[29];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[2] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[2];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[30] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[30];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[31] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[31];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[3] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[3];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[4] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[4];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[5] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[5];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[6] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[6];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[7] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[7];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[8] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[8];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[9] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[9];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_write_1 = x_std_sm_ux_toolbox_0__i_ch3_lavmm_write;
	assign x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch0_1 = x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch0;
	assign x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch1_1 = x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch1;
	assign x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch2_1 = x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch2;
	assign x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch3_1 = x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch3;
	assign x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch0_1 = x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch0;
	assign x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch1_1 = x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch1;
	assign x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch2_1 = x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch2;
	assign x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch3_1 = x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch3;
	assign x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch0_1 = x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch0;
	assign x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch1_1 = x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch1;
	assign x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch2_1 = x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch2;
	assign x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch3_1 = x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch3;
	assign x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch0_1 = x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch0;
	assign x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch1_1 = x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch1;
	assign x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch2_1 = x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch2;
	assign x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch3_1 = x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch3;
	assign x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch0_a_1 = x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch0_a;
	assign x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch1_a_1 = x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch1_a;
	assign x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch2_a_1 = x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch2_a;
	assign x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch3_a_1 = x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch3_a;
	assign x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[0] = x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux[0];
	assign x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[1] = x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux[1];
	assign x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[2] = x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux[2];
	assign x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[3] = x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux[3];
	assign x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch0_1 = x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch0;
	assign x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch1_1 = x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch1;
	assign x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch2_1 = x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch2;
	assign x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch3_1 = x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch3;
	assign x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch0_1 = x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch0;
	assign x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch1_1 = x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch1;
	assign x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch2_1 = x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch2;
	assign x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch3_1 = x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch3;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch0_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch0;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch1_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch1;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch2_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch2;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch3_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch3;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch0_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch0;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch1_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch1;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch2_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch2;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch3_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch3;
	assign x_std_sm_ux_toolbox_0__i_tx_dl_ch0_bit_1 = x_std_sm_ux_toolbox_0__i_tx_dl_ch0_bit;
	assign x_std_sm_ux_toolbox_0__i_tx_dl_ch1_bit_1 = x_std_sm_ux_toolbox_0__i_tx_dl_ch1_bit;
	assign x_std_sm_ux_toolbox_0__i_tx_dl_ch2_bit_1 = x_std_sm_ux_toolbox_0__i_tx_dl_ch2_bit;
	assign x_std_sm_ux_toolbox_0__i_tx_dl_ch3_bit_1 = x_std_sm_ux_toolbox_0__i_tx_dl_ch3_bit;
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[0] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[0];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[10] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[10];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[11] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[11];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[12] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[12];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[13] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[13];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[14] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[14];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[15] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[15];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[16] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[16];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[17] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[17];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[18] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[18];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[19] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[19];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[1] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[1];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[20] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[20];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[21] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[21];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[22] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[22];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[23] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[23];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[24] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[24];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[25] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[25];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[26] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[26];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[27] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[27];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[28] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[28];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[29] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[29];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[2] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[2];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[30] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[30];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[31] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[31];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[3] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[3];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[4] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[4];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[5] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[5];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[6] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[6];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[7] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[7];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[8] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[8];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[9] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[9];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_valid = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_valid_1;
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_waitreq = x_std_sm_ux_toolbox_0__o_ch0_lavmm_waitreq_1;
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[0] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[0];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[10] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[10];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[11] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[11];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[12] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[12];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[13] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[13];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[14] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[14];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[15] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[15];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[16] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[16];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[17] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[17];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[18] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[18];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[19] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[19];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[1] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[1];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[20] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[20];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[21] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[21];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[22] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[22];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[23] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[23];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[24] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[24];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[25] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[25];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[26] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[26];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[27] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[27];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[28] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[28];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[29] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[29];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[2] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[2];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[30] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[30];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[31] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[31];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[3] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[3];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[4] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[4];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[5] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[5];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[6] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[6];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[7] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[7];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[8] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[8];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[9] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[9];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_valid = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_valid_1;
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_waitreq = x_std_sm_ux_toolbox_0__o_ch1_lavmm_waitreq_1;
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[0] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[0];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[10] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[10];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[11] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[11];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[12] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[12];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[13] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[13];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[14] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[14];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[15] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[15];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[16] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[16];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[17] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[17];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[18] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[18];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[19] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[19];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[1] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[1];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[20] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[20];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[21] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[21];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[22] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[22];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[23] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[23];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[24] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[24];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[25] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[25];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[26] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[26];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[27] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[27];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[28] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[28];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[29] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[29];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[2] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[2];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[30] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[30];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[31] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[31];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[3] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[3];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[4] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[4];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[5] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[5];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[6] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[6];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[7] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[7];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[8] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[8];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata[9] = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[9];
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_valid = x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_valid_1;
	assign x_std_sm_ux_toolbox_0__o_ch2_lavmm_waitreq = x_std_sm_ux_toolbox_0__o_ch2_lavmm_waitreq_1;
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[0] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[0];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[10] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[10];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[11] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[11];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[12] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[12];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[13] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[13];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[14] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[14];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[15] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[15];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[16] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[16];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[17] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[17];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[18] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[18];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[19] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[19];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[1] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[1];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[20] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[20];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[21] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[21];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[22] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[22];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[23] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[23];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[24] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[24];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[25] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[25];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[26] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[26];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[27] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[27];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[28] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[28];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[29] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[29];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[2] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[2];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[30] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[30];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[31] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[31];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[3] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[3];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[4] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[4];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[5] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[5];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[6] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[6];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[7] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[7];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[8] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[8];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[9] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[9];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_valid = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_valid_1;
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_waitreq = x_std_sm_ux_toolbox_0__o_ch3_lavmm_waitreq_1;
	assign x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch0 = x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch0_1;
	assign x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch1 = x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch1_1;
	assign x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch2 = x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch2_1;
	assign x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch3 = x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch3_1;
	assign x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch0 = x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch0_1;
	assign x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch1 = x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch1_1;
	assign x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch2 = x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch2_1;
	assign x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch3 = x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch3_1;
	assign x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch0 = x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch0_1;
	assign x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch1 = x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch1_1;
	assign x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch2 = x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch2_1;
	assign x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch3 = x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch3_1;
	assign x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch0_a = x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch0_a_1;
	assign x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch1_a = x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch1_a_1;
	assign x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch2_a = x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch2_a_1;
	assign x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch3_a = x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch3_a_1;
	assign x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc[0] = x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[0];
	assign x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc[1] = x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[1];
	assign x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc[2] = x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[2];
	assign x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc[3] = x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[3];
	assign x_std_sm_ux_toolbox_0__o_rx_dl_ch0_bit = x_std_sm_ux_toolbox_0__o_rx_dl_ch0_bit_1;
	assign x_std_sm_ux_toolbox_0__o_rx_dl_ch1_bit = x_std_sm_ux_toolbox_0__o_rx_dl_ch1_bit_1;
	assign x_std_sm_ux_toolbox_0__o_rx_dl_ch2_bit = x_std_sm_ux_toolbox_0__o_rx_dl_ch2_bit_1;
	assign x_std_sm_ux_toolbox_0__o_rx_dl_ch3_bit = x_std_sm_ux_toolbox_0__o_rx_dl_ch3_bit_1;
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[0] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[100] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[101] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[102] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[103] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[104] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[105] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[106] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[107] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[108] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[109] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[10] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[110] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[111] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[112] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[113] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[114] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[115] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[116] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[117] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[118] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[119] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[11] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[120] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[121] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[122] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[123] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[124] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[12] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[13] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[14] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[15] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[16] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[17] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[18] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[19] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[1] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[20] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[21] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[22] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[23] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[24] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[25] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[26] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[27] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[28] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[29] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[2] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[30] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[31] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[32] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[33] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[34] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[35] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[36] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[37] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[38] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[39] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[3] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[40] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[41] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[42] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[43] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[44] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[45] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[46] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[47] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[48] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[49] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[4] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[50] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[51] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[52] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[53] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[54] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[55] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[56] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[57] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[58] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[59] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[5] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[60] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[61] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[62] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[63] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[64] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[65] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[66] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[67] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[68] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[69] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[6] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[70] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[71] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[72] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[73] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[74] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[75] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[76] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[77] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[78] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[79] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[7] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[80] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[81] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[82] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[83] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[84] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[85] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[86] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[87] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[88] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[89] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[8] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[90] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[91] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[92] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[93] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[94] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[95] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[96] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[97] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[98] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[99] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[9] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[9];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[0] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[100] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[101] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[102] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[103] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[104] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[105] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[106] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[107] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[108] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[109] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[10] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[110] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[111] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[112] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[113] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[114] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[115] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[116] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[117] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[118] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[119] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[11] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[120] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[121] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[122] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[123] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[124] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[12] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[13] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[14] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[15] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[16] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[17] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[18] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[19] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[1] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[20] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[21] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[22] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[23] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[24] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[25] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[26] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[27] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[28] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[29] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[2] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[30] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[31] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[32] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[33] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[34] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[35] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[36] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[37] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[38] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[39] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[3] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[40] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[41] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[42] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[43] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[44] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[45] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[46] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[47] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[48] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[49] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[4] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[50] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[51] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[52] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[53] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[54] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[55] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[56] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[57] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[58] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[59] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[5] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[60] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[61] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[62] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[63] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[64] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[65] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[66] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[67] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[68] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[69] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[6] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[70] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[71] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[72] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[73] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[74] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[75] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[76] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[77] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[78] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[79] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[7] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[80] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[81] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[82] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[83] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[84] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[85] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[86] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[87] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[88] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[89] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[8] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[90] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[91] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[92] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[93] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[94] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[95] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[96] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[97] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[98] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[99] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[9] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[9];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[0] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[100] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[101] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[102] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[103] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[104] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[105] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[106] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[107] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[108] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[109] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[10] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[110] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[111] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[112] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[113] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[114] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[115] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[116] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[117] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[118] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[119] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[11] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[120] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[121] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[122] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[123] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[124] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[12] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[13] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[14] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[15] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[16] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[17] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[18] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[19] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[1] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[20] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[21] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[22] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[23] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[24] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[25] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[26] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[27] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[28] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[29] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[2] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[30] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[31] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[32] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[33] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[34] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[35] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[36] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[37] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[38] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[39] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[3] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[40] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[41] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[42] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[43] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[44] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[45] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[46] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[47] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[48] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[49] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[4] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[50] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[51] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[52] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[53] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[54] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[55] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[56] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[57] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[58] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[59] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[5] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[60] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[61] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[62] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[63] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[64] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[65] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[66] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[67] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[68] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[69] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[6] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[70] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[71] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[72] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[73] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[74] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[75] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[76] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[77] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[78] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[79] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[7] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[80] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[81] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[82] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[83] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[84] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[85] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[86] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[87] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[88] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[89] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[8] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[90] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[91] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[92] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[93] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[94] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[95] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[96] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[97] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[98] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[99] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2[9] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[9];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[0] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[100] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[101] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[102] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[103] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[104] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[105] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[106] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[107] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[108] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[109] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[10] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[110] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[111] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[112] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[113] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[114] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[115] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[116] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[117] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[118] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[119] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[11] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[120] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[121] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[122] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[123] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[124] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[12] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[13] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[14] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[15] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[16] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[17] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[18] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[19] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[1] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[20] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[21] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[22] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[23] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[24] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[25] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[26] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[27] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[28] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[29] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[2] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[30] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[31] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[32] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[33] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[34] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[35] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[36] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[37] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[38] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[39] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[3] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[40] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[41] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[42] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[43] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[44] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[45] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[46] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[47] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[48] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[49] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[4] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[50] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[51] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[52] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[53] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[54] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[55] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[56] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[57] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[58] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[59] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[5] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[60] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[61] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[62] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[63] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[64] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[65] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[66] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[67] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[68] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[69] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[6] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[70] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[71] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[72] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[73] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[74] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[75] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[76] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[77] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[78] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[79] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[7] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[80] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[81] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[82] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[83] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[84] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[85] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[86] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[87] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[88] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[89] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[8] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[90] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[91] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[92] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[93] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[94] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[95] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[96] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[97] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[98] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[99] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[9] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[9];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch0[0] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch0[1] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch0[2] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch0[3] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch0[4] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch1[0] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch1[1] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch1[2] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch1[3] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch1[4] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch2[0] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch2_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch2[1] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch2_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch2[2] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch2_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch2[3] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch2_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch2[4] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch2_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch3[0] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch3[1] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch3[2] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch3[3] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch3[4] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[0] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[100] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[101] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[102] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[103] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[104] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[105] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[106] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[107] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[108] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[109] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[10] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[110] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[111] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[112] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[113] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[114] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[115] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[116] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[117] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[118] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[119] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[11] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[120] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[121] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[122] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[123] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[124] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[125] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[125];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[126] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[126];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[127] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[127];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[128] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[128];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[129] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[129];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[12] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[130] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[130];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[131] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[131];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[132] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[132];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[133] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[133];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[134] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[134];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[135] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[135];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[136] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[136];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[137] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[137];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[138] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[138];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[139] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[139];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[13] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[140] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[140];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[141] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[141];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[142] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[142];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[143] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[143];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[144] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[144];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[145] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[145];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[146] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[146];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[147] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[147];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[148] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[148];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[149] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[149];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[14] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[150] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[150];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[151] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[151];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[152] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[152];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[153] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[153];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[154] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[154];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[155] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[155];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[156] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[156];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[157] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[157];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[158] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[158];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[159] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[159];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[15] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[160] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[160];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[161] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[161];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[162] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[162];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[163] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[163];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[164] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[164];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[165] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[165];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[166] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[166];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[167] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[167];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[168] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[168];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[169] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[169];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[16] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[170] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[170];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[171] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[171];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[172] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[172];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[173] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[173];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[174] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[174];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[175] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[175];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[176] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[176];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[177] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[177];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[178] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[178];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[179] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[179];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[17] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[180] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[180];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[181] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[181];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[182] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[182];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[183] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[183];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[184] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[184];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[185] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[185];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[186] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[186];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[187] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[187];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[188] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[188];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[189] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[189];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[18] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[190] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[190];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[191] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[191];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[192] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[192];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[193] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[193];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[194] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[194];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[195] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[195];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[196] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[196];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[197] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[197];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[198] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[198];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[199] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[199];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[19] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[1] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[200] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[200];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[201] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[201];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[202] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[202];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[203] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[203];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[204] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[204];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[205] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[205];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[206] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[206];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[207] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[207];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[208] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[208];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[209] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[209];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[20] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[210] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[210];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[211] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[211];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[212] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[212];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[213] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[213];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[214] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[214];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[215] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[215];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[216] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[216];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[217] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[217];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[218] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[218];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[219] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[219];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[21] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[220] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[220];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[221] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[221];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[222] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[222];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[223] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[223];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[224] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[224];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[225] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[225];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[226] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[226];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[227] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[227];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[228] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[228];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[229] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[229];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[22] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[230] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[230];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[231] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[231];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[232] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[232];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[233] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[233];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[234] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[234];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[235] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[235];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[236] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[236];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[237] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[237];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[238] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[238];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[239] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[239];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[23] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[240] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[240];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[241] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[241];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[242] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[242];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[243] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[243];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[244] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[244];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[245] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[245];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[246] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[246];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[247] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[247];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[248] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[248];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[249] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[249];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[24] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[25] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[26] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[27] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[28] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[29] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[2] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[30] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[31] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[32] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[33] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[34] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[35] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[36] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[37] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[38] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[39] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[3] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[40] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[41] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[42] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[43] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[44] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[45] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[46] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[47] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[48] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[49] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[4] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[50] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[51] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[52] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[53] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[54] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[55] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[56] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[57] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[58] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[59] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[5] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[60] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[61] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[62] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[63] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[64] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[65] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[66] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[67] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[68] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[69] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[6] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[70] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[71] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[72] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[73] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[74] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[75] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[76] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[77] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[78] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[79] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[7] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[80] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[81] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[82] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[83] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[84] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[85] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[86] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[87] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[88] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[89] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[8] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[90] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[91] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[92] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[93] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[94] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[95] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[96] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[97] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[98] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[99] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[9] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[9];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[0] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[100] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[101] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[102] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[103] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[104] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[105] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[106] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[107] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[108] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[109] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[10] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[110] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[111] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[112] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[113] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[114] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[115] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[116] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[117] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[118] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[119] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[11] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[120] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[121] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[122] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[123] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[124] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[125] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[125];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[126] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[126];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[127] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[127];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[128] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[128];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[129] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[129];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[12] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[130] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[130];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[131] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[131];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[132] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[132];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[133] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[133];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[134] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[134];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[135] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[135];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[136] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[136];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[137] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[137];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[138] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[138];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[139] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[139];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[13] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[140] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[140];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[141] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[141];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[142] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[142];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[143] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[143];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[144] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[144];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[145] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[145];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[146] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[146];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[147] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[147];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[148] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[148];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[149] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[149];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[14] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[150] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[150];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[151] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[151];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[152] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[152];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[153] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[153];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[154] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[154];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[155] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[155];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[156] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[156];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[157] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[157];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[158] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[158];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[159] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[159];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[15] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[160] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[160];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[161] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[161];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[162] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[162];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[163] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[163];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[164] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[164];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[165] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[165];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[166] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[166];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[167] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[167];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[168] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[168];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[169] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[169];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[16] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[170] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[170];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[171] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[171];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[172] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[172];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[173] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[173];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[174] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[174];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[175] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[175];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[176] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[176];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[177] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[177];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[178] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[178];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[179] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[179];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[17] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[180] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[180];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[181] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[181];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[182] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[182];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[183] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[183];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[184] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[184];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[185] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[185];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[186] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[186];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[187] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[187];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[188] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[188];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[189] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[189];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[18] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[190] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[190];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[191] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[191];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[192] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[192];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[193] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[193];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[194] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[194];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[195] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[195];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[196] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[196];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[197] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[197];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[198] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[198];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[199] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[199];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[19] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[1] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[200] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[200];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[201] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[201];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[202] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[202];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[203] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[203];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[204] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[204];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[205] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[205];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[206] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[206];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[207] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[207];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[208] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[208];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[209] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[209];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[20] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[210] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[210];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[211] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[211];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[212] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[212];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[213] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[213];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[214] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[214];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[215] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[215];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[216] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[216];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[217] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[217];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[218] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[218];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[219] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[219];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[21] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[220] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[220];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[221] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[221];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[222] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[222];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[223] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[223];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[224] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[224];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[225] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[225];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[226] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[226];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[227] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[227];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[228] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[228];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[229] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[229];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[22] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[230] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[230];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[231] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[231];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[232] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[232];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[233] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[233];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[234] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[234];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[235] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[235];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[236] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[236];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[237] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[237];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[238] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[238];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[239] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[239];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[23] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[240] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[240];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[241] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[241];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[242] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[242];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[243] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[243];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[244] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[244];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[245] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[245];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[246] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[246];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[247] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[247];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[248] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[248];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[249] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[249];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[24] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[25] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[26] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[27] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[28] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[29] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[2] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[30] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[31] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[32] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[33] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[34] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[35] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[36] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[37] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[38] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[39] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[3] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[40] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[41] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[42] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[43] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[44] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[45] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[46] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[47] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[48] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[49] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[4] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[50] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[51] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[52] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[53] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[54] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[55] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[56] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[57] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[58] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[59] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[5] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[60] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[61] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[62] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[63] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[64] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[65] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[66] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[67] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[68] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[69] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[6] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[70] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[71] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[72] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[73] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[74] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[75] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[76] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[77] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[78] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[79] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[7] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[80] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[81] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[82] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[83] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[84] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[85] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[86] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[87] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[88] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[89] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[8] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[90] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[91] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[92] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[93] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[94] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[95] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[96] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[97] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[98] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[99] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[9] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[9];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[0] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[100] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[101] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[102] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[103] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[104] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[105] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[106] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[107] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[108] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[109] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[10] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[110] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[111] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[112] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[113] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[114] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[115] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[116] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[117] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[118] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[119] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[11] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[120] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[121] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[122] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[123] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[124] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[125] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[125];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[126] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[126];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[127] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[127];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[128] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[128];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[129] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[129];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[12] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[130] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[130];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[131] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[131];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[132] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[132];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[133] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[133];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[134] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[134];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[135] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[135];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[136] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[136];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[137] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[137];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[138] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[138];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[139] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[139];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[13] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[140] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[140];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[141] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[141];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[142] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[142];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[143] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[143];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[144] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[144];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[145] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[145];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[146] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[146];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[147] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[147];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[148] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[148];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[149] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[149];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[14] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[150] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[150];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[151] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[151];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[152] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[152];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[153] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[153];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[154] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[154];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[155] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[155];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[156] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[156];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[157] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[157];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[158] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[158];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[159] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[159];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[15] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[160] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[160];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[161] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[161];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[162] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[162];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[163] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[163];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[164] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[164];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[165] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[165];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[166] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[166];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[167] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[167];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[168] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[168];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[169] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[169];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[16] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[170] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[170];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[171] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[171];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[172] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[172];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[173] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[173];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[174] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[174];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[175] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[175];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[176] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[176];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[177] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[177];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[178] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[178];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[179] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[179];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[17] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[180] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[180];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[181] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[181];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[182] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[182];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[183] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[183];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[184] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[184];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[185] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[185];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[186] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[186];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[187] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[187];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[188] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[188];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[189] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[189];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[18] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[190] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[190];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[191] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[191];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[192] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[192];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[193] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[193];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[194] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[194];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[195] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[195];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[196] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[196];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[197] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[197];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[198] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[198];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[199] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[199];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[19] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[1] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[200] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[200];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[201] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[201];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[202] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[202];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[203] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[203];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[204] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[204];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[205] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[205];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[206] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[206];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[207] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[207];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[208] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[208];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[209] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[209];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[20] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[210] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[210];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[211] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[211];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[212] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[212];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[213] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[213];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[214] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[214];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[215] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[215];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[216] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[216];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[217] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[217];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[218] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[218];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[219] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[219];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[21] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[220] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[220];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[221] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[221];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[222] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[222];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[223] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[223];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[224] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[224];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[225] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[225];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[226] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[226];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[227] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[227];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[228] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[228];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[229] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[229];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[22] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[230] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[230];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[231] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[231];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[232] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[232];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[233] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[233];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[234] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[234];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[235] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[235];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[236] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[236];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[237] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[237];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[238] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[238];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[239] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[239];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[23] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[240] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[240];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[241] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[241];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[242] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[242];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[243] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[243];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[244] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[244];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[245] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[245];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[246] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[246];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[247] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[247];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[248] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[248];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[249] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[249];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[24] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[25] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[26] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[27] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[28] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[29] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[2] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[30] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[31] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[32] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[33] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[34] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[35] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[36] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[37] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[38] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[39] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[3] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[40] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[41] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[42] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[43] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[44] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[45] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[46] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[47] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[48] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[49] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[4] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[50] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[51] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[52] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[53] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[54] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[55] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[56] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[57] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[58] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[59] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[5] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[60] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[61] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[62] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[63] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[64] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[65] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[66] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[67] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[68] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[69] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[6] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[70] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[71] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[72] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[73] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[74] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[75] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[76] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[77] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[78] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[79] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[7] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[80] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[81] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[82] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[83] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[84] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[85] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[86] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[87] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[88] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[89] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[8] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[90] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[91] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[92] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[93] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[94] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[95] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[96] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[97] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[98] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[99] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2[9] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2_0[9];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[0] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[100] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[101] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[102] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[103] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[104] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[105] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[106] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[107] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[108] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[109] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[10] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[110] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[111] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[112] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[113] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[114] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[115] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[116] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[117] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[118] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[119] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[11] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[120] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[121] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[122] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[123] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[124] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[125] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[125];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[126] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[126];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[127] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[127];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[128] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[128];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[129] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[129];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[12] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[130] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[130];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[131] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[131];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[132] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[132];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[133] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[133];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[134] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[134];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[135] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[135];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[136] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[136];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[137] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[137];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[138] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[138];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[139] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[139];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[13] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[140] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[140];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[141] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[141];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[142] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[142];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[143] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[143];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[144] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[144];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[145] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[145];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[146] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[146];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[147] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[147];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[148] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[148];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[149] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[149];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[14] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[150] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[150];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[151] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[151];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[152] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[152];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[153] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[153];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[154] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[154];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[155] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[155];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[156] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[156];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[157] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[157];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[158] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[158];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[159] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[159];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[15] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[160] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[160];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[161] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[161];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[162] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[162];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[163] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[163];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[164] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[164];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[165] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[165];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[166] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[166];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[167] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[167];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[168] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[168];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[169] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[169];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[16] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[170] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[170];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[171] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[171];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[172] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[172];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[173] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[173];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[174] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[174];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[175] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[175];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[176] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[176];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[177] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[177];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[178] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[178];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[179] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[179];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[17] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[180] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[180];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[181] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[181];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[182] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[182];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[183] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[183];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[184] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[184];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[185] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[185];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[186] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[186];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[187] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[187];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[188] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[188];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[189] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[189];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[18] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[190] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[190];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[191] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[191];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[192] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[192];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[193] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[193];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[194] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[194];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[195] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[195];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[196] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[196];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[197] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[197];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[198] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[198];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[199] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[199];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[19] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[1] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[200] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[200];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[201] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[201];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[202] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[202];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[203] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[203];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[204] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[204];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[205] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[205];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[206] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[206];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[207] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[207];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[208] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[208];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[209] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[209];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[20] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[210] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[210];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[211] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[211];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[212] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[212];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[213] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[213];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[214] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[214];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[215] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[215];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[216] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[216];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[217] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[217];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[218] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[218];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[219] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[219];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[21] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[220] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[220];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[221] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[221];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[222] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[222];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[223] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[223];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[224] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[224];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[225] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[225];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[226] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[226];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[227] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[227];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[228] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[228];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[229] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[229];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[22] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[230] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[230];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[231] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[231];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[232] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[232];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[233] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[233];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[234] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[234];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[235] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[235];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[236] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[236];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[237] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[237];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[238] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[238];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[239] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[239];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[23] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[240] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[240];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[241] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[241];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[242] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[242];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[243] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[243];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[244] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[244];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[245] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[245];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[246] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[246];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[247] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[247];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[248] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[248];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[249] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[249];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[24] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[25] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[26] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[27] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[28] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[29] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[2] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[30] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[31] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[32] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[33] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[34] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[35] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[36] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[37] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[38] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[39] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[3] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[40] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[41] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[42] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[43] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[44] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[45] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[46] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[47] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[48] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[49] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[4] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[50] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[51] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[52] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[53] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[54] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[55] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[56] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[57] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[58] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[59] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[5] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[60] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[61] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[62] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[63] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[64] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[65] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[66] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[67] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[68] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[69] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[6] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[70] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[71] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[72] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[73] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[74] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[75] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[76] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[77] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[78] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[79] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[7] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[80] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[81] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[82] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[83] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[84] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[85] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[86] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[87] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[88] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[89] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[8] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[90] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[91] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[92] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[93] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[94] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[95] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[96] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[97] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[98] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[99] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[9] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[9];
	assign x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux2_rxuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux2_rxuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux2_rxuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux2_rxuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux2_rxuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux2_rxuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux2_rxuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux2_rxuser2_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux2_txuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux2_txuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux2_txuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux2_txuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux2_txuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux2_txuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux2_txuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux2_txuser2_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel_0[1];


	tennm_sm_hssi_fec_wrap #(
		.ch0_dr_enabled(x_std_sm_hssi_fec_wrap_0__ch0_dr_enabled),
		.ch0_duplex_mode(x_std_sm_hssi_fec_wrap_0__ch0_duplex_mode),
		.ch0_dyn_tx_mux(x_std_sm_hssi_fec_wrap_0__ch0_dyn_tx_mux),
		.ch0_fec_error(x_std_sm_hssi_fec_wrap_0__ch0_fec_error),
		.ch0_fec_mode(x_std_sm_hssi_fec_wrap_0__ch0_fec_mode),
		.ch0_fec_spec(x_std_sm_hssi_fec_wrap_0__ch0_fec_spec),
		.ch0_fracture(x_std_sm_hssi_fec_wrap_0__ch0_fracture),
		.ch0_loopback_mode(x_std_sm_hssi_fec_wrap_0__ch0_loopback_mode),
		.ch0_pcs_rx_en(x_std_sm_hssi_fec_wrap_0__ch0_pcs_rx_en),
		.ch0_pcs_tx_en(x_std_sm_hssi_fec_wrap_0__ch0_pcs_tx_en),
		.ch0_rx_en(x_std_sm_hssi_fec_wrap_0__ch0_rx_en),
		.ch0_sim_mode(x_std_sm_hssi_fec_wrap_0__ch0_sim_mode),
		.ch0_sup_mode(x_std_sm_hssi_fec_wrap_0__ch0_sup_mode),
		.ch0_tx_en(x_std_sm_hssi_fec_wrap_0__ch0_tx_en),
		.ch1_dr_enabled(x_std_sm_hssi_fec_wrap_0__ch1_dr_enabled),
		.ch1_duplex_mode(x_std_sm_hssi_fec_wrap_0__ch1_duplex_mode),
		.ch1_dyn_tx_mux(x_std_sm_hssi_fec_wrap_0__ch1_dyn_tx_mux),
		.ch1_fec_error(x_std_sm_hssi_fec_wrap_0__ch1_fec_error),
		.ch1_fec_mode(x_std_sm_hssi_fec_wrap_0__ch1_fec_mode),
		.ch1_fec_spec(x_std_sm_hssi_fec_wrap_0__ch1_fec_spec),
		.ch1_fracture(x_std_sm_hssi_fec_wrap_0__ch1_fracture),
		.ch1_loopback_mode(x_std_sm_hssi_fec_wrap_0__ch1_loopback_mode),
		.ch1_pcs_rx_en(x_std_sm_hssi_fec_wrap_0__ch1_pcs_rx_en),
		.ch1_pcs_tx_en(x_std_sm_hssi_fec_wrap_0__ch1_pcs_tx_en),
		.ch1_rx_en(x_std_sm_hssi_fec_wrap_0__ch1_rx_en),
		.ch1_sim_mode(x_std_sm_hssi_fec_wrap_0__ch1_sim_mode),
		.ch1_sup_mode(x_std_sm_hssi_fec_wrap_0__ch1_sup_mode),
		.ch1_tx_en(x_std_sm_hssi_fec_wrap_0__ch1_tx_en),
		.ch2_dr_enabled(x_std_sm_hssi_fec_wrap_0__ch2_dr_enabled),
		.ch2_duplex_mode(x_std_sm_hssi_fec_wrap_0__ch2_duplex_mode),
		.ch2_dyn_tx_mux(x_std_sm_hssi_fec_wrap_0__ch2_dyn_tx_mux),
		.ch2_fec_error(x_std_sm_hssi_fec_wrap_0__ch2_fec_error),
		.ch2_fec_mode(x_std_sm_hssi_fec_wrap_0__ch2_fec_mode),
		.ch2_fec_spec(x_std_sm_hssi_fec_wrap_0__ch2_fec_spec),
		.ch2_fracture(x_std_sm_hssi_fec_wrap_0__ch2_fracture),
		.ch2_loopback_mode(x_std_sm_hssi_fec_wrap_0__ch2_loopback_mode),
		.ch2_pcs_rx_en(x_std_sm_hssi_fec_wrap_0__ch2_pcs_rx_en),
		.ch2_pcs_tx_en(x_std_sm_hssi_fec_wrap_0__ch2_pcs_tx_en),
		.ch2_rx_en(x_std_sm_hssi_fec_wrap_0__ch2_rx_en),
		.ch2_sim_mode(x_std_sm_hssi_fec_wrap_0__ch2_sim_mode),
		.ch2_sup_mode(x_std_sm_hssi_fec_wrap_0__ch2_sup_mode),
		.ch2_tx_en(x_std_sm_hssi_fec_wrap_0__ch2_tx_en),
		.ch3_dr_enabled(x_std_sm_hssi_fec_wrap_0__ch3_dr_enabled),
		.ch3_duplex_mode(x_std_sm_hssi_fec_wrap_0__ch3_duplex_mode),
		.ch3_dyn_tx_mux(x_std_sm_hssi_fec_wrap_0__ch3_dyn_tx_mux),
		.ch3_fec_error(x_std_sm_hssi_fec_wrap_0__ch3_fec_error),
		.ch3_fec_mode(x_std_sm_hssi_fec_wrap_0__ch3_fec_mode),
		.ch3_fec_spec(x_std_sm_hssi_fec_wrap_0__ch3_fec_spec),
		.ch3_fracture(x_std_sm_hssi_fec_wrap_0__ch3_fracture),
		.ch3_loopback_mode(x_std_sm_hssi_fec_wrap_0__ch3_loopback_mode),
		.ch3_pcs_rx_en(x_std_sm_hssi_fec_wrap_0__ch3_pcs_rx_en),
		.ch3_pcs_tx_en(x_std_sm_hssi_fec_wrap_0__ch3_pcs_tx_en),
		.ch3_rx_en(x_std_sm_hssi_fec_wrap_0__ch3_rx_en),
		.ch3_sim_mode(x_std_sm_hssi_fec_wrap_0__ch3_sim_mode),
		.ch3_sup_mode(x_std_sm_hssi_fec_wrap_0__ch3_sup_mode),
		.ch3_tx_en(x_std_sm_hssi_fec_wrap_0__ch3_tx_en)
	) x_std_sm_hssi_fec_wrap_0 (
		.i_ch0_eth_fec_tx_async({ x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[6], x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[5], x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[4], x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[3], x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[2], x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[1], x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async_0[0] }),
		.i_ch0_eth_fec_tx_direct(x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_direct_1),
		.i_ch0_lavmm_fec_addr({ x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[19], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[18], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[17], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[16], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[15], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[14], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[13], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[12], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[11], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[10], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[9], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[8], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[7], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[6], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[5], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[4], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[3], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[2], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[1], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr_0[0] }),
		.i_ch0_lavmm_fec_be({ x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be_0[3], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be_0[2], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be_0[1], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be_0[0] }),
		.i_ch0_lavmm_fec_clk(x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_clk_1),
		.i_ch0_lavmm_fec_read(x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_read_1),
		.i_ch0_lavmm_fec_rstn(x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_rstn_1),
		.i_ch0_lavmm_fec_wdata({ x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[31], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[30], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[29], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[28], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[27], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[26], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[25], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[24], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[23], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[22], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[21], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[20], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[19], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[18], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[17], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[16], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[15], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[14], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[13], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[12], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[11], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[10], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[9], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[8], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[7], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[6], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[5], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[4], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[3], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[2], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[1], x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata_0[0] }),
		.i_ch0_lavmm_fec_write(x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_write_1),
		.i_ch0_rstfec_fec_csr_ret(x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_csr_ret_1),
		.i_ch0_rstfec_fec_rx_rst_n(x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_rx_rst_n_1),
		.i_ch0_rstfec_fec_tx_rst_n(x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_tx_rst_n_1),
		.i_ch0_rstfec_rx_fec_sfrz_n(x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_rx_fec_sfrz_n_1),
		.i_ch0_rstfec_tx_fec_sfrz_n(x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_tx_fec_sfrz_n_1),
		.i_ch1_eth_fec_tx_async({ x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[6], x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[5], x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[4], x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[3], x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[2], x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[1], x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async_0[0] }),
		.i_ch1_eth_fec_tx_direct(x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_direct_1),
		.i_ch1_lavmm_fec_addr({ x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[19], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[18], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[17], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[16], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[15], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[14], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[13], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[12], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[11], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[10], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[9], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[8], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[7], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[6], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[5], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[4], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[3], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[2], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[1], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr_0[0] }),
		.i_ch1_lavmm_fec_be({ x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be_0[3], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be_0[2], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be_0[1], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be_0[0] }),
		.i_ch1_lavmm_fec_clk(x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_clk_1),
		.i_ch1_lavmm_fec_read(x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_read_1),
		.i_ch1_lavmm_fec_rstn(x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_rstn_1),
		.i_ch1_lavmm_fec_wdata({ x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[31], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[30], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[29], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[28], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[27], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[26], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[25], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[24], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[23], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[22], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[21], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[20], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[19], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[18], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[17], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[16], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[15], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[14], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[13], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[12], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[11], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[10], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[9], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[8], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[7], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[6], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[5], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[4], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[3], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[2], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[1], x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata_0[0] }),
		.i_ch1_lavmm_fec_write(x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_write_1),
		.i_ch1_rstfec_fec_csr_ret(x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_csr_ret_1),
		.i_ch1_rstfec_fec_rx_rst_n(x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_rx_rst_n_1),
		.i_ch1_rstfec_fec_tx_rst_n(x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_tx_rst_n_1),
		.i_ch1_rstfec_rx_fec_sfrz_n(x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_rx_fec_sfrz_n_1),
		.i_ch1_rstfec_tx_fec_sfrz_n(x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_tx_fec_sfrz_n_1),
		.i_ch2_eth_fec_tx_async({ x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[6], x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[5], x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[4], x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[3], x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[2], x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[1], x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async_0[0] }),
		.i_ch2_eth_fec_tx_direct(x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_direct_1),
		.i_ch2_lavmm_fec_addr({ x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[19], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[18], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[17], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[16], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[15], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[14], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[13], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[12], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[11], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[10], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[9], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[8], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[7], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[6], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[5], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[4], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[3], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[2], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[1], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr_0[0] }),
		.i_ch2_lavmm_fec_be({ x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be_0[3], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be_0[2], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be_0[1], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be_0[0] }),
		.i_ch2_lavmm_fec_clk(x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_clk_1),
		.i_ch2_lavmm_fec_read(x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_read_1),
		.i_ch2_lavmm_fec_rstn(x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_rstn_1),
		.i_ch2_lavmm_fec_wdata({ x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[31], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[30], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[29], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[28], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[27], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[26], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[25], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[24], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[23], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[22], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[21], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[20], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[19], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[18], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[17], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[16], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[15], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[14], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[13], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[12], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[11], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[10], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[9], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[8], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[7], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[6], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[5], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[4], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[3], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[2], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[1], x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata_0[0] }),
		.i_ch2_lavmm_fec_write(x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_write_1),
		.i_ch2_rstfec_fec_csr_ret(x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_csr_ret_1),
		.i_ch2_rstfec_fec_rx_rst_n(x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_rx_rst_n_1),
		.i_ch2_rstfec_fec_tx_rst_n(x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_tx_rst_n_1),
		.i_ch2_rstfec_rx_fec_sfrz_n(x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_rx_fec_sfrz_n_1),
		.i_ch2_rstfec_tx_fec_sfrz_n(x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_tx_fec_sfrz_n_1),
		.i_ch3_eth_fec_tx_async({ x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[6], x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[5], x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[4], x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[3], x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[2], x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[1], x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async_0[0] }),
		.i_ch3_eth_fec_tx_direct(x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_direct_1),
		.i_ch3_lavmm_fec_addr({ x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[19], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[18], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[17], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[16], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[15], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[14], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[13], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[12], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[11], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[10], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[9], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[8], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[7], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[6], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[5], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[4], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[3], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[2], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[1], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr_0[0] }),
		.i_ch3_lavmm_fec_be({ x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be_0[3], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be_0[2], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be_0[1], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be_0[0] }),
		.i_ch3_lavmm_fec_clk(x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_clk_1),
		.i_ch3_lavmm_fec_read(x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_read_1),
		.i_ch3_lavmm_fec_rstn(x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_rstn_1),
		.i_ch3_lavmm_fec_wdata({ x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[31], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[30], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[29], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[28], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[27], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[26], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[25], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[24], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[23], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[22], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[21], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[20], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[19], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[18], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[17], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[16], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[15], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[14], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[13], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[12], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[11], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[10], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[9], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[8], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[7], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[6], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[5], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[4], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[3], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[2], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[1], x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata_0[0] }),
		.i_ch3_lavmm_fec_write(x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_write_1),
		.i_ch3_rstfec_fec_csr_ret(x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_csr_ret_1),
		.i_ch3_rstfec_fec_rx_rst_n(x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_rx_rst_n_1),
		.i_ch3_rstfec_fec_tx_rst_n(x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_tx_rst_n_1),
		.i_ch3_rstfec_rx_fec_sfrz_n(x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_rx_fec_sfrz_n_1),
		.i_ch3_rstfec_tx_fec_sfrz_n(x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_tx_fec_sfrz_n_1),
		.i_fec_clk(x_std_sm_hssi_fec_wrap_0__i_fec_clk_1),
		.i_fec_wrap_ch0_tx_mux_data({ x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[42], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[41], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[40], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[39], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[38], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[37], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[36], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[35], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[34], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[33], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[32], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[31], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[30], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[29], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[28], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[27], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[26], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[25], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[24], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[23], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[22], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[21], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[20], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[19], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[18], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[17], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[16], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[15], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[14], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[13], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[12], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[11], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[10], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[9], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[8], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[7], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[6], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[5], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[4], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[3], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[2], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[1], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data_0[0] }),
		.i_fec_wrap_ch1_tx_mux_data({ x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[42], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[41], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[40], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[39], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[38], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[37], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[36], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[35], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[34], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[33], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[32], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[31], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[30], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[29], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[28], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[27], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[26], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[25], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[24], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[23], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[22], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[21], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[20], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[19], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[18], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[17], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[16], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[15], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[14], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[13], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[12], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[11], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[10], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[9], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[8], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[7], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[6], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[5], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[4], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[3], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[2], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[1], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data_0[0] }),
		.i_fec_wrap_ch2_tx_mux_data({ x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[42], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[41], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[40], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[39], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[38], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[37], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[36], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[35], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[34], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[33], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[32], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[31], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[30], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[29], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[28], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[27], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[26], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[25], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[24], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[23], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[22], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[21], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[20], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[19], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[18], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[17], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[16], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[15], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[14], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[13], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[12], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[11], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[10], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[9], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[8], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[7], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[6], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[5], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[4], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[3], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[2], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[1], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data_0[0] }),
		.i_fec_wrap_ch3_tx_mux_data({ x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[42], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[41], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[40], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[39], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[38], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[37], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[36], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[35], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[34], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[33], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[32], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[31], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[30], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[29], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[28], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[27], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[26], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[25], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[24], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[23], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[22], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[21], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[20], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[19], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[18], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[17], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[16], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[15], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[14], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[13], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[12], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[11], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[10], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[9], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[8], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[7], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[6], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[5], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[4], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[3], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[2], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[1], x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data_0[0] }),
		.i_pma_rx_sf_ch0(x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch0_1),
		.i_pma_rx_sf_ch1(x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch1_1),
		.i_pma_rx_sf_ch2(x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch2_1),
		.i_pma_rx_sf_ch3(x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch3_1),
		.i_xcvr_ch0_rx_data({ x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[42], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[41], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[40], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[39], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[38], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[37], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[36], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[35], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[34], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[33], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[32], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[31], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[30], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[29], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[28], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[27], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[26], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[25], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[24], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[23], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[22], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[21], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[20], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[19], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[18], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[17], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[16], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[15], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[14], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[13], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[12], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[11], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[10], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[9], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[8], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[7], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[6], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[5], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[4], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[3], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[2], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[1], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data_0[0] }),
		.i_xcvr_ch1_rx_data({ x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[42], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[41], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[40], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[39], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[38], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[37], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[36], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[35], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[34], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[33], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[32], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[31], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[30], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[29], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[28], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[27], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[26], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[25], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[24], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[23], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[22], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[21], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[20], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[19], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[18], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[17], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[16], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[15], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[14], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[13], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[12], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[11], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[10], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[9], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[8], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[7], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[6], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[5], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[4], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[3], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[2], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[1], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data_0[0] }),
		.i_xcvr_ch2_rx_data({ x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[42], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[41], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[40], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[39], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[38], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[37], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[36], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[35], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[34], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[33], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[32], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[31], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[30], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[29], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[28], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[27], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[26], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[25], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[24], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[23], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[22], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[21], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[20], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[19], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[18], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[17], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[16], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[15], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[14], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[13], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[12], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[11], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[10], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[9], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[8], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[7], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[6], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[5], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[4], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[3], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[2], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[1], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data_0[0] }),
		.i_xcvr_ch3_rx_data({ x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[42], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[41], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[40], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[39], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[38], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[37], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[36], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[35], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[34], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[33], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[32], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[31], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[30], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[29], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[28], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[27], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[26], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[25], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[24], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[23], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[22], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[21], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[20], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[19], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[18], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[17], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[16], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[15], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[14], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[13], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[12], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[11], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[10], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[9], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[8], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[7], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[6], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[5], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[4], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[3], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[2], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[1], x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data_0[0] }),
		.o_ch0_eth_fec_rx_async({ x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[11], x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[10], x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[9], x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[8], x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[7], x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[6], x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[5], x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[4], x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[3], x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[2], x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[1], x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async_0[0] }),
		.o_ch0_eth_fec_rx_direct(x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_direct_1),
		.o_ch0_fec_rx_rdy_n(x_std_sm_hssi_fec_wrap_0__o_ch0_fec_rx_rdy_n_1),
		.o_ch0_lavmm_fec_rdata({ x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[31], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[30], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[29], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[28], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[27], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[26], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[25], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[24], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[23], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[22], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[21], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[20], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[19], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[18], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[17], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[16], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[15], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[14], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[13], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[12], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[11], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[10], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[9], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[8], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[7], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[6], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[5], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[4], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[3], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[2], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[1], x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_0[0] }),
		.o_ch0_lavmm_fec_rdata_valid(x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_valid_1),
		.o_ch0_lavmm_fec_waitreq(x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_waitreq_1),
		.o_ch1_eth_fec_rx_async({ x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[11], x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[10], x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[9], x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[8], x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[7], x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[6], x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[5], x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[4], x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[3], x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[2], x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[1], x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async_0[0] }),
		.o_ch1_eth_fec_rx_direct(x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_direct_1),
		.o_ch1_fec_rx_rdy_n(x_std_sm_hssi_fec_wrap_0__o_ch1_fec_rx_rdy_n_1),
		.o_ch1_lavmm_fec_rdata({ x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[31], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[30], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[29], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[28], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[27], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[26], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[25], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[24], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[23], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[22], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[21], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[20], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[19], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[18], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[17], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[16], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[15], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[14], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[13], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[12], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[11], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[10], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[9], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[8], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[7], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[6], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[5], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[4], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[3], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[2], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[1], x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_0[0] }),
		.o_ch1_lavmm_fec_rdata_valid(x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_valid_1),
		.o_ch1_lavmm_fec_waitreq(x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_waitreq_1),
		.o_ch2_eth_fec_rx_async({ x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[11], x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[10], x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[9], x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[8], x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[7], x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[6], x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[5], x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[4], x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[3], x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[2], x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[1], x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async_0[0] }),
		.o_ch2_eth_fec_rx_direct(x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_direct_1),
		.o_ch2_fec_rx_rdy_n(x_std_sm_hssi_fec_wrap_0__o_ch2_fec_rx_rdy_n_1),
		.o_ch2_lavmm_fec_rdata({ x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[31], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[30], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[29], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[28], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[27], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[26], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[25], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[24], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[23], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[22], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[21], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[20], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[19], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[18], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[17], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[16], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[15], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[14], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[13], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[12], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[11], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[10], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[9], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[8], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[7], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[6], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[5], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[4], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[3], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[2], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[1], x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_0[0] }),
		.o_ch2_lavmm_fec_rdata_valid(x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_valid_1),
		.o_ch2_lavmm_fec_waitreq(x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_waitreq_1),
		.o_ch3_eth_fec_rx_async({ x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[11], x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[10], x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[9], x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[8], x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[7], x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[6], x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[5], x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[4], x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[3], x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[2], x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[1], x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async_0[0] }),
		.o_ch3_eth_fec_rx_direct(x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_direct_1),
		.o_ch3_fec_rx_rdy_n(x_std_sm_hssi_fec_wrap_0__o_ch3_fec_rx_rdy_n_1),
		.o_ch3_lavmm_fec_rdata({ x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[31], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[30], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[29], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[28], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[27], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[26], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[25], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[24], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[23], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[22], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[21], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[20], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[19], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[18], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[17], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[16], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[15], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[14], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[13], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[12], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[11], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[10], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[9], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[8], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[7], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[6], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[5], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[4], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[3], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[2], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[1], x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_0[0] }),
		.o_ch3_lavmm_fec_rdata_valid(x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_valid_1),
		.o_ch3_lavmm_fec_waitreq(x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_waitreq_1),
		.o_fec_ch0_rx_data({ x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[42], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[41], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[40], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[39], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[38], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[37], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[36], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[35], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[34], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[33], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[32], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[31], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[30], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[29], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[28], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[27], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[26], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[25], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[24], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[23], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[22], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[21], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[20], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[19], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[18], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[17], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[16], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[15], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[14], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[13], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[12], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[11], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[10], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[9], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[8], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[7], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[6], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[5], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[4], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[3], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[2], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[1], x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data_0[0] }),
		.o_fec_ch1_rx_data({ x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[42], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[41], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[40], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[39], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[38], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[37], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[36], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[35], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[34], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[33], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[32], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[31], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[30], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[29], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[28], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[27], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[26], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[25], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[24], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[23], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[22], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[21], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[20], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[19], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[18], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[17], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[16], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[15], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[14], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[13], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[12], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[11], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[10], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[9], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[8], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[7], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[6], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[5], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[4], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[3], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[2], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[1], x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data_0[0] }),
		.o_fec_ch2_rx_data({ x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[42], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[41], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[40], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[39], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[38], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[37], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[36], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[35], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[34], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[33], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[32], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[31], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[30], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[29], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[28], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[27], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[26], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[25], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[24], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[23], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[22], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[21], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[20], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[19], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[18], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[17], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[16], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[15], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[14], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[13], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[12], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[11], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[10], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[9], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[8], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[7], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[6], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[5], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[4], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[3], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[2], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[1], x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data_0[0] }),
		.o_fec_ch3_rx_data({ x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[42], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[41], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[40], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[39], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[38], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[37], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[36], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[35], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[34], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[33], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[32], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[31], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[30], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[29], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[28], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[27], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[26], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[25], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[24], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[23], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[22], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[21], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[20], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[19], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[18], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[17], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[16], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[15], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[14], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[13], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[12], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[11], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[10], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[9], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[8], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[7], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[6], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[5], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[4], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[3], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[2], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[1], x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data_0[0] }),
		.o_fec_tx_data_mux_sel_ch0(x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch0_1),
		.o_fec_tx_data_mux_sel_ch1(x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch1_1),
		.o_fec_tx_data_mux_sel_ch2(x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch2_1),
		.o_fec_tx_data_mux_sel_ch3(x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch3_1),
		.o_xcvr_ch0_tx_data({ x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[42], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[41], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[40], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[39], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[38], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[37], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[36], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[35], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[34], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[33], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[32], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[31], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[30], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[29], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[28], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[27], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[26], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[25], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[24], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[23], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[22], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[21], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[20], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[19], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[18], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[17], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[16], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[15], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[14], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[13], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[12], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[11], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[10], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[9], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[8], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[7], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[6], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[5], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[4], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[3], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[2], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[1], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data_0[0] }),
		.o_xcvr_ch1_tx_data({ x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[42], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[41], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[40], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[39], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[38], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[37], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[36], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[35], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[34], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[33], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[32], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[31], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[30], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[29], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[28], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[27], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[26], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[25], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[24], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[23], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[22], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[21], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[20], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[19], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[18], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[17], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[16], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[15], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[14], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[13], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[12], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[11], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[10], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[9], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[8], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[7], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[6], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[5], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[4], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[3], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[2], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[1], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data_0[0] }),
		.o_xcvr_ch2_tx_data({ x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[42], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[41], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[40], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[39], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[38], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[37], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[36], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[35], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[34], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[33], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[32], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[31], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[30], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[29], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[28], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[27], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[26], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[25], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[24], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[23], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[22], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[21], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[20], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[19], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[18], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[17], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[16], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[15], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[14], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[13], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[12], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[11], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[10], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[9], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[8], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[7], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[6], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[5], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[4], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[3], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[2], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[1], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data_0[0] }),
		.o_xcvr_ch3_tx_data({ x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[42], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[41], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[40], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[39], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[38], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[37], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[36], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[35], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[34], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[33], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[32], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[31], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[30], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[29], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[28], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[27], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[26], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[25], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[24], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[23], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[22], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[21], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[20], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[19], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[18], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[17], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[16], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[15], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[14], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[13], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[12], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[11], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[10], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[9], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[8], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[7], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[6], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[5], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[4], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[3], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[2], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[1], x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data_0[0] })
	);

	tennm_ipfluxtop_global_mem_wrap x_std_ipfluxtop_global_mem_wrap_0 (
		.car_cpu_bresetn(car_cpu_bresetn_1),
		.car_cpu_clk(car_cpu_clk_1),
		.iflux_mem_dram0checkdata({ iflux_mem_DRam0CheckData_0[19], iflux_mem_DRam0CheckData_0[18], iflux_mem_DRam0CheckData_0[17], iflux_mem_DRam0CheckData_0[16], iflux_mem_DRam0CheckData_0[15], iflux_mem_DRam0CheckData_0[14], iflux_mem_DRam0CheckData_0[13], iflux_mem_DRam0CheckData_0[12], iflux_mem_DRam0CheckData_0[11], iflux_mem_DRam0CheckData_0[10], iflux_mem_DRam0CheckData_0[9], iflux_mem_DRam0CheckData_0[8], iflux_mem_DRam0CheckData_0[7], iflux_mem_DRam0CheckData_0[6], iflux_mem_DRam0CheckData_0[5], iflux_mem_DRam0CheckData_0[4], iflux_mem_DRam0CheckData_0[3], iflux_mem_DRam0CheckData_0[2], iflux_mem_DRam0CheckData_0[1], iflux_mem_DRam0CheckData_0[0] }),
		.iflux_mem_dram0data({ iflux_mem_DRam0Data_0[31], iflux_mem_DRam0Data_0[30], iflux_mem_DRam0Data_0[29], iflux_mem_DRam0Data_0[28], iflux_mem_DRam0Data_0[27], iflux_mem_DRam0Data_0[26], iflux_mem_DRam0Data_0[25], iflux_mem_DRam0Data_0[24], iflux_mem_DRam0Data_0[23], iflux_mem_DRam0Data_0[22], iflux_mem_DRam0Data_0[21], iflux_mem_DRam0Data_0[20], iflux_mem_DRam0Data_0[19], iflux_mem_DRam0Data_0[18], iflux_mem_DRam0Data_0[17], iflux_mem_DRam0Data_0[16], iflux_mem_DRam0Data_0[15], iflux_mem_DRam0Data_0[14], iflux_mem_DRam0Data_0[13], iflux_mem_DRam0Data_0[12], iflux_mem_DRam0Data_0[11], iflux_mem_DRam0Data_0[10], iflux_mem_DRam0Data_0[9], iflux_mem_DRam0Data_0[8], iflux_mem_DRam0Data_0[7], iflux_mem_DRam0Data_0[6], iflux_mem_DRam0Data_0[5], iflux_mem_DRam0Data_0[4], iflux_mem_DRam0Data_0[3], iflux_mem_DRam0Data_0[2], iflux_mem_DRam0Data_0[1], iflux_mem_DRam0Data_0[0] }),
		.iflux_mem_iram0checkdata({ iflux_mem_IRam0CheckData_0[6], iflux_mem_IRam0CheckData_0[5], iflux_mem_IRam0CheckData_0[4], iflux_mem_IRam0CheckData_0[3], iflux_mem_IRam0CheckData_0[2], iflux_mem_IRam0CheckData_0[1], iflux_mem_IRam0CheckData_0[0] }),
		.iflux_mem_iram0data({ iflux_mem_IRam0Data_0[31], iflux_mem_IRam0Data_0[30], iflux_mem_IRam0Data_0[29], iflux_mem_IRam0Data_0[28], iflux_mem_IRam0Data_0[27], iflux_mem_IRam0Data_0[26], iflux_mem_IRam0Data_0[25], iflux_mem_IRam0Data_0[24], iflux_mem_IRam0Data_0[23], iflux_mem_IRam0Data_0[22], iflux_mem_IRam0Data_0[21], iflux_mem_IRam0Data_0[20], iflux_mem_IRam0Data_0[19], iflux_mem_IRam0Data_0[18], iflux_mem_IRam0Data_0[17], iflux_mem_IRam0Data_0[16], iflux_mem_IRam0Data_0[15], iflux_mem_IRam0Data_0[14], iflux_mem_IRam0Data_0[13], iflux_mem_IRam0Data_0[12], iflux_mem_IRam0Data_0[11], iflux_mem_IRam0Data_0[10], iflux_mem_IRam0Data_0[9], iflux_mem_IRam0Data_0[8], iflux_mem_IRam0Data_0[7], iflux_mem_IRam0Data_0[6], iflux_mem_IRam0Data_0[5], iflux_mem_IRam0Data_0[4], iflux_mem_IRam0Data_0[3], iflux_mem_IRam0Data_0[2], iflux_mem_IRam0Data_0[1], iflux_mem_IRam0Data_0[0] }),
		.iflux_mem_qfifo_rd_data({ iflux_mem_qfifo_rd_data_0[31], iflux_mem_qfifo_rd_data_0[30], iflux_mem_qfifo_rd_data_0[29], iflux_mem_qfifo_rd_data_0[28], iflux_mem_qfifo_rd_data_0[27], iflux_mem_qfifo_rd_data_0[26], iflux_mem_qfifo_rd_data_0[25], iflux_mem_qfifo_rd_data_0[24], iflux_mem_qfifo_rd_data_0[23], iflux_mem_qfifo_rd_data_0[22], iflux_mem_qfifo_rd_data_0[21], iflux_mem_qfifo_rd_data_0[20], iflux_mem_qfifo_rd_data_0[19], iflux_mem_qfifo_rd_data_0[18], iflux_mem_qfifo_rd_data_0[17], iflux_mem_qfifo_rd_data_0[16], iflux_mem_qfifo_rd_data_0[15], iflux_mem_qfifo_rd_data_0[14], iflux_mem_qfifo_rd_data_0[13], iflux_mem_qfifo_rd_data_0[12], iflux_mem_qfifo_rd_data_0[11], iflux_mem_qfifo_rd_data_0[10], iflux_mem_qfifo_rd_data_0[9], iflux_mem_qfifo_rd_data_0[8], iflux_mem_qfifo_rd_data_0[7], iflux_mem_qfifo_rd_data_0[6], iflux_mem_qfifo_rd_data_0[5], iflux_mem_qfifo_rd_data_0[4], iflux_mem_qfifo_rd_data_0[3], iflux_mem_qfifo_rd_data_0[2], iflux_mem_qfifo_rd_data_0[1], iflux_mem_qfifo_rd_data_0[0] }),
		.iflux_mem_tracememdata({ iflux_mem_TraceMemData_0[31], iflux_mem_TraceMemData_0[30], iflux_mem_TraceMemData_0[29], iflux_mem_TraceMemData_0[28], iflux_mem_TraceMemData_0[27], iflux_mem_TraceMemData_0[26], iflux_mem_TraceMemData_0[25], iflux_mem_TraceMemData_0[24], iflux_mem_TraceMemData_0[23], iflux_mem_TraceMemData_0[22], iflux_mem_TraceMemData_0[21], iflux_mem_TraceMemData_0[20], iflux_mem_TraceMemData_0[19], iflux_mem_TraceMemData_0[18], iflux_mem_TraceMemData_0[17], iflux_mem_TraceMemData_0[16], iflux_mem_TraceMemData_0[15], iflux_mem_TraceMemData_0[14], iflux_mem_TraceMemData_0[13], iflux_mem_TraceMemData_0[12], iflux_mem_TraceMemData_0[11], iflux_mem_TraceMemData_0[10], iflux_mem_TraceMemData_0[9], iflux_mem_TraceMemData_0[8], iflux_mem_TraceMemData_0[7], iflux_mem_TraceMemData_0[6], iflux_mem_TraceMemData_0[5], iflux_mem_TraceMemData_0[4], iflux_mem_TraceMemData_0[3], iflux_mem_TraceMemData_0[2], iflux_mem_TraceMemData_0[1], iflux_mem_TraceMemData_0[0] }),
		.oflux_mem_dram0addr({ oflux_mem_DRam0Addr_1[15], oflux_mem_DRam0Addr_1[14], oflux_mem_DRam0Addr_1[13], oflux_mem_DRam0Addr_1[12], oflux_mem_DRam0Addr_1[11], oflux_mem_DRam0Addr_1[10], oflux_mem_DRam0Addr_1[9], oflux_mem_DRam0Addr_1[8], oflux_mem_DRam0Addr_1[7], oflux_mem_DRam0Addr_1[6], oflux_mem_DRam0Addr_1[5], oflux_mem_DRam0Addr_1[4], oflux_mem_DRam0Addr_1[3], oflux_mem_DRam0Addr_1[2] }),
		.oflux_mem_dram0byteen({ oflux_mem_DRam0ByteEn_1[3], oflux_mem_DRam0ByteEn_1[2], oflux_mem_DRam0ByteEn_1[1], oflux_mem_DRam0ByteEn_1[0] }),
		.oflux_mem_dram0checkwrdata({ oflux_mem_DRam0CheckWrData_1[19], oflux_mem_DRam0CheckWrData_1[18], oflux_mem_DRam0CheckWrData_1[17], oflux_mem_DRam0CheckWrData_1[16], oflux_mem_DRam0CheckWrData_1[15], oflux_mem_DRam0CheckWrData_1[14], oflux_mem_DRam0CheckWrData_1[13], oflux_mem_DRam0CheckWrData_1[12], oflux_mem_DRam0CheckWrData_1[11], oflux_mem_DRam0CheckWrData_1[10], oflux_mem_DRam0CheckWrData_1[9], oflux_mem_DRam0CheckWrData_1[8], oflux_mem_DRam0CheckWrData_1[7], oflux_mem_DRam0CheckWrData_1[6], oflux_mem_DRam0CheckWrData_1[5], oflux_mem_DRam0CheckWrData_1[4], oflux_mem_DRam0CheckWrData_1[3], oflux_mem_DRam0CheckWrData_1[2], oflux_mem_DRam0CheckWrData_1[1], oflux_mem_DRam0CheckWrData_1[0] }),
		.oflux_mem_dram0en(oflux_mem_DRam0En_1),
		.oflux_mem_dram0wr(oflux_mem_DRam0Wr_1),
		.oflux_mem_dram0wrdata({ oflux_mem_DRam0WrData_1[31], oflux_mem_DRam0WrData_1[30], oflux_mem_DRam0WrData_1[29], oflux_mem_DRam0WrData_1[28], oflux_mem_DRam0WrData_1[27], oflux_mem_DRam0WrData_1[26], oflux_mem_DRam0WrData_1[25], oflux_mem_DRam0WrData_1[24], oflux_mem_DRam0WrData_1[23], oflux_mem_DRam0WrData_1[22], oflux_mem_DRam0WrData_1[21], oflux_mem_DRam0WrData_1[20], oflux_mem_DRam0WrData_1[19], oflux_mem_DRam0WrData_1[18], oflux_mem_DRam0WrData_1[17], oflux_mem_DRam0WrData_1[16], oflux_mem_DRam0WrData_1[15], oflux_mem_DRam0WrData_1[14], oflux_mem_DRam0WrData_1[13], oflux_mem_DRam0WrData_1[12], oflux_mem_DRam0WrData_1[11], oflux_mem_DRam0WrData_1[10], oflux_mem_DRam0WrData_1[9], oflux_mem_DRam0WrData_1[8], oflux_mem_DRam0WrData_1[7], oflux_mem_DRam0WrData_1[6], oflux_mem_DRam0WrData_1[5], oflux_mem_DRam0WrData_1[4], oflux_mem_DRam0WrData_1[3], oflux_mem_DRam0WrData_1[2], oflux_mem_DRam0WrData_1[1], oflux_mem_DRam0WrData_1[0] }),
		.oflux_mem_iram0addr({ oflux_mem_IRam0Addr_1[16], oflux_mem_IRam0Addr_1[15], oflux_mem_IRam0Addr_1[14], oflux_mem_IRam0Addr_1[13], oflux_mem_IRam0Addr_1[12], oflux_mem_IRam0Addr_1[11], oflux_mem_IRam0Addr_1[10], oflux_mem_IRam0Addr_1[9], oflux_mem_IRam0Addr_1[8], oflux_mem_IRam0Addr_1[7], oflux_mem_IRam0Addr_1[6], oflux_mem_IRam0Addr_1[5], oflux_mem_IRam0Addr_1[4], oflux_mem_IRam0Addr_1[3], oflux_mem_IRam0Addr_1[2] }),
		.oflux_mem_iram0checkwrdata({ oflux_mem_IRam0CheckWrData_1[6], oflux_mem_IRam0CheckWrData_1[5], oflux_mem_IRam0CheckWrData_1[4], oflux_mem_IRam0CheckWrData_1[3], oflux_mem_IRam0CheckWrData_1[2], oflux_mem_IRam0CheckWrData_1[1], oflux_mem_IRam0CheckWrData_1[0] }),
		.oflux_mem_iram0en(oflux_mem_IRam0En_1),
		.oflux_mem_iram0wr(oflux_mem_IRam0Wr_1),
		.oflux_mem_iram0wrdata({ oflux_mem_IRam0WrData_1[31], oflux_mem_IRam0WrData_1[30], oflux_mem_IRam0WrData_1[29], oflux_mem_IRam0WrData_1[28], oflux_mem_IRam0WrData_1[27], oflux_mem_IRam0WrData_1[26], oflux_mem_IRam0WrData_1[25], oflux_mem_IRam0WrData_1[24], oflux_mem_IRam0WrData_1[23], oflux_mem_IRam0WrData_1[22], oflux_mem_IRam0WrData_1[21], oflux_mem_IRam0WrData_1[20], oflux_mem_IRam0WrData_1[19], oflux_mem_IRam0WrData_1[18], oflux_mem_IRam0WrData_1[17], oflux_mem_IRam0WrData_1[16], oflux_mem_IRam0WrData_1[15], oflux_mem_IRam0WrData_1[14], oflux_mem_IRam0WrData_1[13], oflux_mem_IRam0WrData_1[12], oflux_mem_IRam0WrData_1[11], oflux_mem_IRam0WrData_1[10], oflux_mem_IRam0WrData_1[9], oflux_mem_IRam0WrData_1[8], oflux_mem_IRam0WrData_1[7], oflux_mem_IRam0WrData_1[6], oflux_mem_IRam0WrData_1[5], oflux_mem_IRam0WrData_1[4], oflux_mem_IRam0WrData_1[3], oflux_mem_IRam0WrData_1[2], oflux_mem_IRam0WrData_1[1], oflux_mem_IRam0WrData_1[0] }),
		.oflux_mem_qfifo_rd_addr({ oflux_mem_qfifo_rd_addr_1[8], oflux_mem_qfifo_rd_addr_1[7], oflux_mem_qfifo_rd_addr_1[6], oflux_mem_qfifo_rd_addr_1[5], oflux_mem_qfifo_rd_addr_1[4], oflux_mem_qfifo_rd_addr_1[3], oflux_mem_qfifo_rd_addr_1[2], oflux_mem_qfifo_rd_addr_1[1], oflux_mem_qfifo_rd_addr_1[0] }),
		.oflux_mem_qfifo_rd_en(oflux_mem_qfifo_rd_en_1),
		.oflux_mem_qfifo_wr_addr({ oflux_mem_qfifo_wr_addr_1[8], oflux_mem_qfifo_wr_addr_1[7], oflux_mem_qfifo_wr_addr_1[6], oflux_mem_qfifo_wr_addr_1[5], oflux_mem_qfifo_wr_addr_1[4], oflux_mem_qfifo_wr_addr_1[3], oflux_mem_qfifo_wr_addr_1[2], oflux_mem_qfifo_wr_addr_1[1], oflux_mem_qfifo_wr_addr_1[0] }),
		.oflux_mem_qfifo_wr_data({ oflux_mem_qfifo_wr_data_1[31], oflux_mem_qfifo_wr_data_1[30], oflux_mem_qfifo_wr_data_1[29], oflux_mem_qfifo_wr_data_1[28], oflux_mem_qfifo_wr_data_1[27], oflux_mem_qfifo_wr_data_1[26], oflux_mem_qfifo_wr_data_1[25], oflux_mem_qfifo_wr_data_1[24], oflux_mem_qfifo_wr_data_1[23], oflux_mem_qfifo_wr_data_1[22], oflux_mem_qfifo_wr_data_1[21], oflux_mem_qfifo_wr_data_1[20], oflux_mem_qfifo_wr_data_1[19], oflux_mem_qfifo_wr_data_1[18], oflux_mem_qfifo_wr_data_1[17], oflux_mem_qfifo_wr_data_1[16], oflux_mem_qfifo_wr_data_1[15], oflux_mem_qfifo_wr_data_1[14], oflux_mem_qfifo_wr_data_1[13], oflux_mem_qfifo_wr_data_1[12], oflux_mem_qfifo_wr_data_1[11], oflux_mem_qfifo_wr_data_1[10], oflux_mem_qfifo_wr_data_1[9], oflux_mem_qfifo_wr_data_1[8], oflux_mem_qfifo_wr_data_1[7], oflux_mem_qfifo_wr_data_1[6], oflux_mem_qfifo_wr_data_1[5], oflux_mem_qfifo_wr_data_1[4], oflux_mem_qfifo_wr_data_1[3], oflux_mem_qfifo_wr_data_1[2], oflux_mem_qfifo_wr_data_1[1], oflux_mem_qfifo_wr_data_1[0] }),
		.oflux_mem_qfifo_wr_en(oflux_mem_qfifo_wr_en_1),
		.oflux_mem_tracememaddr({ oflux_mem_TraceMemAddr_1[8], oflux_mem_TraceMemAddr_1[7], oflux_mem_TraceMemAddr_1[6], oflux_mem_TraceMemAddr_1[5], oflux_mem_TraceMemAddr_1[4], oflux_mem_TraceMemAddr_1[3], oflux_mem_TraceMemAddr_1[2], oflux_mem_TraceMemAddr_1[1], oflux_mem_TraceMemAddr_1[0] }),
		.oflux_mem_tracememen(oflux_mem_TraceMemEn_1),
		.oflux_mem_tracememwr(oflux_mem_TraceMemWr_1),
		.oflux_mem_tracememwrdata({ oflux_mem_TraceMemWrData_1[31], oflux_mem_TraceMemWrData_1[30], oflux_mem_TraceMemWrData_1[29], oflux_mem_TraceMemWrData_1[28], oflux_mem_TraceMemWrData_1[27], oflux_mem_TraceMemWrData_1[26], oflux_mem_TraceMemWrData_1[25], oflux_mem_TraceMemWrData_1[24], oflux_mem_TraceMemWrData_1[23], oflux_mem_TraceMemWrData_1[22], oflux_mem_TraceMemWrData_1[21], oflux_mem_TraceMemWrData_1[20], oflux_mem_TraceMemWrData_1[19], oflux_mem_TraceMemWrData_1[18], oflux_mem_TraceMemWrData_1[17], oflux_mem_TraceMemWrData_1[16], oflux_mem_TraceMemWrData_1[15], oflux_mem_TraceMemWrData_1[14], oflux_mem_TraceMemWrData_1[13], oflux_mem_TraceMemWrData_1[12], oflux_mem_TraceMemWrData_1[11], oflux_mem_TraceMemWrData_1[10], oflux_mem_TraceMemWrData_1[9], oflux_mem_TraceMemWrData_1[8], oflux_mem_TraceMemWrData_1[7], oflux_mem_TraceMemWrData_1[6], oflux_mem_TraceMemWrData_1[5], oflux_mem_TraceMemWrData_1[4], oflux_mem_TraceMemWrData_1[3], oflux_mem_TraceMemWrData_1[2], oflux_mem_TraceMemWrData_1[1], oflux_mem_TraceMemWrData_1[0] })
	);

	tennm_sm_ux_toolbox #(
		.ch0_clkrx_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch0_clkrx_refclk_cssm_fw_control),
		.ch0_clkrx_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch0_clkrx_refclk_sector_specifies_refclk_ready),
		.ch0_dr_enabled(x_std_sm_ux_toolbox_0__ch0_dr_enabled),
		.ch0_flux_mode(x_std_sm_ux_toolbox_0__ch0_flux_mode),
		.ch0_lc_postdiv_sel(x_std_sm_ux_toolbox_0__ch0_lc_postdiv_sel),
		.ch0_local_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch0_local_refclk_cssm_fw_control),
		.ch0_local_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch0_local_refclk_sector_specifies_refclk_ready),
		.ch0_loopback_mode(x_std_sm_ux_toolbox_0__ch0_loopback_mode),
		.ch0_rst_mux_static_sel(x_std_sm_ux_toolbox_0__ch0_rst_mux_static_sel),
		.ch0_rx_dl_enable(x_std_sm_ux_toolbox_0__ch0_rx_dl_enable),
		.ch0_rx_dl_rx_lat_bit_for_async(x_std_sm_ux_toolbox_0__ch0_rx_dl_rx_lat_bit_for_async),
		.ch0_rx_dl_rxbit_cntr_pma(x_std_sm_ux_toolbox_0__ch0_rx_dl_rxbit_cntr_pma),
		.ch0_rx_dl_rxbit_rollover(x_std_sm_ux_toolbox_0__ch0_rx_dl_rxbit_rollover),
		.ch0_rx_fec_type_used(x_std_sm_ux_toolbox_0__ch0_rx_fec_type_used),
		.ch0_rx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch0_rx_preloaded_hardware_configs),
		.ch0_rx_protocol_hint(x_std_sm_ux_toolbox_0__ch0_rx_protocol_hint),
		.ch0_rx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch0_rx_user1_clk_mux_dynamic_sel),
		.ch0_rx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch0_rx_user2_clk_mux_dynamic_sel),
		.ch0_rx_width(x_std_sm_ux_toolbox_0__ch0_rx_width),
		.ch0_sequencer_reg_en(x_std_sm_ux_toolbox_0__ch0_sequencer_reg_en),
		.ch0_tx_bond_size(x_std_sm_ux_toolbox_0__ch0_tx_bond_size),
		.ch0_tx_bonding_category(x_std_sm_ux_toolbox_0__ch0_tx_bonding_category),
		.ch0_tx_dl_enable(x_std_sm_ux_toolbox_0__ch0_tx_dl_enable),
		.ch0_tx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch0_tx_preloaded_hardware_configs),
		.ch0_tx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch0_tx_user1_clk_mux_dynamic_sel),
		.ch0_tx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch0_tx_user2_clk_mux_dynamic_sel),
		.ch1_clkrx_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch1_clkrx_refclk_cssm_fw_control),
		.ch1_clkrx_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch1_clkrx_refclk_sector_specifies_refclk_ready),
		.ch1_dr_enabled(x_std_sm_ux_toolbox_0__ch1_dr_enabled),
		.ch1_flux_mode(x_std_sm_ux_toolbox_0__ch1_flux_mode),
		.ch1_lc_postdiv_sel(x_std_sm_ux_toolbox_0__ch1_lc_postdiv_sel),
		.ch1_local_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch1_local_refclk_cssm_fw_control),
		.ch1_local_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch1_local_refclk_sector_specifies_refclk_ready),
		.ch1_loopback_mode(x_std_sm_ux_toolbox_0__ch1_loopback_mode),
		.ch1_rst_mux_static_sel(x_std_sm_ux_toolbox_0__ch1_rst_mux_static_sel),
		.ch1_rx_dl_enable(x_std_sm_ux_toolbox_0__ch1_rx_dl_enable),
		.ch1_rx_dl_rx_lat_bit_for_async(x_std_sm_ux_toolbox_0__ch1_rx_dl_rx_lat_bit_for_async),
		.ch1_rx_dl_rxbit_cntr_pma(x_std_sm_ux_toolbox_0__ch1_rx_dl_rxbit_cntr_pma),
		.ch1_rx_dl_rxbit_rollover(x_std_sm_ux_toolbox_0__ch1_rx_dl_rxbit_rollover),
		.ch1_rx_fec_type_used(x_std_sm_ux_toolbox_0__ch1_rx_fec_type_used),
		.ch1_rx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch1_rx_preloaded_hardware_configs),
		.ch1_rx_protocol_hint(x_std_sm_ux_toolbox_0__ch1_rx_protocol_hint),
		.ch1_rx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch1_rx_user1_clk_mux_dynamic_sel),
		.ch1_rx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch1_rx_user2_clk_mux_dynamic_sel),
		.ch1_rx_width(x_std_sm_ux_toolbox_0__ch1_rx_width),
		.ch1_sequencer_reg_en(x_std_sm_ux_toolbox_0__ch1_sequencer_reg_en),
		.ch1_tx_bond_size(x_std_sm_ux_toolbox_0__ch1_tx_bond_size),
		.ch1_tx_bonding_category(x_std_sm_ux_toolbox_0__ch1_tx_bonding_category),
		.ch1_tx_dl_enable(x_std_sm_ux_toolbox_0__ch1_tx_dl_enable),
		.ch1_tx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch1_tx_preloaded_hardware_configs),
		.ch1_tx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch1_tx_user1_clk_mux_dynamic_sel),
		.ch1_tx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch1_tx_user2_clk_mux_dynamic_sel),
		.ch2_clkrx_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch2_clkrx_refclk_cssm_fw_control),
		.ch2_clkrx_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch2_clkrx_refclk_sector_specifies_refclk_ready),
		.ch2_dr_enabled(x_std_sm_ux_toolbox_0__ch2_dr_enabled),
		.ch2_flux_mode(x_std_sm_ux_toolbox_0__ch2_flux_mode),
		.ch2_lc_postdiv_sel(x_std_sm_ux_toolbox_0__ch2_lc_postdiv_sel),
		.ch2_local_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch2_local_refclk_cssm_fw_control),
		.ch2_local_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch2_local_refclk_sector_specifies_refclk_ready),
		.ch2_loopback_mode(x_std_sm_ux_toolbox_0__ch2_loopback_mode),
		.ch2_rst_mux_static_sel(x_std_sm_ux_toolbox_0__ch2_rst_mux_static_sel),
		.ch2_rx_dl_enable(x_std_sm_ux_toolbox_0__ch2_rx_dl_enable),
		.ch2_rx_dl_rx_lat_bit_for_async(x_std_sm_ux_toolbox_0__ch2_rx_dl_rx_lat_bit_for_async),
		.ch2_rx_dl_rxbit_cntr_pma(x_std_sm_ux_toolbox_0__ch2_rx_dl_rxbit_cntr_pma),
		.ch2_rx_dl_rxbit_rollover(x_std_sm_ux_toolbox_0__ch2_rx_dl_rxbit_rollover),
		.ch2_rx_fec_type_used(x_std_sm_ux_toolbox_0__ch2_rx_fec_type_used),
		.ch2_rx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch2_rx_preloaded_hardware_configs),
		.ch2_rx_protocol_hint(x_std_sm_ux_toolbox_0__ch2_rx_protocol_hint),
		.ch2_rx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch2_rx_user1_clk_mux_dynamic_sel),
		.ch2_rx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch2_rx_user2_clk_mux_dynamic_sel),
		.ch2_rx_width(x_std_sm_ux_toolbox_0__ch2_rx_width),
		.ch2_sequencer_reg_en(x_std_sm_ux_toolbox_0__ch2_sequencer_reg_en),
		.ch2_tx_bond_size(x_std_sm_ux_toolbox_0__ch2_tx_bond_size),
		.ch2_tx_bonding_category(x_std_sm_ux_toolbox_0__ch2_tx_bonding_category),
		.ch2_tx_dl_enable(x_std_sm_ux_toolbox_0__ch2_tx_dl_enable),
		.ch2_tx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch2_tx_preloaded_hardware_configs),
		.ch2_tx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch2_tx_user1_clk_mux_dynamic_sel),
		.ch2_tx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch2_tx_user2_clk_mux_dynamic_sel),
		.ch3_clkrx_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch3_clkrx_refclk_cssm_fw_control),
		.ch3_clkrx_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch3_clkrx_refclk_sector_specifies_refclk_ready),
		.ch3_dr_enabled(x_std_sm_ux_toolbox_0__ch3_dr_enabled),
		.ch3_flux_mode(x_std_sm_ux_toolbox_0__ch3_flux_mode),
		.ch3_lc_postdiv_sel(x_std_sm_ux_toolbox_0__ch3_lc_postdiv_sel),
		.ch3_local_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch3_local_refclk_cssm_fw_control),
		.ch3_local_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch3_local_refclk_sector_specifies_refclk_ready),
		.ch3_loopback_mode(x_std_sm_ux_toolbox_0__ch3_loopback_mode),
		.ch3_rst_mux_static_sel(x_std_sm_ux_toolbox_0__ch3_rst_mux_static_sel),
		.ch3_rx_dl_enable(x_std_sm_ux_toolbox_0__ch3_rx_dl_enable),
		.ch3_rx_dl_rx_lat_bit_for_async(x_std_sm_ux_toolbox_0__ch3_rx_dl_rx_lat_bit_for_async),
		.ch3_rx_dl_rxbit_cntr_pma(x_std_sm_ux_toolbox_0__ch3_rx_dl_rxbit_cntr_pma),
		.ch3_rx_dl_rxbit_rollover(x_std_sm_ux_toolbox_0__ch3_rx_dl_rxbit_rollover),
		.ch3_rx_fec_type_used(x_std_sm_ux_toolbox_0__ch3_rx_fec_type_used),
		.ch3_rx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch3_rx_preloaded_hardware_configs),
		.ch3_rx_protocol_hint(x_std_sm_ux_toolbox_0__ch3_rx_protocol_hint),
		.ch3_rx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch3_rx_user1_clk_mux_dynamic_sel),
		.ch3_rx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch3_rx_user2_clk_mux_dynamic_sel),
		.ch3_rx_width(x_std_sm_ux_toolbox_0__ch3_rx_width),
		.ch3_sequencer_reg_en(x_std_sm_ux_toolbox_0__ch3_sequencer_reg_en),
		.ch3_tx_bond_size(x_std_sm_ux_toolbox_0__ch3_tx_bond_size),
		.ch3_tx_bonding_category(x_std_sm_ux_toolbox_0__ch3_tx_bonding_category),
		.ch3_tx_dl_enable(x_std_sm_ux_toolbox_0__ch3_tx_dl_enable),
		.ch3_tx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch3_tx_preloaded_hardware_configs),
		.ch3_tx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch3_tx_user1_clk_mux_dynamic_sel),
		.ch3_tx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch3_tx_user2_clk_mux_dynamic_sel),
		.ch0_rx_invert_pin(x_std_sm_ux_toolbox_0__ch0_rx_invert_pin_atom),
        .ch1_rx_invert_pin(x_std_sm_ux_toolbox_0__ch1_rx_invert_pin_atom),
        .ch2_rx_invert_pin(x_std_sm_ux_toolbox_0__ch2_rx_invert_pin_atom),
        .ch3_rx_invert_pin(x_std_sm_ux_toolbox_0__ch3_rx_invert_pin_atom),
        .ch0_tx_invert_pin(x_std_sm_ux_toolbox_0__ch0_tx_invert_pin_atom),
        .ch1_tx_invert_pin(x_std_sm_ux_toolbox_0__ch1_tx_invert_pin_atom),
        .ch2_tx_invert_pin(x_std_sm_ux_toolbox_0__ch2_tx_invert_pin_atom),
        .ch3_tx_invert_pin(x_std_sm_ux_toolbox_0__ch3_tx_invert_pin_atom),
        .ch0_vsr_mode(x_std_sm_ux_toolbox_0__ch0_vsr_mode_atom     ),
        .ch1_vsr_mode(x_std_sm_ux_toolbox_0__ch1_vsr_mode_atom     ),
        .ch2_vsr_mode(x_std_sm_ux_toolbox_0__ch2_vsr_mode_atom     ),
        .ch3_vsr_mode(x_std_sm_ux_toolbox_0__ch3_vsr_mode_atom     )
	) x_std_sm_ux_toolbox_0 (
		.i_ch0_lavmm_addr({ x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[19], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[18], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[17], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[16], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[15], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[14], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[13], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[12], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[11], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[10], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[9], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[8], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[7], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[6], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[5], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[4], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[3], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[2], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[1], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[0] }),
		.i_ch0_lavmm_be({ x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[3], x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[2], x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[1], x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[0] }),
		.i_ch0_lavmm_clk(x_std_sm_ux_toolbox_0__i_ch0_lavmm_clk_1),
		.i_ch0_lavmm_read(x_std_sm_ux_toolbox_0__i_ch0_lavmm_read_1),
		.i_ch0_lavmm_rstn(x_std_sm_ux_toolbox_0__i_ch0_lavmm_rstn_1),
		.i_ch0_lavmm_wdata({ x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[31], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[30], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[29], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[28], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[27], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[26], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[25], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[24], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[23], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[22], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[21], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[20], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[19], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[18], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[17], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[16], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[15], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[14], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[13], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[12], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[11], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[10], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[9], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[8], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[7], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[6], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[5], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[4], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[3], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[2], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[1], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[0] }),
		.i_ch0_lavmm_write(x_std_sm_ux_toolbox_0__i_ch0_lavmm_write_1),
		.i_ch1_lavmm_addr({ x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[19], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[18], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[17], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[16], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[15], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[14], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[13], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[12], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[11], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[10], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[9], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[8], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[7], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[6], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[5], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[4], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[3], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[2], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[1], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[0] }),
		.i_ch1_lavmm_be({ x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[3], x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[2], x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[1], x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[0] }),
		.i_ch1_lavmm_clk(x_std_sm_ux_toolbox_0__i_ch1_lavmm_clk_1),
		.i_ch1_lavmm_read(x_std_sm_ux_toolbox_0__i_ch1_lavmm_read_1),
		.i_ch1_lavmm_rstn(x_std_sm_ux_toolbox_0__i_ch1_lavmm_rstn_1),
		.i_ch1_lavmm_wdata({ x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[31], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[30], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[29], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[28], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[27], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[26], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[25], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[24], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[23], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[22], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[21], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[20], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[19], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[18], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[17], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[16], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[15], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[14], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[13], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[12], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[11], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[10], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[9], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[8], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[7], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[6], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[5], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[4], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[3], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[2], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[1], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[0] }),
		.i_ch1_lavmm_write(x_std_sm_ux_toolbox_0__i_ch1_lavmm_write_1),
		.i_ch2_lavmm_addr({ x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[19], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[18], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[17], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[16], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[15], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[14], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[13], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[12], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[11], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[10], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[9], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[8], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[7], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[6], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[5], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[4], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[3], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[2], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[1], x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr_0[0] }),
		.i_ch2_lavmm_be({ x_std_sm_ux_toolbox_0__i_ch2_lavmm_be_0[3], x_std_sm_ux_toolbox_0__i_ch2_lavmm_be_0[2], x_std_sm_ux_toolbox_0__i_ch2_lavmm_be_0[1], x_std_sm_ux_toolbox_0__i_ch2_lavmm_be_0[0] }),
		.i_ch2_lavmm_clk(x_std_sm_ux_toolbox_0__i_ch2_lavmm_clk_1),
		.i_ch2_lavmm_read(x_std_sm_ux_toolbox_0__i_ch2_lavmm_read_1),
		.i_ch2_lavmm_rstn(x_std_sm_ux_toolbox_0__i_ch2_lavmm_rstn_1),
		.i_ch2_lavmm_wdata({ x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[31], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[30], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[29], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[28], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[27], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[26], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[25], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[24], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[23], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[22], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[21], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[20], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[19], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[18], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[17], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[16], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[15], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[14], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[13], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[12], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[11], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[10], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[9], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[8], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[7], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[6], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[5], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[4], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[3], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[2], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[1], x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata_0[0] }),
		.i_ch2_lavmm_write(x_std_sm_ux_toolbox_0__i_ch2_lavmm_write_1),
		.i_ch3_lavmm_addr({ x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[19], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[18], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[17], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[16], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[15], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[14], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[13], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[12], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[11], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[10], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[9], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[8], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[7], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[6], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[5], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[4], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[3], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[2], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[1], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[0] }),
		.i_ch3_lavmm_be({ x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[3], x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[2], x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[1], x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[0] }),
		.i_ch3_lavmm_clk(x_std_sm_ux_toolbox_0__i_ch3_lavmm_clk_1),
		.i_ch3_lavmm_read(x_std_sm_ux_toolbox_0__i_ch3_lavmm_read_1),
		.i_ch3_lavmm_rstn(x_std_sm_ux_toolbox_0__i_ch3_lavmm_rstn_1),
		.i_ch3_lavmm_wdata({ x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[31], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[30], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[29], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[28], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[27], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[26], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[25], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[24], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[23], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[22], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[21], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[20], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[19], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[18], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[17], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[16], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[15], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[14], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[13], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[12], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[11], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[10], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[9], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[8], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[7], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[6], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[5], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[4], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[3], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[2], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[1], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[0] }),
		.i_ch3_lavmm_write(x_std_sm_ux_toolbox_0__i_ch3_lavmm_write_1),
		.i_dat_pcs_measlatrndtripbit_ch0(x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch0_1),
		.i_dat_pcs_measlatrndtripbit_ch1(x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch1_1),
		.i_dat_pcs_measlatrndtripbit_ch2(x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch2_1),
		.i_dat_pcs_measlatrndtripbit_ch3(x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch3_1),
		.i_flux_apb_prdata({ oflux_ext_pcs_prdata_1[31], oflux_ext_pcs_prdata_1[30], oflux_ext_pcs_prdata_1[29], oflux_ext_pcs_prdata_1[28], oflux_ext_pcs_prdata_1[27], oflux_ext_pcs_prdata_1[26], oflux_ext_pcs_prdata_1[25], oflux_ext_pcs_prdata_1[24], oflux_ext_pcs_prdata_1[23], oflux_ext_pcs_prdata_1[22], oflux_ext_pcs_prdata_1[21], oflux_ext_pcs_prdata_1[20], oflux_ext_pcs_prdata_1[19], oflux_ext_pcs_prdata_1[18], oflux_ext_pcs_prdata_1[17], oflux_ext_pcs_prdata_1[16], oflux_ext_pcs_prdata_1[15], oflux_ext_pcs_prdata_1[14], oflux_ext_pcs_prdata_1[13], oflux_ext_pcs_prdata_1[12], oflux_ext_pcs_prdata_1[11], oflux_ext_pcs_prdata_1[10], oflux_ext_pcs_prdata_1[9], oflux_ext_pcs_prdata_1[8], oflux_ext_pcs_prdata_1[7], oflux_ext_pcs_prdata_1[6], oflux_ext_pcs_prdata_1[5], oflux_ext_pcs_prdata_1[4], oflux_ext_pcs_prdata_1[3], oflux_ext_pcs_prdata_1[2], oflux_ext_pcs_prdata_1[1], oflux_ext_pcs_prdata_1[0] }),
		.i_flux_apb_pready(oflux_ext_pcs_pready_1),
		.i_flux_apb_pslverr(oflux_ext_pcs_pslverr_1),
		.i_ft_rx_sclk_sync_ch0(x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch0_1),
		.i_ft_rx_sclk_sync_ch1(x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch1_1),
		.i_ft_rx_sclk_sync_ch2(x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch2_1),
		.i_ft_rx_sclk_sync_ch3(x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch3_1),
		.i_ft_tx_sclk_sync_ch0(x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch0_1),
		.i_ft_tx_sclk_sync_ch1(x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch1_1),
		.i_ft_tx_sclk_sync_ch2(x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch2_1),
		.i_ft_tx_sclk_sync_ch3(x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch3_1),
		.i_ick_sclk_rx_ch0(x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch0_1),
		.i_ick_sclk_rx_ch1(x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch1_1),
		.i_ick_sclk_rx_ch2(x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch2_1),
		.i_ick_sclk_rx_ch3(x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch3_1),
		.i_octl_pcs_txstatus_ch0_a(x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch0_a_1),
		.i_octl_pcs_txstatus_ch1_a(x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch1_a_1),
		.i_octl_pcs_txstatus_ch2_a(x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch2_a_1),
		.i_octl_pcs_txstatus_ch3_a(x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch3_a_1),
		.i_oflux_cpi_int(oflux_cpi_int_1),
		.i_oflux_int0(oflux_int0_1),
		.i_oflux_int1(oflux_int1_1),
		.i_oflux_int2(oflux_int2_1),
		.i_oflux_int3(oflux_int3_1),
		.i_oflux_srds_rdy0(oflux_srds_rdy0_1),
		.i_oflux_srds_rdy1(oflux_srds_rdy1_1),
		.i_oflux_srds_rdy2(oflux_srds_rdy2_1),
		.i_oflux_srds_rdy3(oflux_srds_rdy3_1),
		.i_pcs_ick_txword_ch0(o_pcs_txword_ch0_0),
		.i_pcs_ick_txword_ch1(o_pcs_txword_ch1_0),
		.i_pcs_ick_txword_ch2(o_pcs_txword_ch2_0),
		.i_pcs_ick_txword_ch3(o_pcs_txword_ch3_0),
		.i_pcs_rxword_ch0(oflux_srds_rx_clk_lane0_1),
		.i_pcs_rxword_ch1(oflux_srds_rx_clk_lane1_1),
		.i_pcs_rxword_ch2(oflux_srds_rx_clk_lane2_1),
		.i_pcs_rxword_ch3(oflux_srds_rx_clk_lane3_1),
		.i_q2q_xcvrrc_ux_ux__txstatus_rc_ux({ x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[3], x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[2], x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[1], x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[0] }),
		.i_rst_ux_rx_pma_rst_n_ch0(x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch0_1),
		.i_rst_ux_rx_pma_rst_n_ch1(x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch1_1),
		.i_rst_ux_rx_pma_rst_n_ch2(x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch2_1),
		.i_rst_ux_rx_pma_rst_n_ch3(x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch3_1),
		.i_rst_ux_tx_pma_rst_n_ch0(x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch0_1),
		.i_rst_ux_tx_pma_rst_n_ch1(x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch1_1),
		.i_rst_ux_tx_pma_rst_n_ch2(x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch2_1),
		.i_rst_ux_tx_pma_rst_n_ch3(x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch3_1),
		.i_sclk_return_sel_rx_ch0(x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch0_1),
		.i_sclk_return_sel_rx_ch1(x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch1_1),
		.i_sclk_return_sel_rx_ch2(x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch2_1),
		.i_sclk_return_sel_rx_ch3(x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch3_1),
		.i_sclk_return_sel_tx_ch0(x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch0_1),
		.i_sclk_return_sel_tx_ch1(x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch1_1),
		.i_sclk_return_sel_tx_ch2(x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch2_1),
		.i_sclk_return_sel_tx_ch3(x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch3_1),
		.i_tx_dl_ch0_bit(x_std_sm_ux_toolbox_0__i_tx_dl_ch0_bit_1),
		.i_tx_dl_ch1_bit(x_std_sm_ux_toolbox_0__i_tx_dl_ch1_bit_1),
		.i_tx_dl_ch2_bit(x_std_sm_ux_toolbox_0__i_tx_dl_ch2_bit_1),
		.i_tx_dl_ch3_bit(x_std_sm_ux_toolbox_0__i_tx_dl_ch3_bit_1),
		.o_ch0_lavmm_rdata({ x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[31], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[30], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[29], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[28], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[27], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[26], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[25], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[24], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[23], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[22], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[21], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[20], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[19], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[18], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[17], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[16], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[15], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[14], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[13], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[12], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[11], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[10], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[9], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[8], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[7], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[6], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[5], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[4], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[3], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[2], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[1], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[0] }),
		.o_ch0_lavmm_rdata_valid(x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_valid_1),
		.o_ch0_lavmm_waitreq(x_std_sm_ux_toolbox_0__o_ch0_lavmm_waitreq_1),
		.o_ch1_lavmm_rdata({ x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[31], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[30], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[29], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[28], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[27], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[26], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[25], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[24], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[23], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[22], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[21], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[20], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[19], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[18], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[17], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[16], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[15], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[14], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[13], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[12], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[11], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[10], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[9], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[8], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[7], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[6], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[5], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[4], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[3], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[2], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[1], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[0] }),
		.o_ch1_lavmm_rdata_valid(x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_valid_1),
		.o_ch1_lavmm_waitreq(x_std_sm_ux_toolbox_0__o_ch1_lavmm_waitreq_1),
		.o_ch2_lavmm_rdata({ x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[31], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[30], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[29], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[28], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[27], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[26], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[25], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[24], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[23], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[22], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[21], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[20], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[19], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[18], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[17], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[16], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[15], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[14], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[13], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[12], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[11], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[10], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[9], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[8], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[7], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[6], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[5], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[4], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[3], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[2], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[1], x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_0[0] }),
		.o_ch2_lavmm_rdata_valid(x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_valid_1),
		.o_ch2_lavmm_waitreq(x_std_sm_ux_toolbox_0__o_ch2_lavmm_waitreq_1),
		.o_ch3_lavmm_rdata({ x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[31], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[30], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[29], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[28], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[27], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[26], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[25], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[24], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[23], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[22], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[21], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[20], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[19], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[18], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[17], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[16], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[15], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[14], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[13], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[12], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[11], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[10], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[9], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[8], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[7], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[6], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[5], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[4], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[3], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[2], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[1], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[0] }),
		.o_ch3_lavmm_rdata_valid(x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_valid_1),
		.o_ch3_lavmm_waitreq(x_std_sm_ux_toolbox_0__o_ch3_lavmm_waitreq_1),
		.o_dat_pcs_measlatbit_ch0(x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch0_1),
		.o_dat_pcs_measlatbit_ch1(x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch1_1),
		.o_dat_pcs_measlatbit_ch2(x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch2_1),
		.o_dat_pcs_measlatbit_ch3(x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch3_1),
		.o_flux_apb_clk(o_flux_apb_clk_0),
		.o_flux_apb_paddr({ o_flux_apb_paddr_0[31], o_flux_apb_paddr_0[30], o_flux_apb_paddr_0[29], o_flux_apb_paddr_0[28], o_flux_apb_paddr_0[27], o_flux_apb_paddr_0[26], o_flux_apb_paddr_0[25], o_flux_apb_paddr_0[24], o_flux_apb_paddr_0[23], o_flux_apb_paddr_0[22], o_flux_apb_paddr_0[21], o_flux_apb_paddr_0[20], o_flux_apb_paddr_0[19], o_flux_apb_paddr_0[18], o_flux_apb_paddr_0[17], o_flux_apb_paddr_0[16], o_flux_apb_paddr_0[15], o_flux_apb_paddr_0[14], o_flux_apb_paddr_0[13], o_flux_apb_paddr_0[12], o_flux_apb_paddr_0[11], o_flux_apb_paddr_0[10], o_flux_apb_paddr_0[9], o_flux_apb_paddr_0[8], o_flux_apb_paddr_0[7], o_flux_apb_paddr_0[6], o_flux_apb_paddr_0[5], o_flux_apb_paddr_0[4], o_flux_apb_paddr_0[3], o_flux_apb_paddr_0[2], o_flux_apb_paddr_0[1], o_flux_apb_paddr_0[0] }),
		.o_flux_apb_penable(o_flux_apb_penable_0),
		.o_flux_apb_pprot({ o_flux_apb_pprot_0[2], o_flux_apb_pprot_0[1], o_flux_apb_pprot_0[0] }),
		.o_flux_apb_psel(o_flux_apb_psel_0),
		.o_flux_apb_pstrb({ o_flux_apb_pstrb_0[3], o_flux_apb_pstrb_0[2], o_flux_apb_pstrb_0[1], o_flux_apb_pstrb_0[0] }),
		.o_flux_apb_pwdata({ o_flux_apb_pwdata_0[31], o_flux_apb_pwdata_0[30], o_flux_apb_pwdata_0[29], o_flux_apb_pwdata_0[28], o_flux_apb_pwdata_0[27], o_flux_apb_pwdata_0[26], o_flux_apb_pwdata_0[25], o_flux_apb_pwdata_0[24], o_flux_apb_pwdata_0[23], o_flux_apb_pwdata_0[22], o_flux_apb_pwdata_0[21], o_flux_apb_pwdata_0[20], o_flux_apb_pwdata_0[19], o_flux_apb_pwdata_0[18], o_flux_apb_pwdata_0[17], o_flux_apb_pwdata_0[16], o_flux_apb_pwdata_0[15], o_flux_apb_pwdata_0[14], o_flux_apb_pwdata_0[13], o_flux_apb_pwdata_0[12], o_flux_apb_pwdata_0[11], o_flux_apb_pwdata_0[10], o_flux_apb_pwdata_0[9], o_flux_apb_pwdata_0[8], o_flux_apb_pwdata_0[7], o_flux_apb_pwdata_0[6], o_flux_apb_pwdata_0[5], o_flux_apb_pwdata_0[4], o_flux_apb_pwdata_0[3], o_flux_apb_pwdata_0[2], o_flux_apb_pwdata_0[1], o_flux_apb_pwdata_0[0] }),
		.o_flux_apb_pwrite(o_flux_apb_pwrite_0),
		.o_flux_apb_rst_n(o_flux_apb_rst_n_0),
		.o_ft_rx_async_pulse_ch0(x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch0_1),
		.o_ft_rx_async_pulse_ch1(x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch1_1),
		.o_ft_rx_async_pulse_ch2(x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch2_1),
		.o_ft_rx_async_pulse_ch3(x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch3_1),
		.o_ft_tx_async_pulse_ch0(x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch0_1),
		.o_ft_tx_async_pulse_ch1(x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch1_1),
		.o_ft_tx_async_pulse_ch2(x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch2_1),
		.o_ft_tx_async_pulse_ch3(x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch3_1),
		.o_ictl_pcs_txenable_ch0_a(x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch0_a_1),
		.o_ictl_pcs_txenable_ch1_a(x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch1_a_1),
		.o_ictl_pcs_txenable_ch2_a(x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch2_a_1),
		.o_ictl_pcs_txenable_ch3_a(x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch3_a_1),
		.o_q2q_xcvrrc_ux_ux__txstatus_ux_rc({ x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[3], x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[2], x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[1], x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[0] }),
		.o_rx_dl_ch0_bit(x_std_sm_ux_toolbox_0__o_rx_dl_ch0_bit_1),
		.o_rx_dl_ch1_bit(x_std_sm_ux_toolbox_0__o_rx_dl_ch1_bit_1),
		.o_rx_dl_ch2_bit(x_std_sm_ux_toolbox_0__o_rx_dl_ch2_bit_1),
		.o_rx_dl_ch3_bit(x_std_sm_ux_toolbox_0__o_rx_dl_ch3_bit_1),
		.o_sync_cfg_data_ch0({ x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[124], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[123], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[122], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[121], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[120], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[119], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[118], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[117], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[116], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[115], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[114], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[113], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[112], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[111], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[110], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[109], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[108], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[107], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[106], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[105], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[104], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[103], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[102], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[101], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[100], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[99], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[98], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[97], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[96], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[95], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[94], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[93], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[92], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[91], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[90], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[89], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[88], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[87], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[86], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[85], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[84], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[83], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[82], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[81], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[80], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[79], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[78], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[77], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[76], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[75], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[74], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[73], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[72], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[71], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[70], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[69], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[68], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[67], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[66], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[65], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[64], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[63], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[62], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[61], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[60], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[59], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[58], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[57], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[56], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[55], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[54], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[53], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[52], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[51], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[50], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[49], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[48], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[47], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[46], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[45], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[44], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[43], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[42], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[41], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[40], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[39], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[38], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[37], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[36], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[35], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[34], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[33], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[32], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[31], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[30], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[29], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[28], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[27], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[26], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[25], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[24], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[23], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[22], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[21], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[20], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[19], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[18], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[17], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[16], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[15], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[14], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[13], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[12], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[11], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[10], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[9], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[8], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[7], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[6], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[5], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[4], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[3], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[2], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[1], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[0] }),
		.o_sync_cfg_data_ch1({ x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[124], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[123], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[122], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[121], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[120], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[119], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[118], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[117], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[116], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[115], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[114], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[113], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[112], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[111], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[110], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[109], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[108], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[107], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[106], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[105], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[104], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[103], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[102], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[101], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[100], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[99], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[98], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[97], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[96], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[95], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[94], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[93], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[92], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[91], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[90], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[89], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[88], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[87], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[86], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[85], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[84], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[83], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[82], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[81], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[80], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[79], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[78], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[77], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[76], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[75], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[74], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[73], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[72], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[71], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[70], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[69], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[68], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[67], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[66], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[65], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[64], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[63], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[62], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[61], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[60], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[59], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[58], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[57], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[56], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[55], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[54], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[53], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[52], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[51], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[50], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[49], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[48], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[47], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[46], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[45], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[44], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[43], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[42], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[41], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[40], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[39], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[38], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[37], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[36], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[35], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[34], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[33], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[32], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[31], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[30], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[29], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[28], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[27], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[26], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[25], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[24], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[23], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[22], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[21], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[20], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[19], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[18], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[17], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[16], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[15], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[14], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[13], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[12], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[11], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[10], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[9], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[8], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[7], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[6], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[5], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[4], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[3], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[2], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[1], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[0] }),
		.o_sync_cfg_data_ch2({ x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[124], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[123], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[122], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[121], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[120], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[119], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[118], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[117], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[116], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[115], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[114], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[113], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[112], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[111], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[110], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[109], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[108], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[107], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[106], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[105], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[104], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[103], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[102], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[101], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[100], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[99], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[98], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[97], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[96], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[95], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[94], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[93], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[92], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[91], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[90], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[89], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[88], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[87], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[86], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[85], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[84], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[83], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[82], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[81], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[80], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[79], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[78], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[77], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[76], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[75], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[74], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[73], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[72], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[71], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[70], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[69], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[68], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[67], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[66], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[65], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[64], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[63], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[62], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[61], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[60], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[59], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[58], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[57], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[56], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[55], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[54], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[53], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[52], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[51], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[50], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[49], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[48], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[47], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[46], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[45], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[44], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[43], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[42], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[41], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[40], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[39], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[38], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[37], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[36], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[35], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[34], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[33], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[32], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[31], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[30], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[29], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[28], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[27], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[26], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[25], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[24], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[23], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[22], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[21], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[20], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[19], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[18], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[17], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[16], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[15], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[14], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[13], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[12], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[11], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[10], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[9], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[8], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[7], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[6], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[5], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[4], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[3], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[2], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[1], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2_0[0] }),
		.o_sync_cfg_data_ch3({ x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[124], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[123], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[122], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[121], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[120], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[119], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[118], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[117], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[116], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[115], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[114], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[113], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[112], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[111], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[110], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[109], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[108], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[107], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[106], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[105], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[104], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[103], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[102], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[101], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[100], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[99], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[98], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[97], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[96], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[95], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[94], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[93], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[92], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[91], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[90], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[89], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[88], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[87], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[86], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[85], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[84], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[83], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[82], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[81], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[80], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[79], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[78], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[77], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[76], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[75], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[74], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[73], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[72], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[71], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[70], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[69], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[68], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[67], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[66], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[65], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[64], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[63], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[62], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[61], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[60], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[59], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[58], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[57], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[56], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[55], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[54], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[53], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[52], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[51], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[50], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[49], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[48], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[47], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[46], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[45], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[44], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[43], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[42], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[41], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[40], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[39], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[38], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[37], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[36], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[35], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[34], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[33], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[32], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[31], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[30], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[29], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[28], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[27], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[26], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[25], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[24], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[23], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[22], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[21], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[20], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[19], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[18], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[17], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[16], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[15], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[14], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[13], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[12], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[11], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[10], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[9], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[8], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[7], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[6], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[5], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[4], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[3], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[2], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[1], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[0] }),
		.o_sync_common_control_ch0({ x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[4], x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[3], x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[2], x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[1], x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[0] }),
		.o_sync_common_control_ch1({ x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[4], x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[3], x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[2], x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[1], x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[0] }),
		.o_sync_common_control_ch2({ x_std_sm_ux_toolbox_0__o_sync_common_control_ch2_0[4], x_std_sm_ux_toolbox_0__o_sync_common_control_ch2_0[3], x_std_sm_ux_toolbox_0__o_sync_common_control_ch2_0[2], x_std_sm_ux_toolbox_0__o_sync_common_control_ch2_0[1], x_std_sm_ux_toolbox_0__o_sync_common_control_ch2_0[0] }),
		.o_sync_common_control_ch3({ x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[4], x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[3], x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[2], x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[1], x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[0] }),
		.o_sync_interface_control_ch0({ x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[249], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[248], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[247], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[246], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[245], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[244], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[243], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[242], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[241], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[240], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[239], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[238], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[237], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[236], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[235], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[234], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[233], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[232], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[231], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[230], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[229], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[228], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[227], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[226], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[225], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[224], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[223], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[222], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[221], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[220], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[219], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[218], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[217], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[216], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[215], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[214], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[213], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[212], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[211], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[210], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[209], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[208], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[207], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[206], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[205], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[204], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[203], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[202], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[201], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[200], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[199], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[198], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[197], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[196], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[195], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[194], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[193], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[192], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[191], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[190], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[189], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[188], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[187], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[186], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[185], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[184], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[183], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[182], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[181], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[180], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[179], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[178], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[177], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[176], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[175], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[174], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[173], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[172], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[171], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[170], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[169], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[168], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[167], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[166], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[165], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[164], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[163], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[162], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[161], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[160], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[159], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[158], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[157], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[156], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[155], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[154], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[153], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[152], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[151], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[150], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[149], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[148], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[147], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[146], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[145], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[144], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[143], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[142], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[141], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[140], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[139], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[138], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[137], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[136], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[135], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[134], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[133], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[132], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[131], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[130], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[129], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[128], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[127], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[126], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[125], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[124], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[123], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[122], 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x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[153], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[152], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[151], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[150], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[149], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[148], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[147], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[146], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[145], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[144], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[143], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[142], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[141], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[140], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[139], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[138], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[137], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[136], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[135], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[134], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[133], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[132], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[131], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[130], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[129], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[128], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[127], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[126], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[125], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[124], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[123], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[122], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[121], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[120], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[119], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[118], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[117], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[116], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[115], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[114], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[113], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[112], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[111], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[110], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[109], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[108], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[107], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[106], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[105], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[104], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[103], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[102], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[101], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[100], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[99], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[98], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[97], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[96], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[95], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[94], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[93], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[92], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[91], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[90], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[89], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[88], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[87], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[86], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[85], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[84], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[83], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[82], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[81], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[80], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[79], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[78], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[77], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[76], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[75], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[74], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[73], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[72], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[71], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[70], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[69], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[68], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[67], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[66], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[65], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[64], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[63], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[62], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[61], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[60], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[59], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[58], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[57], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[56], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[55], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[54], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[53], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[52], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[51], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[50], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[49], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[48], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[47], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[46], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[45], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[44], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[43], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[42], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[41], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[40], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[39], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[38], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[37], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[36], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[35], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[34], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[33], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[32], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[31], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[30], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[29], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[28], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[27], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[26], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[25], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[24], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[23], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[22], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[21], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[20], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[19], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[18], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[17], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[16], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[15], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[14], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[13], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[12], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[11], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[10], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[9], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[8], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[7], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[6], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[5], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[4], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[3], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[2], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[1], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[0] }),
		.o_ux0_rxuser1_sel({ x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel_0[0] }),
		.o_ux0_rxuser2_sel({ x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel_0[0] }),
		.o_ux0_txuser1_sel({ x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel_0[0] }),
		.o_ux0_txuser2_sel({ x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel_0[0] }),
		.o_ux1_rxuser1_sel({ x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel_0[0] }),
		.o_ux1_rxuser2_sel({ x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel_0[0] }),
		.o_ux1_txuser1_sel({ x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel_0[0] }),
		.o_ux1_txuser2_sel({ x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel_0[0] }),
		.o_ux2_rxuser1_sel({ x_std_sm_ux_toolbox_0__o_ux2_rxuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux2_rxuser1_sel_0[0] }),
		.o_ux2_rxuser2_sel({ x_std_sm_ux_toolbox_0__o_ux2_rxuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux2_rxuser2_sel_0[0] }),
		.o_ux2_txuser1_sel({ x_std_sm_ux_toolbox_0__o_ux2_txuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux2_txuser1_sel_0[0] }),
		.o_ux2_txuser2_sel({ x_std_sm_ux_toolbox_0__o_ux2_txuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux2_txuser2_sel_0[0] }),
		.o_ux3_rxuser1_sel({ x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel_0[0] }),
		.o_ux3_rxuser2_sel({ x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel_0[0] }),
		.o_ux3_txuser1_sel({ x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel_0[0] }),
		.o_ux3_txuser2_sel({ x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel_0[0] })
	);

	tennm_ipfluxtop_flux_core_shim_wrap #(
		.ch0_cdr_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_cdr_l_counter),
		.ch0_cdr_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_cdr_refclk_select),
		.ch0_flux_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_flux_mode),
		.ch0_loopback_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_loopback_mode),
		.ch0_pcie_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_pcie_mode),
		.ch0_rx_prbs_monitor_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_prbs_monitor_en),
		.ch0_rx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_prbs_pattern),
		.ch0_rx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_preloaded_hardware_configs),
		.ch0_rx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_sim_mode),
		.ch0_rx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_width),
		.ch0_tx_bonding_category(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_bonding_category),
		.ch0_tx_pll_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_pll_l_counter),
		.ch0_tx_pll_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_pll_refclk_select),
		.ch0_tx_prbs_gen_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_prbs_gen_en),
		.ch0_tx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_prbs_pattern),
		.ch0_tx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_preloaded_hardware_configs),
		.ch0_tx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_sim_mode),
		.ch0_tx_user_clk_only_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_user_clk_only_mode),
		.ch0_tx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_width),
		.ch1_cdr_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_cdr_l_counter),
		.ch1_cdr_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_cdr_refclk_select),
		.ch1_flux_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_flux_mode),
		.ch1_loopback_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_loopback_mode),
		.ch1_pcie_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_pcie_mode),
		.ch1_rx_prbs_monitor_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_prbs_monitor_en),
		.ch1_rx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_prbs_pattern),
		.ch1_rx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_preloaded_hardware_configs),
		.ch1_rx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_sim_mode),
		.ch1_rx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_width),
		.ch1_tx_bonding_category(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_bonding_category),
		.ch1_tx_pll_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_pll_l_counter),
		.ch1_tx_pll_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_pll_refclk_select),
		.ch1_tx_prbs_gen_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_prbs_gen_en),
		.ch1_tx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_prbs_pattern),
		.ch1_tx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_preloaded_hardware_configs),
		.ch1_tx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_sim_mode),
		.ch1_tx_user_clk_only_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_user_clk_only_mode),
		.ch1_tx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_width),
		.ch2_cdr_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_cdr_l_counter),
		.ch2_cdr_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_cdr_refclk_select),
		.ch2_flux_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_flux_mode),
		.ch2_loopback_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_loopback_mode),
		.ch2_pcie_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_pcie_mode),
		.ch2_rx_prbs_monitor_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_prbs_monitor_en),
		.ch2_rx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_prbs_pattern),
		.ch2_rx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_preloaded_hardware_configs),
		.ch2_rx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_sim_mode),
		.ch2_rx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_width),
		.ch2_tx_bonding_category(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_bonding_category),
		.ch2_tx_pll_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_pll_l_counter),
		.ch2_tx_pll_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_pll_refclk_select),
		.ch2_tx_prbs_gen_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_prbs_gen_en),
		.ch2_tx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_prbs_pattern),
		.ch2_tx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_preloaded_hardware_configs),
		.ch2_tx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_sim_mode),
		.ch2_tx_user_clk_only_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_user_clk_only_mode),
		.ch2_tx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_width),
		.ch3_cdr_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_cdr_l_counter),
		.ch3_cdr_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_cdr_refclk_select),
		.ch3_flux_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_flux_mode),
		.ch3_loopback_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_loopback_mode),
		.ch3_pcie_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_pcie_mode),
		.ch3_rx_prbs_monitor_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_prbs_monitor_en),
		.ch3_rx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_prbs_pattern),
		.ch3_rx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_preloaded_hardware_configs),
		.ch3_rx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_sim_mode),
		.ch3_rx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_width),
		.ch3_tx_bonding_category(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_bonding_category),
		.ch3_tx_pll_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_pll_l_counter),
		.ch3_tx_pll_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_pll_refclk_select),
		.ch3_tx_prbs_gen_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_prbs_gen_en),
		.ch3_tx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_prbs_pattern),
		.ch3_tx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_preloaded_hardware_configs),
		.ch3_tx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_sim_mode),
		.ch3_tx_user_clk_only_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_user_clk_only_mode),
		.ch3_tx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_width)
	) x_std_ipfluxtop_flux_core_shim_wrap_0 (
		.car_cpu_bresetn(car_cpu_bresetn_1),
		.car_cpu_clk(car_cpu_clk_1),
		.iflux_ext_car_apb_rstn(o_flux_apb_rst_n_0),
		.iflux_ext_ck_apb_clk(o_flux_apb_clk_0),
		.iflux_ext_cpu_fast_clk(x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ext_cpu_fast_clk_1),
		.iflux_ext_pcs_paddr({ o_flux_apb_paddr_0[31], o_flux_apb_paddr_0[30], o_flux_apb_paddr_0[29], o_flux_apb_paddr_0[28], o_flux_apb_paddr_0[27], o_flux_apb_paddr_0[26], o_flux_apb_paddr_0[25], o_flux_apb_paddr_0[24], o_flux_apb_paddr_0[23], o_flux_apb_paddr_0[22], o_flux_apb_paddr_0[21], o_flux_apb_paddr_0[20], o_flux_apb_paddr_0[19], o_flux_apb_paddr_0[18], o_flux_apb_paddr_0[17], o_flux_apb_paddr_0[16], o_flux_apb_paddr_0[15], o_flux_apb_paddr_0[14], o_flux_apb_paddr_0[13], o_flux_apb_paddr_0[12], o_flux_apb_paddr_0[11], o_flux_apb_paddr_0[10], o_flux_apb_paddr_0[9], o_flux_apb_paddr_0[8], o_flux_apb_paddr_0[7], o_flux_apb_paddr_0[6], o_flux_apb_paddr_0[5], o_flux_apb_paddr_0[4], o_flux_apb_paddr_0[3], o_flux_apb_paddr_0[2], o_flux_apb_paddr_0[1], o_flux_apb_paddr_0[0] }),
		.iflux_ext_pcs_penable(o_flux_apb_penable_0),
		.iflux_ext_pcs_pprot({ o_flux_apb_pprot_0[2], o_flux_apb_pprot_0[1], o_flux_apb_pprot_0[0] }),
		.iflux_ext_pcs_psel(o_flux_apb_psel_0),
		.iflux_ext_pcs_pstrb({ o_flux_apb_pstrb_0[3], o_flux_apb_pstrb_0[2], o_flux_apb_pstrb_0[1], o_flux_apb_pstrb_0[0] }),
		.iflux_ext_pcs_pwdata({ o_flux_apb_pwdata_0[31], o_flux_apb_pwdata_0[30], o_flux_apb_pwdata_0[29], o_flux_apb_pwdata_0[28], o_flux_apb_pwdata_0[27], o_flux_apb_pwdata_0[26], o_flux_apb_pwdata_0[25], o_flux_apb_pwdata_0[24], o_flux_apb_pwdata_0[23], o_flux_apb_pwdata_0[22], o_flux_apb_pwdata_0[21], o_flux_apb_pwdata_0[20], o_flux_apb_pwdata_0[19], o_flux_apb_pwdata_0[18], o_flux_apb_pwdata_0[17], o_flux_apb_pwdata_0[16], o_flux_apb_pwdata_0[15], o_flux_apb_pwdata_0[14], o_flux_apb_pwdata_0[13], o_flux_apb_pwdata_0[12], o_flux_apb_pwdata_0[11], o_flux_apb_pwdata_0[10], o_flux_apb_pwdata_0[9], o_flux_apb_pwdata_0[8], o_flux_apb_pwdata_0[7], o_flux_apb_pwdata_0[6], o_flux_apb_pwdata_0[5], o_flux_apb_pwdata_0[4], o_flux_apb_pwdata_0[3], o_flux_apb_pwdata_0[2], o_flux_apb_pwdata_0[1], o_flux_apb_pwdata_0[0] }),
		.iflux_ext_pcs_pwrite(o_flux_apb_pwrite_0),
		.iflux_ick_pcs_txptr_smpl_clk_l0_lane0(x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane0_1),
		.iflux_ick_pcs_txptr_smpl_clk_l0_lane1(x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane1_1),
		.iflux_ick_pcs_txptr_smpl_clk_l0_lane2(x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane2_1),
		.iflux_ick_pcs_txptr_smpl_clk_l0_lane3(x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane3_1),
		.iflux_ingress_direct_lane0({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[319], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[318], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[317], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[316], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[315], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[314], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[313], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[312], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[311], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[310], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[309], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[308], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[307], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[306], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[305], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[304], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[303], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[302], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[301], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[300], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[299], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[298], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[297], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[296], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[295], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[294], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[293], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[292], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[291], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[290], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[289], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[288], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[287], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[286], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[285], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[284], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[283], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[282], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[281], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[280], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[279], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[278], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[277], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[276], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[275], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[274], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[273], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[272], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[271], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[270], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[269], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[268], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[267], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[266], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[265], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[264], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[263], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[262], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[261], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[260], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[259], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[258], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[257], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[256], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[255], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[254], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[253], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[252], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[251], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[250], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[249], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[248], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[247], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[246], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[245], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[244], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[243], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[242], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[241], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[240], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[239], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[238], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[237], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[236], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[235], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[234], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[233], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[232], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[231], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[230], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[229], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[228], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[227], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[226], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[225], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[224], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[223], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[222], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[221], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[220], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[219], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[218], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[217], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[216], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[215], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[214], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[213], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[212], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[211], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[210], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[209], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[208], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[207], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[206], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[205], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[204], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[203], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[202], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[201], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[200], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[199], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[198], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[197], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[196], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[195], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[194], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[193], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[192], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[191], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[190], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[189], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[188], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[187], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[186], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[185], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[184], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[183], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[182], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[181], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[180], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[179], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[178], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[177], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[176], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[175], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[174], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[173], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[172], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[171], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[170], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[169], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[168], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[167], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[166], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[165], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[164], 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x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[85], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[84], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[83], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[82], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[81], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[80], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[73], 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x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[0] }),
		.iflux_ingress_direct_lane2({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[319], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[318], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[317], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[316], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[315], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[314], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[313], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[312], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[311], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[310], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[309], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[308], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[307], 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		.iflux_ingress_direct_lane3({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[319], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[318], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[317], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[316], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[315], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[314], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[313], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[312], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[311], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[310], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[309], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[308], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[307], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[306], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[305], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[304], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[303], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[302], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[301], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[300], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[299], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[298], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[297], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[296], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[295], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[294], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[293], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[292], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[291], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[290], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[289], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[288], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[287], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[286], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[285], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[284], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[283], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[282], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[281], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[280], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[279], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[278], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[277], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[276], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[275], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[274], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[273], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[272], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[271], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[270], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[269], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[268], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[267], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[266], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[265], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[264], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[263], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[262], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[261], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[260], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[259], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[258], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[257], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[256], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[255], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[254], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[253], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[252], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[251], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[250], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[249], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[248], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[247], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[246], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[245], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[244], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[243], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[242], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[241], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[240], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[239], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[238], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[237], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[236], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[235], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[234], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[233], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[232], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[231], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[230], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[229], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[228], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[227], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[226], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[225], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[224], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[223], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[222], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[221], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[220], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[219], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[218], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[217], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[216], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[215], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[214], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[213], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[212], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[211], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[210], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[209], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[208], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[207], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[206], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[205], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[204], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[203], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[202], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[201], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[200], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[199], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[198], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[197], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[196], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[195], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[194], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[193], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[192], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[191], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[190], 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x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[137], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[136], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[135], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[134], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[133], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[132], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[131], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[130], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[129], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[128], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[127], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[126], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[125], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[124], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[123], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[122], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[121], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[120], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[119], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[118], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[117], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[116], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[115], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[114], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[113], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[112], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[111], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[110], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[109], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[108], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[107], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[106], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[105], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[104], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[103], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[102], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[101], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[100], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[99], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[98], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[97], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[96], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[95], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[94], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[93], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[92], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[91], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[90], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[89], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[88], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[87], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[86], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[85], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[84], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[83], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[82], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[81], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[80], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[0] }),
		.iflux_mem_dram0checkdata({ iflux_mem_DRam0CheckData_0[19], iflux_mem_DRam0CheckData_0[18], iflux_mem_DRam0CheckData_0[17], iflux_mem_DRam0CheckData_0[16], iflux_mem_DRam0CheckData_0[15], iflux_mem_DRam0CheckData_0[14], iflux_mem_DRam0CheckData_0[13], iflux_mem_DRam0CheckData_0[12], iflux_mem_DRam0CheckData_0[11], iflux_mem_DRam0CheckData_0[10], iflux_mem_DRam0CheckData_0[9], iflux_mem_DRam0CheckData_0[8], iflux_mem_DRam0CheckData_0[7], iflux_mem_DRam0CheckData_0[6], iflux_mem_DRam0CheckData_0[5], iflux_mem_DRam0CheckData_0[4], iflux_mem_DRam0CheckData_0[3], iflux_mem_DRam0CheckData_0[2], iflux_mem_DRam0CheckData_0[1], iflux_mem_DRam0CheckData_0[0] }),
		.iflux_mem_dram0data({ iflux_mem_DRam0Data_0[31], iflux_mem_DRam0Data_0[30], iflux_mem_DRam0Data_0[29], iflux_mem_DRam0Data_0[28], iflux_mem_DRam0Data_0[27], iflux_mem_DRam0Data_0[26], iflux_mem_DRam0Data_0[25], iflux_mem_DRam0Data_0[24], iflux_mem_DRam0Data_0[23], iflux_mem_DRam0Data_0[22], iflux_mem_DRam0Data_0[21], iflux_mem_DRam0Data_0[20], iflux_mem_DRam0Data_0[19], iflux_mem_DRam0Data_0[18], iflux_mem_DRam0Data_0[17], iflux_mem_DRam0Data_0[16], iflux_mem_DRam0Data_0[15], iflux_mem_DRam0Data_0[14], iflux_mem_DRam0Data_0[13], iflux_mem_DRam0Data_0[12], iflux_mem_DRam0Data_0[11], iflux_mem_DRam0Data_0[10], iflux_mem_DRam0Data_0[9], iflux_mem_DRam0Data_0[8], iflux_mem_DRam0Data_0[7], iflux_mem_DRam0Data_0[6], iflux_mem_DRam0Data_0[5], iflux_mem_DRam0Data_0[4], iflux_mem_DRam0Data_0[3], iflux_mem_DRam0Data_0[2], iflux_mem_DRam0Data_0[1], iflux_mem_DRam0Data_0[0] }),
		.iflux_mem_iram0checkdata({ iflux_mem_IRam0CheckData_0[6], iflux_mem_IRam0CheckData_0[5], iflux_mem_IRam0CheckData_0[4], iflux_mem_IRam0CheckData_0[3], iflux_mem_IRam0CheckData_0[2], iflux_mem_IRam0CheckData_0[1], iflux_mem_IRam0CheckData_0[0] }),
		.iflux_mem_iram0data({ iflux_mem_IRam0Data_0[31], iflux_mem_IRam0Data_0[30], iflux_mem_IRam0Data_0[29], iflux_mem_IRam0Data_0[28], iflux_mem_IRam0Data_0[27], iflux_mem_IRam0Data_0[26], iflux_mem_IRam0Data_0[25], iflux_mem_IRam0Data_0[24], iflux_mem_IRam0Data_0[23], iflux_mem_IRam0Data_0[22], iflux_mem_IRam0Data_0[21], iflux_mem_IRam0Data_0[20], iflux_mem_IRam0Data_0[19], iflux_mem_IRam0Data_0[18], iflux_mem_IRam0Data_0[17], iflux_mem_IRam0Data_0[16], iflux_mem_IRam0Data_0[15], iflux_mem_IRam0Data_0[14], iflux_mem_IRam0Data_0[13], iflux_mem_IRam0Data_0[12], iflux_mem_IRam0Data_0[11], iflux_mem_IRam0Data_0[10], iflux_mem_IRam0Data_0[9], iflux_mem_IRam0Data_0[8], iflux_mem_IRam0Data_0[7], iflux_mem_IRam0Data_0[6], iflux_mem_IRam0Data_0[5], iflux_mem_IRam0Data_0[4], iflux_mem_IRam0Data_0[3], iflux_mem_IRam0Data_0[2], iflux_mem_IRam0Data_0[1], iflux_mem_IRam0Data_0[0] }),
		.iflux_mem_qfifo_rd_data({ iflux_mem_qfifo_rd_data_0[31], iflux_mem_qfifo_rd_data_0[30], iflux_mem_qfifo_rd_data_0[29], iflux_mem_qfifo_rd_data_0[28], iflux_mem_qfifo_rd_data_0[27], iflux_mem_qfifo_rd_data_0[26], iflux_mem_qfifo_rd_data_0[25], iflux_mem_qfifo_rd_data_0[24], iflux_mem_qfifo_rd_data_0[23], iflux_mem_qfifo_rd_data_0[22], iflux_mem_qfifo_rd_data_0[21], iflux_mem_qfifo_rd_data_0[20], iflux_mem_qfifo_rd_data_0[19], iflux_mem_qfifo_rd_data_0[18], iflux_mem_qfifo_rd_data_0[17], iflux_mem_qfifo_rd_data_0[16], iflux_mem_qfifo_rd_data_0[15], iflux_mem_qfifo_rd_data_0[14], iflux_mem_qfifo_rd_data_0[13], iflux_mem_qfifo_rd_data_0[12], iflux_mem_qfifo_rd_data_0[11], iflux_mem_qfifo_rd_data_0[10], iflux_mem_qfifo_rd_data_0[9], iflux_mem_qfifo_rd_data_0[8], iflux_mem_qfifo_rd_data_0[7], iflux_mem_qfifo_rd_data_0[6], iflux_mem_qfifo_rd_data_0[5], iflux_mem_qfifo_rd_data_0[4], iflux_mem_qfifo_rd_data_0[3], iflux_mem_qfifo_rd_data_0[2], iflux_mem_qfifo_rd_data_0[1], iflux_mem_qfifo_rd_data_0[0] }),
		.iflux_mem_tracememdata({ iflux_mem_TraceMemData_0[31], iflux_mem_TraceMemData_0[30], iflux_mem_TraceMemData_0[29], iflux_mem_TraceMemData_0[28], iflux_mem_TraceMemData_0[27], iflux_mem_TraceMemData_0[26], iflux_mem_TraceMemData_0[25], iflux_mem_TraceMemData_0[24], iflux_mem_TraceMemData_0[23], iflux_mem_TraceMemData_0[22], iflux_mem_TraceMemData_0[21], iflux_mem_TraceMemData_0[20], iflux_mem_TraceMemData_0[19], iflux_mem_TraceMemData_0[18], iflux_mem_TraceMemData_0[17], iflux_mem_TraceMemData_0[16], iflux_mem_TraceMemData_0[15], iflux_mem_TraceMemData_0[14], iflux_mem_TraceMemData_0[13], iflux_mem_TraceMemData_0[12], iflux_mem_TraceMemData_0[11], iflux_mem_TraceMemData_0[10], iflux_mem_TraceMemData_0[9], iflux_mem_TraceMemData_0[8], iflux_mem_TraceMemData_0[7], iflux_mem_TraceMemData_0[6], iflux_mem_TraceMemData_0[5], iflux_mem_TraceMemData_0[4], iflux_mem_TraceMemData_0[3], iflux_mem_TraceMemData_0[2], iflux_mem_TraceMemData_0[1], iflux_mem_TraceMemData_0[0] }),
		.iflux_pcs_txword_lane0({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[0] }),
		.iflux_pcs_txword_lane1({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[0] }),
		.iflux_pcs_txword_lane2({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2_0[0] }),
		.iflux_pcs_txword_lane3({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[0] }),
		.iflux_srds_tx_clk_lane0(o_pcs_txword_ch0_0),
		.iflux_srds_tx_clk_lane1(o_pcs_txword_ch1_0),
		.iflux_srds_tx_clk_lane2(o_pcs_txword_ch2_0),
		.iflux_srds_tx_clk_lane3(o_pcs_txword_ch3_0),
		.oflux_cpi_int(oflux_cpi_int_1),
		.oflux_egress_direct_lane0({ x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[256], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[255], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[254], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[253], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[252], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[251], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[250], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[249], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[248], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[247], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[246], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[245], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[244], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[243], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[242], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[241], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[240], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[239], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[238], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[237], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[236], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[235], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[234], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[233], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[232], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[231], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[230], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[229], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[228], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[227], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[226], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[225], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[224], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[223], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[222], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[221], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[220], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[219], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[218], 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x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[204], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[203], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[202], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[201], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[200], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[199], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[198], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[197], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[196], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[195], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[194], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[193], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[192], 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x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[165], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[164], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[163], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[162], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[161], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[160], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[159], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[158], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[157], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[156], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[155], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[154], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[153], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[152], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[151], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[150], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[149], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[148], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[147], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[146], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[145], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[144], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[143], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[142], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[141], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[140], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[139], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[138], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[137], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[136], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[135], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[134], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[133], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[132], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[131], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[130], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[129], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[128], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[127], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[126], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[125], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[124], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[123], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[122], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[121], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[120], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[119], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[118], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[117], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[116], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[115], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[114], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[113], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[112], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[111], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[110], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[109], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[108], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[107], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[106], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[105], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[104], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[103], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[102], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[101], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[100], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[99], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[98], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[97], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[96], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[95], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[94], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[93], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[92], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[91], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[90], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[89], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[88], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[87], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[86], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[85], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[84], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[83], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[82], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[81], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[80], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[0] }),
		.oflux_ext_pcs_prdata({ oflux_ext_pcs_prdata_1[31], oflux_ext_pcs_prdata_1[30], oflux_ext_pcs_prdata_1[29], oflux_ext_pcs_prdata_1[28], oflux_ext_pcs_prdata_1[27], oflux_ext_pcs_prdata_1[26], oflux_ext_pcs_prdata_1[25], oflux_ext_pcs_prdata_1[24], oflux_ext_pcs_prdata_1[23], oflux_ext_pcs_prdata_1[22], oflux_ext_pcs_prdata_1[21], oflux_ext_pcs_prdata_1[20], oflux_ext_pcs_prdata_1[19], oflux_ext_pcs_prdata_1[18], oflux_ext_pcs_prdata_1[17], oflux_ext_pcs_prdata_1[16], oflux_ext_pcs_prdata_1[15], oflux_ext_pcs_prdata_1[14], oflux_ext_pcs_prdata_1[13], oflux_ext_pcs_prdata_1[12], oflux_ext_pcs_prdata_1[11], oflux_ext_pcs_prdata_1[10], oflux_ext_pcs_prdata_1[9], oflux_ext_pcs_prdata_1[8], oflux_ext_pcs_prdata_1[7], oflux_ext_pcs_prdata_1[6], oflux_ext_pcs_prdata_1[5], oflux_ext_pcs_prdata_1[4], oflux_ext_pcs_prdata_1[3], oflux_ext_pcs_prdata_1[2], oflux_ext_pcs_prdata_1[1], oflux_ext_pcs_prdata_1[0] }),
		.oflux_ext_pcs_pready(oflux_ext_pcs_pready_1),
		.oflux_ext_pcs_pslverr(oflux_ext_pcs_pslverr_1),
		.oflux_int0(oflux_int0_1),
		.oflux_int1(oflux_int1_1),
		.oflux_int2(oflux_int2_1),
		.oflux_int3(oflux_int3_1),
		.oflux_mem_dram0addr({ oflux_mem_DRam0Addr_1[15], oflux_mem_DRam0Addr_1[14], oflux_mem_DRam0Addr_1[13], oflux_mem_DRam0Addr_1[12], oflux_mem_DRam0Addr_1[11], oflux_mem_DRam0Addr_1[10], oflux_mem_DRam0Addr_1[9], oflux_mem_DRam0Addr_1[8], oflux_mem_DRam0Addr_1[7], oflux_mem_DRam0Addr_1[6], oflux_mem_DRam0Addr_1[5], oflux_mem_DRam0Addr_1[4], oflux_mem_DRam0Addr_1[3], oflux_mem_DRam0Addr_1[2] }),
		.oflux_mem_dram0byteen({ oflux_mem_DRam0ByteEn_1[3], oflux_mem_DRam0ByteEn_1[2], oflux_mem_DRam0ByteEn_1[1], oflux_mem_DRam0ByteEn_1[0] }),
		.oflux_mem_dram0checkwrdata({ oflux_mem_DRam0CheckWrData_1[19], oflux_mem_DRam0CheckWrData_1[18], oflux_mem_DRam0CheckWrData_1[17], oflux_mem_DRam0CheckWrData_1[16], oflux_mem_DRam0CheckWrData_1[15], oflux_mem_DRam0CheckWrData_1[14], oflux_mem_DRam0CheckWrData_1[13], oflux_mem_DRam0CheckWrData_1[12], oflux_mem_DRam0CheckWrData_1[11], oflux_mem_DRam0CheckWrData_1[10], oflux_mem_DRam0CheckWrData_1[9], oflux_mem_DRam0CheckWrData_1[8], oflux_mem_DRam0CheckWrData_1[7], oflux_mem_DRam0CheckWrData_1[6], oflux_mem_DRam0CheckWrData_1[5], oflux_mem_DRam0CheckWrData_1[4], oflux_mem_DRam0CheckWrData_1[3], oflux_mem_DRam0CheckWrData_1[2], oflux_mem_DRam0CheckWrData_1[1], oflux_mem_DRam0CheckWrData_1[0] }),
		.oflux_mem_dram0en(oflux_mem_DRam0En_1),
		.oflux_mem_dram0wr(oflux_mem_DRam0Wr_1),
		.oflux_mem_dram0wrdata({ oflux_mem_DRam0WrData_1[31], oflux_mem_DRam0WrData_1[30], oflux_mem_DRam0WrData_1[29], oflux_mem_DRam0WrData_1[28], oflux_mem_DRam0WrData_1[27], oflux_mem_DRam0WrData_1[26], oflux_mem_DRam0WrData_1[25], oflux_mem_DRam0WrData_1[24], oflux_mem_DRam0WrData_1[23], oflux_mem_DRam0WrData_1[22], oflux_mem_DRam0WrData_1[21], oflux_mem_DRam0WrData_1[20], oflux_mem_DRam0WrData_1[19], oflux_mem_DRam0WrData_1[18], oflux_mem_DRam0WrData_1[17], oflux_mem_DRam0WrData_1[16], oflux_mem_DRam0WrData_1[15], oflux_mem_DRam0WrData_1[14], oflux_mem_DRam0WrData_1[13], oflux_mem_DRam0WrData_1[12], oflux_mem_DRam0WrData_1[11], oflux_mem_DRam0WrData_1[10], oflux_mem_DRam0WrData_1[9], oflux_mem_DRam0WrData_1[8], oflux_mem_DRam0WrData_1[7], oflux_mem_DRam0WrData_1[6], oflux_mem_DRam0WrData_1[5], oflux_mem_DRam0WrData_1[4], oflux_mem_DRam0WrData_1[3], oflux_mem_DRam0WrData_1[2], oflux_mem_DRam0WrData_1[1], oflux_mem_DRam0WrData_1[0] }),
		.oflux_mem_iram0addr({ oflux_mem_IRam0Addr_1[16], oflux_mem_IRam0Addr_1[15], oflux_mem_IRam0Addr_1[14], oflux_mem_IRam0Addr_1[13], oflux_mem_IRam0Addr_1[12], oflux_mem_IRam0Addr_1[11], oflux_mem_IRam0Addr_1[10], oflux_mem_IRam0Addr_1[9], oflux_mem_IRam0Addr_1[8], oflux_mem_IRam0Addr_1[7], oflux_mem_IRam0Addr_1[6], oflux_mem_IRam0Addr_1[5], oflux_mem_IRam0Addr_1[4], oflux_mem_IRam0Addr_1[3], oflux_mem_IRam0Addr_1[2] }),
		.oflux_mem_iram0checkwrdata({ oflux_mem_IRam0CheckWrData_1[6], oflux_mem_IRam0CheckWrData_1[5], oflux_mem_IRam0CheckWrData_1[4], oflux_mem_IRam0CheckWrData_1[3], oflux_mem_IRam0CheckWrData_1[2], oflux_mem_IRam0CheckWrData_1[1], oflux_mem_IRam0CheckWrData_1[0] }),
		.oflux_mem_iram0en(oflux_mem_IRam0En_1),
		.oflux_mem_iram0wr(oflux_mem_IRam0Wr_1),
		.oflux_mem_iram0wrdata({ oflux_mem_IRam0WrData_1[31], oflux_mem_IRam0WrData_1[30], oflux_mem_IRam0WrData_1[29], oflux_mem_IRam0WrData_1[28], oflux_mem_IRam0WrData_1[27], oflux_mem_IRam0WrData_1[26], oflux_mem_IRam0WrData_1[25], oflux_mem_IRam0WrData_1[24], oflux_mem_IRam0WrData_1[23], oflux_mem_IRam0WrData_1[22], oflux_mem_IRam0WrData_1[21], oflux_mem_IRam0WrData_1[20], oflux_mem_IRam0WrData_1[19], oflux_mem_IRam0WrData_1[18], oflux_mem_IRam0WrData_1[17], oflux_mem_IRam0WrData_1[16], oflux_mem_IRam0WrData_1[15], oflux_mem_IRam0WrData_1[14], oflux_mem_IRam0WrData_1[13], oflux_mem_IRam0WrData_1[12], oflux_mem_IRam0WrData_1[11], oflux_mem_IRam0WrData_1[10], oflux_mem_IRam0WrData_1[9], oflux_mem_IRam0WrData_1[8], oflux_mem_IRam0WrData_1[7], oflux_mem_IRam0WrData_1[6], oflux_mem_IRam0WrData_1[5], oflux_mem_IRam0WrData_1[4], oflux_mem_IRam0WrData_1[3], oflux_mem_IRam0WrData_1[2], oflux_mem_IRam0WrData_1[1], oflux_mem_IRam0WrData_1[0] }),
		.oflux_mem_qfifo_rd_addr({ oflux_mem_qfifo_rd_addr_1[8], oflux_mem_qfifo_rd_addr_1[7], oflux_mem_qfifo_rd_addr_1[6], oflux_mem_qfifo_rd_addr_1[5], oflux_mem_qfifo_rd_addr_1[4], oflux_mem_qfifo_rd_addr_1[3], oflux_mem_qfifo_rd_addr_1[2], oflux_mem_qfifo_rd_addr_1[1], oflux_mem_qfifo_rd_addr_1[0] }),
		.oflux_mem_qfifo_rd_en(oflux_mem_qfifo_rd_en_1),
		.oflux_mem_qfifo_wr_addr({ oflux_mem_qfifo_wr_addr_1[8], oflux_mem_qfifo_wr_addr_1[7], oflux_mem_qfifo_wr_addr_1[6], oflux_mem_qfifo_wr_addr_1[5], oflux_mem_qfifo_wr_addr_1[4], oflux_mem_qfifo_wr_addr_1[3], oflux_mem_qfifo_wr_addr_1[2], oflux_mem_qfifo_wr_addr_1[1], oflux_mem_qfifo_wr_addr_1[0] }),
		.oflux_mem_qfifo_wr_data({ oflux_mem_qfifo_wr_data_1[31], oflux_mem_qfifo_wr_data_1[30], oflux_mem_qfifo_wr_data_1[29], oflux_mem_qfifo_wr_data_1[28], oflux_mem_qfifo_wr_data_1[27], oflux_mem_qfifo_wr_data_1[26], oflux_mem_qfifo_wr_data_1[25], oflux_mem_qfifo_wr_data_1[24], oflux_mem_qfifo_wr_data_1[23], oflux_mem_qfifo_wr_data_1[22], oflux_mem_qfifo_wr_data_1[21], oflux_mem_qfifo_wr_data_1[20], oflux_mem_qfifo_wr_data_1[19], oflux_mem_qfifo_wr_data_1[18], oflux_mem_qfifo_wr_data_1[17], oflux_mem_qfifo_wr_data_1[16], oflux_mem_qfifo_wr_data_1[15], oflux_mem_qfifo_wr_data_1[14], oflux_mem_qfifo_wr_data_1[13], oflux_mem_qfifo_wr_data_1[12], oflux_mem_qfifo_wr_data_1[11], oflux_mem_qfifo_wr_data_1[10], oflux_mem_qfifo_wr_data_1[9], oflux_mem_qfifo_wr_data_1[8], oflux_mem_qfifo_wr_data_1[7], oflux_mem_qfifo_wr_data_1[6], oflux_mem_qfifo_wr_data_1[5], oflux_mem_qfifo_wr_data_1[4], oflux_mem_qfifo_wr_data_1[3], oflux_mem_qfifo_wr_data_1[2], oflux_mem_qfifo_wr_data_1[1], oflux_mem_qfifo_wr_data_1[0] }),
		.oflux_mem_qfifo_wr_en(oflux_mem_qfifo_wr_en_1),
		.oflux_mem_tracememaddr({ oflux_mem_TraceMemAddr_1[8], oflux_mem_TraceMemAddr_1[7], oflux_mem_TraceMemAddr_1[6], oflux_mem_TraceMemAddr_1[5], oflux_mem_TraceMemAddr_1[4], oflux_mem_TraceMemAddr_1[3], oflux_mem_TraceMemAddr_1[2], oflux_mem_TraceMemAddr_1[1], oflux_mem_TraceMemAddr_1[0] }),
		.oflux_mem_tracememen(oflux_mem_TraceMemEn_1),
		.oflux_mem_tracememwr(oflux_mem_TraceMemWr_1),
		.oflux_mem_tracememwrdata({ oflux_mem_TraceMemWrData_1[31], oflux_mem_TraceMemWrData_1[30], oflux_mem_TraceMemWrData_1[29], oflux_mem_TraceMemWrData_1[28], oflux_mem_TraceMemWrData_1[27], oflux_mem_TraceMemWrData_1[26], oflux_mem_TraceMemWrData_1[25], oflux_mem_TraceMemWrData_1[24], oflux_mem_TraceMemWrData_1[23], oflux_mem_TraceMemWrData_1[22], oflux_mem_TraceMemWrData_1[21], oflux_mem_TraceMemWrData_1[20], oflux_mem_TraceMemWrData_1[19], oflux_mem_TraceMemWrData_1[18], oflux_mem_TraceMemWrData_1[17], oflux_mem_TraceMemWrData_1[16], oflux_mem_TraceMemWrData_1[15], oflux_mem_TraceMemWrData_1[14], oflux_mem_TraceMemWrData_1[13], oflux_mem_TraceMemWrData_1[12], oflux_mem_TraceMemWrData_1[11], oflux_mem_TraceMemWrData_1[10], oflux_mem_TraceMemWrData_1[9], oflux_mem_TraceMemWrData_1[8], oflux_mem_TraceMemWrData_1[7], oflux_mem_TraceMemWrData_1[6], oflux_mem_TraceMemWrData_1[5], oflux_mem_TraceMemWrData_1[4], oflux_mem_TraceMemWrData_1[3], oflux_mem_TraceMemWrData_1[2], oflux_mem_TraceMemWrData_1[1], oflux_mem_TraceMemWrData_1[0] }),
		.oflux_octl_pcs_txptr_smpl_lane0(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane0_1),
		.oflux_octl_pcs_txptr_smpl_lane1(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane1_1),
		.oflux_octl_pcs_txptr_smpl_lane2(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane2_1),
		.oflux_octl_pcs_txptr_smpl_lane3(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane3_1),
		.oflux_pcs_rxword_lane0({ x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[0] }),
		.oflux_pcs_rxword_lane1({ x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[0] }),
		.oflux_pcs_rxword_lane2({ x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2_0[0] }),
		.oflux_pcs_rxword_lane3({ x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[0] }),
		.oflux_srds_rdy0(oflux_srds_rdy0_1),
		.oflux_srds_rdy1(oflux_srds_rdy1_1),
		.oflux_srds_rdy2(oflux_srds_rdy2_1),
		.oflux_srds_rdy3(oflux_srds_rdy3_1),
		.oflux_srds_rx_clk_lane0(oflux_srds_rx_clk_lane0_1),
		.oflux_srds_rx_clk_lane1(oflux_srds_rx_clk_lane1_1),
		.oflux_srds_rx_clk_lane2(oflux_srds_rx_clk_lane2_1),
		.oflux_srds_rx_clk_lane3(oflux_srds_rx_clk_lane3_1),
		.oflux_srds_rx_divn_clk_lane0(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane0_1),
		.oflux_srds_rx_divn_clk_lane1(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane1_1),
		.oflux_srds_rx_divn_clk_lane2(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane2_1),
		.oflux_srds_rx_divn_clk_lane3(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane3_1),
		.oflux_srds_tx_clk_lane0(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane0_1),
		.oflux_srds_tx_clk_lane1(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane1_1),
		.oflux_srds_tx_clk_lane2(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane2_1),
		.oflux_srds_tx_clk_lane3(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane3_1),
		.uxwrap_bus_in_lane0({ x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[767], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[766], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[765], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[764], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[763], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[762], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[761], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[760], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[759], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[758], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[757], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[756], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[755], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[754], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[753], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[752], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[751], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[750], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[749], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[748], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[747], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[746], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[745], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[744], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[743], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[742], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[741], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[740], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[739], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[738], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[737], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[736], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[735], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[734], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[733], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[732], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[731], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[730], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[729], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[728], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[727], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[726], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[725], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[724], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[723], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[722], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[721], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[720], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[719], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[718], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[717], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[716], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[715], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[714], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[713], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[712], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[711], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[710], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[709], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[708], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[707], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[706], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[705], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[704], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[703], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[702], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[701], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[700], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[699], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[698], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[697], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[696], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[695], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[694], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[693], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[692], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[691], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[690], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[689], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[688], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[687], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[686], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[685], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[684], 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x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[655], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[654], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[653], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[652], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[651], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[650], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[649], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[648], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[647], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[646], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[645], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[644], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[643], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[642], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[641], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[640], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[639], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[638], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[637], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[636], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[635], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[634], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[633], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[632], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[631], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[630], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[629], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[628], 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x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[613], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[612], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[611], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[610], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[609], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[608], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[607], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[606], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[605], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[604], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[603], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[602], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[601], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[600], 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x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[0] })
	);

endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "2VFQJEphUyq8CwC8gsQTzYRiy4CKnFrR8CoPpc7J3IzqCDuq0mHM6K7V2GezThdey82bBMPNbBgDXoriW44Et6j33hxoHnsMU5dCyiGmutmx81l+P7dd/ZZHRzlYw5WTW/WUBsKFIF04NTI3bdb3z9ruzOKjaZWeulfiAYKi1f05itJlxUyPe9iDebXZUNjziA/9KjCM/P0e+uVjXL6IPI9Kd704g3ZM2iG17dIZikxqJcV5j8rCfITLAElgYNuIGmSXT/OrXfmTFRdLvYKDoYU+M58JQ2ZXK66bgA7kyPyin42qvugzjZncPNRMahk9yaOwtKye0EThqc8usWsIAObFW+6VuMhVVXm+WPzvS1jzd1Mr1rF8VZlgsmi+TdNOeY0VkqhqDgeZh+r22N630JgZGxVqKJsyxTOOzlsJZfSWN2uytNPzNNPTDST0pciPjyWdZzsyPg/Qa6kwJVmrrOknibUfRNCEWdnO3tXeP/mcHNJJAvvX5AhuonVCdDtFEgP0IBkA0Ezi56OmGmQ069c3swvIDOwG+lMQHb24ULq1qVzfK6bTJt3Zg/cCQzlYWRg7vUPiH0kZyAy+O24vNv6/FDIxxHTIc/zKuVlnJxnGjL3hrUe9u/Wfs+1e+2BXkcII7sVUWGQWoIwgGavFRS8P+tnmjTG+xpo25JbeT8GSYcXYoOeH0TsStxy77RL+eekkQ1bwnsy19zAdSIMy5M1l2+n0EaULwFuAV5nwMn4mkP0OEyD3goukW9p6qBtLbie7tnyL3EQ8DPqCt4ZNsBkPWnpK9E2lS3k8xebS/8YdPQ2J3Wlk4/qcGkYzIKri7P83EgR+YKxODE2f3WFvjAuiu07cTXOhsRH6fWdwvM5YcTOdRpBg9MKVLOM1APcsCvm50GE+Si7DvvpOBbxHtWOT9k8qFAJ4pL+bifAKdaMkXi/MKOss7Z19CuToNHV52bNmsUIyGAImyKcZSZH0Ba11zgf9OwblYM/ua61SbZ7yHQMjk3PtjcwuiCpa2WuL"
`endif