-- gts_axi_streaming_pcie_hal_top_one_lane_pcie_hal_2100_ltignja.vhd

-- Generated using ACDS version 25.1 129

library IEEE;
library one_lane_pcie_hal_2100;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity gts_axi_streaming_pcie_hal_top_one_lane_pcie_hal_2100_ltignja is
	generic (
		ch_tx_channel_mode            : string := "PMAD";
		ch_rx_channel_mode            : string := "PMAD";
		ch_mac_sf_en                  : string := "DISABLED";
		ch_pldif_sf_en                : string := "DISABLED";
		ch_pcs_sf_en                  : string := "DISABLED";
		ch_fec_sf_en                  : string := "DISABLED";
		ch_SF_PCS_TXMUX_EN            : string := "ENABLED";
		ch_SF_PCS_RXMUX_EN            : string := "ENABLED";
		ch_SF_FEC_TXMUX_EN            : string := "ENABLED";
		ch_SF_FEC_INGRESS_EN          : string := "ENABLED";
		ch_SF_FEC_EGRESS_EN           : string := "ENABLED";
		ch_SF_PLDCH_TX_USER1_MUX_EN   : string := "ENABLED";
		ch_SF_PLDCH_TX_USER2_MUX_EN   : string := "ENABLED";
		ch_SF_PLDCH_RX_USER1_MUX_EN   : string := "ENABLED";
		ch_SF_PLDCH_RX_USER2_MUX_EN   : string := "ENABLED";
		ch_SF_DESKEW_EN               : string := "ENABLED";
		ch_SF_DESKEW_RXMUX_EN         : string := "ENABLED";
		ch_SF_PTP_INGRESS_EN          : string := "ENABLED";
		ch_SF_PTP_EGRESS_EN           : string := "ENABLED";
		ch_SF_PTP_S_EN                : string := "ENABLED";
		ch_SF_PTP_EN                  : string := "ENABLED";
		ch_SF_UX_EN                   : string := "ENABLED";
		ch_SF_FLUX_GLOBAL_MEM_EN      : string := "ENABLED";
		ch_SF_FLUX_S_EN               : string := "ENABLED";
		ch_SF_FLUX_TXUSER_CLK1_MUX_EN : string := "ENABLED";
		ch_SF_FLUX_TXUSER_CLK2_MUX_EN : string := "ENABLED";
		ch_SF_FLUX_RXUSER_CLK1_MUX_EN : string := "ENABLED";
		ch_SF_FLUX_RXUSER_CLK2_MUX_EN : string := "ENABLED";
		ch_SF_FLUX_I_EN               : string := "ENABLED";
		ch_SF_UX_TOOLBOX_EN           : string := "ENABLED";
		ch_SF_FLUX_CORE_EN            : string := "ENABLED";
		ch_SF_XCVRIF_1CH_EN           : string := "ENABLED";
		ch_SF_XCVRIF_TXMUX_EN         : string := "ENABLED";
		ch_SF_XCRIF_TX_RST_MUX_EN     : string := "ENABLED";
		ch_SF_XCRIF_TX_WREN_MUX_EN    : string := "ENABLED";
		ch_SF_XCRIF_TX_RDEN_MUX_EN    : string := "ENABLED";
		ch_SF_XCRIF_TXWORD_CLK_MUX_EN : string := "ENABLED";
		ch_SF_XCRIF_RXWORD_CLK_MUX_EN : string := "ENABLED"
	);
	port (
		i_hio_txdata                                : in  std_logic_vector(79 downto 0)  := (others => '0'); --                           i_hio_txdata.data,         Stats Snapshot
		i_hio_txdata_extra                          : in  std_logic_vector(9 downto 0)   := (others => '0'); --                     i_hio_txdata_extra.data,         RX PFC
		i_hio_txdata_fifo_wr_en                     : in  std_logic                      := '0';             --                i_hio_txdata_fifo_wr_en.data,         CSR access address
		i_hio_rxdata_fifo_rd_en                     : in  std_logic                      := '0';             --                i_hio_rxdata_fifo_rd_en.data,         RX error bits asserted on the EOP cycle
		i_hio_ptp_rst_n                             : in  std_logic                      := '0';             --                        i_hio_ptp_rst_n.reset,        Stats Snapshot
		i_hio_ehip_rx_rst_n                         : in  std_logic                      := '0';             --                    i_hio_ehip_rx_rst_n.reset,        RX PFC
		i_hio_ehip_tx_rst_n                         : in  std_logic                      := '0';             --                    i_hio_ehip_tx_rst_n.reset,        CSR access address
		i_hio_ehip_signal_ok                        : in  std_logic                      := '0';             --                   i_hio_ehip_signal_ok.reset,        RX error bits asserted on the EOP cycle
		i_hio_sfreeze_2_r03f_rx_mac_srfz_n          : in  std_logic                      := '0';             --     i_hio_sfreeze_2_r03f_rx_mac_srfz_n.reset,        Stats Snapshot
		i_hio_sfreeze_3_c2f_tx_deskew_srfz_n        : in  std_logic                      := '0';             --   i_hio_sfreeze_3_c2f_tx_deskew_srfz_n.reset,        RX PFC
		i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n          : in  std_logic                      := '0';             --     i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n.reset,        CSR access address
		i_hio_rstfec_fec_rx_rst_n                   : in  std_logic                      := '0';             --              i_hio_rstfec_fec_rx_rst_n.reset,        RX error bits asserted on the EOP cycle
		i_hio_rstfec_fec_tx_rst_n                   : in  std_logic                      := '0';             --              i_hio_rstfec_fec_tx_rst_n.reset,        RX error bits asserted on the EOP cycle
		i_hio_rstfec_fec_csr_ret                    : in  std_logic                      := '0';             --               i_hio_rstfec_fec_csr_ret.reset,        Stats Snapshot
		i_hio_rstfec_rx_fec_sfrz_n                  : in  std_logic                      := '0';             --             i_hio_rstfec_rx_fec_sfrz_n.reset,        RX PFC
		i_hio_rstfec_tx_fec_sfrz_n                  : in  std_logic                      := '0';             --             i_hio_rstfec_tx_fec_sfrz_n.reset,        CSR access address
		i_hio_rstxcvrif_xcvrif_rx_rst_n             : in  std_logic                      := '0';             --        i_hio_rstxcvrif_xcvrif_rx_rst_n.reset
		i_hio_rstxcvrif_xcvrif_tx_rst_n             : in  std_logic                      := '0';             --        i_hio_rstxcvrif_xcvrif_tx_rst_n.reset,        Stats Snapshot
		i_hio_rstxcvrif_xcvrif_signal_ok            : in  std_logic                      := '0';             --       i_hio_rstxcvrif_xcvrif_signal_ok.reset,        RX PFC
		i_hio_rstxcvrif_rx_xcvrif_sfrz_n            : in  std_logic                      := '0';             --       i_hio_rstxcvrif_rx_xcvrif_sfrz_n.reset,        CSR access address
		i_hio_rstxcvrif_tx_xcvrif_sfrz_n            : in  std_logic                      := '0';             --       i_hio_rstxcvrif_tx_xcvrif_sfrz_n.reset
		i_hio_rst_pld_clrhip                        : in  std_logic                      := '0';             --                   i_hio_rst_pld_clrhip.reset,        Stats Snapshot
		i_hio_rst_pld_clrpcs                        : in  std_logic                      := '0';             --                   i_hio_rst_pld_clrpcs.reset
		i_hio_rst_pld_perstn                        : in  std_logic                      := '0';             --                   i_hio_rst_pld_perstn.reset,        CSR access address
		i_hio_rst_pld_ready                         : in  std_logic                      := '0';             --                    i_hio_rst_pld_ready.reset
		i_hio_rst_pld_adapter_rx_pld_rst_n          : in  std_logic                      := '0';             --     i_hio_rst_pld_adapter_rx_pld_rst_n.reset
		i_hio_rst_pld_adapter_tx_pld_rst_n          : in  std_logic                      := '0';             --     i_hio_rst_pld_adapter_tx_pld_rst_n.reset
		i_hio_rst_ux_rx_pma_rst_n                   : in  std_logic                      := '0';             --              i_hio_rst_ux_rx_pma_rst_n.reset
		i_hio_rst_ux_rx_sfrz                        : in  std_logic                      := '0';             --                   i_hio_rst_ux_rx_sfrz.reset
		i_hio_rst_ux_tx_pma_rst_n                   : in  std_logic                      := '0';             --              i_hio_rst_ux_tx_pma_rst_n.reset
		i_hio_pld_reset_clk_row                     : in  std_logic                      := '0';             --                i_hio_pld_reset_clk_row.reset
		i_hio_uxquad_async                          : in  std_logic_vector(79 downto 0)  := (others => '0'); --                     i_hio_uxquad_async.data
		i_hio_uxquad_async_pcie_mux                 : in  std_logic_vector(79 downto 0)  := (others => '0'); --            i_hio_uxquad_async_pcie_mux.data
		i_hio_lavmm_addr                            : in  std_logic_vector(20 downto 0)  := (others => '0'); --                               reconfig.address
		i_hio_lavmm_be                              : in  std_logic_vector(3 downto 0)   := (others => '0'); --                                       .byteenable
		i_hio_lavmm_read                            : in  std_logic                      := '0';             --                                       .read
		i_hio_lavmm_wdata                           : in  std_logic_vector(31 downto 0)  := (others => '0'); --                                       .writedata
		i_hio_lavmm_write                           : in  std_logic                      := '0';             --                                       .write,        RX error bits asserted on the EOP cycle
		o_hio_lavmm_rdata                           : out std_logic_vector(31 downto 0);                     --                                       .readdata
		o_hio_lavmm_rdata_valid                     : out std_logic;                                         --                                       .readdatavalid
		o_hio_lavmm_waitreq                         : out std_logic;                                         --                                       .waitrequest
		i_hio_lavmm_clk                             : in  std_logic                      := '0';             --                           reconfig_clk.clk
		i_hio_lavmm_rstn                            : in  std_logic                      := '0';             --                           reconfig_rst.reset
		o_ss_lavmm_pcie_addr                        : out std_logic_vector(16 downto 0);                     --                          reconfig_phip.address
		o_ss_lavmm_pcie_be                          : out std_logic_vector(3 downto 0);                      --                                       .byteenable
		o_ss_lavmm_pcie_read                        : out std_logic;                                         --                                       .read
		o_ss_lavmm_pcie_wdata                       : out std_logic_vector(31 downto 0);                     --                                       .writedata
		o_ss_lavmm_pcie_write                       : out std_logic;                                         --                                       .write,        RX error bits asserted on the EOP cycle
		i_ss_lavmm_pcie_rdata                       : in  std_logic_vector(31 downto 0)  := (others => '0'); --                                       .readdata
		i_ss_lavmm_pcie_rdata_valid                 : in  std_logic                      := '0';             --                                       .readdatavalid
		i_ss_lavmm_pcie_waitreq                     : in  std_logic                      := '0';             --                                       .waitrequest
		o_ss_lavmm_pcie_clk                         : out std_logic;                                         --                      reconfig_clk_phip.clk
		o_ss_lavmm_pcie_rstn                        : out std_logic;                                         --                      reconfig_rst_phip.reset
		sm_pld_tx_demux_0_o_pcie                    : out std_logic_vector(79 downto 0);                     --               sm_pld_tx_demux_0_o_pcie.data
		sm_pld_rx_mux_0_i_pcie                      : in  std_logic_vector(79 downto 0)  := (others => '0'); --                 sm_pld_rx_mux_0_i_pcie.data
		o_pld_pcie_clk_4                            : in  std_logic                      := '0';             --                       o_pld_pcie_clk_4.clk
		o_pcie_rxword_clk                           : out std_logic;                                         --                      o_pcie_rxword_clk.clk
		o_pcie_txword_clk                           : out std_logic;                                         --                      o_pcie_txword_clk.clk
		ss_rst_ux_rxcdrlock2data                    : out std_logic;                                         --               ss_rst_ux_rxcdrlock2data.data
		o_rxeq_best_eye_vala                        : out std_logic_vector(13 downto 0);                     --                   o_rxeq_best_eye_vala.data
		o_rxeq_donea                                : out std_logic;                                         --                           o_rxeq_donea.data
		o_rxmargin_nacka                            : out std_logic;                                         --                       o_rxmargin_nacka.data
		o_rxmargin_statusa                          : out std_logic;                                         --                     o_rxmargin_statusa.data
		o_rxsignaldetect_lfpsa                      : out std_logic;                                         --                 o_rxsignaldetect_lfpsa.data
		o_rxsignaldetecta                           : out std_logic;                                         --                      o_rxsignaldetecta.data
		o_rxmargin_status_gray                      : out std_logic_vector(1 downto 0);                      --                 o_rxmargin_status_gray.data
		rxstatusa                                   : out std_logic;                                         --                              rxstatusa.data
		o_pcie_pcs                                  : out std_logic_vector(39 downto 0);                     --                             o_pcie_pcs.data
		i_pcie_pcs                                  : in  std_logic_vector(39 downto 0)  := (others => '0'); --                             i_pcie_pcs.data
		o_synthlcfast_postdiv                       : out std_logic;                                         --                  o_synthlcfast_postdiv.data
		o_synthlcmed_postdiv                        : out std_logic;                                         --                   o_synthlcmed_postdiv.data
		o_synthlcslow_postdiv                       : out std_logic;                                         --                  o_synthlcslow_postdiv.data
		o_txdetectrx_acka                           : out std_logic;                                         --                      o_txdetectrx_acka.data
		o_txdetectrx_statct                         : out std_logic;                                         --                    o_txdetectrx_statct.data
		txstatusa                                   : out std_logic;                                         --                              txstatusa.data
		i_pcs_pipe_rstn                             : in  std_logic                      := '0';             --                        i_pcs_pipe_rstn.data
		i_ux_ock_pma_clk                            : in  std_logic                      := '0';             --                       i_ux_ock_pma_clk.data
		i_lfps_ennt                                 : in  std_logic                      := '0';             --                            i_lfps_ennt.data
		i_pcie_l1ctrla                              : in  std_logic_vector(1 downto 0)   := (others => '0'); --                         i_pcie_l1ctrla.data
		i_pma_cmn_ctrl                              : in  std_logic                      := '0';             --                         i_pma_cmn_ctrl.data
		i_pma_ctrl                                  : in  std_logic                      := '0';             --                             i_pma_ctrl.data
		i_pcie_pcs_rx_rst                           : in  std_logic                      := '0';             --                      i_pcie_pcs_rx_rst.data
		i_pcie_pcs_tx_rst                           : in  std_logic                      := '0';             --                      i_pcie_pcs_tx_rst.data
		i_rxeiosdetectstata                         : in  std_logic                      := '0';             --                    i_rxeiosdetectstata.data
		i_rxeq_precal_code_selnt                    : in  std_logic_vector(2 downto 0)   := (others => '0'); --               i_rxeq_precal_code_selnt.data
		i_rxeq_starta                               : in  std_logic                      := '0';             --                          i_rxeq_starta.data
		i_rxeq_static_ena                           : in  std_logic                      := '0';             --                      i_rxeq_static_ena.data
		i_rxmargin_direction_nt                     : in  std_logic                      := '0';             --                i_rxmargin_direction_nt.data
		i_rxmargin_mode_nt                          : in  std_logic                      := '0';             --                     i_rxmargin_mode_nt.data
		i_rxmargin_offset_change_a                  : in  std_logic                      := '0';             --             i_rxmargin_offset_change_a.data
		i_rxmargin_offset_nt                        : in  std_logic_vector(6 downto 0)   := (others => '0'); --                   i_rxmargin_offset_nt.data
		i_rxmargin_start_a                          : in  std_logic                      := '0';             --                     i_rxmargin_start_a.data
		i_rxpstate                                  : in  std_logic_vector(2 downto 0)   := (others => '0'); --                             i_rxpstate.data
		i_rxrate                                    : in  std_logic_vector(3 downto 0)   := (others => '0'); --                               i_rxrate.data
		i_rxterm_hiz_ena                            : in  std_logic                      := '0';             --                       i_rxterm_hiz_ena.data
		i_rxwidth                                   : in  std_logic_vector(2 downto 0)   := (others => '0'); --                              i_rxwidth.data
		i_tstbus_lane                               : in  std_logic                      := '0';             --                          i_tstbus_lane.data
		i_txbeacona                                 : in  std_logic                      := '0';             --                            i_txbeacona.data
		i_txclkdivrate                              : in  std_logic_vector(2 downto 0)   := (others => '0'); --                         i_txclkdivrate.data
		i_txdetectrx_reqa                           : in  std_logic                      := '0';             --                      i_txdetectrx_reqa.data
		i_txdrv_levn                                : in  std_logic_vector(5 downto 0)   := (others => '0'); --                           i_txdrv_levn.data
		i_txdrv_levnm1                              : in  std_logic_vector(4 downto 0)   := (others => '0'); --                         i_txdrv_levnm1.data
		i_txdrv_levnm2                              : in  std_logic_vector(2 downto 0)   := (others => '0'); --                         i_txdrv_levnm2.data
		i_txdrv_levnp1                              : in  std_logic_vector(4 downto 0)   := (others => '0'); --                         i_txdrv_levnp1.data
		i_txdrv_slew                                : in  std_logic_vector(3 downto 0)   := (others => '0'); --                           i_txdrv_slew.data
		i_txelecidle                                : in  std_logic_vector(3 downto 0)   := (others => '0'); --                           i_txelecidle.data
		i_txpstate                                  : in  std_logic_vector(2 downto 0)   := (others => '0'); --                             i_txpstate.data
		i_txrate                                    : in  std_logic_vector(3 downto 0)   := (others => '0'); --                               i_txrate.data
		i_txwidth                                   : in  std_logic_vector(2 downto 0)   := (others => '0'); --                              i_txwidth.data
		i_hio_pld_rx_clk_in_row_clk                 : in  std_logic                      := '0';             --            i_hio_pld_rx_clk_in_row_clk.clk,          RX error bits asserted on the EOP cycle
		i_hio_pld_tx_clk_in_row_clk                 : in  std_logic                      := '0';             --            i_hio_pld_tx_clk_in_row_clk.clk,          RX error bits asserted on the EOP cycle
		i_hio_det_lat_rx_dl_clk                     : in  std_logic                      := '0';             --                i_hio_det_lat_rx_dl_clk.clk,          RX error bits asserted on the EOP cycle
		i_hio_det_lat_rx_mux_select                 : in  std_logic                      := '0';             --            i_hio_det_lat_rx_mux_select.clk,          RX error bits asserted on the EOP cycle
		i_hio_det_lat_rx_sclk_flop                  : in  std_logic                      := '0';             --             i_hio_det_lat_rx_sclk_flop.clk,          RX error bits asserted on the EOP cycle
		i_hio_det_lat_rx_sclk_gen_clk               : in  std_logic                      := '0';             --          i_hio_det_lat_rx_sclk_gen_clk.clk,          RX error bits asserted on the EOP cycle
		i_hio_det_lat_rx_trig_flop                  : in  std_logic                      := '0';             --             i_hio_det_lat_rx_trig_flop.clk,          RX error bits asserted on the EOP cycle
		i_hio_det_lat_sampling_clk                  : in  std_logic                      := '0';             --             i_hio_det_lat_sampling_clk.clk
		i_hio_det_lat_tx_dl_clk                     : in  std_logic                      := '0';             --                i_hio_det_lat_tx_dl_clk.clk
		i_hio_det_lat_tx_mux_select                 : in  std_logic                      := '0';             --            i_hio_det_lat_tx_mux_select.clk
		i_hio_det_lat_tx_sclk_flop                  : in  std_logic                      := '0';             --             i_hio_det_lat_tx_sclk_flop.clk
		i_hio_det_lat_tx_sclk_gen_clk               : in  std_logic                      := '0';             --          i_hio_det_lat_tx_sclk_gen_clk.clk
		i_hio_det_lat_tx_trig_flop                  : in  std_logic                      := '0';             --             i_hio_det_lat_tx_trig_flop.clk
		rx_serial_n                                 : in  std_logic                      := '0';             --                            rx_serial_n.data
		rx_serial_p                                 : in  std_logic                      := '0';             --                            rx_serial_p.data
		o_hio_txdata_fifo_wr_empty                  : out std_logic;                                         --             o_hio_txdata_fifo_wr_empty.data
		o_hio_txdata_fifo_wr_pempty                 : out std_logic;                                         --            o_hio_txdata_fifo_wr_pempty.data
		o_hio_txdata_fifo_wr_full                   : out std_logic;                                         --              o_hio_txdata_fifo_wr_full.data
		o_hio_txdata_fifo_wr_pfull                  : out std_logic;                                         --             o_hio_txdata_fifo_wr_pfull.data
		o_hio_rxdata                                : out std_logic_vector(79 downto 0);                     --                           o_hio_rxdata.data
		o_hio_rxdata_extra                          : out std_logic_vector(9 downto 0);                      --                     o_hio_rxdata_extra.data
		o_hio_rxdata_fifo_rd_empty                  : out std_logic;                                         --             o_hio_rxdata_fifo_rd_empty.data
		o_hio_rxdata_fifo_rd_pempty                 : out std_logic;                                         --            o_hio_rxdata_fifo_rd_pempty.data
		o_hio_rxdata_fifo_rd_full                   : out std_logic;                                         --              o_hio_rxdata_fifo_rd_full.data
		o_hio_rxdata_fifo_rd_pfull                  : out std_logic;                                         --             o_hio_rxdata_fifo_rd_pfull.data
		o_hio_rstepcs_rx_pcs_fully_aligned          : out std_logic;                                         --     o_hio_rstepcs_rx_pcs_fully_aligned.reset
		o_hio_rstfec_fec_rx_rdy_n                   : out std_logic;                                         --              o_hio_rstfec_fec_rx_rdy_n.reset
		o_hio_rst_flux0_cpi_cmn_busy                : out std_logic;                                         --           o_hio_rst_flux0_cpi_cmn_busy.reset
		o_hio_rst_oflux_rx_srds_rdy                 : out std_logic;                                         --            o_hio_rst_oflux_rx_srds_rdy.reset
		o_hio_rst_ux_all_synthlockstatus            : out std_logic;                                         --       o_hio_rst_ux_all_synthlockstatus.reset
		o_hio_rst_ux_octl_pcs_rxstatus              : out std_logic;                                         --         o_hio_rst_ux_octl_pcs_rxstatus.reset
		o_hio_rst_ux_octl_pcs_txstatus              : out std_logic;                                         --         o_hio_rst_ux_octl_pcs_txstatus.reset
		o_hio_rst_ux_rxcdrlock2data                 : out std_logic;                                         --            o_hio_rst_ux_rxcdrlock2data.reset
		o_hio_rst_ux_rxcdrlockstatus                : out std_logic;                                         --           o_hio_rst_ux_rxcdrlockstatus.reset
		o_hio_uxquad_async                          : out std_logic_vector(49 downto 0);                     --                     o_hio_uxquad_async.data
		o_hio_user_rx_clk1_clk                      : out std_logic;                                         --                 o_hio_user_rx_clk1_clk.clk
		o_hio_user_rx_clk2_clk                      : out std_logic;                                         --                 o_hio_user_rx_clk2_clk.clk
		o_hio_user_tx_clk1_clk                      : out std_logic;                                         --                 o_hio_user_tx_clk1_clk.clk
		o_hio_user_tx_clk2_clk                      : out std_logic;                                         --                 o_hio_user_tx_clk2_clk.clk
		o_hio_ux_chnl_refclk_mux                    : out std_logic;                                         --               o_hio_ux_chnl_refclk_mux.clk
		o_hio_det_lat_rx_async_dl_sync              : out std_logic;                                         --         o_hio_det_lat_rx_async_dl_sync.clk
		o_hio_det_lat_rx_async_pulse                : out std_logic;                                         --           o_hio_det_lat_rx_async_pulse.clk
		o_hio_det_lat_rx_async_sample_sync          : out std_logic;                                         --     o_hio_det_lat_rx_async_sample_sync.clk
		o_hio_det_lat_rx_sclk_sample_sync           : out std_logic;                                         --      o_hio_det_lat_rx_sclk_sample_sync.clk
		o_hio_det_lat_rx_trig_sample_sync           : out std_logic;                                         --      o_hio_det_lat_rx_trig_sample_sync.clk
		o_hio_det_lat_tx_async_dl_sync              : out std_logic;                                         --         o_hio_det_lat_tx_async_dl_sync.clk
		o_hio_det_lat_tx_async_pulse                : out std_logic;                                         --           o_hio_det_lat_tx_async_pulse.clk
		o_hio_det_lat_tx_async_sample_sync          : out std_logic;                                         --     o_hio_det_lat_tx_async_sample_sync.clk
		o_hio_det_lat_tx_sclk_sample_sync           : out std_logic;                                         --      o_hio_det_lat_tx_sclk_sample_sync.clk
		o_hio_det_lat_tx_trig_sample_sync           : out std_logic;                                         --      o_hio_det_lat_tx_trig_sample_sync.clk
		o_hio_xcvrif_rx_latency_pulse               : out std_logic;                                         --          o_hio_xcvrif_rx_latency_pulse.clk
		o_hio_xcvrif_tx_latency_pulse               : out std_logic;                                         --          o_hio_xcvrif_tx_latency_pulse.clk
		tx_serial_p                                 : out std_logic;                                         --                            tx_serial_p.data
		tx_serial_n                                 : out std_logic;                                         --                            tx_serial_n.data
		i_hio_txdata_async                          : in  std_logic_vector(99 downto 0)  := (others => '0'); --                     i_hio_txdata_async.data
		i_hio_txdata_direct                         : in  std_logic_vector(9 downto 0)   := (others => '0'); --                    i_hio_txdata_direct.data
		o_hio_rxdata_async                          : out std_logic_vector(99 downto 0);                     --                     o_hio_rxdata_async.data
		o_hio_rxdata_direct                         : out std_logic_vector(9 downto 0);                      --                    o_hio_rxdata_direct.data
		i_uxwrap_bus_in_phy_shared                  : in  std_logic_vector(767 downto 0) := (others => '0'); --                          uxwrap_bus_in.data
		o_uxwrap_bus_out_phy_shared                 : out std_logic_vector(703 downto 0);                    --                         uxwrap_bus_out.data
		o_lavmm_addr_phy_shared                     : out std_logic_vector(19 downto 0);                     --                    reconfig_phy_shared.address
		o_lavmm_be_phy_shared                       : out std_logic_vector(3 downto 0);                      --                                       .byteenable
		o_lavmm_read_phy_shared                     : out std_logic;                                         --                                       .read
		o_lavmm_wdata_phy_shared                    : out std_logic_vector(31 downto 0);                     --                                       .writedata
		o_lavmm_write_phy_shared                    : out std_logic;                                         --                                       .write
		i_lavmm_rdata_phy_shared                    : in  std_logic_vector(31 downto 0)  := (others => '0'); --                                       .readdata
		i_lavmm_rdata_valid_phy_shared              : in  std_logic                      := '0';             --                                       .readdatavalid
		i_lavmm_waitreq_phy_shared                  : in  std_logic                      := '0';             --                                       .waitrequest
		o_lavmm_clk_phy_shared                      : out std_logic;                                         --                reconfig_clk_phy_shared.clk
		o_lavmm_rstn_phy_shared                     : out std_logic;                                         --                reconfig_rst_phy_shared.reset
		o_sclk_return_sel_rx_phy_shared             : out std_logic;                                         --                   o_sclk_return_sel_rx.data
		o_sclk_return_sel_tx_phy_shared             : out std_logic;                                         --                   o_sclk_return_sel_tx.data
		o_ick_sclk_rx_phy_shared                    : out std_logic;                                         --                          o_ick_sclk_rx.clk
		i_sync_common_control_phy_shared            : in  std_logic_vector(4 downto 0)   := (others => '0'); --                  i_sync_common_control.data
		o_ft_rx_sclk_sync_ch_phy_shared             : out std_logic;                                         --                   o_ft_rx_sclk_sync_ch.data
		o_ft_tx_sclk_sync_ch_phy_shared             : out std_logic;                                         --                   o_ft_tx_sclk_sync_ch.data
		o_rst_ux_rx_pma_rst_n_phy_shared            : out std_logic;                                         --                  o_rst_ux_rx_pma_rst_n.reset
		o_rst_ux_tx_pma_rst_n_phy_shared            : out std_logic;                                         --                  o_rst_ux_tx_pma_rst_n.reset
		o_ick_pcs_txword_phy_shared                 : out std_logic;                                         --                       o_ick_pcs_txword.data
		o_tx_dl_ch_bit_phy_shared                   : out std_logic;                                         --                         o_tx_dl_ch_bit.data
		i_dat_pcs_measlatbit_phy_shared             : in  std_logic                      := '0';             --                   i_dat_pcs_measlatbit.data
		i_ft_rx_async_pulse_ch_phy_shared           : in  std_logic                      := '0';             --                 i_ft_rx_async_pulse_ch.data
		i_ft_tx_async_pulse_ch_phy_shared           : in  std_logic                      := '0';             --                 i_ft_tx_async_pulse_ch.data
		i_rx_dl_ch_bit_phy_shared                   : in  std_logic                      := '0';             --                         i_rx_dl_ch_bit.data
		i_ux_rxuser1_sel_phy_shared                 : in  std_logic_vector(1 downto 0)   := (others => '0'); --                       i_ux_rxuser1_sel.data
		i_ux_rxuser2_sel_phy_shared                 : in  std_logic_vector(1 downto 0)   := (others => '0'); --                       i_ux_rxuser2_sel.data
		i_ux_txuser1_sel_phy_shared                 : in  std_logic_vector(1 downto 0)   := (others => '0'); --                       i_ux_txuser1_sel.data
		i_ux_txuser2_sel_phy_shared                 : in  std_logic_vector(1 downto 0)   := (others => '0'); --                       i_ux_txuser2_sel.data
		o_octl_pcs_txstatus_a_phy_shared            : out std_logic;                                         --                  o_octl_pcs_txstatus_a.data
		i_ictl_pcs_txenable_a_phy_shared            : in  std_logic                      := '0';             --                  i_ictl_pcs_txenable_a.data
		i_sync_cfg_data_phy_shared                  : in  std_logic_vector(124 downto 0) := (others => '0'); --                        i_sync_cfg_data.data
		i_sync_interface_control_phy_shared         : in  std_logic_vector(249 downto 0) := (others => '0'); --               i_sync_interface_control.data
		o_tx_data_phy_shared                        : out std_logic_vector(79 downto 0);                     --                              o_tx_data.data
		i_rx_data_phy_shared                        : in  std_logic_vector(79 downto 0)  := (others => '0'); --                              i_rx_data.data
		o_sm_flux_ingress_phy_shared                : out std_logic_vector(319 downto 0);                    --                      o_sm_flux_ingress.data
		i_sm_flux_egress_phy_shared                 : in  std_logic_vector(256 downto 0) := (others => '0'); --                       i_sm_flux_egress.data
		i_flux_cpi_int_phy_shared                   : in  std_logic                      := '0';             --                         i_flux_cpi_int.data
		i_flux_int_phy_shared                       : in  std_logic                      := '0';             --                             i_flux_int.data
		i_oflux_octl_pcs_txptr_smpl_lane_phy_shared : in  std_logic                      := '0';             --       i_oflux_octl_pcs_txptr_smpl_lane.data
		o_ick_sclk_tx_phy_shared                    : out std_logic;                                         --                          o_ick_sclk_tx.clk
		i_flux_srds_rdy_phy_shared                  : in  std_logic                      := '0';             --                        i_flux_srds_rdy.data
		i_pcs_rxword_phy_shared                     : in  std_logic                      := '0';             --                           i_pcs_rxword.data
		i_pcs_rxpostdiv_phy_shared                  : in  std_logic                      := '0';             --                        i_pcs_rxpostdiv.data
		i_ock_pcs_txword_phy_shared                 : in  std_logic                      := '0';             --                       i_ock_pcs_txword.data
		o_dat_pcs_measlatrndtripbit_phy_shared      : out std_logic;                                         -- o_dat_pcs_measlatrndtripbit_phy_shared.data
		i_ch_eth_fec_rx_async_fec_wrap              : in  std_logic_vector(11 downto 0)  := (others => '0'); --                            asyncdata_4.data
		i_ch_eth_fec_rx_direct_fec_wrap             : in  std_logic                      := '0';             --                            asyncdata_5.data
		i_fec_rx_rdy_n_fec_wrap                     : in  std_logic                      := '0';             --                i_fec_rx_rdy_n_fec_wrap.data
		i_fec_tx_data_mux_sel_fec_wrap              : in  std_logic                      := '0';             --         i_fec_tx_data_mux_sel_fec_wrap.muxsel
		i_fec_rx_data_fec_wrap                      : in  std_logic_vector(42 downto 0)  := (others => '0'); --                 i_fec_rx_data_fec_wrap.data
		i_xcvr_tx_data                              : in  std_logic_vector(42 downto 0)  := (others => '0'); --                         i_xcvr_tx_data.data
		ss_rst_flux0_cpi_cmn_busy                   : out std_logic;                                         --              ss_rst_flux0_cpi_cmn_busy.data
		o_pma_rx_sf                                 : out std_logic;                                         --                            o_pma_rx_sf.data
		i_refclk_tx_p                               : in  std_logic                      := '0';             --                          i_refclk_tx_p.clk
		i_syspll_c0_clk                             : in  std_logic                      := '0';             --                        i_syspll_c0_clk.clk
		i_syspll_c1_clk                             : in  std_logic                      := '0';             --                        i_syspll_c1_clk.clk
		i_syspll_c2_clk                             : in  std_logic                      := '0';             --                        i_syspll_c2_clk.clk
		i_flux_clk                                  : in  std_logic                      := '0';             --                             i_flux_clk.clk
		i_refclk_rx_p                               : in  std_logic                      := '0';             --                          i_refclk_rx_p.clk
		i_ux_chnl_refclk_mux_phy_shared             : in  std_logic                      := '0';             --        i_ux_chnl_refclk_mux_phy_shared.clk
		o_xcvrif_tx_fifo_rd_en_mux_x1               : out std_logic;                                         --          o_xcvrif_tx_fifo_rd_en_mux_x1.clk
		i_xcvrif_tx_fifo_rd_en_mux_x2               : in  std_logic                      := '0';             --          i_xcvrif_tx_fifo_rd_en_mux_x2.clk
		i_xcvrif_tx_fifo_rd_en_mux_x4               : in  std_logic                      := '0';             --          i_xcvrif_tx_fifo_rd_en_mux_x4.clk
		i_xcvrif_tx_fifo_rd_en_mux_x6_bot           : in  std_logic                      := '0';             --      i_xcvrif_tx_fifo_rd_en_mux_x6_bot.clk
		i_xcvrif_tx_fifo_rd_en_mux_x6_top           : in  std_logic                      := '0';             --      i_xcvrif_tx_fifo_rd_en_mux_x6_top.clk
		i_xcvrif_tx_fifo_rd_en_mux_x8_bot           : in  std_logic                      := '0';             --      i_xcvrif_tx_fifo_rd_en_mux_x8_bot.clk
		i_xcvrif_tx_fifo_rd_en_mux_x8_top           : in  std_logic                      := '0';             --      i_xcvrif_tx_fifo_rd_en_mux_x8_top.clk
		o_xcvrif_tx_rst_mux_x1                      : out std_logic;                                         --                 o_xcvrif_tx_rst_mux_x1.clk
		i_xcvrif_tx_rst_mux_x2                      : in  std_logic                      := '0';             --                 i_xcvrif_tx_rst_mux_x2.clk
		i_xcvrif_tx_rst_mux_x4                      : in  std_logic                      := '0';             --                 i_xcvrif_tx_rst_mux_x4.clk
		i_xcvrif_tx_rst_mux_x6_bot                  : in  std_logic                      := '0';             --             i_xcvrif_tx_rst_mux_x6_bot.clk
		i_xcvrif_tx_rst_mux_x6_top                  : in  std_logic                      := '0';             --             i_xcvrif_tx_rst_mux_x6_top.clk
		i_xcvrif_tx_rst_mux_x8_bot                  : in  std_logic                      := '0';             --             i_xcvrif_tx_rst_mux_x8_bot.clk
		i_xcvrif_tx_rst_mux_x8_top                  : in  std_logic                      := '0';             --             i_xcvrif_tx_rst_mux_x8_top.clk
		o_xcvrif_tx_word_clk_mux_x1                 : out std_logic;                                         --            o_xcvrif_tx_word_clk_mux_x1.clk
		i_xcvrif_tx_word_clk_mux_x2                 : in  std_logic                      := '0';             --            i_xcvrif_tx_word_clk_mux_x2.clk
		i_xcvrif_tx_word_clk_mux_x4                 : in  std_logic                      := '0';             --            i_xcvrif_tx_word_clk_mux_x4.clk
		i_xcvrif_tx_word_clk_mux_x6_bot             : in  std_logic                      := '0';             --        i_xcvrif_tx_word_clk_mux_x6_bot.clk
		i_xcvrif_tx_word_clk_mux_x6_top             : in  std_logic                      := '0';             --        i_xcvrif_tx_word_clk_mux_x6_top.clk
		i_xcvrif_tx_word_clk_mux_x8_bot             : in  std_logic                      := '0';             --        i_xcvrif_tx_word_clk_mux_x8_bot.clk
		i_xcvrif_tx_word_clk_mux_x8_top             : in  std_logic                      := '0';             --        i_xcvrif_tx_word_clk_mux_x8_top.clk
		ioack_cdrdiv_left_ux_bidir_in               : in  std_logic                      := '0';             --          ioack_cdrdiv_left_ux_bidir_in.clk
		ioack_synthdiv1_left_ux_bidir_in            : in  std_logic                      := '0';             --       ioack_synthdiv1_left_ux_bidir_in.clk
		ioack_synthdiv2_left_ux_bidir_in            : in  std_logic                      := '0';             --       ioack_synthdiv2_left_ux_bidir_in.clk
		ioack_cdrdiv_left_ux_bidir_out              : out std_logic;                                         --         ioack_cdrdiv_left_ux_bidir_out.clk
		ioack_synthdiv1_left_ux_bidir_out           : out std_logic;                                         --      ioack_synthdiv1_left_ux_bidir_out.clk
		ioack_synthdiv2_left_ux_bidir_out           : out std_logic;                                         --      ioack_synthdiv2_left_ux_bidir_out.clk
		o_xcvrif_tx_rst_wr_sync_mux_x1              : out std_logic;                                         --         o_xcvrif_tx_rst_wr_sync_mux_x1.clk
		i_xcvrif_tx_rst_wr_sync_mux_x2              : in  std_logic                      := '0';             --         i_xcvrif_tx_rst_wr_sync_mux_x2.clk
		i_xcvrif_tx_rst_wr_sync_mux_x4              : in  std_logic                      := '0';             --         i_xcvrif_tx_rst_wr_sync_mux_x4.clk
		i_xcvrif_tx_rst_wr_sync_mux_x6_bot          : in  std_logic                      := '0';             --     i_xcvrif_tx_rst_wr_sync_mux_x6_bot.clk
		i_xcvrif_tx_rst_wr_sync_mux_x6_top          : in  std_logic                      := '0';             --     i_xcvrif_tx_rst_wr_sync_mux_x6_top.clk
		i_xcvrif_tx_rst_wr_sync_mux_x8_bot          : in  std_logic                      := '0';             --     i_xcvrif_tx_rst_wr_sync_mux_x8_bot.clk
		i_xcvrif_tx_rst_wr_sync_mux_x8_top          : in  std_logic                      := '0';             --     i_xcvrif_tx_rst_wr_sync_mux_x8_top.clk
		ss_user_rx_clk1_clk                         : out std_logic;                                         --                    ss_user_rx_clk1_clk.clk
		ss_user_rx_clk2_clk                         : out std_logic;                                         --                    ss_user_rx_clk2_clk.clk
		ss_user_tx_clk1_clk                         : out std_logic;                                         --                    ss_user_tx_clk1_clk.clk
		ss_user_tx_clk2_clk                         : out std_logic;                                         --                    ss_user_tx_clk2_clk.clk
		ss_user_rx_clk1_clk_w                       : out std_logic;                                         --                  ss_user_rx_clk1_clk_w.clk
		ss_user_rx_clk2_clk_w                       : out std_logic;                                         --                  ss_user_rx_clk2_clk_w.clk
		ss_user_tx_clk1_clk_w                       : out std_logic;                                         --                  ss_user_tx_clk1_clk_w.clk
		ss_user_tx_clk2_clk_w                       : out std_logic;                                         --                  ss_user_tx_clk2_clk_w.clk
		o_hio_ux_tx_ch_ptr_smpl                     : out std_logic                                          --                o_hio_ux_tx_ch_ptr_smpl.data
	);
end entity gts_axi_streaming_pcie_hal_top_one_lane_pcie_hal_2100_ltignja;

architecture rtl of gts_axi_streaming_pcie_hal_top_one_lane_pcie_hal_2100_ltignja is
	component gts_axi_streaming_one_lane_pcie_hal_2100_2acwd3y_cmp is
		generic (
			ch_tx_channel_mode            : string := "PMAD";
			ch_rx_channel_mode            : string := "PMAD";
			ch_mac_sf_en                  : string := "ENABLED";
			ch_pldif_sf_en                : string := "ENABLED";
			ch_pcs_sf_en                  : string := "ENABLED";
			ch_fec_sf_en                  : string := "ENABLED";
			ch_SF_PCS_TXMUX_EN            : string := "ENABLED";
			ch_SF_PCS_RXMUX_EN            : string := "ENABLED";
			ch_SF_FEC_TXMUX_EN            : string := "ENABLED";
			ch_SF_FEC_INGRESS_EN          : string := "ENABLED";
			ch_SF_FEC_EGRESS_EN           : string := "ENABLED";
			ch_SF_PLDCH_TX_USER1_MUX_EN   : string := "ENABLED";
			ch_SF_PLDCH_TX_USER2_MUX_EN   : string := "ENABLED";
			ch_SF_PLDCH_RX_USER1_MUX_EN   : string := "ENABLED";
			ch_SF_PLDCH_RX_USER2_MUX_EN   : string := "ENABLED";
			ch_SF_DESKEW_EN               : string := "ENABLED";
			ch_SF_DESKEW_RXMUX_EN         : string := "ENABLED";
			ch_SF_PTP_INGRESS_EN          : string := "ENABLED";
			ch_SF_PTP_EGRESS_EN           : string := "ENABLED";
			ch_SF_PTP_S_EN                : string := "ENABLED";
			ch_SF_PTP_EN                  : string := "ENABLED";
			ch_SF_UX_EN                   : string := "ENABLED";
			ch_SF_FLUX_GLOBAL_MEM_EN      : string := "ENABLED";
			ch_SF_FLUX_S_EN               : string := "ENABLED";
			ch_SF_FLUX_TXUSER_CLK1_MUX_EN : string := "ENABLED";
			ch_SF_FLUX_TXUSER_CLK2_MUX_EN : string := "ENABLED";
			ch_SF_FLUX_RXUSER_CLK1_MUX_EN : string := "ENABLED";
			ch_SF_FLUX_RXUSER_CLK2_MUX_EN : string := "ENABLED";
			ch_SF_FLUX_I_EN               : string := "ENABLED";
			ch_SF_UX_TOOLBOX_EN           : string := "ENABLED";
			ch_SF_FLUX_CORE_EN            : string := "ENABLED";
			ch_SF_XCVRIF_1CH_EN           : string := "ENABLED";
			ch_SF_XCVRIF_TXMUX_EN         : string := "ENABLED";
			ch_SF_XCRIF_TX_RST_MUX_EN     : string := "ENABLED";
			ch_SF_XCRIF_TX_WREN_MUX_EN    : string := "ENABLED";
			ch_SF_XCRIF_TX_RDEN_MUX_EN    : string := "ENABLED";
			ch_SF_XCRIF_TXWORD_CLK_MUX_EN : string := "ENABLED";
			ch_SF_XCRIF_RXWORD_CLK_MUX_EN : string := "ENABLED"
		);
		port (
			i_hio_txdata                                : in  std_logic_vector(79 downto 0)  := (others => 'X'); -- data
			i_hio_txdata_extra                          : in  std_logic_vector(9 downto 0)   := (others => 'X'); -- data
			i_hio_txdata_fifo_wr_en                     : in  std_logic                      := 'X';             -- data
			i_hio_rxdata_fifo_rd_en                     : in  std_logic                      := 'X';             -- data
			i_hio_ptp_rst_n                             : in  std_logic                      := 'X';             -- reset
			i_hio_ehip_rx_rst_n                         : in  std_logic                      := 'X';             -- reset
			i_hio_ehip_tx_rst_n                         : in  std_logic                      := 'X';             -- reset
			i_hio_ehip_signal_ok                        : in  std_logic                      := 'X';             -- reset
			i_hio_sfreeze_2_r03f_rx_mac_srfz_n          : in  std_logic                      := 'X';             -- reset
			i_hio_sfreeze_3_c2f_tx_deskew_srfz_n        : in  std_logic                      := 'X';             -- reset
			i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n          : in  std_logic                      := 'X';             -- reset
			i_hio_rstfec_fec_rx_rst_n                   : in  std_logic                      := 'X';             -- reset
			i_hio_rstfec_fec_tx_rst_n                   : in  std_logic                      := 'X';             -- reset
			i_hio_rstfec_fec_csr_ret                    : in  std_logic                      := 'X';             -- reset
			i_hio_rstfec_rx_fec_sfrz_n                  : in  std_logic                      := 'X';             -- reset
			i_hio_rstfec_tx_fec_sfrz_n                  : in  std_logic                      := 'X';             -- reset
			i_hio_rstxcvrif_xcvrif_rx_rst_n             : in  std_logic                      := 'X';             -- reset
			i_hio_rstxcvrif_xcvrif_tx_rst_n             : in  std_logic                      := 'X';             -- reset
			i_hio_rstxcvrif_xcvrif_signal_ok            : in  std_logic                      := 'X';             -- reset
			i_hio_rstxcvrif_rx_xcvrif_sfrz_n            : in  std_logic                      := 'X';             -- reset
			i_hio_rstxcvrif_tx_xcvrif_sfrz_n            : in  std_logic                      := 'X';             -- reset
			i_hio_rst_pld_clrhip                        : in  std_logic                      := 'X';             -- reset
			i_hio_rst_pld_clrpcs                        : in  std_logic                      := 'X';             -- reset
			i_hio_rst_pld_perstn                        : in  std_logic                      := 'X';             -- reset
			i_hio_rst_pld_ready                         : in  std_logic                      := 'X';             -- reset
			i_hio_rst_pld_adapter_rx_pld_rst_n          : in  std_logic                      := 'X';             -- reset
			i_hio_rst_pld_adapter_tx_pld_rst_n          : in  std_logic                      := 'X';             -- reset
			i_hio_rst_ux_rx_pma_rst_n                   : in  std_logic                      := 'X';             -- reset
			i_hio_rst_ux_rx_sfrz                        : in  std_logic                      := 'X';             -- reset
			i_hio_rst_ux_tx_pma_rst_n                   : in  std_logic                      := 'X';             -- reset
			i_hio_pld_reset_clk_row                     : in  std_logic                      := 'X';             -- reset
			i_hio_uxquad_async                          : in  std_logic_vector(79 downto 0)  := (others => 'X'); -- data
			i_hio_uxquad_async_pcie_mux                 : in  std_logic_vector(79 downto 0)  := (others => 'X'); -- data
			i_hio_lavmm_addr                            : in  std_logic_vector(20 downto 0)  := (others => 'X'); -- address
			i_hio_lavmm_be                              : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- byteenable
			i_hio_lavmm_read                            : in  std_logic                      := 'X';             -- read
			i_hio_lavmm_wdata                           : in  std_logic_vector(31 downto 0)  := (others => 'X'); -- writedata
			i_hio_lavmm_write                           : in  std_logic                      := 'X';             -- write
			o_hio_lavmm_rdata                           : out std_logic_vector(31 downto 0);                     -- readdata
			o_hio_lavmm_rdata_valid                     : out std_logic;                                         -- readdatavalid
			o_hio_lavmm_waitreq                         : out std_logic;                                         -- waitrequest
			i_hio_lavmm_clk                             : in  std_logic                      := 'X';             -- clk
			i_hio_lavmm_rstn                            : in  std_logic                      := 'X';             -- reset
			o_ss_lavmm_pcie_addr                        : out std_logic_vector(16 downto 0);                     -- address
			o_ss_lavmm_pcie_be                          : out std_logic_vector(3 downto 0);                      -- byteenable
			o_ss_lavmm_pcie_read                        : out std_logic;                                         -- read
			o_ss_lavmm_pcie_wdata                       : out std_logic_vector(31 downto 0);                     -- writedata
			o_ss_lavmm_pcie_write                       : out std_logic;                                         -- write
			i_ss_lavmm_pcie_rdata                       : in  std_logic_vector(31 downto 0)  := (others => 'X'); -- readdata
			i_ss_lavmm_pcie_rdata_valid                 : in  std_logic                      := 'X';             -- readdatavalid
			i_ss_lavmm_pcie_waitreq                     : in  std_logic                      := 'X';             -- waitrequest
			o_ss_lavmm_pcie_clk                         : out std_logic;                                         -- clk
			o_ss_lavmm_pcie_rstn                        : out std_logic;                                         -- reset
			sm_pld_tx_demux_0_o_pcie                    : out std_logic_vector(79 downto 0);                     -- data
			sm_pld_rx_mux_0_i_pcie                      : in  std_logic_vector(79 downto 0)  := (others => 'X'); -- data
			o_pld_pcie_clk_4                            : in  std_logic                      := 'X';             -- clk
			o_pcie_rxword_clk                           : out std_logic;                                         -- clk
			o_pcie_txword_clk                           : out std_logic;                                         -- clk
			ss_rst_ux_rxcdrlock2data                    : out std_logic;                                         -- data
			o_rxeq_best_eye_vala                        : out std_logic_vector(13 downto 0);                     -- data
			o_rxeq_donea                                : out std_logic;                                         -- data
			o_rxmargin_nacka                            : out std_logic;                                         -- data
			o_rxmargin_statusa                          : out std_logic;                                         -- data
			o_rxsignaldetect_lfpsa                      : out std_logic;                                         -- data
			o_rxsignaldetecta                           : out std_logic;                                         -- data
			o_rxmargin_status_gray                      : out std_logic_vector(1 downto 0);                      -- data
			rxstatusa                                   : out std_logic;                                         -- data
			o_pcie_pcs                                  : out std_logic_vector(39 downto 0);                     -- data
			i_pcie_pcs                                  : in  std_logic_vector(39 downto 0)  := (others => 'X'); -- data
			o_synthlcfast_postdiv                       : out std_logic;                                         -- data
			o_synthlcmed_postdiv                        : out std_logic;                                         -- data
			o_synthlcslow_postdiv                       : out std_logic;                                         -- data
			o_txdetectrx_acka                           : out std_logic;                                         -- data
			o_txdetectrx_statct                         : out std_logic;                                         -- data
			txstatusa                                   : out std_logic;                                         -- data
			i_pcs_pipe_rstn                             : in  std_logic                      := 'X';             -- data
			i_ux_ock_pma_clk                            : in  std_logic                      := 'X';             -- data
			i_lfps_ennt                                 : in  std_logic                      := 'X';             -- data
			i_pcie_l1ctrla                              : in  std_logic_vector(1 downto 0)   := (others => 'X'); -- data
			i_pma_cmn_ctrl                              : in  std_logic                      := 'X';             -- data
			i_pma_ctrl                                  : in  std_logic                      := 'X';             -- data
			i_pcie_pcs_rx_rst                           : in  std_logic                      := 'X';             -- data
			i_pcie_pcs_tx_rst                           : in  std_logic                      := 'X';             -- data
			i_rxeiosdetectstata                         : in  std_logic                      := 'X';             -- data
			i_rxeq_precal_code_selnt                    : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_rxeq_starta                               : in  std_logic                      := 'X';             -- data
			i_rxeq_static_ena                           : in  std_logic                      := 'X';             -- data
			i_rxmargin_direction_nt                     : in  std_logic                      := 'X';             -- data
			i_rxmargin_mode_nt                          : in  std_logic                      := 'X';             -- data
			i_rxmargin_offset_change_a                  : in  std_logic                      := 'X';             -- data
			i_rxmargin_offset_nt                        : in  std_logic_vector(6 downto 0)   := (others => 'X'); -- data
			i_rxmargin_start_a                          : in  std_logic                      := 'X';             -- data
			i_rxpstate                                  : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_rxrate                                    : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- data
			i_rxterm_hiz_ena                            : in  std_logic                      := 'X';             -- data
			i_rxwidth                                   : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_tstbus_lane                               : in  std_logic                      := 'X';             -- data
			i_txbeacona                                 : in  std_logic                      := 'X';             -- data
			i_txclkdivrate                              : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_txdetectrx_reqa                           : in  std_logic                      := 'X';             -- data
			i_txdrv_levn                                : in  std_logic_vector(5 downto 0)   := (others => 'X'); -- data
			i_txdrv_levnm1                              : in  std_logic_vector(4 downto 0)   := (others => 'X'); -- data
			i_txdrv_levnm2                              : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_txdrv_levnp1                              : in  std_logic_vector(4 downto 0)   := (others => 'X'); -- data
			i_txdrv_slew                                : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- data
			i_txelecidle                                : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- data
			i_txpstate                                  : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_txrate                                    : in  std_logic_vector(3 downto 0)   := (others => 'X'); -- data
			i_txwidth                                   : in  std_logic_vector(2 downto 0)   := (others => 'X'); -- data
			i_hio_pld_rx_clk_in_row_clk                 : in  std_logic                      := 'X';             -- clk
			i_hio_pld_tx_clk_in_row_clk                 : in  std_logic                      := 'X';             -- clk
			i_hio_det_lat_rx_dl_clk                     : in  std_logic                      := 'X';             -- clk
			i_hio_det_lat_rx_mux_select                 : in  std_logic                      := 'X';             -- clk
			i_hio_det_lat_rx_sclk_flop                  : in  std_logic                      := 'X';             -- clk
			i_hio_det_lat_rx_sclk_gen_clk               : in  std_logic                      := 'X';             -- clk
			i_hio_det_lat_rx_trig_flop                  : in  std_logic                      := 'X';             -- clk
			i_hio_det_lat_sampling_clk                  : in  std_logic                      := 'X';             -- clk
			i_hio_det_lat_tx_dl_clk                     : in  std_logic                      := 'X';             -- clk
			i_hio_det_lat_tx_mux_select                 : in  std_logic                      := 'X';             -- clk
			i_hio_det_lat_tx_sclk_flop                  : in  std_logic                      := 'X';             -- clk
			i_hio_det_lat_tx_sclk_gen_clk               : in  std_logic                      := 'X';             -- clk
			i_hio_det_lat_tx_trig_flop                  : in  std_logic                      := 'X';             -- clk
			rx_serial_n                                 : in  std_logic                      := 'X';             -- data
			rx_serial_p                                 : in  std_logic                      := 'X';             -- data
			o_hio_txdata_fifo_wr_empty                  : out std_logic;                                         -- data
			o_hio_txdata_fifo_wr_pempty                 : out std_logic;                                         -- data
			o_hio_txdata_fifo_wr_full                   : out std_logic;                                         -- data
			o_hio_txdata_fifo_wr_pfull                  : out std_logic;                                         -- data
			o_hio_rxdata                                : out std_logic_vector(79 downto 0);                     -- data
			o_hio_rxdata_extra                          : out std_logic_vector(9 downto 0);                      -- data
			o_hio_rxdata_fifo_rd_empty                  : out std_logic;                                         -- data
			o_hio_rxdata_fifo_rd_pempty                 : out std_logic;                                         -- data
			o_hio_rxdata_fifo_rd_full                   : out std_logic;                                         -- data
			o_hio_rxdata_fifo_rd_pfull                  : out std_logic;                                         -- data
			o_hio_rstepcs_rx_pcs_fully_aligned          : out std_logic;                                         -- reset
			o_hio_rstfec_fec_rx_rdy_n                   : out std_logic;                                         -- reset
			o_hio_rst_flux0_cpi_cmn_busy                : out std_logic;                                         -- reset
			o_hio_rst_oflux_rx_srds_rdy                 : out std_logic;                                         -- reset
			o_hio_rst_ux_all_synthlockstatus            : out std_logic;                                         -- reset
			o_hio_rst_ux_octl_pcs_rxstatus              : out std_logic;                                         -- reset
			o_hio_rst_ux_octl_pcs_txstatus              : out std_logic;                                         -- reset
			o_hio_rst_ux_rxcdrlock2data                 : out std_logic;                                         -- reset
			o_hio_rst_ux_rxcdrlockstatus                : out std_logic;                                         -- reset
			o_hio_uxquad_async                          : out std_logic_vector(49 downto 0);                     -- data
			o_hio_user_rx_clk1_clk                      : out std_logic;                                         -- clk
			o_hio_user_rx_clk2_clk                      : out std_logic;                                         -- clk
			o_hio_user_tx_clk1_clk                      : out std_logic;                                         -- clk
			o_hio_user_tx_clk2_clk                      : out std_logic;                                         -- clk
			o_hio_ux_chnl_refclk_mux                    : out std_logic;                                         -- clk
			o_hio_det_lat_rx_async_dl_sync              : out std_logic;                                         -- clk
			o_hio_det_lat_rx_async_pulse                : out std_logic;                                         -- clk
			o_hio_det_lat_rx_async_sample_sync          : out std_logic;                                         -- clk
			o_hio_det_lat_rx_sclk_sample_sync           : out std_logic;                                         -- clk
			o_hio_det_lat_rx_trig_sample_sync           : out std_logic;                                         -- clk
			o_hio_det_lat_tx_async_dl_sync              : out std_logic;                                         -- clk
			o_hio_det_lat_tx_async_pulse                : out std_logic;                                         -- clk
			o_hio_det_lat_tx_async_sample_sync          : out std_logic;                                         -- clk
			o_hio_det_lat_tx_sclk_sample_sync           : out std_logic;                                         -- clk
			o_hio_det_lat_tx_trig_sample_sync           : out std_logic;                                         -- clk
			o_hio_xcvrif_rx_latency_pulse               : out std_logic;                                         -- clk
			o_hio_xcvrif_tx_latency_pulse               : out std_logic;                                         -- clk
			tx_serial_p                                 : out std_logic;                                         -- data
			tx_serial_n                                 : out std_logic;                                         -- data
			i_hio_txdata_async                          : in  std_logic_vector(99 downto 0)  := (others => 'X'); -- data
			i_hio_txdata_direct                         : in  std_logic_vector(9 downto 0)   := (others => 'X'); -- data
			o_hio_rxdata_async                          : out std_logic_vector(99 downto 0);                     -- data
			o_hio_rxdata_direct                         : out std_logic_vector(9 downto 0);                      -- data
			i_uxwrap_bus_in_phy_shared                  : in  std_logic_vector(767 downto 0) := (others => 'X'); -- data
			o_uxwrap_bus_out_phy_shared                 : out std_logic_vector(703 downto 0);                    -- data
			o_lavmm_addr_phy_shared                     : out std_logic_vector(19 downto 0);                     -- address
			o_lavmm_be_phy_shared                       : out std_logic_vector(3 downto 0);                      -- byteenable
			o_lavmm_read_phy_shared                     : out std_logic;                                         -- read
			o_lavmm_wdata_phy_shared                    : out std_logic_vector(31 downto 0);                     -- writedata
			o_lavmm_write_phy_shared                    : out std_logic;                                         -- write
			i_lavmm_rdata_phy_shared                    : in  std_logic_vector(31 downto 0)  := (others => 'X'); -- readdata
			i_lavmm_rdata_valid_phy_shared              : in  std_logic                      := 'X';             -- readdatavalid
			i_lavmm_waitreq_phy_shared                  : in  std_logic                      := 'X';             -- waitrequest
			o_lavmm_clk_phy_shared                      : out std_logic;                                         -- clk
			o_lavmm_rstn_phy_shared                     : out std_logic;                                         -- reset
			o_sclk_return_sel_rx_phy_shared             : out std_logic;                                         -- data
			o_sclk_return_sel_tx_phy_shared             : out std_logic;                                         -- data
			o_ick_sclk_rx_phy_shared                    : out std_logic;                                         -- clk
			i_sync_common_control_phy_shared            : in  std_logic_vector(4 downto 0)   := (others => 'X'); -- data
			o_ft_rx_sclk_sync_ch_phy_shared             : out std_logic;                                         -- data
			o_ft_tx_sclk_sync_ch_phy_shared             : out std_logic;                                         -- data
			o_rst_ux_rx_pma_rst_n_phy_shared            : out std_logic;                                         -- reset
			o_rst_ux_tx_pma_rst_n_phy_shared            : out std_logic;                                         -- reset
			o_ick_pcs_txword_phy_shared                 : out std_logic;                                         -- data
			o_tx_dl_ch_bit_phy_shared                   : out std_logic;                                         -- data
			i_dat_pcs_measlatbit_phy_shared             : in  std_logic                      := 'X';             -- data
			i_ft_rx_async_pulse_ch_phy_shared           : in  std_logic                      := 'X';             -- data
			i_ft_tx_async_pulse_ch_phy_shared           : in  std_logic                      := 'X';             -- data
			i_rx_dl_ch_bit_phy_shared                   : in  std_logic                      := 'X';             -- data
			i_ux_rxuser1_sel_phy_shared                 : in  std_logic_vector(1 downto 0)   := (others => 'X'); -- data
			i_ux_rxuser2_sel_phy_shared                 : in  std_logic_vector(1 downto 0)   := (others => 'X'); -- data
			i_ux_txuser1_sel_phy_shared                 : in  std_logic_vector(1 downto 0)   := (others => 'X'); -- data
			i_ux_txuser2_sel_phy_shared                 : in  std_logic_vector(1 downto 0)   := (others => 'X'); -- data
			o_octl_pcs_txstatus_a_phy_shared            : out std_logic;                                         -- data
			i_ictl_pcs_txenable_a_phy_shared            : in  std_logic                      := 'X';             -- data
			i_sync_cfg_data_phy_shared                  : in  std_logic_vector(124 downto 0) := (others => 'X'); -- data
			i_sync_interface_control_phy_shared         : in  std_logic_vector(249 downto 0) := (others => 'X'); -- data
			o_tx_data_phy_shared                        : out std_logic_vector(79 downto 0);                     -- data
			i_rx_data_phy_shared                        : in  std_logic_vector(79 downto 0)  := (others => 'X'); -- data
			o_sm_flux_ingress_phy_shared                : out std_logic_vector(319 downto 0);                    -- data
			i_sm_flux_egress_phy_shared                 : in  std_logic_vector(256 downto 0) := (others => 'X'); -- data
			i_flux_cpi_int_phy_shared                   : in  std_logic                      := 'X';             -- data
			i_flux_int_phy_shared                       : in  std_logic                      := 'X';             -- data
			i_oflux_octl_pcs_txptr_smpl_lane_phy_shared : in  std_logic                      := 'X';             -- data
			o_ick_sclk_tx_phy_shared                    : out std_logic;                                         -- clk
			i_flux_srds_rdy_phy_shared                  : in  std_logic                      := 'X';             -- data
			i_pcs_rxword_phy_shared                     : in  std_logic                      := 'X';             -- data
			i_pcs_rxpostdiv_phy_shared                  : in  std_logic                      := 'X';             -- data
			i_ock_pcs_txword_phy_shared                 : in  std_logic                      := 'X';             -- data
			o_dat_pcs_measlatrndtripbit_phy_shared      : out std_logic;                                         -- data
			i_ch_eth_fec_rx_async_fec_wrap              : in  std_logic_vector(11 downto 0)  := (others => 'X'); -- data
			i_ch_eth_fec_rx_direct_fec_wrap             : in  std_logic                      := 'X';             -- data
			i_fec_rx_rdy_n_fec_wrap                     : in  std_logic                      := 'X';             -- data
			i_fec_tx_data_mux_sel_fec_wrap              : in  std_logic                      := 'X';             -- muxsel
			i_fec_rx_data_fec_wrap                      : in  std_logic_vector(42 downto 0)  := (others => 'X'); -- data
			i_xcvr_tx_data                              : in  std_logic_vector(42 downto 0)  := (others => 'X'); -- data
			ss_rst_flux0_cpi_cmn_busy                   : out std_logic;                                         -- data
			o_pma_rx_sf                                 : out std_logic;                                         -- data
			i_refclk_tx_p                               : in  std_logic                      := 'X';             -- clk
			i_syspll_c0_clk                             : in  std_logic                      := 'X';             -- clk
			i_syspll_c1_clk                             : in  std_logic                      := 'X';             -- clk
			i_syspll_c2_clk                             : in  std_logic                      := 'X';             -- clk
			i_flux_clk                                  : in  std_logic                      := 'X';             -- clk
			i_refclk_rx_p                               : in  std_logic                      := 'X';             -- clk
			i_ux_chnl_refclk_mux_phy_shared             : in  std_logic                      := 'X';             -- clk
			o_xcvrif_tx_fifo_rd_en_mux_x1               : out std_logic;                                         -- clk
			i_xcvrif_tx_fifo_rd_en_mux_x2               : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_fifo_rd_en_mux_x4               : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_fifo_rd_en_mux_x6_bot           : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_fifo_rd_en_mux_x6_top           : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_fifo_rd_en_mux_x8_bot           : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_fifo_rd_en_mux_x8_top           : in  std_logic                      := 'X';             -- clk
			o_xcvrif_tx_rst_mux_x1                      : out std_logic;                                         -- clk
			i_xcvrif_tx_rst_mux_x2                      : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_rst_mux_x4                      : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_rst_mux_x6_bot                  : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_rst_mux_x6_top                  : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_rst_mux_x8_bot                  : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_rst_mux_x8_top                  : in  std_logic                      := 'X';             -- clk
			o_xcvrif_tx_word_clk_mux_x1                 : out std_logic;                                         -- clk
			i_xcvrif_tx_word_clk_mux_x2                 : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_word_clk_mux_x4                 : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_word_clk_mux_x6_bot             : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_word_clk_mux_x6_top             : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_word_clk_mux_x8_bot             : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_word_clk_mux_x8_top             : in  std_logic                      := 'X';             -- clk
			ioack_cdrdiv_left_ux_bidir_in               : in  std_logic                      := 'X';             -- clk
			ioack_synthdiv1_left_ux_bidir_in            : in  std_logic                      := 'X';             -- clk
			ioack_synthdiv2_left_ux_bidir_in            : in  std_logic                      := 'X';             -- clk
			ioack_cdrdiv_left_ux_bidir_out              : out std_logic;                                         -- clk
			ioack_synthdiv1_left_ux_bidir_out           : out std_logic;                                         -- clk
			ioack_synthdiv2_left_ux_bidir_out           : out std_logic;                                         -- clk
			o_xcvrif_tx_rst_wr_sync_mux_x1              : out std_logic;                                         -- clk
			i_xcvrif_tx_rst_wr_sync_mux_x2              : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_rst_wr_sync_mux_x4              : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_rst_wr_sync_mux_x6_bot          : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_rst_wr_sync_mux_x6_top          : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_rst_wr_sync_mux_x8_bot          : in  std_logic                      := 'X';             -- clk
			i_xcvrif_tx_rst_wr_sync_mux_x8_top          : in  std_logic                      := 'X';             -- clk
			ss_user_rx_clk1_clk                         : out std_logic;                                         -- clk
			ss_user_rx_clk2_clk                         : out std_logic;                                         -- clk
			ss_user_tx_clk1_clk                         : out std_logic;                                         -- clk
			ss_user_tx_clk2_clk                         : out std_logic;                                         -- clk
			ss_user_rx_clk1_clk_w                       : out std_logic;                                         -- clk
			ss_user_rx_clk2_clk_w                       : out std_logic;                                         -- clk
			ss_user_tx_clk1_clk_w                       : out std_logic;                                         -- clk
			ss_user_tx_clk2_clk_w                       : out std_logic;                                         -- clk
			o_hio_ux_tx_ch_ptr_smpl                     : out std_logic                                          -- data
		);
	end component gts_axi_streaming_one_lane_pcie_hal_2100_2acwd3y_cmp;

	for one_lane_pcie_hal_top_p2 : gts_axi_streaming_one_lane_pcie_hal_2100_2acwd3y_cmp
		use entity one_lane_pcie_hal_2100.gts_axi_streaming_one_lane_pcie_hal_2100_2acwd3y;
begin

	ch_tx_channel_mode_check : if ch_tx_channel_mode /= "PMAD" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_rx_channel_mode_check : if ch_rx_channel_mode /= "PMAD" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_mac_sf_en_check : if ch_mac_sf_en /= "DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pldif_sf_en_check : if ch_pldif_sf_en /= "DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_pcs_sf_en_check : if ch_pcs_sf_en /= "DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_fec_sf_en_check : if ch_fec_sf_en /= "DISABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_pcs_txmux_en_check : if ch_SF_PCS_TXMUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_pcs_rxmux_en_check : if ch_SF_PCS_RXMUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_fec_txmux_en_check : if ch_SF_FEC_TXMUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_fec_ingress_en_check : if ch_SF_FEC_INGRESS_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_fec_egress_en_check : if ch_SF_FEC_EGRESS_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_pldch_tx_user1_mux_en_check : if ch_SF_PLDCH_TX_USER1_MUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_pldch_tx_user2_mux_en_check : if ch_SF_PLDCH_TX_USER2_MUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_pldch_rx_user1_mux_en_check : if ch_SF_PLDCH_RX_USER1_MUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_pldch_rx_user2_mux_en_check : if ch_SF_PLDCH_RX_USER2_MUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_deskew_en_check : if ch_SF_DESKEW_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_deskew_rxmux_en_check : if ch_SF_DESKEW_RXMUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_ptp_ingress_en_check : if ch_SF_PTP_INGRESS_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_ptp_egress_en_check : if ch_SF_PTP_EGRESS_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_ptp_s_en_check : if ch_SF_PTP_S_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_ptp_en_check : if ch_SF_PTP_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_ux_en_check : if ch_SF_UX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_flux_global_mem_en_check : if ch_SF_FLUX_GLOBAL_MEM_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_flux_s_en_check : if ch_SF_FLUX_S_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_flux_txuser_clk1_mux_en_check : if ch_SF_FLUX_TXUSER_CLK1_MUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_flux_txuser_clk2_mux_en_check : if ch_SF_FLUX_TXUSER_CLK2_MUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_flux_rxuser_clk1_mux_en_check : if ch_SF_FLUX_RXUSER_CLK1_MUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_flux_rxuser_clk2_mux_en_check : if ch_SF_FLUX_RXUSER_CLK2_MUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_flux_i_en_check : if ch_SF_FLUX_I_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_ux_toolbox_en_check : if ch_SF_UX_TOOLBOX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_flux_core_en_check : if ch_SF_FLUX_CORE_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_xcvrif_1ch_en_check : if ch_SF_XCVRIF_1CH_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_xcvrif_txmux_en_check : if ch_SF_XCVRIF_TXMUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_xcrif_tx_rst_mux_en_check : if ch_SF_XCRIF_TX_RST_MUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_xcrif_tx_wren_mux_en_check : if ch_SF_XCRIF_TX_WREN_MUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_xcrif_tx_rden_mux_en_check : if ch_SF_XCRIF_TX_RDEN_MUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_xcrif_txword_clk_mux_en_check : if ch_SF_XCRIF_TXWORD_CLK_MUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	ch_sf_xcrif_rxword_clk_mux_en_check : if ch_SF_XCRIF_RXWORD_CLK_MUX_EN /= "ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	one_lane_pcie_hal_top_p2 : component gts_axi_streaming_one_lane_pcie_hal_2100_2acwd3y_cmp
		generic map (
			ch_tx_channel_mode            => "PMAD",
			ch_rx_channel_mode            => "PMAD",
			ch_mac_sf_en                  => "DISABLED",
			ch_pldif_sf_en                => "DISABLED",
			ch_pcs_sf_en                  => "DISABLED",
			ch_fec_sf_en                  => "DISABLED",
			ch_SF_PCS_TXMUX_EN            => "ENABLED",
			ch_SF_PCS_RXMUX_EN            => "ENABLED",
			ch_SF_FEC_TXMUX_EN            => "ENABLED",
			ch_SF_FEC_INGRESS_EN          => "ENABLED",
			ch_SF_FEC_EGRESS_EN           => "ENABLED",
			ch_SF_PLDCH_TX_USER1_MUX_EN   => "ENABLED",
			ch_SF_PLDCH_TX_USER2_MUX_EN   => "ENABLED",
			ch_SF_PLDCH_RX_USER1_MUX_EN   => "ENABLED",
			ch_SF_PLDCH_RX_USER2_MUX_EN   => "ENABLED",
			ch_SF_DESKEW_EN               => "ENABLED",
			ch_SF_DESKEW_RXMUX_EN         => "ENABLED",
			ch_SF_PTP_INGRESS_EN          => "ENABLED",
			ch_SF_PTP_EGRESS_EN           => "ENABLED",
			ch_SF_PTP_S_EN                => "ENABLED",
			ch_SF_PTP_EN                  => "ENABLED",
			ch_SF_UX_EN                   => "ENABLED",
			ch_SF_FLUX_GLOBAL_MEM_EN      => "ENABLED",
			ch_SF_FLUX_S_EN               => "ENABLED",
			ch_SF_FLUX_TXUSER_CLK1_MUX_EN => "ENABLED",
			ch_SF_FLUX_TXUSER_CLK2_MUX_EN => "ENABLED",
			ch_SF_FLUX_RXUSER_CLK1_MUX_EN => "ENABLED",
			ch_SF_FLUX_RXUSER_CLK2_MUX_EN => "ENABLED",
			ch_SF_FLUX_I_EN               => "ENABLED",
			ch_SF_UX_TOOLBOX_EN           => "ENABLED",
			ch_SF_FLUX_CORE_EN            => "ENABLED",
			ch_SF_XCVRIF_1CH_EN           => "ENABLED",
			ch_SF_XCVRIF_TXMUX_EN         => "ENABLED",
			ch_SF_XCRIF_TX_RST_MUX_EN     => "ENABLED",
			ch_SF_XCRIF_TX_WREN_MUX_EN    => "ENABLED",
			ch_SF_XCRIF_TX_RDEN_MUX_EN    => "ENABLED",
			ch_SF_XCRIF_TXWORD_CLK_MUX_EN => "ENABLED",
			ch_SF_XCRIF_RXWORD_CLK_MUX_EN => "ENABLED"
		)
		port map (
			i_hio_txdata                                => i_hio_txdata,                                --                           i_hio_txdata.data
			i_hio_txdata_extra                          => i_hio_txdata_extra,                          --                     i_hio_txdata_extra.data
			i_hio_txdata_fifo_wr_en                     => i_hio_txdata_fifo_wr_en,                     --                i_hio_txdata_fifo_wr_en.data
			i_hio_rxdata_fifo_rd_en                     => i_hio_rxdata_fifo_rd_en,                     --                i_hio_rxdata_fifo_rd_en.data
			i_hio_ptp_rst_n                             => i_hio_ptp_rst_n,                             --                        i_hio_ptp_rst_n.reset
			i_hio_ehip_rx_rst_n                         => i_hio_ehip_rx_rst_n,                         --                    i_hio_ehip_rx_rst_n.reset
			i_hio_ehip_tx_rst_n                         => i_hio_ehip_tx_rst_n,                         --                    i_hio_ehip_tx_rst_n.reset
			i_hio_ehip_signal_ok                        => i_hio_ehip_signal_ok,                        --                   i_hio_ehip_signal_ok.reset
			i_hio_sfreeze_2_r03f_rx_mac_srfz_n          => i_hio_sfreeze_2_r03f_rx_mac_srfz_n,          --     i_hio_sfreeze_2_r03f_rx_mac_srfz_n.reset
			i_hio_sfreeze_3_c2f_tx_deskew_srfz_n        => i_hio_sfreeze_3_c2f_tx_deskew_srfz_n,        --   i_hio_sfreeze_3_c2f_tx_deskew_srfz_n.reset
			i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n          => i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n,          --     i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n.reset
			i_hio_rstfec_fec_rx_rst_n                   => i_hio_rstfec_fec_rx_rst_n,                   --              i_hio_rstfec_fec_rx_rst_n.reset
			i_hio_rstfec_fec_tx_rst_n                   => i_hio_rstfec_fec_tx_rst_n,                   --              i_hio_rstfec_fec_tx_rst_n.reset
			i_hio_rstfec_fec_csr_ret                    => i_hio_rstfec_fec_csr_ret,                    --               i_hio_rstfec_fec_csr_ret.reset
			i_hio_rstfec_rx_fec_sfrz_n                  => i_hio_rstfec_rx_fec_sfrz_n,                  --             i_hio_rstfec_rx_fec_sfrz_n.reset
			i_hio_rstfec_tx_fec_sfrz_n                  => i_hio_rstfec_tx_fec_sfrz_n,                  --             i_hio_rstfec_tx_fec_sfrz_n.reset
			i_hio_rstxcvrif_xcvrif_rx_rst_n             => i_hio_rstxcvrif_xcvrif_rx_rst_n,             --        i_hio_rstxcvrif_xcvrif_rx_rst_n.reset
			i_hio_rstxcvrif_xcvrif_tx_rst_n             => i_hio_rstxcvrif_xcvrif_tx_rst_n,             --        i_hio_rstxcvrif_xcvrif_tx_rst_n.reset
			i_hio_rstxcvrif_xcvrif_signal_ok            => i_hio_rstxcvrif_xcvrif_signal_ok,            --       i_hio_rstxcvrif_xcvrif_signal_ok.reset
			i_hio_rstxcvrif_rx_xcvrif_sfrz_n            => i_hio_rstxcvrif_rx_xcvrif_sfrz_n,            --       i_hio_rstxcvrif_rx_xcvrif_sfrz_n.reset
			i_hio_rstxcvrif_tx_xcvrif_sfrz_n            => i_hio_rstxcvrif_tx_xcvrif_sfrz_n,            --       i_hio_rstxcvrif_tx_xcvrif_sfrz_n.reset
			i_hio_rst_pld_clrhip                        => i_hio_rst_pld_clrhip,                        --                   i_hio_rst_pld_clrhip.reset
			i_hio_rst_pld_clrpcs                        => i_hio_rst_pld_clrpcs,                        --                   i_hio_rst_pld_clrpcs.reset
			i_hio_rst_pld_perstn                        => i_hio_rst_pld_perstn,                        --                   i_hio_rst_pld_perstn.reset
			i_hio_rst_pld_ready                         => i_hio_rst_pld_ready,                         --                    i_hio_rst_pld_ready.reset
			i_hio_rst_pld_adapter_rx_pld_rst_n          => i_hio_rst_pld_adapter_rx_pld_rst_n,          --     i_hio_rst_pld_adapter_rx_pld_rst_n.reset
			i_hio_rst_pld_adapter_tx_pld_rst_n          => i_hio_rst_pld_adapter_tx_pld_rst_n,          --     i_hio_rst_pld_adapter_tx_pld_rst_n.reset
			i_hio_rst_ux_rx_pma_rst_n                   => i_hio_rst_ux_rx_pma_rst_n,                   --              i_hio_rst_ux_rx_pma_rst_n.reset
			i_hio_rst_ux_rx_sfrz                        => i_hio_rst_ux_rx_sfrz,                        --                   i_hio_rst_ux_rx_sfrz.reset
			i_hio_rst_ux_tx_pma_rst_n                   => i_hio_rst_ux_tx_pma_rst_n,                   --              i_hio_rst_ux_tx_pma_rst_n.reset
			i_hio_pld_reset_clk_row                     => i_hio_pld_reset_clk_row,                     --                i_hio_pld_reset_clk_row.reset
			i_hio_uxquad_async                          => i_hio_uxquad_async,                          --                     i_hio_uxquad_async.data
			i_hio_uxquad_async_pcie_mux                 => i_hio_uxquad_async_pcie_mux,                 --            i_hio_uxquad_async_pcie_mux.data
			i_hio_lavmm_addr                            => i_hio_lavmm_addr,                            --                               reconfig.address
			i_hio_lavmm_be                              => i_hio_lavmm_be,                              --                                       .byteenable
			i_hio_lavmm_read                            => i_hio_lavmm_read,                            --                                       .read
			i_hio_lavmm_wdata                           => i_hio_lavmm_wdata,                           --                                       .writedata
			i_hio_lavmm_write                           => i_hio_lavmm_write,                           --                                       .write
			o_hio_lavmm_rdata                           => o_hio_lavmm_rdata,                           --                                       .readdata
			o_hio_lavmm_rdata_valid                     => o_hio_lavmm_rdata_valid,                     --                                       .readdatavalid
			o_hio_lavmm_waitreq                         => o_hio_lavmm_waitreq,                         --                                       .waitrequest
			i_hio_lavmm_clk                             => i_hio_lavmm_clk,                             --                           reconfig_clk.clk
			i_hio_lavmm_rstn                            => i_hio_lavmm_rstn,                            --                           reconfig_rst.reset
			o_ss_lavmm_pcie_addr                        => o_ss_lavmm_pcie_addr,                        --                          reconfig_phip.address
			o_ss_lavmm_pcie_be                          => o_ss_lavmm_pcie_be,                          --                                       .byteenable
			o_ss_lavmm_pcie_read                        => o_ss_lavmm_pcie_read,                        --                                       .read
			o_ss_lavmm_pcie_wdata                       => o_ss_lavmm_pcie_wdata,                       --                                       .writedata
			o_ss_lavmm_pcie_write                       => o_ss_lavmm_pcie_write,                       --                                       .write
			i_ss_lavmm_pcie_rdata                       => i_ss_lavmm_pcie_rdata,                       --                                       .readdata
			i_ss_lavmm_pcie_rdata_valid                 => i_ss_lavmm_pcie_rdata_valid,                 --                                       .readdatavalid
			i_ss_lavmm_pcie_waitreq                     => i_ss_lavmm_pcie_waitreq,                     --                                       .waitrequest
			o_ss_lavmm_pcie_clk                         => o_ss_lavmm_pcie_clk,                         --                      reconfig_clk_phip.clk
			o_ss_lavmm_pcie_rstn                        => o_ss_lavmm_pcie_rstn,                        --                      reconfig_rst_phip.reset
			sm_pld_tx_demux_0_o_pcie                    => sm_pld_tx_demux_0_o_pcie,                    --               sm_pld_tx_demux_0_o_pcie.data
			sm_pld_rx_mux_0_i_pcie                      => sm_pld_rx_mux_0_i_pcie,                      --                 sm_pld_rx_mux_0_i_pcie.data
			o_pld_pcie_clk_4                            => o_pld_pcie_clk_4,                            --                       o_pld_pcie_clk_4.clk
			o_pcie_rxword_clk                           => o_pcie_rxword_clk,                           --                      o_pcie_rxword_clk.clk
			o_pcie_txword_clk                           => o_pcie_txword_clk,                           --                      o_pcie_txword_clk.clk
			ss_rst_ux_rxcdrlock2data                    => ss_rst_ux_rxcdrlock2data,                    --               ss_rst_ux_rxcdrlock2data.data
			o_rxeq_best_eye_vala                        => o_rxeq_best_eye_vala,                        --                   o_rxeq_best_eye_vala.data
			o_rxeq_donea                                => o_rxeq_donea,                                --                           o_rxeq_donea.data
			o_rxmargin_nacka                            => o_rxmargin_nacka,                            --                       o_rxmargin_nacka.data
			o_rxmargin_statusa                          => o_rxmargin_statusa,                          --                     o_rxmargin_statusa.data
			o_rxsignaldetect_lfpsa                      => o_rxsignaldetect_lfpsa,                      --                 o_rxsignaldetect_lfpsa.data
			o_rxsignaldetecta                           => o_rxsignaldetecta,                           --                      o_rxsignaldetecta.data
			o_rxmargin_status_gray                      => o_rxmargin_status_gray,                      --                 o_rxmargin_status_gray.data
			rxstatusa                                   => rxstatusa,                                   --                              rxstatusa.data
			o_pcie_pcs                                  => o_pcie_pcs,                                  --                             o_pcie_pcs.data
			i_pcie_pcs                                  => i_pcie_pcs,                                  --                             i_pcie_pcs.data
			o_synthlcfast_postdiv                       => o_synthlcfast_postdiv,                       --                  o_synthlcfast_postdiv.data
			o_synthlcmed_postdiv                        => o_synthlcmed_postdiv,                        --                   o_synthlcmed_postdiv.data
			o_synthlcslow_postdiv                       => o_synthlcslow_postdiv,                       --                  o_synthlcslow_postdiv.data
			o_txdetectrx_acka                           => o_txdetectrx_acka,                           --                      o_txdetectrx_acka.data
			o_txdetectrx_statct                         => o_txdetectrx_statct,                         --                    o_txdetectrx_statct.data
			txstatusa                                   => txstatusa,                                   --                              txstatusa.data
			i_pcs_pipe_rstn                             => i_pcs_pipe_rstn,                             --                        i_pcs_pipe_rstn.data
			i_ux_ock_pma_clk                            => i_ux_ock_pma_clk,                            --                       i_ux_ock_pma_clk.data
			i_lfps_ennt                                 => i_lfps_ennt,                                 --                            i_lfps_ennt.data
			i_pcie_l1ctrla                              => i_pcie_l1ctrla,                              --                         i_pcie_l1ctrla.data
			i_pma_cmn_ctrl                              => i_pma_cmn_ctrl,                              --                         i_pma_cmn_ctrl.data
			i_pma_ctrl                                  => i_pma_ctrl,                                  --                             i_pma_ctrl.data
			i_pcie_pcs_rx_rst                           => i_pcie_pcs_rx_rst,                           --                      i_pcie_pcs_rx_rst.data
			i_pcie_pcs_tx_rst                           => i_pcie_pcs_tx_rst,                           --                      i_pcie_pcs_tx_rst.data
			i_rxeiosdetectstata                         => i_rxeiosdetectstata,                         --                    i_rxeiosdetectstata.data
			i_rxeq_precal_code_selnt                    => i_rxeq_precal_code_selnt,                    --               i_rxeq_precal_code_selnt.data
			i_rxeq_starta                               => i_rxeq_starta,                               --                          i_rxeq_starta.data
			i_rxeq_static_ena                           => i_rxeq_static_ena,                           --                      i_rxeq_static_ena.data
			i_rxmargin_direction_nt                     => i_rxmargin_direction_nt,                     --                i_rxmargin_direction_nt.data
			i_rxmargin_mode_nt                          => i_rxmargin_mode_nt,                          --                     i_rxmargin_mode_nt.data
			i_rxmargin_offset_change_a                  => i_rxmargin_offset_change_a,                  --             i_rxmargin_offset_change_a.data
			i_rxmargin_offset_nt                        => i_rxmargin_offset_nt,                        --                   i_rxmargin_offset_nt.data
			i_rxmargin_start_a                          => i_rxmargin_start_a,                          --                     i_rxmargin_start_a.data
			i_rxpstate                                  => i_rxpstate,                                  --                             i_rxpstate.data
			i_rxrate                                    => i_rxrate,                                    --                               i_rxrate.data
			i_rxterm_hiz_ena                            => i_rxterm_hiz_ena,                            --                       i_rxterm_hiz_ena.data
			i_rxwidth                                   => i_rxwidth,                                   --                              i_rxwidth.data
			i_tstbus_lane                               => i_tstbus_lane,                               --                          i_tstbus_lane.data
			i_txbeacona                                 => i_txbeacona,                                 --                            i_txbeacona.data
			i_txclkdivrate                              => i_txclkdivrate,                              --                         i_txclkdivrate.data
			i_txdetectrx_reqa                           => i_txdetectrx_reqa,                           --                      i_txdetectrx_reqa.data
			i_txdrv_levn                                => i_txdrv_levn,                                --                           i_txdrv_levn.data
			i_txdrv_levnm1                              => i_txdrv_levnm1,                              --                         i_txdrv_levnm1.data
			i_txdrv_levnm2                              => i_txdrv_levnm2,                              --                         i_txdrv_levnm2.data
			i_txdrv_levnp1                              => i_txdrv_levnp1,                              --                         i_txdrv_levnp1.data
			i_txdrv_slew                                => i_txdrv_slew,                                --                           i_txdrv_slew.data
			i_txelecidle                                => i_txelecidle,                                --                           i_txelecidle.data
			i_txpstate                                  => i_txpstate,                                  --                             i_txpstate.data
			i_txrate                                    => i_txrate,                                    --                               i_txrate.data
			i_txwidth                                   => i_txwidth,                                   --                              i_txwidth.data
			i_hio_pld_rx_clk_in_row_clk                 => i_hio_pld_rx_clk_in_row_clk,                 --            i_hio_pld_rx_clk_in_row_clk.clk
			i_hio_pld_tx_clk_in_row_clk                 => i_hio_pld_tx_clk_in_row_clk,                 --            i_hio_pld_tx_clk_in_row_clk.clk
			i_hio_det_lat_rx_dl_clk                     => i_hio_det_lat_rx_dl_clk,                     --                i_hio_det_lat_rx_dl_clk.clk
			i_hio_det_lat_rx_mux_select                 => i_hio_det_lat_rx_mux_select,                 --            i_hio_det_lat_rx_mux_select.clk
			i_hio_det_lat_rx_sclk_flop                  => i_hio_det_lat_rx_sclk_flop,                  --             i_hio_det_lat_rx_sclk_flop.clk
			i_hio_det_lat_rx_sclk_gen_clk               => i_hio_det_lat_rx_sclk_gen_clk,               --          i_hio_det_lat_rx_sclk_gen_clk.clk
			i_hio_det_lat_rx_trig_flop                  => i_hio_det_lat_rx_trig_flop,                  --             i_hio_det_lat_rx_trig_flop.clk
			i_hio_det_lat_sampling_clk                  => i_hio_det_lat_sampling_clk,                  --             i_hio_det_lat_sampling_clk.clk
			i_hio_det_lat_tx_dl_clk                     => i_hio_det_lat_tx_dl_clk,                     --                i_hio_det_lat_tx_dl_clk.clk
			i_hio_det_lat_tx_mux_select                 => i_hio_det_lat_tx_mux_select,                 --            i_hio_det_lat_tx_mux_select.clk
			i_hio_det_lat_tx_sclk_flop                  => i_hio_det_lat_tx_sclk_flop,                  --             i_hio_det_lat_tx_sclk_flop.clk
			i_hio_det_lat_tx_sclk_gen_clk               => i_hio_det_lat_tx_sclk_gen_clk,               --          i_hio_det_lat_tx_sclk_gen_clk.clk
			i_hio_det_lat_tx_trig_flop                  => i_hio_det_lat_tx_trig_flop,                  --             i_hio_det_lat_tx_trig_flop.clk
			rx_serial_n                                 => rx_serial_n,                                 --                            rx_serial_n.data
			rx_serial_p                                 => rx_serial_p,                                 --                            rx_serial_p.data
			o_hio_txdata_fifo_wr_empty                  => o_hio_txdata_fifo_wr_empty,                  --             o_hio_txdata_fifo_wr_empty.data
			o_hio_txdata_fifo_wr_pempty                 => o_hio_txdata_fifo_wr_pempty,                 --            o_hio_txdata_fifo_wr_pempty.data
			o_hio_txdata_fifo_wr_full                   => o_hio_txdata_fifo_wr_full,                   --              o_hio_txdata_fifo_wr_full.data
			o_hio_txdata_fifo_wr_pfull                  => o_hio_txdata_fifo_wr_pfull,                  --             o_hio_txdata_fifo_wr_pfull.data
			o_hio_rxdata                                => o_hio_rxdata,                                --                           o_hio_rxdata.data
			o_hio_rxdata_extra                          => o_hio_rxdata_extra,                          --                     o_hio_rxdata_extra.data
			o_hio_rxdata_fifo_rd_empty                  => o_hio_rxdata_fifo_rd_empty,                  --             o_hio_rxdata_fifo_rd_empty.data
			o_hio_rxdata_fifo_rd_pempty                 => o_hio_rxdata_fifo_rd_pempty,                 --            o_hio_rxdata_fifo_rd_pempty.data
			o_hio_rxdata_fifo_rd_full                   => o_hio_rxdata_fifo_rd_full,                   --              o_hio_rxdata_fifo_rd_full.data
			o_hio_rxdata_fifo_rd_pfull                  => o_hio_rxdata_fifo_rd_pfull,                  --             o_hio_rxdata_fifo_rd_pfull.data
			o_hio_rstepcs_rx_pcs_fully_aligned          => o_hio_rstepcs_rx_pcs_fully_aligned,          --     o_hio_rstepcs_rx_pcs_fully_aligned.reset
			o_hio_rstfec_fec_rx_rdy_n                   => o_hio_rstfec_fec_rx_rdy_n,                   --              o_hio_rstfec_fec_rx_rdy_n.reset
			o_hio_rst_flux0_cpi_cmn_busy                => o_hio_rst_flux0_cpi_cmn_busy,                --           o_hio_rst_flux0_cpi_cmn_busy.reset
			o_hio_rst_oflux_rx_srds_rdy                 => o_hio_rst_oflux_rx_srds_rdy,                 --            o_hio_rst_oflux_rx_srds_rdy.reset
			o_hio_rst_ux_all_synthlockstatus            => o_hio_rst_ux_all_synthlockstatus,            --       o_hio_rst_ux_all_synthlockstatus.reset
			o_hio_rst_ux_octl_pcs_rxstatus              => o_hio_rst_ux_octl_pcs_rxstatus,              --         o_hio_rst_ux_octl_pcs_rxstatus.reset
			o_hio_rst_ux_octl_pcs_txstatus              => o_hio_rst_ux_octl_pcs_txstatus,              --         o_hio_rst_ux_octl_pcs_txstatus.reset
			o_hio_rst_ux_rxcdrlock2data                 => o_hio_rst_ux_rxcdrlock2data,                 --            o_hio_rst_ux_rxcdrlock2data.reset
			o_hio_rst_ux_rxcdrlockstatus                => o_hio_rst_ux_rxcdrlockstatus,                --           o_hio_rst_ux_rxcdrlockstatus.reset
			o_hio_uxquad_async                          => o_hio_uxquad_async,                          --                     o_hio_uxquad_async.data
			o_hio_user_rx_clk1_clk                      => o_hio_user_rx_clk1_clk,                      --                 o_hio_user_rx_clk1_clk.clk
			o_hio_user_rx_clk2_clk                      => o_hio_user_rx_clk2_clk,                      --                 o_hio_user_rx_clk2_clk.clk
			o_hio_user_tx_clk1_clk                      => o_hio_user_tx_clk1_clk,                      --                 o_hio_user_tx_clk1_clk.clk
			o_hio_user_tx_clk2_clk                      => o_hio_user_tx_clk2_clk,                      --                 o_hio_user_tx_clk2_clk.clk
			o_hio_ux_chnl_refclk_mux                    => o_hio_ux_chnl_refclk_mux,                    --               o_hio_ux_chnl_refclk_mux.clk
			o_hio_det_lat_rx_async_dl_sync              => o_hio_det_lat_rx_async_dl_sync,              --         o_hio_det_lat_rx_async_dl_sync.clk
			o_hio_det_lat_rx_async_pulse                => o_hio_det_lat_rx_async_pulse,                --           o_hio_det_lat_rx_async_pulse.clk
			o_hio_det_lat_rx_async_sample_sync          => o_hio_det_lat_rx_async_sample_sync,          --     o_hio_det_lat_rx_async_sample_sync.clk
			o_hio_det_lat_rx_sclk_sample_sync           => o_hio_det_lat_rx_sclk_sample_sync,           --      o_hio_det_lat_rx_sclk_sample_sync.clk
			o_hio_det_lat_rx_trig_sample_sync           => o_hio_det_lat_rx_trig_sample_sync,           --      o_hio_det_lat_rx_trig_sample_sync.clk
			o_hio_det_lat_tx_async_dl_sync              => o_hio_det_lat_tx_async_dl_sync,              --         o_hio_det_lat_tx_async_dl_sync.clk
			o_hio_det_lat_tx_async_pulse                => o_hio_det_lat_tx_async_pulse,                --           o_hio_det_lat_tx_async_pulse.clk
			o_hio_det_lat_tx_async_sample_sync          => o_hio_det_lat_tx_async_sample_sync,          --     o_hio_det_lat_tx_async_sample_sync.clk
			o_hio_det_lat_tx_sclk_sample_sync           => o_hio_det_lat_tx_sclk_sample_sync,           --      o_hio_det_lat_tx_sclk_sample_sync.clk
			o_hio_det_lat_tx_trig_sample_sync           => o_hio_det_lat_tx_trig_sample_sync,           --      o_hio_det_lat_tx_trig_sample_sync.clk
			o_hio_xcvrif_rx_latency_pulse               => o_hio_xcvrif_rx_latency_pulse,               --          o_hio_xcvrif_rx_latency_pulse.clk
			o_hio_xcvrif_tx_latency_pulse               => o_hio_xcvrif_tx_latency_pulse,               --          o_hio_xcvrif_tx_latency_pulse.clk
			tx_serial_p                                 => tx_serial_p,                                 --                            tx_serial_p.data
			tx_serial_n                                 => tx_serial_n,                                 --                            tx_serial_n.data
			i_hio_txdata_async                          => i_hio_txdata_async,                          --                     i_hio_txdata_async.data
			i_hio_txdata_direct                         => i_hio_txdata_direct,                         --                    i_hio_txdata_direct.data
			o_hio_rxdata_async                          => o_hio_rxdata_async,                          --                     o_hio_rxdata_async.data
			o_hio_rxdata_direct                         => o_hio_rxdata_direct,                         --                    o_hio_rxdata_direct.data
			i_uxwrap_bus_in_phy_shared                  => i_uxwrap_bus_in_phy_shared,                  --                          uxwrap_bus_in.data
			o_uxwrap_bus_out_phy_shared                 => o_uxwrap_bus_out_phy_shared,                 --                         uxwrap_bus_out.data
			o_lavmm_addr_phy_shared                     => o_lavmm_addr_phy_shared,                     --                    reconfig_phy_shared.address
			o_lavmm_be_phy_shared                       => o_lavmm_be_phy_shared,                       --                                       .byteenable
			o_lavmm_read_phy_shared                     => o_lavmm_read_phy_shared,                     --                                       .read
			o_lavmm_wdata_phy_shared                    => o_lavmm_wdata_phy_shared,                    --                                       .writedata
			o_lavmm_write_phy_shared                    => o_lavmm_write_phy_shared,                    --                                       .write
			i_lavmm_rdata_phy_shared                    => i_lavmm_rdata_phy_shared,                    --                                       .readdata
			i_lavmm_rdata_valid_phy_shared              => i_lavmm_rdata_valid_phy_shared,              --                                       .readdatavalid
			i_lavmm_waitreq_phy_shared                  => i_lavmm_waitreq_phy_shared,                  --                                       .waitrequest
			o_lavmm_clk_phy_shared                      => o_lavmm_clk_phy_shared,                      --                reconfig_clk_phy_shared.clk
			o_lavmm_rstn_phy_shared                     => o_lavmm_rstn_phy_shared,                     --                reconfig_rst_phy_shared.reset
			o_sclk_return_sel_rx_phy_shared             => o_sclk_return_sel_rx_phy_shared,             --                   o_sclk_return_sel_rx.data
			o_sclk_return_sel_tx_phy_shared             => o_sclk_return_sel_tx_phy_shared,             --                   o_sclk_return_sel_tx.data
			o_ick_sclk_rx_phy_shared                    => o_ick_sclk_rx_phy_shared,                    --                          o_ick_sclk_rx.clk
			i_sync_common_control_phy_shared            => i_sync_common_control_phy_shared,            --                  i_sync_common_control.data
			o_ft_rx_sclk_sync_ch_phy_shared             => o_ft_rx_sclk_sync_ch_phy_shared,             --                   o_ft_rx_sclk_sync_ch.data
			o_ft_tx_sclk_sync_ch_phy_shared             => o_ft_tx_sclk_sync_ch_phy_shared,             --                   o_ft_tx_sclk_sync_ch.data
			o_rst_ux_rx_pma_rst_n_phy_shared            => o_rst_ux_rx_pma_rst_n_phy_shared,            --                  o_rst_ux_rx_pma_rst_n.reset
			o_rst_ux_tx_pma_rst_n_phy_shared            => o_rst_ux_tx_pma_rst_n_phy_shared,            --                  o_rst_ux_tx_pma_rst_n.reset
			o_ick_pcs_txword_phy_shared                 => o_ick_pcs_txword_phy_shared,                 --                       o_ick_pcs_txword.data
			o_tx_dl_ch_bit_phy_shared                   => o_tx_dl_ch_bit_phy_shared,                   --                         o_tx_dl_ch_bit.data
			i_dat_pcs_measlatbit_phy_shared             => i_dat_pcs_measlatbit_phy_shared,             --                   i_dat_pcs_measlatbit.data
			i_ft_rx_async_pulse_ch_phy_shared           => i_ft_rx_async_pulse_ch_phy_shared,           --                 i_ft_rx_async_pulse_ch.data
			i_ft_tx_async_pulse_ch_phy_shared           => i_ft_tx_async_pulse_ch_phy_shared,           --                 i_ft_tx_async_pulse_ch.data
			i_rx_dl_ch_bit_phy_shared                   => i_rx_dl_ch_bit_phy_shared,                   --                         i_rx_dl_ch_bit.data
			i_ux_rxuser1_sel_phy_shared                 => i_ux_rxuser1_sel_phy_shared,                 --                       i_ux_rxuser1_sel.data
			i_ux_rxuser2_sel_phy_shared                 => i_ux_rxuser2_sel_phy_shared,                 --                       i_ux_rxuser2_sel.data
			i_ux_txuser1_sel_phy_shared                 => i_ux_txuser1_sel_phy_shared,                 --                       i_ux_txuser1_sel.data
			i_ux_txuser2_sel_phy_shared                 => i_ux_txuser2_sel_phy_shared,                 --                       i_ux_txuser2_sel.data
			o_octl_pcs_txstatus_a_phy_shared            => o_octl_pcs_txstatus_a_phy_shared,            --                  o_octl_pcs_txstatus_a.data
			i_ictl_pcs_txenable_a_phy_shared            => i_ictl_pcs_txenable_a_phy_shared,            --                  i_ictl_pcs_txenable_a.data
			i_sync_cfg_data_phy_shared                  => i_sync_cfg_data_phy_shared,                  --                        i_sync_cfg_data.data
			i_sync_interface_control_phy_shared         => i_sync_interface_control_phy_shared,         --               i_sync_interface_control.data
			o_tx_data_phy_shared                        => o_tx_data_phy_shared,                        --                              o_tx_data.data
			i_rx_data_phy_shared                        => i_rx_data_phy_shared,                        --                              i_rx_data.data
			o_sm_flux_ingress_phy_shared                => o_sm_flux_ingress_phy_shared,                --                      o_sm_flux_ingress.data
			i_sm_flux_egress_phy_shared                 => i_sm_flux_egress_phy_shared,                 --                       i_sm_flux_egress.data
			i_flux_cpi_int_phy_shared                   => i_flux_cpi_int_phy_shared,                   --                         i_flux_cpi_int.data
			i_flux_int_phy_shared                       => i_flux_int_phy_shared,                       --                             i_flux_int.data
			i_oflux_octl_pcs_txptr_smpl_lane_phy_shared => i_oflux_octl_pcs_txptr_smpl_lane_phy_shared, --       i_oflux_octl_pcs_txptr_smpl_lane.data
			o_ick_sclk_tx_phy_shared                    => o_ick_sclk_tx_phy_shared,                    --                          o_ick_sclk_tx.clk
			i_flux_srds_rdy_phy_shared                  => i_flux_srds_rdy_phy_shared,                  --                        i_flux_srds_rdy.data
			i_pcs_rxword_phy_shared                     => i_pcs_rxword_phy_shared,                     --                           i_pcs_rxword.data
			i_pcs_rxpostdiv_phy_shared                  => i_pcs_rxpostdiv_phy_shared,                  --                        i_pcs_rxpostdiv.data
			i_ock_pcs_txword_phy_shared                 => i_ock_pcs_txword_phy_shared,                 --                       i_ock_pcs_txword.data
			o_dat_pcs_measlatrndtripbit_phy_shared      => o_dat_pcs_measlatrndtripbit_phy_shared,      -- o_dat_pcs_measlatrndtripbit_phy_shared.data
			i_ch_eth_fec_rx_async_fec_wrap              => i_ch_eth_fec_rx_async_fec_wrap,              --                            asyncdata_4.data
			i_ch_eth_fec_rx_direct_fec_wrap             => i_ch_eth_fec_rx_direct_fec_wrap,             --                            asyncdata_5.data
			i_fec_rx_rdy_n_fec_wrap                     => i_fec_rx_rdy_n_fec_wrap,                     --                i_fec_rx_rdy_n_fec_wrap.data
			i_fec_tx_data_mux_sel_fec_wrap              => i_fec_tx_data_mux_sel_fec_wrap,              --         i_fec_tx_data_mux_sel_fec_wrap.muxsel
			i_fec_rx_data_fec_wrap                      => i_fec_rx_data_fec_wrap,                      --                 i_fec_rx_data_fec_wrap.data
			i_xcvr_tx_data                              => i_xcvr_tx_data,                              --                         i_xcvr_tx_data.data
			ss_rst_flux0_cpi_cmn_busy                   => ss_rst_flux0_cpi_cmn_busy,                   --              ss_rst_flux0_cpi_cmn_busy.data
			o_pma_rx_sf                                 => o_pma_rx_sf,                                 --                            o_pma_rx_sf.data
			i_refclk_tx_p                               => i_refclk_tx_p,                               --                          i_refclk_tx_p.clk
			i_syspll_c0_clk                             => i_syspll_c0_clk,                             --                        i_syspll_c0_clk.clk
			i_syspll_c1_clk                             => i_syspll_c1_clk,                             --                        i_syspll_c1_clk.clk
			i_syspll_c2_clk                             => i_syspll_c2_clk,                             --                        i_syspll_c2_clk.clk
			i_flux_clk                                  => i_flux_clk,                                  --                             i_flux_clk.clk
			i_refclk_rx_p                               => i_refclk_rx_p,                               --                          i_refclk_rx_p.clk
			i_ux_chnl_refclk_mux_phy_shared             => i_ux_chnl_refclk_mux_phy_shared,             --        i_ux_chnl_refclk_mux_phy_shared.clk
			o_xcvrif_tx_fifo_rd_en_mux_x1               => o_xcvrif_tx_fifo_rd_en_mux_x1,               --          o_xcvrif_tx_fifo_rd_en_mux_x1.clk
			i_xcvrif_tx_fifo_rd_en_mux_x2               => i_xcvrif_tx_fifo_rd_en_mux_x2,               --          i_xcvrif_tx_fifo_rd_en_mux_x2.clk
			i_xcvrif_tx_fifo_rd_en_mux_x4               => i_xcvrif_tx_fifo_rd_en_mux_x4,               --          i_xcvrif_tx_fifo_rd_en_mux_x4.clk
			i_xcvrif_tx_fifo_rd_en_mux_x6_bot           => i_xcvrif_tx_fifo_rd_en_mux_x6_bot,           --      i_xcvrif_tx_fifo_rd_en_mux_x6_bot.clk
			i_xcvrif_tx_fifo_rd_en_mux_x6_top           => i_xcvrif_tx_fifo_rd_en_mux_x6_top,           --      i_xcvrif_tx_fifo_rd_en_mux_x6_top.clk
			i_xcvrif_tx_fifo_rd_en_mux_x8_bot           => i_xcvrif_tx_fifo_rd_en_mux_x8_bot,           --      i_xcvrif_tx_fifo_rd_en_mux_x8_bot.clk
			i_xcvrif_tx_fifo_rd_en_mux_x8_top           => i_xcvrif_tx_fifo_rd_en_mux_x8_top,           --      i_xcvrif_tx_fifo_rd_en_mux_x8_top.clk
			o_xcvrif_tx_rst_mux_x1                      => o_xcvrif_tx_rst_mux_x1,                      --                 o_xcvrif_tx_rst_mux_x1.clk
			i_xcvrif_tx_rst_mux_x2                      => i_xcvrif_tx_rst_mux_x2,                      --                 i_xcvrif_tx_rst_mux_x2.clk
			i_xcvrif_tx_rst_mux_x4                      => i_xcvrif_tx_rst_mux_x4,                      --                 i_xcvrif_tx_rst_mux_x4.clk
			i_xcvrif_tx_rst_mux_x6_bot                  => i_xcvrif_tx_rst_mux_x6_bot,                  --             i_xcvrif_tx_rst_mux_x6_bot.clk
			i_xcvrif_tx_rst_mux_x6_top                  => i_xcvrif_tx_rst_mux_x6_top,                  --             i_xcvrif_tx_rst_mux_x6_top.clk
			i_xcvrif_tx_rst_mux_x8_bot                  => i_xcvrif_tx_rst_mux_x8_bot,                  --             i_xcvrif_tx_rst_mux_x8_bot.clk
			i_xcvrif_tx_rst_mux_x8_top                  => i_xcvrif_tx_rst_mux_x8_top,                  --             i_xcvrif_tx_rst_mux_x8_top.clk
			o_xcvrif_tx_word_clk_mux_x1                 => o_xcvrif_tx_word_clk_mux_x1,                 --            o_xcvrif_tx_word_clk_mux_x1.clk
			i_xcvrif_tx_word_clk_mux_x2                 => i_xcvrif_tx_word_clk_mux_x2,                 --            i_xcvrif_tx_word_clk_mux_x2.clk
			i_xcvrif_tx_word_clk_mux_x4                 => i_xcvrif_tx_word_clk_mux_x4,                 --            i_xcvrif_tx_word_clk_mux_x4.clk
			i_xcvrif_tx_word_clk_mux_x6_bot             => i_xcvrif_tx_word_clk_mux_x6_bot,             --        i_xcvrif_tx_word_clk_mux_x6_bot.clk
			i_xcvrif_tx_word_clk_mux_x6_top             => i_xcvrif_tx_word_clk_mux_x6_top,             --        i_xcvrif_tx_word_clk_mux_x6_top.clk
			i_xcvrif_tx_word_clk_mux_x8_bot             => i_xcvrif_tx_word_clk_mux_x8_bot,             --        i_xcvrif_tx_word_clk_mux_x8_bot.clk
			i_xcvrif_tx_word_clk_mux_x8_top             => i_xcvrif_tx_word_clk_mux_x8_top,             --        i_xcvrif_tx_word_clk_mux_x8_top.clk
			ioack_cdrdiv_left_ux_bidir_in               => ioack_cdrdiv_left_ux_bidir_in,               --          ioack_cdrdiv_left_ux_bidir_in.clk
			ioack_synthdiv1_left_ux_bidir_in            => ioack_synthdiv1_left_ux_bidir_in,            --       ioack_synthdiv1_left_ux_bidir_in.clk
			ioack_synthdiv2_left_ux_bidir_in            => ioack_synthdiv2_left_ux_bidir_in,            --       ioack_synthdiv2_left_ux_bidir_in.clk
			ioack_cdrdiv_left_ux_bidir_out              => ioack_cdrdiv_left_ux_bidir_out,              --         ioack_cdrdiv_left_ux_bidir_out.clk
			ioack_synthdiv1_left_ux_bidir_out           => ioack_synthdiv1_left_ux_bidir_out,           --      ioack_synthdiv1_left_ux_bidir_out.clk
			ioack_synthdiv2_left_ux_bidir_out           => ioack_synthdiv2_left_ux_bidir_out,           --      ioack_synthdiv2_left_ux_bidir_out.clk
			o_xcvrif_tx_rst_wr_sync_mux_x1              => o_xcvrif_tx_rst_wr_sync_mux_x1,              --         o_xcvrif_tx_rst_wr_sync_mux_x1.clk
			i_xcvrif_tx_rst_wr_sync_mux_x2              => i_xcvrif_tx_rst_wr_sync_mux_x2,              --         i_xcvrif_tx_rst_wr_sync_mux_x2.clk
			i_xcvrif_tx_rst_wr_sync_mux_x4              => i_xcvrif_tx_rst_wr_sync_mux_x4,              --         i_xcvrif_tx_rst_wr_sync_mux_x4.clk
			i_xcvrif_tx_rst_wr_sync_mux_x6_bot          => i_xcvrif_tx_rst_wr_sync_mux_x6_bot,          --     i_xcvrif_tx_rst_wr_sync_mux_x6_bot.clk
			i_xcvrif_tx_rst_wr_sync_mux_x6_top          => i_xcvrif_tx_rst_wr_sync_mux_x6_top,          --     i_xcvrif_tx_rst_wr_sync_mux_x6_top.clk
			i_xcvrif_tx_rst_wr_sync_mux_x8_bot          => i_xcvrif_tx_rst_wr_sync_mux_x8_bot,          --     i_xcvrif_tx_rst_wr_sync_mux_x8_bot.clk
			i_xcvrif_tx_rst_wr_sync_mux_x8_top          => i_xcvrif_tx_rst_wr_sync_mux_x8_top,          --     i_xcvrif_tx_rst_wr_sync_mux_x8_top.clk
			ss_user_rx_clk1_clk                         => ss_user_rx_clk1_clk,                         --                    ss_user_rx_clk1_clk.clk
			ss_user_rx_clk2_clk                         => ss_user_rx_clk2_clk,                         --                    ss_user_rx_clk2_clk.clk
			ss_user_tx_clk1_clk                         => ss_user_tx_clk1_clk,                         --                    ss_user_tx_clk1_clk.clk
			ss_user_tx_clk2_clk                         => ss_user_tx_clk2_clk,                         --                    ss_user_tx_clk2_clk.clk
			ss_user_rx_clk1_clk_w                       => ss_user_rx_clk1_clk_w,                       --                  ss_user_rx_clk1_clk_w.clk
			ss_user_rx_clk2_clk_w                       => ss_user_rx_clk2_clk_w,                       --                  ss_user_rx_clk2_clk_w.clk
			ss_user_tx_clk1_clk_w                       => ss_user_tx_clk1_clk_w,                       --                  ss_user_tx_clk1_clk_w.clk
			ss_user_tx_clk2_clk_w                       => ss_user_tx_clk2_clk_w,                       --                  ss_user_tx_clk2_clk_w.clk
			o_hio_ux_tx_ch_ptr_smpl                     => o_hio_ux_tx_ch_ptr_smpl                      --                o_hio_ux_tx_ch_ptr_smpl.data
		);

end architecture rtl; -- of gts_axi_streaming_pcie_hal_top_one_lane_pcie_hal_2100_ltignja
