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module qhip_gts_axi_streaming_intel_pcie_gts_800_qgc2y5a  #(

  //SM QHIP sm_pcie_sip_top parameter
  //`include "intel_pcie_sm_qhip_ast_qhip_parameter.iv"

  //HAL TOP phip parameters
  //`include "intel_pcie_hal_top_parameter.iv"
   parameter  device_family                                                      =   "AGILEX",  
   parameter  core16_topology                                                    =   "pcie_x4",

   parameter  core16_tdata_width_integer_hwtcl                            =    256, //new: 256, 128
   //parameter  core16_empty_width_integer_hwtcl                            =    3, //new: tdata_width=256, empty_width=3 .if tdata_width=128, empty_width=2

   parameter  ctop_core16_virtual_rp_ep_mode                               =   "CTOP_CORE4_EP",
   parameter  core16_virtual_tlp_bypass_en_hwtcl                           =     0,
   parameter  core16_total_pf_count_width_hwtcl                            =     1,
   parameter  core16_total_vf_count_width_hwtcl                            =     0,
   parameter  core16_total_pf_count_hwtcl                                  =     1,
   parameter  core16_total_vf_count_hwtcl                                  =     1,

   // PCS Reconfig
   parameter  PCS_CONFIG_EN                                               =     0,
   parameter  core16_hip_reconfig_hwtcl                                    =     0,

   // rx_buffer_limit
   parameter  core16_enable_rx_buffer_limit_ports_hwtcl                  =     1,

   // PTM
   parameter  core16_virtual_ptm_hwtcl                                     =     0,

   // ARI_ACS_FUN_GRP_CAP
   parameter  ctop_core16_pf0_ari_acs_fun_grp_cap                          =     "FALSE", 

   // Debug Toolkit
   parameter  debug_toolkit_hwtcl                                   =   0,
   parameter  enable_pciess_register_access_hwtcl                   =   0,
   parameter  link_insp_en_hwtcl                                    =   0,
   parameter  link_insp_avmm_en_hwtcl                               =   0,
   parameter  core16_perfmon_clk_freq				    =   250,
   parameter  core8_perfmon_clk_freq				    =   250,

   //Independent pin perst
   parameter  ctop_virtual_x16_perst_sel                                  =    "CTOP_CMN_HARD_X4",

   // ECC enable
   parameter core16_enable_ecc_hwtcl                                     =     0,

   //USER_MODE_TO_PLD_IN_USE
   parameter  core16_user_mode_to_pld_in_use_hwtcl                       =     0,

   // pld_warm_rst_rdy
   parameter  core16_enable_pld_warm_rst_rdy_hwtcl                       =     0,

   // max payload
   parameter  ctop_core16_virtual_maxpayload_size                        =     "CTOP_CORE16_MAX_PAYLOAD_512",
   
   // ast_parity
   parameter  core16_use_ast_parity_hwtcl                                =     0,
   
   // Power Management
   parameter  core16_enable_power_mgnt_intf_hwtcl                        =     0,

   // Error Interface
   parameter  core16_enable_error_intf_hwtcl                             =     0,
   
   // FLR
   parameter  core16_flr_cap_hwtcl                                       =     0,
   
   // cpl_timeout
   parameter  core16_enable_cpl_timeout_hwtcl                            =     0,
   
   // multi_func
   parameter  core16_enable_multi_func_hwtcl                               =     0,
   
   // SRIOV
   parameter  core16_enable_sriov_hwtcl                                    =     0,
   
   // 10-bit tag
   
  // CEB
   parameter  core16_pf_ceb_pointer_addr_hwtcl                       =     0,
   parameter  core16_vf_ceb_pointer_addr_hwtcl                       =     0,

   // Virtio
   parameter  core16_enable_virtio_hwtcl                                   =     0,
   parameter  core16_virtio_start_byte_address_hwtcl                       =     8'h48,
   parameter  core16_pf0_virtio_capability_present_hwtcl                   =     00,
   parameter  core16_pf0_virtio_device_specific_cap_present_hwtcl          =     0,
   parameter  core16_pf0_virtio_cmn_config_bar_indicator_hwtcl             =     0,
   parameter  core16_pf0_virtio_cmn_config_bar_offset_hwtcl                =     0,
   parameter  core16_pf0_virtio_cmn_config_structure_length_hwtcl          =     0,
   parameter  core16_pf0_virtio_notification_bar_indicator_hwtcl           =     0,
   parameter  core16_pf0_virtio_notification_bar_offset_hwtcl              =     0,
   parameter  core16_pf0_virtio_notification_structure_length_hwtcl        =     0,
   parameter  core16_pf0_virtio_notify_off_multiplier_hwtcl                =     0,
   parameter  core16_pf0_virtio_isrstatus_bar_indicator_hwtcl              =     0,
   parameter  core16_pf0_virtio_isrstatus_bar_offset_hwtcl                 =     0,
   parameter  core16_pf0_virtio_isrstatus_structure_length_hwtcl           =     0,
   parameter  core16_pf0_virtio_devspecific_bar_indicator_hwtcl            =     0,
   parameter  core16_pf0_virtio_devspecific_bar_offset_hwtcl               =     0,
   parameter  core16_pf0_virtio_devspecific_structure_length_hwtcl         =     0,
   parameter  core16_pf0_virtio_pciconfig_access_bar_indicator_hwtcl       =     0,
   parameter  core16_pf0_virtio_pciconfig_access_bar_offset_hwtcl          =     0,
   parameter  core16_pf0_virtio_pciconfig_access_structure_length_hwtcl    =     0,
   parameter  core16_pf1_virtio_capability_present_hwtcl                   =     0,
   parameter  core16_pf1_virtio_device_specific_cap_present_hwtcl          =     0,
   parameter  core16_pf1_virtio_cmn_config_bar_indicator_hwtcl             =     0,
   parameter  core16_pf1_virtio_cmn_config_bar_offset_hwtcl                =     0,
   parameter  core16_pf1_virtio_cmn_config_structure_length_hwtcl          =     0,
   parameter  core16_pf1_virtio_notification_bar_indicator_hwtcl           =     0,
   parameter  core16_pf1_virtio_notification_bar_offset_hwtcl              =     0,
   parameter  core16_pf1_virtio_notification_structure_length_hwtcl        =     0,
   parameter  core16_pf1_virtio_notify_off_multiplier_hwtcl                =     0,
   parameter  core16_pf1_virtio_isrstatus_bar_indicator_hwtcl              =     0,
   parameter  core16_pf1_virtio_isrstatus_bar_offset_hwtcl                 =     0,
   parameter  core16_pf1_virtio_isrstatus_structure_length_hwtcl           =     0,
   parameter  core16_pf1_virtio_devspecific_bar_indicator_hwtcl            =     0,
   parameter  core16_pf1_virtio_devspecific_bar_offset_hwtcl               =     0,
   parameter  core16_pf1_virtio_devspecific_structure_length_hwtcl         =     0,
   parameter  core16_pf1_virtio_pciconfig_access_bar_indicator_hwtcl       =     0,
   parameter  core16_pf1_virtio_pciconfig_access_bar_offset_hwtcl          =     0,
   parameter  core16_pf1_virtio_pciconfig_access_structure_length_hwtcl    =     0,
   parameter  core16_pf2_virtio_capability_present_hwtcl                   =     0,
   parameter  core16_pf2_virtio_device_specific_cap_present_hwtcl          =     0,
   parameter  core16_pf2_virtio_cmn_config_bar_indicator_hwtcl             =     0,
   parameter  core16_pf2_virtio_cmn_config_bar_offset_hwtcl                =     0,
   parameter  core16_pf2_virtio_cmn_config_structure_length_hwtcl          =     0,
   parameter  core16_pf2_virtio_notification_bar_indicator_hwtcl           =     0,
   parameter  core16_pf2_virtio_notification_bar_offset_hwtcl              =     0,
   parameter  core16_pf2_virtio_notification_structure_length_hwtcl        =     0,
   parameter  core16_pf2_virtio_notify_off_multiplier_hwtcl                =     0,
   parameter  core16_pf2_virtio_isrstatus_bar_indicator_hwtcl              =     0,
   parameter  core16_pf2_virtio_isrstatus_bar_offset_hwtcl                 =     0,
   parameter  core16_pf2_virtio_isrstatus_structure_length_hwtcl           =     0,
   parameter  core16_pf2_virtio_devspecific_bar_indicator_hwtcl            =     0,
   parameter  core16_pf2_virtio_devspecific_bar_offset_hwtcl               =     0,
   parameter  core16_pf2_virtio_devspecific_structure_length_hwtcl         =     0,
   parameter  core16_pf2_virtio_pciconfig_access_bar_indicator_hwtcl       =     0,
   parameter  core16_pf2_virtio_pciconfig_access_bar_offset_hwtcl          =     0,
   parameter  core16_pf2_virtio_pciconfig_access_structure_length_hwtcl    =     0,
   parameter  core16_pf3_virtio_capability_present_hwtcl                   =     0,
   parameter  core16_pf3_virtio_device_specific_cap_present_hwtcl          =     0,
   parameter  core16_pf3_virtio_cmn_config_bar_indicator_hwtcl             =     0,
   parameter  core16_pf3_virtio_cmn_config_bar_offset_hwtcl                =     0,
   parameter  core16_pf3_virtio_cmn_config_structure_length_hwtcl          =     0,
   parameter  core16_pf3_virtio_notification_bar_indicator_hwtcl           =     0,
   parameter  core16_pf3_virtio_notification_bar_offset_hwtcl              =     0,
   parameter  core16_pf3_virtio_notification_structure_length_hwtcl        =     0,
   parameter  core16_pf3_virtio_notify_off_multiplier_hwtcl                =     0,
   parameter  core16_pf3_virtio_isrstatus_bar_indicator_hwtcl              =     0,
   parameter  core16_pf3_virtio_isrstatus_bar_offset_hwtcl                 =     0,
   parameter  core16_pf3_virtio_isrstatus_structure_length_hwtcl           =     0,
   parameter  core16_pf3_virtio_devspecific_bar_indicator_hwtcl            =     0,
   parameter  core16_pf3_virtio_devspecific_bar_offset_hwtcl               =     0,
   parameter  core16_pf3_virtio_devspecific_structure_length_hwtcl         =     0,
   parameter  core16_pf3_virtio_pciconfig_access_bar_indicator_hwtcl       =     0,
   parameter  core16_pf3_virtio_pciconfig_access_bar_offset_hwtcl          =     0,
   parameter  core16_pf3_virtio_pciconfig_access_structure_length_hwtcl    =     0,
   parameter  core16_pf0vf_virtio_capability_present_hwtcl                 =     0,
   parameter  core16_pf0vf_virtio_device_specific_cap_present_hwtcl        =     0,
   parameter  core16_pf0vf_virtio_cmn_config_bar_indicator_hwtcl           =     0,
   parameter  core16_pf0vf_virtio_cmn_config_bar_offset_hwtcl              =     0,
   parameter  core16_pf0vf_virtio_cmn_config_structure_length_hwtcl        =     0,
   parameter  core16_pf0vf_virtio_notification_bar_indicator_hwtcl         =     0,
   parameter  core16_pf0vf_virtio_notification_bar_offset_hwtcl            =     0,
   parameter  core16_pf0vf_virtio_notification_structure_length_hwtcl      =     0,
   parameter  core16_pf0vf_virtio_notify_off_multiplier_hwtcl              =     0,
   parameter  core16_pf0vf_virtio_isrstatus_bar_indicator_hwtcl            =     0,
   parameter  core16_pf0vf_virtio_isrstatus_bar_offset_hwtcl               =     0,
   parameter  core16_pf0vf_virtio_isrstatus_structure_length_hwtcl         =     0,
   parameter  core16_pf0vf_virtio_devspecific_bar_indicator_hwtcl          =     0,
   parameter  core16_pf0vf_virtio_devspecific_bar_offset_hwtcl             =     0,
   parameter  core16_pf0vf_virtio_devspecific_structure_length_hwtcl       =     0,
   parameter  core16_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl     =     0,
   parameter  core16_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl        =     0,
   parameter  core16_pf0vf_virtio_pciconfig_access_structure_length_hwtcl  =     0,
   parameter  core16_pf1vf_virtio_capability_present_hwtcl                 =     0,
   parameter  core16_pf1vf_virtio_device_specific_cap_present_hwtcl        =     0,
   parameter  core16_pf1vf_virtio_cmn_config_bar_indicator_hwtcl           =     0,
   parameter  core16_pf1vf_virtio_cmn_config_bar_offset_hwtcl              =     0,
   parameter  core16_pf1vf_virtio_cmn_config_structure_length_hwtcl        =     0,
   parameter  core16_pf1vf_virtio_notification_bar_indicator_hwtcl         =     0,
   parameter  core16_pf1vf_virtio_notification_bar_offset_hwtcl            =     0,
   parameter  core16_pf1vf_virtio_notification_structure_length_hwtcl      =     0,
   parameter  core16_pf1vf_virtio_notify_off_multiplier_hwtcl              =     0,
   parameter  core16_pf1vf_virtio_isrstatus_bar_indicator_hwtcl            =     0,
   parameter  core16_pf1vf_virtio_isrstatus_bar_offset_hwtcl               =     0,
   parameter  core16_pf1vf_virtio_isrstatus_structure_length_hwtcl         =     0,
   parameter  core16_pf1vf_virtio_devspecific_bar_indicator_hwtcl          =     0,
   parameter  core16_pf1vf_virtio_devspecific_bar_offset_hwtcl             =     0,
   parameter  core16_pf1vf_virtio_devspecific_structure_length_hwtcl       =     0,
   parameter  core16_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl     =     0,
   parameter  core16_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl        =     0,
   parameter  core16_pf1vf_virtio_pciconfig_access_structure_length_hwtcl  =     0,
   parameter  core16_pf2vf_virtio_capability_present_hwtcl                 =     0,
   parameter  core16_pf2vf_virtio_device_specific_cap_present_hwtcl        =     0,
   parameter  core16_pf2vf_virtio_cmn_config_bar_indicator_hwtcl           =     0,
   parameter  core16_pf2vf_virtio_cmn_config_bar_offset_hwtcl              =     0,
   parameter  core16_pf2vf_virtio_cmn_config_structure_length_hwtcl        =     0,
   parameter  core16_pf2vf_virtio_notification_bar_indicator_hwtcl         =     0,
   parameter  core16_pf2vf_virtio_notification_bar_offset_hwtcl            =     0,
   parameter  core16_pf2vf_virtio_notification_structure_length_hwtcl      =     0,
   parameter  core16_pf2vf_virtio_notify_off_multiplier_hwtcl              =     0,
   parameter  core16_pf2vf_virtio_isrstatus_bar_indicator_hwtcl            =     0,
   parameter  core16_pf2vf_virtio_isrstatus_bar_offset_hwtcl               =     0,
   parameter  core16_pf2vf_virtio_isrstatus_structure_length_hwtcl         =     0,
   parameter  core16_pf2vf_virtio_devspecific_bar_indicator_hwtcl          =     0,
   parameter  core16_pf2vf_virtio_devspecific_bar_offset_hwtcl             =     0,
   parameter  core16_pf2vf_virtio_devspecific_structure_length_hwtcl       =     0,
   parameter  core16_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl     =     0,
   parameter  core16_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl        =     0,
   parameter  core16_pf2vf_virtio_pciconfig_access_structure_length_hwtcl  =     0,
   parameter  core16_pf3vf_virtio_capability_present_hwtcl                 =     0,
   parameter  core16_pf3vf_virtio_device_specific_cap_present_hwtcl        =     0,
   parameter  core16_pf3vf_virtio_cmn_config_bar_indicator_hwtcl           =     0,
   parameter  core16_pf3vf_virtio_cmn_config_bar_offset_hwtcl              =     0,
   parameter  core16_pf3vf_virtio_cmn_config_structure_length_hwtcl        =     0,
   parameter  core16_pf3vf_virtio_notification_bar_indicator_hwtcl         =     0,
   parameter  core16_pf3vf_virtio_notification_bar_offset_hwtcl            =     0,
   parameter  core16_pf3vf_virtio_notification_structure_length_hwtcl      =     0,
   parameter  core16_pf3vf_virtio_notify_off_multiplier_hwtcl              =     0,
   parameter  core16_pf3vf_virtio_isrstatus_bar_indicator_hwtcl            =     0,
   parameter  core16_pf3vf_virtio_isrstatus_bar_offset_hwtcl               =     0,
   parameter  core16_pf3vf_virtio_isrstatus_structure_length_hwtcl         =     0,
   parameter  core16_pf3vf_virtio_devspecific_bar_indicator_hwtcl          =     0,
   parameter  core16_pf3vf_virtio_devspecific_bar_offset_hwtcl             =     0,
   parameter  core16_pf3vf_virtio_devspecific_structure_length_hwtcl       =     0,
   parameter  core16_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl     =     0,
   parameter  core16_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl        =     0,
   parameter  core16_pf3vf_virtio_pciconfig_access_structure_length_hwtcl  =     0,
   parameter  core16_pf0_vf_count_hwtcl                                    =     0,
   parameter  core16_pf1_vf_count_hwtcl                                    =     0,
   parameter  core16_pf2_vf_count_hwtcl                                    =     0,
   parameter  core16_pf3_vf_count_hwtcl                                    =     0,

   parameter sm_hssi_pcie_ctl_x4_rxbuf_limit_bypass_hwtcl                           =   7,
   parameter sm_hssi_pcie_ctl_x4_maxpayload_size_hwtcl                              =   "MAXPAYLOAD_SIZE_MAX_PAYLOAD_128",
   parameter sm_hssi_pcie_ctl_x4_port_type_hwtcl                                    =   "PORT_TYPE_NATIVE_EP",
   parameter sm_hssi_pcie_ctl_x4_sris_enable_hwtcl                                  =   "SRIS_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_link_num_hwtcl                                     =   "SRIS_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_sris_mode_hwtcl                                    =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_sim_mode_hwtcl                                     =   "SIM_MODE_DISABLE_VSIM_MODE",
   parameter sm_hssi_pcie_ctl_x4_sup_mode_hwtcl                                     =   "SUP_MODE_USER_MODE",
   parameter sm_hssi_pcie_ctl_x4_cvp_enable_hwtcl                                   =   "CVP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_cii_monitor_en_hwtcl                               =   "CII_MONITOR_EN_DISABLE",
   parameter sm_hssi_pcie_ctl_x4_pclk_clk_hz_hwtcl                                  =   0,
   parameter sm_hssi_pcie_ctl_x4_sys_clk_hz_hwtcl                                   =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_cap_link_surprise_down_err_cap_hwtcl           =   "PF0_CAP_LINK_SURPRISE_DOWN_ERR_CAP_DISABLE",
   parameter sm_hssi_pcie_ctl_x4_pf0_port_logic_fast_link_mode                      =   "PF0_PORT_LOGIC_FAST_LINK_MODE_ENABLE",
   parameter sm_hssi_pcie_ctl_x4_pf0_prefetch_decode_hwtcl                          =   "PF0_PREFETCH_DECODE_PREF32",
   parameter sm_hssi_pcie_ctl_x4_link_rate_hwtcl				    =   "LINK_RATE_GEN3",
   parameter sm_hssi_pcie_ctl_x4_link_width_hwtcl				    =   "LINK_WIDTH_X4",
   parameter sm_hssi_pcie_ctl_x4_ecrc_strip_hwtcl				    =   "ECRC_STRIP_DISABLE",
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset0_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset1_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset2_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset3_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset4_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset5_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset6_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset7_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset8_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset9_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset10_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset11_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset12_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset13_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset14_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_16g_tx_preset15_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset0_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset1_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset2_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset3_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset4_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset5_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset6_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset7_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset8_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset9_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset10_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset11_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset12_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset13_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset14_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_dsp_tx_preset15_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset0_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset1_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset2_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset3_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset4_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset5_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset6_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset7_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset8_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset9_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset10_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset11_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset12_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset13_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset14_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_16g_tx_preset15_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset0_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset1_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset2_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset3_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset4_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset5_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset6_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset7_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset8_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset9_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset10_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset11_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset12_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset13_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset14_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_usp_tx_preset15_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x4_pf0_virtio_en_hwtcl                                =   "PF0_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_virtio_en_hwtcl                                =   "PF1_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_virtio_en_hwtcl                                =   "PF2_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_virtio_en_hwtcl                                =   "PF3_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_exvf_virtio_en_hwtcl                           =   "PF0_EXVF_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_exvf_virtio_en_hwtcl                           =   "PF1_EXVF_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_exvf_virtio_en_hwtcl                           =   "PF2_EXVF_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_exvf_virtio_en_hwtcl                           =   "PF3_EXVF_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_device_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_vendor_id_hwtcl                      =   4466,
   parameter sm_hssi_pcie_ctl_x4_pf0_revision_id_hwtcl                              =   1,
   parameter sm_hssi_pcie_ctl_x4_pf0_base_class_code_hwtcl                          =   255,
   parameter sm_hssi_pcie_ctl_x4_pf0_subclass_code_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_program_interface_hwtcl                        =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_subsys_vendor_id_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_subsys_dev_id_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_device_id_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_subsysid_pf0_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_vendor_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_device_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_revision_id_hwtcl                              =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_base_class_code_hwtcl                          =   255,
   parameter sm_hssi_pcie_ctl_x4_pf1_subclass_code_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_program_interface_hwtcl                        =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_subsys_vendor_id_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_subsys_dev_id_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_device_id_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_subsysid_pf1_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_vendor_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_device_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_revision_id_hwtcl                              =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_base_class_code_hwtcl                          =   255,
   parameter sm_hssi_pcie_ctl_x4_pf2_subclass_code_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_program_interface_hwtcl                        =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_subsys_vendor_id_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_subsys_dev_id_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_device_id_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_subsysid_pf2_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_vendor_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_device_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_revision_id_hwtcl                              =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_base_class_code_hwtcl                          =   255,
   parameter sm_hssi_pcie_ctl_x4_pf3_subclass_code_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_program_interface_hwtcl                        =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_subsys_vendor_id_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_subsys_dev_id_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_device_id_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_subsysid_pf3_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_user_vsec_cap_enable_hwtcl                     =   "PF0_USER_VSEC_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_user_vsec_cap_enable_hwtcl                     =   "PF1_USER_VSEC_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_user_vsec_cap_enable_hwtcl                     =   "PF2_USER_VSEC_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_user_vsec_cap_enable_hwtcl                     =   "PF3_USER_VSEC_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_vsec_next_offset_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_user_vsec_offset_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_user_vsec_offset_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_user_vsec_offset_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x4_cvp_vendor_specific_header_id_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x4_drop_vendor0_msg_hwtcl                             =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_drop_vendor1_msg_hwtcl                             =   "FALSE",
//   parameter sm_hssi_pcie_ctl_x4_num_of_lanes_hwtcl                                 =   4,
   parameter sm_hssi_pcie_ctl_x4_pf0_int_pin_hwtcl                                  =   "PF0_INT_PIN_NO_INT",
   parameter sm_hssi_pcie_ctl_x4_pf1_int_pin_hwtcl                                  =   "PF1_INT_PIN_NO_INT",
   parameter sm_hssi_pcie_ctl_x4_pf2_int_pin_hwtcl                                  =   "PF2_INT_PIN_NO_INT",
   parameter sm_hssi_pcie_ctl_x4_pf3_int_pin_hwtcl                                  =   "PF3_INT_PIN_NO_INT",
   parameter sm_hssi_pcie_ctl_x4_pf0_ats_cap_enable_hwtcl                           =   "PF0_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_ats_cap_enable_hwtcl                           =   "PF1_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_ats_cap_enable_hwtcl                           =   "PF2_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_ats_cap_enable_hwtcl                           =   "PF3_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_exvf_ats_cap_enable_hwtcl                      =   "PF0_EXVF_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_exvf_ats_cap_enable_hwtcl                      =   "PF1_EXVF_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_exvf_ats_cap_enable_hwtcl                      =   "PF2_EXVF_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_exvf_ats_cap_enable_hwtcl                      =   "PF3_EXVF_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_ats_exvf_align_request_hwtcl                   =   "PF0_ATS_EXVF_ALIGN_REQUEST_DISABLE",
   parameter sm_hssi_pcie_ctl_x4_pf1_ats_exvf_align_request_hwtcl                   =   "PF1_ATS_EXVF_ALIGN_REQUEST_DISABLE",
   parameter sm_hssi_pcie_ctl_x4_pf2_ats_exvf_align_request_hwtcl                   =   "PF2_ATS_EXVF_ALIGN_REQUEST_DISABLE",
   parameter sm_hssi_pcie_ctl_x4_pf3_ats_exvf_align_request_hwtcl                   =   "PF3_ATS_EXVF_ALIGN_REQUEST_DISABLE",
   parameter sm_hssi_pcie_ctl_x4_pf0_tph_cap_enable_hwtcl                           =   "PF0_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_tph_cap_enable_hwtcl                           =   "PF1_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_tph_cap_enable_hwtcl                           =   "PF2_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_tph_cap_enable_hwtcl                           =   "PF3_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_exvf_tph_cap_enable_hwtcl                      =   "PF0_EXVF_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_exvf_tph_cap_enable_hwtcl                      =   "PF1_EXVF_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_exvf_tph_cap_enable_hwtcl                      =   "PF2_EXVF_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_exvf_tph_cap_enable_hwtcl                      =   "PF3_EXVF_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_tph_req_cap_int_vec_hwtcl                      =   "PF0_TPH_REQ_CAP_INT_VEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_tph_req_cap_int_vec_hwtcl                      =   "PF1_TPH_REQ_CAP_INT_VEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_tph_req_cap_int_vec_hwtcl                      =   "PF2_TPH_REQ_CAP_INT_VEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_tph_req_cap_int_vec_hwtcl                      =   "PF3_TPH_REQ_CAP_INT_VEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_tph_req_cap_int_vec_vfcomm_cs2_hwtcl           =   "PF0_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_tph_req_cap_int_vec_vfcomm_cs2_hwtcl           =   "PF1_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_tph_req_cap_int_vec_vfcomm_cs2_hwtcl           =   "PF2_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_tph_req_cap_int_vec_vfcomm_cs2_hwtcl           =   "PF3_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl    =   "PF0_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF",
   parameter sm_hssi_pcie_ctl_x4_pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl    =   "PF1_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF",
   parameter sm_hssi_pcie_ctl_x4_pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl    =   "PF2_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF",
   parameter sm_hssi_pcie_ctl_x4_pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl    =   "PF3_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF",
   parameter sm_hssi_pcie_ctl_x4_pf0_tph_req_cap_st_table_loc_1_hwtcl               =   "PF0_TPH_REQ_CAP_ST_TABLE_LOC_1_IN_MSIX_TABLE",
   parameter sm_hssi_pcie_ctl_x4_pf1_tph_req_cap_st_table_loc_1_hwtcl               =   "PF1_TPH_REQ_CAP_ST_TABLE_LOC_1_IN_MSIX_TABLE",
   parameter sm_hssi_pcie_ctl_x4_pf2_tph_req_cap_st_table_loc_1_hwtcl               =   "PF2_TPH_REQ_CAP_ST_TABLE_LOC_1_IN_MSIX_TABLE",
   parameter sm_hssi_pcie_ctl_x4_pf3_tph_req_cap_st_table_loc_1_hwtcl               =   "PF3_TPH_REQ_CAP_ST_TABLE_LOC_1_IN_MSIX_TABLE",
   parameter sm_hssi_pcie_ctl_x4_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl    =   "PF0_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF",
   parameter sm_hssi_pcie_ctl_x4_pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl    =   "PF1_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF",
   parameter sm_hssi_pcie_ctl_x4_pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl    =   "PF2_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF",
   parameter sm_hssi_pcie_ctl_x4_pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl    =   "PF3_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF",
   parameter sm_hssi_pcie_ctl_x4_pf0_tph_req_cap_st_table_size_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_tph_req_cap_st_table_size_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_tph_req_cap_st_table_size_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_tph_req_cap_st_table_size_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl     =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl     =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl     =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl     =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_tph_req_device_spec_hwtcl                      =   "PF0_TPH_REQ_DEVICE_SPEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_tph_req_device_spec_hwtcl                      =   "PF1_TPH_REQ_DEVICE_SPEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_tph_req_device_spec_hwtcl                      =   "PF2_TPH_REQ_DEVICE_SPEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_tph_req_device_spec_hwtcl                      =   "PF3_TPH_REQ_DEVICE_SPEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_tph_req_device_spec_vfcomm_cs2_hwtcl           =   "PF0_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_tph_req_device_spec_vfcomm_cs2_hwtcl           =   "PF1_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_tph_req_device_spec_vfcomm_cs2_hwtcl           =   "PF2_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_tph_req_device_spec_vfcomm_cs2_hwtcl           =   "PF3_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_acs_cap_enable_hwtcl                           =   "PF0_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_acs_cap_enable_hwtcl                           =   "PF1_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_acs_cap_enable_hwtcl                           =   "PF2_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_acs_cap_enable_hwtcl                           =   "PF3_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_exvf_acs_cap_enable_hwtcl                      =   "PF0_EXVF_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_exvf_acs_cap_enable_hwtcl                      =   "PF1_EXVF_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_exvf_acs_cap_enable_hwtcl                      =   "PF2_EXVF_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_exvf_acs_cap_enable_hwtcl                      =   "PF3_EXVF_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_acs_cap_acs_src_valid_hwtcl                    =   "PF0_ACS_CAP_ACS_SRC_VALID_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_acs_cap_acs_src_valid_hwtcl                    =   "PF1_ACS_CAP_ACS_SRC_VALID_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_acs_cap_acs_src_valid_hwtcl                    =   "PF2_ACS_CAP_ACS_SRC_VALID_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_acs_cap_acs_src_valid_hwtcl                    =   "PF3_ACS_CAP_ACS_SRC_VALID_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_acs_cap_acs_at_block_hwtcl                     =   "PF0_ACS_CAP_ACS_AT_BLOCK_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_acs_cap_acs_at_block_hwtcl                     =   "PF1_ACS_CAP_ACS_AT_BLOCK_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_acs_cap_acs_at_block_hwtcl                     =   "PF2_ACS_CAP_ACS_AT_BLOCK_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_acs_cap_acs_at_block_hwtcl                     =   "PF3_ACS_CAP_ACS_AT_BLOCK_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_acs_cap_acs_p2p_req_redirect_hwtcl             =   "PF0_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_acs_cap_acs_p2p_req_redirect_hwtcl             =   "PF1_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_acs_cap_acs_p2p_req_redirect_hwtcl             =   "PF2_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_acs_cap_acs_p2p_req_redirect_hwtcl             =   "PF3_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_acs_cap_acs_p2p_cpl_redirect_hwtcl             =   "PF0_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_acs_cap_acs_p2p_cpl_redirect_hwtcl             =   "PF1_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_acs_cap_acs_p2p_cpl_redirect_hwtcl             =   "PF2_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_acs_cap_acs_p2p_cpl_redirect_hwtcl             =   "PF3_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_acs_cap_acs_usp_forwarding_hwtcl               =   "PF0_ACS_CAP_ACS_USP_FORWARDING_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_acs_cap_acs_usp_forwarding_hwtcl               =   "PF1_ACS_CAP_ACS_USP_FORWARDING_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_acs_cap_acs_usp_forwarding_hwtcl               =   "PF2_ACS_CAP_ACS_USP_FORWARDING_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_acs_cap_acs_usp_forwarding_hwtcl               =   "PF3_ACS_CAP_ACS_USP_FORWARDING_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_acs_cap_acs_p2p_egress_control_hwtcl           =   "PF0_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_acs_cap_acs_p2p_egress_control_hwtcl           =   "PF1_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_acs_cap_acs_p2p_egress_control_hwtcl           =   "PF2_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_acs_cap_acs_p2p_egress_control_hwtcl           =   "PF3_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_acs_cap_acs_egress_ctrl_size_hwtcl             =   8,
   parameter sm_hssi_pcie_ctl_x4_pf1_acs_cap_acs_egress_ctrl_size_hwtcl             =   8,
   parameter sm_hssi_pcie_ctl_x4_pf2_acs_cap_acs_egress_ctrl_size_hwtcl             =   8,
   parameter sm_hssi_pcie_ctl_x4_pf3_acs_cap_acs_egress_ctrl_size_hwtcl             =   8,
   parameter sm_hssi_pcie_ctl_x4_pf0_acs_cap_acs_direct_translated_p2p_hwtcl        =   "PF0_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_acs_cap_acs_direct_translated_p2p_hwtcl        =   "PF1_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_acs_cap_acs_direct_translated_p2p_hwtcl        =   "PF2_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_acs_cap_acs_direct_translated_p2p_hwtcl        =   "PF3_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_pcie_cap_ext_tag_en_hwtcl                      =   "TRUE",
   parameter sm_hssi_pcie_ctl_x4_pf1_pcie_cap_ext_tag_en_hwtcl                      =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_pcie_cap_ext_tag_en_hwtcl                      =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_pcie_cap_ext_tag_en_hwtcl                      =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_pcie_cap_flr_cap_hwtcl                         =   "PF0_PCIE_CAP_FLR_CAP_NOT_CAPABLE",
   parameter sm_hssi_pcie_ctl_x4_pf1_pcie_cap_flr_cap_hwtcl                         =   "PF1_PCIE_CAP_FLR_CAP_NOT_CAPABLE",
   parameter sm_hssi_pcie_ctl_x4_pf2_pcie_cap_flr_cap_hwtcl                         =   "PF2_PCIE_CAP_FLR_CAP_NOT_CAPABLE",
   parameter sm_hssi_pcie_ctl_x4_pf3_pcie_cap_flr_cap_hwtcl                         =   "PF3_PCIE_CAP_FLR_CAP_NOT_CAPABLE",
   parameter sm_hssi_pcie_ctl_x4_pf0_pcie_cap_port_num_hwtcl                        =   1,
   parameter sm_hssi_pcie_ctl_x4_pf1_pcie_cap_port_num_hwtcl                        =   1,
   parameter sm_hssi_pcie_ctl_x4_pf2_pcie_cap_port_num_hwtcl                        =   1,
   parameter sm_hssi_pcie_ctl_x4_pf3_pcie_cap_port_num_hwtcl                        =   1,
   parameter sm_hssi_pcie_ctl_x4_pf0_pcie_cap_slot_clk_config_hwtcl                 =   "TRUE",
   parameter sm_hssi_pcie_ctl_x4_pf1_pcie_cap_slot_clk_config_hwtcl                 =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_pcie_cap_slot_clk_config_hwtcl                 =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_pcie_cap_slot_clk_config_hwtcl                 =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_msi_enable_hwtcl                               =   "PF0_MSI_ENABLE_ENABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_msi_enable_hwtcl                               =   "PF1_MSI_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_msi_enable_hwtcl                               =   "PF2_MSI_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_msi_enable_hwtcl                               =   "PF3_MSI_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_msi_ext_data_cap_hwtcl                     =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_msi_ext_data_cap_hwtcl                     =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_msi_ext_data_cap_hwtcl                     =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_msi_ext_data_cap_hwtcl                     =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_msi_64_bit_addr_cap_hwtcl                  =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_msi_64_bit_addr_cap_hwtcl                  =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_msi_64_bit_addr_cap_hwtcl                  =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_msi_64_bit_addr_cap_hwtcl                  =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_msi_multiple_msg_cap_hwtcl                 =   "PF0_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1",
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_msi_multiple_msg_cap_hwtcl                 =   "PF1_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1",
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_msi_multiple_msg_cap_hwtcl                 =   "PF2_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1",
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_msi_multiple_msg_cap_hwtcl                 =   "PF3_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1",
   parameter sm_hssi_pcie_ctl_x4_pf0_msix_enable_hwtcl                              =   "PF0_MSIX_ENABLE_ENABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_msix_enable_hwtcl                              =   "PF1_MSIX_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_msix_enable_hwtcl                              =   "PF2_MSIX_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_msix_enable_hwtcl                              =   "PF3_MSIX_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_msix_table_size_hwtcl                      =   3,
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_msix_table_size_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_msix_table_size_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_msix_table_size_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_msix_table_offset_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_msix_table_offset_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_msix_table_offset_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_msix_table_offset_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_msix_bir_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_msix_bir_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_msix_bir_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_msix_bir_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_msix_pba_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_msix_pba_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_msix_pba_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_msix_pba_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_msix_pba_offset_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_msix_pba_offset_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_msix_pba_offset_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_msix_pba_offset_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_msix_table_size_vfcomm_cs2_hwtcl           =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_msix_table_size_vfcomm_cs2_hwtcl           =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_msix_table_size_vfcomm_cs2_hwtcl           =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_msix_table_size_vfcomm_cs2_hwtcl           =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_exvf_msix_cap_enable_hwtcl                     =   "PF0_EXVF_MSIX_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_exvf_msix_cap_enable_hwtcl                     =   "PF1_EXVF_MSIX_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_exvf_msix_cap_enable_hwtcl                     =   "PF2_EXVF_MSIX_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_exvf_msix_cap_enable_hwtcl                     =   "PF3_EXVF_MSIX_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_exvf_msix_tablesize_pf0_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msix_tablesize_pf1_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msix_tablesize_pf2_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msix_tablesize_pf3_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixtable_offset_pf0_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixtable_offset_pf1_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixtable_offset_pf2_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixtable_offset_pf3_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixtable_bir_pf0_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixtable_bir_pf1_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixtable_bir_pf2_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixtable_bir_pf3_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixpba_offset_pf0_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixpba_offset_pf1_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixpba_offset_pf2_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixpba_offset_pf3_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixpba_bir_pf0_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixpba_bir_pf1_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixpba_bir_pf2_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x4_exvf_msixpba_bir_pf3_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pcie_slot_imp_hwtcl                            =   "PF0_PCIE_SLOT_IMP_NOT_IMPLEMENTED",
   parameter sm_hssi_pcie_ctl_x4_pf0_pcie_cap_slot_power_limit_scale_hwtcl          =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pcie_cap_slot_power_limit_value_hwtcl          =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pcie_cap_phy_slot_num_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pcie_cap_hot_plug_capable_hwtcl                =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_pcie_cap_ep_l0s_accpt_latency_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pcie_cap_ep_l1_accpt_latency_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pcie_cap_ep_l0s_accpt_latency_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pcie_cap_ep_l1_accpt_latency_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pcie_cap_ep_l0s_accpt_latency_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pcie_cap_ep_l1_accpt_latency_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pcie_cap_ep_l0s_accpt_latency_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pcie_cap_ep_l1_accpt_latency_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pcie_cap_l0s_exit_latency_commclk_dis_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pcie_cap_l1_exit_latency_commclk_dis_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pcie_cap_l0s_exit_latency_commclk_dis_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pcie_cap_l1_exit_latency_commclk_dis_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pcie_cap_l0s_exit_latency_commclk_dis_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pcie_cap_l1_exit_latency_commclk_dis_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pcie_cap_l0s_exit_latency_commclk_dis_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pcie_cap_l1_exit_latency_commclk_dis_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x4_aspm_support_hwtcl				   =    "ASPM_SUPPORT_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_dbi_ro_wr_disable_hwtcl                           =   "DBI_RO_WR_DISABLE_DISABLE",
   parameter sm_hssi_pcie_ctl_x4_pf0_gen3_eq_pset_req_vec_hwtcl                     =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_gen3_eq_pset_req_vec_atg4_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_prs_ext_cap_enable_hwtcl                       =   "PF0_PRS_EXT_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_prs_ext_cap_enable_hwtcl                       =   "PF1_PRS_EXT_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_prs_ext_cap_enable_hwtcl                       =   "PF2_PRS_EXT_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_prs_ext_cap_enable_hwtcl                       =   "PF3_PRS_EXT_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_prs_ext_cap_outstanding_capacity_hwtcl         =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_prs_ext_cap_outstanding_capacity_hwtcl         =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_prs_ext_cap_outstanding_capacity_hwtcl         =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_prs_ext_cap_outstanding_capacity_hwtcl         =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_sn_cap_enable_hwtcl                            =   "PF0_SN_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_sn_cap_enable_hwtcl                            =   "PF1_SN_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_sn_cap_enable_hwtcl                            =   "PF2_SN_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_sn_cap_enable_hwtcl                            =   "PF3_SN_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_sn_ser_num_reg_1_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_sn_ser_num_reg_1_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_sn_ser_num_reg_1_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_sn_ser_num_reg_1_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_sn_ser_num_reg_2_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_sn_ser_num_reg_2_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_sn_ser_num_reg_2_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_sn_ser_num_reg_2_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pasid_cap_enable_hwtcl                         =   "PF0_PASID_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_pasid_cap_enable_hwtcl                         =   "PF1_PASID_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_pasid_cap_enable_hwtcl                         =   "PF2_PASID_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_pasid_cap_enable_hwtcl                         =   "PF3_PASID_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_pasid_cap_execute_permission_supported_hwtcl   =   "PF0_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_pasid_cap_execute_permission_supported_hwtcl   =   "PF1_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_pasid_cap_execute_permission_supported_hwtcl   =   "PF2_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_pasid_cap_execute_permission_supported_hwtcl   =   "PF3_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_pasid_cap_max_pasid_width_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pasid_cap_max_pasid_width_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pasid_cap_max_pasid_width_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pasid_cap_max_pasid_width_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pasid_cap_privileged_mode_supported_hwtcl      =   "PF0_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_pasid_cap_privileged_mode_supported_hwtcl      =   "PF1_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_pasid_cap_privileged_mode_supported_hwtcl      =   "PF2_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_pasid_cap_privileged_mode_supported_hwtcl      =   "PF3_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_ltr_cap_enable_hwtcl                           =   "PF0_LTR_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_virtual_ptm_hwtcl                                  =   "PTM_ENABLE_DISABLE",
   parameter sm_hssi_pcie_ctl_x4_ptm_autoupdate_hwtcl                               =   "PTM_AUTOUPDATE_AUTOUPDATE_DISABLE",
   parameter sm_hssi_pcie_ctl_x4_pf1_enable_hwtcl                                   =   "PF1_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_enable_hwtcl                                   =   "PF2_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_enable_hwtcl                                   =   "PF3_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_enable_hwtcl                             =   "PF0_SRIOV_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_enable_hwtcl                             =   "PF1_SRIOV_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_enable_hwtcl                             =   "PF2_SRIOV_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_enable_hwtcl                             =   "PF3_SRIOV_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_cap_sup_page_size_hwtcl                  =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_cap_sup_page_size_hwtcl                  =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_cap_sup_page_size_hwtcl                  =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_cap_sup_page_size_hwtcl                  =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar0_enabled_hwtcl                   =   "PF0_PCI_TYPE0_BAR0_ENABLED_ENABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar1_enabled_hwtcl                   =   "PF0_PCI_TYPE0_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar2_enabled_hwtcl                   =   "PF0_PCI_TYPE0_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar3_enabled_hwtcl                   =   "PF0_PCI_TYPE0_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar4_enabled_hwtcl                   =   "PF0_PCI_TYPE0_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar5_enabled_hwtcl                   =   "PF0_PCI_TYPE0_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar0_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar1_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar2_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar3_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar4_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar5_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_bar0_prefetch_hwtcl                            =   "TRUE",
   parameter sm_hssi_pcie_ctl_x4_pf0_bar1_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_bar2_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_bar3_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_bar4_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_bar5_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_rom_bar_enable_hwtcl                           =   "PF0_ROM_BAR_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_rom_bar_enabled_hwtcl                          =   "PF0_ROM_BAR_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_rom_mask_hwtcl                                 =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_rp_rom_bar_enabled_hwtcl                       =   "PF0_RP_ROM_BAR_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_rp_rom_mask_hwtcl                              =   0,
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar0_enabled_hwtcl                    =   "PF0_SRIOV_VF_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar1_enabled_hwtcl                    =   "PF0_SRIOV_VF_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar2_enabled_hwtcl                    =   "PF0_SRIOV_VF_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar3_enabled_hwtcl                    =   "PF0_SRIOV_VF_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar4_enabled_hwtcl                    =   "PF0_SRIOV_VF_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar5_enabled_hwtcl                    =   "PF0_SRIOV_VF_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar0_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar1_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar2_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar3_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar4_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar5_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar0_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar1_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar2_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar3_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar4_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar5_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf0_bar0_type_hwtcl                                =   "PF0_BAR0_TYPE_BAR_MEM64",
   parameter sm_hssi_pcie_ctl_x4_pf0_bar2_type_hwtcl                                =   "PF0_BAR2_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf0_bar4_type_hwtcl                                =   "PF0_BAR4_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar0_type_hwtcl                       =   "PF0_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar2_type_hwtcl                       =   "PF0_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf0_sriov_vf_bar4_type_hwtcl                       =   "PF0_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_bar0_enabled_hwtcl                   =   "PF1_PCI_TYPE0_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_bar1_enabled_hwtcl                   =   "PF1_PCI_TYPE0_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_bar2_enabled_hwtcl                   =   "PF1_PCI_TYPE0_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_bar3_enabled_hwtcl                   =   "PF1_PCI_TYPE0_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_bar4_enabled_hwtcl                   =   "PF1_PCI_TYPE0_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_bar5_enabled_hwtcl                   =   "PF1_PCI_TYPE0_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_bar0_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_bar1_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_bar2_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_bar3_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_bar4_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_pci_type0_bar5_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_bar0_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_bar1_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_bar2_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_bar3_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_bar4_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_bar5_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_rom_bar_enable_hwtcl                           =   "PF1_ROM_BAR_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_rom_bar_enabled_hwtcl                          =   "PF1_ROM_BAR_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_rom_mask_hwtcl                                 =   0,
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar0_enabled_hwtcl                    =   "PF1_SRIOV_VF_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar1_enabled_hwtcl                    =   "PF1_SRIOV_VF_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar2_enabled_hwtcl                    =   "PF1_SRIOV_VF_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar3_enabled_hwtcl                    =   "PF1_SRIOV_VF_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar4_enabled_hwtcl                    =   "PF1_SRIOV_VF_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar5_enabled_hwtcl                    =   "PF1_SRIOV_VF_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar0_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar1_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar2_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar3_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar4_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar5_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar0_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar1_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar2_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar3_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar4_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar5_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf1_bar0_type_hwtcl                                =   "PF1_BAR0_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf1_bar2_type_hwtcl                                =   "PF1_BAR2_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf1_bar4_type_hwtcl                                =   "PF1_BAR4_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar0_type_hwtcl                       =   "PF1_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar2_type_hwtcl                       =   "PF1_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf1_sriov_vf_bar4_type_hwtcl                       =   "PF1_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_bar0_enabled_hwtcl                   =   "PF2_PCI_TYPE0_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_bar1_enabled_hwtcl                   =   "PF2_PCI_TYPE0_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_bar2_enabled_hwtcl                   =   "PF2_PCI_TYPE0_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_bar3_enabled_hwtcl                   =   "PF2_PCI_TYPE0_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_bar4_enabled_hwtcl                   =   "PF2_PCI_TYPE0_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_bar5_enabled_hwtcl                   =   "PF2_PCI_TYPE0_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_bar0_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_bar1_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_bar2_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_bar3_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_bar4_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_pci_type0_bar5_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_bar0_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_bar1_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_bar2_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_bar3_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_bar4_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_bar5_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_rom_bar_enable_hwtcl                           =   "PF2_ROM_BAR_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_rom_bar_enabled_hwtcl                          =   "PF2_ROM_BAR_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_rom_mask_hwtcl                                 =   0,
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar0_enabled_hwtcl                    =   "PF2_SRIOV_VF_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar1_enabled_hwtcl                    =   "PF2_SRIOV_VF_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar2_enabled_hwtcl                    =   "PF2_SRIOV_VF_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar3_enabled_hwtcl                    =   "PF2_SRIOV_VF_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar4_enabled_hwtcl                    =   "PF2_SRIOV_VF_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar5_enabled_hwtcl                    =   "PF2_SRIOV_VF_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar0_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar1_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar2_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar3_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar4_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar5_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar0_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar1_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar2_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar3_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar4_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar5_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf2_bar0_type_hwtcl                                =   "PF2_BAR0_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf2_bar2_type_hwtcl                                =   "PF2_BAR2_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf2_bar4_type_hwtcl                                =   "PF2_BAR4_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar0_type_hwtcl                       =   "PF2_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar2_type_hwtcl                       =   "PF2_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf2_sriov_vf_bar4_type_hwtcl                       =   "PF2_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_bar0_enabled_hwtcl                   =   "PF3_PCI_TYPE0_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_bar1_enabled_hwtcl                   =   "PF3_PCI_TYPE0_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_bar2_enabled_hwtcl                   =   "PF3_PCI_TYPE0_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_bar3_enabled_hwtcl                   =   "PF3_PCI_TYPE0_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_bar4_enabled_hwtcl                   =   "PF3_PCI_TYPE0_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_bar5_enabled_hwtcl                   =   "PF3_PCI_TYPE0_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_bar0_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_bar1_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_bar2_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_bar3_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_bar4_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_pci_type0_bar5_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_bar0_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_bar1_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_bar2_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_bar3_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_bar4_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_bar5_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_rom_bar_enable_hwtcl                           =   "PF3_ROM_BAR_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_rom_bar_enabled_hwtcl                          =   "PF3_ROM_BAR_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_rom_mask_hwtcl                                 =   0,
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar0_enabled_hwtcl                    =   "PF3_SRIOV_VF_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar1_enabled_hwtcl                    =   "PF3_SRIOV_VF_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar2_enabled_hwtcl                    =   "PF3_SRIOV_VF_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar3_enabled_hwtcl                    =   "PF3_SRIOV_VF_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar4_enabled_hwtcl                    =   "PF3_SRIOV_VF_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar5_enabled_hwtcl                    =   "PF3_SRIOV_VF_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar0_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar1_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar2_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar3_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar4_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar5_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar0_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar1_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar2_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar3_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar4_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar5_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x4_pf3_bar0_type_hwtcl                                =   "PF3_BAR0_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf3_bar2_type_hwtcl                                =   "PF3_BAR2_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf3_bar4_type_hwtcl                                =   "PF3_BAR4_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar0_type_hwtcl                       =   "PF3_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar2_type_hwtcl                       =   "PF3_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x4_pf3_sriov_vf_bar4_type_hwtcl                       =   "PF3_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32",
   parameter ch0_xcvr_rx_protocol_hint_hwtcl                                        =   "PCIE_GEN3",
   parameter ch1_xcvr_rx_protocol_hint_hwtcl                                        =   "PCIE_GEN3",
   parameter ch2_xcvr_rx_protocol_hint_hwtcl                                        =   "PCIE_GEN3",
   parameter ch3_xcvr_rx_protocol_hint_hwtcl                                        =   "PCIE_GEN3",
   parameter ch0_xcvr_tx_protocol_hint_hwtcl                                        =   "PCIE_GEN3",
   parameter ch1_xcvr_tx_protocol_hint_hwtcl                                        =   "PCIE_GEN3",
   parameter ch2_xcvr_tx_protocol_hint_hwtcl                                        =   "PCIE_GEN3",
   parameter ch3_xcvr_tx_protocol_hint_hwtcl                                        =   "PCIE_GEN3",
   parameter ch0_sim_mode_hwtcl                                                     =   "DISABLE",
   parameter ch1_sim_mode_hwtcl                                                     =   "DISABLE",
   parameter ch2_sim_mode_hwtcl                                                     =   "DISABLE",
   parameter ch3_sim_mode_hwtcl                                                     =   "DISABLE",

parameter   sm_hssi_pcie_ctl_x4_num_of_lanes_hwtcl = "NUM_OF_LANES_NUM_1",
parameter   core16_empty_width_integer_hwtcl  =    3, //new: tdata_width=256, empty_width=3 .if tdata_width=128, empty_width=2
parameter   core16_func_mode_hwtcl = "Enable",
parameter   core16_pf0_bar0_address_width_hwtcl = 16,
parameter   core16_pf0_bar1_address_width_hwtcl = 16,
parameter   core16_pf0_bar2_address_width_hwtcl = 16,
parameter   core16_pf0_bar3_address_width_hwtcl = 16,
parameter   core16_pf0_bar4_address_width_hwtcl = 16,
parameter   core16_pf0_bar5_address_width_hwtcl = 16,

parameter is_sm4_sm7_revA = 0,
parameter l_quad_num = 0,
//vteh ww35 added for pipemode sim
parameter pipemode_sim_hwtcl = 0,

   //--------------------------------core8 params-------------------------------------------------------------------------------------
   parameter  core8_topology                                                    =   "pcie_x8",

   parameter  core8_tdata_width_integer_hwtcl                            =    256, //new: 256, 128
   //parameter  core8_empty_width_integer_hwtcl                            =    3, //new: tdata_width=256, empty_width=3 .if tdata_width=128, empty_width=2

   parameter  ctop_core8_virtual_rp_ep_mode                               =   "CTOP_CORE4_EP",
   parameter  core8_virtual_tlp_bypass_en_hwtcl                           =     0,
   parameter  core8_total_pf_count_width_hwtcl                            =     1,
   parameter  core8_total_vf_count_width_hwtcl                            =     0,
   parameter  core8_total_pf_count_hwtcl                                  =     1,
   parameter  core8_total_vf_count_hwtcl                                  =     1,

   // PCS Reconfig
   parameter  core8_hip_reconfig_hwtcl                                    =     0,

   // rx_buffer_limit
   parameter  core8_enable_rx_buffer_limit_ports_hwtcl                  =     1,

   // PTM
   parameter  core8_virtual_ptm_hwtcl                                     =     0,

   // ARI_ACS_FUN_GRP_CAP
   parameter  ctop_core8_pf0_ari_acs_fun_grp_cap                          =     "FALSE", 

   //Independent pin perst
   parameter  ctop_virtual_x8_perst_sel                                  =    "CTOP_CMN_HARD_X4",

   // ECC enable
   parameter core8_enable_ecc_hwtcl                                     =     0,

   //USER_MODE_TO_PLD_IN_USE
   parameter  core8_user_mode_to_pld_in_use_hwtcl                       =     0,

   // pld_warm_rst_rdy
   parameter  core8_enable_pld_warm_rst_rdy_hwtcl                       =     0,

   // max payload
   parameter  ctop_core8_virtual_maxpayload_size                        =     "CTOP_CORE8_MAX_PAYLOAD_512",
   
   // ast_parity
   parameter  core8_use_ast_parity_hwtcl                                =     0,
   
   // Power Management
   parameter  core8_enable_power_mgnt_intf_hwtcl                        =     0,

   // Error Interface
   parameter  core8_enable_error_intf_hwtcl                             =     0,
   
   // FLR
   parameter  core8_flr_cap_hwtcl                                       =     0,
   
   // cpl_timeout
   parameter  core8_enable_cpl_timeout_hwtcl                            =     0,
   
   // multi_func
   parameter  core8_enable_multi_func_hwtcl                               =     0,
   
   // SRIOV
   parameter  core8_enable_sriov_hwtcl                                    =     0,
   
   // 10-bit tag
   
   // CEB
   parameter  core8_pf_ceb_pointer_addr_hwtcl                        =     0,
   parameter  core8_vf_ceb_pointer_addr_hwtcl                        =     0,

   // Virtio
   parameter  core8_enable_virtio_hwtcl                                   =     0,
   parameter  core8_virtio_start_byte_address_hwtcl                       =     8'h48,
   parameter  core8_pf0_virtio_capability_present_hwtcl                   =     00,
   parameter  core8_pf0_virtio_device_specific_cap_present_hwtcl          =     0,
   parameter  core8_pf0_virtio_cmn_config_bar_indicator_hwtcl             =     0,
   parameter  core8_pf0_virtio_cmn_config_bar_offset_hwtcl                =     0,
   parameter  core8_pf0_virtio_cmn_config_structure_length_hwtcl          =     0,
   parameter  core8_pf0_virtio_notification_bar_indicator_hwtcl           =     0,
   parameter  core8_pf0_virtio_notification_bar_offset_hwtcl              =     0,
   parameter  core8_pf0_virtio_notification_structure_length_hwtcl        =     0,
   parameter  core8_pf0_virtio_notify_off_multiplier_hwtcl                =     0,
   parameter  core8_pf0_virtio_isrstatus_bar_indicator_hwtcl              =     0,
   parameter  core8_pf0_virtio_isrstatus_bar_offset_hwtcl                 =     0,
   parameter  core8_pf0_virtio_isrstatus_structure_length_hwtcl           =     0,
   parameter  core8_pf0_virtio_devspecific_bar_indicator_hwtcl            =     0,
   parameter  core8_pf0_virtio_devspecific_bar_offset_hwtcl               =     0,
   parameter  core8_pf0_virtio_devspecific_structure_length_hwtcl         =     0,
   parameter  core8_pf0_virtio_pciconfig_access_bar_indicator_hwtcl       =     0,
   parameter  core8_pf0_virtio_pciconfig_access_bar_offset_hwtcl          =     0,
   parameter  core8_pf0_virtio_pciconfig_access_structure_length_hwtcl    =     0,
   parameter  core8_pf1_virtio_capability_present_hwtcl                   =     0,
   parameter  core8_pf1_virtio_device_specific_cap_present_hwtcl          =     0,
   parameter  core8_pf1_virtio_cmn_config_bar_indicator_hwtcl             =     0,
   parameter  core8_pf1_virtio_cmn_config_bar_offset_hwtcl                =     0,
   parameter  core8_pf1_virtio_cmn_config_structure_length_hwtcl          =     0,
   parameter  core8_pf1_virtio_notification_bar_indicator_hwtcl           =     0,
   parameter  core8_pf1_virtio_notification_bar_offset_hwtcl              =     0,
   parameter  core8_pf1_virtio_notification_structure_length_hwtcl        =     0,
   parameter  core8_pf1_virtio_notify_off_multiplier_hwtcl                =     0,
   parameter  core8_pf1_virtio_isrstatus_bar_indicator_hwtcl              =     0,
   parameter  core8_pf1_virtio_isrstatus_bar_offset_hwtcl                 =     0,
   parameter  core8_pf1_virtio_isrstatus_structure_length_hwtcl           =     0,
   parameter  core8_pf1_virtio_devspecific_bar_indicator_hwtcl            =     0,
   parameter  core8_pf1_virtio_devspecific_bar_offset_hwtcl               =     0,
   parameter  core8_pf1_virtio_devspecific_structure_length_hwtcl         =     0,
   parameter  core8_pf1_virtio_pciconfig_access_bar_indicator_hwtcl       =     0,
   parameter  core8_pf1_virtio_pciconfig_access_bar_offset_hwtcl          =     0,
   parameter  core8_pf1_virtio_pciconfig_access_structure_length_hwtcl    =     0,
   parameter  core8_pf2_virtio_capability_present_hwtcl                   =     0,
   parameter  core8_pf2_virtio_device_specific_cap_present_hwtcl          =     0,
   parameter  core8_pf2_virtio_cmn_config_bar_indicator_hwtcl             =     0,
   parameter  core8_pf2_virtio_cmn_config_bar_offset_hwtcl                =     0,
   parameter  core8_pf2_virtio_cmn_config_structure_length_hwtcl          =     0,
   parameter  core8_pf2_virtio_notification_bar_indicator_hwtcl           =     0,
   parameter  core8_pf2_virtio_notification_bar_offset_hwtcl              =     0,
   parameter  core8_pf2_virtio_notification_structure_length_hwtcl        =     0,
   parameter  core8_pf2_virtio_notify_off_multiplier_hwtcl                =     0,
   parameter  core8_pf2_virtio_isrstatus_bar_indicator_hwtcl              =     0,
   parameter  core8_pf2_virtio_isrstatus_bar_offset_hwtcl                 =     0,
   parameter  core8_pf2_virtio_isrstatus_structure_length_hwtcl           =     0,
   parameter  core8_pf2_virtio_devspecific_bar_indicator_hwtcl            =     0,
   parameter  core8_pf2_virtio_devspecific_bar_offset_hwtcl               =     0,
   parameter  core8_pf2_virtio_devspecific_structure_length_hwtcl         =     0,
   parameter  core8_pf2_virtio_pciconfig_access_bar_indicator_hwtcl       =     0,
   parameter  core8_pf2_virtio_pciconfig_access_bar_offset_hwtcl          =     0,
   parameter  core8_pf2_virtio_pciconfig_access_structure_length_hwtcl    =     0,
   parameter  core8_pf3_virtio_capability_present_hwtcl                   =     0,
   parameter  core8_pf3_virtio_device_specific_cap_present_hwtcl          =     0,
   parameter  core8_pf3_virtio_cmn_config_bar_indicator_hwtcl             =     0,
   parameter  core8_pf3_virtio_cmn_config_bar_offset_hwtcl                =     0,
   parameter  core8_pf3_virtio_cmn_config_structure_length_hwtcl          =     0,
   parameter  core8_pf3_virtio_notification_bar_indicator_hwtcl           =     0,
   parameter  core8_pf3_virtio_notification_bar_offset_hwtcl              =     0,
   parameter  core8_pf3_virtio_notification_structure_length_hwtcl        =     0,
   parameter  core8_pf3_virtio_notify_off_multiplier_hwtcl                =     0,
   parameter  core8_pf3_virtio_isrstatus_bar_indicator_hwtcl              =     0,
   parameter  core8_pf3_virtio_isrstatus_bar_offset_hwtcl                 =     0,
   parameter  core8_pf3_virtio_isrstatus_structure_length_hwtcl           =     0,
   parameter  core8_pf3_virtio_devspecific_bar_indicator_hwtcl            =     0,
   parameter  core8_pf3_virtio_devspecific_bar_offset_hwtcl               =     0,
   parameter  core8_pf3_virtio_devspecific_structure_length_hwtcl         =     0,
   parameter  core8_pf3_virtio_pciconfig_access_bar_indicator_hwtcl       =     0,
   parameter  core8_pf3_virtio_pciconfig_access_bar_offset_hwtcl          =     0,
   parameter  core8_pf3_virtio_pciconfig_access_structure_length_hwtcl    =     0,
   parameter  core8_pf0vf_virtio_capability_present_hwtcl                 =     0,
   parameter  core8_pf0vf_virtio_device_specific_cap_present_hwtcl        =     0,
   parameter  core8_pf0vf_virtio_cmn_config_bar_indicator_hwtcl           =     0,
   parameter  core8_pf0vf_virtio_cmn_config_bar_offset_hwtcl              =     0,
   parameter  core8_pf0vf_virtio_cmn_config_structure_length_hwtcl        =     0,
   parameter  core8_pf0vf_virtio_notification_bar_indicator_hwtcl         =     0,
   parameter  core8_pf0vf_virtio_notification_bar_offset_hwtcl            =     0,
   parameter  core8_pf0vf_virtio_notification_structure_length_hwtcl      =     0,
   parameter  core8_pf0vf_virtio_notify_off_multiplier_hwtcl              =     0,
   parameter  core8_pf0vf_virtio_isrstatus_bar_indicator_hwtcl            =     0,
   parameter  core8_pf0vf_virtio_isrstatus_bar_offset_hwtcl               =     0,
   parameter  core8_pf0vf_virtio_isrstatus_structure_length_hwtcl         =     0,
   parameter  core8_pf0vf_virtio_devspecific_bar_indicator_hwtcl          =     0,
   parameter  core8_pf0vf_virtio_devspecific_bar_offset_hwtcl             =     0,
   parameter  core8_pf0vf_virtio_devspecific_structure_length_hwtcl       =     0,
   parameter  core8_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl     =     0,
   parameter  core8_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl        =     0,
   parameter  core8_pf0vf_virtio_pciconfig_access_structure_length_hwtcl  =     0,
   parameter  core8_pf1vf_virtio_capability_present_hwtcl                 =     0,
   parameter  core8_pf1vf_virtio_device_specific_cap_present_hwtcl        =     0,
   parameter  core8_pf1vf_virtio_cmn_config_bar_indicator_hwtcl           =     0,
   parameter  core8_pf1vf_virtio_cmn_config_bar_offset_hwtcl              =     0,
   parameter  core8_pf1vf_virtio_cmn_config_structure_length_hwtcl        =     0,
   parameter  core8_pf1vf_virtio_notification_bar_indicator_hwtcl         =     0,
   parameter  core8_pf1vf_virtio_notification_bar_offset_hwtcl            =     0,
   parameter  core8_pf1vf_virtio_notification_structure_length_hwtcl      =     0,
   parameter  core8_pf1vf_virtio_notify_off_multiplier_hwtcl              =     0,
   parameter  core8_pf1vf_virtio_isrstatus_bar_indicator_hwtcl            =     0,
   parameter  core8_pf1vf_virtio_isrstatus_bar_offset_hwtcl               =     0,
   parameter  core8_pf1vf_virtio_isrstatus_structure_length_hwtcl         =     0,
   parameter  core8_pf1vf_virtio_devspecific_bar_indicator_hwtcl          =     0,
   parameter  core8_pf1vf_virtio_devspecific_bar_offset_hwtcl             =     0,
   parameter  core8_pf1vf_virtio_devspecific_structure_length_hwtcl       =     0,
   parameter  core8_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl     =     0,
   parameter  core8_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl        =     0,
   parameter  core8_pf1vf_virtio_pciconfig_access_structure_length_hwtcl  =     0,
   parameter  core8_pf2vf_virtio_capability_present_hwtcl                 =     0,
   parameter  core8_pf2vf_virtio_device_specific_cap_present_hwtcl        =     0,
   parameter  core8_pf2vf_virtio_cmn_config_bar_indicator_hwtcl           =     0,
   parameter  core8_pf2vf_virtio_cmn_config_bar_offset_hwtcl              =     0,
   parameter  core8_pf2vf_virtio_cmn_config_structure_length_hwtcl        =     0,
   parameter  core8_pf2vf_virtio_notification_bar_indicator_hwtcl         =     0,
   parameter  core8_pf2vf_virtio_notification_bar_offset_hwtcl            =     0,
   parameter  core8_pf2vf_virtio_notification_structure_length_hwtcl      =     0,
   parameter  core8_pf2vf_virtio_notify_off_multiplier_hwtcl              =     0,
   parameter  core8_pf2vf_virtio_isrstatus_bar_indicator_hwtcl            =     0,
   parameter  core8_pf2vf_virtio_isrstatus_bar_offset_hwtcl               =     0,
   parameter  core8_pf2vf_virtio_isrstatus_structure_length_hwtcl         =     0,
   parameter  core8_pf2vf_virtio_devspecific_bar_indicator_hwtcl          =     0,
   parameter  core8_pf2vf_virtio_devspecific_bar_offset_hwtcl             =     0,
   parameter  core8_pf2vf_virtio_devspecific_structure_length_hwtcl       =     0,
   parameter  core8_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl     =     0,
   parameter  core8_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl        =     0,
   parameter  core8_pf2vf_virtio_pciconfig_access_structure_length_hwtcl  =     0,
   parameter  core8_pf3vf_virtio_capability_present_hwtcl                 =     0,
   parameter  core8_pf3vf_virtio_device_specific_cap_present_hwtcl        =     0,
   parameter  core8_pf3vf_virtio_cmn_config_bar_indicator_hwtcl           =     0,
   parameter  core8_pf3vf_virtio_cmn_config_bar_offset_hwtcl              =     0,
   parameter  core8_pf3vf_virtio_cmn_config_structure_length_hwtcl        =     0,
   parameter  core8_pf3vf_virtio_notification_bar_indicator_hwtcl         =     0,
   parameter  core8_pf3vf_virtio_notification_bar_offset_hwtcl            =     0,
   parameter  core8_pf3vf_virtio_notification_structure_length_hwtcl      =     0,
   parameter  core8_pf3vf_virtio_notify_off_multiplier_hwtcl              =     0,
   parameter  core8_pf3vf_virtio_isrstatus_bar_indicator_hwtcl            =     0,
   parameter  core8_pf3vf_virtio_isrstatus_bar_offset_hwtcl               =     0,
   parameter  core8_pf3vf_virtio_isrstatus_structure_length_hwtcl         =     0,
   parameter  core8_pf3vf_virtio_devspecific_bar_indicator_hwtcl          =     0,
   parameter  core8_pf3vf_virtio_devspecific_bar_offset_hwtcl             =     0,
   parameter  core8_pf3vf_virtio_devspecific_structure_length_hwtcl       =     0,
   parameter  core8_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl     =     0,
   parameter  core8_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl        =     0,
   parameter  core8_pf3vf_virtio_pciconfig_access_structure_length_hwtcl  =     0,
   parameter  core8_pf0_vf_count_hwtcl                                    =     0,
   parameter  core8_pf1_vf_count_hwtcl                                    =     0,
   parameter  core8_pf2_vf_count_hwtcl                                    =     0,
   parameter  core8_pf3_vf_count_hwtcl                                    =     0,

   parameter sm_hssi_pcie_ctl_x8_rxbuf_limit_bypass_hwtcl                           =   7,
   parameter sm_hssi_pcie_ctl_x8_maxpayload_size_hwtcl                              =   "MAXPAYLOAD_SIZE_MAX_PAYLOAD_128",
   parameter sm_hssi_pcie_ctl_x8_port_type_hwtcl                                    =   "PORT_TYPE_NATIVE_EP",
   parameter sm_hssi_pcie_ctl_x8_sris_enable_hwtcl                                  =   "SRIS_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_link_num_hwtcl                                     =   "SRIS_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_sris_mode_hwtcl                                    =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_sim_mode_hwtcl                                     =   "SIM_MODE_DISABLE_VSIM_MODE",
   parameter sm_hssi_pcie_ctl_x8_sup_mode_hwtcl                                     =   "SUP_MODE_USER_MODE",
   parameter sm_hssi_pcie_ctl_x8_cvp_enable_hwtcl                                   =   "CVP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_cii_monitor_en_hwtcl                               =   "CII_MONITOR_EN_DISABLE",
   parameter sm_hssi_pcie_ctl_x8_pclk_clk_hz_hwtcl                                  =   0,
   parameter sm_hssi_pcie_ctl_x8_sys_clk_hz_hwtcl                                   =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_cap_link_surprise_down_err_cap_hwtcl           =   "PF0_CAP_LINK_SURPRISE_DOWN_ERR_CAP_DISABLE",
   parameter sm_hssi_pcie_ctl_x8_pf0_port_logic_fast_link_mode                      =   "PF0_PORT_LOGIC_FAST_LINK_MODE_ENABLE",
   parameter sm_hssi_pcie_ctl_x8_pf0_prefetch_decode_hwtcl                          =   "PF0_PREFETCH_DECODE_PREF32",
   parameter sm_hssi_pcie_ctl_x8_link_rate_hwtcl				    =   "LINK_RATE_GEN3",
   parameter sm_hssi_pcie_ctl_x8_link_width_hwtcl				    =   "LINK_WIDTH_X4",
   parameter sm_hssi_pcie_ctl_x8_ecrc_strip_hwtcl				    =   "ECRC_STRIP_DISABLE",
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset0_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset1_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset2_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset3_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset4_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset5_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset6_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset7_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset8_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset9_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset10_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset11_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset12_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset13_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset14_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_16g_tx_preset15_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset0_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset1_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset2_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset3_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset4_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset5_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset6_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset7_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset8_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset9_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset10_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset11_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset12_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset13_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset14_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_dsp_tx_preset15_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset0_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset1_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset2_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset3_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset4_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset5_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset6_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset7_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset8_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset9_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset10_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset11_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset12_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset13_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset14_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_16g_tx_preset15_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset0_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset1_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset2_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset3_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset4_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset5_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset6_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset7_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset8_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset9_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset10_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset11_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset12_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset13_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset14_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_usp_tx_preset15_hwtcl			    =	0,
   parameter sm_hssi_pcie_ctl_x8_pf0_virtio_en_hwtcl                                =   "PF0_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_virtio_en_hwtcl                                =   "PF1_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_virtio_en_hwtcl                                =   "PF2_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_virtio_en_hwtcl                                =   "PF3_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_exvf_virtio_en_hwtcl                           =   "PF0_EXVF_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_exvf_virtio_en_hwtcl                           =   "PF1_EXVF_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_exvf_virtio_en_hwtcl                           =   "PF2_EXVF_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_exvf_virtio_en_hwtcl                           =   "PF3_EXVF_VIRTIO_EN_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_device_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_vendor_id_hwtcl                      =   4466,
   parameter sm_hssi_pcie_ctl_x8_pf0_revision_id_hwtcl                              =   1,
   parameter sm_hssi_pcie_ctl_x8_pf0_base_class_code_hwtcl                          =   255,
   parameter sm_hssi_pcie_ctl_x8_pf0_subclass_code_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_program_interface_hwtcl                        =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_subsys_vendor_id_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_subsys_dev_id_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_device_id_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_subsysid_pf0_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_vendor_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_device_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_revision_id_hwtcl                              =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_base_class_code_hwtcl                          =   255,
   parameter sm_hssi_pcie_ctl_x8_pf1_subclass_code_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_program_interface_hwtcl                        =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_subsys_vendor_id_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_subsys_dev_id_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_device_id_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_subsysid_pf1_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_vendor_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_device_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_revision_id_hwtcl                              =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_base_class_code_hwtcl                          =   255,
   parameter sm_hssi_pcie_ctl_x8_pf2_subclass_code_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_program_interface_hwtcl                        =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_subsys_vendor_id_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_subsys_dev_id_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_device_id_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_subsysid_pf2_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_vendor_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_device_id_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_revision_id_hwtcl                              =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_base_class_code_hwtcl                          =   255,
   parameter sm_hssi_pcie_ctl_x8_pf3_subclass_code_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_program_interface_hwtcl                        =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_subsys_vendor_id_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_subsys_dev_id_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_device_id_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_subsysid_pf3_hwtcl                            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_user_vsec_cap_enable_hwtcl                     =   "PF0_USER_VSEC_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_user_vsec_cap_enable_hwtcl                     =   "PF1_USER_VSEC_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_user_vsec_cap_enable_hwtcl                     =   "PF2_USER_VSEC_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_user_vsec_cap_enable_hwtcl                     =   "PF3_USER_VSEC_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_vsec_next_offset_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_user_vsec_offset_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_user_vsec_offset_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_user_vsec_offset_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x8_cvp_vendor_specific_header_id_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x8_drop_vendor0_msg_hwtcl                             =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_drop_vendor1_msg_hwtcl                             =   "FALSE",
//   parameter sm_hssi_pcie_ctl_x8_num_of_lanes_hwtcl                                 =   4,
   parameter sm_hssi_pcie_ctl_x8_pf0_int_pin_hwtcl                                  =   "PF0_INT_PIN_NO_INT",
   parameter sm_hssi_pcie_ctl_x8_pf1_int_pin_hwtcl                                  =   "PF1_INT_PIN_NO_INT",
   parameter sm_hssi_pcie_ctl_x8_pf2_int_pin_hwtcl                                  =   "PF2_INT_PIN_NO_INT",
   parameter sm_hssi_pcie_ctl_x8_pf3_int_pin_hwtcl                                  =   "PF3_INT_PIN_NO_INT",
   parameter sm_hssi_pcie_ctl_x8_pf0_ats_cap_enable_hwtcl                           =   "PF0_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_ats_cap_enable_hwtcl                           =   "PF1_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_ats_cap_enable_hwtcl                           =   "PF2_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_ats_cap_enable_hwtcl                           =   "PF3_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_exvf_ats_cap_enable_hwtcl                      =   "PF0_EXVF_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_exvf_ats_cap_enable_hwtcl                      =   "PF1_EXVF_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_exvf_ats_cap_enable_hwtcl                      =   "PF2_EXVF_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_exvf_ats_cap_enable_hwtcl                      =   "PF3_EXVF_ATS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_ats_exvf_align_request_hwtcl                   =   "PF0_ATS_EXVF_ALIGN_REQUEST_DISABLE",
   parameter sm_hssi_pcie_ctl_x8_pf1_ats_exvf_align_request_hwtcl                   =   "PF1_ATS_EXVF_ALIGN_REQUEST_DISABLE",
   parameter sm_hssi_pcie_ctl_x8_pf2_ats_exvf_align_request_hwtcl                   =   "PF2_ATS_EXVF_ALIGN_REQUEST_DISABLE",
   parameter sm_hssi_pcie_ctl_x8_pf3_ats_exvf_align_request_hwtcl                   =   "PF3_ATS_EXVF_ALIGN_REQUEST_DISABLE",
   parameter sm_hssi_pcie_ctl_x8_pf0_tph_cap_enable_hwtcl                           =   "PF0_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_tph_cap_enable_hwtcl                           =   "PF1_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_tph_cap_enable_hwtcl                           =   "PF2_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_tph_cap_enable_hwtcl                           =   "PF3_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_exvf_tph_cap_enable_hwtcl                      =   "PF0_EXVF_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_exvf_tph_cap_enable_hwtcl                      =   "PF1_EXVF_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_exvf_tph_cap_enable_hwtcl                      =   "PF2_EXVF_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_exvf_tph_cap_enable_hwtcl                      =   "PF3_EXVF_TPH_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_tph_req_cap_int_vec_hwtcl                      =   "PF0_TPH_REQ_CAP_INT_VEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_tph_req_cap_int_vec_hwtcl                      =   "PF1_TPH_REQ_CAP_INT_VEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_tph_req_cap_int_vec_hwtcl                      =   "PF2_TPH_REQ_CAP_INT_VEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_tph_req_cap_int_vec_hwtcl                      =   "PF3_TPH_REQ_CAP_INT_VEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_tph_req_cap_int_vec_vfcomm_cs2_hwtcl           =   "PF0_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_tph_req_cap_int_vec_vfcomm_cs2_hwtcl           =   "PF1_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_tph_req_cap_int_vec_vfcomm_cs2_hwtcl           =   "PF2_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_tph_req_cap_int_vec_vfcomm_cs2_hwtcl           =   "PF3_TPH_REQ_CAP_INT_VEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl    =   "PF0_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF",
   parameter sm_hssi_pcie_ctl_x8_pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl    =   "PF1_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF",
   parameter sm_hssi_pcie_ctl_x8_pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl    =   "PF2_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF",
   parameter sm_hssi_pcie_ctl_x8_pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2_hwtcl    =   "PF3_TPH_REQ_CAP_ST_TABLE_LOC_0_VFCOMM_CS2_NOT_IN_TPH_STRUCT_VF",
   parameter sm_hssi_pcie_ctl_x8_pf0_tph_req_cap_st_table_loc_1_hwtcl               =   "PF0_TPH_REQ_CAP_ST_TABLE_LOC_1_IN_MSIX_TABLE",
   parameter sm_hssi_pcie_ctl_x8_pf1_tph_req_cap_st_table_loc_1_hwtcl               =   "PF1_TPH_REQ_CAP_ST_TABLE_LOC_1_IN_MSIX_TABLE",
   parameter sm_hssi_pcie_ctl_x8_pf2_tph_req_cap_st_table_loc_1_hwtcl               =   "PF2_TPH_REQ_CAP_ST_TABLE_LOC_1_IN_MSIX_TABLE",
   parameter sm_hssi_pcie_ctl_x8_pf3_tph_req_cap_st_table_loc_1_hwtcl               =   "PF3_TPH_REQ_CAP_ST_TABLE_LOC_1_IN_MSIX_TABLE",
   parameter sm_hssi_pcie_ctl_x8_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl    =   "PF0_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF",
   parameter sm_hssi_pcie_ctl_x8_pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl    =   "PF1_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF",
   parameter sm_hssi_pcie_ctl_x8_pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl    =   "PF2_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF",
   parameter sm_hssi_pcie_ctl_x8_pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl    =   "PF3_TPH_REQ_CAP_ST_TABLE_LOC_1_VFCOMM_CS2_NOT_IN_MSIX_TABLE_VF",
   parameter sm_hssi_pcie_ctl_x8_pf0_tph_req_cap_st_table_size_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_tph_req_cap_st_table_size_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_tph_req_cap_st_table_size_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_tph_req_cap_st_table_size_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl     =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl     =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl     =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl     =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_tph_req_device_spec_hwtcl                      =   "PF0_TPH_REQ_DEVICE_SPEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_tph_req_device_spec_hwtcl                      =   "PF1_TPH_REQ_DEVICE_SPEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_tph_req_device_spec_hwtcl                      =   "PF2_TPH_REQ_DEVICE_SPEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_tph_req_device_spec_hwtcl                      =   "PF3_TPH_REQ_DEVICE_SPEC_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_tph_req_device_spec_vfcomm_cs2_hwtcl           =   "PF0_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_tph_req_device_spec_vfcomm_cs2_hwtcl           =   "PF1_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_tph_req_device_spec_vfcomm_cs2_hwtcl           =   "PF2_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_tph_req_device_spec_vfcomm_cs2_hwtcl           =   "PF3_TPH_REQ_DEVICE_SPEC_VFCOMM_CS2_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_acs_cap_enable_hwtcl                           =   "PF0_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_acs_cap_enable_hwtcl                           =   "PF1_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_acs_cap_enable_hwtcl                           =   "PF2_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_acs_cap_enable_hwtcl                           =   "PF3_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_exvf_acs_cap_enable_hwtcl                      =   "PF0_EXVF_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_exvf_acs_cap_enable_hwtcl                      =   "PF1_EXVF_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_exvf_acs_cap_enable_hwtcl                      =   "PF2_EXVF_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_exvf_acs_cap_enable_hwtcl                      =   "PF3_EXVF_ACS_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_acs_cap_acs_src_valid_hwtcl                    =   "PF0_ACS_CAP_ACS_SRC_VALID_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_acs_cap_acs_src_valid_hwtcl                    =   "PF1_ACS_CAP_ACS_SRC_VALID_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_acs_cap_acs_src_valid_hwtcl                    =   "PF2_ACS_CAP_ACS_SRC_VALID_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_acs_cap_acs_src_valid_hwtcl                    =   "PF3_ACS_CAP_ACS_SRC_VALID_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_acs_cap_acs_at_block_hwtcl                     =   "PF0_ACS_CAP_ACS_AT_BLOCK_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_acs_cap_acs_at_block_hwtcl                     =   "PF1_ACS_CAP_ACS_AT_BLOCK_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_acs_cap_acs_at_block_hwtcl                     =   "PF2_ACS_CAP_ACS_AT_BLOCK_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_acs_cap_acs_at_block_hwtcl                     =   "PF3_ACS_CAP_ACS_AT_BLOCK_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_acs_cap_acs_p2p_req_redirect_hwtcl             =   "PF0_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_acs_cap_acs_p2p_req_redirect_hwtcl             =   "PF1_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_acs_cap_acs_p2p_req_redirect_hwtcl             =   "PF2_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_acs_cap_acs_p2p_req_redirect_hwtcl             =   "PF3_ACS_CAP_ACS_P2P_REQ_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_acs_cap_acs_p2p_cpl_redirect_hwtcl             =   "PF0_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_acs_cap_acs_p2p_cpl_redirect_hwtcl             =   "PF1_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_acs_cap_acs_p2p_cpl_redirect_hwtcl             =   "PF2_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_acs_cap_acs_p2p_cpl_redirect_hwtcl             =   "PF3_ACS_CAP_ACS_P2P_CPL_REDIRECT_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_acs_cap_acs_usp_forwarding_hwtcl               =   "PF0_ACS_CAP_ACS_USP_FORWARDING_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_acs_cap_acs_usp_forwarding_hwtcl               =   "PF1_ACS_CAP_ACS_USP_FORWARDING_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_acs_cap_acs_usp_forwarding_hwtcl               =   "PF2_ACS_CAP_ACS_USP_FORWARDING_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_acs_cap_acs_usp_forwarding_hwtcl               =   "PF3_ACS_CAP_ACS_USP_FORWARDING_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_acs_cap_acs_p2p_egress_control_hwtcl           =   "PF0_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_acs_cap_acs_p2p_egress_control_hwtcl           =   "PF1_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_acs_cap_acs_p2p_egress_control_hwtcl           =   "PF2_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_acs_cap_acs_p2p_egress_control_hwtcl           =   "PF3_ACS_CAP_ACS_P2P_EGRESS_CONTROL_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_acs_cap_acs_egress_ctrl_size_hwtcl             =   8,
   parameter sm_hssi_pcie_ctl_x8_pf1_acs_cap_acs_egress_ctrl_size_hwtcl             =   8,
   parameter sm_hssi_pcie_ctl_x8_pf2_acs_cap_acs_egress_ctrl_size_hwtcl             =   8,
   parameter sm_hssi_pcie_ctl_x8_pf3_acs_cap_acs_egress_ctrl_size_hwtcl             =   8,
   parameter sm_hssi_pcie_ctl_x8_pf0_acs_cap_acs_direct_translated_p2p_hwtcl        =   "PF0_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_acs_cap_acs_direct_translated_p2p_hwtcl        =   "PF1_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_acs_cap_acs_direct_translated_p2p_hwtcl        =   "PF2_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_acs_cap_acs_direct_translated_p2p_hwtcl        =   "PF3_ACS_CAP_ACS_DIRECT_TRANSLATED_P2P_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_pcie_cap_ext_tag_en_hwtcl                      =   "TRUE",
   parameter sm_hssi_pcie_ctl_x8_pf1_pcie_cap_ext_tag_en_hwtcl                      =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_pcie_cap_ext_tag_en_hwtcl                      =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_pcie_cap_ext_tag_en_hwtcl                      =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_pcie_cap_flr_cap_hwtcl                         =   "PF0_PCIE_CAP_FLR_CAP_NOT_CAPABLE",
   parameter sm_hssi_pcie_ctl_x8_pf1_pcie_cap_flr_cap_hwtcl                         =   "PF1_PCIE_CAP_FLR_CAP_NOT_CAPABLE",
   parameter sm_hssi_pcie_ctl_x8_pf2_pcie_cap_flr_cap_hwtcl                         =   "PF2_PCIE_CAP_FLR_CAP_NOT_CAPABLE",
   parameter sm_hssi_pcie_ctl_x8_pf3_pcie_cap_flr_cap_hwtcl                         =   "PF3_PCIE_CAP_FLR_CAP_NOT_CAPABLE",
   parameter sm_hssi_pcie_ctl_x8_pf0_pcie_cap_port_num_hwtcl                        =   1,
   parameter sm_hssi_pcie_ctl_x8_pf1_pcie_cap_port_num_hwtcl                        =   1,
   parameter sm_hssi_pcie_ctl_x8_pf2_pcie_cap_port_num_hwtcl                        =   1,
   parameter sm_hssi_pcie_ctl_x8_pf3_pcie_cap_port_num_hwtcl                        =   1,
   parameter sm_hssi_pcie_ctl_x8_pf0_pcie_cap_slot_clk_config_hwtcl                 =   "TRUE",
   parameter sm_hssi_pcie_ctl_x8_pf1_pcie_cap_slot_clk_config_hwtcl                 =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_pcie_cap_slot_clk_config_hwtcl                 =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_pcie_cap_slot_clk_config_hwtcl                 =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_msi_enable_hwtcl                               =   "PF0_MSI_ENABLE_ENABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_msi_enable_hwtcl                               =   "PF1_MSI_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_msi_enable_hwtcl                               =   "PF2_MSI_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_msi_enable_hwtcl                               =   "PF3_MSI_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_msi_ext_data_cap_hwtcl                     =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_msi_ext_data_cap_hwtcl                     =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_msi_ext_data_cap_hwtcl                     =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_msi_ext_data_cap_hwtcl                     =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_msi_64_bit_addr_cap_hwtcl                  =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_msi_64_bit_addr_cap_hwtcl                  =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_msi_64_bit_addr_cap_hwtcl                  =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_msi_64_bit_addr_cap_hwtcl                  =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_msi_multiple_msg_cap_hwtcl                 =   "PF0_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1",
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_msi_multiple_msg_cap_hwtcl                 =   "PF1_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1",
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_msi_multiple_msg_cap_hwtcl                 =   "PF2_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1",
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_msi_multiple_msg_cap_hwtcl                 =   "PF3_PCI_MSI_MULTIPLE_MSG_CAP_MSI_VEC_1",
   parameter sm_hssi_pcie_ctl_x8_pf0_msix_enable_hwtcl                              =   "PF0_MSIX_ENABLE_ENABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_msix_enable_hwtcl                              =   "PF1_MSIX_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_msix_enable_hwtcl                              =   "PF2_MSIX_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_msix_enable_hwtcl                              =   "PF3_MSIX_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_msix_table_size_hwtcl                      =   3,
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_msix_table_size_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_msix_table_size_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_msix_table_size_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_msix_table_offset_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_msix_table_offset_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_msix_table_offset_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_msix_table_offset_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_msix_bir_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_msix_bir_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_msix_bir_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_msix_bir_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_msix_pba_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_msix_pba_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_msix_pba_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_msix_pba_hwtcl                             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_msix_pba_offset_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_msix_pba_offset_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_msix_pba_offset_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_msix_pba_offset_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_msix_table_size_vfcomm_cs2_hwtcl           =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_msix_table_size_vfcomm_cs2_hwtcl           =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_msix_table_size_vfcomm_cs2_hwtcl           =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_msix_table_size_vfcomm_cs2_hwtcl           =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_exvf_msix_cap_enable_hwtcl                     =   "PF0_EXVF_MSIX_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_exvf_msix_cap_enable_hwtcl                     =   "PF1_EXVF_MSIX_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_exvf_msix_cap_enable_hwtcl                     =   "PF2_EXVF_MSIX_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_exvf_msix_cap_enable_hwtcl                     =   "PF3_EXVF_MSIX_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_exvf_msix_tablesize_pf0_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msix_tablesize_pf1_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msix_tablesize_pf2_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msix_tablesize_pf3_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixtable_offset_pf0_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixtable_offset_pf1_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixtable_offset_pf2_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixtable_offset_pf3_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixtable_bir_pf0_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixtable_bir_pf1_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixtable_bir_pf2_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixtable_bir_pf3_hwtcl                       =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixpba_offset_pf0_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixpba_offset_pf1_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixpba_offset_pf2_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixpba_offset_pf3_hwtcl                      =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixpba_bir_pf0_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixpba_bir_pf1_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixpba_bir_pf2_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x8_exvf_msixpba_bir_pf3_hwtcl                         =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pcie_slot_imp_hwtcl                            =   "PF0_PCIE_SLOT_IMP_NOT_IMPLEMENTED",
   parameter sm_hssi_pcie_ctl_x8_pf0_pcie_cap_slot_power_limit_scale_hwtcl          =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pcie_cap_slot_power_limit_value_hwtcl          =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pcie_cap_phy_slot_num_hwtcl                    =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pcie_cap_hot_plug_capable_hwtcl                =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_pcie_cap_ep_l0s_accpt_latency_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pcie_cap_ep_l1_accpt_latency_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pcie_cap_ep_l0s_accpt_latency_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pcie_cap_ep_l1_accpt_latency_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pcie_cap_ep_l0s_accpt_latency_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pcie_cap_ep_l1_accpt_latency_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pcie_cap_ep_l0s_accpt_latency_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pcie_cap_ep_l1_accpt_latency_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pcie_cap_l0s_exit_latency_commclk_dis_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pcie_cap_l1_exit_latency_commclk_dis_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pcie_cap_l0s_exit_latency_commclk_dis_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pcie_cap_l1_exit_latency_commclk_dis_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pcie_cap_l0s_exit_latency_commclk_dis_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pcie_cap_l1_exit_latency_commclk_dis_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pcie_cap_l0s_exit_latency_commclk_dis_hwtcl            =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pcie_cap_l1_exit_latency_commclk_dis_hwtcl             =   0,
   parameter sm_hssi_pcie_ctl_x8_aspm_support_hwtcl				   =    "ASPM_SUPPORT_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_dbi_ro_wr_disable_hwtcl                           =   "DBI_RO_WR_DISABLE_DISABLE",
   parameter sm_hssi_pcie_ctl_x8_pf0_gen3_eq_pset_req_vec_hwtcl                     =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_gen3_eq_pset_req_vec_atg4_hwtcl                =   0,   
   parameter sm_hssi_pcie_ctl_x8_pf0_prs_ext_cap_enable_hwtcl                       =   "PF0_PRS_EXT_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_prs_ext_cap_enable_hwtcl                       =   "PF1_PRS_EXT_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_prs_ext_cap_enable_hwtcl                       =   "PF2_PRS_EXT_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_prs_ext_cap_enable_hwtcl                       =   "PF3_PRS_EXT_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_prs_ext_cap_outstanding_capacity_hwtcl         =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_prs_ext_cap_outstanding_capacity_hwtcl         =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_prs_ext_cap_outstanding_capacity_hwtcl         =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_prs_ext_cap_outstanding_capacity_hwtcl         =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_sn_cap_enable_hwtcl                            =   "PF0_SN_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_sn_cap_enable_hwtcl                            =   "PF1_SN_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_sn_cap_enable_hwtcl                            =   "PF2_SN_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_sn_cap_enable_hwtcl                            =   "PF3_SN_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_sn_ser_num_reg_1_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_sn_ser_num_reg_1_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_sn_ser_num_reg_1_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_sn_ser_num_reg_1_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_sn_ser_num_reg_2_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_sn_ser_num_reg_2_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_sn_ser_num_reg_2_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_sn_ser_num_reg_2_dw_hwtcl                      =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pasid_cap_enable_hwtcl                         =   "PF0_PASID_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_pasid_cap_enable_hwtcl                         =   "PF1_PASID_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_pasid_cap_enable_hwtcl                         =   "PF2_PASID_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_pasid_cap_enable_hwtcl                         =   "PF3_PASID_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_pasid_cap_execute_permission_supported_hwtcl   =   "PF0_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_pasid_cap_execute_permission_supported_hwtcl   =   "PF1_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_pasid_cap_execute_permission_supported_hwtcl   =   "PF2_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_pasid_cap_execute_permission_supported_hwtcl   =   "PF3_PASID_CAP_EXECUTE_PERMISSION_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_pasid_cap_max_pasid_width_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pasid_cap_max_pasid_width_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pasid_cap_max_pasid_width_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pasid_cap_max_pasid_width_hwtcl                =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pasid_cap_privileged_mode_supported_hwtcl      =   "PF0_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_pasid_cap_privileged_mode_supported_hwtcl      =   "PF1_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_pasid_cap_privileged_mode_supported_hwtcl      =   "PF2_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_pasid_cap_privileged_mode_supported_hwtcl      =   "PF3_PASID_CAP_PRIVILEGED_MODE_SUPPORTED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_ltr_cap_enable_hwtcl                           =   "PF0_LTR_CAP_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_virtual_ptm_hwtcl                                  =   "PTM_ENABLE_DISABLE",
   parameter sm_hssi_pcie_ctl_x8_ptm_autoupdate_hwtcl                               =   "PTM_AUTOUPDATE_AUTOUPDATE_DISABLE",
   parameter sm_hssi_pcie_ctl_x8_pf1_enable_hwtcl                                   =   "PF1_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_enable_hwtcl                                   =   "PF2_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_enable_hwtcl                                   =   "PF3_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_enable_hwtcl                             =   "PF0_SRIOV_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_enable_hwtcl                             =   "PF1_SRIOV_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_enable_hwtcl                             =   "PF2_SRIOV_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_enable_hwtcl                             =   "PF3_SRIOV_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_cap_sup_page_size_hwtcl                  =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_cap_sup_page_size_hwtcl                  =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_cap_sup_page_size_hwtcl                  =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_cap_sup_page_size_hwtcl                  =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_bar0_enabled_hwtcl                   =   "PF0_PCI_TYPE0_BAR0_ENABLED_ENABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_bar1_enabled_hwtcl                   =   "PF0_PCI_TYPE0_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_bar2_enabled_hwtcl                   =   "PF0_PCI_TYPE0_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_bar3_enabled_hwtcl                   =   "PF0_PCI_TYPE0_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_bar4_enabled_hwtcl                   =   "PF0_PCI_TYPE0_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_bar5_enabled_hwtcl                   =   "PF0_PCI_TYPE0_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_bar0_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_bar1_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_bar2_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_bar3_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_bar4_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_pci_type0_bar5_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_bar0_prefetch_hwtcl                            =   "TRUE",
   parameter sm_hssi_pcie_ctl_x8_pf0_bar1_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_bar2_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_bar3_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_bar4_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_bar5_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_rom_bar_enable_hwtcl                           =   "PF0_ROM_BAR_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_rom_bar_enabled_hwtcl                          =   "PF0_ROM_BAR_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_rom_mask_hwtcl                                 =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_rp_rom_bar_enabled_hwtcl                       =   "PF0_RP_ROM_BAR_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_rp_rom_mask_hwtcl                              =   0,
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar0_enabled_hwtcl                    =   "PF0_SRIOV_VF_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar1_enabled_hwtcl                    =   "PF0_SRIOV_VF_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar2_enabled_hwtcl                    =   "PF0_SRIOV_VF_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar3_enabled_hwtcl                    =   "PF0_SRIOV_VF_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar4_enabled_hwtcl                    =   "PF0_SRIOV_VF_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar5_enabled_hwtcl                    =   "PF0_SRIOV_VF_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar0_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar1_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar2_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar3_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar4_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar5_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar0_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar1_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar2_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar3_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar4_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar5_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf0_bar0_type_hwtcl                                =   "PF0_BAR0_TYPE_BAR_MEM64",
   parameter sm_hssi_pcie_ctl_x8_pf0_bar2_type_hwtcl                                =   "PF0_BAR2_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf0_bar4_type_hwtcl                                =   "PF0_BAR4_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar0_type_hwtcl                       =   "PF0_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar2_type_hwtcl                       =   "PF0_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf0_sriov_vf_bar4_type_hwtcl                       =   "PF0_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_bar0_enabled_hwtcl                   =   "PF1_PCI_TYPE0_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_bar1_enabled_hwtcl                   =   "PF1_PCI_TYPE0_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_bar2_enabled_hwtcl                   =   "PF1_PCI_TYPE0_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_bar3_enabled_hwtcl                   =   "PF1_PCI_TYPE0_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_bar4_enabled_hwtcl                   =   "PF1_PCI_TYPE0_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_bar5_enabled_hwtcl                   =   "PF1_PCI_TYPE0_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_bar0_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_bar1_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_bar2_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_bar3_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_bar4_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_pci_type0_bar5_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_bar0_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_bar1_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_bar2_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_bar3_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_bar4_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_bar5_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_rom_bar_enable_hwtcl                           =   "PF1_ROM_BAR_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_rom_bar_enabled_hwtcl                          =   "PF1_ROM_BAR_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_rom_mask_hwtcl                                 =   0,
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar0_enabled_hwtcl                    =   "PF1_SRIOV_VF_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar1_enabled_hwtcl                    =   "PF1_SRIOV_VF_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar2_enabled_hwtcl                    =   "PF1_SRIOV_VF_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar3_enabled_hwtcl                    =   "PF1_SRIOV_VF_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar4_enabled_hwtcl                    =   "PF1_SRIOV_VF_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar5_enabled_hwtcl                    =   "PF1_SRIOV_VF_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar0_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar1_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar2_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar3_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar4_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar5_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar0_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar1_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar2_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar3_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar4_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar5_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf1_bar0_type_hwtcl                                =   "PF1_BAR0_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf1_bar2_type_hwtcl                                =   "PF1_BAR2_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf1_bar4_type_hwtcl                                =   "PF1_BAR4_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar0_type_hwtcl                       =   "PF1_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar2_type_hwtcl                       =   "PF1_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf1_sriov_vf_bar4_type_hwtcl                       =   "PF1_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_bar0_enabled_hwtcl                   =   "PF2_PCI_TYPE0_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_bar1_enabled_hwtcl                   =   "PF2_PCI_TYPE0_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_bar2_enabled_hwtcl                   =   "PF2_PCI_TYPE0_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_bar3_enabled_hwtcl                   =   "PF2_PCI_TYPE0_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_bar4_enabled_hwtcl                   =   "PF2_PCI_TYPE0_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_bar5_enabled_hwtcl                   =   "PF2_PCI_TYPE0_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_bar0_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_bar1_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_bar2_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_bar3_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_bar4_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_pci_type0_bar5_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_bar0_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_bar1_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_bar2_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_bar3_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_bar4_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_bar5_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_rom_bar_enable_hwtcl                           =   "PF2_ROM_BAR_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_rom_bar_enabled_hwtcl                          =   "PF2_ROM_BAR_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_rom_mask_hwtcl                                 =   0,
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar0_enabled_hwtcl                    =   "PF2_SRIOV_VF_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar1_enabled_hwtcl                    =   "PF2_SRIOV_VF_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar2_enabled_hwtcl                    =   "PF2_SRIOV_VF_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar3_enabled_hwtcl                    =   "PF2_SRIOV_VF_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar4_enabled_hwtcl                    =   "PF2_SRIOV_VF_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar5_enabled_hwtcl                    =   "PF2_SRIOV_VF_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar0_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar1_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar2_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar3_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar4_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar5_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar0_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar1_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar2_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar3_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar4_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar5_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf2_bar0_type_hwtcl                                =   "PF2_BAR0_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf2_bar2_type_hwtcl                                =   "PF2_BAR2_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf2_bar4_type_hwtcl                                =   "PF2_BAR4_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar0_type_hwtcl                       =   "PF2_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar2_type_hwtcl                       =   "PF2_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf2_sriov_vf_bar4_type_hwtcl                       =   "PF2_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_bar0_enabled_hwtcl                   =   "PF3_PCI_TYPE0_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_bar1_enabled_hwtcl                   =   "PF3_PCI_TYPE0_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_bar2_enabled_hwtcl                   =   "PF3_PCI_TYPE0_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_bar3_enabled_hwtcl                   =   "PF3_PCI_TYPE0_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_bar4_enabled_hwtcl                   =   "PF3_PCI_TYPE0_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_bar5_enabled_hwtcl                   =   "PF3_PCI_TYPE0_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_bar0_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_bar1_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_bar2_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_bar3_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_bar4_mask_31_1_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_pci_type0_bar5_mask_31_0_hwtcl		    =	32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_bar0_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_bar1_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_bar2_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_bar3_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_bar4_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_bar5_prefetch_hwtcl                            =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_rom_bar_enable_hwtcl                           =   "PF3_ROM_BAR_ENABLE_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_rom_bar_enabled_hwtcl                          =   "PF3_ROM_BAR_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_rom_mask_hwtcl                                 =   0,
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar0_enabled_hwtcl                    =   "PF3_SRIOV_VF_BAR0_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar1_enabled_hwtcl                    =   "PF3_SRIOV_VF_BAR1_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar2_enabled_hwtcl                    =   "PF3_SRIOV_VF_BAR2_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar3_enabled_hwtcl                    =   "PF3_SRIOV_VF_BAR3_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar4_enabled_hwtcl                    =   "PF3_SRIOV_VF_BAR4_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar5_enabled_hwtcl                    =   "PF3_SRIOV_VF_BAR5_ENABLED_DISABLED",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar0_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar1_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar2_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar3_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar4_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar5_mask_hwtcl                       =   32'h0,
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar0_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar1_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar2_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar3_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar4_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar5_prefetch_hwtcl                   =   "FALSE",
   parameter sm_hssi_pcie_ctl_x8_pf3_bar0_type_hwtcl                                =   "PF3_BAR0_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf3_bar2_type_hwtcl                                =   "PF3_BAR2_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf3_bar4_type_hwtcl                                =   "PF3_BAR4_TYPE_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar0_type_hwtcl                       =   "PF3_SRIOV_VF_BAR0_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar2_type_hwtcl                       =   "PF3_SRIOV_VF_BAR2_TYPE_SRIOV_VF_BAR_MEM32",
   parameter sm_hssi_pcie_ctl_x8_pf3_sriov_vf_bar4_type_hwtcl                       =   "PF3_SRIOV_VF_BAR4_TYPE_SRIOV_VF_BAR_MEM32",
   parameter core8_ch0_xcvr_rx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch1_xcvr_rx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch2_xcvr_rx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch3_xcvr_rx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch4_xcvr_rx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch5_xcvr_rx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch6_xcvr_rx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch7_xcvr_rx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch0_xcvr_tx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch1_xcvr_tx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch2_xcvr_tx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch3_xcvr_tx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch4_xcvr_tx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch5_xcvr_tx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch6_xcvr_tx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch7_xcvr_tx_protocol_hint_hwtcl                                  =   "PCIE_GEN3",
   parameter core8_ch0_sim_mode_hwtcl                                               =   "DISABLE",
   parameter core8_ch1_sim_mode_hwtcl                                               =   "DISABLE",
   parameter core8_ch2_sim_mode_hwtcl                                               =   "DISABLE",
   parameter core8_ch3_sim_mode_hwtcl                                               =   "DISABLE",
   parameter core8_ch4_sim_mode_hwtcl                                               =   "DISABLE",
   parameter core8_ch5_sim_mode_hwtcl                                               =   "DISABLE",
   parameter core8_ch6_sim_mode_hwtcl                                               =   "DISABLE",
   parameter core8_ch7_sim_mode_hwtcl                                               =   "DISABLE",

   parameter   sm_hssi_pcie_ctl_x8_num_of_lanes_hwtcl = "NUM_OF_LANES_NUM_1",
   parameter   core8_empty_width_integer_hwtcl  =    3, //new: tdata_width=256, empty_width=3 .if tdata_width=128, empty_width=2
   parameter   core8_func_mode_hwtcl = "Enable",
   parameter   core8_pf0_bar0_address_width_hwtcl = 16,
   parameter   core8_pf0_bar1_address_width_hwtcl = 16,
   parameter   core8_pf0_bar2_address_width_hwtcl = 16,
   parameter   core8_pf0_bar3_address_width_hwtcl = 16,
   parameter   core8_pf0_bar4_address_width_hwtcl = 16,
   parameter   core8_pf0_bar5_address_width_hwtcl = 16

)(
   // Clocks
   (* tile_ip_find_net *) input                        refclk0,
//   (* tile_ip_find_net *) input                        refclk0_n,
   (* tile_ip_find_net *) input                        refclk1,
//   (* tile_ip_find_net *) input                        refclk1_n,


   output                                              p0_coreclkout_hip,
   output                                              p1_coreclkout_hip,

// x0x1, x1x0
   input  rx_n_in0,
   input  rx_p_in0,
   output tx_n_out0,
   output tx_p_out0,
// x0x2, x1x1, x2x0
   input  rx_n_in1,
   input  rx_p_in1,
   output tx_n_out1,
   output tx_p_out1,
// x1x2, x2x1 
   input  rx_n_in2,
   input  rx_p_in2,
   output tx_n_out2,
   output tx_p_out2,
// x0x4, x2x2, x4x0
   input  rx_n_in3,
   input  rx_p_in3,
   output tx_n_out3,
   output tx_p_out3,
// x1x4, x4x1
// x2x4, x4x2
// x0x8, x4x4


   input                                               p0_axi_lite_clk,
   input                                               p0_axi_st_clk,

   input                                               p1_axi_lite_clk,
   input                                               p1_axi_st_clk,


   // Reset
   input                                               p0_pin_perst_n_i,
   input                                               p0_pin_perst_n_1_i,   
   input                                               p1_pin_perst_n_i,
   input                                               ninit_done,

   input                                               i_gpio_perst0_n,
   input                                               i_gpio_perst1_n,

   output                                              p0_pin_perst_n,
   output                                              p1_pin_perst_n,

   output                                              p0_reset_status_n,
   output                                              p1_reset_status_n,

   input                                               p0_axi_st_areset_n,
   input                                               p0_axi_lite_areset_n,
   input                                               p1_axi_st_areset_n,
   input                                               p1_axi_lite_areset_n,

   output                                              p0_rst_req_o,
   input                                               p0_rst_rdy_i,
   output                                              p1_rst_req_o,
   input                                               p1_rst_rdy_i,

   input   [2:0]                                       p0_rx_tuser_halt,
   input   [2:0]                                       p1_rx_tuser_halt,


   output                                              p0_st_rx_tvalid_o,
   input                                               p0_st_rx_tready_i,
   output  [core16_tdata_width_integer_hwtcl-1:0]      p0_st_rx_tdata_o,
   output  [(core16_tdata_width_integer_hwtcl/8)-1:0]      p0_st_rx_tkeep_o,
   output                                              p0_st_rx_tlast_o,
   output                                              p0_st_rx_tuser_last_segment,
   output                                              p1_st_rx_tvalid_o,
   input                                               p1_st_rx_tready_i,
   output  [core8_tdata_width_integer_hwtcl-1:0]      p1_st_rx_tdata_o,
   output  [(core8_tdata_width_integer_hwtcl/8)-1:0]  p1_st_rx_tkeep_o,
   output                                              p1_st_rx_tlast_o,
   output                                              p1_st_rx_tuser_last_segment,


   output                                              p0_pcie_pld_rx_fbk_tready,
   output                                              p1_pcie_pld_rx_fbk_tready,


   input                                               p0_st_tx_tvalid_i,
   output                                              p0_st_tx_tready_o,
   input   [core16_tdata_width_integer_hwtcl-1:0]      p0_st_tx_tdata_i,
   input   [(core16_tdata_width_integer_hwtcl/8)-1:0]      p0_st_tx_tkeep_i,
   input                                               p0_st_tx_tlast_i,
   input                                          p0_st_tx_tuser_last_segment,
   input                                               p1_st_tx_tvalid_i,
   output                                              p1_st_tx_tready_o,
   input   [core8_tdata_width_integer_hwtcl-1:0]       p1_st_tx_tdata_i,
   input   [(core8_tdata_width_integer_hwtcl/8)-1:0]   p1_st_tx_tkeep_i,
   input                                               p1_st_tx_tlast_i,
   input                                               p1_st_tx_tuser_last_segment,


   output                                              p0_st_txcrdt_tvalid_o,
   output  [18:0]                                      p0_st_txcrdt_tvdata_o,
   input					       p0_st_txcrdt_tldrdy_i,
   output                                              p1_st_txcrdt_tvalid_o,
   output  [18:0]                                      p1_st_txcrdt_tvdata_o,
   input					       p1_st_txcrdt_tldrdy_i,


   //p0 _int_ ports
   input  [7:0]                                        p0_app_int_i,
   output [7:0]                                        p0_app_int_ready_o,
   output                                              p0_int_status_o,
   input  [7:0]                                        p1_app_int_i,
   output [7:0]                                        p1_app_int_ready_o,
   output                                              p1_int_status_o,


   //p0 msi ports (EP only)
   //soft logic to allign with 32bit data width
   input   [2:0]                                       p0_msi_pnd_func_i,
   input   [1:0]                                       p0_msi_pnd_addr_i,
   input   [7:0]                                       p0_msi_pnd_byte_i,    //need soft logic to convert 32 bit data to 8bit bytedata and 2bit addr
   input   [10:0]                                      p0_msi_pnd_vf_num_i,
   input                                               p0_msi_pnd_vfa_i,
   output                                              p0_msi_pnd_ready_o,

   //p0 msi ports (EP only)
   //soft logic to allign with 32bit data width
   input   [2:0]                                       p1_msi_pnd_func_i,
   input   [1:0]                                       p1_msi_pnd_addr_i,
   input   [7:0]                                       p1_msi_pnd_byte_i,    //need soft logic to convert 32 bit data to 8bit bytedata and 2bit addr
   input   [10:0]                                      p1_msi_pnd_vf_num_i,
   input                                               p1_msi_pnd_vfa_i,
   output                                              p1_msi_pnd_ready_o,


   //export output
   //soft logic needs to control input
   input                                               p0_app_xfer_pending_i,
   input                                               p0_apps_ready_entr_l23_i,
   input   [7:0]                                       p0_apps_pm_xmt_pme_i,
   input                                               p0_app_init_rst_i,
   input                                               p0_apps_pm_xmt_turnoff_i,
   output  [9:0]                                       p0_apps_pm_ready_o,
   input                                               p1_app_xfer_pending_i,
   input                                               p1_apps_ready_entr_l23_i,
   input   [7:0]                                       p1_apps_pm_xmt_pme_i,
   input                                               p1_app_init_rst_i,
   input                                               p1_apps_pm_xmt_turnoff_i,
   output  [9:0]                                       p1_apps_pm_ready_o,

   output                                              p0_surprise_down_err_o,
   output                                              p0_link_up_o,
   output                                              p0_dl_up_o,
   output  [2:0]                                       p0_pm_state_o,
   output  [31:0]                                      p0_pm_dstate_o,
   output  [5:0]                                       p0_ltssm_state_o,
   input   [7:0]                                       p0_pld_gp_status_i,
   output  [7:0]                                       p0_pld_gp_ctrl_o,
   input   [7:0]                                       p0_app_req_retry_en_i, //KAHUAT_EDIT
   output                                              p0_app_retry_en_ready_o, //KLAI4 EDIT
   input                                               p0_sys_aux_pwr_det_i,
   output                                              p1_surprise_down_err_o,
   output                                              p1_link_up_o,
   output                                              p1_dl_up_o,
   output  [2:0]                                       p1_pm_state_o,
   output  [31:0]                                      p1_pm_dstate_o,
   output  [5:0]                                       p1_ltssm_state_o,
   input   [7:0]                                       p1_pld_gp_status_i,
   output  [7:0]                                       p1_pld_gp_ctrl_o,
   input   [7:0]                                       p1_app_req_retry_en_i, //KAHUAT_EDIT
   output                                              p1_app_retry_en_ready_o, //KLAI4 EDIT
   input                                               p1_sys_aux_pwr_det_i,


   //p0 err_ ports
   //requires 5 cycles
   //need soft logic to ease user effort
   input                                               p0_app_err_valid_i,
   input   [2:0]                                       p0_app_err_func_num_i,
   input   [31:0]                                      p0_app_err_hdr_i,        //add soft logic to convert hdr+prfx to 5 cycles of 32bit
   input   [13:0]                                      p0_app_err_info_i,
   output                                              p0_app_err_ready_o,
   output                                              p0_serr_out_o,
   output                                              p0_hip_enter_err_mode_o,

   //p1 err_ ports
   //requires 5 cycles
   //need soft logic to ease user effort
   input                                               p1_app_err_valid_i,
   input   [2:0]                                       p1_app_err_func_num_i,
   input   [31:0]                                      p1_app_err_hdr_i,        //add soft logic to convert hdr+prfx to 5 cycles of 32bit
   input   [13:0]                                      p1_app_err_info_i,
   output                                              p1_app_err_ready_o,
   output                                              p1_serr_out_o,
   output                                              p1_hip_enter_err_mode_o,


   //confirm whether or not to support
   //p0 hot plug ports
   //terminate in QSYS
   input                                               p0_sys_pwr_fault_det_i,
   input                                               p0_sys_mrl_sensor_state_i,
   input                                               p0_sys_mrl_sensor_chged_i,
   input                                               p0_sys_pre_det_state_i,
   input                                               p0_sys_pre_det_chged_i,
   input                                               p0_sys_cmd_cpled_int_i,
   input                                               p0_sys_atten_button_pressed_i,
   input                                               p0_sys_eml_interlock_engaged_i,
   output  [7:0]                                       p0_sys_hotplug_ready_o,

   //p1 hot plug ports
   input                                               p1_sys_pwr_fault_det_i,
   input                                               p1_sys_mrl_sensor_state_i,
   input                                               p1_sys_mrl_sensor_chged_i,
   input                                               p1_sys_pre_det_state_i,
   input                                               p1_sys_pre_det_chged_i,
   input                                               p1_sys_cmd_cpled_int_i,
   input                                               p1_sys_atten_button_pressed_i,
   input                                               p1_sys_eml_interlock_engaged_i,
   output  [7:0]                                       p1_sys_hotplug_ready_o,


   output [7:0]                                        p0_flr_rcvd_pf_o,
   output                                              p0_flr_rcvd_vf_o,
   output [2:0]                                        p0_flr_rcvd_pf_num_o,
   output [10:0]                                       p0_flr_rcvd_vf_num_o,
   input  [7:0]                                        p0_flr_cmpl_pf_i,
   input                                               p0_flr_cmpl_vf_i,
   input  [2:0]                                        p0_flr_cmpl_pf_num_i,
   input  [10:0]                                       p0_flr_cmpl_vf_num_i,
   output                                              p0_flr_cmpl_tready_o,
   output [7:0]                                        p1_flr_rcvd_pf_o,
   output                                              p1_flr_rcvd_vf_o,
   output [2:0]                                        p1_flr_rcvd_pf_num_o,
   output [10:0]                                       p1_flr_rcvd_vf_num_o,
   input  [7:0]                                        p1_flr_cmpl_pf_i,
   input                                               p1_flr_cmpl_vf_i,
   input  [2:0]                                        p1_flr_cmpl_pf_num_i,
   input  [10:0]                                       p1_flr_cmpl_vf_num_i,
   output                                              p1_flr_cmpl_tready_o,

   output                                              p0_virtio_pcicfgreq_tvalid_o,
   output  [95:0]                                      p0_virtio_pcicfgreq_tdata_o,
   input                                               p0_virtio_pcicfgcmpl_tvalid_i,
   input   [31:0]                                      p0_virtio_pcicfgcmpl_tdata_i,
   output                                              p1_virtio_pcicfgreq_tvalid_o,
   output  [95:0]                                      p1_virtio_pcicfgreq_tdata_o,
   input                                               p1_virtio_pcicfgcmpl_tvalid_i,
   input   [31:0]                                      p1_virtio_pcicfgcmpl_tdata_i,



   output  [4:0]                                       p0_tl_cfg_add_o,
   output  [2:0]                                       p0_tl_cfg_func_o,
   output  [15:0]                                      p0_tl_cfg_ctl_o,
   output                                              p0_dl_timer_update_o,
   output  [4:0]                                       p1_tl_cfg_add_o,
   output  [2:0]                                       p1_tl_cfg_func_o,
   output  [15:0]                                      p1_tl_cfg_ctl_o,
   output                                              p1_dl_timer_update_o,

   // VirtIO PCI Config Access Interface
   output           p0_virtio_pcicfg_vfaccess_o,
   output [10:0]    p0_virtio_pcicfg_vfnum_o,
   output [ 2:0]    p0_virtio_pcicfg_pfnum_o,
   output [ 7:0]    p0_virtio_pcicfg_bar_o,
   output [31:0]    p0_virtio_pcicfg_length_o,
   output [31:0]    p0_virtio_pcicfg_baroffset_o,
   output [31:0]    p0_virtio_pcicfg_cfgdata_o,
   output           p0_virtio_pcicfg_cfgwr_o,
   output           p0_virtio_pcicfg_cfgrd_o,

   input  [10:0]    p0_virtio_pcicfg_appvfnum_i,  // Application indicates for which VF offset.
   input  [ 2:0]    p0_virtio_pcicfg_apppfnum_i,  // Application indicates for which PF.
   input            p0_virtio_pcicfg_rdack_i,     // Application Read Data Ack to store config data.
   input  [ 3:0]    p0_virtio_pcicfg_rdbe_i,      // Application indicates which byte to store.
   input  [31:0]    p0_virtio_pcicfg_data_i,      // Data to be stored in config data registers.

   output           p1_virtio_pcicfg_vfaccess_o,
   output [10:0]    p1_virtio_pcicfg_vfnum_o,
   output [ 2:0]    p1_virtio_pcicfg_pfnum_o,
   output [ 7:0]    p1_virtio_pcicfg_bar_o,
   output [31:0]    p1_virtio_pcicfg_length_o,
   output [31:0]    p1_virtio_pcicfg_baroffset_o,
   output [31:0]    p1_virtio_pcicfg_cfgdata_o,
   output           p1_virtio_pcicfg_cfgwr_o,
   output           p1_virtio_pcicfg_cfgrd_o,

   input  [10:0]    p1_virtio_pcicfg_appvfnum_i,  // Application indicates for which VF offset.
   input  [ 2:0]    p1_virtio_pcicfg_apppfnum_i,  // Application indicates for which PF.
   input            p1_virtio_pcicfg_rdack_i,     // Application Read Data Ack to store config data.
   input  [ 3:0]    p1_virtio_pcicfg_rdbe_i,      // Application indicates which byte to store.
   input  [31:0]    p1_virtio_pcicfg_data_i,      // Data to be stored in config data registers.

// nwai: Should not exist:   output                                              p0_st_ciireq_tvalid_o,
// nwai: Should not exist:   input                                               p0_st_cciireq_tready_i,
   output  [67:0]                                      p0_st_ciireq_tdata_o,
   output  [67:0]                                      p1_st_ciireq_tdata_o,


   input                                               p0_st_cii_halt_i,
   output                                              p0_st_cii_req_o,
   input                                               p1_st_cii_halt_i,
   output                                              p1_st_cii_req_o,


// nwai: Should not exist:   input                                               p0_st_ciiresp_tvalid_i,
   input   [32:0]                                      p0_st_ciiresp_tdata_i,
   input   [32:0]                                      p1_st_ciiresp_tdata_i,


   //p0 vf_err_ ports
   input                                               p0_user_sent_vfnonfatalmsg_i,
   input   [2:0]                                       p0_user_vfnonfatalmsg_func_num_i,
   input   [10:0]                                      p0_user_vfnonfatalmsg_vfnum_i,
   output                                              p0_user_vfnonfatalmsg_ready_o, 
   output                                              p0_vf_err_ur_posted_s0_o,
   output                                              p0_vf_err_ca_postedreq_s0_o,
   output                                              p0_vf_err_poisonedwrreq_s0_o,
   output                                              p0_vf_err_poisonedcompl_s0_o,
   output  [2:0]                                       p0_vf_err_func_num_s0_o,
   output  [10:0]                                      p0_vf_err_vf_num_s0_o,
   output                                              p0_vf_err_ur_posted_s1_o,
   output                                              p0_vf_err_ca_postedreq_s1_o,
   output                                              p0_vf_err_poisonedwrreq_s1_o,
   output                                              p0_vf_err_poisonedcompl_s1_o,
   output  [2:0]                                       p0_vf_err_func_num_s1_o,
   output  [10:0]                                      p0_vf_err_vf_num_s1_o,
   output                                              p0_vf_err_overflow_o,

   //p1 vf_err_ ports
   input                                               p1_user_sent_vfnonfatalmsg_i,
   input   [2:0]                                       p1_user_vfnonfatalmsg_func_num_i,
   input   [10:0]                                      p1_user_vfnonfatalmsg_vfnum_i,
   output                                              p1_user_vfnonfatalmsg_ready_o, 
   output                                              p1_vf_err_ur_posted_s0_o,
   output                                              p1_vf_err_ca_postedreq_s0_o,
   output                                              p1_vf_err_poisonedwrreq_s0_o,
   output                                              p1_vf_err_poisonedcompl_s0_o,
   output  [2:0]                                       p1_vf_err_func_num_s0_o,
   output  [10:0]                                      p1_vf_err_vf_num_s0_o,
   output                                              p1_vf_err_ur_posted_s1_o,
   output                                              p1_vf_err_ca_postedreq_s1_o,
   output                                              p1_vf_err_poisonedwrreq_s1_o,
   output                                              p1_vf_err_poisonedcompl_s1_o,
   output  [2:0]                                       p1_vf_err_func_num_s1_o,
   output  [10:0]                                      p1_vf_err_vf_num_s1_o,
   output                                              p1_vf_err_overflow_o,


   output                                              p0_st_cplto_tvalid_o,
   output  [48:0]                                      p0_st_cplto_tdata_o,
   input					       p0_st_cplto_ready_i,
   output                                              p1_st_cplto_tvalid_o,
   output  [48:0]                                      p1_st_cplto_tdata_o,
   input					       p1_st_cplto_ready_i,


   input   [1:0]                                       p0_qhip_prs_event_i,
   input   [2:0]                                       p0_qhip_prs_event_func_i,
   input                                               p0_qhip_prs_event_valid_i,
   output                                              p0_qhip_prs_event_ready_o,
   input   [1:0]                                       p1_qhip_prs_event_i,
   input   [2:0]                                       p1_qhip_prs_event_func_i,
   input                                               p1_qhip_prs_event_valid_i,
   output                                              p1_qhip_prs_event_ready_o,


   //p0 test_ ports
   input                                               p0_test_in_i,
   output  [34:0]                                      p0_test_out_o,

   //p1 test_ ports
   input                                               p1_test_in_i,
   output  [69:0]                                      p1_test_out_o,


   //PTM
   input          				       p0_ptm_manual_update,      
   output         				       p0_ptm_context_valid,      
   output         				       p0_start_ptm_newclk_value, 
   output         				       p0_ptm_newclk_value,       
   output         				       p0_ptm_clock_correction,   
   input          				       p1_ptm_manual_update,      
   output         				       p1_ptm_context_valid,      
   output         				       p1_start_ptm_newclk_value, 
   output         				       p1_ptm_newclk_value,       
   output         				       p1_ptm_clock_correction,   

   // User AVMM ports
   //p0 user_avmm ports
   input					       p0_axi_lite_div2_clk,
   input                                               p0_hip_reconfig_clk,
   input   [23:0]                                      p0_hip_reconfig_address,
   input                                               p0_hip_reconfig_write,
   input   [31:0]                                      p0_hip_reconfig_writedata,
   input                                               p0_hip_reconfig_read,
   output                                              p0_hip_reconfig_readdatavalid,
   output  [31:0]                                      p0_hip_reconfig_readdata,
   output                                              p0_hip_reconfig_waitrequest,
   input   [3:0]                                       p0_hip_reconfig_byteen,
   output  [1:0]                                       p0_hip_reconfig_resp,

   //p1 user_avmm ports
   input					       p1_axi_lite_div2_clk,
   input                                               p1_hip_reconfig_clk,
   input   [23:0]                                      p1_hip_reconfig_address,
   input                                               p1_hip_reconfig_write,
   input   [31:0]                                      p1_hip_reconfig_writedata,
   input                                               p1_hip_reconfig_read,
   output                                              p1_hip_reconfig_readdatavalid,
   output  [31:0]                                      p1_hip_reconfig_readdata,
   output                                              p1_hip_reconfig_waitrequest,
   input   [3:0]                                       p1_hip_reconfig_byteen,
   output  [1:0]                                       p1_hip_reconfig_resp,
   
   output  [15:0]                                      p0_tlpbyp_tdata_o,
   output                                              p0_tlpbyp_tvalid_o,
				                                      
   input                                               p0_tlpbyp_ready_i,
   output  [15:0]                                      p1_tlpbyp_tdata_o,
   output                                              p1_tlpbyp_tvalid_o,                      

   input                                               p1_tlpbyp_ready_i,
   
   output 	[20:0]					p0_pciess_reconfig_address,
   output						p0_pciess_reconfig_write,
   output 	[31:0]					p0_pciess_reconfig_writedata,
   output						p0_pciess_reconfig_read,
   input  	[31:0]					p0_pciess_reconfig_readdata,
   input						p0_pciess_reconfig_readdatavalid,
   input						p0_pciess_reconfig_waitrequest,
   output 	[20:0]					p1_pciess_reconfig_address,
   output						p1_pciess_reconfig_write,
   output 	[31:0]					p1_pciess_reconfig_writedata,
   output						p1_pciess_reconfig_read,
   input  	[31:0]					p1_pciess_reconfig_readdata,
   input						p1_pciess_reconfig_readdatavalid,
   input						p1_pciess_reconfig_waitrequest,
   output						p0_toolkit_mode,
   output						p1_toolkit_mode,

   output        p0_pld_in_use_o,
   output        p1_pld_in_use_o,

   input         p0_i_syspll_c0_clk,
   input         p1_i_syspll_c0_clk,
   input         i_syspll_c1_clk,
   input         i_syspll_c2_clk,
   input         p0_i_ss_vccl_syspll_locked,
   input         p1_i_ss_vccl_syspll_locked,
   input [l_quad_num-1:0]         i_flux_clk,

   //vteh pipemode sim signals
   
   output	 p0_user_mode_to_pld_o,
   output	 p1_user_mode_to_pld_o

);

  localparam core16_num_of_lanes = (core16_func_mode_hwtcl == "Enable") ? ((sm_hssi_pcie_ctl_x4_num_of_lanes_hwtcl == "NUM_OF_LANES_NUM_4")? 4 : (sm_hssi_pcie_ctl_x4_num_of_lanes_hwtcl == "NUM_OF_LANES_NUM_2")? 2 : 1) : 1;
  localparam core8_num_of_lanes = (core8_func_mode_hwtcl == "Enable") ? ((sm_hssi_pcie_ctl_x8_num_of_lanes_hwtcl == "NUM_OF_LANES_NUM_8")? 8 :(sm_hssi_pcie_ctl_x8_num_of_lanes_hwtcl == "NUM_OF_LANES_NUM_4")? 4 : (sm_hssi_pcie_ctl_x8_num_of_lanes_hwtcl == "NUM_OF_LANES_NUM_2")? 2 : 1) : 1;

  wire  p0_coreclkout_hip_w;
  wire  p1_coreclkout_hip_w;
  assign p0_coreclkout_hip = p0_coreclkout_hip_w;
  assign p1_coreclkout_hip = '0;

  wire [((core16_num_of_lanes+1)*100)-1:0] p0_o_hio_rxdata_async;
/////  zhejieta: when core8 is x8 route all P1 async signals to ch5, when core8 is x4/x2/x1 route all P1 async signals to ch0 
  wire [((core8_num_of_lanes+1)*100)-1:0] p1_o_hio_rxdata_async;

  assign p1_o_hio_rxdata_async = '0;

  wire   p0_hip_pin_perst_n;
  wire   p0_core_pll_lock;
  wire   p0_tx_dsk_done;
  wire   p0_user_mode_to_pld;
  wire   p0_pld_in_use;
  wire   p0_pld_core_rst_n;
  wire   p0_pld_link_req_rst;
  wire [2:0] p0_pm_state;
  wire [3:0] p0_pm_pf0_dstate;
  wire [3:0] p0_pm_pf1_dstate;
  wire [3:0] p0_pm_pf2_dstate;
  wire [3:0] p0_pm_pf3_dstate;
  wire   p1_hip_pin_perst_n;
  wire   p1_core_pll_lock;
  wire   p1_tx_dsk_done;
  wire   p1_user_mode_to_pld;
  wire   p1_pld_in_use;
  wire   p1_pld_link_req_rst;
  wire   p1_pld_core_rst_n;
  wire [2:0] p1_pm_state;
  wire [3:0] p1_pm_pf0_dstate;
  wire [3:0] p1_pm_pf1_dstate;
  wire [3:0] p1_pm_pf2_dstate;
  wire [3:0] p1_pm_pf3_dstate;

  assign p0_hip_pin_perst_n  = p0_o_hio_rxdata_async[30];
  assign p0_core_pll_lock    = p0_o_hio_rxdata_async[31];
  assign p0_tx_dsk_done      = p0_o_hio_rxdata_async[64];
  assign p0_user_mode_to_pld = p0_o_hio_rxdata_async[66]; 
  assign p0_pld_in_use       = p0_o_hio_rxdata_async[67];
  assign p0_pld_core_rst_n   = p0_o_hio_rxdata_async[68];
  assign p0_pld_link_req_rst = p0_o_hio_rxdata_async[70]; 
  assign p0_pm_state         = p0_o_hio_rxdata_async[73:71];  // HSD:15015636881
  assign p0_pm_pf0_dstate    = p0_o_hio_rxdata_async[59:56];
  assign p0_pm_pf1_dstate    = p0_o_hio_rxdata_async[77:74];
  assign p0_pm_pf2_dstate    = p0_o_hio_rxdata_async[81:78];
  assign p0_pm_pf3_dstate    = p0_o_hio_rxdata_async[85:82];
  assign p1_hip_pin_perst_n  = p1_o_hio_rxdata_async[30];
  assign p1_core_pll_lock    = p1_o_hio_rxdata_async[31];
  assign p1_tx_dsk_done      = p1_o_hio_rxdata_async[64];
  assign p1_user_mode_to_pld = p1_o_hio_rxdata_async[66]; 
  assign p1_pld_in_use       = p1_o_hio_rxdata_async[67];
  assign p1_pld_core_rst_n   = p1_o_hio_rxdata_async[68];
  assign p1_pld_link_req_rst = p1_o_hio_rxdata_async[70]; 
  assign p1_pm_state         = p1_o_hio_rxdata_async[73:71];
  assign p1_pm_pf0_dstate    = p1_o_hio_rxdata_async[59:56];
  assign p1_pm_pf1_dstate    = p1_o_hio_rxdata_async[77:74];
  assign p1_pm_pf2_dstate    = p1_o_hio_rxdata_async[81:78];
  assign p1_pm_pf3_dstate    = p1_o_hio_rxdata_async[85:82];


  wire   p0_pld_ready ;
  wire p0_pld_warm_rst_rdy ;
  wire   p1_pld_ready ;
  wire p1_pld_warm_rst_rdy ;

  wire [((core16_num_of_lanes+1)*100)-1:0] p0_i_hio_txdata_async;
/////  zhejieta: when core8 is x8 route all P1 async signals to ch5, when core8 is x4/x2/x1 route all P1 async signals to ch0 
  wire [((core8_num_of_lanes+1)*100)-1:0] p1_i_hio_txdata_async;

  assign p0_i_hio_txdata_async[24:0]    = '0;
  assign p0_i_hio_txdata_async[36:25]   = '1;
  assign p0_i_hio_txdata_async[37]      = p0_pld_warm_rst_rdy; 
  assign p0_i_hio_txdata_async[38]      = p0_pld_ready;
  assign p0_i_hio_txdata_async[42:39]   = p0_app_req_retry_en_i[3:0];
  assign p0_i_hio_txdata_async[99:43]   = '0;
  assign p0_i_hio_txdata_async[((core16_num_of_lanes+1)*100)-1:100] = '0;
  assign p1_i_hio_txdata_async[24:0]    = '0;
  assign p1_i_hio_txdata_async[36:25]   = '1;
  assign p1_i_hio_txdata_async[37]      = p1_pld_warm_rst_rdy; 
  assign p1_i_hio_txdata_async[38]      = p1_pld_ready;
  assign p1_i_hio_txdata_async[42:39]   = p1_app_req_retry_en_i[3:0];
  assign p1_i_hio_txdata_async[99:43]   = '0;
  assign p1_i_hio_txdata_async[((core8_num_of_lanes+1)*100)-1:100] = '0;


//RX synchronous datapath
   wire   [79:0]  ch0_rx_data;
   wire   [79:0]  ch1_rx_data;
   wire   [79:0]  ch2_rx_data;
   wire   [79:0]  ch3_rx_data;
   wire   [79:0]  ch4_rx_data; 
   wire   [79:0]  ch5_rx_data;
   wire   [79:0]  ch6_rx_data;
   wire   [79:0]  ch7_rx_data;
   wire   [79:0]  ch8_rx_data;
   wire   [79:0]  ch9_rx_data; 
   wire   [79:0]  ch10_rx_data; 
   wire   [79:0]  ch11_rx_data; 



//TX synchronous datapath
   wire   [79:0]  ch0_tx_data;
   wire   [79:0]  ch1_tx_data;
   wire   [79:0]  ch2_tx_data;
   wire   [79:0]  ch3_tx_data;
   wire   [79:0]  ch4_tx_data; 
   wire   [79:0]  ch5_tx_data;
   wire   [79:0]  ch6_tx_data;
   wire   [79:0]  ch7_tx_data;
   wire   [79:0]  ch8_tx_data;
   wire   [79:0]  ch9_tx_data; 
   wire   [79:0]  ch10_tx_data; 
   wire   [79:0]  ch11_tx_data; 



//KAHUAT_EDIT 
   localparam core16_num_of_chnl_w = (core16_func_mode_hwtcl == "Enable") ? ((core16_topology=="pcie_x4") ? 5 : (core16_topology=="pcie_x2") ? 3 : (core16_topology=="pcie_x1") ? 2 : 5) : 1;
   localparam core8_num_of_chnl_w = (core8_func_mode_hwtcl == "Enable") ? ((core8_topology=="pcie_x8") ? 9 :(core8_topology=="pcie_x4") ? 5 : (core8_topology=="pcie_x2") ? 3 : (core8_topology=="pcie_x1") ? 2 : 5) : 1; 
 
   wire   [core16_num_of_chnl_w -1:0] p0_pld_adapter_tx_pld_rst_n;
   wire   [core16_num_of_chnl_w -1:0] p0_pld_adapter_rx_pld_rst_n;
   wire   [core8_num_of_chnl_w :0] p1_pld_adapter_tx_pld_rst_n;
   wire   [core8_num_of_chnl_w :0] p1_pld_adapter_rx_pld_rst_n;

   wire   [core16_num_of_chnl_w -1:0] p0_pld_adapter_tx_pld_rst_n_nc;
   wire   [core16_num_of_chnl_w -1:0] p0_pld_adapter_rx_pld_rst_n_nc;
   wire   [core8_num_of_chnl_w :0] p1_pld_adapter_tx_pld_rst_n_nc;
   wire   [core8_num_of_chnl_w :0] p1_pld_adapter_rx_pld_rst_n_nc; 



//KLAI4 EDIT for temporary DEF PARAM include 
   `ifndef PCIE_QHIP
      `define PCIE_QHIP `TEST_TOP.sm_inst.intel_pcie_gts_inst.gen_sm_qhip.u_sm_qhip
   `endif //SM QHIP

   `ifndef TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0
      `define TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0 sm_pcie_hal_top_inst.pcie_hal_top.one_lane_pcie_inst_0.one_lane_pcie_hal_top_p0.phy_hal_top_inst.phy_hal_top.phy_hal_coreip_inst.ch4_phy_inst.x_std_ipfluxtop_uxtop_wrap_0
   `endif
   `ifndef TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1
      `define TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1 sm_pcie_hal_top_inst.pcie_hal_top.one_lane_pcie_inst_1.one_lane_pcie_hal_top_p1.phy_hal_top_inst.phy_hal_top.phy_hal_coreip_inst.ch4_phy_inst.x_std_ipfluxtop_uxtop_wrap_0
   `endif
   `ifndef TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2
      `define TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2 sm_pcie_hal_top_inst.pcie_hal_top.one_lane_pcie_inst_2.one_lane_pcie_hal_top_p2.phy_hal_top_inst.phy_hal_top.phy_hal_coreip_inst.ch4_phy_inst.x_std_ipfluxtop_uxtop_wrap_0
   `endif
   `ifndef TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3
      `define TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3 sm_pcie_hal_top_inst.pcie_hal_top.one_lane_pcie_inst_3.one_lane_pcie_hal_top_p3.phy_hal_top_inst.phy_hal_top.phy_hal_coreip_inst.ch4_phy_inst.x_std_ipfluxtop_uxtop_wrap_0
   `endif
/*   `ifndef TENNM_SM_HSSI_FEC__HSSI_U0__XCVRIF_TOP_U0__XCVRIF_1CH_U0
      `define TENNM_SM_HSSI_FEC__HSSI_U0__XCVRIF_TOP_U0__XCVRIF_1CH_U0 sm_pcie_hal_top_inst.pcie_hal_top.one_lane_pcie_inst_0.one_lane_pcie_hal_top_p0.phy_hal_top_inst.phy_hal_top.phy_hal_coreip_inst.ch4_phy_inst.x_std_sm_xcvrif_1ch_0
   `endif
   `ifndef TENNM_SM_HSSI_FEC__HSSI_U0__XCVRIF_TOP_U0__XCVRIF_1CH_U1
      `define TENNM_SM_HSSI_FEC__HSSI_U0__XCVRIF_TOP_U0__XCVRIF_1CH_U1 sm_pcie_hal_top_inst.pcie_hal_top.one_lane_pcie_inst_1.one_lane_pcie_hal_top_p1.phy_hal_top_inst.phy_hal_top.phy_hal_coreip_inst.ch4_phy_inst.x_std_sm_xcvrif_1ch_0
   `endif
   `ifndef TENNM_SM_HSSI_FEC__HSSI_U0__XCVRIF_TOP_U0__XCVRIF_1CH_U2
      `define TENNM_SM_HSSI_FEC__HSSI_U0__XCVRIF_TOP_U0__XCVRIF_1CH_U2 sm_pcie_hal_top_inst.pcie_hal_top.one_lane_pcie_inst_2.one_lane_pcie_hal_top_p2.phy_hal_top_inst.phy_hal_top.phy_hal_coreip_inst.ch4_phy_inst.x_std_sm_xcvrif_1ch_0
   `endif
   `ifndef TENNM_SM_HSSI_FEC__HSSI_U0__XCVRIF_TOP_U0__XCVRIF_1CH_U3
      `define TENNM_SM_HSSI_FEC__HSSI_U0__XCVRIF_TOP_U0__XCVRIF_1CH_U3 sm_pcie_hal_top_inst.pcie_hal_top.one_lane_pcie_inst_3.one_lane_pcie_hal_top_p3.phy_hal_top_inst.phy_hal_top.phy_hal_coreip_inst.ch4_phy_inst.x_std_sm_xcvrif_1ch_0
   `endif
   `ifndef TENNM_SM_FLUX_INGRESS__HSSI_SS_U0__UX_QUAD_U0__UX_TOOLBOX_TOP_U0__FLUX_INGRESS_U0
      `define TENNM_SM_FLUX_INGRESS__HSSI_SS_U0__UX_QUAD_U0__UX_TOOLBOX_TOP_U0__FLUX_INGRESS_U0 sm_pcie_hal_top_inst.pcie_hal_top.one_lane_pcie_inst_0.one_lane_pcie_hal_top_p0.phy_hal_top_inst.phy_hal_top.phy_hal_coreip_inst.ch4_phy_inst.x_std_sm_flux_ingress_0
   `endif
   `ifndef TENNM_SM_FLUX_INGRESS__HSSI_SS_U0__UX_QUAD_U0__UX_TOOLBOX_TOP_U0__FLUX_INGRESS_U1
      `define TENNM_SM_FLUX_INGRESS__HSSI_SS_U0__UX_QUAD_U0__UX_TOOLBOX_TOP_U0__FLUX_INGRESS_U1 sm_pcie_hal_top_inst.pcie_hal_top.one_lane_pcie_inst_1.one_lane_pcie_hal_top_p1.phy_hal_top_inst.phy_hal_top.phy_hal_coreip_inst.ch4_phy_inst.x_std_sm_flux_ingress_0
   `endif
   `ifndef TENNM_SM_FLUX_INGRESS__HSSI_SS_U0__UX_QUAD_U0__UX_TOOLBOX_TOP_U0__FLUX_INGRESS_U2
      `define TENNM_SM_FLUX_INGRESS__HSSI_SS_U0__UX_QUAD_U0__UX_TOOLBOX_TOP_U0__FLUX_INGRESS_U2 sm_pcie_hal_top_inst.pcie_hal_top.one_lane_pcie_inst_2.one_lane_pcie_hal_top_p2.phy_hal_top_inst.phy_hal_top.phy_hal_coreip_inst.ch4_phy_inst.x_std_sm_flux_ingress_0
   `endif
   `ifndef TENNM_SM_FLUX_INGRESS__HSSI_SS_U0__UX_QUAD_U0__UX_TOOLBOX_TOP_U0__FLUX_INGRESS_U3
      `define TENNM_SM_FLUX_INGRESS__HSSI_SS_U0__UX_QUAD_U0__UX_TOOLBOX_TOP_U0__FLUX_INGRESS_U3 sm_pcie_hal_top_inst.pcie_hal_top.one_lane_pcie_inst_3.one_lane_pcie_hal_top_p3.phy_hal_top_inst.phy_hal_top.phy_hal_coreip_inst.ch4_phy_inst.x_std_sm_flux_ingress_0
   `endif
*/

//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.cdr_f_out_hz = 36'h4a817c80;//1.25Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.cdr_f_pfd_hz = 36'h5f5e100;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.cdr_f_ref_hz = 36'h5f5e100;//100MHz
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.cdr_f_vco_hz = 36'h2540be400;//10Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.cdr_l_counter = 6'h8;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.cdr_m_counter = 9'h32;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.cdr_n_counter = 6'h1;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.rx_datarate_bps = 37'h9502f900;//2.5Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_datarate_bps = 37'h9502f900;//2.5Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_pll_f_out_hz = 36'h4a817c80;//1.25Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_pll_f_pfd_hz = 36'h5f5e100;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_pll_f_ref_hz = 36'h5f5e100;//100MHz
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_pll_f_vco_hz = 36'h2540be400;//10Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_pll_k_counter = 22'h0;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_pll_l_counter = 6'h8;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_pll_m_counter = 9'h64;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_pll_n_counter = 6'h1;

//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.rx_word_clk_hz = 36'h6b61f3534;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_pll_postdiv_sel = "TX_PLL_POSTDIV_SEL_SYNTH2";
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_postdiv_cdr_refclk_divider = 8'h5a;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_postdiv_cdr_refclk_hz = 36'h63f82fa00;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_postdiv_clk_hz = 36'h88c9543;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_synthdiv_out_divider = 8'hb;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_synthdiv_out_hz = 36'h8f05e2c00;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE0.tx_word_clk_hz = 36'hf1967516a;


//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.cdr_f_out_hz = 36'h4a817c80;//1.25Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.cdr_f_pfd_hz = 36'h5f5e100;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.cdr_f_ref_hz = 36'h5f5e100;//100MHz
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.cdr_f_vco_hz = 36'h2540be400;//10Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.cdr_l_counter = 6'h8;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.cdr_m_counter = 9'h32;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.cdr_n_counter = 6'h1;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.rx_datarate_bps = 37'h9502f900;//2.5Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_datarate_bps = 37'h9502f900;//2.5Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_pll_f_out_hz = 36'h4a817c80;//1.25Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_pll_f_pfd_hz = 36'h5f5e100;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_pll_f_ref_hz = 36'h5f5e100;//100MHz
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_pll_f_vco_hz = 36'h2540be400;//10Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_pll_k_counter = 22'h0;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_pll_l_counter = 6'h8;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_pll_m_counter = 9'h64;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_pll_n_counter = 6'h1;

//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.rx_word_clk_hz = 36'h52e8e8c8a;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_pll_postdiv_sel = "TX_PLL_POSTDIV_SEL_SYNTH2";
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_postdiv_cdr_refclk_divider = 8'h15;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_postdiv_cdr_refclk_hz = 36'h0;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_postdiv_clk_hz = 36'h18860a26;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_synthdiv_out_divider = 8'h48;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_synthdiv_out_hz = 36'h7cf63b880;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE1.tx_word_clk_hz = 36'h9d89613fb;

//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.cdr_f_out_hz = 36'h4a817c80;//1.25Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.cdr_f_pfd_hz = 36'h5f5e100;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.cdr_f_ref_hz = 36'h5f5e100;//100MHz
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.cdr_f_vco_hz = 36'h2540be400;//10Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.cdr_l_counter = 6'h8;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.cdr_m_counter = 9'h32;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.cdr_n_counter = 6'h1;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.rx_datarate_bps = 37'h9502f900;//2.5Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_datarate_bps = 37'h9502f900;//2.5Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_pll_f_out_hz = 36'h4a817c80;//1.25Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_pll_f_pfd_hz = 36'h5f5e100;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_pll_f_ref_hz = 36'h5f5e100;//100MHz
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_pll_f_vco_hz = 36'h2540be400;//10Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_pll_k_counter = 22'h0;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_pll_l_counter = 6'h8;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_pll_m_counter = 9'h64;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_pll_n_counter = 6'h1;

//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.rx_word_clk_hz = 36'h2c97f232;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_pll_postdiv_sel = "TX_PLL_POSTDIV_SEL_SYNTH2";
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_postdiv_cdr_refclk_divider = 8'hbe;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_postdiv_cdr_refclk_hz = 36'hdab74e00;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_postdiv_clk_hz = 36'h44e2d89;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_synthdiv_out_divider = 8'h14;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_synthdiv_out_hz = 36'h1dcd6500;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE2.tx_word_clk_hz = 36'h2214879a2;



//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.cdr_f_out_hz = 36'h4a817c80;//1.25Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.cdr_f_pfd_hz = 36'h5f5e100;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.cdr_f_ref_hz = 36'h5f5e100;//100MHz
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.cdr_f_vco_hz = 36'h2540be400;//10Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.cdr_l_counter = 6'h8;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.cdr_m_counter = 9'h32;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.cdr_n_counter = 6'h1;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.rx_datarate_bps = 37'h9502f900;//2.5Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_datarate_bps = 37'h9502f900;//2.5Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_pll_f_out_hz = 36'h4a817c80;//1.25Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_pll_f_pfd_hz = 36'h5f5e100;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_pll_f_ref_hz = 36'h5f5e100;//100MHz
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_pll_f_vco_hz = 36'h2540be400;//10Gbps
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_pll_k_counter = 22'h0;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_pll_l_counter = 6'h8;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_pll_m_counter = 9'h64;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_pll_n_counter = 6'h1;

//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.rx_word_clk_hz = 36'haa1fbb5d9;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_pll_postdiv_sel = "TX_PLL_POSTDIV_SEL_SYNTH2";
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_postdiv_cdr_refclk_divider = 8'he6;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_postdiv_cdr_refclk_hz = 36'he455fc600;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_postdiv_clk_hz = 36'h347065c8;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_synthdiv_out_divider = 8'h5b;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_synthdiv_out_hz = 36'h1c8a8ec00;
//defparam `TENNM_IPFLUXTOP_UXTOP_WRAP__HSSI_SS_U0__UX_QUAD_U0__IPFLUXTOP_U0__FLUX_CORE_INS__FLUX_4UX_WRAP_INS__I_UXTOP_WRAP_LANE3.tx_word_clk_hz = 36'h2e32b3c8c;



/*
defparam `TENNM_SM_HSSI_FEC__HSSI_U0__XCVRIF_TOP_U0__XCVRIF_1CH_U0.tx_bond_size = "TX_BOND_SIZE_UNUSED";
defparam `TENNM_SM_HSSI_FEC__HSSI_U0__XCVRIF_TOP_U0__XCVRIF_1CH_U1.tx_bond_size = "TX_BOND_SIZE_UNUSED";
defparam `TENNM_SM_HSSI_FEC__HSSI_U0__XCVRIF_TOP_U0__XCVRIF_1CH_U2.tx_bond_size = "TX_BOND_SIZE_UNUSED";
defparam `TENNM_SM_HSSI_FEC__HSSI_U0__XCVRIF_TOP_U0__XCVRIF_1CH_U3.tx_bond_size = "TX_BOND_SIZE_UNUSED";

defparam `TENNM_SM_FLUX_INGRESS__HSSI_SS_U0__UX_QUAD_U0__UX_TOOLBOX_TOP_U0__FLUX_INGRESS_U0.tx_bond_size = "TX_BOND_SIZE_X4";
defparam `TENNM_SM_FLUX_INGRESS__HSSI_SS_U0__UX_QUAD_U0__UX_TOOLBOX_TOP_U0__FLUX_INGRESS_U1.tx_bond_size = "TX_BOND_SIZE_X4";
defparam `TENNM_SM_FLUX_INGRESS__HSSI_SS_U0__UX_QUAD_U0__UX_TOOLBOX_TOP_U0__FLUX_INGRESS_U2.tx_bond_size = "TX_BOND_SIZE_X4";
defparam `TENNM_SM_FLUX_INGRESS__HSSI_SS_U0__UX_QUAD_U0__UX_TOOLBOX_TOP_U0__FLUX_INGRESS_U3.tx_bond_size = "TX_BOND_SIZE_X4";
*/

//KLAI4 EDIT end

/*
//KAHUAT_EDIT
   // start of BAR mask localparam
   function [63:0] get_bar_size_mask;
   // Compute bar size mask based on BAR size 
      input integer bara_64bit_mem_space ;// Integer 1 or 0 
      input integer bara_size            ;// Integer number of bits 
      input integer barb_size            ;// Integer number of bits 
      reg [63:0] barab_size_mask64;
      reg [31:0] bara_size_mask31_0;
      reg [31:0] barb_size_mask31_0;
      begin
         barab_size_mask64   = ~{64'hffff_ffff_ffff_ffff << (bara_size )   };   
         bara_size_mask31_0  = ~{32'hffff_ffff           << (bara_size )};
         barb_size_mask31_0  = ~{32'hffff_ffff           << (barb_size  )};  
         get_bar_size_mask   = (bara_64bit_mem_space == 1)? barab_size_mask64[63:0]:
                               {barb_size_mask31_0[31:0]  , bara_size_mask31_0[31:0]};
      end  
   endfunction

   function [20:00] get_expansion_base_addr_mask;
      // Compute expansion ROM size mask based on expansion ROM size 
      input integer expansion_base_address_size;
      reg [31:0] mask31_0;
      begin
         mask31_0 = ~{32'hffff_ffff << (expansion_base_address_size)};
         get_expansion_base_addr_mask = mask31_0[31:11];
      end  
   endfunction

   // -------------------------- core16 BAR mask localparam --------------------------
   // PF0 BAR0-5 mask & ROM BAR mask
   localparam [63:0] core16_pf0_bar01_size_mask                                      = (core16_func_mode_hwtcl=="Enable")?(get_bar_size_mask((sm_hssi_pcie_ctl_x4_pf0_bar0_type_hwtcl=="PF0_BAR0_TYPE_BAR_MEM64")?1:0,core16_pf0_bar0_address_width_hwtcl, core16_pf0_bar1_address_width_hwtcl)):64'b0;
   localparam [30:0] sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar0_mask_31_1_hwtcl          = (sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar0_enabled_hwtcl=="PF0_PCI_TYPE0_BAR0_ENABLED_ENABLED")?(core16_pf0_bar01_size_mask[31:1]):32'b0;
   localparam [30:0] sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar1_mask_31_0_hwtcl          = (sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar1_enabled_hwtcl=="PF0_PCI_TYPE0_BAR1_ENABLED_ENABLED" || sm_hssi_pcie_ctl_x4_pf0_bar0_type_hwtcl=="PF0_BAR0_TYPE_BAR_MEM64")?(core16_pf0_bar01_size_mask[63:33]):32'b0;
//   localparam        ctop_core16_virtual_pf0_bar1_mask_bit0            = (ctop_core16_pf0_bar0_type=="CTOP_CORE16_PF0_BAR0_MEM64")? ((ctop_core16_pf0_bar01_size_mask[32]==1'b1) ?"TRUE":"FALSE"):"FALSE";

   localparam [63:0] core16_pf0_bar23_size_mask                                      = (core16_func_mode_hwtcl=="Enable")?(get_bar_size_mask((sm_hssi_pcie_ctl_x4_pf0_bar2_type_hwtcl=="PF0_BAR2_TYPE_BAR_MEM64")?1:0,core16_pf0_bar2_address_width_hwtcl, core16_pf0_bar3_address_width_hwtcl)):64'b0;
   localparam [30:0] sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar2_mask_31_1_hwtcl          = (sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar2_enabled_hwtcl=="PF0_PCI_TYPE0_BAR2_ENABLED_ENABLED")?(core16_pf0_bar23_size_mask[31:1]):32'b0;
   localparam [30:0] sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar3_mask_31_0_hwtcl          = (sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar3_enabled_hwtcl=="PF0_PCI_TYPE0_BAR3_ENABLED_ENABLED" || sm_hssi_pcie_ctl_x4_pf0_bar2_type_hwtcl=="PF0_BAR2_TYPE_BAR_MEM64")?(core16_pf0_bar23_size_mask[63:33]):32'b0;
//   localparam        ctop_core16_virtual_pf0_bar3_mask_bit0            = (ctop_core16_pf0_bar2_type=="CTOP_CORE16_PF0_BAR2_MEM64")?((ctop_core16_pf0_bar23_size_mask[32]==1'b1) ?"TRUE":"FALSE"):"FALSE";

   localparam [63:0] core16_pf0_bar45_size_mask                                      = (core16_func_mode_hwtcl=="Enable")?(get_bar_size_mask((sm_hssi_pcie_ctl_x4_pf0_bar4_type_hwtcl=="PF0_BAR4_TYPE_BAR_MEM64")?1:0,core16_pf0_bar4_address_width_hwtcl, core16_pf0_bar5_address_width_hwtcl)):64'b0;
   localparam [30:0] sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar4_mask_31_1_hwtcl          = (sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar4_enabled_hwtcl=="PF0_PCI_TYPE0_BAR4_ENABLED_ENABLED")?(core16_pf0_bar45_size_mask[31:1]):32'b0;
   localparam [30:0] sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar5_mask_31_0_hwtcl          = (sm_hssi_pcie_ctl_x4_pf0_pci_type0_bar5_enabled_hwtcl=="PF0_PCI_TYPE0_BAR5_ENABLED_ENABLED" || sm_hssi_pcie_ctl_x4_pf0_bar4_type_hwtcl=="PF0_BAR4_TYPE_BAR_MEM64")?(core16_pf0_bar45_size_mask[63:33]):32'b0;
//   localparam        ctop_core16_virtual_pf0_bar5_mask_bit0            = (ctop_core16_pf0_bar4_type=="CTOP_CORE16_PF0_BAR4_MEM64")?((ctop_core16_pf0_bar45_size_mask[32]==1'b1) ?"TRUE":"FALSE"):"FALSE";
*/

// DTK Mode
	wire [23:0]	p0_hip_reconfig_address_w;
	wire 		p0_hip_reconfig_write_w;
	wire [31:0]	p0_hip_reconfig_writedata_w;
	wire 		p0_hip_reconfig_read_w;
	wire [31:0]	p0_hip_reconfig_readdata_w;
	wire		p0_hip_reconfig_readdatavalid_w;
	wire		p0_hip_reconfig_waitrequest_w;
	wire [3:0]	p0_hip_reconfig_byteen_w;
	wire [23:0]	p1_hip_reconfig_address_w;
	wire 		p1_hip_reconfig_write_w;
	wire [31:0]	p1_hip_reconfig_writedata_w;
	wire 		p1_hip_reconfig_read_w;
	wire [31:0]	p1_hip_reconfig_readdata_w;
	wire		p1_hip_reconfig_readdatavalid_w;
	wire		p1_hip_reconfig_waitrequest_w;
	wire [3:0]	p1_hip_reconfig_byteen_w;
	wire [31:0]	p0_dtk_ss_avmm_readdata;
	wire		p0_dtk_ss_avmm_readdatavalid;
	wire		p0_dtk_ss_avmm_waitrequest;
	wire [20:0]	p0_dtk_ss_avmm_address;
	wire		p0_dtk_ss_avmm_write;
	wire [31:0]	p0_dtk_ss_avmm_writedata;
	wire		p0_dtk_ss_avmm_read;
	wire [31:0]	p1_dtk_ss_avmm_readdata;
	wire		p1_dtk_ss_avmm_readdatavalid;
	wire		p1_dtk_ss_avmm_waitrequest;
	wire [20:0]	p1_dtk_ss_avmm_address;
	wire		p1_dtk_ss_avmm_write;
	wire [31:0]	p1_dtk_ss_avmm_writedata;
	wire		p1_dtk_ss_avmm_read;
	wire [20:0]	dtk_p0_avmm_address;
	wire		dtk_p0_avmm_write;
	wire [31:0]	dtk_p0_avmm_writedata;
	wire		dtk_p0_avmm_read;
	wire [31:0]	dtk_p0_avmm_readdata;
	wire		dtk_p0_avmm_readdatavalid;
	wire		dtk_p0_avmm_waitrequest;
	wire [20:0]	dtk_p1_avmm_address;
	wire		dtk_p1_avmm_write;
	wire [31:0]	dtk_p1_avmm_writedata;
	wire		dtk_p1_avmm_read;
	wire [31:0]	dtk_p1_avmm_readdata;
	wire		dtk_p1_avmm_readdatavalid;
	wire		dtk_p1_avmm_waitrequest;
	wire		p0_pacer_phy_avmm_read;
	wire		p0_pacer_phy_avmm_write;
	wire [23:0]	p0_pacer_phy_avmm_address;
	wire [31:0]	p0_pacer_phy_avmm_writedata;
	wire		p0_pacer_phy_avmm_readdatavalid;
	wire [31:0]	p0_pacer_phy_avmm_readdata;
	wire		p0_pacer_phy_avmm_waitrequest;
	wire		p1_pacer_phy_avmm_read;
	wire		p1_pacer_phy_avmm_write;
	wire [23:0]	p1_pacer_phy_avmm_address;
	wire [31:0]	p1_pacer_phy_avmm_writedata;
	wire		p1_pacer_phy_avmm_readdatavalid;
	wire [31:0]	p1_pacer_phy_avmm_readdata;
	wire		p1_pacer_phy_avmm_waitrequest;
	wire		p0_phy_avmm_clk;
	wire		p0_phy_avmm_read;
	wire		p0_phy_avmm_write;
	wire [23:0]	p0_phy_avmm_address;
	wire [31:0]	p0_phy_avmm_writedata;
	wire		p0_phy_avmm_readdatavalid;
	wire [31:0]	p0_phy_avmm_readdata;
	wire		p0_phy_avmm_waitrequest;
	wire        	phy0_avmm_read;
    	wire         	phy0_avmm_write;
    	wire [20:0]  	phy0_avmm_address;
    	wire [31:0]  	phy0_avmm_writedata;
    	wire       	phy0_avmm_readdatavalid;
    	wire [31:0]  	phy0_avmm_readdata;
    	wire       	phy0_avmm_waitrequest;
	wire      	phy1_avmm_read;
    	wire      	phy1_avmm_write;
    	wire [20:0]  	phy1_avmm_address;
    	wire [31:0]  	phy1_avmm_writedata;
    	wire       	phy1_avmm_readdatavalid;
    	wire [31:0]  	phy1_avmm_readdata;
    	wire       	phy1_avmm_waitrequest;
	wire      	phy2_avmm_read;
    	wire      	phy2_avmm_write;
    	wire [20:0]  	phy2_avmm_address;
    	wire [31:0]  	phy2_avmm_writedata;
    	wire       	phy2_avmm_readdatavalid;
    	wire [31:0]  	phy2_avmm_readdata;
    	wire       	phy2_avmm_waitrequest;
	wire      	phy3_avmm_read;
    	wire      	phy3_avmm_write;
    	wire [20:0]  	phy3_avmm_address;
    	wire [31:0]  	phy3_avmm_writedata;
    	wire       	phy3_avmm_readdatavalid;
    	wire [31:0]  	phy3_avmm_readdata;
    	wire          	phy3_avmm_waitrequest;
	wire		p1_phy_avmm_clk;
	wire		p1_phy_avmm_read;
	wire		p1_phy_avmm_write;
	wire [23:0]	p1_phy_avmm_address;
	wire [31:0]	p1_phy_avmm_writedata;
	wire		p1_phy_avmm_readdatavalid;
	wire [31:0]	p1_phy_avmm_readdata;
	wire		p1_phy_avmm_waitrequest;
	wire        	phy4_avmm_read;
    	wire         	phy4_avmm_write;
    	wire [20:0]  	phy4_avmm_address;
    	wire [31:0]  	phy4_avmm_writedata;
    	wire       	phy4_avmm_readdatavalid;
    	wire [31:0]  	phy4_avmm_readdata;
    	wire       	phy4_avmm_waitrequest;
	wire        	phy5_avmm_read;
    	wire         	phy5_avmm_write;
    	wire [20:0]  	phy5_avmm_address;
    	wire [31:0]  	phy5_avmm_writedata;
    	wire       	phy5_avmm_readdatavalid;
    	wire [31:0]  	phy5_avmm_readdata;
    	wire       	phy5_avmm_waitrequest;
	wire        	phy6_avmm_read;
    	wire         	phy6_avmm_write;
    	wire [20:0]  	phy6_avmm_address;
    	wire [31:0]  	phy6_avmm_writedata;
    	wire       	phy6_avmm_readdatavalid;
    	wire [31:0]  	phy6_avmm_readdata;
    	wire       	phy6_avmm_waitrequest;
	wire        	phy7_avmm_read;
    	wire         	phy7_avmm_write;
    	wire [20:0]  	phy7_avmm_address;
    	wire [31:0]  	phy7_avmm_writedata;
    	wire       	phy7_avmm_readdatavalid;
    	wire [31:0]  	phy7_avmm_readdata;
    	wire       	phy7_avmm_waitrequest;

	
	assign p0_hip_reconfig_address_w 	= p0_toolkit_mode ? {3'b0, dtk_p0_avmm_address} : p0_hip_reconfig_address;
	assign p0_hip_reconfig_write_w 		= p0_toolkit_mode ? dtk_p0_avmm_write : p0_hip_reconfig_write;
	assign p0_hip_reconfig_writedata_w 	= p0_toolkit_mode ? dtk_p0_avmm_writedata : p0_hip_reconfig_writedata;
	assign p0_hip_reconfig_read_w 		= p0_toolkit_mode ? dtk_p0_avmm_read : p0_hip_reconfig_read;
	assign p0_hip_reconfig_byteen_w		= p0_toolkit_mode ? 4'hf : p0_hip_reconfig_byteen;
	assign p0_hip_reconfig_readdata 	= p0_toolkit_mode ? 32'h0 : p0_hip_reconfig_readdata_w;
	assign p0_hip_reconfig_readdatavalid 	= p0_toolkit_mode ? 1'h0 : p0_hip_reconfig_readdatavalid_w;
	assign p0_hip_reconfig_waitrequest	= p0_toolkit_mode ? 1'h1 : p0_hip_reconfig_waitrequest_w;
	assign dtk_p0_avmm_readdata             = p0_toolkit_mode ? p0_hip_reconfig_readdata_w      : 32'h0;
	assign dtk_p0_avmm_readdatavalid        = p0_toolkit_mode ? p0_hip_reconfig_readdatavalid_w : 1'h0;
	assign dtk_p0_avmm_waitrequest          = p0_toolkit_mode ? p0_hip_reconfig_waitrequest_w   : 1'h0;

	assign p1_hip_reconfig_address_w 	= p1_toolkit_mode ? {3'b0, dtk_p1_avmm_address} : p1_hip_reconfig_address;
	assign p1_hip_reconfig_write_w 		= p1_toolkit_mode ? dtk_p1_avmm_write : p1_hip_reconfig_write;
	assign p1_hip_reconfig_writedata_w 	= p1_toolkit_mode ? dtk_p1_avmm_writedata : p1_hip_reconfig_writedata;
	assign p1_hip_reconfig_read_w 		= p1_toolkit_mode ? dtk_p1_avmm_read : p1_hip_reconfig_read;
	assign p1_hip_reconfig_byteen_w		= p1_toolkit_mode ? 4'hf : p1_hip_reconfig_byteen;
	assign p1_hip_reconfig_readdata 	= p1_toolkit_mode ? 32'h0 : p1_hip_reconfig_readdata_w;
	assign p1_hip_reconfig_readdatavalid 	= p1_toolkit_mode ? 1'h0 : p1_hip_reconfig_readdatavalid_w;
	assign p1_hip_reconfig_waitrequest	= p1_toolkit_mode ? 1'h1 : p1_hip_reconfig_waitrequest_w;
	assign dtk_p1_avmm_readdata             = p1_toolkit_mode ? p1_hip_reconfig_readdata_w      : 32'h0;
	assign dtk_p1_avmm_readdatavalid        = p1_toolkit_mode ? p1_hip_reconfig_readdatavalid_w : 1'h0;
	assign dtk_p1_avmm_waitrequest          = p1_toolkit_mode ? p1_hip_reconfig_waitrequest_w   : 1'h0;

	generate 
	if (enable_pciess_register_access_hwtcl) begin : gen_ss_access_enable
		assign p0_pciess_reconfig_address     = p0_toolkit_mode ? p0_dtk_ss_avmm_address   : 21'b0;
		assign p0_pciess_reconfig_write       = p0_toolkit_mode ? p0_dtk_ss_avmm_write     : 1'b0;
		assign p0_pciess_reconfig_writedata   = p0_toolkit_mode ? p0_dtk_ss_avmm_writedata : 32'b0;
		assign p0_pciess_reconfig_read        = p0_toolkit_mode ? p0_dtk_ss_avmm_read      : 1'b0;
		assign p0_dtk_ss_avmm_readdata        = p0_toolkit_mode ? p0_pciess_reconfig_readdata      : 32'b0;
		assign p0_dtk_ss_avmm_readdatavalid   = p0_toolkit_mode ? p0_pciess_reconfig_readdatavalid : 1'b0;
		assign p0_dtk_ss_avmm_waitrequest     = p0_toolkit_mode ? p0_pciess_reconfig_waitrequest   : 1'b0;

		assign p1_pciess_reconfig_address     = p1_toolkit_mode ? p1_dtk_ss_avmm_address   : 21'b0;
		assign p1_pciess_reconfig_write       = p1_toolkit_mode ? p1_dtk_ss_avmm_write     : 1'b0;
		assign p1_pciess_reconfig_writedata   = p1_toolkit_mode ? p1_dtk_ss_avmm_writedata : 32'b0;
		assign p1_pciess_reconfig_read        = p1_toolkit_mode ? p1_dtk_ss_avmm_read      : 1'b0;
		assign p1_dtk_ss_avmm_readdata        = p1_toolkit_mode ? p1_pciess_reconfig_readdata      : 32'b0;
		assign p1_dtk_ss_avmm_readdatavalid   = p1_toolkit_mode ? p1_pciess_reconfig_readdatavalid : 1'b0;
		assign p1_dtk_ss_avmm_waitrequest     = p1_toolkit_mode ? p1_pciess_reconfig_waitrequest   : 1'b0;

	end else begin : gen_ss_access_disable
	   	assign p0_dtk_ss_avmm_readdata        = '0;
		assign p0_dtk_ss_avmm_readdatavalid   = '0;
		assign p0_dtk_ss_avmm_waitrequest     = '0;
		assign p0_pciess_reconfig_address     = '0;
		assign p0_pciess_reconfig_write       = '0;
		assign p0_pciess_reconfig_writedata   = '0;
		assign p0_pciess_reconfig_read        = '0;

	   	assign p1_dtk_ss_avmm_readdata        = '0;
		assign p1_dtk_ss_avmm_readdatavalid   = '0;
		assign p1_dtk_ss_avmm_waitrequest     = '0;
		assign p1_pciess_reconfig_address     = '0;
		assign p1_pciess_reconfig_write       = '0;
		assign p1_pciess_reconfig_writedata   = '0;
		assign p1_pciess_reconfig_read        = '0;

	end
	endgenerate

// If p0 disabled and p1 not set to 1x8

// If p0 is enabled but not using 4 lanes


// If p1 disabled

	assign ch6_rx_data = '0;
	assign ch7_rx_data = '0;
	assign ch8_rx_data = '0;
	assign ch9_rx_data = '0;
	assign ch10_rx_data = '0;


// If p1 is enabled but not using 4/8 lanes


// tie ch5 and ch11 to 0 as it is set to reserved for lower quad and upper quad respectively
	assign ch5_rx_data = '0;
	assign ch11_rx_data = '0;



   //# SM HAL_TOP
//   pcie_hal_top #(
//KAHUAT_EDIT
//   `include "intel_pcie_qhip_hal_top_parameter_connection.iv"
//
//   . num_of_lanes                    ( sm_hssi_pcie_ctl_x4_num_of_lanes_hwtcl )
//
//   ) sm_pcie_hal_top_inst( 
   gts_axi_streaming_intel_pcie_gts_pcie_hal_top_800_a4pwunq sm_pcie_hal_top_inst(
   // ----------------------------- hwtcl params -----------------------------
   // core16


    .        i_hio_txdata                                 ({ch4_tx_data,ch3_tx_data,ch2_tx_data,ch1_tx_data,ch0_tx_data}),
    .        i_hio_pld_reset_clk_row                      ({p0_axi_lite_div2_clk,p0_axi_lite_div2_clk,p0_axi_lite_div2_clk,p0_axi_lite_div2_clk,p0_axi_lite_div2_clk}),
    .        o_hio_rxdata                                 ({ch4_rx_data,ch3_rx_data,ch2_rx_data,ch1_rx_data,ch0_rx_data}),
    .        i_hio_txdata_extra                           ('0),
    .        i_hio_txdata_fifo_wr_en                      ('0),
    .        i_hio_rxdata_fifo_rd_en                      ('0),
    .        o_hio_pcie_user_rx_clk1_clk                  (p0_coreclkout_hip_w),
    .        o_hio_pcie_user_rx_clk2_clk                  (),
    .        o_hio_pcie_user_tx_clk1_clk                  (),
    .        o_hio_pcie_user_tx_clk2_clk                  (),
    .        o_hio_ch0_user_rx_clk1_clk                   (),
    .        o_hio_ch0_user_rx_clk2_clk                   (),
    .        o_hio_ch0_user_tx_clk1_clk                   (),
    .        o_hio_ch0_user_tx_clk2_clk                   (),
    
    .        o_hio_ch1_user_rx_clk1_clk                   (),
    .        o_hio_ch1_user_rx_clk2_clk                   (),
    .        o_hio_ch1_user_tx_clk1_clk                   (),
    .        o_hio_ch1_user_tx_clk2_clk                   (), 

    .        o_hio_ch2_user_rx_clk1_clk                   (),
    .        o_hio_ch2_user_rx_clk2_clk                   (),
    .        o_hio_ch2_user_tx_clk1_clk                   (),
    .        o_hio_ch2_user_tx_clk2_clk                   (),
    .        o_hio_ch3_user_rx_clk1_clk                   (),
    .        o_hio_ch3_user_rx_clk2_clk                   (),
    .        o_hio_ch3_user_tx_clk1_clk                   (),
    .        o_hio_ch3_user_tx_clk2_clk                   (),
    
    .        i_hio_ch0_lavmm_addr                         ('0),
    .        i_hio_ch0_lavmm_be                           ('0),
    .        i_hio_ch0_lavmm_read                         ('0),
    .        i_hio_ch0_lavmm_write                        ('0),
    .        i_hio_ch0_lavmm_wdata                        ('0),
    .        o_hio_ch0_lavmm_rdata                        (),
    .        o_hio_ch0_lavmm_rdata_valid                  (),
    .        o_hio_ch0_lavmm_waitreq                      (),
    .        i_hio_ch0_lavmm_rstn                         ('1),
    .        i_hio_ch0_lavmm_clk                          ('0),

    .        i_hio_ch0_pld_rx_clk_in_row_clk              (p0_coreclkout_hip_w),
    .        i_hio_ch0_pld_tx_clk_in_row_clk              (p0_coreclkout_hip_w),
    .        i_hio_ch0_det_lat_rx_dl_clk                  ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch0_det_lat_rx_mux_select              ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch0_det_lat_rx_sclk_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch0_det_lat_rx_sclk_gen_clk            ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch0_det_lat_rx_trig_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch0_det_lat_sampling_clk               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch0_det_lat_tx_dl_clk                  ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch0_det_lat_tx_mux_select              ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch0_det_lat_tx_sclk_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch0_det_lat_tx_sclk_gen_clk            ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch0_det_lat_tx_trig_flop               ('0), //REVIEWED AND NOT REQUIRE.
 //   .        o_hio_ch0_user_rx_clk1_clk                   (p0_coreclkout_hip_w),
 //   .        o_hio_ch0_user_rx_clk2_clk                   (),
 //   .        o_hio_ch0_user_tx_clk1_clk                   (),
 //   .        o_hio_ch0_user_tx_clk2_clk                   (),
    .        o_hio_ch0_ux_chnl_refclk_mux                 (),
    .        o_hio_ch0_det_lat_rx_async_dl_sync           (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch0_det_lat_rx_async_pulse             (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch0_det_lat_rx_async_sample_sync       (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch0_det_lat_rx_sclk_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch0_det_lat_rx_trig_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch0_det_lat_tx_async_dl_sync           (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch0_det_lat_tx_async_pulse             (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch0_det_lat_tx_async_sample_sync       (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch0_det_lat_tx_sclk_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch0_det_lat_tx_trig_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch0_xcvrif_rx_latency_pulse            (),
    .        o_hio_ch0_xcvrif_tx_latency_pulse            (),
    .        i_hio_ch1_lavmm_addr                         ('0),
    .        i_hio_ch1_lavmm_be                           ('0),
    .        i_hio_ch1_lavmm_read                         ('0),
    .        i_hio_ch1_lavmm_write                        ('0),
    .        i_hio_ch1_lavmm_wdata                        ('0),
    .        o_hio_ch1_lavmm_rdata                        (),
    .        o_hio_ch1_lavmm_rdata_valid                  (),
    .        o_hio_ch1_lavmm_waitreq                      (),
    .        i_hio_ch1_lavmm_rstn                         ('1),
    .        i_hio_ch1_lavmm_clk                          ('0),
    .        i_hio_ch1_pld_rx_clk_in_row_clk              (p0_coreclkout_hip_w),
    .        i_hio_ch1_pld_tx_clk_in_row_clk              (p0_coreclkout_hip_w),
    .        i_hio_ch1_det_lat_rx_dl_clk                  ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch1_det_lat_rx_mux_select              ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch1_det_lat_rx_sclk_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch1_det_lat_rx_sclk_gen_clk            ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch1_det_lat_rx_trig_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch1_det_lat_sampling_clk               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch1_det_lat_tx_dl_clk                  ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch1_det_lat_tx_mux_select              ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch1_det_lat_tx_sclk_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch1_det_lat_tx_sclk_gen_clk            ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch1_det_lat_tx_trig_flop               ('0), //REVIEWED AND NOT REQUIRE.
 //   .        o_hio_ch1_user_rx_clk1_clk                   (p0_coreclkout_hip_w),
 //   .        o_hio_ch1_user_rx_clk2_clk                   (),
 //   .        o_hio_ch1_user_tx_clk1_clk                   (),
 //   .        o_hio_ch1_user_tx_clk2_clk                   (),
    .        o_hio_ch1_ux_chnl_refclk_mux                 (),
    .        o_hio_ch1_det_lat_rx_async_dl_sync           (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch1_det_lat_rx_async_pulse             (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch1_det_lat_rx_async_sample_sync       (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch1_det_lat_rx_sclk_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch1_det_lat_rx_trig_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch1_det_lat_tx_async_dl_sync           (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch1_det_lat_tx_async_pulse             (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch1_det_lat_tx_async_sample_sync       (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch1_det_lat_tx_sclk_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch1_det_lat_tx_trig_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch1_xcvrif_rx_latency_pulse            (),
    .        o_hio_ch1_xcvrif_tx_latency_pulse            (),
    .        i_hio_ch2_lavmm_addr                         ('0),
    .        i_hio_ch2_lavmm_be                           ('0),
    .        i_hio_ch2_lavmm_read                         ('0),
    .        i_hio_ch2_lavmm_write                        ('0),
    .        i_hio_ch2_lavmm_wdata                        ('0),
    .        o_hio_ch2_lavmm_rdata                        (),
    .        o_hio_ch2_lavmm_rdata_valid                  (),
    .        o_hio_ch2_lavmm_waitreq                      (),
    .        i_hio_ch2_lavmm_rstn                         ('1),
    .        i_hio_ch2_lavmm_clk                          ('0),
    .        i_hio_ch2_pld_rx_clk_in_row_clk              (p0_coreclkout_hip_w),
    .        i_hio_ch2_pld_tx_clk_in_row_clk              (p0_coreclkout_hip_w),
    .        i_hio_ch2_det_lat_rx_dl_clk                  ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch2_det_lat_rx_mux_select              ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch2_det_lat_rx_sclk_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch2_det_lat_rx_sclk_gen_clk            ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch2_det_lat_rx_trig_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch2_det_lat_sampling_clk               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch2_det_lat_tx_dl_clk                  ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch2_det_lat_tx_mux_select              ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch2_det_lat_tx_sclk_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch2_det_lat_tx_sclk_gen_clk            ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch2_det_lat_tx_trig_flop               ('0), //REVIEWED AND NOT REQUIRE.
 //   .        o_hio_ch2_user_rx_clk1_clk                   (p0_coreclkout_hip_w),
 //   .        o_hio_ch2_user_rx_clk2_clk                   (),
 //   .        o_hio_ch2_user_tx_clk1_clk                   (),
 //   .        o_hio_ch2_user_tx_clk2_clk                   (),
    .        o_hio_ch2_ux_chnl_refclk_mux                 (),
    .        o_hio_ch2_det_lat_rx_async_dl_sync           (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch2_det_lat_rx_async_pulse             (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch2_det_lat_rx_async_sample_sync       (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch2_det_lat_rx_sclk_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch2_det_lat_rx_trig_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch2_det_lat_tx_async_dl_sync           (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch2_det_lat_tx_async_pulse             (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch2_det_lat_tx_async_sample_sync       (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch2_det_lat_tx_sclk_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch2_det_lat_tx_trig_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch2_xcvrif_rx_latency_pulse            (),
    .        o_hio_ch2_xcvrif_tx_latency_pulse            (),
    .        i_hio_ch3_lavmm_addr                         ('0),
    .        i_hio_ch3_lavmm_be                           ('0),
    .        i_hio_ch3_lavmm_read                         ('0),
    .        i_hio_ch3_lavmm_write                        ('0),
    .        i_hio_ch3_lavmm_wdata                        ('0),
    .        o_hio_ch3_lavmm_rdata                        (),
    .        o_hio_ch3_lavmm_rdata_valid                  (),
    .        o_hio_ch3_lavmm_waitreq                      (),
    .        i_hio_ch3_lavmm_rstn                         ('1),
    .        i_hio_ch3_lavmm_clk                          ('0),
    .        i_hio_ch3_pld_rx_clk_in_row_clk              (p0_coreclkout_hip_w),
    .        i_hio_ch3_pld_tx_clk_in_row_clk              (p0_coreclkout_hip_w),
    .        i_hio_ch3_det_lat_rx_dl_clk                  ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch3_det_lat_rx_mux_select              ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch3_det_lat_rx_sclk_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch3_det_lat_rx_sclk_gen_clk            ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch3_det_lat_rx_trig_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch3_det_lat_sampling_clk               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch3_det_lat_tx_dl_clk                  ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch3_det_lat_tx_mux_select              ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch3_det_lat_tx_sclk_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch3_det_lat_tx_sclk_gen_clk            ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch3_det_lat_tx_trig_flop               ('0), //REVIEWED AND NOT REQUIRE.
 //   .        o_hio_ch3_user_rx_clk1_clk                   (p0_coreclkout_hip_w),
 //   .        o_hio_ch3_user_rx_clk2_clk                   (),
 //   .        o_hio_ch3_user_tx_clk1_clk                   (),
 //   .        o_hio_ch3_user_tx_clk2_clk                   (),
    .        o_hio_ch3_ux_chnl_refclk_mux                 (),
    .        o_hio_ch3_det_lat_rx_async_dl_sync           (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch3_det_lat_rx_async_pulse             (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch3_det_lat_rx_async_sample_sync       (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch3_det_lat_rx_sclk_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch3_det_lat_rx_trig_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch3_det_lat_tx_async_dl_sync           (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch3_det_lat_tx_async_pulse             (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch3_det_lat_tx_async_sample_sync       (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch3_det_lat_tx_sclk_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch3_det_lat_tx_trig_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch3_xcvrif_rx_latency_pulse            (),
    .        o_hio_ch3_xcvrif_tx_latency_pulse            (),
    .        i_hio_ch4_lavmm_addr                         ('0),
    .        i_hio_ch4_lavmm_be                           ('0),
    .        i_hio_ch4_lavmm_read                         ('0),
    .        i_hio_ch4_lavmm_write                        ('0),
    .        i_hio_ch4_lavmm_wdata                        ('0),
    .        o_hio_ch4_lavmm_rdata                        (),
    .        o_hio_ch4_lavmm_rdata_valid                  (),
    .        o_hio_ch4_lavmm_waitreq                      (),
    .        i_hio_ch4_lavmm_rstn                         ('1),
    .        i_hio_ch4_lavmm_clk                          ('0),
    .        i_hio_ch4_pld_rx_clk_in_row_clk              (p0_coreclkout_hip_w),
    .        i_hio_ch4_pld_tx_clk_in_row_clk              (p0_coreclkout_hip_w),
    .        i_hio_ch4_det_lat_rx_dl_clk                  ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch4_det_lat_rx_mux_select              ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch4_det_lat_rx_sclk_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch4_det_lat_rx_sclk_gen_clk            ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch4_det_lat_rx_trig_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch4_det_lat_sampling_clk               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch4_det_lat_tx_dl_clk                  ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch4_det_lat_tx_mux_select              ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch4_det_lat_tx_sclk_flop               ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch4_det_lat_tx_sclk_gen_clk            ('0), //REVIEWED AND NOT REQUIRE.
    .        i_hio_ch4_det_lat_tx_trig_flop               ('0), //REVIEWED AND NOT REQUIRE.
 //   .        o_hio_ch4_user_rx_clk1_clk                   (p0_coreclkout_hip_w),
 //   .        o_hio_ch4_user_rx_clk2_clk                   (),
 //   .        o_hio_ch4_user_tx_clk1_clk                   (),
 //   .        o_hio_ch4_user_tx_clk2_clk                   (),
    .        o_hio_ch4_ux_chnl_refclk_mux                 (),
    .        o_hio_ch4_det_lat_rx_async_dl_sync           (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch4_det_lat_rx_async_pulse             (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch4_det_lat_rx_async_sample_sync       (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch4_det_lat_rx_sclk_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch4_det_lat_rx_trig_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch4_det_lat_tx_async_dl_sync           (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch4_det_lat_tx_async_pulse             (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch4_det_lat_tx_async_sample_sync       (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch4_det_lat_tx_sclk_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch4_det_lat_tx_trig_sample_sync        (), //REVIEWED AND NOT REQUIRE.
    .        o_hio_ch4_xcvrif_rx_latency_pulse            (),
    .        o_hio_ch4_xcvrif_tx_latency_pulse            (),

    .        i_hio_ptp_rst_n                              ('1), //REVIEWED.
    .        i_hio_ehip_rx_rst_n                          ('1), //REVIEWED.
    .        i_hio_ehip_tx_rst_n                          ('1), //REVIEWED.
    .        i_hio_ehip_signal_ok                         ('0), //REVIEWED.
    .        i_hio_sfreeze_2_r03f_rx_mac_srfz_n           ('0),
    .        i_hio_sfreeze_3_c2f_tx_deskew_srfz_n         ('0),
    .        i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n           ('0),
    .        i_hio_rstfec_fec_rx_rst_n                    ('1),
    .        i_hio_rstfec_fec_tx_rst_n                    ('1),
    .        i_hio_rstfec_fec_csr_ret                     ('0),
    .        i_hio_rstfec_rx_fec_sfrz_n                   ('1),
    .        i_hio_rstfec_tx_fec_sfrz_n                   ('1),
    .        i_hio_rstxcvrif_xcvrif_rx_rst_n              ('1),
    .        i_hio_rstxcvrif_xcvrif_tx_rst_n              ('1),
    .        i_hio_rstxcvrif_xcvrif_signal_ok             ('0),
    .        i_hio_rstxcvrif_rx_xcvrif_sfrz_n             ('1),
    .        i_hio_rstxcvrif_tx_xcvrif_sfrz_n             ('1),
    .        i_hio_rst_pld_clrhip                         ('0),
    .        i_hio_rst_pld_clrpcs                         ('0),
    .        i_hio_rst_pld_perstn                         (i_gpio_perst0_n),
    .        i_hio_rst_pld_ready                          ('0),
    .        i_hio_rst_pld_adapter_rx_pld_rst_n           (p0_pld_adapter_rx_pld_rst_n),
    .        i_hio_rst_pld_adapter_tx_pld_rst_n           (p0_pld_adapter_tx_pld_rst_n),
    .        i_hio_rst_ux_rx_pma_rst_n                    ('1),
    .        i_hio_rst_ux_rx_sfrz                         ('0),
    .        i_hio_rst_ux_tx_pma_rst_n                    ('1),
    //.        i_hio_pld_reset_clk_row                      ({p0_coreclkout_hip_w,p0_coreclkout_hip_w,p0_coreclkout_hip_w,p0_coreclkout_hip_w,p0_coreclkout_hip_w}),
    .        i_hio_uxquad_async                           ('0),
    .        i_hio_uxquad_async_pcie_mux                  ('0),
    //.        i_hio_pld_rx_clk_in_row_clk                  (),
    //.        i_hio_pld_tx_clk_in_row_clk                  (),
    //.        i_hio_det_lat_rx_dl_clk                      (),
    //.        i_hio_det_lat_rx_mux_select                  (),
    //.        i_hio_det_lat_rx_sclk_flop                   (),
    //.        i_hio_det_lat_rx_sclk_gen_clk                (),
    //.        i_hio_det_lat_rx_trig_flop                   (),
    //.        i_hio_det_lat_sampling_clk                   (),
    //.        i_hio_det_lat_tx_dl_clk                      (),
    //.        i_hio_det_lat_tx_mux_select                  (),
    //.        i_hio_det_lat_tx_sclk_flop                   (),
    //.        i_hio_det_lat_tx_sclk_gen_clk                (),
    //.        i_hio_det_lat_tx_trig_flop                   (),
    .        rx_serial_n                                  ({rx_n_in3,rx_n_in2,rx_n_in1,rx_n_in0}),
    .        rx_serial_p                                  ({rx_p_in3,rx_p_in2,rx_p_in1,rx_p_in0}), 
    //.        i_hio_tx_pfc                                 ()     (),//bits defined
    //.        i_hio_tx_pause                               ()     (),//bits defined
    //.        i_hio_clear_internal                         ()     (),//bits defined
    //.        i_hio_signal_ok                              ()     (),//bits defined
    //.        i_hio_pld_ready                              ()     (),//bits defined
    //.        i_hio_pma_rx_sf                              ()     (),//bits defined
    //.        i_hio_ch_rstxcvrif_lphy_signal_ok            ()     (),//bits defined
    //.        i_clear_tx_internal_err                      ()     (),//bits defined 
    .        o_hio_txdata_fifo_wr_empty                   (),
    .        o_hio_txdata_fifo_wr_pempty                  (),
    .        o_hio_txdata_fifo_wr_full                    (),
    .        o_hio_txdata_fifo_wr_pfull                   (),
    //.        o_hio_rxdata                                 ({ch4_rx_data,ch3_rx_data,ch2_rx_data,ch1_rx_data,ch0_rx_data}),    
    .        o_hio_rxdata_extra                           (),
    .        o_hio_rxdata_fifo_rd_empty                   (),
    .        o_hio_rxdata_fifo_rd_pempty                  (),
    .        o_hio_rxdata_fifo_rd_full                    (),
    .        o_hio_rxdata_fifo_rd_pfull                   (),
    .        o_hio_rstepcs_rx_pcs_fully_aligned           (),
    .        o_hio_rstfec_fec_rx_rdy_n                    (),
    .        o_hio_rst_flux0_cpi_cmn_busy                 (),
    .        o_hio_rst_oflux_rx_srds_rdy                  (),
    .        o_hio_rst_ux_all_synthlockstatus             (),
    .        o_hio_rst_ux_octl_pcs_rxstatus               (),
    .        o_hio_rst_ux_octl_pcs_txstatus               (),
    .        o_hio_rst_ux_rxcdrlock2data                  (),
    .        o_hio_rst_ux_rxcdrlockstatus                 (),
    .        o_hio_uxquad_async                           (),
    //.      k_user_rx_clk1_c0c1c2_sel                      (),
    //.      k_user_rx_clk2_c0c1c2_sel                      (),
    //.      k_user_tx_clk1_c0c1c2_sel                      (),
    //.      k_user_tx_clk2_c0c1c2_sel                      (),
    //.      o_hio_user_rx_clk1_clk                         (),
    //.      o_hio_user_rx_clk2_clk                         (),
    //.      o_hio_user_tx_clk1_clk                         (),
    //.      o_hio_user_tx_clk2_clk                         (),
    //.      o_hio_ux_chnl_refclk_mux                       (),
    //.      o_hio_det_lat_rx_async_dl_sync                 (),
    //.      o_hio_det_lat_rx_async_pulse                   (),
    //.      o_hio_det_lat_rx_async_sample_sync             (),
    //.      o_hio_det_lat_rx_sclk_sample_sync              (),
    //.      o_hio_det_lat_rx_trig_sample_sync              (),
    //.      o_hio_det_lat_tx_async_dl_sync                 (),
    //.      o_hio_det_lat_tx_async_pulse                   (),
    //.      o_hio_det_lat_tx_async_sample_sync             (),
    //.      o_hio_det_lat_tx_sclk_sample_sync              (),
    //.      o_hio_det_lat_tx_trig_sample_sync              (),
    //.      o_hio_xcvrif_rx_latency_pulse                  (),
    //.      o_hio_xcvrif_tx_latency_pulse                  (),
    .      tx_serial_p                                    ({tx_p_out3,tx_p_out2,tx_p_out1,tx_p_out0}),
    .      tx_serial_n                                    ({tx_n_out3,tx_n_out2,tx_n_out1,tx_n_out0}),
    //.      o_hio_local_fault                              ()     (),//bits defined
    //.      o_hio_remote_fault                             ()     (),//bits defined
    //.      o_hio_rx_pause                                 ()     (),//bits defined
    //.      o_hio_rx_pfc                                   ()     (),//bits defined
    //.      o_hio_txfifo_pfull                             ()     (),//bits defined
    //.      o_hio_dsk_err                                  ()     (),//bits defined
    //.      o_hio_dsk_mon_err                              ()     (),//bits defined
    //.      o_hio_hip_ready                                ()     (),//bits defined
    //.      o_hio_rx_block_lock                            ()     (),//bits defined
    //.      o_hio_rx_dsk_done                              ()     (),//bits defined
    //.      o_hio_rx_am_lock                               ()     (),//bits defined
    //.      o_hio_rx_pcs_fully_aligned                     ()     (),//bits defined
    //.      o_hio_hi_ber                                   ()     (),//bits defined
    //.      o_hio_rx_pcs_internal_err                      ()     (),//bits defined
    //.      o_hio_tx_fifo_status_fifo_wr_pfull             ()     (),//bits defined
    //.      o_hio_tx_fifo_status_fifo_pempty               ()     (),//bits defined
    //.      o_hio_rx_fifo_status_fifo_pempty               ()     (),//bits defined
    //.      o_hio_rx_fifo_status_fifo_wr_pfull             ()     (),//bits defined
    //.      o_hio_rx_fifo_status_fifo_empty                ()     (),//bits defined
    //.      o_hio_tx_fifo_status_fifo_empty                ()     (),//bits defined
    //.      o_hio_rx_fifo_status_gb_restarted              ()     (),//bits defined
    //.      o_hio_tx_fifo_status_gb_restarted                        //bits defined 

    .    i_hio_txdata_async                               (p0_i_hio_txdata_async),   
    .    i_hio_txdata_direct                              ('0),   
    .    o_hio_rxdata_async                               (p0_o_hio_rxdata_async),    
    .    o_hio_rxdata_direct                              (),

    
//KAHUAT_EDIT
//    .    i_ch0_tx_data   ('0),                             
//    .    i_ch1_tx_data   ('0),                             
//    .    i_ch2_tx_data   ('0),                             
//    .    i_ch3_tx_data   ('0),                             
//    .    i_ch4_tx_data   ('0),                             
//    .    i_ch5_tx_data   ('0),                             //KAHUAT_EDIT
//    .    i_ch6_tx_data   ('0),                             //KAHUAT_EDIT
//    .    i_ch7_tx_data   ('0),                             //KAHUAT_EDIT
//    .    i_ch8_tx_data   ('0),                             //KAHUAT_EDIT
    .     i_pin_perst_n    (p0_pin_perst_n_i),
    .     i_pin_perst_n_1  (p0_pin_perst_n_1_i),    
//    .     o_ch0_rx_data    (),                             
//    .     o_ch1_rx_data    (),                             
//    .     o_ch2_rx_data    (),                             
//    .     o_ch3_rx_data    (),                             
//    .     o_ch4_rx_data    (),                             
//    .     o_ch5_rx_data    (),                             //KAHUAT_EDIT
//    .     o_ch6_rx_data    (),                             //KAHUAT_EDIT
//    .     o_ch7_rx_data    (),                             //KAHUAT_EDIT
//    .     o_ch8_rx_data    (),                             //KAHUAT_EDIT

        
    .     i_refclk_tx_p           (refclk0),
//    .     i_refclk_tx_n           (refclk0_n),//can derive as negated i_refclk_tx_p
    .     i_syspll_c0_clk         (p0_i_syspll_c0_clk),//connect to output of syspll
    .     i_syspll_c1_clk         ('0),
    .     i_syspll_c2_clk         ('0),
    .     i_flux_clk              (i_flux_clk[0]),
    .     i_flux_clk_1            ('0),
    .     i_refclk_rx_p           (refclk0),
//    .     i_refclk_rx_n           (refclk0_n),
    .     i_ss_vccl_syspll_locked (p0_i_ss_vccl_syspll_locked)  //connect to locked signal of syspll output

    )
    ;//hal_top instantion end


// x8 pcie HAL top instantiation

  altera_std_synchronizer u_axi_st_areset_n_axi_st_clk_sync
  (
     .clk      (p0_axi_st_clk),
     .reset_n  (p0_axi_st_areset_n),
     .din      (1'b1),
     .dout     (p0_axi_st_areset_n_axi_clk_sync)
  );

  altera_std_synchronizer u_axi_lite_areset_n_axi_lite_clk_sync
  (
     .clk      (p0_axi_lite_clk),
     .reset_n  (p0_axi_lite_areset_n),
     .din      (1'b1),
     .dout     (p0_axi_lite_areset_n_axi_clk_sync)
  );


sm_pcie_sip_top # ( 
  //SM QHIP sm_pcie_sip_top parameter 
  //`include "intel_pcie_sm_qhip_ast_qhip_parameter_connection.iv"
  
   
   .device_family                                               (device_family),
   .core16_tdata_width_integer_hwtcl	                        (core16_tdata_width_integer_hwtcl),
   .core16_empty_width_integer_hwtcl                            (core16_empty_width_integer_hwtcl),
   .core8_tdata_width_integer_hwtcl	                        (core8_tdata_width_integer_hwtcl),
   .core8_empty_width_integer_hwtcl                             (core8_empty_width_integer_hwtcl),


   .ctop_core16_virtual_rp_ep_mode                               (ctop_core16_virtual_rp_ep_mode),
   .core16_virtual_tlp_bypass_en_hwtcl                           (core16_virtual_tlp_bypass_en_hwtcl),
   .core16_total_pf_count_width_hwtcl                            (core16_total_pf_count_width_hwtcl),
   .core16_total_vf_count_width_hwtcl                            (core16_total_vf_count_width_hwtcl),
   .core16_total_pf_count_hwtcl                                  (core16_total_pf_count_hwtcl),
   .core16_total_vf_count_hwtcl                                  (core16_total_vf_count_hwtcl),
   .ctop_core8_virtual_rp_ep_mode                                (ctop_core8_virtual_rp_ep_mode),
   .core8_virtual_tlp_bypass_en_hwtcl                            (core8_virtual_tlp_bypass_en_hwtcl),
   .core8_total_pf_count_width_hwtcl                             (core8_total_pf_count_width_hwtcl),
   .core8_total_vf_count_width_hwtcl                             (core8_total_vf_count_width_hwtcl),
   .core8_total_pf_count_hwtcl                                   (core8_total_pf_count_hwtcl),
   .core8_total_vf_count_hwtcl                                   (core8_total_vf_count_hwtcl),


   // PCS Reconfig
   .PCS_CONFIG_EN                                               (PCS_CONFIG_EN),
   .core16_hip_reconfig_hwtcl                                   (core16_hip_reconfig_hwtcl),
   .core8_hip_reconfig_hwtcl                                    (core8_hip_reconfig_hwtcl),

   // rx_buffer_limit
   .core16_enable_rx_buffer_limit_ports_hwtcl                  (core16_enable_rx_buffer_limit_ports_hwtcl),
   .core8_enable_rx_buffer_limit_ports_hwtcl                   (core8_enable_rx_buffer_limit_ports_hwtcl),

   // PTM
   .core16_virtual_ptm_hwtcl                                     (core16_virtual_ptm_hwtcl),
   .core8_virtual_ptm_hwtcl                                      (core8_virtual_ptm_hwtcl),

   // ARI_ACS_FUN_GRP_CAP
   .ctop_core16_pf0_ari_acs_fun_grp_cap                          (ctop_core16_pf0_ari_acs_fun_grp_cap), 
   .ctop_core8_pf0_ari_acs_fun_grp_cap                           (ctop_core8_pf0_ari_acs_fun_grp_cap), 

   // Debug Toolkit
   .debug_toolkit_hwtcl                                   (debug_toolkit_hwtcl),
   .enable_pciess_register_access_hwtcl                   (enable_pciess_register_access_hwtcl),
   .link_insp_en_hwtcl                                    (link_insp_en_hwtcl),
   .link_insp_avmm_en_hwtcl                               (link_insp_avmm_en_hwtcl),

   //Independent pin perst
   .ctop_virtual_x16_perst_sel                                  (ctop_virtual_x16_perst_sel),
   .ctop_virtual_x8_perst_sel                                  (ctop_virtual_x8_perst_sel),

   // ECC enable	   
   .core16_enable_ecc_hwtcl                                    (core16_enable_ecc_hwtcl),
   .core8_enable_ecc_hwtcl                                     (core8_enable_ecc_hwtcl),

   //USER_MODE_TO_PLD_IN_USE
   .core16_user_mode_to_pld_in_use_hwtcl                       (core16_user_mode_to_pld_in_use_hwtcl),
   .core8_user_mode_to_pld_in_use_hwtcl                        (core8_user_mode_to_pld_in_use_hwtcl),

   // pld_warm_rst_rdy
   .core16_enable_pld_warm_rst_rdy_hwtcl                       (core16_enable_pld_warm_rst_rdy_hwtcl),
   .core8_enable_pld_warm_rst_rdy_hwtcl                        (core8_enable_pld_warm_rst_rdy_hwtcl),

   // max payload
   .ctop_core16_virtual_maxpayload_size                        (ctop_core16_virtual_maxpayload_size ),
   .ctop_core8_virtual_maxpayload_size                         (ctop_core8_virtual_maxpayload_size ),
   
   // ast_parity
   .core16_use_ast_parity_hwtcl                                (core16_use_ast_parity_hwtcl         ),
   .core8_use_ast_parity_hwtcl                                 (core8_use_ast_parity_hwtcl         ),
   
   // Power Management
   .core16_enable_power_mgnt_intf_hwtcl                        (core16_enable_power_mgnt_intf_hwtcl ),
   .core8_enable_power_mgnt_intf_hwtcl                         (core8_enable_power_mgnt_intf_hwtcl ),

   // Error Interface
   .core16_enable_error_intf_hwtcl                             (core16_enable_error_intf_hwtcl      ),
   .core8_enable_error_intf_hwtcl                              (core8_enable_error_intf_hwtcl      ),
   
   // FLR
   .core16_flr_cap_hwtcl                                       (core16_flr_cap_hwtcl                ),
   .core8_flr_cap_hwtcl                                        (core8_flr_cap_hwtcl                ),
   
   // cpl_timeout
   .core16_enable_cpl_timeout_hwtcl                            (core16_enable_cpl_timeout_hwtcl     ),
   .core8_enable_cpl_timeout_hwtcl                             (core8_enable_cpl_timeout_hwtcl     ),
   
   // multi_func
   .core16_enable_multi_func_hwtcl                               (core16_enable_multi_func_hwtcl        ),
   .core8_enable_multi_func_hwtcl                                (core8_enable_multi_func_hwtcl        ),
   
   // SRIOV
   .core16_enable_sriov_hwtcl                                    (core16_enable_sriov_hwtcl             ),
   .core8_enable_sriov_hwtcl                                     (core8_enable_sriov_hwtcl             ),
   
   // 10-bit tag
   
   // CEB
   .core16_pf_ceb_pointer_addr_hwtcl                             (core16_pf_ceb_pointer_addr_hwtcl),
   .core16_vf_ceb_pointer_addr_hwtcl                             (core16_vf_ceb_pointer_addr_hwtcl),
   .core8_pf_ceb_pointer_addr_hwtcl                              (core8_pf_ceb_pointer_addr_hwtcl),
   .core8_vf_ceb_pointer_addr_hwtcl                              (core8_vf_ceb_pointer_addr_hwtcl),
   
   // Virtio
   .core16_enable_virtio_hwtcl                                   (core16_enable_virtio_hwtcl),
   .core16_virtio_start_byte_address_hwtcl                       (core16_virtio_start_byte_address_hwtcl),
   .core16_pf0_virtio_capability_present_hwtcl                   (core16_pf0_virtio_capability_present_hwtcl),
   .core16_pf0_virtio_device_specific_cap_present_hwtcl          (core16_pf0_virtio_device_specific_cap_present_hwtcl),
   .core16_pf0_virtio_cmn_config_bar_indicator_hwtcl             (core16_pf0_virtio_cmn_config_bar_indicator_hwtcl),
   .core16_pf0_virtio_cmn_config_bar_offset_hwtcl                (core16_pf0_virtio_cmn_config_bar_offset_hwtcl),
   .core16_pf0_virtio_cmn_config_structure_length_hwtcl          (core16_pf0_virtio_cmn_config_structure_length_hwtcl),
   .core16_pf0_virtio_notification_bar_indicator_hwtcl           (core16_pf0_virtio_notification_bar_indicator_hwtcl),
   .core16_pf0_virtio_notification_bar_offset_hwtcl              (core16_pf0_virtio_notification_bar_offset_hwtcl),
   .core16_pf0_virtio_notification_structure_length_hwtcl        (core16_pf0_virtio_notification_structure_length_hwtcl),
   .core16_pf0_virtio_notify_off_multiplier_hwtcl                (core16_pf0_virtio_notify_off_multiplier_hwtcl),
   .core16_pf0_virtio_isrstatus_bar_indicator_hwtcl              (core16_pf0_virtio_isrstatus_bar_indicator_hwtcl),
   .core16_pf0_virtio_isrstatus_bar_offset_hwtcl                 (core16_pf0_virtio_isrstatus_bar_offset_hwtcl),
   .core16_pf0_virtio_isrstatus_structure_length_hwtcl           (core16_pf0_virtio_isrstatus_structure_length_hwtcl),
   .core16_pf0_virtio_devspecific_bar_indicator_hwtcl            (core16_pf0_virtio_devspecific_bar_indicator_hwtcl),
   .core16_pf0_virtio_devspecific_bar_offset_hwtcl               (core16_pf0_virtio_devspecific_bar_offset_hwtcl),
   .core16_pf0_virtio_devspecific_structure_length_hwtcl         (core16_pf0_virtio_devspecific_structure_length_hwtcl),
   .core16_pf0_virtio_pciconfig_access_bar_indicator_hwtcl       (core16_pf0_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core16_pf0_virtio_pciconfig_access_bar_offset_hwtcl          (core16_pf0_virtio_pciconfig_access_bar_offset_hwtcl),
   .core16_pf0_virtio_pciconfig_access_structure_length_hwtcl    (core16_pf0_virtio_pciconfig_access_structure_length_hwtcl),
   .core16_pf1_virtio_capability_present_hwtcl                   (core16_pf1_virtio_capability_present_hwtcl),
   .core16_pf1_virtio_device_specific_cap_present_hwtcl          (core16_pf1_virtio_device_specific_cap_present_hwtcl),
   .core16_pf1_virtio_cmn_config_bar_indicator_hwtcl             (core16_pf1_virtio_cmn_config_bar_indicator_hwtcl),
   .core16_pf1_virtio_cmn_config_bar_offset_hwtcl                (core16_pf1_virtio_cmn_config_bar_offset_hwtcl),
   .core16_pf1_virtio_cmn_config_structure_length_hwtcl          (core16_pf1_virtio_cmn_config_structure_length_hwtcl),
   .core16_pf1_virtio_notification_bar_indicator_hwtcl           (core16_pf1_virtio_notification_bar_indicator_hwtcl),
   .core16_pf1_virtio_notification_bar_offset_hwtcl              (core16_pf1_virtio_notification_bar_offset_hwtcl),
   .core16_pf1_virtio_notification_structure_length_hwtcl        (core16_pf1_virtio_notification_structure_length_hwtcl),
   .core16_pf1_virtio_notify_off_multiplier_hwtcl                (core16_pf1_virtio_notify_off_multiplier_hwtcl),
   .core16_pf1_virtio_isrstatus_bar_indicator_hwtcl              (core16_pf1_virtio_isrstatus_bar_indicator_hwtcl),
   .core16_pf1_virtio_isrstatus_bar_offset_hwtcl                 (core16_pf1_virtio_isrstatus_bar_offset_hwtcl),
   .core16_pf1_virtio_isrstatus_structure_length_hwtcl           (core16_pf1_virtio_isrstatus_structure_length_hwtcl),
   .core16_pf1_virtio_devspecific_bar_indicator_hwtcl            (core16_pf1_virtio_devspecific_bar_indicator_hwtcl),
   .core16_pf1_virtio_devspecific_bar_offset_hwtcl               (core16_pf1_virtio_devspecific_bar_offset_hwtcl),
   .core16_pf1_virtio_devspecific_structure_length_hwtcl         (core16_pf1_virtio_devspecific_structure_length_hwtcl),
   .core16_pf1_virtio_pciconfig_access_bar_indicator_hwtcl       (core16_pf1_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core16_pf1_virtio_pciconfig_access_bar_offset_hwtcl          (core16_pf1_virtio_pciconfig_access_bar_offset_hwtcl),
   .core16_pf1_virtio_pciconfig_access_structure_length_hwtcl    (core16_pf1_virtio_pciconfig_access_structure_length_hwtcl),
   .core16_pf2_virtio_capability_present_hwtcl                   (core16_pf2_virtio_capability_present_hwtcl),
   .core16_pf2_virtio_device_specific_cap_present_hwtcl          (core16_pf2_virtio_device_specific_cap_present_hwtcl),
   .core16_pf2_virtio_cmn_config_bar_indicator_hwtcl             (core16_pf2_virtio_cmn_config_bar_indicator_hwtcl),
   .core16_pf2_virtio_cmn_config_bar_offset_hwtcl                (core16_pf2_virtio_cmn_config_bar_offset_hwtcl),
   .core16_pf2_virtio_cmn_config_structure_length_hwtcl          (core16_pf2_virtio_cmn_config_structure_length_hwtcl),
   .core16_pf2_virtio_notification_bar_indicator_hwtcl           (core16_pf2_virtio_notification_bar_indicator_hwtcl),
   .core16_pf2_virtio_notification_bar_offset_hwtcl              (core16_pf2_virtio_notification_bar_offset_hwtcl),
   .core16_pf2_virtio_notification_structure_length_hwtcl        (core16_pf2_virtio_notification_structure_length_hwtcl),
   .core16_pf2_virtio_notify_off_multiplier_hwtcl                (core16_pf2_virtio_notify_off_multiplier_hwtcl),
   .core16_pf2_virtio_isrstatus_bar_indicator_hwtcl              (core16_pf2_virtio_isrstatus_bar_indicator_hwtcl),
   .core16_pf2_virtio_isrstatus_bar_offset_hwtcl                 (core16_pf2_virtio_isrstatus_bar_offset_hwtcl),
   .core16_pf2_virtio_isrstatus_structure_length_hwtcl           (core16_pf2_virtio_isrstatus_structure_length_hwtcl),
   .core16_pf2_virtio_devspecific_bar_indicator_hwtcl            (core16_pf2_virtio_devspecific_bar_indicator_hwtcl),
   .core16_pf2_virtio_devspecific_bar_offset_hwtcl               (core16_pf2_virtio_devspecific_bar_offset_hwtcl),
   .core16_pf2_virtio_devspecific_structure_length_hwtcl         (core16_pf2_virtio_devspecific_structure_length_hwtcl),
   .core16_pf2_virtio_pciconfig_access_bar_indicator_hwtcl       (core16_pf2_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core16_pf2_virtio_pciconfig_access_bar_offset_hwtcl          (core16_pf2_virtio_pciconfig_access_bar_offset_hwtcl),
   .core16_pf2_virtio_pciconfig_access_structure_length_hwtcl    (core16_pf2_virtio_pciconfig_access_structure_length_hwtcl),
   .core16_pf3_virtio_capability_present_hwtcl                   (core16_pf3_virtio_capability_present_hwtcl),
   .core16_pf3_virtio_device_specific_cap_present_hwtcl          (core16_pf3_virtio_device_specific_cap_present_hwtcl),
   .core16_pf3_virtio_cmn_config_bar_indicator_hwtcl             (core16_pf3_virtio_cmn_config_bar_indicator_hwtcl),
   .core16_pf3_virtio_cmn_config_bar_offset_hwtcl                (core16_pf3_virtio_cmn_config_bar_offset_hwtcl),
   .core16_pf3_virtio_cmn_config_structure_length_hwtcl          (core16_pf3_virtio_cmn_config_structure_length_hwtcl),
   .core16_pf3_virtio_notification_bar_indicator_hwtcl           (core16_pf3_virtio_notification_bar_indicator_hwtcl),
   .core16_pf3_virtio_notification_bar_offset_hwtcl              (core16_pf3_virtio_notification_bar_offset_hwtcl),
   .core16_pf3_virtio_notification_structure_length_hwtcl        (core16_pf3_virtio_notification_structure_length_hwtcl),
   .core16_pf3_virtio_notify_off_multiplier_hwtcl                (core16_pf3_virtio_notify_off_multiplier_hwtcl),
   .core16_pf3_virtio_isrstatus_bar_indicator_hwtcl              (core16_pf3_virtio_isrstatus_bar_indicator_hwtcl),
   .core16_pf3_virtio_isrstatus_bar_offset_hwtcl                 (core16_pf3_virtio_isrstatus_bar_offset_hwtcl),
   .core16_pf3_virtio_isrstatus_structure_length_hwtcl           (core16_pf3_virtio_isrstatus_structure_length_hwtcl),
   .core16_pf3_virtio_devspecific_bar_indicator_hwtcl            (core16_pf3_virtio_devspecific_bar_indicator_hwtcl),
   .core16_pf3_virtio_devspecific_bar_offset_hwtcl               (core16_pf3_virtio_devspecific_bar_offset_hwtcl),
   .core16_pf3_virtio_devspecific_structure_length_hwtcl         (core16_pf3_virtio_devspecific_structure_length_hwtcl),
   .core16_pf3_virtio_pciconfig_access_bar_indicator_hwtcl       (core16_pf3_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core16_pf3_virtio_pciconfig_access_bar_offset_hwtcl          (core16_pf3_virtio_pciconfig_access_bar_offset_hwtcl),
   .core16_pf3_virtio_pciconfig_access_structure_length_hwtcl    (core16_pf3_virtio_pciconfig_access_structure_length_hwtcl),
   .core16_pf0vf_virtio_capability_present_hwtcl                 (core16_pf0vf_virtio_capability_present_hwtcl),
   .core16_pf0vf_virtio_device_specific_cap_present_hwtcl        (core16_pf0vf_virtio_device_specific_cap_present_hwtcl),
   .core16_pf0vf_virtio_cmn_config_bar_indicator_hwtcl           (core16_pf0vf_virtio_cmn_config_bar_indicator_hwtcl),
   .core16_pf0vf_virtio_cmn_config_bar_offset_hwtcl              (core16_pf0vf_virtio_cmn_config_bar_offset_hwtcl),
   .core16_pf0vf_virtio_cmn_config_structure_length_hwtcl        (core16_pf0vf_virtio_cmn_config_structure_length_hwtcl),
   .core16_pf0vf_virtio_notification_bar_indicator_hwtcl         (core16_pf0vf_virtio_notification_bar_indicator_hwtcl),
   .core16_pf0vf_virtio_notification_bar_offset_hwtcl            (core16_pf0vf_virtio_notification_bar_offset_hwtcl),
   .core16_pf0vf_virtio_notification_structure_length_hwtcl      (core16_pf0vf_virtio_notification_structure_length_hwtcl),
   .core16_pf0vf_virtio_notify_off_multiplier_hwtcl              (core16_pf0vf_virtio_notify_off_multiplier_hwtcl),
   .core16_pf0vf_virtio_isrstatus_bar_indicator_hwtcl            (core16_pf0vf_virtio_isrstatus_bar_indicator_hwtcl),
   .core16_pf0vf_virtio_isrstatus_bar_offset_hwtcl               (core16_pf0vf_virtio_isrstatus_bar_offset_hwtcl),
   .core16_pf0vf_virtio_isrstatus_structure_length_hwtcl         (core16_pf0vf_virtio_isrstatus_structure_length_hwtcl),
   .core16_pf0vf_virtio_devspecific_bar_indicator_hwtcl          (core16_pf0vf_virtio_devspecific_bar_indicator_hwtcl),
   .core16_pf0vf_virtio_devspecific_bar_offset_hwtcl             (core16_pf0vf_virtio_devspecific_bar_offset_hwtcl),
   .core16_pf0vf_virtio_devspecific_structure_length_hwtcl       (core16_pf0vf_virtio_devspecific_structure_length_hwtcl),
   .core16_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl     (core16_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core16_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl        (core16_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl),
   .core16_pf0vf_virtio_pciconfig_access_structure_length_hwtcl  (core16_pf0vf_virtio_pciconfig_access_structure_length_hwtcl),
   .core16_pf1vf_virtio_capability_present_hwtcl                 (core16_pf1vf_virtio_capability_present_hwtcl),
   .core16_pf1vf_virtio_device_specific_cap_present_hwtcl        (core16_pf1vf_virtio_device_specific_cap_present_hwtcl),
   .core16_pf1vf_virtio_cmn_config_bar_indicator_hwtcl           (core16_pf1vf_virtio_cmn_config_bar_indicator_hwtcl),
   .core16_pf1vf_virtio_cmn_config_bar_offset_hwtcl              (core16_pf1vf_virtio_cmn_config_bar_offset_hwtcl),
   .core16_pf1vf_virtio_cmn_config_structure_length_hwtcl        (core16_pf1vf_virtio_cmn_config_structure_length_hwtcl),
   .core16_pf1vf_virtio_notification_bar_indicator_hwtcl         (core16_pf1vf_virtio_notification_bar_indicator_hwtcl),
   .core16_pf1vf_virtio_notification_bar_offset_hwtcl            (core16_pf1vf_virtio_notification_bar_offset_hwtcl),
   .core16_pf1vf_virtio_notification_structure_length_hwtcl      (core16_pf1vf_virtio_notification_structure_length_hwtcl),
   .core16_pf1vf_virtio_notify_off_multiplier_hwtcl              (core16_pf1vf_virtio_notify_off_multiplier_hwtcl),
   .core16_pf1vf_virtio_isrstatus_bar_indicator_hwtcl            (core16_pf1vf_virtio_isrstatus_bar_indicator_hwtcl),
   .core16_pf1vf_virtio_isrstatus_bar_offset_hwtcl               (core16_pf1vf_virtio_isrstatus_bar_offset_hwtcl),
   .core16_pf1vf_virtio_isrstatus_structure_length_hwtcl         (core16_pf1vf_virtio_isrstatus_structure_length_hwtcl),
   .core16_pf1vf_virtio_devspecific_bar_indicator_hwtcl          (core16_pf1vf_virtio_devspecific_bar_indicator_hwtcl),
   .core16_pf1vf_virtio_devspecific_bar_offset_hwtcl             (core16_pf1vf_virtio_devspecific_bar_offset_hwtcl),
   .core16_pf1vf_virtio_devspecific_structure_length_hwtcl       (core16_pf1vf_virtio_devspecific_structure_length_hwtcl),
   .core16_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl     (core16_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core16_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl        (core16_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl),
   .core16_pf1vf_virtio_pciconfig_access_structure_length_hwtcl  (core16_pf1vf_virtio_pciconfig_access_structure_length_hwtcl),
   .core16_pf2vf_virtio_capability_present_hwtcl                 (core16_pf2vf_virtio_capability_present_hwtcl),
   .core16_pf2vf_virtio_device_specific_cap_present_hwtcl        (core16_pf2vf_virtio_device_specific_cap_present_hwtcl),
   .core16_pf2vf_virtio_cmn_config_bar_indicator_hwtcl           (core16_pf2vf_virtio_cmn_config_bar_indicator_hwtcl),
   .core16_pf2vf_virtio_cmn_config_bar_offset_hwtcl              (core16_pf2vf_virtio_cmn_config_bar_offset_hwtcl),
   .core16_pf2vf_virtio_cmn_config_structure_length_hwtcl        (core16_pf2vf_virtio_cmn_config_structure_length_hwtcl),
   .core16_pf2vf_virtio_notification_bar_indicator_hwtcl         (core16_pf2vf_virtio_notification_bar_indicator_hwtcl),
   .core16_pf2vf_virtio_notification_bar_offset_hwtcl            (core16_pf2vf_virtio_notification_bar_offset_hwtcl),
   .core16_pf2vf_virtio_notification_structure_length_hwtcl      (core16_pf2vf_virtio_notification_structure_length_hwtcl),
   .core16_pf2vf_virtio_notify_off_multiplier_hwtcl              (core16_pf2vf_virtio_notify_off_multiplier_hwtcl),
   .core16_pf2vf_virtio_isrstatus_bar_indicator_hwtcl            (core16_pf2vf_virtio_isrstatus_bar_indicator_hwtcl),
   .core16_pf2vf_virtio_isrstatus_bar_offset_hwtcl               (core16_pf2vf_virtio_isrstatus_bar_offset_hwtcl),
   .core16_pf2vf_virtio_isrstatus_structure_length_hwtcl         (core16_pf2vf_virtio_isrstatus_structure_length_hwtcl),
   .core16_pf2vf_virtio_devspecific_bar_indicator_hwtcl          (core16_pf2vf_virtio_devspecific_bar_indicator_hwtcl),
   .core16_pf2vf_virtio_devspecific_bar_offset_hwtcl             (core16_pf2vf_virtio_devspecific_bar_offset_hwtcl),
   .core16_pf2vf_virtio_devspecific_structure_length_hwtcl       (core16_pf2vf_virtio_devspecific_structure_length_hwtcl),
   .core16_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl     (core16_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core16_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl        (core16_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl),
   .core16_pf2vf_virtio_pciconfig_access_structure_length_hwtcl  (core16_pf2vf_virtio_pciconfig_access_structure_length_hwtcl),
   .core16_pf3vf_virtio_capability_present_hwtcl                 (core16_pf3vf_virtio_capability_present_hwtcl),
   .core16_pf3vf_virtio_device_specific_cap_present_hwtcl        (core16_pf3vf_virtio_device_specific_cap_present_hwtcl),
   .core16_pf3vf_virtio_cmn_config_bar_indicator_hwtcl           (core16_pf3vf_virtio_cmn_config_bar_indicator_hwtcl),
   .core16_pf3vf_virtio_cmn_config_bar_offset_hwtcl              (core16_pf3vf_virtio_cmn_config_bar_offset_hwtcl),
   .core16_pf3vf_virtio_cmn_config_structure_length_hwtcl        (core16_pf3vf_virtio_cmn_config_structure_length_hwtcl),
   .core16_pf3vf_virtio_notification_bar_indicator_hwtcl         (core16_pf3vf_virtio_notification_bar_indicator_hwtcl),
   .core16_pf3vf_virtio_notification_bar_offset_hwtcl            (core16_pf3vf_virtio_notification_bar_offset_hwtcl),
   .core16_pf3vf_virtio_notification_structure_length_hwtcl      (core16_pf3vf_virtio_notification_structure_length_hwtcl),
   .core16_pf3vf_virtio_notify_off_multiplier_hwtcl              (core16_pf3vf_virtio_notify_off_multiplier_hwtcl),
   .core16_pf3vf_virtio_isrstatus_bar_indicator_hwtcl            (core16_pf3vf_virtio_isrstatus_bar_indicator_hwtcl),
   .core16_pf3vf_virtio_isrstatus_bar_offset_hwtcl               (core16_pf3vf_virtio_isrstatus_bar_offset_hwtcl),
   .core16_pf3vf_virtio_isrstatus_structure_length_hwtcl         (core16_pf3vf_virtio_isrstatus_structure_length_hwtcl),
   .core16_pf3vf_virtio_devspecific_bar_indicator_hwtcl          (core16_pf3vf_virtio_devspecific_bar_indicator_hwtcl),
   .core16_pf3vf_virtio_devspecific_bar_offset_hwtcl             (core16_pf3vf_virtio_devspecific_bar_offset_hwtcl),
   .core16_pf3vf_virtio_devspecific_structure_length_hwtcl       (core16_pf3vf_virtio_devspecific_structure_length_hwtcl),
   .core16_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl     (core16_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core16_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl        (core16_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl),
   .core16_pf3vf_virtio_pciconfig_access_structure_length_hwtcl  (core16_pf3vf_virtio_pciconfig_access_structure_length_hwtcl),
   .core16_pf0_vf_count_hwtcl                                    (core16_pf0_vf_count_hwtcl),
   .core16_pf1_vf_count_hwtcl                                    (core16_pf1_vf_count_hwtcl),
   .core16_pf2_vf_count_hwtcl                                    (core16_pf2_vf_count_hwtcl),
   .core16_pf3_vf_count_hwtcl                                    (core16_pf3_vf_count_hwtcl),


   .core16_topology                         (core16_topology),

   .core8_enable_virtio_hwtcl                                   (core8_enable_virtio_hwtcl),
   .core8_virtio_start_byte_address_hwtcl                       (core8_virtio_start_byte_address_hwtcl),
   .core8_pf0_virtio_capability_present_hwtcl                   (core8_pf0_virtio_capability_present_hwtcl),
   .core8_pf0_virtio_device_specific_cap_present_hwtcl          (core8_pf0_virtio_device_specific_cap_present_hwtcl),
   .core8_pf0_virtio_cmn_config_bar_indicator_hwtcl             (core8_pf0_virtio_cmn_config_bar_indicator_hwtcl),
   .core8_pf0_virtio_cmn_config_bar_offset_hwtcl                (core8_pf0_virtio_cmn_config_bar_offset_hwtcl),
   .core8_pf0_virtio_cmn_config_structure_length_hwtcl          (core8_pf0_virtio_cmn_config_structure_length_hwtcl),
   .core8_pf0_virtio_notification_bar_indicator_hwtcl           (core8_pf0_virtio_notification_bar_indicator_hwtcl),
   .core8_pf0_virtio_notification_bar_offset_hwtcl              (core8_pf0_virtio_notification_bar_offset_hwtcl),
   .core8_pf0_virtio_notification_structure_length_hwtcl        (core8_pf0_virtio_notification_structure_length_hwtcl),
   .core8_pf0_virtio_notify_off_multiplier_hwtcl                (core8_pf0_virtio_notify_off_multiplier_hwtcl),
   .core8_pf0_virtio_isrstatus_bar_indicator_hwtcl              (core8_pf0_virtio_isrstatus_bar_indicator_hwtcl),
   .core8_pf0_virtio_isrstatus_bar_offset_hwtcl                 (core8_pf0_virtio_isrstatus_bar_offset_hwtcl),
   .core8_pf0_virtio_isrstatus_structure_length_hwtcl           (core8_pf0_virtio_isrstatus_structure_length_hwtcl),
   .core8_pf0_virtio_devspecific_bar_indicator_hwtcl            (core8_pf0_virtio_devspecific_bar_indicator_hwtcl),
   .core8_pf0_virtio_devspecific_bar_offset_hwtcl               (core8_pf0_virtio_devspecific_bar_offset_hwtcl),
   .core8_pf0_virtio_devspecific_structure_length_hwtcl         (core8_pf0_virtio_devspecific_structure_length_hwtcl),
   .core8_pf0_virtio_pciconfig_access_bar_indicator_hwtcl       (core8_pf0_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core8_pf0_virtio_pciconfig_access_bar_offset_hwtcl          (core8_pf0_virtio_pciconfig_access_bar_offset_hwtcl),
   .core8_pf0_virtio_pciconfig_access_structure_length_hwtcl    (core8_pf0_virtio_pciconfig_access_structure_length_hwtcl),
   .core8_pf1_virtio_capability_present_hwtcl                   (core8_pf1_virtio_capability_present_hwtcl),
   .core8_pf1_virtio_device_specific_cap_present_hwtcl          (core8_pf1_virtio_device_specific_cap_present_hwtcl),
   .core8_pf1_virtio_cmn_config_bar_indicator_hwtcl             (core8_pf1_virtio_cmn_config_bar_indicator_hwtcl),
   .core8_pf1_virtio_cmn_config_bar_offset_hwtcl                (core8_pf1_virtio_cmn_config_bar_offset_hwtcl),
   .core8_pf1_virtio_cmn_config_structure_length_hwtcl          (core8_pf1_virtio_cmn_config_structure_length_hwtcl),
   .core8_pf1_virtio_notification_bar_indicator_hwtcl           (core8_pf1_virtio_notification_bar_indicator_hwtcl),
   .core8_pf1_virtio_notification_bar_offset_hwtcl              (core8_pf1_virtio_notification_bar_offset_hwtcl),
   .core8_pf1_virtio_notification_structure_length_hwtcl        (core8_pf1_virtio_notification_structure_length_hwtcl),
   .core8_pf1_virtio_notify_off_multiplier_hwtcl                (core8_pf1_virtio_notify_off_multiplier_hwtcl),
   .core8_pf1_virtio_isrstatus_bar_indicator_hwtcl              (core8_pf1_virtio_isrstatus_bar_indicator_hwtcl),
   .core8_pf1_virtio_isrstatus_bar_offset_hwtcl                 (core8_pf1_virtio_isrstatus_bar_offset_hwtcl),
   .core8_pf1_virtio_isrstatus_structure_length_hwtcl           (core8_pf1_virtio_isrstatus_structure_length_hwtcl),
   .core8_pf1_virtio_devspecific_bar_indicator_hwtcl            (core8_pf1_virtio_devspecific_bar_indicator_hwtcl),
   .core8_pf1_virtio_devspecific_bar_offset_hwtcl               (core8_pf1_virtio_devspecific_bar_offset_hwtcl),
   .core8_pf1_virtio_devspecific_structure_length_hwtcl         (core8_pf1_virtio_devspecific_structure_length_hwtcl),
   .core8_pf1_virtio_pciconfig_access_bar_indicator_hwtcl       (core8_pf1_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core8_pf1_virtio_pciconfig_access_bar_offset_hwtcl          (core8_pf1_virtio_pciconfig_access_bar_offset_hwtcl),
   .core8_pf1_virtio_pciconfig_access_structure_length_hwtcl    (core8_pf1_virtio_pciconfig_access_structure_length_hwtcl),
   .core8_pf2_virtio_capability_present_hwtcl                   (core8_pf2_virtio_capability_present_hwtcl),
   .core8_pf2_virtio_device_specific_cap_present_hwtcl          (core8_pf2_virtio_device_specific_cap_present_hwtcl),
   .core8_pf2_virtio_cmn_config_bar_indicator_hwtcl             (core8_pf2_virtio_cmn_config_bar_indicator_hwtcl),
   .core8_pf2_virtio_cmn_config_bar_offset_hwtcl                (core8_pf2_virtio_cmn_config_bar_offset_hwtcl),
   .core8_pf2_virtio_cmn_config_structure_length_hwtcl          (core8_pf2_virtio_cmn_config_structure_length_hwtcl),
   .core8_pf2_virtio_notification_bar_indicator_hwtcl           (core8_pf2_virtio_notification_bar_indicator_hwtcl),
   .core8_pf2_virtio_notification_bar_offset_hwtcl              (core8_pf2_virtio_notification_bar_offset_hwtcl),
   .core8_pf2_virtio_notification_structure_length_hwtcl        (core8_pf2_virtio_notification_structure_length_hwtcl),
   .core8_pf2_virtio_notify_off_multiplier_hwtcl                (core8_pf2_virtio_notify_off_multiplier_hwtcl),
   .core8_pf2_virtio_isrstatus_bar_indicator_hwtcl              (core8_pf2_virtio_isrstatus_bar_indicator_hwtcl),
   .core8_pf2_virtio_isrstatus_bar_offset_hwtcl                 (core8_pf2_virtio_isrstatus_bar_offset_hwtcl),
   .core8_pf2_virtio_isrstatus_structure_length_hwtcl           (core8_pf2_virtio_isrstatus_structure_length_hwtcl),
   .core8_pf2_virtio_devspecific_bar_indicator_hwtcl            (core8_pf2_virtio_devspecific_bar_indicator_hwtcl),
   .core8_pf2_virtio_devspecific_bar_offset_hwtcl               (core8_pf2_virtio_devspecific_bar_offset_hwtcl),
   .core8_pf2_virtio_devspecific_structure_length_hwtcl         (core8_pf2_virtio_devspecific_structure_length_hwtcl),
   .core8_pf2_virtio_pciconfig_access_bar_indicator_hwtcl       (core8_pf2_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core8_pf2_virtio_pciconfig_access_bar_offset_hwtcl          (core8_pf2_virtio_pciconfig_access_bar_offset_hwtcl),
   .core8_pf2_virtio_pciconfig_access_structure_length_hwtcl    (core8_pf2_virtio_pciconfig_access_structure_length_hwtcl),
   .core8_pf3_virtio_capability_present_hwtcl                   (core8_pf3_virtio_capability_present_hwtcl),
   .core8_pf3_virtio_device_specific_cap_present_hwtcl          (core8_pf3_virtio_device_specific_cap_present_hwtcl),
   .core8_pf3_virtio_cmn_config_bar_indicator_hwtcl             (core8_pf3_virtio_cmn_config_bar_indicator_hwtcl),
   .core8_pf3_virtio_cmn_config_bar_offset_hwtcl                (core8_pf3_virtio_cmn_config_bar_offset_hwtcl),
   .core8_pf3_virtio_cmn_config_structure_length_hwtcl          (core8_pf3_virtio_cmn_config_structure_length_hwtcl),
   .core8_pf3_virtio_notification_bar_indicator_hwtcl           (core8_pf3_virtio_notification_bar_indicator_hwtcl),
   .core8_pf3_virtio_notification_bar_offset_hwtcl              (core8_pf3_virtio_notification_bar_offset_hwtcl),
   .core8_pf3_virtio_notification_structure_length_hwtcl        (core8_pf3_virtio_notification_structure_length_hwtcl),
   .core8_pf3_virtio_notify_off_multiplier_hwtcl                (core8_pf3_virtio_notify_off_multiplier_hwtcl),
   .core8_pf3_virtio_isrstatus_bar_indicator_hwtcl              (core8_pf3_virtio_isrstatus_bar_indicator_hwtcl),
   .core8_pf3_virtio_isrstatus_bar_offset_hwtcl                 (core8_pf3_virtio_isrstatus_bar_offset_hwtcl),
   .core8_pf3_virtio_isrstatus_structure_length_hwtcl           (core8_pf3_virtio_isrstatus_structure_length_hwtcl),
   .core8_pf3_virtio_devspecific_bar_indicator_hwtcl            (core8_pf3_virtio_devspecific_bar_indicator_hwtcl),
   .core8_pf3_virtio_devspecific_bar_offset_hwtcl               (core8_pf3_virtio_devspecific_bar_offset_hwtcl),
   .core8_pf3_virtio_devspecific_structure_length_hwtcl         (core8_pf3_virtio_devspecific_structure_length_hwtcl),
   .core8_pf3_virtio_pciconfig_access_bar_indicator_hwtcl       (core8_pf3_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core8_pf3_virtio_pciconfig_access_bar_offset_hwtcl          (core8_pf3_virtio_pciconfig_access_bar_offset_hwtcl),
   .core8_pf3_virtio_pciconfig_access_structure_length_hwtcl    (core8_pf3_virtio_pciconfig_access_structure_length_hwtcl),
   .core8_pf0vf_virtio_capability_present_hwtcl                 (core8_pf0vf_virtio_capability_present_hwtcl),
   .core8_pf0vf_virtio_device_specific_cap_present_hwtcl        (core8_pf0vf_virtio_device_specific_cap_present_hwtcl),
   .core8_pf0vf_virtio_cmn_config_bar_indicator_hwtcl           (core8_pf0vf_virtio_cmn_config_bar_indicator_hwtcl),
   .core8_pf0vf_virtio_cmn_config_bar_offset_hwtcl              (core8_pf0vf_virtio_cmn_config_bar_offset_hwtcl),
   .core8_pf0vf_virtio_cmn_config_structure_length_hwtcl        (core8_pf0vf_virtio_cmn_config_structure_length_hwtcl),
   .core8_pf0vf_virtio_notification_bar_indicator_hwtcl         (core8_pf0vf_virtio_notification_bar_indicator_hwtcl),
   .core8_pf0vf_virtio_notification_bar_offset_hwtcl            (core8_pf0vf_virtio_notification_bar_offset_hwtcl),
   .core8_pf0vf_virtio_notification_structure_length_hwtcl      (core8_pf0vf_virtio_notification_structure_length_hwtcl),
   .core8_pf0vf_virtio_notify_off_multiplier_hwtcl              (core8_pf0vf_virtio_notify_off_multiplier_hwtcl),
   .core8_pf0vf_virtio_isrstatus_bar_indicator_hwtcl            (core8_pf0vf_virtio_isrstatus_bar_indicator_hwtcl),
   .core8_pf0vf_virtio_isrstatus_bar_offset_hwtcl               (core8_pf0vf_virtio_isrstatus_bar_offset_hwtcl),
   .core8_pf0vf_virtio_isrstatus_structure_length_hwtcl         (core8_pf0vf_virtio_isrstatus_structure_length_hwtcl),
   .core8_pf0vf_virtio_devspecific_bar_indicator_hwtcl          (core8_pf0vf_virtio_devspecific_bar_indicator_hwtcl),
   .core8_pf0vf_virtio_devspecific_bar_offset_hwtcl             (core8_pf0vf_virtio_devspecific_bar_offset_hwtcl),
   .core8_pf0vf_virtio_devspecific_structure_length_hwtcl       (core8_pf0vf_virtio_devspecific_structure_length_hwtcl),
   .core8_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl     (core8_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core8_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl        (core8_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl),
   .core8_pf0vf_virtio_pciconfig_access_structure_length_hwtcl  (core8_pf0vf_virtio_pciconfig_access_structure_length_hwtcl),
   .core8_pf1vf_virtio_capability_present_hwtcl                 (core8_pf1vf_virtio_capability_present_hwtcl),
   .core8_pf1vf_virtio_device_specific_cap_present_hwtcl        (core8_pf1vf_virtio_device_specific_cap_present_hwtcl),
   .core8_pf1vf_virtio_cmn_config_bar_indicator_hwtcl           (core8_pf1vf_virtio_cmn_config_bar_indicator_hwtcl),
   .core8_pf1vf_virtio_cmn_config_bar_offset_hwtcl              (core8_pf1vf_virtio_cmn_config_bar_offset_hwtcl),
   .core8_pf1vf_virtio_cmn_config_structure_length_hwtcl        (core8_pf1vf_virtio_cmn_config_structure_length_hwtcl),
   .core8_pf1vf_virtio_notification_bar_indicator_hwtcl         (core8_pf1vf_virtio_notification_bar_indicator_hwtcl),
   .core8_pf1vf_virtio_notification_bar_offset_hwtcl            (core8_pf1vf_virtio_notification_bar_offset_hwtcl),
   .core8_pf1vf_virtio_notification_structure_length_hwtcl      (core8_pf1vf_virtio_notification_structure_length_hwtcl),
   .core8_pf1vf_virtio_notify_off_multiplier_hwtcl              (core8_pf1vf_virtio_notify_off_multiplier_hwtcl),
   .core8_pf1vf_virtio_isrstatus_bar_indicator_hwtcl            (core8_pf1vf_virtio_isrstatus_bar_indicator_hwtcl),
   .core8_pf1vf_virtio_isrstatus_bar_offset_hwtcl               (core8_pf1vf_virtio_isrstatus_bar_offset_hwtcl),
   .core8_pf1vf_virtio_isrstatus_structure_length_hwtcl         (core8_pf1vf_virtio_isrstatus_structure_length_hwtcl),
   .core8_pf1vf_virtio_devspecific_bar_indicator_hwtcl          (core8_pf1vf_virtio_devspecific_bar_indicator_hwtcl),
   .core8_pf1vf_virtio_devspecific_bar_offset_hwtcl             (core8_pf1vf_virtio_devspecific_bar_offset_hwtcl),
   .core8_pf1vf_virtio_devspecific_structure_length_hwtcl       (core8_pf1vf_virtio_devspecific_structure_length_hwtcl),
   .core8_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl     (core8_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core8_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl        (core8_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl),
   .core8_pf1vf_virtio_pciconfig_access_structure_length_hwtcl  (core8_pf1vf_virtio_pciconfig_access_structure_length_hwtcl),
   .core8_pf2vf_virtio_capability_present_hwtcl                 (core8_pf2vf_virtio_capability_present_hwtcl),
   .core8_pf2vf_virtio_device_specific_cap_present_hwtcl        (core8_pf2vf_virtio_device_specific_cap_present_hwtcl),
   .core8_pf2vf_virtio_cmn_config_bar_indicator_hwtcl           (core8_pf2vf_virtio_cmn_config_bar_indicator_hwtcl),
   .core8_pf2vf_virtio_cmn_config_bar_offset_hwtcl              (core8_pf2vf_virtio_cmn_config_bar_offset_hwtcl),
   .core8_pf2vf_virtio_cmn_config_structure_length_hwtcl        (core8_pf2vf_virtio_cmn_config_structure_length_hwtcl),
   .core8_pf2vf_virtio_notification_bar_indicator_hwtcl         (core8_pf2vf_virtio_notification_bar_indicator_hwtcl),
   .core8_pf2vf_virtio_notification_bar_offset_hwtcl            (core8_pf2vf_virtio_notification_bar_offset_hwtcl),
   .core8_pf2vf_virtio_notification_structure_length_hwtcl      (core8_pf2vf_virtio_notification_structure_length_hwtcl),
   .core8_pf2vf_virtio_notify_off_multiplier_hwtcl              (core8_pf2vf_virtio_notify_off_multiplier_hwtcl),
   .core8_pf2vf_virtio_isrstatus_bar_indicator_hwtcl            (core8_pf2vf_virtio_isrstatus_bar_indicator_hwtcl),
   .core8_pf2vf_virtio_isrstatus_bar_offset_hwtcl               (core8_pf2vf_virtio_isrstatus_bar_offset_hwtcl),
   .core8_pf2vf_virtio_isrstatus_structure_length_hwtcl         (core8_pf2vf_virtio_isrstatus_structure_length_hwtcl),
   .core8_pf2vf_virtio_devspecific_bar_indicator_hwtcl          (core8_pf2vf_virtio_devspecific_bar_indicator_hwtcl),
   .core8_pf2vf_virtio_devspecific_bar_offset_hwtcl             (core8_pf2vf_virtio_devspecific_bar_offset_hwtcl),
   .core8_pf2vf_virtio_devspecific_structure_length_hwtcl       (core8_pf2vf_virtio_devspecific_structure_length_hwtcl),
   .core8_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl     (core8_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core8_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl        (core8_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl),
   .core8_pf2vf_virtio_pciconfig_access_structure_length_hwtcl  (core8_pf2vf_virtio_pciconfig_access_structure_length_hwtcl),
   .core8_pf3vf_virtio_capability_present_hwtcl                 (core8_pf3vf_virtio_capability_present_hwtcl),
   .core8_pf3vf_virtio_device_specific_cap_present_hwtcl        (core8_pf3vf_virtio_device_specific_cap_present_hwtcl),
   .core8_pf3vf_virtio_cmn_config_bar_indicator_hwtcl           (core8_pf3vf_virtio_cmn_config_bar_indicator_hwtcl),
   .core8_pf3vf_virtio_cmn_config_bar_offset_hwtcl              (core8_pf3vf_virtio_cmn_config_bar_offset_hwtcl),
   .core8_pf3vf_virtio_cmn_config_structure_length_hwtcl        (core8_pf3vf_virtio_cmn_config_structure_length_hwtcl),
   .core8_pf3vf_virtio_notification_bar_indicator_hwtcl         (core8_pf3vf_virtio_notification_bar_indicator_hwtcl),
   .core8_pf3vf_virtio_notification_bar_offset_hwtcl            (core8_pf3vf_virtio_notification_bar_offset_hwtcl),
   .core8_pf3vf_virtio_notification_structure_length_hwtcl      (core8_pf3vf_virtio_notification_structure_length_hwtcl),
   .core8_pf3vf_virtio_notify_off_multiplier_hwtcl              (core8_pf3vf_virtio_notify_off_multiplier_hwtcl),
   .core8_pf3vf_virtio_isrstatus_bar_indicator_hwtcl            (core8_pf3vf_virtio_isrstatus_bar_indicator_hwtcl),
   .core8_pf3vf_virtio_isrstatus_bar_offset_hwtcl               (core8_pf3vf_virtio_isrstatus_bar_offset_hwtcl),
   .core8_pf3vf_virtio_isrstatus_structure_length_hwtcl         (core8_pf3vf_virtio_isrstatus_structure_length_hwtcl),
   .core8_pf3vf_virtio_devspecific_bar_indicator_hwtcl          (core8_pf3vf_virtio_devspecific_bar_indicator_hwtcl),
   .core8_pf3vf_virtio_devspecific_bar_offset_hwtcl             (core8_pf3vf_virtio_devspecific_bar_offset_hwtcl),
   .core8_pf3vf_virtio_devspecific_structure_length_hwtcl       (core8_pf3vf_virtio_devspecific_structure_length_hwtcl),
   .core8_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl     (core8_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl),
   .core8_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl        (core8_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl),
   .core8_pf3vf_virtio_pciconfig_access_structure_length_hwtcl  (core8_pf3vf_virtio_pciconfig_access_structure_length_hwtcl),
   .core8_pf0_vf_count_hwtcl                                    (core8_pf0_vf_count_hwtcl),
   .core8_pf1_vf_count_hwtcl                                    (core8_pf1_vf_count_hwtcl),
   .core8_pf2_vf_count_hwtcl                                    (core8_pf2_vf_count_hwtcl),
   .core8_pf3_vf_count_hwtcl                                    (core8_pf3_vf_count_hwtcl),

   .core16_func_mode_hwtcl                 (core16_func_mode_hwtcl),
   .core8_func_mode_hwtcl                  (core8_func_mode_hwtcl),
   .core8_topology                         (core8_topology),

   .core16_num_of_chnl_w                   (core16_num_of_chnl_w),
   .core8_num_of_chnl_w                    (core8_num_of_chnl_w),
   
   .sm_hssi_pcie_ctl_x4_cvp_enable_hwtcl   (sm_hssi_pcie_ctl_x4_cvp_enable_hwtcl),
   .sm_hssi_pcie_ctl_x8_cvp_enable_hwtcl   (sm_hssi_pcie_ctl_x8_cvp_enable_hwtcl)

) pcie_sip_top_inst (
   .ninit_done                              (ninit_done),
   .coreclkout_hip                          (p0_coreclkout_hip_w),
   .p0_axi_lite_clk                         (p0_axi_lite_clk),
   .p0_axi_st_clk                           (p0_axi_st_clk),
   .p1_axi_lite_clk                         (p1_axi_lite_clk),
   .p1_axi_st_clk                           (p1_axi_st_clk),


   .p0_pin_perst_n_o                          (p0_pin_perst_n),
   .p0_reset_status_n                       (p0_reset_status_n),
   .p1_pin_perst_n_o                          (p1_pin_perst_n),
   .p1_reset_status_n                       (p1_reset_status_n),


   .p0_rst_req_o                            (p0_rst_req_o),
   .p0_rst_rdy_i                            (p0_rst_rdy_i),
   .p0_axi_st_areset_n                      (p0_axi_st_areset_n_axi_clk_sync),
   .p0_axi_lite_areset_n                    (p0_axi_lite_areset_n_axi_clk_sync),
   .p1_axi_st_areset_n                      ('0),
   .p1_axi_lite_areset_n                    ('0),
   .p1_rst_req_o                            (p1_rst_req_o),
   .p1_rst_rdy_i                            (p1_rst_rdy_i),
   
   .p0_pin_perst_n_i                           (p0_hip_pin_perst_n),
   .p1_pin_perst_n_i                           (p1_hip_pin_perst_n),

   .p0_core_pll_lock_i                         (p0_core_pll_lock),
   .p1_core_pll_lock_i                         (p1_core_pll_lock),

  .  p0_tx_dsk_done_i(p0_tx_dsk_done   ),
  .  p0_pld_core_rst_n_i(p0_pld_core_rst_n   ),
  .   p0_user_mode_to_pld_i(p0_user_mode_to_pld   ),
  .   p0_pld_in_use_i( p0_pld_in_use  ),
  . p0_pld_link_req_rst_i ( p0_pld_link_req_rst ), 
  . p0_pld_in_use_o(p0_pld_in_use_o),
  . p0_user_mode_to_pld_o(p0_user_mode_to_pld_o),
  . p0_pld_warm_rst_rdy_o(p0_pld_warm_rst_rdy   ),
  . p0_pld_ready_o(p0_pld_ready ),

  .p0_pm_state_i      (p0_pm_state[2:0]),
  .p0_pm_pf0_dstate_i (p0_pm_pf0_dstate[3:0]),
  .p0_pm_pf1_dstate_i (p0_pm_pf1_dstate[3:0]),
  .p0_pm_pf2_dstate_i (p0_pm_pf2_dstate[3:0]),
  .p0_pm_pf3_dstate_i (p0_pm_pf3_dstate[3:0]),

  .p1_pm_state_i      (p1_pm_state[2:0]),
  .p1_pm_pf0_dstate_i (p1_pm_pf0_dstate[3:0]),
  .p1_pm_pf1_dstate_i (p1_pm_pf1_dstate[3:0]),
  .p1_pm_pf2_dstate_i (p1_pm_pf2_dstate[3:0]),
  .p1_pm_pf3_dstate_i (p1_pm_pf3_dstate[3:0]),

  .  p1_tx_dsk_done_i(p1_tx_dsk_done   ),
  .  p1_pld_core_rst_n_i(p1_pld_core_rst_n   ),
  .   p1_user_mode_to_pld_i(p1_user_mode_to_pld   ),
  .   p1_pld_in_use_i( p1_pld_in_use  ),
  . p1_pld_link_req_rst_i ( p1_pld_link_req_rst ), 
  . p1_pld_in_use_o(p1_pld_in_use_o),
  . p1_user_mode_to_pld_o(p1_user_mode_to_pld_o),
  . p1_pld_warm_rst_rdy_o(p1_pld_warm_rst_rdy   ),
  . p1_pld_ready_o(p1_pld_ready ),



   .p0_pld_adapter_tx_pld_rst_n      ( p0_pld_adapter_tx_pld_rst_n  ),
   .p0_pld_adapter_rx_pld_rst_n      ( p0_pld_adapter_rx_pld_rst_n  ),

   .p1_pld_adapter_tx_pld_rst_n      ( p1_pld_adapter_tx_pld_rst_n_nc  ),
   .p1_pld_adapter_rx_pld_rst_n      ( p1_pld_adapter_rx_pld_rst_n_nc  ),



   .ch0_rx_data_i                           (ch0_rx_data),//wire connection to haltop
   .ch1_rx_data_i                           (ch1_rx_data), 
   .ch2_rx_data_i                           (ch2_rx_data), 
   .ch3_rx_data_i                           (ch3_rx_data), 
   .ch4_rx_data_i                           (ch4_rx_data), 
   .ch5_rx_data_i                           (ch5_rx_data),
   .ch6_rx_data_i		            (ch6_rx_data), 
   .ch7_rx_data_i               	    (ch7_rx_data), 
   .ch8_rx_data_i       	            (ch8_rx_data), 
   .ch9_rx_data_i	                    (ch9_rx_data), 
   .ch10_rx_data_i	                    (ch10_rx_data), 

   .ch0_tx_data_o                           (ch0_tx_data), 
   .ch1_tx_data_o                           (ch1_tx_data), 
   .ch2_tx_data_o                           (ch2_tx_data), 
   .ch3_tx_data_o                           (ch3_tx_data),
   .ch4_tx_data_o			    (ch4_tx_data),//shunxiong-fix lint_23ww2501 
   .ch5_tx_data_o                     	    (ch5_tx_data), 
   .ch6_tx_data_o                           (ch6_tx_data), 
   .ch7_tx_data_o                           (ch7_tx_data), 
   .ch8_tx_data_o                           (ch8_tx_data),
   .ch9_tx_data_o			    (ch9_tx_data), 
   .ch10_tx_data_o			    (ch10_tx_data), 


   .p0_rx_tuser_halt                        (p0_rx_tuser_halt),   
   .p1_rx_tuser_halt                        (p1_rx_tuser_halt),   

   //AXI-S Interface
   .p0_st_rx_tready_i                         (p0_st_rx_tready_i), //bring up to top
   .p0_st_rx_tvalid_o                         (p0_st_rx_tvalid_o),
   .p0_st_rx_tlast_o                          (p0_st_rx_tlast_o),
   .p0_st_rx_tdata_o                          (p0_st_rx_tdata_o),
   .p0_st_rx_tkeep_o                          (p0_st_rx_tkeep_o),
   .p0_st_rx_tuser_last_segment               (p0_st_rx_tuser_last_segment),

   .p1_st_rx_tready_i                         (p1_st_rx_tready_i), //bring up to top
   .p1_st_rx_tvalid_o                         (p1_st_rx_tvalid_o),
   .p1_st_rx_tlast_o                          (p1_st_rx_tlast_o),
   .p1_st_rx_tdata_o                          (p1_st_rx_tdata_o),
   .p1_st_rx_tkeep_o                          (p1_st_rx_tkeep_o),
   .p1_st_rx_tuser_last_segment               (p1_st_rx_tuser_last_segment),


   .p0_pcie_pld_rx_fbk_tready                     (p0_pcie_pld_rx_fbk_tready),
   .p1_pcie_pld_rx_fbk_tready                     (p1_pcie_pld_rx_fbk_tready),


   .p0_st_tx_tvalid_i                          (p0_st_tx_tvalid_i),
   .p0_st_tx_tlast_i                           (p0_st_tx_tlast_i),
   .p0_st_tx_tdata_i                           (p0_st_tx_tdata_i),
   .p0_st_tx_tkeep_i                           (p0_st_tx_tkeep_i),
   .p0_st_tx_tuser_last_segment                (p0_st_tx_tuser_last_segment),  
   .p0_st_tx_tready_o                          (p0_st_tx_tready_o),

   .p1_st_tx_tvalid_i                          (p1_st_tx_tvalid_i),
   .p1_st_tx_tlast_i                           (p1_st_tx_tlast_i),
   .p1_st_tx_tdata_i                           (p1_st_tx_tdata_i),
   .p1_st_tx_tkeep_i                           (p1_st_tx_tkeep_i),
   .p1_st_tx_tuser_last_segment                (p1_st_tx_tuser_last_segment),  
   .p1_st_tx_tready_o                          (p1_st_tx_tready_o),

   
   .p0_st_txcrdt_tvalid_o                   (p0_st_txcrdt_tvalid_o),
   .p0_st_txcrdt_tvdata_o                   (p0_st_txcrdt_tvdata_o),
   .p0_st_txcrdt_tldrdy_i		    (p0_st_txcrdt_tldrdy_i),

   .p1_st_txcrdt_tvalid_o                   (p1_st_txcrdt_tvalid_o),
   .p1_st_txcrdt_tvdata_o                   (p1_st_txcrdt_tvdata_o),
   .p1_st_txcrdt_tldrdy_i		    (p1_st_txcrdt_tldrdy_i),


   .p0_app_int_i                            (p0_app_int_i),
   .p0_app_int_ready_o                      (p0_app_int_ready_o),
   .p0_int_status_o                         (p0_int_status_o),
   .p1_app_int_i                            (p1_app_int_i),
   .p1_app_int_ready_o                      (p1_app_int_ready_o),
   .p1_int_status_o                         (p1_int_status_o),


   .p0_msi_pnd_func_i                       (p0_msi_pnd_func_i),
   .p0_msi_pnd_addr_i                       (p0_msi_pnd_addr_i),
   .p0_msi_pnd_byte_i                       (p0_msi_pnd_byte_i),
   .p0_msi_pnd_vf_num_i                     (p0_msi_pnd_vf_num_i),
   .p0_msi_pnd_vfa_i                        (p0_msi_pnd_vfa_i),
   .p0_msi_pnd_ready_o                      (p0_msi_pnd_ready_o),  
   .p0_sys_hotplug_ready_o                  (p0_sys_hotplug_ready_o),
   .p0_apps_pm_ready_o                      (p0_apps_pm_ready_o),
   .p0_qhip_prs_event_ready_o               (p0_qhip_prs_event_ready_o),

   .p1_msi_pnd_func_i                       (p1_msi_pnd_func_i),
   .p1_msi_pnd_addr_i                       (p1_msi_pnd_addr_i),
   .p1_msi_pnd_byte_i                       (p1_msi_pnd_byte_i),
   .p1_msi_pnd_vf_num_i                     (p1_msi_pnd_vf_num_i),
   .p1_msi_pnd_vfa_i                        (p1_msi_pnd_vfa_i),
   .p1_msi_pnd_ready_o                      (p1_msi_pnd_ready_o),  
   .p1_sys_hotplug_ready_o                  (p1_sys_hotplug_ready_o),
   .p1_apps_pm_ready_o                      (p1_apps_pm_ready_o),
   .p1_qhip_prs_event_ready_o               (p1_qhip_prs_event_ready_o),


   .p0_app_xfer_pending_i                   (p0_app_xfer_pending_i),
   .p0_app_ready_entr_l23_i                 (p0_apps_ready_entr_l23_i),
   .p0_apps_pm_xmt_pme_i                    (p0_apps_pm_xmt_pme_i),
   .p0_app_init_rst_i                       (p0_app_init_rst_i),
   .p0_apps_pm_xmt_turnoff_i                (p0_apps_pm_xmt_turnoff_i),
   .p0_surprise_down_err_o                  (p0_surprise_down_err_o),
   .p0_link_up_o                            (p0_link_up_o),
   .p0_dl_up_o                              (p0_dl_up_o),
   .p0_pm_state_o                           (p0_pm_state_o),
   .p0_pm_dstate_o                          (p0_pm_dstate_o),
   .p0_ltssm_state_o                        (p0_ltssm_state_o),
   .p0_pld_gp_status_i                      (p0_pld_gp_status_i),
   .p0_pld_gp_ctrl_o                        (p0_pld_gp_ctrl_o),
   .p0_app_retry_en_i                       (8'b0), // taken out  22018718117
   .p0_app_retry_en_ready_o                 (p0_app_retry_en_ready_o),
   .p0_sys_aux_pwr_det_i                    (p0_sys_aux_pwr_det_i),

   .p1_app_xfer_pending_i                   (p1_app_xfer_pending_i),
   .p1_app_ready_entr_l23_i                 (p1_apps_ready_entr_l23_i),
   .p1_apps_pm_xmt_pme_i                    (p1_apps_pm_xmt_pme_i),
   .p1_app_init_rst_i                       (p1_app_init_rst_i),
   .p1_apps_pm_xmt_turnoff_i                (p1_apps_pm_xmt_turnoff_i),
   .p1_surprise_down_err_o                  (p1_surprise_down_err_o),
   .p1_link_up_o                            (p1_link_up_o),
   .p1_dl_up_o                              (p1_dl_up_o),
   .p1_pm_state_o                           (p1_pm_state_o),
   .p1_pm_dstate_o                          (p1_pm_dstate_o),
   .p1_ltssm_state_o                        (p1_ltssm_state_o),
   .p1_pld_gp_status_i                      (p1_pld_gp_status_i),
   .p1_pld_gp_ctrl_o                        (p1_pld_gp_ctrl_o),
   .p1_app_retry_en_i                       (8'b0), // taken out  22018718117
   .p1_app_retry_en_ready_o                 (p1_app_retry_en_ready_o),
   .p1_sys_aux_pwr_det_i                    (p1_sys_aux_pwr_det_i),


   .p0_app_err_valid_i                      (p0_app_err_valid_i),
   .p0_app_err_func_num_i                   (p0_app_err_func_num_i),
   .p0_app_err_hdr_i                        (p0_app_err_hdr_i),
   .p0_app_err_info_i                       (p0_app_err_info_i),
   .p0_app_err_ready_o                      (p0_app_err_ready_o),
   .p0_serr_out_o                           (p0_serr_out_o),
   .p0_hip_enter_err_mode_o                 (p0_hip_enter_err_mode_o),

   .p1_app_err_valid_i                      (p1_app_err_valid_i),
   .p1_app_err_func_num_i                   (p1_app_err_func_num_i),
   .p1_app_err_hdr_i                        (p1_app_err_hdr_i),
   .p1_app_err_info_i                       (p1_app_err_info_i),
   .p1_app_err_ready_o                      (p1_app_err_ready_o),
   .p1_serr_out_o                           (p1_serr_out_o),
   .p1_hip_enter_err_mode_o                 (p1_hip_enter_err_mode_o),


   .p0_sys_pwr_fault_det_i                  (p0_sys_pwr_fault_det_i),
   .p0_sys_mrl_sensor_state_i               (p0_sys_mrl_sensor_state_i),
   .p0_sys_mrl_sensor_chged_i               (p0_sys_mrl_sensor_chged_i),
   .p0_sys_pre_det_state_i                  (p0_sys_pre_det_state_i),
   .p0_sys_pre_det_chged_i                  (p0_sys_pre_det_chged_i),
   .p0_sys_cmd_cpled_int_i                  (p0_sys_cmd_cpled_int_i),
   .p0_sys_atten_button_pressed_i           (p0_sys_atten_button_pressed_i),
   .p0_sys_eml_interlock_engaged_i          (p0_sys_eml_interlock_engaged_i),

   .p1_sys_pwr_fault_det_i                  (p1_sys_pwr_fault_det_i),
   .p1_sys_mrl_sensor_state_i               (p1_sys_mrl_sensor_state_i),
   .p1_sys_mrl_sensor_chged_i               (p1_sys_mrl_sensor_chged_i),
   .p1_sys_pre_det_state_i                  (p1_sys_pre_det_state_i),
   .p1_sys_pre_det_chged_i                  (p1_sys_pre_det_chged_i),
   .p1_sys_cmd_cpled_int_i                  (p1_sys_cmd_cpled_int_i),
   .p1_sys_atten_button_pressed_i           (p1_sys_atten_button_pressed_i),
   .p1_sys_eml_interlock_engaged_i          (p1_sys_eml_interlock_engaged_i),


   .p0_flr_rcvd_pf_o                        (p0_flr_rcvd_pf_o),
   .p0_flr_rcvd_vf_o                        (p0_flr_rcvd_vf_o),
   .p0_flr_rcvd_pf_num_o                    (p0_flr_rcvd_pf_num_o),
   .p0_flr_rcvd_vf_num_o                    (p0_flr_rcvd_vf_num_o),
   .p0_flr_cmpl_pf_i                        (p0_flr_cmpl_pf_i),
   .p0_flr_cmpl_vf_i                        (p0_flr_cmpl_vf_i),
   .p0_flr_cmpl_pf_num_i                    (p0_flr_cmpl_pf_num_i),
   .p0_flr_cmpl_vf_num_i                    (p0_flr_cmpl_vf_num_i),
   .p0_flr_cmpl_tready_o                    (p0_flr_cmpl_tready_o),

   .p1_flr_rcvd_pf_o                        (p1_flr_rcvd_pf_o),
   .p1_flr_rcvd_vf_o                        (p1_flr_rcvd_vf_o),
   .p1_flr_rcvd_pf_num_o                    (p1_flr_rcvd_pf_num_o),
   .p1_flr_rcvd_vf_num_o                    (p1_flr_rcvd_vf_num_o),
   .p1_flr_cmpl_pf_i                        (p1_flr_cmpl_pf_i),
   .p1_flr_cmpl_vf_i                        (p1_flr_cmpl_vf_i),
   .p1_flr_cmpl_pf_num_i                    (p1_flr_cmpl_pf_num_i),
   .p1_flr_cmpl_vf_num_i                    (p1_flr_cmpl_vf_num_i),
   .p1_flr_cmpl_tready_o                    (p1_flr_cmpl_tready_o),


   .p0_virtio_pcicfgreq_tvalid_o            (p0_virtio_pcicfgreq_tvalid_o),
   .p0_virtio_pcicfgreq_tdata_o             (p0_virtio_pcicfgreq_tdata_o),
   .p0_virtio_pcicfgcmpl_tvalid_i           (p0_virtio_pcicfgcmpl_tvalid_i),
   .p0_virtio_pcicfgcmpl_tdata_i            (p0_virtio_pcicfgcmpl_tdata_i),

   .p1_virtio_pcicfgreq_tvalid_o            (p1_virtio_pcicfgreq_tvalid_o),
   .p1_virtio_pcicfgreq_tdata_o             (p1_virtio_pcicfgreq_tdata_o),
   .p1_virtio_pcicfgcmpl_tvalid_i           (p1_virtio_pcicfgcmpl_tvalid_i),
   .p1_virtio_pcicfgcmpl_tdata_i            (p1_virtio_pcicfgcmpl_tdata_i),


   .p0_tl_cfg_add_o                         (p0_tl_cfg_add_o),
   .p0_tl_cfg_func_o                        (p0_tl_cfg_func_o),
   .p0_tl_cfg_ctl_o                         (p0_tl_cfg_ctl_o),
   .p0_dl_timer_update_o                    (p0_dl_timer_update_o),

   .p1_tl_cfg_add_o                         (p1_tl_cfg_add_o),
   .p1_tl_cfg_func_o                        (p1_tl_cfg_func_o),
   .p1_tl_cfg_ctl_o                         (p1_tl_cfg_ctl_o),
   .p1_dl_timer_update_o                    (p1_dl_timer_update_o),

   // VirtIO PCI Config Access Interface
   .p0_virtio_pcicfg_vfaccess_o,        
   .p0_virtio_pcicfg_vfnum_o,
   .p0_virtio_pcicfg_pfnum_o,
   .p0_virtio_pcicfg_bar_o,
   .p0_virtio_pcicfg_length_o,
   .p0_virtio_pcicfg_baroffset_o,
   .p0_virtio_pcicfg_cfgdata_o,
   .p0_virtio_pcicfg_cfgwr_o,        
   .p0_virtio_pcicfg_cfgrd_o, 

   .p0_virtio_pcicfg_appvfnum_i,  // Application indicates for which VF offset.
   .p0_virtio_pcicfg_apppfnum_i,  // Application indicates for which PF.
   .p0_virtio_pcicfg_rdack_i,     // Application Read Data Ack to store config data.
   .p0_virtio_pcicfg_rdbe_i,      // Application indicates which byte to store.
   .p0_virtio_pcicfg_data_i,       // Data to be stored in config data registers.

   .p1_virtio_pcicfg_vfaccess_o,        
   .p1_virtio_pcicfg_vfnum_o,
   .p1_virtio_pcicfg_pfnum_o,
   .p1_virtio_pcicfg_bar_o,
   .p1_virtio_pcicfg_length_o,
   .p1_virtio_pcicfg_baroffset_o,
   .p1_virtio_pcicfg_cfgdata_o,
   .p1_virtio_pcicfg_cfgwr_o,        
   .p1_virtio_pcicfg_cfgrd_o, 

   .p1_virtio_pcicfg_appvfnum_i,  // Application indicates for which VF offset.
   .p1_virtio_pcicfg_apppfnum_i,  // Application indicates for which PF.
   .p1_virtio_pcicfg_rdack_i,     // Application Read Data Ack to store config data.
   .p1_virtio_pcicfg_rdbe_i,      // Application indicates which byte to store.
   .p1_virtio_pcicfg_data_i,       // Data to be stored in config data registers.

   //Configuration Intercept Interface Signals

//nwai   .p0_st_ciireq_tvalid_o                   (p0_st_ciireq_tvalid_o),
//nwai   .p0_st_cciireq_tready_i                  (p0_st_cciireq_tready_i),
   .p0_st_ciireq_tdata_o                    (p0_st_ciireq_tdata_o),

   .p0_st_cii_halt_i                        (p0_st_cii_halt_i),
   .p0_st_cii_req_o                         (p0_st_cii_req_o),

//nwai   .p1_st_ciireq_tvalid_o                   (p1_st_ciireq_tvalid_o),
//nwai   .p1_st_cciireq_tready_i                  (p1_st_cciireq_tready_i),
   .p1_st_ciireq_tdata_o                    (p1_st_ciireq_tdata_o),

   .p1_st_cii_halt_i                        (p1_st_cii_halt_i),
   .p1_st_cii_req_o                         (p1_st_cii_req_o),

 
   //Configuration Intercept Response Interface
//nwai   .p0_st_ciiresp_tvalid_i                  (p0_st_ciiresp_tvalid_i),
   .p0_st_ciiresp_tdata_i                   (p0_st_ciiresp_tdata_i),
//nwai   .p1_st_ciiresp_tvalid_i                  (p1_st_ciiresp_tvalid_i),
   .p1_st_ciiresp_tdata_i                   (p1_st_ciiresp_tdata_i),


   .p0_user_sent_vfnonfatalmsg_i            (p0_user_sent_vfnonfatalmsg_i),
   .p0_user_vfnonfatalmsg_func_num_i        (p0_user_vfnonfatalmsg_func_num_i),
   .p0_user_vfnonfatalmsg_vfnum_i           (p0_user_vfnonfatalmsg_vfnum_i),
   .p0_user_vfnonfatalmsg_ready_o           (p0_user_vfnonfatalmsg_ready_o), 
   .p0_vf_err_ur_posted_s0_o                (p0_vf_err_ur_posted_s0_o),
   .p0_vf_err_ca_postedreq_s0_o             (p0_vf_err_ca_postedreq_s0_o),
   .p0_vf_err_poisonedwrreq_s0_o            (p0_vf_err_poisonedwrreq_s0_o),
   .p0_vf_err_poisonedcompl_s0_o            (p0_vf_err_poisonedcompl_s0_o),
   .p0_vf_err_func_num_s0_o                 (p0_vf_err_func_num_s0_o),
   .p0_vf_err_vf_num_s0_o                   (p0_vf_err_vf_num_s0_o),
   .p0_vf_err_ur_posted_s1_o                (p0_vf_err_ur_posted_s1_o),
   .p0_vf_err_ca_postedreq_s1_o             (p0_vf_err_ca_postedreq_s1_o),
   .p0_vf_err_poisonedwrreq_s1_o            (p0_vf_err_poisonedwrreq_s1_o),
   .p0_vf_err_poisonedcompl_s1_o            (p0_vf_err_poisonedcompl_s1_o),
   .p0_vf_err_func_num_s1_o                 (p0_vf_err_func_num_s1_o),
   .p0_vf_err_vf_num_s1_o                   (p0_vf_err_vf_num_s1_o),
   .p0_vf_err_overflow_o                    (p0_vf_err_overflow_o),

   .p1_user_sent_vfnonfatalmsg_i            (p1_user_sent_vfnonfatalmsg_i),
   .p1_user_vfnonfatalmsg_func_num_i        (p1_user_vfnonfatalmsg_func_num_i),
   .p1_user_vfnonfatalmsg_vfnum_i           (p1_user_vfnonfatalmsg_vfnum_i),
   .p1_user_vfnonfatalmsg_ready_o           (p1_user_vfnonfatalmsg_ready_o), 
   .p1_vf_err_ur_posted_s0_o                (p1_vf_err_ur_posted_s0_o),
   .p1_vf_err_ca_postedreq_s0_o             (p1_vf_err_ca_postedreq_s0_o),
   .p1_vf_err_poisonedwrreq_s0_o            (p1_vf_err_poisonedwrreq_s0_o),
   .p1_vf_err_poisonedcompl_s0_o            (p1_vf_err_poisonedcompl_s0_o),
   .p1_vf_err_func_num_s0_o                 (p1_vf_err_func_num_s0_o),
   .p1_vf_err_vf_num_s0_o                   (p1_vf_err_vf_num_s0_o),
   .p1_vf_err_ur_posted_s1_o                (p1_vf_err_ur_posted_s1_o),
   .p1_vf_err_ca_postedreq_s1_o             (p1_vf_err_ca_postedreq_s1_o),
   .p1_vf_err_poisonedwrreq_s1_o            (p1_vf_err_poisonedwrreq_s1_o),
   .p1_vf_err_poisonedcompl_s1_o            (p1_vf_err_poisonedcompl_s1_o),
   .p1_vf_err_func_num_s1_o                 (p1_vf_err_func_num_s1_o),
   .p1_vf_err_vf_num_s1_o                   (p1_vf_err_vf_num_s1_o),
   .p1_vf_err_overflow_o                    (p1_vf_err_overflow_o),


   .p0_st_cplto_tvalid_o                    (p0_st_cplto_tvalid_o),
   .p0_st_cplto_tdata_o                     (p0_st_cplto_tdata_o),
   .p0_st_cplto_ready_i                     (p0_st_cplto_ready_i),
   .p1_st_cplto_tvalid_o                    (p1_st_cplto_tvalid_o),
   .p1_st_cplto_tdata_o                     (p1_st_cplto_tdata_o),
   .p1_st_cplto_ready_i                     (p1_st_cplto_ready_i),

   
   .p0_qhip_prs_event_i                     (p0_qhip_prs_event_i),
   .p0_qhip_prs_event_func_i                (p0_qhip_prs_event_func_i),
   .p0_qhip_prs_event_valid_i               (p0_qhip_prs_event_valid_i),
   .p1_qhip_prs_event_i                     (p1_qhip_prs_event_i),
   .p1_qhip_prs_event_func_i                (p1_qhip_prs_event_func_i),
   .p1_qhip_prs_event_valid_i               (p1_qhip_prs_event_valid_i),


   .p0_test_in_i                            (p0_test_in_i),
   .p0_test_out_o                           (p0_test_out_o),
   .p1_test_in_i                            (p1_test_in_i),
   .p1_test_out_o                           (p1_test_out_o),

   .p0_ptm_manual_update_i                  (p0_ptm_manual_update),
   .p0_ptm_context_valid_o                  (p0_ptm_context_valid),
   .p0_start_ptm_newclk_value_o             (p0_start_ptm_newclk_value),
   .p0_ptm_newclk_value_o                   (p0_ptm_newclk_value),
   .p0_ptm_clock_correction_o               (p0_ptm_clock_correction),
   .p1_ptm_manual_update_i                  (p1_ptm_manual_update),
   .p1_ptm_context_valid_o                  (p1_ptm_context_valid),
   .p1_start_ptm_newclk_value_o             (p1_start_ptm_newclk_value),
   .p1_ptm_newclk_value_o                   (p1_ptm_newclk_value),
   .p1_ptm_clock_correction_o               (p1_ptm_clock_correction),

   .p0_hip_reconfig_clk                     (p0_hip_reconfig_clk),
   .p0_hip_reconfig_address                 (p0_hip_reconfig_address_w),
   .p0_hip_reconfig_write                   (p0_hip_reconfig_write_w),
   .p0_hip_reconfig_writedata               (p0_hip_reconfig_writedata_w),
   .p0_hip_reconfig_read                    (p0_hip_reconfig_read_w),
   .p0_hip_reconfig_readdatavalid           (p0_hip_reconfig_readdatavalid_w),
   .p0_hip_reconfig_readdata                (p0_hip_reconfig_readdata_w),
   .p0_hip_reconfig_waitrequest             (p0_hip_reconfig_waitrequest_w),
   .p0_hip_reconfig_byteen                  (p0_hip_reconfig_byteen_w),
   .p0_hip_reconfig_resp                    (p0_hip_reconfig_resp),

   .p1_hip_reconfig_clk                     (p1_hip_reconfig_clk),
   .p1_hip_reconfig_address                 (p1_hip_reconfig_address_w),
   .p1_hip_reconfig_write                   (p1_hip_reconfig_write_w),
   .p1_hip_reconfig_writedata               (p1_hip_reconfig_writedata_w),
   .p1_hip_reconfig_read                    (p1_hip_reconfig_read_w),
   .p1_hip_reconfig_readdatavalid           (p1_hip_reconfig_readdatavalid_w),
   .p1_hip_reconfig_readdata                (p1_hip_reconfig_readdata_w),
   .p1_hip_reconfig_waitrequest             (p1_hip_reconfig_waitrequest_w),
   .p1_hip_reconfig_byteen                  (p1_hip_reconfig_byteen_w),
   .p1_hip_reconfig_resp                    (p1_hip_reconfig_resp),
   
   .p0_tlpbyp_tdata_o                       (p0_tlpbyp_tdata_o),  
   .p0_tlpbyp_tvalid_o                      (p0_tlpbyp_tvalid_o), 
   
   .p0_tlpbyp_ready_i                       (p0_tlpbyp_ready_i), 
   .p1_tlpbyp_tdata_o                       (p1_tlpbyp_tdata_o),  
   .p1_tlpbyp_tvalid_o                      (p1_tlpbyp_tvalid_o), 
   .p1_tlpbyp_ready_i                       (p1_tlpbyp_ready_i) 

);

generate
    if (debug_toolkit_hwtcl) begin : gen_dtk
		sm_pcie_debug_toolkit # (
			.core16_func_mode_hwtcl                 (core16_func_mode_hwtcl),
			.core8_func_mode_hwtcl                  ("Disable"),
			.hard_dtk_en_hwtcl                 	(0), //0 for A0 turn on soft logger; 1 for B0 turn off soft logger
			.sm_enable_pciess_register_access_hwtcl	(enable_pciess_register_access_hwtcl),  
			.sm_link_insp_en_hwtcl			(link_insp_en_hwtcl),
			.core16_perfmon_clk_freq		(core16_perfmon_clk_freq),
			.core8_perfmon_clk_freq			(0),
			.set_slave_map				("{typeName agilex5_debug_toolkit_p0_adme address 0x0 span 67108864 hpath {p0_adme}}")
		) p0_sm_pcie_debug_toolkit_inst (
			.p0_ltssm			(p0_ltssm_state_o), 
			.p1_ltssm			('0), 
			.p0_core_pll_lock		(p0_core_pll_lock),  
			.p1_core_pll_lock		('0),  
			.hip_coreclk			(p0_coreclkout_hip_w), 
			.avmm_clk			(p0_axi_lite_clk), 
			.ninit_done			(ninit_done), 
			.toolkit_mode			(p0_toolkit_mode),
			.phy_avmm_read_o		(p0_pacer_phy_avmm_read),
			.phy_avmm_write_o		(p0_pacer_phy_avmm_write),
			.phy_avmm_address_o		(p0_pacer_phy_avmm_address),
			.phy_avmm_writedata_o		(p0_pacer_phy_avmm_writedata),
			.phy_avmm_readdatavalid_i	(p0_pacer_phy_avmm_readdatavalid),
			.phy_avmm_readdata_i		(p0_pacer_phy_avmm_readdata),
			.phy_avmm_waitrequest_i		(p0_pacer_phy_avmm_waitrequest),
			.p0_avmm_read_o			(dtk_p0_avmm_read),
			.p0_avmm_write_o		(dtk_p0_avmm_write),
			.p0_avmm_address_o		(dtk_p0_avmm_address),
			.p0_avmm_writedata_o		(dtk_p0_avmm_writedata),
			.p0_avmm_readdatavalid_i	(dtk_p0_avmm_readdatavalid),
			.p0_avmm_readdata_i		(dtk_p0_avmm_readdata),
			.p0_avmm_waitrequest_i		(dtk_p0_avmm_waitrequest),
			.p1_avmm_read_o			(),
			.p1_avmm_write_o		(),
			.p1_avmm_address_o		(),
			.p1_avmm_writedata_o		(),
			.p1_avmm_readdatavalid_i	('0),
			.p1_avmm_readdata_i		('0),
			.p1_avmm_waitrequest_i		('0),
			.ss_avmm_read_o			(p0_dtk_ss_avmm_read), 
			.ss_avmm_write_o		(p0_dtk_ss_avmm_write),
			.ss_avmm_address_o		(p0_dtk_ss_avmm_address),
			.ss_avmm_writedata_o		(p0_dtk_ss_avmm_writedata),
			.ss_avmm_readdatavalid_i	(p0_dtk_ss_avmm_readdatavalid),
			.ss_avmm_readdata_i		(p0_dtk_ss_avmm_readdata),
			.ss_avmm_waitrequest_i		(p0_dtk_ss_avmm_waitrequest)
	);

	// Convert PHY AVMM interface fast clock(AXI Lite) to slow (max 125MHz lavmm)
	avmm_pacer p0_avmm_pacer_inst(
		.clk_i			(p0_axi_lite_clk),
		.rstn_i			(~ninit_done),
		.avmm_addr_i		(p0_pacer_phy_avmm_address),
		.avmm_read_i		(p0_pacer_phy_avmm_read),
		.avmm_rdata_o		(p0_pacer_phy_avmm_readdata),
		.avmm_rdata_valid_o	(p0_pacer_phy_avmm_readdatavalid),
		.avmm_write_i		(p0_pacer_phy_avmm_write),
		.avmm_wdata_i		(p0_pacer_phy_avmm_writedata),
		.avmm_waitreq_o		(p0_pacer_phy_avmm_waitrequest),
		
		.slw_clk_o		(p0_phy_avmm_clk),
		.slw_avmm_addr_o	(p0_phy_avmm_address),
		.slw_avmm_read_o	(p0_phy_avmm_read),
		.slw_avmm_rdata_i	(p0_phy_avmm_readdata),
		.slw_avmm_rdata_valid_i (p0_phy_avmm_readdatavalid),
		.slw_avmm_write_o	(p0_phy_avmm_write),
		.slw_avmm_wdata_o	(p0_phy_avmm_writedata),
		.slw_avmm_waitreq_i	(p0_phy_avmm_waitrequest)
	);

	// PHY Local AVMM Arbiter
	pcie_phy_user_avmm_arb p0_pcie_phy_user_avmm_arb_inst(
		.phy_avmm_read		(p0_phy_avmm_read),
		.phy_avmm_write		(p0_phy_avmm_write),
		.phy_avmm_address	(p0_phy_avmm_address),
		.phy_avmm_writedata	(p0_phy_avmm_writedata),
		.phy_avmm_readdatavalid	(p0_phy_avmm_readdatavalid),
		.phy_avmm_readdata	(p0_phy_avmm_readdata),
		.phy_avmm_waitrequest	(p0_phy_avmm_waitrequest),
		.phy0_avmm_read,
		.phy0_avmm_write,
		.phy0_avmm_address,
		.phy0_avmm_writedata,
		.phy0_avmm_readdatavalid,
		.phy0_avmm_readdata,
		.phy0_avmm_waitrequest,
		.phy1_avmm_read,
		.phy1_avmm_write,
		.phy1_avmm_address,
		.phy1_avmm_writedata,
		.phy1_avmm_readdatavalid,
		.phy1_avmm_readdata,
		.phy1_avmm_waitrequest,
		.phy2_avmm_read,
		.phy2_avmm_write,
		.phy2_avmm_address,
		.phy2_avmm_writedata,
		.phy2_avmm_readdatavalid,
		.phy2_avmm_readdata,
		.phy2_avmm_waitrequest,
		.phy3_avmm_read,
		.phy3_avmm_write,
		.phy3_avmm_address,
		.phy3_avmm_writedata,
		.phy3_avmm_readdatavalid,
		.phy3_avmm_readdata,
		.phy3_avmm_waitrequest,
		.phy4_avmm_read		(),
		.phy4_avmm_write	(),
		.phy4_avmm_address	(),
		.phy4_avmm_writedata	(),
		.phy4_avmm_readdatavalid('0),
		.phy4_avmm_readdata	('0),
		.phy4_avmm_waitrequest	('0),
		.phy5_avmm_read		(),
		.phy5_avmm_write	(),
		.phy5_avmm_address	(),
		.phy5_avmm_writedata	(),
		.phy5_avmm_readdatavalid('0),
		.phy5_avmm_readdata	('0),
		.phy5_avmm_waitrequest	('0),
		.phy6_avmm_read		(),
		.phy6_avmm_write	(),
		.phy6_avmm_address	(),
		.phy6_avmm_writedata	(),
		.phy6_avmm_readdatavalid('0),
		.phy6_avmm_readdata	('0),
		.phy6_avmm_waitrequest	('0),
		.phy7_avmm_read		(),
		.phy7_avmm_write	(),
		.phy7_avmm_address	(),
		.phy7_avmm_writedata	(),
		.phy7_avmm_readdatavalid('0),
		.phy7_avmm_readdata	('0),
		.phy7_avmm_waitrequest	('0)
	);

	assign p1_toolkit_mode          = '0;
	assign dtk_p1_avmm_read         = '0;
	assign dtk_p1_avmm_write        = '0;
	assign dtk_p1_avmm_address      = '0;
	assign dtk_p1_avmm_writedata    = '0;
	assign p1_dtk_ss_avmm_read      = '0;
	assign p1_dtk_ss_avmm_write     = '0;
	assign p1_dtk_ss_avmm_address   = '0;
	assign p1_dtk_ss_avmm_writedata = '0;


     end else begin : gen_no_dtk
	assign p0_toolkit_mode          = '0;
	assign p1_toolkit_mode          = '0;
	assign dtk_p0_avmm_read         = '0;
	assign dtk_p0_avmm_write        = '0;
	assign dtk_p0_avmm_address      = '0;
	assign dtk_p0_avmm_writedata    = '0;
	assign dtk_p1_avmm_read         = '0;
	assign dtk_p1_avmm_write        = '0;
	assign dtk_p1_avmm_address      = '0;
	assign dtk_p1_avmm_writedata    = '0;
	assign p0_dtk_ss_avmm_read      = '0;
	assign p0_dtk_ss_avmm_write     = '0;
	assign p0_dtk_ss_avmm_address   = '0;
	assign p0_dtk_ss_avmm_writedata = '0;
	assign p1_dtk_ss_avmm_read      = '0;
	assign p1_dtk_ss_avmm_write     = '0;
	assign p1_dtk_ss_avmm_address   = '0;
	assign p1_dtk_ss_avmm_writedata = '0;
     end
endgenerate


endmodule


