-- gts_system_pll_intel_systemclk_gts_spll_hal_501_cjra5dy.vhd

-- Generated using ACDS version 25.1 129

library IEEE;
library spll_hal_2100;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity gts_system_pll_intel_systemclk_gts_spll_hal_501_cjra5dy is
	generic (
		sys_pll_c0_output_enable_atom  : string                        := "SYS_PLL_C0_OUTPUT_ENABLE_ENABLE";
		sys_pll_c1_output_enable_atom  : string                        := "SYS_PLL_C1_OUTPUT_ENABLE_ENABLE";
		sys_pll_c2_output_enable_atom  : string                        := "SYS_PLL_C2_OUTPUT_ENABLE_ENABLE";
		sys_pll_c3_output_enable_atom  : string                        := "SYS_PLL_C3_OUTPUT_ENABLE_DISABLE";
		sys_pll_f_ref_hz_atom          : std_logic_vector(35 downto 0) := "000000000101111101011110000100000000";
		sys_pll_f_out_c0_hz_atom       : std_logic_vector(35 downto 0) := "000000010001111000011010001100000000";
		sys_pll_f_out_c1_hz_atom       : std_logic_vector(35 downto 0) := "000000010001111000011010001100000000";
		sys_pll_f_out_c2_hz_atom       : std_logic_vector(35 downto 0) := "000000010001111000011010001100000000";
		sys_pll_f_out_c3_hz_atom       : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
		pll_primary_use_atom           : string                        := "PLL_PRIMARY_USE_PCIE";
		sys_pll_preset_atom            : string                        := "SYS_PLL_PRESET_FREQ_300_100";
		sys_pll_f_pfd_hz_atom          : std_logic_vector(35 downto 0) := "000000000101111101011110000100000000";
		sys_pll_f_vco_hz_atom          : std_logic_vector(35 downto 0) := "000010001111000011010001100000000000";
		sys_pll_n_counter_atom         : std_logic_vector(4 downto 0)  := "00001";
		sys_pll_m_counter_atom         : std_logic_vector(9 downto 0)  := "0000011000";
		sys_pll_k_counter_atom         : std_logic_vector(23 downto 0) := "000000000000000000000000";
		sys_pll_c0_counter_atom        : std_logic_vector(10 downto 0) := "00000001000";
		sys_pll_c1_counter_atom        : std_logic_vector(10 downto 0) := "00000001000";
		sys_pll_c2_counter_atom        : std_logic_vector(10 downto 0) := "00000001000";
		sys_pll_c3_counter_atom        : std_logic_vector(10 downto 0) := "00000000000";
		sys_pll_fractional_enable_atom : string                        := "SYS_PLL_FRACTIONAL_ENABLE_DISABLE";
		pll_always_on_atom             : string                        := "PLL_ALWAYS_ON_ALWAYS_ON_ENABLED";
		sup_mode_atom                  : string                        := "SUP_MODE_USER_MODE"
	);
	port (
		o_spll_lock  : out std_logic;        --  o_spll_lock.out_systempll_synthlock
		o_syspll_c0  : out std_logic;        --  o_syspll_c0.clk
		o_syspll_c1  : out std_logic;        --  o_syspll_c1.clk
		o_syspll_c2  : out std_logic;        --  o_syspll_c2.clk
		i_refclk     : in  std_logic := '0'; --  refclk_xcvr.clk
		i_refclk_rdy : in  std_logic := '0'  -- i_refclk_rdy.data
	);
end entity gts_system_pll_intel_systemclk_gts_spll_hal_501_cjra5dy;

architecture rtl of gts_system_pll_intel_systemclk_gts_spll_hal_501_cjra5dy is
	component gts_system_pll_spll_hal_2100_egfjwmi_cmp is
		generic (
			sys_pll_c0_output_enable_atom  : string                        := "";
			sys_pll_c1_output_enable_atom  : string                        := "";
			sys_pll_c2_output_enable_atom  : string                        := "";
			sys_pll_c3_output_enable_atom  : string                        := "";
			sys_pll_f_ref_hz_atom          : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			sys_pll_f_out_c0_hz_atom       : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			sys_pll_f_out_c1_hz_atom       : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			sys_pll_f_out_c2_hz_atom       : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			sys_pll_f_out_c3_hz_atom       : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			pll_primary_use_atom           : string                        := "";
			sys_pll_preset_atom            : string                        := "";
			sys_pll_f_pfd_hz_atom          : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			sys_pll_f_vco_hz_atom          : std_logic_vector(35 downto 0) := "000000000000000000000000000000000000";
			sys_pll_n_counter_atom         : std_logic_vector(4 downto 0)  := "00000";
			sys_pll_m_counter_atom         : std_logic_vector(9 downto 0)  := "0000000000";
			sys_pll_k_counter_atom         : std_logic_vector(23 downto 0) := "000000000000000000000000";
			sys_pll_c0_counter_atom        : std_logic_vector(10 downto 0) := "00000000000";
			sys_pll_c1_counter_atom        : std_logic_vector(10 downto 0) := "00000000000";
			sys_pll_c2_counter_atom        : std_logic_vector(10 downto 0) := "00000000000";
			sys_pll_c3_counter_atom        : std_logic_vector(10 downto 0) := "00000000000";
			sys_pll_fractional_enable_atom : string                        := "";
			pll_always_on_atom             : string                        := "";
			sup_mode_atom                  : string                        := ""
		);
		port (
			o_spll_lock  : out std_logic;        -- out_systempll_synthlock
			o_syspll_c0  : out std_logic;        -- clk
			o_syspll_c1  : out std_logic;        -- clk
			o_syspll_c2  : out std_logic;        -- clk
			i_refclk     : in  std_logic := 'X'; -- clk
			i_refclk_rdy : in  std_logic := 'X'  -- data
		);
	end component gts_system_pll_spll_hal_2100_egfjwmi_cmp;

	for spll_hal_top : gts_system_pll_spll_hal_2100_egfjwmi_cmp
		use entity spll_hal_2100.gts_system_pll_spll_hal_2100_egfjwmi;
begin

	sys_pll_c0_output_enable_atom_check : if sys_pll_c0_output_enable_atom /= "SYS_PLL_C0_OUTPUT_ENABLE_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_c1_output_enable_atom_check : if sys_pll_c1_output_enable_atom /= "SYS_PLL_C1_OUTPUT_ENABLE_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_c2_output_enable_atom_check : if sys_pll_c2_output_enable_atom /= "SYS_PLL_C2_OUTPUT_ENABLE_ENABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_c3_output_enable_atom_check : if sys_pll_c3_output_enable_atom /= "SYS_PLL_C3_OUTPUT_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_f_ref_hz_atom_check : if sys_pll_f_ref_hz_atom /= "000000000101111101011110000100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_f_out_c0_hz_atom_check : if sys_pll_f_out_c0_hz_atom /= "000000010001111000011010001100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_f_out_c1_hz_atom_check : if sys_pll_f_out_c1_hz_atom /= "000000010001111000011010001100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_f_out_c2_hz_atom_check : if sys_pll_f_out_c2_hz_atom /= "000000010001111000011010001100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_f_out_c3_hz_atom_check : if sys_pll_f_out_c3_hz_atom /= "000000000000000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pll_primary_use_atom_check : if pll_primary_use_atom /= "PLL_PRIMARY_USE_PCIE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_preset_atom_check : if sys_pll_preset_atom /= "SYS_PLL_PRESET_FREQ_300_100" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_f_pfd_hz_atom_check : if sys_pll_f_pfd_hz_atom /= "000000000101111101011110000100000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_f_vco_hz_atom_check : if sys_pll_f_vco_hz_atom /= "000010001111000011010001100000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_n_counter_atom_check : if sys_pll_n_counter_atom /= "00001" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_m_counter_atom_check : if sys_pll_m_counter_atom /= "0000011000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_k_counter_atom_check : if sys_pll_k_counter_atom /= "000000000000000000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_c0_counter_atom_check : if sys_pll_c0_counter_atom /= "00000001000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_c1_counter_atom_check : if sys_pll_c1_counter_atom /= "00000001000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_c2_counter_atom_check : if sys_pll_c2_counter_atom /= "00000001000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_c3_counter_atom_check : if sys_pll_c3_counter_atom /= "00000000000" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sys_pll_fractional_enable_atom_check : if sys_pll_fractional_enable_atom /= "SYS_PLL_FRACTIONAL_ENABLE_DISABLE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	pll_always_on_atom_check : if pll_always_on_atom /= "PLL_ALWAYS_ON_ALWAYS_ON_ENABLED" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	sup_mode_atom_check : if sup_mode_atom /= "SUP_MODE_USER_MODE" generate
		assert false report "Supplied generics do not match expected generics" severity Failure;
	end generate;

	spll_hal_top : component gts_system_pll_spll_hal_2100_egfjwmi_cmp
		generic map (
			sys_pll_c0_output_enable_atom  => "SYS_PLL_C0_OUTPUT_ENABLE_ENABLE",
			sys_pll_c1_output_enable_atom  => "SYS_PLL_C1_OUTPUT_ENABLE_ENABLE",
			sys_pll_c2_output_enable_atom  => "SYS_PLL_C2_OUTPUT_ENABLE_ENABLE",
			sys_pll_c3_output_enable_atom  => "SYS_PLL_C3_OUTPUT_ENABLE_DISABLE",
			sys_pll_f_ref_hz_atom          => "000000000101111101011110000100000000",
			sys_pll_f_out_c0_hz_atom       => "000000010001111000011010001100000000",
			sys_pll_f_out_c1_hz_atom       => "000000010001111000011010001100000000",
			sys_pll_f_out_c2_hz_atom       => "000000010001111000011010001100000000",
			sys_pll_f_out_c3_hz_atom       => "000000000000000000000000000000000000",
			pll_primary_use_atom           => "PLL_PRIMARY_USE_PCIE",
			sys_pll_preset_atom            => "SYS_PLL_PRESET_FREQ_300_100",
			sys_pll_f_pfd_hz_atom          => "000000000101111101011110000100000000",
			sys_pll_f_vco_hz_atom          => "000010001111000011010001100000000000",
			sys_pll_n_counter_atom         => "00001",
			sys_pll_m_counter_atom         => "0000011000",
			sys_pll_k_counter_atom         => "000000000000000000000000",
			sys_pll_c0_counter_atom        => "00000001000",
			sys_pll_c1_counter_atom        => "00000001000",
			sys_pll_c2_counter_atom        => "00000001000",
			sys_pll_c3_counter_atom        => "00000000000",
			sys_pll_fractional_enable_atom => "SYS_PLL_FRACTIONAL_ENABLE_DISABLE",
			pll_always_on_atom             => "PLL_ALWAYS_ON_ALWAYS_ON_ENABLED",
			sup_mode_atom                  => "SUP_MODE_USER_MODE"
		)
		port map (
			o_spll_lock  => o_spll_lock,  --  o_spll_lock.out_systempll_synthlock
			o_syspll_c0  => o_syspll_c0,  --  o_syspll_c0.clk
			o_syspll_c1  => o_syspll_c1,  --  o_syspll_c1.clk
			o_syspll_c2  => o_syspll_c2,  --  o_syspll_c2.clk
			i_refclk     => i_refclk,     --  refclk_xcvr.clk
			i_refclk_rdy => i_refclk_rdy  -- i_refclk_rdy.data
		);

end architecture rtl; -- of gts_system_pll_intel_systemclk_gts_spll_hal_501_cjra5dy
