// (C) 2001-2025 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License Subscription 
// Agreement, Altera IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the applicable 
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`ifdef ALTERA_RESERVED_QIS
// See https://wiki.ith.intel.com/pages/viewpage.action?pageId=3466839469#SMHSSIMisc.Notes-__USE_SOF_SETTINGS__
`ifndef __TILE_IP_SIM_FLOW__
`define __USE_SOF_SETTINGS__
`endif
`endif

//------------------------------------------------------------------------------
 
  module phy_hal_coreip 
  #(
        parameter ch_l_xcvr_tx_preloaded_hardware_configs_atom     = "TX_PRELOADED_HARDWARE_CONFIGS_NONE"       ,
        parameter ch_l_xcvr_tx_protocol_hint_atom                  = "TX_PROTOCOL_HINT_DISABLED"                ,
        parameter ch_l_xcvr_tx_datarate_bps_atom                   = 37'b0000000000000000000000000000000000000  ,
        parameter ch_l_xcvr_tx_prbs_gen_en_atom                    = "TX_PRBS_GEN_EN_DISABLE"                   ,
        parameter ch_l_xcvr_tx_prbs_pattern_atom                   = 4'b1001                                    ,
        parameter ch_l_xcvr_tx_bond_size_atom                      = "TX_BOND_SIZE_UNUSED"                      ,
        parameter ch_l_xcvr_tx_user_clk_only_mode_atom             = "TX_USER_CLK_ONLY_MODE_DISABLE"            ,
        parameter ch_l_xcvr_tx_width_atom                          = "TX_WIDTH_DISABLED"                        ,
        parameter ch_l_xcvr_tx_word_clk_hz_atom                    = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_xcvr_tx_dl_enable_atom                      = "TX_DL_ENABLE_DISABLE"                     ,
        parameter ch_l_xcvr_rx_preloaded_hardware_configs_atom     = "RX_PRELOADED_HARDWARE_CONFIGS_NONE"       ,
        parameter ch_l_xcvr_rx_protocol_hint_atom                  = "RX_PROTOCOL_HINT_DISABLED"                ,
        parameter ch_l_xcvr_rx_datarate_bps_atom                   = 37'b0000000000000000000000000000000000000  ,
        parameter ch_l_xcvr_rx_prbs_monitor_en_atom                = "RX_PRBS_MONITOR_EN_DISABLE"               ,
        parameter ch_l_xcvr_rx_prbs_pattern_atom                   = 4'b1001                                    ,   
        parameter ch_l_xcvr_rx_width_atom                          = "RX_WIDTH_DISABLED"                        ,   
        parameter ch_l_xcvr_rx_force_cdr_ltr_atom                  = "FALSE"                                    ,
        parameter ch_l_xcvr_rx_adaptation_mode_atom                = "RX_ADAPTATION_MODE_DISABLED"              ,   
        parameter ch_l_xcvr_rx_word_clk_hz_atom                    = 36'b000000000000000000000000000000000000   ,   
        parameter ch_l_xcvr_rx_dl_enable_atom                      = "RX_DL_ENABLE_DISABLE"                     ,
        parameter ch_l_rx_postdiv_clk_en_atom                      = "RX_POSTDIV_CLK_EN_DISABLE"                ,
        parameter ch_l_rx_postdiv_clk_divider_atom                 = 8'b00000001                                ,
        parameter ch_l_tx_postdiv_clk_divider_atom                 = 8'b00000001                                ,
        parameter ch_l_tx_pll_refclk_select_atom                   = "TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0"      ,
        parameter ch_l_loopback_mode_atom                          = "LOOPBACK_MODE_DISABLED"                   ,
        parameter ch_flux_l_flux_mode_atom                         = "FLUX_MODE_DISABLED"                       ,
        parameter ch_flux_l_rx_protocol_hint_atom                  = "RX_PROTOCOL_HINT_DISABLED"                ,
        parameter ch_flux_l_tx_dl_enable_atom                      = "TX_DL_ENABLE_ENABLE"                      ,   
        parameter ch_flux_l_rx_dl_enable_atom                      = "RX_DL_ENABLE_ENABLE"                      ,
        parameter ch_xcvrif_l_tx_dl_enable_atom                    = "TX_DL_ENABLE_ENABLE"                      ,
        parameter ch_xcvrif_l_rx_dl_enable_atom                    = "RX_DL_ENABLE_ENABLE"                      ,
        parameter ch_xcvrif_l_loopback_mode_atom                   = "LOOPBACK_MODE_DISABLE"                    ,
        parameter ch_xcvrif_l_tx_fifo_mode_atom                    = "TX_FIFO_MODE_DISABLED"                    ,
        parameter ch_xcvrif_l_rx_fifo_mode_atom                    = "RX_FIFO_MODE_DISABLED"                    ,
        parameter ch_xcvrif_l_tx_bond_size_atom                    = "TX_BOND_SIZE_UNUSED"                      ,
        parameter ch_flux_l_tx_bond_size_atom                      = "TX_BOND_SIZE_UNUSED"                      ,
        parameter ch_xcvrif_l_rx_bond_size_atom                    = "RX_BOND_SIZE_UNUSED"                      ,
        parameter ch_l_xcvr_tx_en_atom                             = "FALSE"                                    ,           
        parameter ch_l_xcvr_rx_en_atom                             = "FALSE"                                    ,
        parameter ch_l_duplex_mode_atom                            = "DUPLEX_MODE_DUPLEX"                       ,
        parameter ch_xcvrif_l_tx_en_atom                           = "FALSE"                                    ,
        parameter ch_xcvrif_l_rx_en_atom                           = "FALSE"                                    ,
        parameter ch_xcvrif_l_duplex_mode_atom                     = "DUPLEX_MODE_DUPLEX"                       ,
        parameter ch_flux_l_rx_fec_type_used_atom                  = "RX_FEC_TYPE_USED_NONE"                    ,
        parameter ch_l_sim_mode_atom                               = "SIM_MODE_ENABLE"                          ,
        parameter ch_flux_l_rx_sim_mode_atom                       = "RX_SIM_MODE_ENABLE"                       ,
        parameter ch_flux_l_tx_sim_mode_atom                       = "TX_SIM_MODE_ENABLE"                       ,
        parameter ch_flux_l_dr_enabled_atom                        = "DR_ENABLED_DR_ENABLED"                    ,
        parameter ch_xcvrif_l_sup_mode_atom                        = "SUP_MODE_USER_MODE"                       ,
        parameter ch_xcvrif_l_sim_mode_atom                        = "SIM_MODE_DISABLE"                         ,
        parameter ch_xcvrif_l_dr_enabled_atom                      = "DR_ENABLED_DR_ENABLED"                    ,
        parameter ch_l_xcvr_tx_spread_spectrum_en_atom             = "TX_SPREAD_SPECTRUM_EN_ENABLE"             ,
        parameter ch_l_xcvr_cdr_f_ref_hz_atom                      = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_xcvr_cdr_f_vco_hz_atom                      = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_xcvr_cdr_f_out_hz_atom                      = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_xcvr_cdr_f_pfd_hz_atom                      = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_cdr_l_counter_atom                          = 6'b000001                                  ,
        parameter ch_l_cdr_m_counter_atom                          = 9'b000000001                               ,
        parameter ch_l_cdr_n_counter_atom                          = 6'b000001                                  ,
        parameter ch_l_tx_pll_f_ref_hz_atom                        = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_tx_pll_f_out_hz_atom                        = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_tx_pll_f_pfd_hz_atom                        = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_tx_pll_f_vco_hz_atom                        = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_tx_pll_k_counter_atom                       = 22'b0000000000000000000000                 ,
        parameter ch_l_tx_pll_l_counter_atom                       = 6'b000001                                  ,
        parameter ch_l_tx_pll_m_counter_atom                       = 9'b000000001                               ,
        parameter ch_l_tx_pll_n_counter_atom                       = 6'b000001                                  ,
        parameter ch_l_tx_pll_fb_counter_atom                      = 2'b10                                      ,
        parameter ch_l_tx_pll_postdiv_sel_sm4_atom                 = "TX_PLL_POSTDIV_SEL_SYNTH_FAST"            ,
        parameter ch_l_tx_pll_postdiv_sel_sm7_atom                 = "TX_PLL_POSTDIV_SEL_SYNTH_FAST"            ,
        parameter ch_l_tx_synthdiv_out_hz_atom                     = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_tx_synthdiv_out_divider_atom                = 8'b00000001                                ,
        parameter ch_l_tx_postdiv_cdr_refclk_hz_atom               = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_tx_postdiv_cdr_refclk_divider_atom          = 8'b00000001                                ,
        parameter ch_l_rx_postdiv_clk_hz_atom                      = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_rx_postdiv_clk_fractional_en_atom           = "RX_POSTDIV_CLK_FRACTIONAL_EN_DISABLE"     ,
        parameter ch_l_cdr_refclk_select_atom                      = "CDR_REFCLK_SELECT_GLOBAL_REFCLK0"         ,
        parameter ch_l_tx_postdiv_clk_hz_atom                      = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_tx_postdiv_clk_fractional_en_atom           = "TX_POSTDIV_CLK_FRACTIONAL_EN_DISABLE"     ,
        parameter ch_flux_l_lc_postdiv_sel_atom                    = "LC_POSTDIV_SEL_SYNTH_FAST"                ,
        parameter ch_flux_l_tx_user1_clk_mux_dynamic_sel_atom      = "TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED"      ,
        parameter ch_flux_l_tx_user2_clk_mux_dynamic_sel_atom      = "TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED"      ,
        parameter ch_flux_l_rx_user1_clk_mux_dynamic_sel_atom      = "RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED"      ,
        parameter ch_flux_l_rx_user2_clk_mux_dynamic_sel_atom      = "RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED"      ,
        parameter ch_xcvrif_l_tx_gb_width_atom                     = "TX_GB_WIDTH_DISABLED"                     ,
        parameter ch_xcvrif_l_rx_gb_width_atom                     = "RX_GB_WIDTH_DISABLED"                     ,
        parameter ch_xcvrif_l_tx_dynamic_mux_atom                  = "TX_DYNAMIC_MUX_UNUSED"                    ,
        parameter ch_xcvrif_l_tx_word_clk_dynamic_mux_atom         = "TX_WORD_CLK_DYNAMIC_MUX_UNUSED"           ,
        parameter ch_xcvrif_l_rx_word_clk_dynamic_mux_atom         = "RX_WORD_CLK_DYNAMIC_MUX_RXWORD_CLK"       ,
        parameter ch_xcvrif_l_tx_fifo_rd_en_dynamic_mux_atom       = "TX_FIFO_RD_EN_DYNAMIC_MUX_UNUSED"         ,
        parameter ch_xcvrif_l_rx_fifo_rd_en_dynamic_mux_atom       = "RX_FIFO_RD_EN_DYNAMIC_MUX_UNUSED"         ,
        parameter ch_xcvrif_l_tx_rst_dynamic_mux_atom              = "TX_RST_DYNAMIC_MUX_UNUSED"                ,
        parameter ch_l_clk_debug_select_0_enable_atom              = "CLK_DEBUG_SELECT_0_ENABLE_DISABLE"        ,
        parameter ch_l_clk_debug_select_0_setting_atom             = "CLK_DEBUG_SELECT_0_SETTING_DISABLED"      ,
        parameter ch_l_clk_debug_select_1_enable_atom              = "CLK_DEBUG_SELECT_1_ENABLE_DISABLE"        ,
        parameter ch_l_clk_debug_select_1_setting_atom             = "CLK_DEBUG_SELECT_1_SETTING_DISABLED"      ,
        parameter ch_l_xcvr_tx_eq_main_tap_atom                    = 6'b000000                                  ,
        parameter ch_l_xcvr_tx_eq_post_tap_1_atom                  = 5'b00000                                   ,
        parameter ch_l_xcvr_tx_eq_pre_tap_1_atom                   = 5'b00000                                   ,
        parameter ch_l_xcvr_tx_eq_pre_tap_2_atom                   = 3'b000                                     ,
        parameter ch_l_tx_pll_feed_forward_gain_atom               = 8'b00000001                                ,
        parameter ch_l_xcvr_rx_termination_mode_atom               = "RX_TERMINATION_MODE_HIGH_Z"               ,
        parameter ch_l_xcvr_rx_onchip_termination_setting_atom     = "RX_ONCHIP_TERMINATION_SETTING_R_1"        ,
        parameter ch_l_xcvr_rx_eq_vga_gain_atom                    = 7'b0000000                                 ,
        parameter ch_l_xcvr_x_eq_hf_boost_atom                     = 6'b000000                                  ,
        parameter ch_l_xcvr_rx_eq_dfe_tap_1_atom                   = 6'b000000                                  ,
        parameter ch_l_xcvr_rx_external_couple_type_atom           = "RX_EXTERNAL_COUPLE_TYPE_AC"               ,
        parameter ch_l_tx_pll_bw_sel_atom                          = "TX_PLL_BW_SEL_LOW"                        ,
        parameter ch_l_xcvr_tx_bonding_category_atom               = "TX_BONDING_CATEGORY_UNUSED"               ,
        parameter ch_l_xcvr_tx_master_pll_mode_atom                = "TX_MASTER_PLL_MODE_DISABLED"              ,
        parameter ch_l_xcvr_rx_cdrdivout_en_atom                   = "RX_CDRDIVOUT_EN_DISABLE"                  ,
        parameter ch_xcvrif_l_tx_bonding_mode_atom                 = "TX_BONDING_MODE_UNUSED"                   ,
        parameter ch_xcvrif_l_rx_bonding_mode_atom                 = "RX_BONDING_MODE_UNUSED"                   ,
        parameter ch_l_speed_grade_atom                            = "SPEED_GRADE_DASH_1"                       ,
        parameter ch_flux_l_sequencer_reg_en_atom                  = "SEQUENCER_REG_EN_DISABLE"                 ,
        parameter ch_usb_mode_atom                                 = "USB_MODE_DISABLED"                        ,
        parameter ch_pcie_mode_atom                                = "PCIE_MODE_DISABLED"                       ,
        parameter ch_l_ick_tx_word_clk_hz_atom                     = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_pcs_ref_clk_hz_atom                         = 36'b000000000000000000000000000000000000   ,
        parameter ch_l_lane_common_ref_clk_hz_atom                 = 36'b000000000000000000000000000000000000   ,
        parameter ch_rx_invert_pin_atom                            = "RX_INVERT_PIN_DISABLE"                    ,
        parameter ch_tx_invert_pin_atom                            = "TX_INVERT_PIN_DISABLE"                    ,
        parameter ch_vsr_mode_atom                                 = "VSR_MODE_DISABLED"                        ,
        parameter ch_rx_dl_rx_lat_bit_for_async_atom               = 18'b000000000000000000                     ,
        parameter ch_rx_dl_rxbit_cntr_pma_atom                     = "RX_DL_RXBIT_CNTR_PMA_ENABLE"              ,
        parameter ch_rx_dl_rxbit_rollover_atom                     = 18'b000000000000000000                     ,
        parameter ch_eth_rx_clk_hz_atom                            = 36'b000000000000000000000000000000000000   ,
        parameter ch_eth_tx_clk_hz_atom                            = 36'b000000000000000000000000000000000000   ,
        
        parameter ch_clkrx_refclk_cssm_fw_control_atom                = "CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE"               ,
        parameter ch_clkrx_refclk_sector_specifies_refclk_ready_atom  = "CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE" ,
        parameter ch_local_refclk_cssm_fw_control_atom                = "LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE"               ,
        parameter ch_local_refclk_sector_specifies_refclk_ready_atom  = "LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE" ,
        parameter ch_flux_l_flux_mode_hw_atom                         = "FLUX_MODE_FLUX_MODE_SNIFFER"                       ,
        parameter ch_l_xcvr_rx_adaptation_mode_hw_atom                = "RX_ADAPTATION_MODE_FLUX_ADAPTATION"                ,
        

        parameter ch_flux_l_stmux_rx_demux_sel                     = "SEL_XCVRIF"                               ,
        parameter ch_flux_l_stmux_rx_rxword_clk_demux_sel          = "SEL_ETH_RXWORD_CLK"                       ,
        parameter ch_flux_l_stmux_tx_txword_clk_demux_sel          = "SEL_ETH_TXWORD_CLK"                       ,
        parameter ch_flux_l_stmux_tx_mux_sel                       = "SEL_XCVRIF"                               ,
        parameter ch_flux_l_stmux_tx_txword_clk_mux_sel            = "SEL_XCVR_TXWORD_CLK"                      ,
        parameter ch_xcvrif_rx_ch_clk_static_mux                   = "SEL_SYS_CLK"                              ,
        parameter ch_xcvrif_tx_ch_clk_static_mux                   = "SEL_SYS_CLK"                              ,
        parameter device_die_type                                  = "MAIN_SM7"                                 ,
        parameter device_die_revisions                             = "MAIN_SM7_REVA"
        
)
(
        output          oflux_xoa_tx_n_l0_ux,
        output          oflux_xoa_tx_p_l0_ux,
        input           iflux_xia_rx_n_l0_ux,
        input           iflux_xia_rx_p_l0_ux,
        input   [79:0]  i_ss_async_pldif,        
        output  [49:0]  o_ss_async_pldif,        
        input   [79:0]  i_ss_async_pldif_pcie_mux,
        input   [19:0]  i_lavmm_addr,                       
        input   [3:0]   i_lavmm_be,
        input           i_lavmm_clk,
        input           i_lavmm_read,
        input           i_lavmm_rstn,
        input   [31:0]  i_lavmm_wdata,
        input           i_lavmm_write,
        output  [31:0]  o_lavmm_rdata,
        output          o_lavmm_rdata_valid,
        output          o_lavmm_waitreq,
        input           i_ft_rx_sclk_sync_ch,
        input           i_ft_tx_sclk_sync_ch,
        output          o_ft_rx_async_pulse_ch,
        output          o_ft_tx_async_pulse_ch,
        output          o_rxcdrlock2dataa,
        input           i_rst_ux_rx_sfrz,
        output          o_rst_flux0_cpi_cmn_busy,
        output          o_rst_oflux_rx_srds_rdy,
        output          o_rst_ux_all_synthlockstatus,
        output          o_rst_ux_rxcdrlockstatus,
//        output          o_ux_tx_ch_ptr_smpl,                                                    //Check, Raised to PFE
        input           i_ick_sclk_tx,
        input           i_ick_sclk_rx,
        input           i_rst_pld_ux_tx_pma_rst_n,
        input           i_rst_pld_ux_rx_pma_rst_n,
        output  [31:0]  o_ch_lavmm_xcvrif_rdata,
        output          o_ch_lavmm_xcvrif_rdata_valid,
        output          o_ch_lavmm_xcvrif_waitreq,
        input   [19:0]  i_ch_lavmm_xcvrif_addr,
        input   [3:0]   i_ch_lavmm_xcvrif_be,
        input           i_ch_lavmm_xcvrif_clk,
        input           i_ch_lavmm_xcvrif_read,
        input           i_ch_lavmm_xcvrif_rstn,
        input   [31:0]  i_ch_lavmm_xcvrif_wdata,
        input           i_ch_lavmm_xcvrif_write,
//        input           i_pld_rx_lat_sclk_ch,             //In r10 Removed
//        input           i_pld_tx_lat_sclk_ch,             //In r10 Removed
        output          o_rx_latency_pulse,
        output          o_tx_latency_pulse,
        input   [42:0]  i_xcvrif_tx_mux_data,                        
        output  [42:0]  o_rx_data,
        output  [1:0]   o_tx_source_sel,  
        input   [6:0]   i_ch_eth_xcvrif_tx_async,
        input           i_ch_eth_xcvrif_tx_direct,
        output  [13:0]  o_ch_eth_xcvrif_rx_async,
        output          o_ch_eth_xcvrif_rx_direct,
        input           i_rstxcvrif_xcvrif_signal_ok,
        input           i_rstxcvrif_rx_xcvrif_sfrz_n,
        input           i_rstxcvrif_xcvrif_rx_rst_n,
        input           i_rstxcvrif_tx_xcvrif_sfrz_n,
        input           i_rstxcvrif_xcvrif_tx_rst_n,
        output          o_pma_rx_sf,
        output  [2:0]   o_rx_fifo_en_sel,
        output  [2:0]   o_tx_rst_source_sel,
        input           i_ch_xcvrif_rx_fifo_rd_en,
        output          o_ch_xcvrif_rx_fifo_rd_en,
        input           i_ch_xcvrif_tx_fifo_rd_en,
        output          o_ch_xcvrif_tx_fifo_rd_en,
//        input           i_xcvr_rx_ch_clk,                 In r10 Removed
//        input           i_xcvr_tx_ch_clk,                 In r10 Removed
        output  [1:0]   o_ux_rxuser1_sel,
        output  [1:0]   o_ux_rxuser2_sel,
        output  [1:0]   o_ux_txuser1_sel,
        output  [1:0]   o_ux_txuser2_sel,
        output          o_pcs_rxpostdiv,
        output          o_pcs_rxword,
        output          o_ux_txlc_clk,
        output          o_ock_pcs_txword,
        output  [2:0]   o_tx_xcvr_wordclk_sel,
        output  [1:0]   o_rx_xcvr_wordclk_sel,
        output          o_eth_rx_ch_clk,                                                   
        input           i_eth_rx_ch_clk,
//        input           i_eth_tx_ch_clk,                                                    //NA in ch4_phy Sujoy RTL
        input  [767:0]  uxwrap_bus_in  ,                 
        output [703:0]  uxwrap_bus_out ,        
        output [19:0]   o_lavmm_addr,
        output [3:0]    o_lavmm_be,
        output          o_lavmm_clk,
        output          o_lavmm_read,
        output          o_lavmm_rstn,
        output [31:0]   o_lavmm_wdata,
        output          o_lavmm_write,   
        input  [31:0]   i_lavmm_rdata, 
        input           i_lavmm_rdata_valid,
        input           i_lavmm_waitreq,    
        output          o_sclk_return_sel_rx,
        output          o_sclk_return_sel_tx,      
        output          o_ick_sclk_rx,           
        input   [4:0]   i_sync_common_control,          
        output          o_ft_rx_sclk_sync_ch,       
        output          o_ft_tx_sclk_sync_ch,       
        output          o_rst_ux_rx_pma_rst_n,      
        output          o_rst_ux_tx_pma_rst_n,       
        output          o_ick_pcs_txword,                   
        output          o_tx_dl_ch_bit,                     
        input           i_dat_pcs_measlatbit,               
        input           i_ft_rx_async_pulse_ch,
        input           i_ft_tx_async_pulse_ch,             
        input           i_rx_dl_ch_bit,                 
        input   [1:0]   i_ux_rxuser1_sel,
        input   [1:0]   i_ux_rxuser2_sel,                   
        input   [1:0]   i_ux_txuser1_sel,
        input   [1:0]   i_ux_txuser2_sel,                   
        output          o_octl_pcs_txstatus_a,              
        input           i_ictl_pcs_txenable_a,      
        input   [124:0] i_sync_cfg_data,                
        input   [249:0] i_sync_interface_control,           
        output  [79:0]  o_tx_data,                          
        input   [79:0]  i_rx_data,                      
        output  [319:0] o_sm_flux_ingress,              
        input   [256:0] i_sm_flux_egress,                       
        input           i_flux_cpi_int,                     
        input           i_flux_int,                     
        input           i_oflux_octl_pcs_txptr_smpl_lane,   
        output          o_ick_sclk_tx,                      
        input           i_flux_srds_rdy,                    
        input           i_pcs_rxword,                           
        input           i_pcs_rxpostdiv,                    
        input           i_ock_pcs_txword,            
        output          o_dat_pcs_measlatrndtripbit,            
//        input           i_dpma_refclk,                //Connected this from cnoc atom
        output          o_ock_pcs_cdrfbclk,            
        output          o_ock_pcs_ref   ,
        output [39:0]   o_pcie_pcs,
        input [39:0]    i_pcie_pcs,
//New signals Added after r9
        input           i_sel_rxword_clk,
        input           i_xcvr_txword_clk,
        output          o_pcie_rxword_clk,
        output          o_eth_rxword_clk ,
        output          o_pcie_txword_clk,
        output          o_eth_txword_clk,
//New signals Added after r10   
        output           o_eth_tx_ch_clk,
//New Signals Added after r11       
//        input [5:0] ioack_ref_left_n_ux_bidir_in,
        input [5:0] ioack_ref_left_p_ux_bidir_in,
//        input ioack_hsref_left_n_ux_bidir_in,
        input ioack_hsref_left_p_ux_bidir_in,
//New Signals Added after r12
        input ioack_cdrdiv_left_ux_bidir_in,
        input ioack_synthdiv1_left_ux_bidir_in,
        input ioack_synthdiv2_left_ux_bidir_in,
        output ioack_cdrdiv_left_ux_bidir_out,
        output ioack_synthdiv1_left_ux_bidir_out,
        output ioack_synthdiv2_left_ux_bidir_out,

//KAHUAT_EDIT
        output [13:0] o_rxeq_best_eye_vala,
        output        o_rxeq_donea,
        output        o_rxmargin_nacka,
        output        o_rxmargin_statusa,
        output        o_rxsignaldetect_lfpsa,
        output        o_rxsignaldetecta,
        output [1:0]  o_rxmargin_status_gray,
        output        o_synthlcfast_postdiv,
        output        o_synthlcmed_postdiv,
        output        o_synthlcslow_postdiv,
        output        o_txdetectrx_acka,
        output        o_txdetectrx_statct,
        input         i_pcs_pipe_rstn,
        input         i_ux_ock_pma_clk,
        input         i_lfps_ennt,
        input  [1:0]  i_pcie_l1ctrla,
        input         i_pma_cmn_ctrl,
        input         i_pma_ctrl,
        input         i_pcie_pcs_rx_rst,
        input         i_pcie_pcs_tx_rst,
        input         i_rxeiosdetectstata,
        input  [2:0]  i_rxeq_precal_code_selnt,
        input         i_rxeq_starta,
        input         i_rxeq_static_ena,
        input         i_rxmargin_direction_nt,
        input         i_rxmargin_mode_nt,
        input         i_rxmargin_offset_change_a,
        input  [6:0]  i_rxmargin_offset_nt,     
        input         i_rxmargin_start_a,
        input  [2:0]  i_rxpstate,
        input  [3:0]  i_rxrate,
        input         i_rxterm_hiz_ena,
        input  [2:0]  i_rxwidth,
        input         i_tstbus_lane,
        input         i_txbeacona,
        input  [2:0]  i_txclkdivrate,
        input         i_txdetectrx_reqa,
        input  [5:0]  i_txdrv_levn,
        input  [4:0]  i_txdrv_levnm1,
        input  [2:0]  i_txdrv_levnm2,
        input  [4:0]  i_txdrv_levnp1,
        input  [3:0]  i_txdrv_slew,
        input  [3:0]  i_txelecidle,
        input  [2:0]  i_txpstate,
        input  [3:0]  i_txrate,
        input  [2:0]  i_txwidth,

        output o_rxstatusa,     //As per Kumaran Suggestion Connected this port to PLDIF i_ss_rst_ux_octl_pcs_rxstatus
        output o_txstatusa,      //As per Kumaran Suggestion Connected this port to PLDIF i_ss_rst_ux_octl_pcs_txstatus
        input  i_quartus_flux_s_to_ingress, //R24 Integration
        //Added in 1p0 allignment
        input  i_rstxcvrif_xcvrif_tx_rd_rst_n,
        input  i_rstxcvrif_xcvrif_tx_wr_rst_n,
        output o_tx_rst_rd_sync_rst_n,
        output o_tx_rst_wr_sync_rst_n       
);

        wire dpma_refclk;

ch4_phy #(
    .x_decoder_sm_flux_rx_demux_0__sel                                      (ch_flux_l_stmux_rx_demux_sel            ),
    .x_decoder_sm_flux_rx_rxword_clk_demux_0__sel                           (ch_flux_l_stmux_rx_rxword_clk_demux_sel ),
    .x_decoder_sm_flux_tx_txword_clk_demux_0__sel                           (ch_flux_l_stmux_tx_txword_clk_demux_sel ),
    .x_mux_sm_flux_tx_mux_0__sel                                            (ch_flux_l_stmux_tx_mux_sel              ),
    .x_mux_sm_flux_tx_txword_clk_mux_0__sel                                 (ch_flux_l_stmux_tx_txword_clk_mux_sel   ),
    .x_mux_sm_xcvrif_rx_ch_clk_mux_0__sel                                   (ch_xcvrif_rx_ch_clk_static_mux     ),
    .x_mux_sm_xcvrif_tx_ch_clk_mux_0__sel                                   (ch_xcvrif_tx_ch_clk_static_mux     ),
    .x_std_ipfluxtop_uxtop_wrap_0__cdr_f_out_hz                             (ch_l_xcvr_cdr_f_out_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__cdr_f_pfd_hz                             (ch_l_xcvr_cdr_f_pfd_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__cdr_f_ref_hz                             (ch_l_xcvr_cdr_f_ref_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__cdr_f_vco_hz                             (ch_l_xcvr_cdr_f_vco_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__cdr_l_counter                            (ch_l_cdr_l_counter_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__cdr_m_counter                            (ch_l_cdr_m_counter_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__cdr_n_counter                            (ch_l_cdr_n_counter_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__cdr_refclk_select                        (ch_l_cdr_refclk_select_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__clk_debug_select_0_enable                (ch_l_clk_debug_select_0_enable_atom ),
    .x_std_ipfluxtop_uxtop_wrap_0__clk_debug_select_0_setting               (ch_l_clk_debug_select_0_setting_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__clk_debug_select_1_enable                (ch_l_clk_debug_select_1_enable_atom ),
    .x_std_ipfluxtop_uxtop_wrap_0__clk_debug_select_1_setting               (ch_l_clk_debug_select_1_setting_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__duplex_mode                              (ch_l_duplex_mode_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__ick_tx_word_clk_hz                       (ch_l_ick_tx_word_clk_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__lane_common_ref_clk_hz                   (ch_l_lane_common_ref_clk_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__loopback_mode                            (ch_l_loopback_mode_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__pcie_mode                                (ch_pcie_mode_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__pcs_ref_clk_hz                           (ch_l_pcs_ref_clk_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_cdrdivout_en                          (ch_l_xcvr_rx_cdrdivout_en_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_datarate_bps                          (ch_l_xcvr_rx_datarate_bps_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_en                                    (ch_l_xcvr_rx_en_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_eq_dfe_tap_1                          (ch_l_xcvr_rx_eq_dfe_tap_1_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_eq_hf_boost                           (ch_l_xcvr_x_eq_hf_boost_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_eq_vga_gain                           (ch_l_xcvr_rx_eq_vga_gain_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_external_couple_type                  (ch_l_xcvr_rx_external_couple_type_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_invert_pin                            (ch_rx_invert_pin_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_force_cdr_ltr                         (ch_l_xcvr_rx_force_cdr_ltr_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_onchip_termination_setting            (ch_l_xcvr_rx_onchip_termination_setting_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_postdiv_clk_divider                   (ch_l_rx_postdiv_clk_divider_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_postdiv_clk_en                        (ch_l_rx_postdiv_clk_en_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_postdiv_clk_fractional_en             (ch_l_rx_postdiv_clk_fractional_en_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_postdiv_clk_hz                        (ch_l_rx_postdiv_clk_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_prbs_monitor_en                       (ch_l_xcvr_rx_prbs_monitor_en_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_prbs_pattern                          (ch_l_xcvr_rx_prbs_pattern_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_preloaded_hardware_configs            (ch_l_xcvr_rx_preloaded_hardware_configs_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_protocol_hint                         (ch_l_xcvr_rx_protocol_hint_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_width                                 (ch_l_xcvr_rx_width_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_word_clk_hz                           (ch_l_xcvr_rx_word_clk_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__speed_grade                              (ch_l_speed_grade_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_bond_size                             (ch_l_xcvr_tx_bond_size_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_bonding_category                      (ch_l_xcvr_tx_bonding_category_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_datarate_bps                          (ch_l_xcvr_tx_datarate_bps_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_en                                    (ch_l_xcvr_tx_en_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_eq_pre_tap_1                          (ch_l_xcvr_tx_eq_pre_tap_1_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_eq_pre_tap_2                          (ch_l_xcvr_tx_eq_pre_tap_2_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_invert_pin                            (ch_tx_invert_pin_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__vsr_mode                                 (ch_vsr_mode_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_master_pll_mode                       (ch_l_xcvr_tx_master_pll_mode_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_pll_bw_sel                            (ch_l_tx_pll_bw_sel_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_pll_f_out_hz                          (ch_l_tx_pll_f_out_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_pll_f_pfd_hz                          (ch_l_tx_pll_f_pfd_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_pll_f_ref_hz                          (ch_l_tx_pll_f_ref_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_pll_f_vco_hz                          (ch_l_tx_pll_f_vco_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_pll_fb_counter                        (ch_l_tx_pll_fb_counter_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_pll_feed_forward_gain                 (ch_l_tx_pll_feed_forward_gain_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_pll_k_counter                         (ch_l_tx_pll_k_counter_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_pll_l_counter                         (ch_l_tx_pll_l_counter_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_pll_m_counter                         (ch_l_tx_pll_m_counter_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_pll_n_counter                         (ch_l_tx_pll_n_counter_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_pll_postdiv_sel                       ((device_die_revisions == "MAIN_SM7_REVA")? ch_l_tx_pll_postdiv_sel_sm7_atom : ch_l_tx_pll_postdiv_sel_sm4_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_pll_refclk_select                     (ch_l_tx_pll_refclk_select_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_cdr_refclk_divider            (ch_l_tx_postdiv_cdr_refclk_divider_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_cdr_refclk_hz                 (ch_l_tx_postdiv_cdr_refclk_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_clk_divider                   (ch_l_tx_postdiv_clk_divider_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_clk_fractional_en             (ch_l_tx_postdiv_clk_fractional_en_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_clk_hz                        (ch_l_tx_postdiv_clk_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_prbs_gen_en                           (ch_l_xcvr_tx_prbs_gen_en_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_prbs_pattern                          (ch_l_xcvr_tx_prbs_pattern_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_preloaded_hardware_configs            (ch_l_xcvr_tx_preloaded_hardware_configs_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_protocol_hint                         (ch_l_xcvr_tx_protocol_hint_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_spread_spectrum_en                    (ch_l_xcvr_tx_spread_spectrum_en_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_synthdiv_out_divider                  (ch_l_tx_synthdiv_out_divider_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_synthdiv_out_hz                       (ch_l_tx_synthdiv_out_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_user_clk_only_mode                    (ch_l_xcvr_tx_user_clk_only_mode_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_width                                 (ch_l_xcvr_tx_width_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_word_clk_hz                           (ch_l_xcvr_tx_word_clk_hz_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__usb_mode                                 (ch_usb_mode_atom),
    .x_std_sm_flux_ingress_0__clkrx_refclk_cssm_fw_control                  (ch_clkrx_refclk_cssm_fw_control_atom),
    .x_std_sm_flux_ingress_0__clkrx_refclk_sector_specifies_refclk_ready    (ch_clkrx_refclk_sector_specifies_refclk_ready_atom),
    .x_std_sm_flux_ingress_0__dr_enabled                                    (ch_flux_l_dr_enabled_atom),
    .x_std_sm_flux_ingress_0__local_refclk_cssm_fw_control                  (ch_local_refclk_cssm_fw_control_atom),
    .x_std_sm_flux_ingress_0__local_refclk_sector_specifies_refclk_ready    (ch_local_refclk_sector_specifies_refclk_ready_atom),
    .x_std_sm_flux_ingress_0__rx_dl_enable                                  (ch_flux_l_rx_dl_enable_atom),
    .x_std_sm_flux_ingress_0__rx_dl_rx_lat_bit_for_async                    (ch_rx_dl_rx_lat_bit_for_async_atom),
    .x_std_sm_flux_ingress_0__rx_dl_rxbit_cntr_pma                          (ch_rx_dl_rxbit_cntr_pma_atom),
    .x_std_sm_flux_ingress_0__rx_dl_rxbit_rollover                          (ch_rx_dl_rxbit_rollover_atom),
    .x_std_sm_flux_ingress_0__rx_fec_type_used                              (ch_flux_l_rx_fec_type_used_atom),
    .x_std_sm_flux_ingress_0__rx_protocol_hint                              (ch_flux_l_rx_protocol_hint_atom),
    .x_std_sm_flux_ingress_0__rx_user1_clk_mux_dynamic_sel                  (ch_flux_l_rx_user1_clk_mux_dynamic_sel_atom),
    .x_std_sm_flux_ingress_0__rx_user2_clk_mux_dynamic_sel                  (ch_flux_l_rx_user2_clk_mux_dynamic_sel_atom),
    .x_std_sm_flux_ingress_0__sequencer_reg_en                              (ch_flux_l_sequencer_reg_en_atom),
    .x_std_sm_flux_ingress_0__tx_bond_size                                  (ch_flux_l_tx_bond_size_atom),
    .x_std_sm_flux_ingress_0__tx_dl_enable                                  (ch_flux_l_tx_dl_enable_atom),
    .x_std_sm_flux_ingress_0__tx_user1_clk_mux_dynamic_sel                  (ch_flux_l_tx_user1_clk_mux_dynamic_sel_atom),
    .x_std_sm_flux_ingress_0__tx_user2_clk_mux_dynamic_sel                  (ch_flux_l_tx_user2_clk_mux_dynamic_sel_atom),
    .x_std_sm_xcvrif_1ch_0__dr_enabled                                      (ch_xcvrif_l_dr_enabled_atom),
    .x_std_sm_xcvrif_1ch_0__duplex_mode                                     (ch_xcvrif_l_duplex_mode_atom),
    .x_std_sm_xcvrif_1ch_0__eth_rx_clk_hz                                   (ch_eth_rx_clk_hz_atom),
    .x_std_sm_xcvrif_1ch_0__eth_tx_clk_hz                                   (ch_eth_tx_clk_hz_atom),
    .x_std_sm_xcvrif_1ch_0__loopback_mode                                   (ch_xcvrif_l_loopback_mode_atom),
    .x_std_sm_xcvrif_1ch_0__rx_bond_size                                    (ch_xcvrif_l_rx_bond_size_atom),
    .x_std_sm_xcvrif_1ch_0__rx_bonding_mode                                 (ch_xcvrif_l_rx_bonding_mode_atom),
    .x_std_sm_xcvrif_1ch_0__rx_dl_enable                                    (ch_xcvrif_l_rx_dl_enable_atom),
    .x_std_sm_xcvrif_1ch_0__rx_en                                           (ch_xcvrif_l_rx_en_atom),
    .x_std_sm_xcvrif_1ch_0__rx_fifo_mode                                    (ch_xcvrif_l_rx_fifo_mode_atom),
    .x_std_sm_xcvrif_1ch_0__rx_fifo_rd_en_dynamic_mux                       (ch_xcvrif_l_rx_fifo_rd_en_dynamic_mux_atom),
    .x_std_sm_xcvrif_1ch_0__rx_gb_width                                     (ch_xcvrif_l_rx_gb_width_atom),
    .x_std_sm_xcvrif_1ch_0__rx_word_clk_dynamic_mux                         (ch_xcvrif_l_rx_word_clk_dynamic_mux_atom),
    .x_std_sm_xcvrif_1ch_0__sup_mode                                        (ch_xcvrif_l_sup_mode_atom),
    .x_std_sm_xcvrif_1ch_0__tx_bond_size                                    (ch_xcvrif_l_tx_bond_size_atom),
    .x_std_sm_xcvrif_1ch_0__tx_bonding_mode                                 (ch_xcvrif_l_tx_bonding_mode_atom),
    .x_std_sm_xcvrif_1ch_0__tx_dl_enable                                    (ch_xcvrif_l_tx_dl_enable_atom),
    .x_std_sm_xcvrif_1ch_0__tx_dynamic_mux                                  (ch_xcvrif_l_tx_dynamic_mux_atom),
    .x_std_sm_xcvrif_1ch_0__tx_en                                           (ch_xcvrif_l_tx_en_atom),
    .x_std_sm_xcvrif_1ch_0__tx_fifo_mode                                    (ch_xcvrif_l_tx_fifo_mode_atom),
    .x_std_sm_xcvrif_1ch_0__tx_fifo_rd_en_dynamic_mux                       (ch_xcvrif_l_tx_fifo_rd_en_dynamic_mux_atom),
    .x_std_sm_xcvrif_1ch_0__tx_gb_width                                     (ch_xcvrif_l_tx_gb_width_atom),
    .x_std_sm_xcvrif_1ch_0__tx_rst_dynamic_mux                              (ch_xcvrif_l_tx_rst_dynamic_mux_atom),
    .x_std_sm_xcvrif_1ch_0__xcvr_rxword_clk_hz                              (ch_l_xcvr_rx_word_clk_hz_atom),
    .x_std_sm_xcvrif_1ch_0__xcvr_txword_clk_hz                              (ch_l_xcvr_tx_word_clk_hz_atom),
    
`ifdef __USE_SOF_SETTINGS__
    .x_std_ipfluxtop_uxtop_wrap_0__rx_sim_mode                              ("RX_SIM_MODE_DISABLE"),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_sim_mode                              ("TX_SIM_MODE_DISABLE"),
    .x_std_sm_flux_ingress_0__rx_sim_mode                                   ("RX_SIM_MODE_DISABLE"),
    .x_std_sm_flux_ingress_0__tx_sim_mode                                   ("TX_SIM_MODE_DISABLE"),
    .x_std_sm_xcvrif_1ch_0__sim_mode                                        ("SIM_MODE_DISABLE"),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_adaptation_mode                       ((ch_pcie_mode_atom=="PCIE_MODE_DISABLED")? ch_l_xcvr_rx_adaptation_mode_hw_atom : ch_l_xcvr_rx_adaptation_mode_atom),
    .x_std_sm_flux_ingress_0__flux_mode                                     ((ch_pcie_mode_atom=="PCIE_MODE_DISABLED")? ch_flux_l_flux_mode_hw_atom : ch_flux_l_flux_mode_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_termination_mode                      ((ch_pcie_mode_atom=="PCIE_MODE_DISABLED")? "RX_TERMINATION_MODE_GROUNDED" : ch_l_xcvr_rx_termination_mode_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_eq_main_tap                           (ch_l_xcvr_tx_eq_main_tap_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_eq_post_tap_1                         (ch_l_xcvr_tx_eq_post_tap_1_atom),
`else
    .x_std_ipfluxtop_uxtop_wrap_0__rx_sim_mode                              (ch_flux_l_rx_sim_mode_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_sim_mode                              (ch_flux_l_tx_sim_mode_atom),
    .x_std_sm_flux_ingress_0__rx_sim_mode                                   (ch_flux_l_rx_sim_mode_atom),
    .x_std_sm_flux_ingress_0__tx_sim_mode                                   (ch_flux_l_tx_sim_mode_atom),
    .x_std_sm_xcvrif_1ch_0__sim_mode                                        (ch_xcvrif_l_sim_mode_atom),
    .x_std_sm_flux_ingress_0__flux_mode                                     (ch_flux_l_flux_mode_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_adaptation_mode                       (ch_l_xcvr_rx_adaptation_mode_atom),
    .x_std_ipfluxtop_uxtop_wrap_0__rx_termination_mode                      (ch_l_xcvr_rx_termination_mode_atom), 
    .x_std_ipfluxtop_uxtop_wrap_0__tx_eq_main_tap                           (6'b000000),
    .x_std_ipfluxtop_uxtop_wrap_0__tx_eq_post_tap_1                         (5'b00000),   
`endif
    .x_std_sm_xcvrif_1ch_0__tx_word_clk_dynamic_mux                         (ch_xcvrif_l_tx_word_clk_dynamic_mux_atom)

) ch4_phy_inst (
    .x_std_sm_flux_ingress_0__i_sync_cfg_data                           (i_sync_cfg_data),
    .x_std_sm_flux_ingress_0__i_lavmm_addr                              (i_lavmm_addr),
    .x_std_sm_xcvrif_1ch_0__i_ch_lavmm_xcvrif_addr                      (i_ch_lavmm_xcvrif_addr),
    .x_std_sm_flux_ingress_0__i_pcie_l1ctrla                            (i_pcie_l1ctrla),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_ux_rxuser1_sel                          (i_ux_rxuser1_sel),
    .x_std_sm_flux_ingress_0__i_ux_rxuser2_sel                          (i_ux_rxuser2_sel),
    .x_std_sm_flux_ingress_0__i_ux_txuser1_sel                          (i_ux_txuser1_sel),
    .x_std_sm_flux_ingress_0__i_ux_txuser2_sel                          (i_ux_txuser2_sel),
    .x_std_sm_flux_ingress_0__i_sync_interface_control                  (i_sync_interface_control),
    .x_std_sm_flux_ingress_0__i_sm_flux_egress                          (i_sm_flux_egress),
    .x_std_sm_flux_ingress_0__i_rxeq_precal_code_selnt                  (i_rxeq_precal_code_selnt),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_rxpstate                                (i_rxpstate),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_rxwidth                                 (i_rxwidth),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_txclkdivrate                            (i_txclkdivrate),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_txdrv_levnm2                            (i_txdrv_levnm2),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_txpstate                                (i_txpstate),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_txwidth                                 (i_txwidth),             //PPCS //KAHAUT_EDIT
    .x_std_sm_flux_ingress_0__i_lavmm_rdata                             (i_lavmm_rdata),
    .x_std_sm_flux_ingress_0__i_lavmm_wdata                             (i_lavmm_wdata),
    .x_std_sm_xcvrif_1ch_0__i_ch_lavmm_xcvrif_wdata                     (i_ch_lavmm_xcvrif_wdata),
    .x_mux_sm_flux_tx_mux_0__i_pcie_pcs                                 (i_pcie_pcs),
    .x_std_sm_flux_ingress_0__i_lavmm_be                                (i_lavmm_be),
    .x_std_sm_flux_ingress_0__i_rxrate                                  (i_rxrate),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_txdrv_slew                              (i_txdrv_slew),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_txelecidle                              (i_txelecidle),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_txrate                                  (i_txrate),             //PPCS //KAHAUT_EDIT
    .x_std_sm_xcvrif_1ch_0__i_ch_lavmm_xcvrif_be                        (i_ch_lavmm_xcvrif_be),
    .x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data                        (i_xcvrif_tx_mux_data),
    .x_std_sm_flux_ingress_0__i_sync_common_control                     (i_sync_common_control),
    .x_std_sm_flux_ingress_0__i_txdrv_levnm1                            (i_txdrv_levnm1),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_txdrv_levnp1                            (i_txdrv_levnp1),             //PPCS //KAHUAT_EDIT
    .x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in         (ioack_ref_left_p_ux_bidir_in),             
    .x_std_ipfluxtop_uxtop_wrap_0__ioack_cdrdiv_left_ux_bidir_in        (ioack_cdrdiv_left_ux_bidir_in),             
    .x_std_ipfluxtop_uxtop_wrap_0__ioack_hsref_left_p_ux_bidir_in       (ioack_hsref_left_p_ux_bidir_in),             
    .x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv1_left_ux_bidir_in     (ioack_synthdiv1_left_ux_bidir_in),             
    .x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv2_left_ux_bidir_in     (ioack_synthdiv2_left_ux_bidir_in),             
    .x_std_sm_flux_ingress_0__i_txdrv_levn                              (i_txdrv_levn),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_rxmargin_offset_nt                      (i_rxmargin_offset_nt),             //PPCS //KAHUAT_EDIT
    .x_std_sm_xcvrif_1ch_0__i_ch_eth_xcvrif_tx_async                    (i_ch_eth_xcvrif_tx_async),
    .x_std_ipfluxtop_uxtop_wrap_0__uxwrap_bus_in                        (uxwrap_bus_in),
    .x_std_sm_flux_ingress_0__i_rx_data                                 (i_rx_data),
    .x_std_sm_flux_ingress_0__i_ss_async_pldif                          (i_ss_async_pldif),
    .x_std_sm_flux_ingress_0__i_ss_async_pldif_pcie_mux                 (i_ss_async_pldif_pcie_mux),
    .x_mux_sm_flux_tx_txword_clk_mux_0__i_ux_ock_pma_clk                (i_ux_ock_pma_clk),             //PPCS  //KAHUAT_EDIT
    .x_mux_sm_flux_tx_txword_clk_mux_0__i_xcvr_txword_clk               (i_xcvr_txword_clk),
    .x_mux_sm_xcvrif_rx_ch_clk_mux_0__i_rxword_clk                      (i_sel_rxword_clk),
    .x_mux_sm_xcvrif_rx_ch_clk_mux_0__i_sys_clk                         (i_eth_rx_ch_clk),
    .x_std_ipfluxtop_uxtop_wrap_0__iflux_xia_rx_n_l0_ux                 (iflux_xia_rx_n_l0_ux),
    .x_std_ipfluxtop_uxtop_wrap_0__iflux_xia_rx_p_l0_ux                 (iflux_xia_rx_p_l0_ux),
   
    .x_std_sm_flux_ingress_0__i_dat_pcs_measlatbit                      (i_dat_pcs_measlatbit),
    .x_std_sm_flux_ingress_0__i_dpma_refclk                             (dpma_refclk),
    .x_std_sm_flux_ingress_0__i_flux_cpi_int                            (i_flux_cpi_int),
    .x_std_sm_flux_ingress_0__i_flux_int                                (i_flux_int),
    .x_std_sm_flux_ingress_0__i_flux_srds_rdy                           (i_flux_srds_rdy),
    .x_std_sm_flux_ingress_0__i_ft_rx_async_pulse_ch                    (i_ft_rx_async_pulse_ch),
    .x_std_sm_flux_ingress_0__i_ft_rx_sclk_sync_ch                      (i_ft_rx_sclk_sync_ch),
    .x_std_sm_flux_ingress_0__i_ft_tx_async_pulse_ch                    (i_ft_tx_async_pulse_ch),
    .x_std_sm_flux_ingress_0__i_ft_tx_sclk_sync_ch                      (i_ft_tx_sclk_sync_ch),
    .x_std_sm_flux_ingress_0__i_ictl_pcs_txenable_a                     (i_ictl_pcs_txenable_a),
    .x_std_sm_flux_ingress_0__i_lavmm_clk                               (i_lavmm_clk),
    .x_std_sm_flux_ingress_0__i_lavmm_rdata_valid                       (i_lavmm_rdata_valid),
    .x_std_sm_flux_ingress_0__i_lavmm_read                              (i_lavmm_read),
    .x_std_sm_flux_ingress_0__i_lavmm_rstn                              (i_lavmm_rstn),
    .x_std_sm_flux_ingress_0__i_lavmm_waitreq                           (i_lavmm_waitreq),
    .x_std_sm_flux_ingress_0__i_lavmm_write                             (i_lavmm_write),
    .x_std_sm_flux_ingress_0__i_lfps_ennt                               (i_lfps_ennt),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_ock_pcs_txword                          (i_ock_pcs_txword),
    .x_std_sm_flux_ingress_0__i_oflux_octl_pcs_txptr_smpl_lane          (i_oflux_octl_pcs_txptr_smpl_lane),
    .x_std_sm_flux_ingress_0__i_pcie_pcs_rx_rst                         (i_pcie_pcs_rx_rst),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_pcie_pcs_tx_rst                         (i_pcie_pcs_tx_rst),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_pcs_pipe_rstn                           (i_pcs_pipe_rstn),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_pcs_rxpostdiv                           (i_pcs_rxpostdiv),
    .x_std_sm_flux_ingress_0__i_pcs_rxword                              (i_pcs_rxword),
    .x_std_sm_flux_ingress_0__i_pma_cmn_ctrl                            (i_pma_cmn_ctrl),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_pma_ctrl                                (i_pma_ctrl),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_rst_pld_ux_rx_pma_rst_n                 (i_rst_pld_ux_rx_pma_rst_n),
    .x_std_sm_flux_ingress_0__i_rst_pld_ux_tx_pma_rst_n                 (i_rst_pld_ux_tx_pma_rst_n),
    .x_std_sm_flux_ingress_0__i_rst_ux_rx_sfrz                          (i_rst_ux_rx_sfrz),
    .x_std_sm_flux_ingress_0__i_rx_dl_ch_bit                            (i_rx_dl_ch_bit),
    .x_std_sm_flux_ingress_0__i_rxeiosdetectstata                       (i_rxeiosdetectstata),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_rxeq_starta                             (i_rxeq_starta),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_rxeq_static_ena                         (i_rxeq_static_ena),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_rxmargin_direction_nt                   (i_rxmargin_direction_nt),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_rxmargin_mode_nt                        (i_rxmargin_mode_nt),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_rxmargin_offset_change_a                (i_rxmargin_offset_change_a),     //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_rxmargin_start_a                        (i_rxmargin_start_a),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_rxterm_hiz_ena                          (i_rxterm_hiz_ena),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_tstbus_lane                             (i_tstbus_lane),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_txbeacona                               (i_txbeacona),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_txdetectrx_reqa                         (i_txdetectrx_reqa),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__i_ick_sclk_rx                             (i_ick_sclk_rx),
    .x_std_sm_flux_ingress_0__i_ick_sclk_tx                             (i_ick_sclk_tx),
    .x_std_sm_xcvrif_1ch_0__i_ch_eth_xcvrif_tx_direct                   (i_ch_eth_xcvrif_tx_direct),
    .x_std_sm_xcvrif_1ch_0__i_ch_lavmm_xcvrif_clk                       (i_ch_lavmm_xcvrif_clk),
    .x_std_sm_xcvrif_1ch_0__i_ch_lavmm_xcvrif_read                      (i_ch_lavmm_xcvrif_read),
    .x_std_sm_xcvrif_1ch_0__i_ch_lavmm_xcvrif_rstn                      (i_ch_lavmm_xcvrif_rstn),
    .x_std_sm_xcvrif_1ch_0__i_ch_lavmm_xcvrif_write                     (i_ch_lavmm_xcvrif_write),
    .x_std_sm_xcvrif_1ch_0__i_ch_xcvrif_rx_fifo_rd_en                   (i_ch_xcvrif_rx_fifo_rd_en),
    .x_std_sm_xcvrif_1ch_0__i_ch_xcvrif_tx_fifo_rd_en                   (i_ch_xcvrif_tx_fifo_rd_en),
    .x_std_sm_xcvrif_1ch_0__i_rstxcvrif_rx_xcvrif_sfrz_n                (i_rstxcvrif_rx_xcvrif_sfrz_n),
    .x_std_sm_xcvrif_1ch_0__i_rstxcvrif_tx_xcvrif_sfrz_n                (i_rstxcvrif_tx_xcvrif_sfrz_n),
    .x_std_sm_xcvrif_1ch_0__i_rstxcvrif_xcvrif_rx_rst_n                 (i_rstxcvrif_xcvrif_rx_rst_n),
    .x_std_sm_xcvrif_1ch_0__i_rstxcvrif_xcvrif_signal_ok                (i_rstxcvrif_xcvrif_signal_ok),
    .x_std_sm_xcvrif_1ch_0__i_rstxcvrif_xcvrif_tx_rd_rst_n              (i_rstxcvrif_xcvrif_tx_rd_rst_n),
    .x_std_sm_xcvrif_1ch_0__i_rstxcvrif_xcvrif_tx_rst_n                 (i_rstxcvrif_xcvrif_tx_rst_n),
    .x_std_sm_xcvrif_1ch_0__i_rstxcvrif_xcvrif_tx_wr_rst_n              (i_rstxcvrif_xcvrif_tx_wr_rst_n),
    .x_std_sm_flux_ingress_0__o_rxeq_best_eye_vala                      (o_rxeq_best_eye_vala),             //PPCS //KAHUAT_EDIT
    .x_std_sm_xcvrif_1ch_0__o_ch_eth_xcvrif_rx_async                    (o_ch_eth_xcvrif_rx_async),
    .x_std_sm_flux_ingress_0__o_lavmm_addr                              (o_lavmm_addr),
    .x_std_sm_flux_ingress_0__o_rxmargin_status_gray                    (o_rxmargin_status_gray),           //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__o_ux_rxuser1_sel                          (o_ux_rxuser1_sel),
    .x_std_sm_flux_ingress_0__o_ux_rxuser2_sel                          (o_ux_rxuser2_sel),
    .x_std_sm_flux_ingress_0__o_ux_txuser1_sel                          (o_ux_txuser1_sel),
    .x_std_sm_flux_ingress_0__o_ux_txuser2_sel                          (o_ux_txuser2_sel),
    .x_std_sm_xcvrif_1ch_0__o_tx_source_sel                             (o_tx_source_sel),
    .x_std_sm_xcvrif_1ch_0__o_rx_fifo_en_sel                            (o_rx_fifo_en_sel),
    .x_std_sm_xcvrif_1ch_0__o_tx_rst_source_sel                         (o_tx_rst_source_sel),
    .x_std_sm_xcvrif_1ch_0__o_tx_xcvr_wordclk_sel                       (o_tx_xcvr_wordclk_sel),
    .x_std_sm_xcvrif_1ch_0__o_rx_xcvr_wordclk_sel                       (o_rx_xcvr_wordclk_sel),
    .x_std_sm_flux_ingress_0__o_sm_flux_ingress                         (o_sm_flux_ingress),
    .x_std_sm_flux_ingress_0__o_lavmm_rdata                             (o_lavmm_rdata),
    .x_std_sm_flux_ingress_0__o_lavmm_wdata                             (o_lavmm_wdata),
    .x_std_sm_xcvrif_1ch_0__o_ch_lavmm_xcvrif_rdata                     (o_ch_lavmm_xcvrif_rdata),
    .x_decoder_sm_flux_rx_demux_0__o_pcie_pcs                           (o_pcie_pcs),
    .x_std_sm_flux_ingress_0__o_lavmm_be                                (o_lavmm_be),
    .x_std_sm_xcvrif_1ch_0__o_rx_data                                   (o_rx_data),
    .x_std_sm_flux_ingress_0__o_ss_async_pldif                          (o_ss_async_pldif),
    .x_std_ipfluxtop_uxtop_wrap_0__uxwrap_bus_out                       (uxwrap_bus_out),
    .x_std_sm_flux_ingress_0__o_tx_data                                 (o_tx_data),
    .x_decoder_sm_flux_rx_rxword_clk_demux_0__o_eth_rxword_clk          (o_eth_rxword_clk),
    .x_decoder_sm_flux_rx_rxword_clk_demux_0__o_pcie_rxword_clk         (o_pcie_rxword_clk),
    .x_decoder_sm_flux_tx_txword_clk_demux_0__o_eth_txword_clk          (o_eth_txword_clk),
    .x_decoder_sm_flux_tx_txword_clk_demux_0__o_pcie_txword_clk         (o_pcie_txword_clk),
    .x_mux_sm_xcvrif_rx_ch_clk_mux_0__o_eth_rx_ch_clk                   (o_eth_rx_ch_clk),
    .x_mux_sm_xcvrif_tx_ch_clk_mux_0__o_eth_tx_ch_clk                   (o_eth_tx_ch_clk),
    .x_std_ipfluxtop_uxtop_wrap_0__ioack_cdrdiv_left_ux_bidir_out       (ioack_cdrdiv_left_ux_bidir_out),
    .x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv1_left_ux_bidir_out    (ioack_synthdiv1_left_ux_bidir_out),
    .x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv2_left_ux_bidir_out    (ioack_synthdiv2_left_ux_bidir_out),
    .x_std_ipfluxtop_uxtop_wrap_0__oflux_xoa_tx_n_l0_ux                 (oflux_xoa_tx_n_l0_ux),
    .x_std_ipfluxtop_uxtop_wrap_0__oflux_xoa_tx_p_l0_ux                 (oflux_xoa_tx_p_l0_ux),
    .x_std_sm_flux_ingress_0__o_dat_pcs_measlatrndtripbit               (o_dat_pcs_measlatrndtripbit),
    .x_std_sm_flux_ingress_0__o_ft_rx_async_pulse_ch                    (o_ft_rx_async_pulse_ch),
    .x_std_sm_flux_ingress_0__o_ft_rx_sclk_sync_ch                      (o_ft_rx_sclk_sync_ch),
    .x_std_sm_flux_ingress_0__o_ft_tx_async_pulse_ch                    (o_ft_tx_async_pulse_ch),
    .x_std_sm_flux_ingress_0__o_ft_tx_sclk_sync_ch                      (o_ft_tx_sclk_sync_ch),
    .x_std_sm_flux_ingress_0__o_ick_pcs_txword                          (o_ick_pcs_txword),
    .x_std_sm_flux_ingress_0__o_ick_sclk_rx                             (o_ick_sclk_rx),
    .x_std_sm_flux_ingress_0__o_ick_sclk_tx                             (o_ick_sclk_tx),
    .x_std_sm_flux_ingress_0__o_lavmm_clk                               (o_lavmm_clk),
    .x_std_sm_flux_ingress_0__o_lavmm_rdata_valid                       (o_lavmm_rdata_valid),
    .x_std_sm_flux_ingress_0__o_lavmm_read                              (o_lavmm_read),
    .x_std_sm_flux_ingress_0__o_lavmm_rstn                              (o_lavmm_rstn),
    .x_std_sm_flux_ingress_0__o_lavmm_waitreq                           (o_lavmm_waitreq),
    .x_std_sm_flux_ingress_0__o_lavmm_write                             (o_lavmm_write),
    .x_std_sm_flux_ingress_0__o_ock_pcs_cdrfbclk                        (o_ock_pcs_cdrfbclk),
    .x_std_sm_flux_ingress_0__o_ock_pcs_ref                             (o_ock_pcs_ref),
    .x_std_sm_flux_ingress_0__o_ock_pcs_txword                          (o_ock_pcs_txword),
    .x_std_sm_flux_ingress_0__o_octl_pcs_txstatus_a                     (o_octl_pcs_txstatus_a),
    .x_std_sm_flux_ingress_0__o_pcs_rxpostdiv                           (o_pcs_rxpostdiv),
    .x_std_sm_flux_ingress_0__o_pcs_rxword                              (o_pcs_rxword),
    .x_std_sm_flux_ingress_0__o_rst_flux0_cpi_cmn_busy                  (o_rst_flux0_cpi_cmn_busy),
    .x_std_sm_flux_ingress_0__o_rst_oflux_rx_srds_rdy                   (o_rst_oflux_rx_srds_rdy),
    .x_std_sm_flux_ingress_0__o_rst_ux_all_synthlockstatus              (o_rst_ux_all_synthlockstatus),
    .x_std_sm_flux_ingress_0__o_rst_ux_rx_pma_rst_n                     (o_rst_ux_rx_pma_rst_n),
    .x_std_sm_flux_ingress_0__o_rst_ux_rxcdrlockstatus                  (o_rst_ux_rxcdrlockstatus),
    .x_std_sm_flux_ingress_0__o_rst_ux_tx_pma_rst_n                     (o_rst_ux_tx_pma_rst_n),
    .x_std_sm_flux_ingress_0__o_rxcdrlock2dataa                         (o_rxcdrlock2dataa),
    .x_std_sm_flux_ingress_0__o_rxeq_donea                              (o_rxeq_donea),            //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__o_rxmargin_nacka                          (o_rxmargin_nacka),        //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__o_rxmargin_statusa                        (o_rxmargin_statusa),      //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__o_rxsignaldetect_lfpsa                    (o_rxsignaldetect_lfpsa),  //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__o_rxsignaldetecta                         (o_rxsignaldetecta),       //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__o_rxstatusa                               (o_rxstatusa),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__o_sclk_return_sel_rx                      (o_sclk_return_sel_rx),
    .x_std_sm_flux_ingress_0__o_sclk_return_sel_tx                      (o_sclk_return_sel_tx),
    .x_std_sm_flux_ingress_0__o_synthlcfast_postdiv                     (o_synthlcfast_postdiv),   //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__o_synthlcmed_postdiv                      (o_synthlcmed_postdiv),    //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__o_synthlcslow_postdiv                     (o_synthlcslow_postdiv),   //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__o_tx_dl_ch_bit                            (o_tx_dl_ch_bit),
    .x_std_sm_flux_ingress_0__o_txdetectrx_acka                         (o_txdetectrx_acka),       //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__o_txdetectrx_statct                       (o_txdetectrx_statct),     //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__o_txstatusa                               (o_txstatusa),             //PPCS //KAHUAT_EDIT
    .x_std_sm_flux_ingress_0__o_ux_txlc_clk                             (o_ux_txlc_clk),
    .x_std_sm_xcvrif_1ch_0__o_ch_eth_xcvrif_rx_direct                   (o_ch_eth_xcvrif_rx_direct),
    .x_std_sm_xcvrif_1ch_0__o_ch_lavmm_xcvrif_rdata_valid               (o_ch_lavmm_xcvrif_rdata_valid),
    .x_std_sm_xcvrif_1ch_0__o_ch_lavmm_xcvrif_waitreq                   (o_ch_lavmm_xcvrif_waitreq),
    .x_std_sm_xcvrif_1ch_0__o_ch_xcvrif_rx_fifo_rd_en                   (o_ch_xcvrif_rx_fifo_rd_en),
    .x_std_sm_xcvrif_1ch_0__o_ch_xcvrif_tx_fifo_rd_en                   (o_ch_xcvrif_tx_fifo_rd_en),
    .x_std_sm_xcvrif_1ch_0__o_pma_rx_sf                                 (o_pma_rx_sf),
    .x_std_sm_xcvrif_1ch_0__o_rx_latency_pulse                          (o_rx_latency_pulse),
    .x_std_sm_xcvrif_1ch_0__o_tx_latency_pulse                          (o_tx_latency_pulse),
    .x_std_sm_flux_ingress_0__i_quartus_flux_s_to_ingress               (i_quartus_flux_s_to_ingress),  //AG: R24 Integration
    .x_std_sm_xcvrif_1ch_0__o_tx_rst_rd_sync_rst_n                      (o_tx_rst_rd_sync_rst_n),       //Added in 1p0
    .x_std_sm_xcvrif_1ch_0__o_tx_rst_wr_sync_rst_n                      (o_tx_rst_wr_sync_rst_n)
);

    tennm_sm_cnoc_clk x_std_sm_cnoc_clk (
        .o_cnoc_clk(dpma_refclk)
    );
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "gpr4+lyWyppc7jIlltsQFtIlGyCoLf6iAew3iyvRntbcFY4053zn6zLu18GRHF3s0vDqHwBJh4GlXrShHOP9oSa3vukKq+W2/qDS2QS657eX5jciP01Ckf5fs+ILhvABoQ7+PsKkxxirY3Gm4vubojKPy8MexhFJYRbniDCEUjPjKbhVlKzclKLG0V2YikqOCYwqbI8k4sdYe9msW6JT0Di2pweaKdPsGwhkZzJFhemvuMZh1vAfD6pjdx1rKMJazKSRi0n3Cvz1PGH42i47paEkd3mhP7luyNz11NV78xbdCqvfOQ2zyFgXZacDtAilEC+ze6VyvaeOpexfvcwqwGeJRt9v0+8zsVQMleMldG18DtCapQcj4/aJN/02JxI/SKdNpVv985XPuuiRnyvNcuux/I/YabarEzQMeDV4QjqioqxdriJy5wbgamRYX1PNtdnWmE0Q7TdcSvo2+76OjgIq+6Necrzr/yY5bo1Hbpx6ryO8lQSPW6R4FGHqnvvtk0gi1Zih8MC5sZ/p126Pcb+MqqFeqCCGT/vrXojBpKTyhi8aSn1Nqs6ZNSarOFqtKz91SQMXQ1LlEDE5GuD1WcRcdwC/U/5rb8jR/t9VDkGgytT0AX16V+Uv1Nby7LItfZjdUZz9rSC0evcYDrgcdzMgLN4ftXR32CspCvDMd73wiFg8w7WdG1dP48CGV8SIgX3wtwBCuZJ0JL/dM3w/FHQBmQBvd3JHIlTeNsNCQrpwWPx9pCJ0DENnl6hWTfdFX+io/+e+Ge4nMKWzhlXKN7z/huH20wPhoGIhnJxfOnWLUbCgg2pto7WLow8JdbNproTJ/IeAHASrvtoghPvmnxLcLIrxtwP1wddmQGWMATR5UmTMbwIexD9yRUUuJDTIQP4x3uJTIN10K+hmCFBUD6cQMQjZWC+KDvTQo1alBpBgye+yXxXcrA/xLmzTd7LIKd9zYBbJBm7hPXTWlT+KG3fsoDNJmi+fnQJ8yNWalcMxDJOPERHgbVaxbD2YSXzl"
`endif