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module shared_hal_coreip 
  #(
    //fec_hal_shared parameters
    parameter ch0_duplex_mode_atom                      = "CH0_DUPLEX_MODE_DUPLEX"   ,
    parameter ch0_fec_spec_atom                         = "CH0_FEC_SPEC_DISABLED"    ,
    parameter ch0_fracture_atom                         = "CH0_FRACTURE_F25G"        ,
    parameter ch0_dr_enabled_atom                       = "CH0_DR_ENABLED_DR_ENABLED",
    parameter ch0_sup_mode_atom                         = "CH0_SUP_MODE_USER_MODE"   ,
    parameter ch0_sim_mode_atom                         = "CH0_SIM_MODE_DISABLE"     ,
    parameter ch1_duplex_mode_atom                      = "CH1_DUPLEX_MODE_DUPLEX"   ,
    parameter ch1_fec_spec_atom                         = "CH1_FEC_SPEC_DISABLED"    ,
    parameter ch1_fracture_atom                         = "CH1_FRACTURE_F25G"        ,
    parameter ch1_dr_enabled_atom                       = "CH1_DR_ENABLED_DR_ENABLED",
    parameter ch1_sup_mode_atom                         = "CH1_SUP_MODE_USER_MODE"   ,
    parameter ch1_sim_mode_atom                         = "CH1_SIM_MODE_DISABLE"     ,
    parameter ch2_duplex_mode_atom                      = "CH2_DUPLEX_MODE_DUPLEX"   ,
    parameter ch2_fec_spec_atom                         = "CH2_FEC_SPEC_DISABLED"    ,
    parameter ch2_fracture_atom                         = "CH2_FRACTURE_F25G"        ,
    parameter ch2_dr_enabled_atom                       = "CH2_DR_ENABLED_DR_ENABLED",
    parameter ch2_sup_mode_atom                         = "CH2_SUP_MODE_USER_MODE"   ,
    parameter ch2_sim_mode_atom                         = "CH2_SIM_MODE_DISABLE"     ,
    parameter ch3_duplex_mode_atom                      = "CH3_DUPLEX_MODE_DUPLEX"   ,
    parameter ch3_fec_spec_atom                         = "CH3_FEC_SPEC_DISABLED"    ,
    parameter ch3_fracture_atom                         = "CH3_FRACTURE_F25G"        ,
    parameter ch3_dr_enabled_atom                       = "CH3_DR_ENABLED_DR_ENABLED",
    parameter ch3_sup_mode_atom                         = "CH3_SUP_MODE_USER_MODE"   ,
    parameter ch3_sim_mode_atom                         = "CH3_SIM_MODE_DISABLE"     ,
    parameter ch0_pcs_l_tx_en_atom                      = "FALSE"                    ,
    parameter ch0_pcs_l_rx_en_atom                      = "FALSE"                    ,
    parameter ch0_fec_loopback_mode_atom                = "CH0_LOOPBACK_MODE_DISABLE",
    parameter ch0_fec_dyn_tx_mux_atom                   = "CH0_DYN_TX_MUX_UNUSED"    ,
    parameter ch0_fec_error_atom                        = "FALSE"                    ,
    parameter ch0_fec_rx_en_atom                        = "FALSE"                    ,
    parameter ch0_fec_tx_en_atom                        = "FALSE"                    ,
    parameter ch0_fec_mode_atom                         = "CH0_FEC_MODE_DISABLED"    ,
    parameter ch1_pcs_l_tx_en_atom                      = "FALSE"                    ,
    parameter ch1_pcs_l_rx_en_atom                      = "FALSE"                    ,
    parameter ch1_fec_loopback_mode_atom                = "CH1_LOOPBACK_MODE_DISABLE",
    parameter ch1_fec_dyn_tx_mux_atom                   = "CH1_DYN_TX_MUX_UNUSED"    ,
    parameter ch1_fec_error_atom                        = "FALSE"                    ,
    parameter ch1_fec_rx_en_atom                        = "FALSE"                    ,
    parameter ch1_fec_tx_en_atom                        = "FALSE"                    ,
    parameter ch1_fec_mode_atom                         = "CH1_FEC_MODE_DISABLED"    ,
    parameter ch2_pcs_l_tx_en_atom                      = "FALSE"                    ,
    parameter ch2_pcs_l_rx_en_atom                      = "FALSE"                    ,
    parameter ch2_fec_loopback_mode_atom                = "CH2_LOOPBACK_MODE_DISABLE",
    parameter ch2_fec_dyn_tx_mux_atom                   = "CH2_DYN_TX_MUX_UNUSED"    ,
    parameter ch2_fec_error_atom                        = "FALSE"                    ,
    parameter ch2_fec_rx_en_atom                        = "FALSE"                    ,
    parameter ch2_fec_tx_en_atom                        = "FALSE"                    ,
    parameter ch2_fec_mode_atom                         = "CH2_FEC_MODE_DISABLED"    ,
    parameter ch3_pcs_l_tx_en_atom                      = "FALSE"                    ,
    parameter ch3_pcs_l_rx_en_atom                      = "FALSE"                    ,
    parameter ch3_fec_loopback_mode_atom                = "CH3_LOOPBACK_MODE_DISABLE",
    parameter ch3_fec_dyn_tx_mux_atom                   = "CH3_DYN_TX_MUX_UNUSED"    ,
    parameter ch3_fec_error_atom                        = "FALSE"                    ,
    parameter ch3_fec_rx_en_atom                        = "FALSE"                    ,
    parameter ch3_fec_tx_en_atom                        = "FALSE"                    ,
    parameter ch3_fec_mode_atom                         = "CH3_FEC_MODE_DISABLED"    ,  
    //phy_hal_shared parameters
    parameter ch0_xcvr_tx_preloaded_hardware_configs_atom   = "CH0_TX_PRELOADED_HARDWARE_CONFIGS_NONE"             ,   
    parameter ch0_xcvr_rx_preloaded_hardware_configs_atom   = "CH0_RX_PRELOADED_HARDWARE_CONFIGS_NONE"             ,   
    parameter ch0_lc_postdiv_sel_atom                       = "CH0_LC_POSTDIV_SEL_SYNTH_FAST"                      ,   
    parameter ch0_sequencer_reg_en_atom                     = "CH0_SEQUENCER_REG_EN_DISABLE"                       ,   
    parameter ch0_rst_mux_static_sel_atom                   = "CH0_RST_MUX_STATIC_SEL_UNUSED"                      ,
    parameter ch0_xcvr_tx_prbs_pattern_atom                 = "4'D1"                                               ,
    parameter ch0_xcvr_rx_prbs_pattern_atom                 = "4'D1"                                               ,
    parameter ch0_xcvr_tx_user_clk_only_mode_atom           = "CH0_TX_USER_CLK_ONLY_MODE_ENABLE"                   ,
    parameter ch0_xcvr_tx_width_atom                        = "CH0_TX_WIDTH_DISABLED"                              ,
    parameter ch0_xcvr_rx_width_atom                        = "CH0_RX_WIDTH_DISABLED"                              ,
    parameter ch0_phy_loopback_mode_atom                    = "CH0_LOOPBACK_MODE_DISABLED"                         ,
    parameter ch0_flux_mode_atom                            = "CH0_FLUX_MODE_DISABLED"                             ,
    parameter ch0_tx_sim_mode_atom                          = "CH0_TX_SIM_MODE_DISABLE"                            ,
    parameter ch0_rx_sim_mode_atom                          = "CH0_RX_SIM_MODE_DISABLE"                            ,
    parameter ch0_tx_dl_enable_atom                         = "CH0_TX_DL_ENABLE_DISABLE"                           , 
    parameter ch0_rx_dl_enable_atom                         = "CH0_RX_DL_ENABLE_DISABLE"                           , 
    parameter ch0_rx_fec_type_used_atom                     = "CH0_RX_FEC_TYPE_USED_NONE"                          , 
    parameter ch0_xcvr_rx_prbs_monitor_en_atom              = "CH0_RX_PRBS_MONITOR_EN_DISABLE"                     , 
    parameter ch0_tx_prbs_gen_en_atom                       = "CH0_TX_PRBS_GEN_EN_DISABLE"                         , 
    parameter ch0_rx_user1_clk_mux_dynamic_sel_atom         = "CH0_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch0_rx_user2_clk_mux_dynamic_sel_atom         = "CH0_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch0_tx_user1_clk_mux_dynamic_sel_atom         = "CH0_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch0_tx_user2_clk_mux_dynamic_sel_atom         = "CH0_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch0_xcvr_rx_protocol_hint_atom                = "CH0_RX_PROTOCOL_HINT_DISABLED"                      , 
    parameter ch0_pcie_mode_atom                            = "CH0_PCIE_MODE_DISABLED"                             , 
    parameter ch1_xcvr_tx_preloaded_hardware_configs_atom   = "CH1_TX_PRELOADED_HARDWARE_CONFIGS_NONE"             ,
    parameter ch1_xcvr_rx_preloaded_hardware_configs_atom   = "CH1_RX_PRELOADED_HARDWARE_CONFIGS_NONE"             ,
    parameter ch1_lc_postdiv_sel_atom                       = "CH1_LC_POSTDIV_SEL_SYNTH_FAST"                      ,
    parameter ch1_sequencer_reg_en_atom                     = "CH1_SEQUENCER_REG_EN_DISABLE"                       ,  
    parameter ch1_rst_mux_static_sel_atom                   = "CH1_RST_MUX_STATIC_SEL_UNUSED"                      ,  
    parameter ch1_xcvr_tx_prbs_pattern_atom                 = "4'D1"                                               ,
    parameter ch1_xcvr_rx_prbs_pattern_atom                 = "4'D1"                                               ,  
    parameter ch1_xcvr_tx_user_clk_only_mode_atom           = "CH1_TX_USER_CLK_ONLY_MODE_ENABLE"                   ,  
    parameter ch1_xcvr_tx_width_atom                        = "CH1_TX_WIDTH_DISABLED"                              ,
    parameter ch1_xcvr_rx_width_atom                        = "CH1_RX_WIDTH_DISABLED"                              , 
    parameter ch1_phy_loopback_mode_atom                    = "CH1_LOOPBACK_MODE_DISABLED"                         , 
    parameter ch1_flux_mode_atom                            = "CH1_FLUX_MODE_DISABLED"                             , 
    parameter ch1_tx_sim_mode_atom                          = "CH1_TX_SIM_MODE_DISABLE"                            , 
    parameter ch1_rx_sim_mode_atom                          = "CH1_RX_SIM_MODE_DISABLE"                            ,
    parameter ch1_tx_dl_enable_atom                         = "CH1_TX_DL_ENABLE_DISABLE"                           ,
    parameter ch1_rx_dl_enable_atom                         = "CH1_RX_DL_ENABLE_DISABLE"                           ,
    parameter ch1_rx_fec_type_used_atom                     = "CH1_RX_FEC_TYPE_USED_NONE"                          ,
    parameter ch1_xcvr_rx_prbs_monitor_en_atom              = "CH1_RX_PRBS_MONITOR_EN_DISABLE"                     , 
    parameter ch1_tx_prbs_gen_en_atom                       = "CH1_TX_PRBS_GEN_EN_DISABLE"                         , 
    parameter ch1_rx_user1_clk_mux_dynamic_sel_atom         = "CH1_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch1_rx_user2_clk_mux_dynamic_sel_atom         = "CH1_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch1_tx_user1_clk_mux_dynamic_sel_atom         = "CH1_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch1_tx_user2_clk_mux_dynamic_sel_atom         = "CH1_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch1_xcvr_rx_protocol_hint_atom                = "CH1_RX_PROTOCOL_HINT_DISABLED"                      , 
    parameter ch1_pcie_mode_atom                            = "CH1_PCIE_MODE_DISABLED"                             , 
    parameter ch2_xcvr_tx_preloaded_hardware_configs_atom   = "CH2_TX_PRELOADED_HARDWARE_CONFIGS_NONE"             ,
    parameter ch2_xcvr_rx_preloaded_hardware_configs_atom   = "CH2_RX_PRELOADED_HARDWARE_CONFIGS_NONE"             ,
    parameter ch2_lc_postdiv_sel_atom                       = "CH2_LC_POSTDIV_SEL_SYNTH_FAST"                      ,
    parameter ch2_sequencer_reg_en_atom                     = "CH2_SEQUENCER_REG_EN_DISABLE"                       ,
    parameter ch2_rst_mux_static_sel_atom                   = "CH2_RST_MUX_STATIC_SEL_UNUSED"                      , 
    parameter ch2_xcvr_tx_prbs_pattern_atom                 = "4'D1"                                               , 
    parameter ch2_xcvr_rx_prbs_pattern_atom                 = "4'D1"                                               , 
    parameter ch2_xcvr_tx_user_clk_only_mode_atom           = "CH2_TX_USER_CLK_ONLY_MODE_ENABLE"                   , 
    parameter ch2_xcvr_tx_width_atom                        = "CH2_TX_WIDTH_DISABLED"                              ,
    parameter ch2_xcvr_rx_width_atom                        = "CH2_RX_WIDTH_DISABLED"                              ,
    parameter ch2_phy_loopback_mode_atom                    = "CH2_LOOPBACK_MODE_DISABLED"                         ,
    parameter ch2_flux_mode_atom                            = "CH2_FLUX_MODE_DISABLED"                             ,
    parameter ch2_tx_sim_mode_atom                          = "CH2_TX_SIM_MODE_DISABLE"                            ,
    parameter ch2_rx_sim_mode_atom                          = "CH2_RX_SIM_MODE_DISABLE"                            ,
    parameter ch2_tx_dl_enable_atom                         = "CH2_TX_DL_ENABLE_DISABLE"                           ,
    parameter ch2_rx_dl_enable_atom                         = "CH2_RX_DL_ENABLE_DISABLE"                           ,
    parameter ch2_rx_fec_type_used_atom                     = "CH2_RX_FEC_TYPE_USED_NONE"                          ,
    parameter ch2_xcvr_rx_prbs_monitor_en_atom              = "CH2_RX_PRBS_MONITOR_EN_DISABLE"                     , 
    parameter ch2_tx_prbs_gen_en_atom                       = "CH2_TX_PRBS_GEN_EN_DISABLE"                         , 
    parameter ch2_rx_user1_clk_mux_dynamic_sel_atom         = "CH2_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch2_rx_user2_clk_mux_dynamic_sel_atom         = "CH2_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch2_tx_user1_clk_mux_dynamic_sel_atom         = "CH2_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch2_tx_user2_clk_mux_dynamic_sel_atom         = "CH2_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch2_xcvr_rx_protocol_hint_atom                = "CH2_RX_PROTOCOL_HINT_DISABLED"                      , 
    parameter ch2_pcie_mode_atom                            = "CH2_PCIE_MODE_DISABLED"                             , 
    parameter ch3_xcvr_tx_preloaded_hardware_configs_atom   = "CH3_TX_PRELOADED_HARDWARE_CONFIGS_NONE"             ,
    parameter ch3_xcvr_rx_preloaded_hardware_configs_atom   = "CH3_RX_PRELOADED_HARDWARE_CONFIGS_NONE"             ,
    parameter ch3_lc_postdiv_sel_atom                       = "CH3_LC_POSTDIV_SEL_SYNTH_FAST"                      ,
    parameter ch3_sequencer_reg_en_atom                     = "CH3_SEQUENCER_REG_EN_DISABLE"                       ,
    parameter ch3_rst_mux_static_sel_atom                   = "CH3_RST_MUX_STATIC_SEL_UNUSED"                      ,
    parameter ch3_xcvr_tx_prbs_pattern_atom                 = "4'D1"                                               ,
    parameter ch3_xcvr_rx_prbs_pattern_atom                 = "4'D1"                                               ,
    parameter ch3_xcvr_tx_user_clk_only_mode_atom           = "CH3_TX_USER_CLK_ONLY_MODE_ENABLE"                   ,
    parameter ch3_xcvr_tx_width_atom                        = "CH3_TX_WIDTH_DISABLED"                              ,
    parameter ch3_xcvr_rx_width_atom                        = "CH3_RX_WIDTH_DISABLED"                              ,
    parameter ch3_phy_loopback_mode_atom                    = "CH3_LOOPBACK_MODE_DISABLED"                         ,
    parameter ch3_flux_mode_atom                            = "CH3_FLUX_MODE_DISABLED"                             ,
    parameter ch3_tx_sim_mode_atom                          = "CH3_TX_SIM_MODE_DISABLE"                            ,
    parameter ch3_rx_sim_mode_atom                          = "CH3_RX_SIM_MODE_DISABLE"                            ,
    parameter ch3_tx_dl_enable_atom                         = "CH3_TX_DL_ENABLE_DISABLE"                           ,
    parameter ch3_rx_dl_enable_atom                         = "CH3_RX_DL_ENABLE_DISABLE"                           ,
    parameter ch3_rx_fec_type_used_atom                     = "CH3_RX_FEC_TYPE_USED_NONE"                          ,
    parameter ch3_xcvr_rx_prbs_monitor_en_atom              = "CH3_RX_PRBS_MONITOR_EN_DISABLE"                     , 
    parameter ch3_tx_prbs_gen_en_atom                       = "CH3_TX_PRBS_GEN_EN_DISABLE"                         , 
    parameter ch3_rx_user1_clk_mux_dynamic_sel_atom         = "CH3_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch3_rx_user2_clk_mux_dynamic_sel_atom         = "CH3_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch3_tx_user1_clk_mux_dynamic_sel_atom         = "CH3_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch3_tx_user2_clk_mux_dynamic_sel_atom         = "CH3_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED"            , 
    parameter ch3_xcvr_rx_protocol_hint_atom                = "CH3_RX_PROTOCOL_HINT_DISABLED"                      , 
    parameter ch3_pcie_mode_atom                            = "CH3_PCIE_MODE_DISABLED"                             ,
    //Added 0p8 Allignment
    parameter ch0_tx_pll_l_counter_atom                     = 0                                                    ,
    parameter ch0_cdr_l_counter_atom                        = 0                                                    ,
    parameter ch0_tx_pll_refclk_select_atom                 = "CH0_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0"            ,
    parameter ch0_cdr_refclk_select_atom                    = "CH0_CDR_REFCLK_SELECT_GLOBAL_REFCLK0"               ,
    parameter ch1_tx_pll_l_counter_atom                     = 0                                                    ,
    parameter ch1_cdr_l_counter_atom                        = 0                                                    ,
    parameter ch1_tx_pll_refclk_select_atom                 = "CH1_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0"            ,
    parameter ch1_cdr_refclk_select_atom                    = "CH1_CDR_REFCLK_SELECT_GLOBAL_REFCLK0"               ,
    parameter ch2_tx_pll_l_counter_atom                     = 0                                                    ,
    parameter ch2_cdr_l_counter_atom                        = 0                                                    ,
    parameter ch2_tx_pll_refclk_select_atom                 = "CH2_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0"            ,
    parameter ch2_cdr_refclk_select_atom                    = "CH2_CDR_REFCLK_SELECT_GLOBAL_REFCLK0"               ,
    parameter ch3_tx_pll_l_counter_atom                     = 0                                                    ,
    parameter ch3_cdr_l_counter_atom                        = 0                                                    ,
    parameter ch3_tx_pll_refclk_select_atom                 = "CH3_TX_PLL_REFCLK_SELECT_GLOBAL_REFCLK0"            ,
    parameter ch3_cdr_refclk_select_atom                    = "CH3_CDR_REFCLK_SELECT_GLOBAL_REFCLK0"               ,
    parameter ch0_rx_dl_rx_lat_bit_for_async_atom           = 0                                                    ,
    parameter ch0_rx_dl_rxbit_cntr_pma_atom                 = "CH0_RX_DL_RXBIT_CNTR_PMA_DISABLE"                   ,
    parameter ch0_rx_dl_rxbit_rollover_atom                 = 0                                                    ,
    parameter ch1_rx_dl_rx_lat_bit_for_async_atom           = 0                                                    ,
    parameter ch1_rx_dl_rxbit_cntr_pma_atom                 = "CH1_RX_DL_RXBIT_CNTR_PMA_DISABLE"                   ,
    parameter ch1_rx_dl_rxbit_rollover_atom                 = 0                                                    ,
    parameter ch2_rx_dl_rx_lat_bit_for_async_atom           = 0                                                    ,
    parameter ch2_rx_dl_rxbit_cntr_pma_atom                 = "CH2_RX_DL_RXBIT_CNTR_PMA_DISABLE"                   ,
    parameter ch2_rx_dl_rxbit_rollover_atom                 = 0                                                    ,
    parameter ch3_rx_dl_rx_lat_bit_for_async_atom           = 0                                                    ,
    parameter ch3_rx_dl_rxbit_cntr_pma_atom                 = "CH3_RX_DL_RXBIT_CNTR_PMA_DISABLE"                   ,
    parameter ch3_rx_dl_rxbit_rollover_atom                 = 0                                                    ,
    parameter ch0_tx_bonding_category_atom                  = "CH0_TX_BONDING_CATEGORY_UNUSED"                     ,
    parameter ch1_tx_bonding_category_atom                  = "CH1_TX_BONDING_CATEGORY_UNUSED"                     ,
    parameter ch2_tx_bonding_category_atom                  = "CH2_TX_BONDING_CATEGORY_UNUSED"                     ,
    parameter ch3_tx_bonding_category_atom                  = "CH3_TX_BONDING_CATEGORY_UNUSED"                     ,
    parameter ch0_tx_bond_size_atom                         = "CH0_TX_BOND_SIZE_UNUSED"                            ,
    parameter ch1_tx_bond_size_atom                         = "CH1_TX_BOND_SIZE_UNUSED"                            ,
    parameter ch2_tx_bond_size_atom                         = "CH2_TX_BOND_SIZE_UNUSED"                            ,
    parameter ch3_tx_bond_size_atom                         = "CH3_TX_BOND_SIZE_UNUSED"                            ,
    parameter ch0_rx_invert_pin_atom                        = "CH0_RX_INVERT_PIN_DISABLE"                          ,
    parameter ch1_rx_invert_pin_atom                        = "CH1_RX_INVERT_PIN_DISABLE"                          ,
    parameter ch2_rx_invert_pin_atom                        = "CH2_RX_INVERT_PIN_DISABLE"                          ,
    parameter ch3_rx_invert_pin_atom                        = "CH3_RX_INVERT_PIN_DISABLE"                          ,
    parameter ch0_tx_invert_pin_atom                        = "CH0_TX_INVERT_PIN_DISABLE"                          ,
    parameter ch1_tx_invert_pin_atom                        = "CH1_TX_INVERT_PIN_DISABLE"                          ,
    parameter ch2_tx_invert_pin_atom                        = "CH2_TX_INVERT_PIN_DISABLE"                          ,
    parameter ch3_tx_invert_pin_atom                        = "CH3_TX_INVERT_PIN_DISABLE"                          ,
    parameter ch0_vsr_mode_atom                             = "CH0_VSR_MODE_DISABLED"                              ,
    parameter ch1_vsr_mode_atom                             = "CH1_VSR_MODE_DISABLED"                              ,
    parameter ch2_vsr_mode_atom                             = "CH2_VSR_MODE_DISABLED"                              ,
    parameter ch3_vsr_mode_atom                             = "CH3_VSR_MODE_DISABLED"                              ,

    parameter ch0_clkrx_refclk_cssm_fw_control_atom                = "CH0_CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE"                ,
    parameter ch1_clkrx_refclk_cssm_fw_control_atom                = "CH1_CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE"                ,
    parameter ch2_clkrx_refclk_cssm_fw_control_atom                = "CH2_CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE"                ,
    parameter ch3_clkrx_refclk_cssm_fw_control_atom                = "CH3_CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE"                ,
    parameter ch0_clkrx_refclk_sector_specifies_refclk_ready_atom  = "CH0_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE"  ,
    parameter ch1_clkrx_refclk_sector_specifies_refclk_ready_atom  = "CH1_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE"  ,
    parameter ch2_clkrx_refclk_sector_specifies_refclk_ready_atom  = "CH2_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE"  ,
    parameter ch3_clkrx_refclk_sector_specifies_refclk_ready_atom  = "CH3_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE"  ,
    parameter ch0_local_refclk_cssm_fw_control_atom                = "CH0_LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE"                   ,
    parameter ch1_local_refclk_cssm_fw_control_atom                = "CH1_LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE"                   ,
    parameter ch2_local_refclk_cssm_fw_control_atom                = "CH2_LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE"                   ,
    parameter ch3_local_refclk_cssm_fw_control_atom                = "CH3_LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE"                   ,
    parameter ch0_local_refclk_sector_specifies_refclk_ready_atom  = "CH0_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE"  ,
    parameter ch1_local_refclk_sector_specifies_refclk_ready_atom  = "CH1_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE"  ,
    parameter ch2_local_refclk_sector_specifies_refclk_ready_atom  = "CH2_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE"  ,
    parameter ch3_local_refclk_sector_specifies_refclk_ready_atom  = "CH3_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE"  ,

    parameter num_of_lanes                                  = 1
)
(
    //fec_hal_shared interfaces
    input   [42:0]  i_fec_wrap_ch0_tx_mux_data ,
    input   [42:0]  i_fec_wrap_ch1_tx_mux_data ,
    input   [42:0]  i_fec_wrap_ch2_tx_mux_data ,
    input   [42:0]  i_fec_wrap_ch3_tx_mux_data ,
    output  [42:0]  o_fec_ch0_rx_data          ,
    output  [42:0]  o_fec_ch1_rx_data          ,
    output  [42:0]  o_fec_ch2_rx_data          ,
    output  [42:0]  o_fec_ch3_rx_data          ,
    input   [42:0]  i_xcvr_ch0_rx_data         ,
    input   [42:0]  i_xcvr_ch1_rx_data         ,
    input   [42:0]  i_xcvr_ch2_rx_data         ,
    input   [42:0]  i_xcvr_ch3_rx_data         ,
    output  [42:0]  o_xcvr_ch0_tx_data         ,
    output  [42:0]  o_xcvr_ch1_tx_data         ,
    output  [42:0]  o_xcvr_ch2_tx_data         ,
    output  [42:0]  o_xcvr_ch3_tx_data         ,
    input           i_fec_clk                  ,
    output          o_fec_tx_data_mux_sel_ch0  ,
    output          o_fec_tx_data_mux_sel_ch1  ,
    output          o_fec_tx_data_mux_sel_ch2  ,
    output          o_fec_tx_data_mux_sel_ch3  ,
    output  [31:0]  o_ch0_lavmm_fec_rdata      ,
    output          o_ch0_lavmm_fec_rdata_valid,
    output          o_ch0_lavmm_fec_waitreq    ,
    input   [19:0]  i_ch0_lavmm_fec_addr       ,
    input   [3:0]   i_ch0_lavmm_fec_be         ,
    input           i_ch0_lavmm_fec_clk        ,
    input           i_ch0_lavmm_fec_read       ,
    input           i_ch0_lavmm_fec_rstn       ,
    input   [31:0]  i_ch0_lavmm_fec_wdata      ,
    input           i_ch0_lavmm_fec_write      ,
    output  [31:0]  o_ch1_lavmm_fec_rdata      ,
    output          o_ch1_lavmm_fec_rdata_valid,
    output          o_ch1_lavmm_fec_waitreq    ,
    input   [19:0]  i_ch1_lavmm_fec_addr       ,
    input   [3:0]   i_ch1_lavmm_fec_be         ,
    input           i_ch1_lavmm_fec_clk        ,
    input           i_ch1_lavmm_fec_read       ,
    input           i_ch1_lavmm_fec_rstn       ,
    input   [31:0]  i_ch1_lavmm_fec_wdata      ,
    input           i_ch1_lavmm_fec_write      ,
    output  [31:0]  o_ch2_lavmm_fec_rdata      ,
    output          o_ch2_lavmm_fec_rdata_valid,
    output          o_ch2_lavmm_fec_waitreq    ,
    input   [19:0]  i_ch2_lavmm_fec_addr       ,
    input   [3:0]   i_ch2_lavmm_fec_be         ,
    input           i_ch2_lavmm_fec_clk        ,
    input           i_ch2_lavmm_fec_read       ,
    input           i_ch2_lavmm_fec_rstn       ,
    input   [31:0]  i_ch2_lavmm_fec_wdata      ,
    input           i_ch2_lavmm_fec_write      ,
    output  [31:0]  o_ch3_lavmm_fec_rdata      ,
    output          o_ch3_lavmm_fec_rdata_valid,
    output          o_ch3_lavmm_fec_waitreq    ,
    input   [19:0]  i_ch3_lavmm_fec_addr       ,
    input   [3:0]   i_ch3_lavmm_fec_be         ,
    input           i_ch3_lavmm_fec_clk        ,
    input           i_ch3_lavmm_fec_read       ,
    input           i_ch3_lavmm_fec_rstn       ,
    input   [31:0]  i_ch3_lavmm_fec_wdata      ,
    input           i_ch3_lavmm_fec_write      ,
    input   [6:0]   i_ch0_eth_fec_tx_async     ,
    input           i_ch0_eth_fec_tx_direct    ,
    output  [11:0]  o_ch0_eth_fec_rx_async     ,
    output          o_ch0_eth_fec_rx_direct    ,
    input   [6:0]   i_ch1_eth_fec_tx_async     ,
    input           i_ch1_eth_fec_tx_direct    ,
    output  [11:0]  o_ch1_eth_fec_rx_async     ,
    output          o_ch1_eth_fec_rx_direct    ,
    input   [6:0]   i_ch2_eth_fec_tx_async     ,
    input           i_ch2_eth_fec_tx_direct    ,
    output  [11:0]  o_ch2_eth_fec_rx_async     ,
    output          o_ch2_eth_fec_rx_direct    ,
    input   [6:0]   i_ch3_eth_fec_tx_async     ,
    input           i_ch3_eth_fec_tx_direct    ,
    output  [11:0]  o_ch3_eth_fec_rx_async     ,
    output          o_ch3_eth_fec_rx_direct    ,
    input           i_ch0_rstfec_fec_csr_ret   ,
    output          o_ch0_fec_rx_rdy_n         ,
    input           i_ch0_rstfec_fec_rx_rst_n  ,
    input           i_ch0_rstfec_fec_tx_rst_n  ,
    input           i_ch0_rstfec_rx_fec_sfrz_n ,
    input           i_ch0_rstfec_tx_fec_sfrz_n ,
    input           i_ch1_rstfec_fec_csr_ret   ,
    output          o_ch1_fec_rx_rdy_n         ,
    input           i_ch1_rstfec_fec_rx_rst_n  ,
    input           i_ch1_rstfec_fec_tx_rst_n  ,
    input           i_ch1_rstfec_rx_fec_sfrz_n ,
    input           i_ch1_rstfec_tx_fec_sfrz_n ,
    input           i_ch2_rstfec_fec_csr_ret   ,
    output          o_ch2_fec_rx_rdy_n         ,
    input           i_ch2_rstfec_fec_rx_rst_n  ,
    input           i_ch2_rstfec_fec_tx_rst_n  ,
    input           i_ch2_rstfec_rx_fec_sfrz_n ,
    input           i_ch2_rstfec_tx_fec_sfrz_n ,
    input           i_ch3_rstfec_fec_csr_ret   ,
    output          o_ch3_fec_rx_rdy_n         ,
    input           i_ch3_rstfec_fec_rx_rst_n  ,
    input           i_ch3_rstfec_fec_tx_rst_n  ,
    input           i_ch3_rstfec_rx_fec_sfrz_n ,
    input           i_ch3_rstfec_tx_fec_sfrz_n ,
    input           i_pma_rx_sf_ch0            ,
    input           i_pma_rx_sf_ch1            ,
    input           i_pma_rx_sf_ch2            ,
    input           i_pma_rx_sf_ch3             ,
    //phy_hal_shared interfaces 
    input [19:0]    i_ch0_lavmm_addr,                       //sm_ux_toolbox interfaces to phy_hal
    input [3:0]     i_ch0_lavmm_be,
    input           i_ch0_lavmm_clk,
    input           i_ch0_lavmm_read,
    input           i_ch0_lavmm_rstn,
    input [31:0]    i_ch0_lavmm_wdata,
    input           i_ch0_lavmm_write,
    input [19:0]    i_ch1_lavmm_addr,
    input [3:0]     i_ch1_lavmm_be,
    input           i_ch1_lavmm_clk,
    input           i_ch1_lavmm_read,
    input           i_ch1_lavmm_rstn,
    input [31:0]    i_ch1_lavmm_wdata,
    input           i_ch1_lavmm_write,
    input [19:0]    i_ch2_lavmm_addr,
    input [3:0]     i_ch2_lavmm_be,
    input           i_ch2_lavmm_clk,
    input           i_ch2_lavmm_read,
    input           i_ch2_lavmm_rstn,
    input [31:0]    i_ch2_lavmm_wdata,
    input           i_ch2_lavmm_write,
    input [19:0]    i_ch3_lavmm_addr,
    input [3:0]     i_ch3_lavmm_be,
    input           i_ch3_lavmm_clk,
    input           i_ch3_lavmm_read,
    input           i_ch3_lavmm_rstn,
    input [31:0]    i_ch3_lavmm_wdata,
    input           i_ch3_lavmm_write,
    output [31:0]   o_ch0_lavmm_rdata,
    output          o_ch0_lavmm_rdata_valid,
    output          o_ch0_lavmm_waitreq,
    output [31:0]   o_ch1_lavmm_rdata,
    output          o_ch1_lavmm_rdata_valid,
    output          o_ch1_lavmm_waitreq,
    output [31:0]   o_ch2_lavmm_rdata,
    output          o_ch2_lavmm_rdata_valid,
    output          o_ch2_lavmm_waitreq,
    output [31:0]   o_ch3_lavmm_rdata,
    output          o_ch3_lavmm_rdata_valid,
    output          o_ch3_lavmm_waitreq,
    input           i_dat_pcs_measlatrndtripbit_ch0, 
    input           i_dat_pcs_measlatrndtripbit_ch1, 
    input           i_dat_pcs_measlatrndtripbit_ch2, 
    input           i_dat_pcs_measlatrndtripbit_ch3, 
    input           i_ft_rx_sclk_sync_ch0,
    input           i_ft_rx_sclk_sync_ch1,
    input           i_ft_rx_sclk_sync_ch2,
    input           i_ft_rx_sclk_sync_ch3,
    input           i_ft_tx_sclk_sync_ch0,
    input           i_ft_tx_sclk_sync_ch1,
    input           i_ft_tx_sclk_sync_ch2,
    input           i_ft_tx_sclk_sync_ch3,
    input           i_rst_ux_rx_pma_rst_n_ch0,
    input           i_rst_ux_rx_pma_rst_n_ch1,
    input           i_rst_ux_rx_pma_rst_n_ch2,
    input           i_rst_ux_rx_pma_rst_n_ch3,
    input           i_rst_ux_tx_pma_rst_n_ch0,
    input           i_rst_ux_tx_pma_rst_n_ch1,
    input           i_rst_ux_tx_pma_rst_n_ch2,
    input           i_rst_ux_tx_pma_rst_n_ch3,
/*     input           i_pcs_ick_txword_ch0,
    input           i_pcs_ick_txword_ch1,
    input           i_pcs_ick_txword_ch2,
    input           i_pcs_ick_txword_ch3, */
    input           i_tx_dl_ch0_bit,
    input           i_tx_dl_ch1_bit,
    input           i_tx_dl_ch2_bit,
    input           i_tx_dl_ch3_bit,
    output          o_dat_pcs_measlatbit_ch0,
    output          o_dat_pcs_measlatbit_ch1,
    output          o_dat_pcs_measlatbit_ch2,
    output          o_dat_pcs_measlatbit_ch3,
    output          o_ft_rx_async_pulse_ch0,
    output          o_ft_rx_async_pulse_ch1,
    output          o_ft_rx_async_pulse_ch2,
    output          o_ft_rx_async_pulse_ch3,
    output          o_ft_tx_async_pulse_ch0,
    output          o_ft_tx_async_pulse_ch1,
    output          o_ft_tx_async_pulse_ch2,
    output          o_ft_tx_async_pulse_ch3,  
    output          o_rx_dl_ch0_bit,
    output          o_rx_dl_ch1_bit,
    output          o_rx_dl_ch2_bit,
    output          o_rx_dl_ch3_bit,
    output [1:0]    o_ux0_rxuser1_sel,
    output [1:0]    o_ux0_rxuser2_sel,
    output [1:0]    o_ux0_txuser1_sel,
    output [1:0]    o_ux0_txuser2_sel,
    output [1:0]    o_ux1_rxuser1_sel,
    output [1:0]    o_ux1_rxuser2_sel,
    output [1:0]    o_ux1_txuser1_sel,
    output [1:0]    o_ux1_txuser2_sel,
    output [1:0]    o_ux2_rxuser1_sel,
    output [1:0]    o_ux2_rxuser2_sel,
    output [1:0]    o_ux2_txuser1_sel,
    output [1:0]    o_ux2_txuser2_sel,
    output [1:0]    o_ux3_rxuser1_sel,
    output [1:0]    o_ux3_rxuser2_sel,
    output [1:0]    o_ux3_txuser1_sel,
    output [1:0]    o_ux3_txuser2_sel,
    input           i_octl_pcs_txstatus_ch0_a,
    input           i_octl_pcs_txstatus_ch1_a,
    input           i_octl_pcs_txstatus_ch2_a,
    input           i_octl_pcs_txstatus_ch3_a,
    output          o_ictl_pcs_txenable_ch0_a,
    output          o_ictl_pcs_txenable_ch1_a,
    output          o_ictl_pcs_txenable_ch2_a,
    output          o_ictl_pcs_txenable_ch3_a,
    input           i_ick_sclk_rx_ch0,
    input           i_ick_sclk_rx_ch1,
    input           i_ick_sclk_rx_ch2,
    input           i_ick_sclk_rx_ch3,
    input           i_sclk_return_sel_rx_ch0,
    input           i_sclk_return_sel_rx_ch1,
    input           i_sclk_return_sel_rx_ch2,
    input           i_sclk_return_sel_rx_ch3,
    input           i_sclk_return_sel_tx_ch0,
    input           i_sclk_return_sel_tx_ch1,
    input           i_sclk_return_sel_tx_ch2,
    input           i_sclk_return_sel_tx_ch3,
    output [124:0]  o_sync_cfg_data_ch0,
    output [124:0]  o_sync_cfg_data_ch1,
    output [124:0]  o_sync_cfg_data_ch2,
    output [124:0]  o_sync_cfg_data_ch3,
    output [4:0]    o_sync_common_control_ch0,
    output [4:0]    o_sync_common_control_ch1,
    output [4:0]    o_sync_common_control_ch2,
    output [4:0]    o_sync_common_control_ch3,
    output [249:0]  o_sync_interface_control_ch0,
    output [249:0]  o_sync_interface_control_ch1,
    output [249:0]  o_sync_interface_control_ch2,
    output [249:0]  o_sync_interface_control_ch3,
    input           iflux_ext_cpu_fast_clk ,                //ipfluxtop_flux_core_shim_wrap interfaces to phy_hal 
    input  [79:0]   iflux_pcs_txword_lane0 , 
    input  [79:0]   iflux_pcs_txword_lane1 , 
    input  [79:0]   iflux_pcs_txword_lane2 , 
    input  [79:0]   iflux_pcs_txword_lane3 , 
    output [79:0]   oflux_pcs_rxword_lane0 , 
    output [79:0]   oflux_pcs_rxword_lane1 , 
    output [79:0]   oflux_pcs_rxword_lane2 , 
    output [79:0]   oflux_pcs_rxword_lane3 , 
    input  [319:0]  iflux_ingress_direct_lane0 , 
    input  [319:0]  iflux_ingress_direct_lane1 , 
    input  [319:0]  iflux_ingress_direct_lane2 , 
    input  [319:0]  iflux_ingress_direct_lane3 , 
    output [256:0]  oflux_egress_direct_lane0 , 
    output [256:0]  oflux_egress_direct_lane1 , 
    output [256:0]  oflux_egress_direct_lane2 , 
    output [256:0]  oflux_egress_direct_lane3 , 
    input           iflux_srds_tx_clk_lane0 , 
    input           iflux_srds_tx_clk_lane1 , 
    input           iflux_srds_tx_clk_lane2 , 
    input           iflux_srds_tx_clk_lane3 , 
    output          oflux_cpi_int ,
    output          oflux_int0 ,
    output          oflux_int1 ,
    output          oflux_int2 ,
    output          oflux_int3 ,
    output          oflux_octl_pcs_txptr_smpl_lane0 , 
    output          oflux_octl_pcs_txptr_smpl_lane1 , 
    output          oflux_octl_pcs_txptr_smpl_lane2 , 
    output          oflux_octl_pcs_txptr_smpl_lane3 , 
    input           iflux_ick_pcs_txptr_smpl_clk_l0_lane0 , 
    input           iflux_ick_pcs_txptr_smpl_clk_l0_lane1 , 
    input           iflux_ick_pcs_txptr_smpl_clk_l0_lane2 , 
    input           iflux_ick_pcs_txptr_smpl_clk_l0_lane3 , 
    output          oflux_srds_rdy0 , 
    output          oflux_srds_rdy1 , 
    output          oflux_srds_rdy2 , 
    output          oflux_srds_rdy3 , 
    output          oflux_srds_rx_clk_lane0 , 
    output          oflux_srds_rx_clk_lane1 , 
    output          oflux_srds_rx_clk_lane2 , 
    output          oflux_srds_rx_clk_lane3 ,  
    output          oflux_srds_rx_divn_clk_lane0 , 
    output          oflux_srds_rx_divn_clk_lane1 , 
    output          oflux_srds_rx_divn_clk_lane2 , 
    output          oflux_srds_rx_divn_clk_lane3 , 
    output          oflux_srds_tx_clk_lane0 , 
    output          oflux_srds_tx_clk_lane1 , 
    output          oflux_srds_tx_clk_lane2 , 
    output          oflux_srds_tx_clk_lane3 ,
    output [767:0]  uxwrap_bus_in_lane0 , 
    output [767:0]  uxwrap_bus_in_lane1 , 
    output [767:0]  uxwrap_bus_in_lane2 , 
    output [767:0]  uxwrap_bus_in_lane3 , 
    input  [703:0]  uxwrap_bus_out_lane0 ,
    input  [703:0]  uxwrap_bus_out_lane1 , 
    input  [703:0]  uxwrap_bus_out_lane2 , 
    input  [703:0]  uxwrap_bus_out_lane3 ,  

    input  [3:0]  i_q2q_xcvrrc_ux_ux__txstatus_rc_ux ,  
    output [3:0]  o_q2q_xcvrrc_ux_ux__txstatus_ux_rc  
);

/* `ifdef ALTERA_RESERVED_QIS

`else
    //#4480;
   initial
        begin
            if (num_of_lanes == 2) begin
            //#4480ns;
            #4480000;
                force mc_inst.x_std_ipfluxtop_flux_core_shim_wrap_0.sf_rtl_ncrypt_inst.sf_rtl_inst.serdes_ctrl_ins.serdes_lane_wrap_ins.serdes_lane_ctrl_lane0_ins.i_serdes_lane_car.i_srds_shim_lane_car_regs.srds_shim_lane_car_clkmux0[15:0] = 16'h8304;
                force mc_inst.x_std_ipfluxtop_flux_core_shim_wrap_0.sf_rtl_ncrypt_inst.sf_rtl_inst.serdes_ctrl_ins.serdes_lane_wrap_ins.serdes_lane_ctrl_lane1_ins.i_serdes_lane_car.i_srds_shim_lane_car_regs.srds_shim_lane_car_clkmux0[15:0] = 16'h8304;
            end 
            else if (num_of_lanes == 3) begin
             //#4480ns;
             #4480000;
                force mc_inst.x_std_ipfluxtop_flux_core_shim_wrap_0.sf_rtl_ncrypt_inst.sf_rtl_inst.serdes_ctrl_ins.serdes_lane_wrap_ins.serdes_lane_ctrl_lane0_ins.i_serdes_lane_car.i_srds_shim_lane_car_regs.srds_shim_lane_car_clkmux0[15:0] = 16'h8304;
                force mc_inst.x_std_ipfluxtop_flux_core_shim_wrap_0.sf_rtl_ncrypt_inst.sf_rtl_inst.serdes_ctrl_ins.serdes_lane_wrap_ins.serdes_lane_ctrl_lane1_ins.i_serdes_lane_car.i_srds_shim_lane_car_regs.srds_shim_lane_car_clkmux0[15:0] = 16'h8304;
                force mc_inst.x_std_ipfluxtop_flux_core_shim_wrap_0.sf_rtl_ncrypt_inst.sf_rtl_inst.serdes_ctrl_ins.serdes_lane_wrap_ins.serdes_lane_ctrl_lane2_ins.i_serdes_lane_car.i_srds_shim_lane_car_regs.srds_shim_lane_car_clkmux0[15:0] = 16'h8304;
            end 
            else if (num_of_lanes == 4) begin
            //#4480ns;
            #4480000;
                force mc_inst.x_std_ipfluxtop_flux_core_shim_wrap_0.sf_rtl_ncrypt_inst.sf_rtl_inst.serdes_ctrl_ins.serdes_lane_wrap_ins.serdes_lane_ctrl_lane0_ins.i_serdes_lane_car.i_srds_shim_lane_car_regs.srds_shim_lane_car_clkmux0[15:0] = 16'h8304;    
                force mc_inst.x_std_ipfluxtop_flux_core_shim_wrap_0.sf_rtl_ncrypt_inst.sf_rtl_inst.serdes_ctrl_ins.serdes_lane_wrap_ins.serdes_lane_ctrl_lane1_ins.i_serdes_lane_car.i_srds_shim_lane_car_regs.srds_shim_lane_car_clkmux0[15:0] = 16'h8304;
                force mc_inst.x_std_ipfluxtop_flux_core_shim_wrap_0.sf_rtl_ncrypt_inst.sf_rtl_inst.serdes_ctrl_ins.serdes_lane_wrap_ins.serdes_lane_ctrl_lane2_ins.i_serdes_lane_car.i_srds_shim_lane_car_regs.srds_shim_lane_car_clkmux0[15:0] = 16'h8304;
                force mc_inst.x_std_ipfluxtop_flux_core_shim_wrap_0.sf_rtl_ncrypt_inst.sf_rtl_inst.serdes_ctrl_ins.serdes_lane_wrap_ins.serdes_lane_ctrl_lane3_ins.i_serdes_lane_car.i_srds_shim_lane_car_regs.srds_shim_lane_car_clkmux0[15:0] = 16'h8304;
            end
        end
`endif */

mc #(
    .x_std_sm_hssi_fec_wrap_0__ch0_dr_enabled                                      (ch0_dr_enabled_atom                         ),      
    .x_std_sm_hssi_fec_wrap_0__ch0_duplex_mode                                     (ch0_duplex_mode_atom                        ),
    .x_std_sm_hssi_fec_wrap_0__ch0_dyn_tx_mux                                      (ch0_fec_dyn_tx_mux_atom                     ),  
    .x_std_sm_hssi_fec_wrap_0__ch0_fec_error                                       (ch0_fec_error_atom                          ),
    .x_std_sm_hssi_fec_wrap_0__ch0_fec_mode                                        (ch0_fec_mode_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch0_fec_spec                                        (ch0_fec_spec_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch0_fracture                                        (ch0_fracture_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch0_loopback_mode                                   (ch0_fec_loopback_mode_atom                  ),
    .x_std_sm_hssi_fec_wrap_0__ch0_pcs_rx_en                                       (ch0_pcs_l_rx_en_atom                        ),
    .x_std_sm_hssi_fec_wrap_0__ch0_pcs_tx_en                                       (ch0_pcs_l_tx_en_atom                        ),
    .x_std_sm_hssi_fec_wrap_0__ch0_rx_en                                           (ch0_fec_rx_en_atom                          ),
    .x_std_sm_hssi_fec_wrap_0__ch0_sim_mode                                        (ch0_sim_mode_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch0_sup_mode                                        (ch0_sup_mode_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch0_tx_en                                           (ch0_fec_tx_en_atom                          ),
    .x_std_sm_hssi_fec_wrap_0__ch1_dr_enabled                                      (ch1_dr_enabled_atom                         ),
    .x_std_sm_hssi_fec_wrap_0__ch1_duplex_mode                                     (ch1_duplex_mode_atom                        ),  
    .x_std_sm_hssi_fec_wrap_0__ch1_dyn_tx_mux                                      (ch1_fec_dyn_tx_mux_atom                     ),
    .x_std_sm_hssi_fec_wrap_0__ch1_fec_error                                       (ch1_fec_error_atom                          ),
    .x_std_sm_hssi_fec_wrap_0__ch1_fec_mode                                        (ch1_fec_mode_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch1_fec_spec                                        (ch1_fec_spec_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch1_fracture                                        (ch1_fracture_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch1_loopback_mode                                   (ch1_fec_loopback_mode_atom                  ),
    .x_std_sm_hssi_fec_wrap_0__ch1_pcs_rx_en                                       (ch1_pcs_l_rx_en_atom                        ),
    .x_std_sm_hssi_fec_wrap_0__ch1_pcs_tx_en                                       (ch1_pcs_l_tx_en_atom                        ),
    .x_std_sm_hssi_fec_wrap_0__ch1_rx_en                                           (ch1_fec_rx_en_atom                          ),
    .x_std_sm_hssi_fec_wrap_0__ch1_sim_mode                                        (ch1_sim_mode_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch1_sup_mode                                        (ch1_sup_mode_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch1_tx_en                                           (ch1_fec_tx_en_atom                          ),
    .x_std_sm_hssi_fec_wrap_0__ch2_dr_enabled                                      (ch2_dr_enabled_atom                         ),
    .x_std_sm_hssi_fec_wrap_0__ch2_duplex_mode                                     (ch2_duplex_mode_atom                        ),  
    .x_std_sm_hssi_fec_wrap_0__ch2_dyn_tx_mux                                      (ch2_fec_dyn_tx_mux_atom                     ),
    .x_std_sm_hssi_fec_wrap_0__ch2_fec_error                                       (ch2_fec_error_atom                          ),
    .x_std_sm_hssi_fec_wrap_0__ch2_fec_mode                                        (ch2_fec_mode_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch2_fec_spec                                        (ch2_fec_spec_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch2_fracture                                        (ch2_fracture_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch2_loopback_mode                                   (ch2_fec_loopback_mode_atom                  ),
    .x_std_sm_hssi_fec_wrap_0__ch2_pcs_rx_en                                       (ch2_pcs_l_rx_en_atom                        ),
    .x_std_sm_hssi_fec_wrap_0__ch2_pcs_tx_en                                       (ch2_pcs_l_tx_en_atom                        ),
    .x_std_sm_hssi_fec_wrap_0__ch2_rx_en                                           (ch2_fec_rx_en_atom                          ),
    .x_std_sm_hssi_fec_wrap_0__ch2_sim_mode                                        (ch2_sim_mode_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch2_sup_mode                                        (ch2_sup_mode_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch2_tx_en                                           (ch2_fec_tx_en_atom                          ),
    .x_std_sm_hssi_fec_wrap_0__ch3_dr_enabled                                      (ch3_dr_enabled_atom                         ),
    .x_std_sm_hssi_fec_wrap_0__ch3_duplex_mode                                     (ch3_duplex_mode_atom                        ),  
    .x_std_sm_hssi_fec_wrap_0__ch3_dyn_tx_mux                                      (ch3_fec_dyn_tx_mux_atom                     ),
    .x_std_sm_hssi_fec_wrap_0__ch3_fec_error                                       (ch3_fec_error_atom                          ),
    .x_std_sm_hssi_fec_wrap_0__ch3_fec_mode                                        (ch3_fec_mode_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch3_fec_spec                                        (ch3_fec_spec_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch3_fracture                                        (ch3_fracture_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch3_loopback_mode                                   (ch3_fec_loopback_mode_atom                  ),
    .x_std_sm_hssi_fec_wrap_0__ch3_pcs_rx_en                                       (ch3_pcs_l_rx_en_atom                        ),
    .x_std_sm_hssi_fec_wrap_0__ch3_pcs_tx_en                                       (ch3_pcs_l_tx_en_atom                        ),
    .x_std_sm_hssi_fec_wrap_0__ch3_rx_en                                           (ch3_fec_rx_en_atom                          ),
    .x_std_sm_hssi_fec_wrap_0__ch3_sim_mode                                        (ch3_sim_mode_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch3_sup_mode                                        (ch3_sup_mode_atom                           ),
    .x_std_sm_hssi_fec_wrap_0__ch3_tx_en                                           (ch3_fec_tx_en_atom                          ),
                                                                                   
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_cdr_l_counter                      (ch0_cdr_l_counter_atom                      ),                                  
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_cdr_refclk_select                  (ch0_cdr_refclk_select_atom                  ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_flux_mode                          (ch0_flux_mode_atom                          ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_loopback_mode                      (ch0_phy_loopback_mode_atom                  ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_pcie_mode                          (ch0_pcie_mode_atom                          ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_prbs_monitor_en                 (ch0_xcvr_rx_prbs_monitor_en_atom            ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_prbs_pattern                    (ch0_xcvr_rx_prbs_pattern_atom               ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_preloaded_hardware_configs      (ch0_xcvr_rx_preloaded_hardware_configs_atom ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_sim_mode                        (ch0_rx_sim_mode_atom                        ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_width                           (ch0_xcvr_rx_width_atom                      ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_bonding_category                (ch0_tx_bonding_category_atom                ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_pll_l_counter                   (ch0_tx_pll_l_counter_atom                   ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_pll_refclk_select               (ch0_tx_pll_refclk_select_atom               ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_prbs_gen_en                     (ch0_tx_prbs_gen_en_atom                     ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_prbs_pattern                    (ch0_xcvr_tx_prbs_pattern_atom               ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_preloaded_hardware_configs      (ch0_xcvr_tx_preloaded_hardware_configs_atom ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_sim_mode                        (ch0_tx_sim_mode_atom                        ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_user_clk_only_mode              (ch0_xcvr_tx_user_clk_only_mode_atom         ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_width                           (ch0_xcvr_tx_width_atom                      ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_cdr_l_counter                      (ch1_cdr_l_counter_atom                      ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_cdr_refclk_select                  (ch1_cdr_refclk_select_atom                  ),    
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_flux_mode                          (ch1_flux_mode_atom                          ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_loopback_mode                      (ch1_phy_loopback_mode_atom                  ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_pcie_mode                          (ch1_pcie_mode_atom                          ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_prbs_monitor_en                 (ch1_xcvr_rx_prbs_monitor_en_atom            ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_prbs_pattern                    (ch1_xcvr_rx_prbs_pattern_atom               ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_preloaded_hardware_configs      (ch1_xcvr_rx_preloaded_hardware_configs_atom ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_sim_mode                        (ch1_rx_sim_mode_atom                        ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_width                           (ch1_xcvr_rx_width_atom                      ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_bonding_category                (ch1_tx_bonding_category_atom                ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_pll_l_counter                   (ch1_tx_pll_l_counter_atom                   ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_pll_refclk_select               (ch1_tx_pll_refclk_select_atom               ),    
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_prbs_gen_en                     (ch1_tx_prbs_gen_en_atom                     ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_prbs_pattern                    (ch1_xcvr_tx_prbs_pattern_atom               ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_preloaded_hardware_configs      (ch1_xcvr_tx_preloaded_hardware_configs_atom ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_sim_mode                        (ch1_tx_sim_mode_atom                        ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_user_clk_only_mode              (ch1_xcvr_tx_user_clk_only_mode_atom         ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_width                           (ch1_xcvr_tx_width_atom                      ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_cdr_l_counter                      (ch2_cdr_l_counter_atom                      ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_cdr_refclk_select                  (ch2_cdr_refclk_select_atom                  ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_flux_mode                          (ch2_flux_mode_atom                          ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_loopback_mode                      (ch2_phy_loopback_mode_atom                  ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_pcie_mode                          (ch2_pcie_mode_atom                          ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_prbs_monitor_en                 (ch2_xcvr_rx_prbs_monitor_en_atom            ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_prbs_pattern                    (ch2_xcvr_rx_prbs_pattern_atom               ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_preloaded_hardware_configs      (ch2_xcvr_rx_preloaded_hardware_configs_atom ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_sim_mode                        (ch2_rx_sim_mode_atom                        ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_width                           (ch2_xcvr_rx_width_atom                      ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_bonding_category                (ch2_tx_bonding_category_atom                ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_pll_l_counter                   (ch2_tx_pll_l_counter_atom                   ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_pll_refclk_select               (ch2_tx_pll_refclk_select_atom               ), 
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_prbs_gen_en                     (ch2_tx_prbs_gen_en_atom                     ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_prbs_pattern                    (ch2_xcvr_tx_prbs_pattern_atom               ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_preloaded_hardware_configs      (ch2_xcvr_tx_preloaded_hardware_configs_atom ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_sim_mode                        (ch2_tx_sim_mode_atom                        ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_user_clk_only_mode              (ch2_xcvr_tx_user_clk_only_mode_atom         ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_width                           (ch2_xcvr_tx_width_atom                      ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_cdr_l_counter                      (ch3_cdr_l_counter_atom                      ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_cdr_refclk_select                  (ch3_cdr_refclk_select_atom                  ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_flux_mode                          (ch3_flux_mode_atom                          ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_loopback_mode                      (ch3_phy_loopback_mode_atom                  ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_pcie_mode                          (ch3_pcie_mode_atom                          ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_prbs_monitor_en                 (ch3_xcvr_rx_prbs_monitor_en_atom            ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_prbs_pattern                    (ch3_xcvr_rx_prbs_pattern_atom               ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_preloaded_hardware_configs      (ch3_xcvr_rx_preloaded_hardware_configs_atom ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_sim_mode                        (ch3_rx_sim_mode_atom                        ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_width                           (ch3_xcvr_rx_width_atom                      ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_bonding_category                (ch3_tx_bonding_category_atom                ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_pll_l_counter                   (ch3_tx_pll_l_counter_atom                   ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_pll_refclk_select               (ch3_tx_pll_refclk_select_atom               ), 
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_prbs_gen_en                     (ch3_tx_prbs_gen_en_atom                     ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_prbs_pattern                    (ch3_xcvr_tx_prbs_pattern_atom               ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_preloaded_hardware_configs      (ch3_xcvr_tx_preloaded_hardware_configs_atom ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_sim_mode                        (ch3_tx_sim_mode_atom                        ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_user_clk_only_mode              (ch3_xcvr_tx_user_clk_only_mode_atom         ),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_width                           (ch3_xcvr_tx_width_atom                      ),

    .x_std_sm_ux_toolbox_0__ch0_clkrx_refclk_cssm_fw_control                       (ch0_clkrx_refclk_cssm_fw_control_atom       ),
    .x_std_sm_ux_toolbox_0__ch0_clkrx_refclk_sector_specifies_refclk_ready         (ch0_clkrx_refclk_sector_specifies_refclk_ready_atom ),
    .x_std_sm_ux_toolbox_0__ch0_dr_enabled                                         (ch0_dr_enabled_atom                         ),
    .x_std_sm_ux_toolbox_0__ch0_flux_mode                                          (ch0_flux_mode_atom                          ),
    .x_std_sm_ux_toolbox_0__ch0_lc_postdiv_sel                                     (ch0_lc_postdiv_sel_atom                     ),
    .x_std_sm_ux_toolbox_0__ch0_local_refclk_cssm_fw_control                       (ch0_local_refclk_cssm_fw_control_atom       ),
    .x_std_sm_ux_toolbox_0__ch0_local_refclk_sector_specifies_refclk_ready         (ch0_local_refclk_sector_specifies_refclk_ready_atom ),
    .x_std_sm_ux_toolbox_0__ch0_loopback_mode                                      (ch0_phy_loopback_mode_atom                  ),
    .x_std_sm_ux_toolbox_0__ch0_rst_mux_static_sel                                 (ch0_rst_mux_static_sel_atom                 ),
    .x_std_sm_ux_toolbox_0__ch0_rx_dl_enable                                       (ch0_rx_dl_enable_atom                       ),
    .x_std_sm_ux_toolbox_0__ch0_rx_dl_rx_lat_bit_for_async                         (ch0_rx_dl_rx_lat_bit_for_async_atom         ),
    .x_std_sm_ux_toolbox_0__ch0_rx_dl_rxbit_cntr_pma                               (ch0_rx_dl_rxbit_cntr_pma_atom               ),
    .x_std_sm_ux_toolbox_0__ch0_rx_dl_rxbit_rollover                               (ch0_rx_dl_rxbit_rollover_atom               ),
    .x_std_sm_ux_toolbox_0__ch0_rx_fec_type_used                                   (ch0_rx_fec_type_used_atom                   ),
    .x_std_sm_ux_toolbox_0__ch0_rx_preloaded_hardware_configs                      (ch0_xcvr_rx_preloaded_hardware_configs_atom ),
    .x_std_sm_ux_toolbox_0__ch0_rx_protocol_hint                                   (ch0_xcvr_rx_protocol_hint_atom              ),
    .x_std_sm_ux_toolbox_0__ch0_rx_user1_clk_mux_dynamic_sel                       (ch0_rx_user1_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch0_rx_user2_clk_mux_dynamic_sel                       (ch0_rx_user2_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch0_rx_width                                           (ch0_xcvr_rx_width_atom                      ),
    .x_std_sm_ux_toolbox_0__ch0_sequencer_reg_en                                   (ch0_sequencer_reg_en_atom                   ),
    .x_std_sm_ux_toolbox_0__ch0_tx_bond_size                                       (ch0_tx_bond_size_atom                       ),
    .x_std_sm_ux_toolbox_0__ch0_tx_bonding_category                                (ch0_tx_bonding_category_atom                ),
    .x_std_sm_ux_toolbox_0__ch0_tx_dl_enable                                       (ch0_tx_dl_enable_atom                       ),
    .x_std_sm_ux_toolbox_0__ch0_tx_preloaded_hardware_configs                      (ch0_xcvr_tx_preloaded_hardware_configs_atom ),
    .x_std_sm_ux_toolbox_0__ch0_tx_user1_clk_mux_dynamic_sel                       (ch0_tx_user1_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch0_tx_user2_clk_mux_dynamic_sel                       (ch0_tx_user2_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch1_clkrx_refclk_cssm_fw_control                       (ch1_clkrx_refclk_cssm_fw_control_atom       ),
    .x_std_sm_ux_toolbox_0__ch1_clkrx_refclk_sector_specifies_refclk_ready         (ch1_clkrx_refclk_sector_specifies_refclk_ready_atom ),
    .x_std_sm_ux_toolbox_0__ch1_dr_enabled                                         (ch1_dr_enabled_atom                         ),
    .x_std_sm_ux_toolbox_0__ch1_flux_mode                                          (ch1_flux_mode_atom                          ),
    .x_std_sm_ux_toolbox_0__ch1_lc_postdiv_sel                                     (ch1_lc_postdiv_sel_atom                     ),
    .x_std_sm_ux_toolbox_0__ch1_local_refclk_cssm_fw_control                       (ch1_local_refclk_cssm_fw_control_atom       ),
    .x_std_sm_ux_toolbox_0__ch1_local_refclk_sector_specifies_refclk_ready         (ch1_local_refclk_sector_specifies_refclk_ready_atom ),
    .x_std_sm_ux_toolbox_0__ch1_loopback_mode                                      (ch1_phy_loopback_mode_atom                  ),
    .x_std_sm_ux_toolbox_0__ch1_rst_mux_static_sel                                 (ch1_rst_mux_static_sel_atom                 ),
    .x_std_sm_ux_toolbox_0__ch1_rx_dl_enable                                       (ch1_rx_dl_enable_atom                       ),
    .x_std_sm_ux_toolbox_0__ch1_rx_dl_rx_lat_bit_for_async                         (ch1_rx_dl_rx_lat_bit_for_async_atom         ),
    .x_std_sm_ux_toolbox_0__ch1_rx_dl_rxbit_cntr_pma                               (ch1_rx_dl_rxbit_cntr_pma_atom               ),
    .x_std_sm_ux_toolbox_0__ch1_rx_dl_rxbit_rollover                               (ch1_rx_dl_rxbit_rollover_atom               ),
    .x_std_sm_ux_toolbox_0__ch1_rx_fec_type_used                                   (ch1_rx_fec_type_used_atom                   ),
    .x_std_sm_ux_toolbox_0__ch1_rx_preloaded_hardware_configs                      (ch1_xcvr_rx_preloaded_hardware_configs_atom ),
    .x_std_sm_ux_toolbox_0__ch1_rx_protocol_hint                                   (ch1_xcvr_rx_protocol_hint_atom              ),
    .x_std_sm_ux_toolbox_0__ch1_rx_user1_clk_mux_dynamic_sel                       (ch1_rx_user1_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch1_rx_user2_clk_mux_dynamic_sel                       (ch1_rx_user2_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch1_rx_width                                           (ch1_xcvr_rx_width_atom                      ),
    .x_std_sm_ux_toolbox_0__ch1_sequencer_reg_en                                   (ch1_sequencer_reg_en_atom                   ),
    .x_std_sm_ux_toolbox_0__ch1_tx_bond_size                                       (ch1_tx_bond_size_atom                       ),
    .x_std_sm_ux_toolbox_0__ch1_tx_bonding_category                                (ch1_tx_bonding_category_atom                ),    
    .x_std_sm_ux_toolbox_0__ch1_tx_dl_enable                                       (ch1_tx_dl_enable_atom                       ),
    .x_std_sm_ux_toolbox_0__ch1_tx_preloaded_hardware_configs                      (ch1_xcvr_tx_preloaded_hardware_configs_atom ),
    .x_std_sm_ux_toolbox_0__ch1_tx_user1_clk_mux_dynamic_sel                       (ch1_tx_user1_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch1_tx_user2_clk_mux_dynamic_sel                       (ch1_tx_user2_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch2_clkrx_refclk_cssm_fw_control                       (ch2_clkrx_refclk_cssm_fw_control_atom       ),
    .x_std_sm_ux_toolbox_0__ch2_clkrx_refclk_sector_specifies_refclk_ready         (ch2_clkrx_refclk_sector_specifies_refclk_ready_atom ),
    .x_std_sm_ux_toolbox_0__ch2_dr_enabled                                         (ch2_dr_enabled_atom                         ),
    .x_std_sm_ux_toolbox_0__ch2_flux_mode                                          (ch2_flux_mode_atom                          ),
    .x_std_sm_ux_toolbox_0__ch2_lc_postdiv_sel                                     (ch2_lc_postdiv_sel_atom                     ),
    .x_std_sm_ux_toolbox_0__ch2_local_refclk_cssm_fw_control                       (ch2_local_refclk_cssm_fw_control_atom       ),
    .x_std_sm_ux_toolbox_0__ch2_local_refclk_sector_specifies_refclk_ready         (ch2_local_refclk_sector_specifies_refclk_ready_atom ),
    .x_std_sm_ux_toolbox_0__ch2_loopback_mode                                      (ch2_phy_loopback_mode_atom                  ),
    .x_std_sm_ux_toolbox_0__ch2_rst_mux_static_sel                                 (ch2_rst_mux_static_sel_atom                 ),
    .x_std_sm_ux_toolbox_0__ch2_rx_dl_enable                                       (ch2_rx_dl_enable_atom                       ),
    .x_std_sm_ux_toolbox_0__ch2_rx_dl_rx_lat_bit_for_async                         (ch2_rx_dl_rx_lat_bit_for_async_atom         ),
    .x_std_sm_ux_toolbox_0__ch2_rx_dl_rxbit_cntr_pma                               (ch2_rx_dl_rxbit_cntr_pma_atom               ),
    .x_std_sm_ux_toolbox_0__ch2_rx_dl_rxbit_rollover                               (ch2_rx_dl_rxbit_rollover_atom               ),
    .x_std_sm_ux_toolbox_0__ch2_rx_fec_type_used                                   (ch2_rx_fec_type_used_atom                   ),
    .x_std_sm_ux_toolbox_0__ch2_rx_preloaded_hardware_configs                      (ch2_xcvr_rx_preloaded_hardware_configs_atom ),
    .x_std_sm_ux_toolbox_0__ch2_rx_protocol_hint                                   (ch2_xcvr_rx_protocol_hint_atom              ),
    .x_std_sm_ux_toolbox_0__ch2_rx_user1_clk_mux_dynamic_sel                       (ch2_rx_user1_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch2_rx_user2_clk_mux_dynamic_sel                       (ch2_rx_user2_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch2_rx_width                                           (ch2_xcvr_rx_width_atom                      ),
    .x_std_sm_ux_toolbox_0__ch2_sequencer_reg_en                                   (ch2_sequencer_reg_en_atom                   ),
    .x_std_sm_ux_toolbox_0__ch2_tx_bond_size                                       (ch2_tx_bond_size_atom                       ),
    .x_std_sm_ux_toolbox_0__ch2_tx_bonding_category                                (ch2_tx_bonding_category_atom                ),
    .x_std_sm_ux_toolbox_0__ch2_tx_dl_enable                                       (ch2_tx_dl_enable_atom                       ),
    .x_std_sm_ux_toolbox_0__ch2_tx_preloaded_hardware_configs                      (ch2_xcvr_tx_preloaded_hardware_configs_atom ),
    .x_std_sm_ux_toolbox_0__ch2_tx_user1_clk_mux_dynamic_sel                       (ch2_tx_user1_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch2_tx_user2_clk_mux_dynamic_sel                       (ch2_tx_user2_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch3_clkrx_refclk_cssm_fw_control                       (ch3_clkrx_refclk_cssm_fw_control_atom       ),
    .x_std_sm_ux_toolbox_0__ch3_clkrx_refclk_sector_specifies_refclk_ready         (ch3_clkrx_refclk_sector_specifies_refclk_ready_atom ),
    .x_std_sm_ux_toolbox_0__ch3_dr_enabled                                         (ch3_dr_enabled_atom                         ),
    .x_std_sm_ux_toolbox_0__ch3_flux_mode                                          (ch3_flux_mode_atom                          ),
    .x_std_sm_ux_toolbox_0__ch3_lc_postdiv_sel                                     (ch3_lc_postdiv_sel_atom                     ),
    .x_std_sm_ux_toolbox_0__ch3_local_refclk_cssm_fw_control                       (ch3_local_refclk_cssm_fw_control_atom       ),
    .x_std_sm_ux_toolbox_0__ch3_local_refclk_sector_specifies_refclk_ready         (ch3_local_refclk_sector_specifies_refclk_ready_atom ),
    .x_std_sm_ux_toolbox_0__ch3_loopback_mode                                      (ch3_phy_loopback_mode_atom                  ),
    .x_std_sm_ux_toolbox_0__ch3_rst_mux_static_sel                                 (ch3_rst_mux_static_sel_atom                 ),
    .x_std_sm_ux_toolbox_0__ch3_rx_dl_enable                                       (ch3_rx_dl_enable_atom                       ),
    .x_std_sm_ux_toolbox_0__ch3_rx_dl_rx_lat_bit_for_async                         (ch3_rx_dl_rx_lat_bit_for_async_atom         ),
    .x_std_sm_ux_toolbox_0__ch3_rx_dl_rxbit_cntr_pma                               (ch3_rx_dl_rxbit_cntr_pma_atom               ),
    .x_std_sm_ux_toolbox_0__ch3_rx_dl_rxbit_rollover                               (ch3_rx_dl_rxbit_rollover_atom               ),
    .x_std_sm_ux_toolbox_0__ch3_rx_fec_type_used                                   (ch3_rx_fec_type_used_atom                   ),
    .x_std_sm_ux_toolbox_0__ch3_rx_preloaded_hardware_configs                      (ch3_xcvr_rx_preloaded_hardware_configs_atom ),
    .x_std_sm_ux_toolbox_0__ch3_rx_protocol_hint                                   (ch3_xcvr_rx_protocol_hint_atom              ),
    .x_std_sm_ux_toolbox_0__ch3_rx_user1_clk_mux_dynamic_sel                       (ch3_rx_user1_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch3_rx_user2_clk_mux_dynamic_sel                       (ch3_rx_user2_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch3_rx_width                                           (ch3_xcvr_rx_width_atom                      ),
    .x_std_sm_ux_toolbox_0__ch3_sequencer_reg_en                                   (ch3_sequencer_reg_en_atom                   ),
    .x_std_sm_ux_toolbox_0__ch3_tx_bond_size                                       (ch3_tx_bond_size_atom                       ),
    .x_std_sm_ux_toolbox_0__ch3_tx_bonding_category                                (ch3_tx_bonding_category_atom                ),
    .x_std_sm_ux_toolbox_0__ch3_tx_dl_enable                                       (ch3_tx_dl_enable_atom                       ),
    .x_std_sm_ux_toolbox_0__ch3_tx_preloaded_hardware_configs                      (ch3_xcvr_tx_preloaded_hardware_configs_atom ),
    .x_std_sm_ux_toolbox_0__ch3_tx_user1_clk_mux_dynamic_sel                       (ch3_tx_user1_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch3_tx_user2_clk_mux_dynamic_sel                       (ch3_tx_user2_clk_mux_dynamic_sel_atom       ),
    .x_std_sm_ux_toolbox_0__ch0_rx_invert_pin_atom                                 (ch0_rx_invert_pin_atom       ),
    .x_std_sm_ux_toolbox_0__ch1_rx_invert_pin_atom                                 (ch1_rx_invert_pin_atom       ),
    .x_std_sm_ux_toolbox_0__ch2_rx_invert_pin_atom                                 (ch2_rx_invert_pin_atom       ),
    .x_std_sm_ux_toolbox_0__ch3_rx_invert_pin_atom                                 (ch3_rx_invert_pin_atom       ),
    .x_std_sm_ux_toolbox_0__ch0_tx_invert_pin_atom                                 (ch0_tx_invert_pin_atom       ),
    .x_std_sm_ux_toolbox_0__ch1_tx_invert_pin_atom                                 (ch1_tx_invert_pin_atom       ),
    .x_std_sm_ux_toolbox_0__ch2_tx_invert_pin_atom                                 (ch2_tx_invert_pin_atom       ),
    .x_std_sm_ux_toolbox_0__ch3_tx_invert_pin_atom                                 (ch3_tx_invert_pin_atom       ),
    .x_std_sm_ux_toolbox_0__ch0_vsr_mode_atom                                      (ch0_vsr_mode_atom            ),
    .x_std_sm_ux_toolbox_0__ch1_vsr_mode_atom                                      (ch1_vsr_mode_atom            ),
    .x_std_sm_ux_toolbox_0__ch2_vsr_mode_atom                                      (ch2_vsr_mode_atom            ),
    .x_std_sm_ux_toolbox_0__ch3_vsr_mode_atom                                      (ch3_vsr_mode_atom            )
) mc_inst (
    .x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_addr                                 (i_ch0_lavmm_fec_addr),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_addr                                 (i_ch1_lavmm_fec_addr),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_addr                                 (i_ch2_lavmm_fec_addr),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_addr                                 (i_ch3_lavmm_fec_addr),
    .x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_wdata                                (i_ch0_lavmm_fec_wdata),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_wdata                                (i_ch1_lavmm_fec_wdata),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_wdata                                (i_ch2_lavmm_fec_wdata),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_wdata                                (i_ch3_lavmm_fec_wdata),
    .x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_be                                   (i_ch0_lavmm_fec_be),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_be                                   (i_ch1_lavmm_fec_be),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_be                                   (i_ch2_lavmm_fec_be),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_be                                   (i_ch3_lavmm_fec_be),
    .x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch0_tx_mux_data                           (i_fec_wrap_ch0_tx_mux_data),
    .x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch1_tx_mux_data                           (i_fec_wrap_ch1_tx_mux_data),
    .x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch2_tx_mux_data                           (i_fec_wrap_ch2_tx_mux_data),
    .x_std_sm_hssi_fec_wrap_0__i_fec_wrap_ch3_tx_mux_data                           (i_fec_wrap_ch3_tx_mux_data),
    .x_std_sm_hssi_fec_wrap_0__i_xcvr_ch0_rx_data                                   (i_xcvr_ch0_rx_data),
    .x_std_sm_hssi_fec_wrap_0__i_xcvr_ch1_rx_data                                   (i_xcvr_ch1_rx_data),
    .x_std_sm_hssi_fec_wrap_0__i_xcvr_ch2_rx_data                                   (i_xcvr_ch2_rx_data),
    .x_std_sm_hssi_fec_wrap_0__i_xcvr_ch3_rx_data                                   (i_xcvr_ch3_rx_data),
    .x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_async                               (i_ch0_eth_fec_tx_async),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_async                               (i_ch1_eth_fec_tx_async),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_async                               (i_ch2_eth_fec_tx_async),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_async                               (i_ch3_eth_fec_tx_async),
    .x_std_sm_hssi_fec_wrap_0__i_ch0_eth_fec_tx_direct                              (i_ch0_eth_fec_tx_direct),
    .x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_clk                                  (i_ch0_lavmm_fec_clk),
    .x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_read                                 (i_ch0_lavmm_fec_read),
    .x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_rstn                                 (i_ch0_lavmm_fec_rstn),
    .x_std_sm_hssi_fec_wrap_0__i_ch0_lavmm_fec_write                                (i_ch0_lavmm_fec_write),
    .x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_csr_ret                             (i_ch0_rstfec_fec_csr_ret),
    .x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_rx_rst_n                            (i_ch0_rstfec_fec_rx_rst_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_fec_tx_rst_n                            (i_ch0_rstfec_fec_tx_rst_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_rx_fec_sfrz_n                           (i_ch0_rstfec_rx_fec_sfrz_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch0_rstfec_tx_fec_sfrz_n                           (i_ch0_rstfec_tx_fec_sfrz_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_eth_fec_tx_direct                              (i_ch1_eth_fec_tx_direct),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_clk                                  (i_ch1_lavmm_fec_clk),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_read                                 (i_ch1_lavmm_fec_read),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_rstn                                 (i_ch1_lavmm_fec_rstn),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_lavmm_fec_write                                (i_ch1_lavmm_fec_write),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_csr_ret                             (i_ch1_rstfec_fec_csr_ret),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_rx_rst_n                            (i_ch1_rstfec_fec_rx_rst_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_fec_tx_rst_n                            (i_ch1_rstfec_fec_tx_rst_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_rx_fec_sfrz_n                           (i_ch1_rstfec_rx_fec_sfrz_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch1_rstfec_tx_fec_sfrz_n                           (i_ch1_rstfec_tx_fec_sfrz_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_eth_fec_tx_direct                              (i_ch2_eth_fec_tx_direct),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_clk                                  (i_ch2_lavmm_fec_clk),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_read                                 (i_ch2_lavmm_fec_read),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_rstn                                 (i_ch2_lavmm_fec_rstn),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_lavmm_fec_write                                (i_ch2_lavmm_fec_write),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_csr_ret                             (i_ch2_rstfec_fec_csr_ret),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_rx_rst_n                            (i_ch2_rstfec_fec_rx_rst_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_fec_tx_rst_n                            (i_ch2_rstfec_fec_tx_rst_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_rx_fec_sfrz_n                           (i_ch2_rstfec_rx_fec_sfrz_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch2_rstfec_tx_fec_sfrz_n                           (i_ch2_rstfec_tx_fec_sfrz_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_eth_fec_tx_direct                              (i_ch3_eth_fec_tx_direct),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_clk                                  (i_ch3_lavmm_fec_clk),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_read                                 (i_ch3_lavmm_fec_read),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_rstn                                 (i_ch3_lavmm_fec_rstn),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_lavmm_fec_write                                (i_ch3_lavmm_fec_write),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_csr_ret                             (i_ch3_rstfec_fec_csr_ret),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_rx_rst_n                            (i_ch3_rstfec_fec_rx_rst_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_fec_tx_rst_n                            (i_ch3_rstfec_fec_tx_rst_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_rx_fec_sfrz_n                           (i_ch3_rstfec_rx_fec_sfrz_n),
    .x_std_sm_hssi_fec_wrap_0__i_ch3_rstfec_tx_fec_sfrz_n                           (i_ch3_rstfec_tx_fec_sfrz_n),
    .x_std_sm_hssi_fec_wrap_0__i_fec_clk                                            (i_fec_clk),
    .x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch0                                      (i_pma_rx_sf_ch0),
    .x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch1                                      (i_pma_rx_sf_ch1),
    .x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch2                                      (i_pma_rx_sf_ch2),
    .x_std_sm_hssi_fec_wrap_0__i_pma_rx_sf_ch3                                      (i_pma_rx_sf_ch3),
    .x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_async                               (o_ch0_eth_fec_rx_async),
    .x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_async                               (o_ch1_eth_fec_rx_async),
    .x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_async                               (o_ch2_eth_fec_rx_async),
    .x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_async                               (o_ch3_eth_fec_rx_async),
    .x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata                                (o_ch0_lavmm_fec_rdata),
    .x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata                                (o_ch1_lavmm_fec_rdata),
    .x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata                                (o_ch2_lavmm_fec_rdata),
    .x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata                                (o_ch3_lavmm_fec_rdata),
    .x_std_sm_hssi_fec_wrap_0__o_fec_ch0_rx_data                                    (o_fec_ch0_rx_data),
    .x_std_sm_hssi_fec_wrap_0__o_fec_ch1_rx_data                                    (o_fec_ch1_rx_data),
    .x_std_sm_hssi_fec_wrap_0__o_fec_ch2_rx_data                                    (o_fec_ch2_rx_data),
    .x_std_sm_hssi_fec_wrap_0__o_fec_ch3_rx_data                                    (o_fec_ch3_rx_data),
    .x_std_sm_hssi_fec_wrap_0__o_xcvr_ch0_tx_data                                   (o_xcvr_ch0_tx_data),
    .x_std_sm_hssi_fec_wrap_0__o_xcvr_ch1_tx_data                                   (o_xcvr_ch1_tx_data),
    .x_std_sm_hssi_fec_wrap_0__o_xcvr_ch2_tx_data                                   (o_xcvr_ch2_tx_data),
    .x_std_sm_hssi_fec_wrap_0__o_xcvr_ch3_tx_data                                   (o_xcvr_ch3_tx_data),
    .x_std_sm_hssi_fec_wrap_0__o_ch0_eth_fec_rx_direct                              (o_ch0_eth_fec_rx_direct),
    .x_std_sm_hssi_fec_wrap_0__o_ch0_fec_rx_rdy_n                                   (o_ch0_fec_rx_rdy_n),
    .x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_rdata_valid                          (o_ch0_lavmm_fec_rdata_valid),
    .x_std_sm_hssi_fec_wrap_0__o_ch0_lavmm_fec_waitreq                              (o_ch0_lavmm_fec_waitreq),
    .x_std_sm_hssi_fec_wrap_0__o_ch1_eth_fec_rx_direct                              (o_ch1_eth_fec_rx_direct),
    .x_std_sm_hssi_fec_wrap_0__o_ch1_fec_rx_rdy_n                                   (o_ch1_fec_rx_rdy_n),
    .x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_rdata_valid                          (o_ch1_lavmm_fec_rdata_valid),
    .x_std_sm_hssi_fec_wrap_0__o_ch1_lavmm_fec_waitreq                              (o_ch1_lavmm_fec_waitreq),
    .x_std_sm_hssi_fec_wrap_0__o_ch2_eth_fec_rx_direct                              (o_ch2_eth_fec_rx_direct),
    .x_std_sm_hssi_fec_wrap_0__o_ch2_fec_rx_rdy_n                                   (o_ch2_fec_rx_rdy_n),
    .x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_rdata_valid                          (o_ch2_lavmm_fec_rdata_valid),
    .x_std_sm_hssi_fec_wrap_0__o_ch2_lavmm_fec_waitreq                              (o_ch2_lavmm_fec_waitreq),
    .x_std_sm_hssi_fec_wrap_0__o_ch3_eth_fec_rx_direct                              (o_ch3_eth_fec_rx_direct),
    .x_std_sm_hssi_fec_wrap_0__o_ch3_fec_rx_rdy_n                                   (o_ch3_fec_rx_rdy_n),
    .x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_rdata_valid                          (o_ch3_lavmm_fec_rdata_valid),
    .x_std_sm_hssi_fec_wrap_0__o_ch3_lavmm_fec_waitreq                              (o_ch3_lavmm_fec_waitreq),
    .x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch0                            (o_fec_tx_data_mux_sel_ch0),
    .x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch1                            (o_fec_tx_data_mux_sel_ch1),
    .x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch2                            (o_fec_tx_data_mux_sel_ch2),
    .x_std_sm_hssi_fec_wrap_0__o_fec_tx_data_mux_sel_ch3                            (o_fec_tx_data_mux_sel_ch3),
    
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0              (iflux_ingress_direct_lane0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1              (iflux_ingress_direct_lane1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2              (iflux_ingress_direct_lane2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3              (iflux_ingress_direct_lane3),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0                    (uxwrap_bus_out_lane0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1                    (uxwrap_bus_out_lane1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane2                    (uxwrap_bus_out_lane2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3                    (uxwrap_bus_out_lane3),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0                  (iflux_pcs_txword_lane0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1                  (iflux_pcs_txword_lane1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane2                  (iflux_pcs_txword_lane2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3                  (iflux_pcs_txword_lane3),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ext_cpu_fast_clk                  (iflux_ext_cpu_fast_clk),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane0   (iflux_ick_pcs_txptr_smpl_clk_l0_lane0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane1   (iflux_ick_pcs_txptr_smpl_clk_l0_lane1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane2   (iflux_ick_pcs_txptr_smpl_clk_l0_lane2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane3   (iflux_ick_pcs_txptr_smpl_clk_l0_lane3),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane0                 (iflux_srds_tx_clk_lane0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane1                 (iflux_srds_tx_clk_lane1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane2                 (iflux_srds_tx_clk_lane2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane3                 (iflux_srds_tx_clk_lane3),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0               (oflux_egress_direct_lane0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1               (oflux_egress_direct_lane1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane2               (oflux_egress_direct_lane2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3               (oflux_egress_direct_lane3),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0                     (uxwrap_bus_in_lane0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1                     (uxwrap_bus_in_lane1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane2                     (uxwrap_bus_in_lane2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3                     (uxwrap_bus_in_lane3),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0                  (oflux_pcs_rxword_lane0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1                  (oflux_pcs_rxword_lane1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane2                  (oflux_pcs_rxword_lane2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3                  (oflux_pcs_rxword_lane3),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_cpi_int                           (oflux_cpi_int),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int0                              (oflux_int0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int1                              (oflux_int1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int2                              (oflux_int2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int3                              (oflux_int3),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane0         (oflux_octl_pcs_txptr_smpl_lane0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane1         (oflux_octl_pcs_txptr_smpl_lane1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane2         (oflux_octl_pcs_txptr_smpl_lane2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane3         (oflux_octl_pcs_txptr_smpl_lane3),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy0                         (oflux_srds_rdy0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy1                         (oflux_srds_rdy1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy2                         (oflux_srds_rdy2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy3                         (oflux_srds_rdy3),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane0                 (oflux_srds_rx_clk_lane0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane1                 (oflux_srds_rx_clk_lane1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane2                 (oflux_srds_rx_clk_lane2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane3                 (oflux_srds_rx_clk_lane3),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane0            (oflux_srds_rx_divn_clk_lane0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane1            (oflux_srds_rx_divn_clk_lane1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane2            (oflux_srds_rx_divn_clk_lane2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane3            (oflux_srds_rx_divn_clk_lane3),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane0                 (oflux_srds_tx_clk_lane0),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane1                 (oflux_srds_tx_clk_lane1),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane2                 (oflux_srds_tx_clk_lane2),
    .x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane3                 (oflux_srds_tx_clk_lane3),
    
    .x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr                                        (i_ch0_lavmm_addr),
    .x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr                                        (i_ch1_lavmm_addr),
    .x_std_sm_ux_toolbox_0__i_ch2_lavmm_addr                                        (i_ch2_lavmm_addr),
    .x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr                                        (i_ch3_lavmm_addr),
    .x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata                                       (i_ch0_lavmm_wdata),
    .x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata                                       (i_ch1_lavmm_wdata),
    .x_std_sm_ux_toolbox_0__i_ch2_lavmm_wdata                                       (i_ch2_lavmm_wdata),
    .x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata                                       (i_ch3_lavmm_wdata),
    .x_std_sm_ux_toolbox_0__i_ch0_lavmm_be                                          (i_ch0_lavmm_be),
    .x_std_sm_ux_toolbox_0__i_ch1_lavmm_be                                          (i_ch1_lavmm_be),
    .x_std_sm_ux_toolbox_0__i_ch2_lavmm_be                                          (i_ch2_lavmm_be),
    .x_std_sm_ux_toolbox_0__i_ch3_lavmm_be                                          (i_ch3_lavmm_be),
    .x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux                      (i_q2q_xcvrrc_ux_ux__txstatus_rc_ux),
    .x_std_sm_ux_toolbox_0__i_ch0_lavmm_clk                                         (i_ch0_lavmm_clk),
    .x_std_sm_ux_toolbox_0__i_ch0_lavmm_read                                        (i_ch0_lavmm_read),
    .x_std_sm_ux_toolbox_0__i_ch0_lavmm_rstn                                        (i_ch0_lavmm_rstn),
    .x_std_sm_ux_toolbox_0__i_ch0_lavmm_write                                       (i_ch0_lavmm_write),
    .x_std_sm_ux_toolbox_0__i_ch1_lavmm_clk                                         (i_ch1_lavmm_clk),
    .x_std_sm_ux_toolbox_0__i_ch1_lavmm_read                                        (i_ch1_lavmm_read),
    .x_std_sm_ux_toolbox_0__i_ch1_lavmm_rstn                                        (i_ch1_lavmm_rstn),
    .x_std_sm_ux_toolbox_0__i_ch1_lavmm_write                                       (i_ch1_lavmm_write),
    .x_std_sm_ux_toolbox_0__i_ch2_lavmm_clk                                         (i_ch2_lavmm_clk),
    .x_std_sm_ux_toolbox_0__i_ch2_lavmm_read                                        (i_ch2_lavmm_read),
    .x_std_sm_ux_toolbox_0__i_ch2_lavmm_rstn                                        (i_ch2_lavmm_rstn),
    .x_std_sm_ux_toolbox_0__i_ch2_lavmm_write                                       (i_ch2_lavmm_write),
    .x_std_sm_ux_toolbox_0__i_ch3_lavmm_clk                                         (i_ch3_lavmm_clk),
    .x_std_sm_ux_toolbox_0__i_ch3_lavmm_read                                        (i_ch3_lavmm_read),
    .x_std_sm_ux_toolbox_0__i_ch3_lavmm_rstn                                        (i_ch3_lavmm_rstn),
    .x_std_sm_ux_toolbox_0__i_ch3_lavmm_write                                       (i_ch3_lavmm_write),
    .x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch0                         (i_dat_pcs_measlatrndtripbit_ch0),
    .x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch1                         (i_dat_pcs_measlatrndtripbit_ch1),
    .x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch2                         (i_dat_pcs_measlatrndtripbit_ch2),
    .x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch3                         (i_dat_pcs_measlatrndtripbit_ch3),
    .x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch0                                   (i_ft_rx_sclk_sync_ch0),
    .x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch1                                   (i_ft_rx_sclk_sync_ch1),
    .x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch2                                   (i_ft_rx_sclk_sync_ch2),
    .x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch3                                   (i_ft_rx_sclk_sync_ch3),
    .x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch0                                   (i_ft_tx_sclk_sync_ch0),
    .x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch1                                   (i_ft_tx_sclk_sync_ch1),
    .x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch2                                   (i_ft_tx_sclk_sync_ch2),
    .x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch3                                   (i_ft_tx_sclk_sync_ch3),
    .x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch0                                       (i_ick_sclk_rx_ch0),
    .x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch1                                       (i_ick_sclk_rx_ch1),
    .x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch2                                       (i_ick_sclk_rx_ch2),
    .x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch3                                       (i_ick_sclk_rx_ch3),
    .x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch0_a                               (i_octl_pcs_txstatus_ch0_a),
    .x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch1_a                               (i_octl_pcs_txstatus_ch1_a),
    .x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch2_a                               (i_octl_pcs_txstatus_ch2_a),
    .x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch3_a                               (i_octl_pcs_txstatus_ch3_a),
    .x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch0                               (i_rst_ux_rx_pma_rst_n_ch0),
    .x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch1                               (i_rst_ux_rx_pma_rst_n_ch1),
    .x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch2                               (i_rst_ux_rx_pma_rst_n_ch2),
    .x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch3                               (i_rst_ux_rx_pma_rst_n_ch3),
    .x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch0                               (i_rst_ux_tx_pma_rst_n_ch0),
    .x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch1                               (i_rst_ux_tx_pma_rst_n_ch1),
    .x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch2                               (i_rst_ux_tx_pma_rst_n_ch2),
    .x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch3                               (i_rst_ux_tx_pma_rst_n_ch3),
    .x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch0                                (i_sclk_return_sel_rx_ch0),
    .x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch1                                (i_sclk_return_sel_rx_ch1),
    .x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch2                                (i_sclk_return_sel_rx_ch2),
    .x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch3                                (i_sclk_return_sel_rx_ch3),
    .x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch0                                (i_sclk_return_sel_tx_ch0),
    .x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch1                                (i_sclk_return_sel_tx_ch1),
    .x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch2                                (i_sclk_return_sel_tx_ch2),
    .x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch3                                (i_sclk_return_sel_tx_ch3),
    .x_std_sm_ux_toolbox_0__i_tx_dl_ch0_bit                                         (i_tx_dl_ch0_bit),
    .x_std_sm_ux_toolbox_0__i_tx_dl_ch1_bit                                         (i_tx_dl_ch1_bit),
    .x_std_sm_ux_toolbox_0__i_tx_dl_ch2_bit                                         (i_tx_dl_ch2_bit),
    .x_std_sm_ux_toolbox_0__i_tx_dl_ch3_bit                                         (i_tx_dl_ch3_bit),
    .x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0                                     (o_sync_cfg_data_ch0),
    .x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1                                     (o_sync_cfg_data_ch1),
    .x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch2                                     (o_sync_cfg_data_ch2),
    .x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3                                     (o_sync_cfg_data_ch3),
    .x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel                                       (o_ux0_rxuser1_sel),
    .x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel                                       (o_ux0_rxuser2_sel),
    .x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel                                       (o_ux0_txuser1_sel),
    .x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel                                       (o_ux0_txuser2_sel),
    .x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel                                       (o_ux1_rxuser1_sel),
    .x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel                                       (o_ux1_rxuser2_sel),
    .x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel                                       (o_ux1_txuser1_sel),
    .x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel                                       (o_ux1_txuser2_sel),
    .x_std_sm_ux_toolbox_0__o_ux2_rxuser1_sel                                       (o_ux2_rxuser1_sel),
    .x_std_sm_ux_toolbox_0__o_ux2_rxuser2_sel                                       (o_ux2_rxuser2_sel),
    .x_std_sm_ux_toolbox_0__o_ux2_txuser1_sel                                       (o_ux2_txuser1_sel),
    .x_std_sm_ux_toolbox_0__o_ux2_txuser2_sel                                       (o_ux2_txuser2_sel),
    .x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel                                       (o_ux3_rxuser1_sel),
    .x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel                                       (o_ux3_rxuser2_sel),
    .x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel                                       (o_ux3_txuser1_sel),
    .x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel                                       (o_ux3_txuser2_sel),
    .x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0                            (o_sync_interface_control_ch0),
    .x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1                            (o_sync_interface_control_ch1),
    .x_std_sm_ux_toolbox_0__o_sync_interface_control_ch2                            (o_sync_interface_control_ch2),
    .x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3                            (o_sync_interface_control_ch3),
    .x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata                                       (o_ch0_lavmm_rdata),
    .x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata                                       (o_ch1_lavmm_rdata),
    .x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata                                       (o_ch2_lavmm_rdata),
    .x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata                                       (o_ch3_lavmm_rdata),
    .x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc                      (o_q2q_xcvrrc_ux_ux__txstatus_ux_rc),
    .x_std_sm_ux_toolbox_0__o_sync_common_control_ch0                               (o_sync_common_control_ch0),
    .x_std_sm_ux_toolbox_0__o_sync_common_control_ch1                               (o_sync_common_control_ch1),
    .x_std_sm_ux_toolbox_0__o_sync_common_control_ch2                               (o_sync_common_control_ch2),
    .x_std_sm_ux_toolbox_0__o_sync_common_control_ch3                               (o_sync_common_control_ch3),
    .x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_valid                                 (o_ch0_lavmm_rdata_valid),
    .x_std_sm_ux_toolbox_0__o_ch0_lavmm_waitreq                                     (o_ch0_lavmm_waitreq),
    .x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_valid                                 (o_ch1_lavmm_rdata_valid),
    .x_std_sm_ux_toolbox_0__o_ch1_lavmm_waitreq                                     (o_ch1_lavmm_waitreq),
    .x_std_sm_ux_toolbox_0__o_ch2_lavmm_rdata_valid                                 (o_ch2_lavmm_rdata_valid),
    .x_std_sm_ux_toolbox_0__o_ch2_lavmm_waitreq                                     (o_ch2_lavmm_waitreq),
    .x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_valid                                 (o_ch3_lavmm_rdata_valid),
    .x_std_sm_ux_toolbox_0__o_ch3_lavmm_waitreq                                     (o_ch3_lavmm_waitreq),
    .x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch0                                (o_dat_pcs_measlatbit_ch0),
    .x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch1                                (o_dat_pcs_measlatbit_ch1),
    .x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch2                                (o_dat_pcs_measlatbit_ch2),
    .x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch3                                (o_dat_pcs_measlatbit_ch3),
    .x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch0                                 (o_ft_rx_async_pulse_ch0),
    .x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch1                                 (o_ft_rx_async_pulse_ch1),
    .x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch2                                 (o_ft_rx_async_pulse_ch2),
    .x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch3                                 (o_ft_rx_async_pulse_ch3),
    .x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch0                                 (o_ft_tx_async_pulse_ch0),
    .x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch1                                 (o_ft_tx_async_pulse_ch1),
    .x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch2                                 (o_ft_tx_async_pulse_ch2),
    .x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch3                                 (o_ft_tx_async_pulse_ch3),
    .x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch0_a                               (o_ictl_pcs_txenable_ch0_a),
    .x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch1_a                               (o_ictl_pcs_txenable_ch1_a),
    .x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch2_a                               (o_ictl_pcs_txenable_ch2_a),
    .x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch3_a                               (o_ictl_pcs_txenable_ch3_a),
    .x_std_sm_ux_toolbox_0__o_rx_dl_ch0_bit                                         (o_rx_dl_ch0_bit),
    .x_std_sm_ux_toolbox_0__o_rx_dl_ch1_bit                                         (o_rx_dl_ch1_bit),
    .x_std_sm_ux_toolbox_0__o_rx_dl_ch2_bit                                         (o_rx_dl_ch2_bit),
    .x_std_sm_ux_toolbox_0__o_rx_dl_ch3_bit                                         (o_rx_dl_ch3_bit)
);
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "2VFQJEphUyq8CwC8gsQTzYRiy4CKnFrR8CoPpc7J3IzqCDuq0mHM6K7V2GezThdey82bBMPNbBgDXoriW44Et6j33hxoHnsMU5dCyiGmutmx81l+P7dd/ZZHRzlYw5WTW/WUBsKFIF04NTI3bdb3z9ruzOKjaZWeulfiAYKi1f05itJlxUyPe9iDebXZUNjziA/9KjCM/P0e+uVjXL6IPI9Kd704g3ZM2iG17dIZikx1tHA522pwY6d/F+yChJuhJTw8xmpX4BETgLo0SygihcC2Ll4qwKDNSYntqdBC1J0+15D2RowO8Ubc/Jo8zLH/w7DMfaG+PINikOLUjXABmGP/H82v/fij276I8ccl5YvjPsNdqr0ymsNWDV73/8+ItyNiOIuQes/ikPzh7hLLrVP4KBsUsJLgz/QAQRy6l3jypiaEY/M3qsexBPc/XDCUSFhVybwDtA3ZBIdMOLERTLsEpg3wFelrm/o1t5cG2ygPWGY1XfIiRzA5zn9AirVD0MO6HZlwxZgVfu5dKZDtR576xK6yViZIRc5pgY+KC67ezNVmGCkImm+sEH/ameTBy13z4rFt3uiJI7Q+azqjrqx0rZp/74o18eA/TXKXHRnU/teZDAQy7zUNH1EFZ96wXZn+WOn1F17g8WiNLdno08Bw5q9sWFP0r8/Xzcc40G8hvFjfoaqkKY+iz4krSPSN+5+PVO8hwj5OeW6jemDolJ2EYu/TkUZEgyhQ+FTMWYo6FPlPCBl0lhWIXEiBuVUHcKIp5FrvENkPVg1fDctaJyUqegjfngetQ7MftSNNL+GjDxDp9k2CXWLLM9GcWh+Fyt9SQ5GHrdWtP1FjndZopd3hJzBhhgXgjCoFqWOSqoGns7hMuknSBUAHKo6wXyovgA6hBH3WQJCy5CTd0Rl9maoG2h6HM6OEIql1sPtDUfYkHpM4zjC4RUgTC14IzbO7SZwPKfSZRdFfK3HEJOXkTfgm01MBXOoSN0kO52uhrQBbVqrFzOuXxqmhmsiyi4EH"
`endif