/*
 * system.h - SOPC Builder system and BSP software package information
 *
 * Machine generated for CPU 'nios2' in SOPC Builder design 'main_qsys'
 * SOPC Builder design path: ../../main_qsys.sopcinfo
 *
 * Generated: Sun Jan 19 14:26:35 CST 2025
 */

/*
 * DO NOT MODIFY THIS FILE
 *
 * Changing this file will have subtle consequences
 * which will almost certainly lead to a nonfunctioning
 * system. If you do modify this file, be aware that your
 * changes will be overwritten and lost when this file
 * is generated again.
 *
 * DO NOT MODIFY THIS FILE
 */

/*
 * License Agreement
 *
 * Copyright (c) 2008
 * Altera Corporation, San Jose, California, USA.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * This agreement shall be governed in all respects by the laws of the State
 * of California and by the laws of the United States of America.
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/* Include definitions from linker script generator */
#include "linker.h"


/*
 * CPU configuration
 *
 */

#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x20005820
#define ALT_CPU_CPU_ARCH_NIOS2_R1
#define ALT_CPU_CPU_FREQ 100000000u
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "fast"
#define ALT_CPU_DATA_ADDR_WIDTH 0x1e
#define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000
#define ALT_CPU_DCACHE_LINE_SIZE 32
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_DCACHE_SIZE 2048
#define ALT_CPU_EXCEPTION_ADDR 0x00000020
#define ALT_CPU_FLASH_ACCELERATOR_LINES 0
#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
#define ALT_CPU_FLUSHDA_SUPPORTED
#define ALT_CPU_FREQ 100000000
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1
#define ALT_CPU_HARDWARE_MULX_PRESENT 0
#define ALT_CPU_HAS_DEBUG_CORE 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_HAS_EXTRA_EXCEPTION_INFO
#define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
#define ALT_CPU_HAS_JMPI_INSTRUCTION
#define ALT_CPU_ICACHE_LINE_SIZE 32
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_ICACHE_SIZE 4096
#define ALT_CPU_INITDA_SUPPORTED
#define ALT_CPU_INST_ADDR_WIDTH 0x1e
#define ALT_CPU_NAME "nios2"
#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
#define ALT_CPU_OCI_VERSION 1
#define ALT_CPU_RESET_ADDR 0x00000000


/*
 * CPU configuration (with legacy prefix - don't use these anymore)
 *
 */

#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x20005820
#define NIOS2_CPU_ARCH_NIOS2_R1
#define NIOS2_CPU_FREQ 100000000u
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_DATA_ADDR_WIDTH 0x1e
#define NIOS2_DCACHE_BYPASS_MASK 0x80000000
#define NIOS2_DCACHE_LINE_SIZE 32
#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_SIZE 2048
#define NIOS2_EXCEPTION_ADDR 0x00000020
#define NIOS2_FLASH_ACCELERATOR_LINES 0
#define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0
#define NIOS2_FLUSHDA_SUPPORTED
#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1
#define NIOS2_HARDWARE_MULX_PRESENT 0
#define NIOS2_HAS_DEBUG_CORE 1
#define NIOS2_HAS_DEBUG_STUB
#define NIOS2_HAS_EXTRA_EXCEPTION_INFO
#define NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
#define NIOS2_HAS_JMPI_INSTRUCTION
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_INITDA_SUPPORTED
#define NIOS2_INST_ADDR_WIDTH 0x1e
#define NIOS2_NUM_OF_SHADOW_REG_SETS 0
#define NIOS2_OCI_VERSION 1
#define NIOS2_RESET_ADDR 0x00000000


/*
 * Define for each module class mastered by the CPU
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PERFORMANCE_COUNTER
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SYSID_QSYS
#define __ALTERA_AVALON_TIMER
#define __ALTERA_ETH_TSE
#define __ALTERA_MEM_IF_DDR3_EMIF
#define __ALTERA_MSGDMA
#define __ALTERA_NIOS2_GEN2


/*
 * System configuration
 *
 */

#define ALT_DEVICE_FAMILY "Cyclone V"
#define ALT_ENHANCED_INTERRUPT_API_PRESENT
#define ALT_IRQ_BASE NULL
#define ALT_LOG_PORT "/dev/null"
#define ALT_LOG_PORT_BASE 0x0
#define ALT_LOG_PORT_DEV null
#define ALT_LOG_PORT_TYPE ""
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/peripheral_jtag_uart"
#define ALT_STDERR_BASE 0x200061a8
#define ALT_STDERR_DEV peripheral_jtag_uart
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/peripheral_jtag_uart"
#define ALT_STDIN_BASE 0x200061a8
#define ALT_STDIN_DEV peripheral_jtag_uart
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/peripheral_jtag_uart"
#define ALT_STDOUT_BASE 0x200061a8
#define ALT_STDOUT_DEV peripheral_jtag_uart
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_SYSTEM_NAME "main_qsys"


/*
 * altera_iniche configuration
 *
 */

#define DHCP_CLIENT
#define INCLUDE_TCP
#define INICHE_DEFAULT_IF "NOT_USED"
#define IP_FRAGMENTS


/*
 * ethernet_subsystem_descriptor_memory configuration
 *
 */

#define ALT_MODULE_CLASS_ethernet_subsystem_descriptor_memory altera_avalon_onchip_memory2
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_BASE 0x20002000
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_CONTENTS_INFO ""
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_DUAL_PORT 1
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_GUI_RAM_BLOCK_TYPE "AUTO"
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_INIT_CONTENTS_FILE "main_qsys_ethernet_subsystem_descriptor_memory"
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_INIT_MEM_CONTENT 1
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_INSTANCE_ID "NONE"
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_IRQ -1
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_NAME "/dev/ethernet_subsystem_descriptor_memory"
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_RAM_BLOCK_TYPE "AUTO"
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_SINGLE_CLOCK_OP 0
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_SIZE_MULTIPLE 1
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_SIZE_VALUE 8192
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_SPAN 8192
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_TYPE "altera_avalon_onchip_memory2"
#define ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY_WRITABLE 1


/*
 * ethernet_subsystem_msgdma_rx_csr configuration
 *
 */

#define ALT_MODULE_CLASS_ethernet_subsystem_msgdma_rx_csr altera_msgdma
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_BASE 0x20005460
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_BURST_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_BURST_WRAPPING_SUPPORT 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_CHANNEL_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_CHANNEL_ENABLE_DERIVED 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_CHANNEL_WIDTH 8
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_DATA_FIFO_DEPTH 32
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_DATA_WIDTH 32
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_DESCRIPTOR_FIFO_DEPTH 128
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_DMA_MODE 2
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_ENHANCED_FEATURES 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_ERROR_ENABLE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_ERROR_ENABLE_DERIVED 1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_ERROR_WIDTH 6
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_IRQ -1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_MAX_BURST_COUNT 2
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_MAX_BYTE 524288
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_MAX_STRIDE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_NAME "/dev/ethernet_subsystem_msgdma_rx_csr"
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_PACKET_ENABLE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_PACKET_ENABLE_DERIVED 1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_PREFETCHER_ENABLE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_PROGRAMMABLE_BURST_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_RESPONSE_PORT 2
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_SPAN 32
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_STRIDE_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_STRIDE_ENABLE_DERIVED 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_TRANSFER_TYPE "Aligned Accesses"
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_CSR_TYPE "altera_msgdma"


/*
 * ethernet_subsystem_msgdma_rx_prefetcher_csr configuration
 *
 */

#define ALT_MODULE_CLASS_ethernet_subsystem_msgdma_rx_prefetcher_csr altera_msgdma
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_BASE 0x20005420
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_BURST_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_BURST_WRAPPING_SUPPORT 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_CHANNEL_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_CHANNEL_ENABLE_DERIVED 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_CHANNEL_WIDTH 8
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_DATA_FIFO_DEPTH 32
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_DATA_WIDTH 32
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_DESCRIPTOR_FIFO_DEPTH 128
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_DMA_MODE 2
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_ENHANCED_FEATURES 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_ERROR_ENABLE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_ERROR_ENABLE_DERIVED 1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_ERROR_WIDTH 6
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_IRQ 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_MAX_BURST_COUNT 2
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_MAX_BYTE 524288
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_MAX_STRIDE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_NAME "/dev/ethernet_subsystem_msgdma_rx_prefetcher_csr"
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_PACKET_ENABLE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_PACKET_ENABLE_DERIVED 1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_PREFETCHER_ENABLE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_PROGRAMMABLE_BURST_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_RESPONSE_PORT 2
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_SPAN 32
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_STRIDE_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_STRIDE_ENABLE_DERIVED 0
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_TRANSFER_TYPE "Aligned Accesses"
#define ETHERNET_SUBSYSTEM_MSGDMA_RX_PREFETCHER_CSR_TYPE "altera_msgdma"


/*
 * ethernet_subsystem_msgdma_tx_csr configuration
 *
 */

#define ALT_MODULE_CLASS_ethernet_subsystem_msgdma_tx_csr altera_msgdma
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_BASE 0x20005440
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_BURST_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_BURST_WRAPPING_SUPPORT 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_CHANNEL_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_CHANNEL_ENABLE_DERIVED 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_CHANNEL_WIDTH 8
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_DATA_FIFO_DEPTH 32
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_DATA_WIDTH 32
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_DESCRIPTOR_FIFO_DEPTH 128
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_DMA_MODE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_ENHANCED_FEATURES 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_ERROR_ENABLE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_ERROR_ENABLE_DERIVED 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_ERROR_WIDTH 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_IRQ -1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_MAX_BURST_COUNT 2
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_MAX_BYTE 262144
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_MAX_STRIDE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_NAME "/dev/ethernet_subsystem_msgdma_tx_csr"
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_PACKET_ENABLE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_PACKET_ENABLE_DERIVED 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_PREFETCHER_ENABLE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_PROGRAMMABLE_BURST_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_RESPONSE_PORT 2
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_SPAN 32
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_STRIDE_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_STRIDE_ENABLE_DERIVED 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_TRANSFER_TYPE "Aligned Accesses"
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_CSR_TYPE "altera_msgdma"


/*
 * ethernet_subsystem_msgdma_tx_prefetcher_csr configuration
 *
 */

#define ALT_MODULE_CLASS_ethernet_subsystem_msgdma_tx_prefetcher_csr altera_msgdma
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_BASE 0x20005400
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_BURST_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_BURST_WRAPPING_SUPPORT 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_CHANNEL_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_CHANNEL_ENABLE_DERIVED 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_CHANNEL_WIDTH 8
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_DATA_FIFO_DEPTH 32
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_DATA_WIDTH 32
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_DESCRIPTOR_FIFO_DEPTH 128
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_DMA_MODE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_ENHANCED_FEATURES 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_ERROR_ENABLE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_ERROR_ENABLE_DERIVED 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_ERROR_WIDTH 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_IRQ 2
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_MAX_BURST_COUNT 2
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_MAX_BYTE 262144
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_MAX_STRIDE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_NAME "/dev/ethernet_subsystem_msgdma_tx_prefetcher_csr"
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_PACKET_ENABLE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_PACKET_ENABLE_DERIVED 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_PREFETCHER_ENABLE 1
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_PROGRAMMABLE_BURST_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_RESPONSE_PORT 2
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_SPAN 32
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_STRIDE_ENABLE 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_STRIDE_ENABLE_DERIVED 0
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_TRANSFER_TYPE "Aligned Accesses"
#define ETHERNET_SUBSYSTEM_MSGDMA_TX_PREFETCHER_CSR_TYPE "altera_msgdma"


/*
 * ethernet_subsystem_tse_mac configuration
 *
 */

#define ALT_MODULE_CLASS_ethernet_subsystem_tse_mac altera_eth_tse
#define ETHERNET_SUBSYSTEM_TSE_MAC_BASE 0x20005000
#define ETHERNET_SUBSYSTEM_TSE_MAC_ENABLE_MACLITE 0
#define ETHERNET_SUBSYSTEM_TSE_MAC_FIFO_WIDTH 32
#define ETHERNET_SUBSYSTEM_TSE_MAC_IRQ -1
#define ETHERNET_SUBSYSTEM_TSE_MAC_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ETHERNET_SUBSYSTEM_TSE_MAC_IS_MULTICHANNEL_MAC 0
#define ETHERNET_SUBSYSTEM_TSE_MAC_MACLITE_GIGE 0
#define ETHERNET_SUBSYSTEM_TSE_MAC_MDIO_SHARED 0
#define ETHERNET_SUBSYSTEM_TSE_MAC_NAME "/dev/ethernet_subsystem_tse_mac"
#define ETHERNET_SUBSYSTEM_TSE_MAC_NUMBER_OF_CHANNEL 1
#define ETHERNET_SUBSYSTEM_TSE_MAC_NUMBER_OF_MAC_MDIO_SHARED 1
#define ETHERNET_SUBSYSTEM_TSE_MAC_PCS 0
#define ETHERNET_SUBSYSTEM_TSE_MAC_PCS_ID 0
#define ETHERNET_SUBSYSTEM_TSE_MAC_PCS_SGMII 0
#define ETHERNET_SUBSYSTEM_TSE_MAC_RECEIVE_FIFO_DEPTH 4096
#define ETHERNET_SUBSYSTEM_TSE_MAC_REGISTER_SHARED 0
#define ETHERNET_SUBSYSTEM_TSE_MAC_RGMII 1
#define ETHERNET_SUBSYSTEM_TSE_MAC_SPAN 1024
#define ETHERNET_SUBSYSTEM_TSE_MAC_TRANSMIT_FIFO_DEPTH 4096
#define ETHERNET_SUBSYSTEM_TSE_MAC_TYPE "altera_eth_tse"
#define ETHERNET_SUBSYSTEM_TSE_MAC_USE_MDIO 1


/*
 * hal configuration
 *
 */

#define ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
#define ALT_MAX_FD 32
#define ALT_SYS_CLK PERIPHERAL_SYS_CLK_TIMER
#define ALT_TIMESTAMP_CLK none


/*
 * peripheral_button_pio configuration
 *
 */

#define ALT_MODULE_CLASS_peripheral_button_pio altera_avalon_pio
#define PERIPHERAL_BUTTON_PIO_BASE 0x20006180
#define PERIPHERAL_BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define PERIPHERAL_BUTTON_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PERIPHERAL_BUTTON_PIO_CAPTURE 1
#define PERIPHERAL_BUTTON_PIO_DATA_WIDTH 4
#define PERIPHERAL_BUTTON_PIO_DO_TEST_BENCH_WIRING 1
#define PERIPHERAL_BUTTON_PIO_DRIVEN_SIM_VALUE 3
#define PERIPHERAL_BUTTON_PIO_EDGE_TYPE "RISING"
#define PERIPHERAL_BUTTON_PIO_FREQ 100000000
#define PERIPHERAL_BUTTON_PIO_HAS_IN 1
#define PERIPHERAL_BUTTON_PIO_HAS_OUT 0
#define PERIPHERAL_BUTTON_PIO_HAS_TRI 0
#define PERIPHERAL_BUTTON_PIO_IRQ 5
#define PERIPHERAL_BUTTON_PIO_IRQ_INTERRUPT_CONTROLLER_ID 0
#define PERIPHERAL_BUTTON_PIO_IRQ_TYPE "EDGE"
#define PERIPHERAL_BUTTON_PIO_NAME "/dev/peripheral_button_pio"
#define PERIPHERAL_BUTTON_PIO_RESET_VALUE 0
#define PERIPHERAL_BUTTON_PIO_SPAN 16
#define PERIPHERAL_BUTTON_PIO_TYPE "altera_avalon_pio"


/*
 * peripheral_high_res_timer configuration
 *
 */

#define ALT_MODULE_CLASS_peripheral_high_res_timer altera_avalon_timer
#define PERIPHERAL_HIGH_RES_TIMER_ALWAYS_RUN 0
#define PERIPHERAL_HIGH_RES_TIMER_BASE 0x20006160
#define PERIPHERAL_HIGH_RES_TIMER_COUNTER_SIZE 32
#define PERIPHERAL_HIGH_RES_TIMER_FIXED_PERIOD 0
#define PERIPHERAL_HIGH_RES_TIMER_FREQ 100000000
#define PERIPHERAL_HIGH_RES_TIMER_IRQ 4
#define PERIPHERAL_HIGH_RES_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0
#define PERIPHERAL_HIGH_RES_TIMER_LOAD_VALUE 999
#define PERIPHERAL_HIGH_RES_TIMER_MULT 1.0E-6
#define PERIPHERAL_HIGH_RES_TIMER_NAME "/dev/peripheral_high_res_timer"
#define PERIPHERAL_HIGH_RES_TIMER_PERIOD 10.0
#define PERIPHERAL_HIGH_RES_TIMER_PERIOD_UNITS "us"
#define PERIPHERAL_HIGH_RES_TIMER_RESET_OUTPUT 0
#define PERIPHERAL_HIGH_RES_TIMER_SNAPSHOT 1
#define PERIPHERAL_HIGH_RES_TIMER_SPAN 32
#define PERIPHERAL_HIGH_RES_TIMER_TICKS_PER_SEC 100000
#define PERIPHERAL_HIGH_RES_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define PERIPHERAL_HIGH_RES_TIMER_TYPE "altera_avalon_timer"


/*
 * peripheral_jtag_uart configuration
 *
 */

#define ALT_MODULE_CLASS_peripheral_jtag_uart altera_avalon_jtag_uart
#define PERIPHERAL_JTAG_UART_BASE 0x200061a8
#define PERIPHERAL_JTAG_UART_IRQ 3
#define PERIPHERAL_JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
#define PERIPHERAL_JTAG_UART_NAME "/dev/peripheral_jtag_uart"
#define PERIPHERAL_JTAG_UART_READ_DEPTH 64
#define PERIPHERAL_JTAG_UART_READ_THRESHOLD 8
#define PERIPHERAL_JTAG_UART_SPAN 8
#define PERIPHERAL_JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define PERIPHERAL_JTAG_UART_WRITE_DEPTH 64
#define PERIPHERAL_JTAG_UART_WRITE_THRESHOLD 8


/*
 * peripheral_led_pio configuration
 *
 */

#define ALT_MODULE_CLASS_peripheral_led_pio altera_avalon_pio
#define PERIPHERAL_LED_PIO_BASE 0x20006190
#define PERIPHERAL_LED_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define PERIPHERAL_LED_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PERIPHERAL_LED_PIO_CAPTURE 0
#define PERIPHERAL_LED_PIO_DATA_WIDTH 4
#define PERIPHERAL_LED_PIO_DO_TEST_BENCH_WIRING 0
#define PERIPHERAL_LED_PIO_DRIVEN_SIM_VALUE 0
#define PERIPHERAL_LED_PIO_EDGE_TYPE "NONE"
#define PERIPHERAL_LED_PIO_FREQ 100000000
#define PERIPHERAL_LED_PIO_HAS_IN 0
#define PERIPHERAL_LED_PIO_HAS_OUT 1
#define PERIPHERAL_LED_PIO_HAS_TRI 0
#define PERIPHERAL_LED_PIO_IRQ -1
#define PERIPHERAL_LED_PIO_IRQ_INTERRUPT_CONTROLLER_ID -1
#define PERIPHERAL_LED_PIO_IRQ_TYPE "NONE"
#define PERIPHERAL_LED_PIO_NAME "/dev/peripheral_led_pio"
#define PERIPHERAL_LED_PIO_RESET_VALUE 0
#define PERIPHERAL_LED_PIO_SPAN 16
#define PERIPHERAL_LED_PIO_TYPE "altera_avalon_pio"


/*
 * peripheral_performance_counter configuration
 *
 */

#define ALT_MODULE_CLASS_peripheral_performance_counter altera_avalon_performance_counter
#define PERIPHERAL_PERFORMANCE_COUNTER_BASE 0x20006100
#define PERIPHERAL_PERFORMANCE_COUNTER_HOW_MANY_SECTIONS 3
#define PERIPHERAL_PERFORMANCE_COUNTER_IRQ -1
#define PERIPHERAL_PERFORMANCE_COUNTER_IRQ_INTERRUPT_CONTROLLER_ID -1
#define PERIPHERAL_PERFORMANCE_COUNTER_NAME "/dev/peripheral_performance_counter"
#define PERIPHERAL_PERFORMANCE_COUNTER_SPAN 64
#define PERIPHERAL_PERFORMANCE_COUNTER_TYPE "altera_avalon_performance_counter"


/*
 * peripheral_sys_clk_timer configuration
 *
 */

#define ALT_MODULE_CLASS_peripheral_sys_clk_timer altera_avalon_timer
#define PERIPHERAL_SYS_CLK_TIMER_ALWAYS_RUN 0
#define PERIPHERAL_SYS_CLK_TIMER_BASE 0x20006140
#define PERIPHERAL_SYS_CLK_TIMER_COUNTER_SIZE 32
#define PERIPHERAL_SYS_CLK_TIMER_FIXED_PERIOD 0
#define PERIPHERAL_SYS_CLK_TIMER_FREQ 100000000
#define PERIPHERAL_SYS_CLK_TIMER_IRQ 1
#define PERIPHERAL_SYS_CLK_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0
#define PERIPHERAL_SYS_CLK_TIMER_LOAD_VALUE 999999
#define PERIPHERAL_SYS_CLK_TIMER_MULT 0.001
#define PERIPHERAL_SYS_CLK_TIMER_NAME "/dev/peripheral_sys_clk_timer"
#define PERIPHERAL_SYS_CLK_TIMER_PERIOD 10.0
#define PERIPHERAL_SYS_CLK_TIMER_PERIOD_UNITS "ms"
#define PERIPHERAL_SYS_CLK_TIMER_RESET_OUTPUT 0
#define PERIPHERAL_SYS_CLK_TIMER_SNAPSHOT 1
#define PERIPHERAL_SYS_CLK_TIMER_SPAN 32
#define PERIPHERAL_SYS_CLK_TIMER_TICKS_PER_SEC 100
#define PERIPHERAL_SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define PERIPHERAL_SYS_CLK_TIMER_TYPE "altera_avalon_timer"


/*
 * sdram configuration
 *
 */

#define ALT_MODULE_CLASS_sdram altera_mem_if_ddr3_emif
#define SDRAM_BASE 0x0
#define SDRAM_IRQ -1
#define SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SDRAM_NAME "/dev/sdram"
#define SDRAM_SPAN 536870912
#define SDRAM_TYPE "altera_mem_if_ddr3_emif"


/*
 * sysid_qsys_0 configuration
 *
 */

#define ALT_MODULE_CLASS_sysid_qsys_0 altera_avalon_sysid_qsys
#define SYSID_QSYS_0_BASE 0x20006208
#define SYSID_QSYS_0_ID 0
#define SYSID_QSYS_0_IRQ -1
#define SYSID_QSYS_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SYSID_QSYS_0_NAME "/dev/sysid_qsys_0"
#define SYSID_QSYS_0_SPAN 8
#define SYSID_QSYS_0_TIMESTAMP 1737078964
#define SYSID_QSYS_0_TYPE "altera_avalon_sysid_qsys"


/*
 * ucosii configuration
 *
 */

#define OS_ARG_CHK_EN 1
#define OS_CPU_HOOKS_EN 1
#define OS_DEBUG_EN 1
#define OS_EVENT_NAME_SIZE 32
#define OS_FLAGS_NBITS 16
#define OS_FLAG_ACCEPT_EN 1
#define OS_FLAG_DEL_EN 1
#define OS_FLAG_EN 1
#define OS_FLAG_NAME_SIZE 32
#define OS_FLAG_QUERY_EN 1
#define OS_FLAG_WAIT_CLR_EN 1
#define OS_LOWEST_PRIO 20
#define OS_MAX_EVENTS 60
#define OS_MAX_FLAGS 20
#define OS_MAX_MEM_PART 60
#define OS_MAX_QS 20
#define OS_MAX_TASKS 10
#define OS_MBOX_ACCEPT_EN 1
#define OS_MBOX_DEL_EN 1
#define OS_MBOX_EN 1
#define OS_MBOX_POST_EN 1
#define OS_MBOX_POST_OPT_EN 1
#define OS_MBOX_QUERY_EN 1
#define OS_MEM_EN 1
#define OS_MEM_NAME_SIZE 32
#define OS_MEM_QUERY_EN 1
#define OS_MUTEX_ACCEPT_EN 1
#define OS_MUTEX_DEL_EN 1
#define OS_MUTEX_EN 1
#define OS_MUTEX_QUERY_EN 1
#define OS_Q_ACCEPT_EN 1
#define OS_Q_DEL_EN 1
#define OS_Q_EN 1
#define OS_Q_FLUSH_EN 1
#define OS_Q_POST_EN 1
#define OS_Q_POST_FRONT_EN 1
#define OS_Q_POST_OPT_EN 1
#define OS_Q_QUERY_EN 1
#define OS_SCHED_LOCK_EN 1
#define OS_SEM_ACCEPT_EN 1
#define OS_SEM_DEL_EN 1
#define OS_SEM_EN 1
#define OS_SEM_QUERY_EN 1
#define OS_SEM_SET_EN 1
#define OS_TASK_CHANGE_PRIO_EN 1
#define OS_TASK_CREATE_EN 1
#define OS_TASK_CREATE_EXT_EN 1
#define OS_TASK_DEL_EN 1
#define OS_TASK_IDLE_STK_SIZE 512
#define OS_TASK_NAME_SIZE 32
#define OS_TASK_PROFILE_EN 1
#define OS_TASK_QUERY_EN 1
#define OS_TASK_STAT_EN 1
#define OS_TASK_STAT_STK_CHK_EN 1
#define OS_TASK_STAT_STK_SIZE 512
#define OS_TASK_SUSPEND_EN 1
#define OS_TASK_SW_HOOK_EN 1
#define OS_TASK_TMR_PRIO 0
#define OS_TASK_TMR_STK_SIZE 512
#define OS_THREAD_SAFE_NEWLIB 1
#define OS_TICKS_PER_SEC PERIPHERAL_SYS_CLK_TIMER_TICKS_PER_SEC
#define OS_TICK_STEP_EN 1
#define OS_TIME_DLY_HMSM_EN 1
#define OS_TIME_DLY_RESUME_EN 1
#define OS_TIME_GET_SET_EN 1
#define OS_TIME_TICK_HOOK_EN 1
#define OS_TMR_CFG_MAX 16
#define OS_TMR_CFG_NAME_SIZE 16
#define OS_TMR_CFG_TICKS_PER_SEC 10
#define OS_TMR_CFG_WHEEL_SIZE 2
#define OS_TMR_EN 0

#endif /* __SYSTEM_H_ */
