// main_qsys_peripheral.v

// Generated using ACDS version 18.1 625

`timescale 1 ps / 1 ps
module main_qsys_peripheral (
		input  wire [3:0]  button_pio_external_connection_export, // button_pio_external_connection.export
		output wire        button_pio_irq_irq,                    //                 button_pio_irq.irq
		output wire        high_res_timer_irq_irq,                //             high_res_timer_irq.irq
		output wire        jtag_uart_irq_irq,                     //                  jtag_uart_irq.irq
		output wire [3:0]  led_pio_external_connection_export,    //    led_pio_external_connection.export
		output wire        peripheral_bridge_s0_waitrequest,      //           peripheral_bridge_s0.waitrequest
		output wire [31:0] peripheral_bridge_s0_readdata,         //                               .readdata
		output wire        peripheral_bridge_s0_readdatavalid,    //                               .readdatavalid
		input  wire [0:0]  peripheral_bridge_s0_burstcount,       //                               .burstcount
		input  wire [31:0] peripheral_bridge_s0_writedata,        //                               .writedata
		input  wire [7:0]  peripheral_bridge_s0_address,          //                               .address
		input  wire        peripheral_bridge_s0_write,            //                               .write
		input  wire        peripheral_bridge_s0_read,             //                               .read
		input  wire [3:0]  peripheral_bridge_s0_byteenable,       //                               .byteenable
		input  wire        peripheral_bridge_s0_debugaccess,      //                               .debugaccess
		input  wire        peripheral_subsys_clk_in_clk,          //       peripheral_subsys_clk_in.clk
		input  wire        peripheral_subsys_reset_in_reset_n,    //     peripheral_subsys_reset_in.reset_n
		output wire        sys_clk_timer_irq_irq                  //              sys_clk_timer_irq.irq
	);

	wire         peripheral_bridge_m0_waitrequest;                                  // mm_interconnect_0:peripheral_bridge_m0_waitrequest -> peripheral_bridge:m0_waitrequest
	wire  [31:0] peripheral_bridge_m0_readdata;                                     // mm_interconnect_0:peripheral_bridge_m0_readdata -> peripheral_bridge:m0_readdata
	wire         peripheral_bridge_m0_debugaccess;                                  // peripheral_bridge:m0_debugaccess -> mm_interconnect_0:peripheral_bridge_m0_debugaccess
	wire   [7:0] peripheral_bridge_m0_address;                                      // peripheral_bridge:m0_address -> mm_interconnect_0:peripheral_bridge_m0_address
	wire         peripheral_bridge_m0_read;                                         // peripheral_bridge:m0_read -> mm_interconnect_0:peripheral_bridge_m0_read
	wire   [3:0] peripheral_bridge_m0_byteenable;                                   // peripheral_bridge:m0_byteenable -> mm_interconnect_0:peripheral_bridge_m0_byteenable
	wire         peripheral_bridge_m0_readdatavalid;                                // mm_interconnect_0:peripheral_bridge_m0_readdatavalid -> peripheral_bridge:m0_readdatavalid
	wire  [31:0] peripheral_bridge_m0_writedata;                                    // peripheral_bridge:m0_writedata -> mm_interconnect_0:peripheral_bridge_m0_writedata
	wire         peripheral_bridge_m0_write;                                        // peripheral_bridge:m0_write -> mm_interconnect_0:peripheral_bridge_m0_write
	wire   [0:0] peripheral_bridge_m0_burstcount;                                   // peripheral_bridge:m0_burstcount -> mm_interconnect_0:peripheral_bridge_m0_burstcount
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect;          // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
	wire  [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata;            // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest;         // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
	wire   [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address;             // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_read;                // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_write;               // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
	wire  [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata;           // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
	wire  [31:0] mm_interconnect_0_performance_counter_control_slave_readdata;      // performance_counter:readdata -> mm_interconnect_0:performance_counter_control_slave_readdata
	wire   [3:0] mm_interconnect_0_performance_counter_control_slave_address;       // mm_interconnect_0:performance_counter_control_slave_address -> performance_counter:address
	wire         mm_interconnect_0_performance_counter_control_slave_begintransfer; // mm_interconnect_0:performance_counter_control_slave_begintransfer -> performance_counter:begintransfer
	wire         mm_interconnect_0_performance_counter_control_slave_write;         // mm_interconnect_0:performance_counter_control_slave_write -> performance_counter:write
	wire  [31:0] mm_interconnect_0_performance_counter_control_slave_writedata;     // mm_interconnect_0:performance_counter_control_slave_writedata -> performance_counter:writedata
	wire         mm_interconnect_0_sys_clk_timer_s1_chipselect;                     // mm_interconnect_0:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect
	wire  [15:0] mm_interconnect_0_sys_clk_timer_s1_readdata;                       // sys_clk_timer:readdata -> mm_interconnect_0:sys_clk_timer_s1_readdata
	wire   [2:0] mm_interconnect_0_sys_clk_timer_s1_address;                        // mm_interconnect_0:sys_clk_timer_s1_address -> sys_clk_timer:address
	wire         mm_interconnect_0_sys_clk_timer_s1_write;                          // mm_interconnect_0:sys_clk_timer_s1_write -> sys_clk_timer:write_n
	wire  [15:0] mm_interconnect_0_sys_clk_timer_s1_writedata;                      // mm_interconnect_0:sys_clk_timer_s1_writedata -> sys_clk_timer:writedata
	wire         mm_interconnect_0_high_res_timer_s1_chipselect;                    // mm_interconnect_0:high_res_timer_s1_chipselect -> high_res_timer:chipselect
	wire  [15:0] mm_interconnect_0_high_res_timer_s1_readdata;                      // high_res_timer:readdata -> mm_interconnect_0:high_res_timer_s1_readdata
	wire   [2:0] mm_interconnect_0_high_res_timer_s1_address;                       // mm_interconnect_0:high_res_timer_s1_address -> high_res_timer:address
	wire         mm_interconnect_0_high_res_timer_s1_write;                         // mm_interconnect_0:high_res_timer_s1_write -> high_res_timer:write_n
	wire  [15:0] mm_interconnect_0_high_res_timer_s1_writedata;                     // mm_interconnect_0:high_res_timer_s1_writedata -> high_res_timer:writedata
	wire         mm_interconnect_0_button_pio_s1_chipselect;                        // mm_interconnect_0:button_pio_s1_chipselect -> button_pio:chipselect
	wire  [31:0] mm_interconnect_0_button_pio_s1_readdata;                          // button_pio:readdata -> mm_interconnect_0:button_pio_s1_readdata
	wire   [1:0] mm_interconnect_0_button_pio_s1_address;                           // mm_interconnect_0:button_pio_s1_address -> button_pio:address
	wire         mm_interconnect_0_button_pio_s1_write;                             // mm_interconnect_0:button_pio_s1_write -> button_pio:write_n
	wire  [31:0] mm_interconnect_0_button_pio_s1_writedata;                         // mm_interconnect_0:button_pio_s1_writedata -> button_pio:writedata
	wire         mm_interconnect_0_led_pio_s1_chipselect;                           // mm_interconnect_0:led_pio_s1_chipselect -> led_pio:chipselect
	wire  [31:0] mm_interconnect_0_led_pio_s1_readdata;                             // led_pio:readdata -> mm_interconnect_0:led_pio_s1_readdata
	wire   [1:0] mm_interconnect_0_led_pio_s1_address;                              // mm_interconnect_0:led_pio_s1_address -> led_pio:address
	wire         mm_interconnect_0_led_pio_s1_write;                                // mm_interconnect_0:led_pio_s1_write -> led_pio:write_n
	wire  [31:0] mm_interconnect_0_led_pio_s1_writedata;                            // mm_interconnect_0:led_pio_s1_writedata -> led_pio:writedata
	wire         rst_controller_reset_out_reset;                                    // rst_controller:reset_out -> [button_pio:reset_n, high_res_timer:reset_n, jtag_uart:rst_n, led_pio:reset_n, mm_interconnect_0:peripheral_bridge_reset_reset_bridge_in_reset_reset, performance_counter:reset_n, peripheral_bridge:reset, sys_clk_timer:reset_n]

	main_qsys_peripheral_button_pio button_pio (
		.clk        (peripheral_subsys_clk_in_clk),               //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),            //               reset.reset_n
		.address    (mm_interconnect_0_button_pio_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_button_pio_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_button_pio_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_button_pio_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_button_pio_s1_readdata),   //                    .readdata
		.in_port    (button_pio_external_connection_export),      // external_connection.export
		.irq        (button_pio_irq_irq)                          //                 irq.irq
	);

	main_qsys_peripheral_high_res_timer high_res_timer (
		.clk        (peripheral_subsys_clk_in_clk),                   //   clk.clk
		.reset_n    (~rst_controller_reset_out_reset),                // reset.reset_n
		.address    (mm_interconnect_0_high_res_timer_s1_address),    //    s1.address
		.writedata  (mm_interconnect_0_high_res_timer_s1_writedata),  //      .writedata
		.readdata   (mm_interconnect_0_high_res_timer_s1_readdata),   //      .readdata
		.chipselect (mm_interconnect_0_high_res_timer_s1_chipselect), //      .chipselect
		.write_n    (~mm_interconnect_0_high_res_timer_s1_write),     //      .write_n
		.irq        (high_res_timer_irq_irq)                          //   irq.irq
	);

	main_qsys_peripheral_jtag_uart jtag_uart (
		.clk            (peripheral_subsys_clk_in_clk),                              //               clk.clk
		.rst_n          (~rst_controller_reset_out_reset),                           //             reset.reset_n
		.av_chipselect  (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect),  // avalon_jtag_slave.chipselect
		.av_address     (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address),     //                  .address
		.av_read_n      (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read),       //                  .read_n
		.av_readdata    (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata),    //                  .readdata
		.av_write_n     (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write),      //                  .write_n
		.av_writedata   (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata),   //                  .writedata
		.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), //                  .waitrequest
		.av_irq         (jtag_uart_irq_irq)                                          //               irq.irq
	);

	main_qsys_peripheral_led_pio led_pio (
		.clk        (peripheral_subsys_clk_in_clk),            //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),         //               reset.reset_n
		.address    (mm_interconnect_0_led_pio_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_led_pio_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_led_pio_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_led_pio_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_led_pio_s1_readdata),   //                    .readdata
		.out_port   (led_pio_external_connection_export)       // external_connection.export
	);

	main_qsys_peripheral_performance_counter performance_counter (
		.clk           (peripheral_subsys_clk_in_clk),                                      //           clk.clk
		.reset_n       (~rst_controller_reset_out_reset),                                   //         reset.reset_n
		.address       (mm_interconnect_0_performance_counter_control_slave_address),       // control_slave.address
		.begintransfer (mm_interconnect_0_performance_counter_control_slave_begintransfer), //              .begintransfer
		.readdata      (mm_interconnect_0_performance_counter_control_slave_readdata),      //              .readdata
		.write         (mm_interconnect_0_performance_counter_control_slave_write),         //              .write
		.writedata     (mm_interconnect_0_performance_counter_control_slave_writedata)      //              .writedata
	);

	altera_avalon_mm_bridge #(
		.DATA_WIDTH        (32),
		.SYMBOL_WIDTH      (8),
		.HDL_ADDR_WIDTH    (8),
		.BURSTCOUNT_WIDTH  (1),
		.PIPELINE_COMMAND  (1),
		.PIPELINE_RESPONSE (1)
	) peripheral_bridge (
		.clk              (peripheral_subsys_clk_in_clk),       //   clk.clk
		.reset            (rst_controller_reset_out_reset),     // reset.reset
		.s0_waitrequest   (peripheral_bridge_s0_waitrequest),   //    s0.waitrequest
		.s0_readdata      (peripheral_bridge_s0_readdata),      //      .readdata
		.s0_readdatavalid (peripheral_bridge_s0_readdatavalid), //      .readdatavalid
		.s0_burstcount    (peripheral_bridge_s0_burstcount),    //      .burstcount
		.s0_writedata     (peripheral_bridge_s0_writedata),     //      .writedata
		.s0_address       (peripheral_bridge_s0_address),       //      .address
		.s0_write         (peripheral_bridge_s0_write),         //      .write
		.s0_read          (peripheral_bridge_s0_read),          //      .read
		.s0_byteenable    (peripheral_bridge_s0_byteenable),    //      .byteenable
		.s0_debugaccess   (peripheral_bridge_s0_debugaccess),   //      .debugaccess
		.m0_waitrequest   (peripheral_bridge_m0_waitrequest),   //    m0.waitrequest
		.m0_readdata      (peripheral_bridge_m0_readdata),      //      .readdata
		.m0_readdatavalid (peripheral_bridge_m0_readdatavalid), //      .readdatavalid
		.m0_burstcount    (peripheral_bridge_m0_burstcount),    //      .burstcount
		.m0_writedata     (peripheral_bridge_m0_writedata),     //      .writedata
		.m0_address       (peripheral_bridge_m0_address),       //      .address
		.m0_write         (peripheral_bridge_m0_write),         //      .write
		.m0_read          (peripheral_bridge_m0_read),          //      .read
		.m0_byteenable    (peripheral_bridge_m0_byteenable),    //      .byteenable
		.m0_debugaccess   (peripheral_bridge_m0_debugaccess),   //      .debugaccess
		.s0_response      (),                                   // (terminated)
		.m0_response      (2'b00)                               // (terminated)
	);

	main_qsys_peripheral_sys_clk_timer sys_clk_timer (
		.clk        (peripheral_subsys_clk_in_clk),                  //   clk.clk
		.reset_n    (~rst_controller_reset_out_reset),               // reset.reset_n
		.address    (mm_interconnect_0_sys_clk_timer_s1_address),    //    s1.address
		.writedata  (mm_interconnect_0_sys_clk_timer_s1_writedata),  //      .writedata
		.readdata   (mm_interconnect_0_sys_clk_timer_s1_readdata),   //      .readdata
		.chipselect (mm_interconnect_0_sys_clk_timer_s1_chipselect), //      .chipselect
		.write_n    (~mm_interconnect_0_sys_clk_timer_s1_write),     //      .write_n
		.irq        (sys_clk_timer_irq_irq)                          //   irq.irq
	);

	main_qsys_peripheral_mm_interconnect_0 mm_interconnect_0 (
		.clk_clk_clk                                         (peripheral_subsys_clk_in_clk),                                      //                                       clk_clk.clk
		.peripheral_bridge_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset),                                    // peripheral_bridge_reset_reset_bridge_in_reset.reset
		.peripheral_bridge_m0_address                        (peripheral_bridge_m0_address),                                      //                          peripheral_bridge_m0.address
		.peripheral_bridge_m0_waitrequest                    (peripheral_bridge_m0_waitrequest),                                  //                                              .waitrequest
		.peripheral_bridge_m0_burstcount                     (peripheral_bridge_m0_burstcount),                                   //                                              .burstcount
		.peripheral_bridge_m0_byteenable                     (peripheral_bridge_m0_byteenable),                                   //                                              .byteenable
		.peripheral_bridge_m0_read                           (peripheral_bridge_m0_read),                                         //                                              .read
		.peripheral_bridge_m0_readdata                       (peripheral_bridge_m0_readdata),                                     //                                              .readdata
		.peripheral_bridge_m0_readdatavalid                  (peripheral_bridge_m0_readdatavalid),                                //                                              .readdatavalid
		.peripheral_bridge_m0_write                          (peripheral_bridge_m0_write),                                        //                                              .write
		.peripheral_bridge_m0_writedata                      (peripheral_bridge_m0_writedata),                                    //                                              .writedata
		.peripheral_bridge_m0_debugaccess                    (peripheral_bridge_m0_debugaccess),                                  //                                              .debugaccess
		.button_pio_s1_address                               (mm_interconnect_0_button_pio_s1_address),                           //                                 button_pio_s1.address
		.button_pio_s1_write                                 (mm_interconnect_0_button_pio_s1_write),                             //                                              .write
		.button_pio_s1_readdata                              (mm_interconnect_0_button_pio_s1_readdata),                          //                                              .readdata
		.button_pio_s1_writedata                             (mm_interconnect_0_button_pio_s1_writedata),                         //                                              .writedata
		.button_pio_s1_chipselect                            (mm_interconnect_0_button_pio_s1_chipselect),                        //                                              .chipselect
		.high_res_timer_s1_address                           (mm_interconnect_0_high_res_timer_s1_address),                       //                             high_res_timer_s1.address
		.high_res_timer_s1_write                             (mm_interconnect_0_high_res_timer_s1_write),                         //                                              .write
		.high_res_timer_s1_readdata                          (mm_interconnect_0_high_res_timer_s1_readdata),                      //                                              .readdata
		.high_res_timer_s1_writedata                         (mm_interconnect_0_high_res_timer_s1_writedata),                     //                                              .writedata
		.high_res_timer_s1_chipselect                        (mm_interconnect_0_high_res_timer_s1_chipselect),                    //                                              .chipselect
		.jtag_uart_avalon_jtag_slave_address                 (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address),             //                   jtag_uart_avalon_jtag_slave.address
		.jtag_uart_avalon_jtag_slave_write                   (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write),               //                                              .write
		.jtag_uart_avalon_jtag_slave_read                    (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read),                //                                              .read
		.jtag_uart_avalon_jtag_slave_readdata                (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata),            //                                              .readdata
		.jtag_uart_avalon_jtag_slave_writedata               (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata),           //                                              .writedata
		.jtag_uart_avalon_jtag_slave_waitrequest             (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest),         //                                              .waitrequest
		.jtag_uart_avalon_jtag_slave_chipselect              (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect),          //                                              .chipselect
		.led_pio_s1_address                                  (mm_interconnect_0_led_pio_s1_address),                              //                                    led_pio_s1.address
		.led_pio_s1_write                                    (mm_interconnect_0_led_pio_s1_write),                                //                                              .write
		.led_pio_s1_readdata                                 (mm_interconnect_0_led_pio_s1_readdata),                             //                                              .readdata
		.led_pio_s1_writedata                                (mm_interconnect_0_led_pio_s1_writedata),                            //                                              .writedata
		.led_pio_s1_chipselect                               (mm_interconnect_0_led_pio_s1_chipselect),                           //                                              .chipselect
		.performance_counter_control_slave_address           (mm_interconnect_0_performance_counter_control_slave_address),       //             performance_counter_control_slave.address
		.performance_counter_control_slave_write             (mm_interconnect_0_performance_counter_control_slave_write),         //                                              .write
		.performance_counter_control_slave_readdata          (mm_interconnect_0_performance_counter_control_slave_readdata),      //                                              .readdata
		.performance_counter_control_slave_writedata         (mm_interconnect_0_performance_counter_control_slave_writedata),     //                                              .writedata
		.performance_counter_control_slave_begintransfer     (mm_interconnect_0_performance_counter_control_slave_begintransfer), //                                              .begintransfer
		.sys_clk_timer_s1_address                            (mm_interconnect_0_sys_clk_timer_s1_address),                        //                              sys_clk_timer_s1.address
		.sys_clk_timer_s1_write                              (mm_interconnect_0_sys_clk_timer_s1_write),                          //                                              .write
		.sys_clk_timer_s1_readdata                           (mm_interconnect_0_sys_clk_timer_s1_readdata),                       //                                              .readdata
		.sys_clk_timer_s1_writedata                          (mm_interconnect_0_sys_clk_timer_s1_writedata),                      //                                              .writedata
		.sys_clk_timer_s1_chipselect                         (mm_interconnect_0_sys_clk_timer_s1_chipselect)                      //                                              .chipselect
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~peripheral_subsys_reset_in_reset_n), // reset_in0.reset
		.clk            (peripheral_subsys_clk_in_clk),        //       clk.clk
		.reset_out      (rst_controller_reset_out_reset),      // reset_out.reset
		.reset_req      (),                                    // (terminated)
		.reset_req_in0  (1'b0),                                // (terminated)
		.reset_in1      (1'b0),                                // (terminated)
		.reset_req_in1  (1'b0),                                // (terminated)
		.reset_in2      (1'b0),                                // (terminated)
		.reset_req_in2  (1'b0),                                // (terminated)
		.reset_in3      (1'b0),                                // (terminated)
		.reset_req_in3  (1'b0),                                // (terminated)
		.reset_in4      (1'b0),                                // (terminated)
		.reset_req_in4  (1'b0),                                // (terminated)
		.reset_in5      (1'b0),                                // (terminated)
		.reset_req_in5  (1'b0),                                // (terminated)
		.reset_in6      (1'b0),                                // (terminated)
		.reset_req_in6  (1'b0),                                // (terminated)
		.reset_in7      (1'b0),                                // (terminated)
		.reset_req_in7  (1'b0),                                // (terminated)
		.reset_in8      (1'b0),                                // (terminated)
		.reset_req_in8  (1'b0),                                // (terminated)
		.reset_in9      (1'b0),                                // (terminated)
		.reset_req_in9  (1'b0),                                // (terminated)
		.reset_in10     (1'b0),                                // (terminated)
		.reset_req_in10 (1'b0),                                // (terminated)
		.reset_in11     (1'b0),                                // (terminated)
		.reset_req_in11 (1'b0),                                // (terminated)
		.reset_in12     (1'b0),                                // (terminated)
		.reset_req_in12 (1'b0),                                // (terminated)
		.reset_in13     (1'b0),                                // (terminated)
		.reset_req_in13 (1'b0),                                // (terminated)
		.reset_in14     (1'b0),                                // (terminated)
		.reset_req_in14 (1'b0),                                // (terminated)
		.reset_in15     (1'b0),                                // (terminated)
		.reset_req_in15 (1'b0)                                 // (terminated)
	);

endmodule
