
module main_qsys (
	clk_clk,
	ddr3_mem_a,
	ddr3_mem_ba,
	ddr3_mem_ck,
	ddr3_mem_ck_n,
	ddr3_mem_cke,
	ddr3_mem_cs_n,
	ddr3_mem_dm,
	ddr3_mem_ras_n,
	ddr3_mem_cas_n,
	ddr3_mem_we_n,
	ddr3_mem_reset_n,
	ddr3_mem_dq,
	ddr3_mem_dqs,
	ddr3_mem_dqs_n,
	ddr3_mem_odt,
	enet_125m_clk,
	enet_25m_clk,
	mac_mdio_mdc,
	mac_mdio_mdio_in,
	mac_mdio_mdio_out,
	mac_mdio_mdio_oen,
	mac_misc_xon_gen,
	mac_misc_xoff_gen,
	mac_misc_ff_tx_crc_fwd,
	mac_misc_ff_tx_septy,
	mac_misc_tx_ff_uflow,
	mac_misc_ff_tx_a_full,
	mac_misc_ff_tx_a_empty,
	mac_misc_rx_err_stat,
	mac_misc_rx_frm_type,
	mac_misc_ff_rx_dsav,
	mac_misc_ff_rx_a_full,
	mac_misc_ff_rx_a_empty,
	mac_rgmii_rgmii_in,
	mac_rgmii_rgmii_out,
	mac_rgmii_rx_control,
	mac_rgmii_tx_control,
	mac_status_set_10,
	mac_status_set_1000,
	mac_status_eth_mode,
	mac_status_ena_10,
	oct_rzqin,
	reset_reset_n,
	rx_clock_clk,
	sdram_status_local_init_done,
	sdram_status_local_cal_success,
	sdram_status_local_cal_fail,
	tx_clock_clk);	

	input		clk_clk;
	output	[14:0]	ddr3_mem_a;
	output	[2:0]	ddr3_mem_ba;
	output	[0:0]	ddr3_mem_ck;
	output	[0:0]	ddr3_mem_ck_n;
	output	[0:0]	ddr3_mem_cke;
	output	[0:0]	ddr3_mem_cs_n;
	output	[1:0]	ddr3_mem_dm;
	output	[0:0]	ddr3_mem_ras_n;
	output	[0:0]	ddr3_mem_cas_n;
	output	[0:0]	ddr3_mem_we_n;
	output		ddr3_mem_reset_n;
	inout	[15:0]	ddr3_mem_dq;
	inout	[1:0]	ddr3_mem_dqs;
	inout	[1:0]	ddr3_mem_dqs_n;
	output	[0:0]	ddr3_mem_odt;
	output		enet_125m_clk;
	output		enet_25m_clk;
	output		mac_mdio_mdc;
	input		mac_mdio_mdio_in;
	output		mac_mdio_mdio_out;
	output		mac_mdio_mdio_oen;
	input		mac_misc_xon_gen;
	input		mac_misc_xoff_gen;
	input		mac_misc_ff_tx_crc_fwd;
	output		mac_misc_ff_tx_septy;
	output		mac_misc_tx_ff_uflow;
	output		mac_misc_ff_tx_a_full;
	output		mac_misc_ff_tx_a_empty;
	output	[17:0]	mac_misc_rx_err_stat;
	output	[3:0]	mac_misc_rx_frm_type;
	output		mac_misc_ff_rx_dsav;
	output		mac_misc_ff_rx_a_full;
	output		mac_misc_ff_rx_a_empty;
	input	[3:0]	mac_rgmii_rgmii_in;
	output	[3:0]	mac_rgmii_rgmii_out;
	input		mac_rgmii_rx_control;
	output		mac_rgmii_tx_control;
	input		mac_status_set_10;
	input		mac_status_set_1000;
	output		mac_status_eth_mode;
	output		mac_status_ena_10;
	input		oct_rzqin;
	input		reset_reset_n;
	input		rx_clock_clk;
	output		sdram_status_local_init_done;
	output		sdram_status_local_cal_success;
	output		sdram_status_local_cal_fail;
	input		tx_clock_clk;
endmodule
