# PIN MAP for core < main_qsys_sdram_p0 >
#
# Generated by main_qsys_sdram_p0_pin_assignments.tcl
#
# This file is for reference only and is not used by Quartus Prime
#

INSTANCE: u0|sdram
DQS: {ddr3_fpga_dqs_p[0]} {ddr3_fpga_dqs_p[1]}
DQSn: {ddr3_fpga_dqs_n[0]} {ddr3_fpga_dqs_n[1]}
DQ: {{ddr3_fpga_dq[0]} {ddr3_fpga_dq[1]} {ddr3_fpga_dq[2]} {ddr3_fpga_dq[3]} {ddr3_fpga_dq[4]} {ddr3_fpga_dq[5]} {ddr3_fpga_dq[6]} {ddr3_fpga_dq[7]}} {{ddr3_fpga_dq[8]} {ddr3_fpga_dq[9]} {ddr3_fpga_dq[10]} {ddr3_fpga_dq[11]} {ddr3_fpga_dq[12]} {ddr3_fpga_dq[13]} {ddr3_fpga_dq[14]} {ddr3_fpga_dq[15]}}
DM {ddr3_fpga_dm[0]} {ddr3_fpga_dm[1]}
CK: ddr3_fpga_clk_p
CKn: ddr3_fpga_clk_n
ADD: {ddr3_fpga_a[0]} {ddr3_fpga_a[10]} {ddr3_fpga_a[11]} {ddr3_fpga_a[12]} {ddr3_fpga_a[13]} {ddr3_fpga_a[14]} {ddr3_fpga_a[1]} {ddr3_fpga_a[2]} {ddr3_fpga_a[3]} {ddr3_fpga_a[4]} {ddr3_fpga_a[5]} {ddr3_fpga_a[6]} {ddr3_fpga_a[7]} {ddr3_fpga_a[8]} {ddr3_fpga_a[9]}
CMD: ddr3_fpga_csn ddr3_fpga_wen ddr3_fpga_rasn ddr3_fpga_casn ddr3_fpga_odt ddr3_fpga_cke
RESET: ddr3_fpga_resetn
BA: {ddr3_fpga_ba[0]} {ddr3_fpga_ba[1]} {ddr3_fpga_ba[2]}
REF CLK: sys_clk
PLL AFI: u0|sdram|pll0|pll1~PLL_OUTPUT_COUNTER|divclk
PLL AFI PHY: u0|sdram|pll0|pll1_phy~PLL_OUTPUT_COUNTER|divclk
PLL CK: u0|sdram|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk
PLL DQ WRITE: u0|sdram|pll0|pll3~PLL_OUTPUT_COUNTER|divclk
PLL WRITE: u0|sdram|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk
PLL AC: u0|sdram|pll0|pll4~PLL_OUTPUT_COUNTER|divclk
PLL AVL: u0|sdram|pll0|pll6~PLL_OUTPUT_COUNTER|divclk
PLL CONFIG: u0|sdram|pll0|pll7~PLL_OUTPUT_COUNTER|divclk
DQS_IN_CLOCK DQS_PIN (0): ddr3_fpga_dqs_p[0]
DQS_IN_CLOCK DQS_SHIFTED_PIN (0): u0|sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (0): u0|sdram|div_clock_0
DQS_IN_CLOCK DIV_PIN (0): u0|sdram|p0|umemphy|uread_datapath|read_capture_clk_div2[0]
DQS_IN_CLOCK DQS_PIN (1): ddr3_fpga_dqs_p[1]
DQS_IN_CLOCK DQS_SHIFTED_PIN (1): u0|sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (1): u0|sdram|div_clock_1
DQS_IN_CLOCK DIV_PIN (1): u0|sdram|p0|umemphy|uread_datapath|read_capture_clk_div2[1]
DQS_OUT_CLOCK SRC (0): u0|sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (0): ddr3_fpga_dqs_p[0]
DQS_OUT_CLOCK DM (0): ddr3_fpga_dm[0]
DQS_OUT_CLOCK SRC (1): u0|sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (1): ddr3_fpga_dqs_p[1]
DQS_OUT_CLOCK DM (1): ddr3_fpga_dm[1]
DQSN_OUT_CLOCK SRC (0): u0|sdram|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (0): ddr3_fpga_dqs_n[0]
DQSN_OUT_CLOCK DM (0): ddr3_fpga_dm[0]
DQSN_OUT_CLOCK SRC (1): u0|sdram|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (1): ddr3_fpga_dqs_n[1]
DQSN_OUT_CLOCK DM (1): ddr3_fpga_dm[1]
READ CAPTURE DDIO: {*:u0|*:sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:u0|*:sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}
AFI RESET REGISTERS: *:u0|*:sdram|*:p0|*:umemphy|*:ureset|*:ureset_afi_clk|reset_reg[3]
SEQ  RESET REGISTERS: *:u0|*:sdram|*:s0|*
SYNCHRONIZERS: *:u0|*:sdram|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].seq_read_fifo_reset_sync
SYNCHRONIZATION FIFO WRITE ADDRESS REGISTERS: *:u0|*:sdram|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].read_subgroup[*].wraddress[*]
SYNCHRONIZATION FIFO WRITE REGISTERS: *:u0|*:sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|*INPUT_DFF*
SYNCHRONIZATION FIFO READ REGISTERS: *:u0|*:sdram|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|dout[*]

#
# END OF INSTANCE: u0|sdram

