//--------------------------------------------------------------------------//
// Title:       golden_top.v                                                //
// Rev:         Rev 5                                                       //
// Created:     July 22, 2015                                             //
//--------------------------------------------------------------------------//
// Description: Cyclone V SX SoC pinout and IO Standard example design      //              					                        //
//--------------------------------------------------------------------------//
// Revision History:                                                        //
// Rev 0:       1st cut                                                      //
//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
//Copyright 2012 Altera Corporation. All rights reserved.  Altera products  
//are protected under numerous U.S. and foreign patents, maskwork rights,     
//copyrights and other intellectual property laws.                            
//                                                                            
//This reference design file, and your use thereof, is subject to and         
//governed by the terms and conditions of the applicable Altera Reference     
//Design License Agreement.  By using this reference design file, you         
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//Altera Corporation.  In the event that you do not agree with such terms and 
//conditions, you may not use the reference design file. Please promptly      
//destroy any copies you have made.                                           
//                                                                            
//This reference design file being provided on an "as-is" basis and as an                                             
//accommodation and therefore all warranties, representations or guarantees   
//of any kind (whether express, implied or statutory) including, without      
//limitation, warranties of merchantability, non-infringement, or fitness for 
//a particular purpose, are specifically disclaimed.  By making this          
//reference design file available, Altera expressly does not recommend,       
//suggest or require that this reference design file be used in combination   
//with any other product not provided by Altera.                              
//                                                                            

//`define ENABLE_FPGA_USER_IO
`define ENABLE_FPGA_GPLL_CLK
//`define ENABLE_HPS
//`define ENABLE_DDR3_HPS
//`define ENABLE_DDR3_FPGA
`define ENABLE_FPGA_ETHERNET
//`define ENABLE_SDI_XCVR
`define ENABLE_I2C_FPGA
`define ENABLE_MAX_FPGA
//`define ENABLE_HSMA_XCVR      
//`define ENABLE_HSMA_LVDS
//`define 	ENABLE_HSMA_CMOS 
//`define ENABLE_PCIE_XCVR

module golden_top (
	
   input          clk_osc1,        
   input          clk_osc2,            

//HPS-Reset 3.3 V LVCMOS
   inout          mictor_rstn,         
   input          hps_resetn,          

//HPS-User-IO
   input  [3:0]   user_dipsw_hps,      //1.5V
   output [3:0]   user_led_hps,        //3.3V LVCMOS
   input  [1:0]   user_pb_hps,         //1.5V

//HPS-UART 3.3 V LVCMOS
   input          uart_rx,            
   output         uart_tx,            



//FPGA-DDR3-400Mx32
   output [14:0]  ddr3_fpga_a,         //SSTL15  //Address
   output [2:0]   ddr3_fpga_ba,        //SSTL15  //Bank Address
   output         ddr3_fpga_casn,      //SSTL15  //Column Address Strobe
   output         ddr3_fpga_cke,       //SSTL15  //Clock Enable
   output         ddr3_fpga_clk_n,     //SSTL15  //Diff Clock - Neg
   output         ddr3_fpga_clk_p,     //SSTL15  //Diff Clock - Pos
   output         ddr3_fpga_csn,       //SSTL15  //Chip Select
   output [3:0]   ddr3_fpga_dm,        //SSTL15  //Data Write Mask
   inout  [31:0]  ddr3_fpga_dq,        //SSTL15  //Data Bus
   inout  [3:0]   ddr3_fpga_dqs_n,     //SSTL15  //Diff Data Strobe - Neg
   inout  [3:0]   ddr3_fpga_dqs_p,     //SSTL15  //Diff Data Strobe - Pos
   output         ddr3_fpga_odt,       //SSTL15  //On-Die Termination Enable
   input          ddr3_fpga_rasn,      //SSTL15  //Row Address Strobe
   input          ddr3_fpga_resetn,    //SSTL15  //Reset
   input          ddr3_fpga_wen,       //SSTL15  //Write Enable
   input          ddr3_fpga_rzq        //OCT_rzqin

	

);

	
// Rev A board Ethernet reset can interrupt device configuration, to fix
// enet_dual_reset tristate as input or drive as output to 1
assign	enet_dual_resetn	=	1'b1;	
// FPGA user dipswitches drive user LEDs
//assign   user_led_fpga		=	~user_dipsw_fpga;
// Disable FPGA DDR3 
assign   ddr3_fpga_csn		=	1'b1;	

	main_qsys u0 (
		.clk_clk                        (clk_osc1),                        //          clk.clk
		.reset_reset_n                  (enet_dual_resetn),                  //        reset.reset_n
		
		.pll_ref_clk_clk                (clk_osc1),                //  pll_ref_clk.clk
		.ddr3_mem_a                     (ddr3_fpga_a),                   //       memory.mem_a
		.ddr3_mem_ba                    (ddr3_fpga_ba),                  //             .mem_ba
		.ddr3_mem_ck                    (ddr3_fpga_clk_p),                  //             .mem_ck
		.ddr3_mem_ck_n                  (ddr3_fpga_clk_n),                //             .mem_ck_n
		.ddr3_mem_cke                   (ddr3_fpga_cke),                 //             .mem_cke
		.ddr3_mem_cs_n                  (ddr3_fpga_csn),                //             .mem_cs_n
		.ddr3_mem_dm                    (ddr3_fpga_dm),                  //             .mem_dm
		.ddr3_mem_ras_n                 (ddr3_fpga_rasn),               //             .mem_ras_n
		.ddr3_mem_cas_n                 (ddr3_fpga_casn),               //             .mem_cas_n
		.ddr3_mem_we_n                  (ddr3_fpga_wen),                //             .mem_we_n
		.ddr3_mem_reset_n               (ddr3_fpga_resetn),             //             .mem_reset_n
		.ddr3_mem_dq                    (ddr3_fpga_dq),                  //             .mem_dq
		.ddr3_mem_dqs                   (ddr3_fpga_dqs_p),                 //             .mem_dqs
		.ddr3_mem_dqs_n                 (ddr3_fpga_dqs_n),               //             .mem_dqs_n
		.ddr3_mem_odt                   (ddr3_fpga_odt),                 //             .mem_odt
		.oct_rzqin                      (ddr3_fpga_rzq),                      //          oct.rzqin
		.sdram_status_local_init_done   (),   // sdram_status.local_init_done
		.sdram_status_local_cal_success (), //             .local_cal_success
		.sdram_status_local_cal_fail    (),    //             .local_cal_fail
		
		//Ethernet
		.rx_clock_clk                   (),                   //     rx_clock.clk
		.tx_clock_clk                   ()                    //     tx_clock.clk
	);



endmodule











