// main_qsys.v

// Generated using ACDS version 18.1 625

`timescale 1 ps / 1 ps
module main_qsys (
		input  wire        clk_clk,                        //          clk.clk
		output wire [14:0] ddr3_mem_a,                     //         ddr3.mem_a
		output wire [2:0]  ddr3_mem_ba,                    //             .mem_ba
		output wire [0:0]  ddr3_mem_ck,                    //             .mem_ck
		output wire [0:0]  ddr3_mem_ck_n,                  //             .mem_ck_n
		output wire [0:0]  ddr3_mem_cke,                   //             .mem_cke
		output wire [0:0]  ddr3_mem_cs_n,                  //             .mem_cs_n
		output wire [1:0]  ddr3_mem_dm,                    //             .mem_dm
		output wire [0:0]  ddr3_mem_ras_n,                 //             .mem_ras_n
		output wire [0:0]  ddr3_mem_cas_n,                 //             .mem_cas_n
		output wire [0:0]  ddr3_mem_we_n,                  //             .mem_we_n
		output wire        ddr3_mem_reset_n,               //             .mem_reset_n
		inout  wire [15:0] ddr3_mem_dq,                    //             .mem_dq
		inout  wire [1:0]  ddr3_mem_dqs,                   //             .mem_dqs
		inout  wire [1:0]  ddr3_mem_dqs_n,                 //             .mem_dqs_n
		output wire [0:0]  ddr3_mem_odt,                   //             .mem_odt
		output wire        enet_125m_clk,                  //    enet_125m.clk
		output wire        enet_25m_clk,                   //     enet_25m.clk
		output wire        mac_mdio_mdc,                   //     mac_mdio.mdc
		input  wire        mac_mdio_mdio_in,               //             .mdio_in
		output wire        mac_mdio_mdio_out,              //             .mdio_out
		output wire        mac_mdio_mdio_oen,              //             .mdio_oen
		input  wire        mac_misc_xon_gen,               //     mac_misc.xon_gen
		input  wire        mac_misc_xoff_gen,              //             .xoff_gen
		input  wire        mac_misc_ff_tx_crc_fwd,         //             .ff_tx_crc_fwd
		output wire        mac_misc_ff_tx_septy,           //             .ff_tx_septy
		output wire        mac_misc_tx_ff_uflow,           //             .tx_ff_uflow
		output wire        mac_misc_ff_tx_a_full,          //             .ff_tx_a_full
		output wire        mac_misc_ff_tx_a_empty,         //             .ff_tx_a_empty
		output wire [17:0] mac_misc_rx_err_stat,           //             .rx_err_stat
		output wire [3:0]  mac_misc_rx_frm_type,           //             .rx_frm_type
		output wire        mac_misc_ff_rx_dsav,            //             .ff_rx_dsav
		output wire        mac_misc_ff_rx_a_full,          //             .ff_rx_a_full
		output wire        mac_misc_ff_rx_a_empty,         //             .ff_rx_a_empty
		input  wire [3:0]  mac_rgmii_rgmii_in,             //    mac_rgmii.rgmii_in
		output wire [3:0]  mac_rgmii_rgmii_out,            //             .rgmii_out
		input  wire        mac_rgmii_rx_control,           //             .rx_control
		output wire        mac_rgmii_tx_control,           //             .tx_control
		input  wire        mac_status_set_10,              //   mac_status.set_10
		input  wire        mac_status_set_1000,            //             .set_1000
		output wire        mac_status_eth_mode,            //             .eth_mode
		output wire        mac_status_ena_10,              //             .ena_10
		input  wire        oct_rzqin,                      //          oct.rzqin
		input  wire        reset_reset_n,                  //        reset.reset_n
		input  wire        rx_clock_clk,                   //     rx_clock.clk
		output wire        sdram_status_local_init_done,   // sdram_status.local_init_done
		output wire        sdram_status_local_cal_success, //             .local_cal_success
		output wire        sdram_status_local_cal_fail,    //             .local_cal_fail
		input  wire        tx_clock_clk                    //     tx_clock.clk
	);

	wire         pll_0_outclk0_clk;                                                     // pll_0:outclk_0 -> [ethernet_subsystem:ethernet_subsys_clk_in_clk, irq_mapper:clk, mm_interconnect_0:pll_0_outclk0_clk, nios2:clk, peripheral:peripheral_subsys_clk_in_clk, rst_controller_001:clk, rst_controller_003:clk, sysid_qsys_0:clock]
	wire  [31:0] nios2_data_master_readdata;                                            // mm_interconnect_0:nios2_data_master_readdata -> nios2:d_readdata
	wire         nios2_data_master_waitrequest;                                         // mm_interconnect_0:nios2_data_master_waitrequest -> nios2:d_waitrequest
	wire         nios2_data_master_debugaccess;                                         // nios2:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_data_master_debugaccess
	wire  [29:0] nios2_data_master_address;                                             // nios2:d_address -> mm_interconnect_0:nios2_data_master_address
	wire   [3:0] nios2_data_master_byteenable;                                          // nios2:d_byteenable -> mm_interconnect_0:nios2_data_master_byteenable
	wire         nios2_data_master_read;                                                // nios2:d_read -> mm_interconnect_0:nios2_data_master_read
	wire         nios2_data_master_readdatavalid;                                       // mm_interconnect_0:nios2_data_master_readdatavalid -> nios2:d_readdatavalid
	wire         nios2_data_master_write;                                               // nios2:d_write -> mm_interconnect_0:nios2_data_master_write
	wire  [31:0] nios2_data_master_writedata;                                           // nios2:d_writedata -> mm_interconnect_0:nios2_data_master_writedata
	wire  [31:0] nios2_instruction_master_readdata;                                     // mm_interconnect_0:nios2_instruction_master_readdata -> nios2:i_readdata
	wire         nios2_instruction_master_waitrequest;                                  // mm_interconnect_0:nios2_instruction_master_waitrequest -> nios2:i_waitrequest
	wire  [29:0] nios2_instruction_master_address;                                      // nios2:i_address -> mm_interconnect_0:nios2_instruction_master_address
	wire         nios2_instruction_master_read;                                         // nios2:i_read -> mm_interconnect_0:nios2_instruction_master_read
	wire         nios2_instruction_master_readdatavalid;                                // mm_interconnect_0:nios2_instruction_master_readdatavalid -> nios2:i_readdatavalid
	wire         ethernet_subsystem_sgdma_bridge_m0_waitrequest;                        // mm_interconnect_0:ethernet_subsystem_sgdma_bridge_m0_waitrequest -> ethernet_subsystem:sgdma_bridge_m0_waitrequest
	wire  [31:0] ethernet_subsystem_sgdma_bridge_m0_readdata;                           // mm_interconnect_0:ethernet_subsystem_sgdma_bridge_m0_readdata -> ethernet_subsystem:sgdma_bridge_m0_readdata
	wire         ethernet_subsystem_sgdma_bridge_m0_debugaccess;                        // ethernet_subsystem:sgdma_bridge_m0_debugaccess -> mm_interconnect_0:ethernet_subsystem_sgdma_bridge_m0_debugaccess
	wire  [30:0] ethernet_subsystem_sgdma_bridge_m0_address;                            // ethernet_subsystem:sgdma_bridge_m0_address -> mm_interconnect_0:ethernet_subsystem_sgdma_bridge_m0_address
	wire         ethernet_subsystem_sgdma_bridge_m0_read;                               // ethernet_subsystem:sgdma_bridge_m0_read -> mm_interconnect_0:ethernet_subsystem_sgdma_bridge_m0_read
	wire   [3:0] ethernet_subsystem_sgdma_bridge_m0_byteenable;                         // ethernet_subsystem:sgdma_bridge_m0_byteenable -> mm_interconnect_0:ethernet_subsystem_sgdma_bridge_m0_byteenable
	wire         ethernet_subsystem_sgdma_bridge_m0_readdatavalid;                      // mm_interconnect_0:ethernet_subsystem_sgdma_bridge_m0_readdatavalid -> ethernet_subsystem:sgdma_bridge_m0_readdatavalid
	wire  [31:0] ethernet_subsystem_sgdma_bridge_m0_writedata;                          // ethernet_subsystem:sgdma_bridge_m0_writedata -> mm_interconnect_0:ethernet_subsystem_sgdma_bridge_m0_writedata
	wire         ethernet_subsystem_sgdma_bridge_m0_write;                              // ethernet_subsystem:sgdma_bridge_m0_write -> mm_interconnect_0:ethernet_subsystem_sgdma_bridge_m0_write
	wire   [0:0] ethernet_subsystem_sgdma_bridge_m0_burstcount;                         // ethernet_subsystem:sgdma_bridge_m0_burstcount -> mm_interconnect_0:ethernet_subsystem_sgdma_bridge_m0_burstcount
	wire         mm_interconnect_0_sdram_avl_beginbursttransfer;                        // mm_interconnect_0:sdram_avl_beginbursttransfer -> sdram:avl_burstbegin
	wire  [63:0] mm_interconnect_0_sdram_avl_readdata;                                  // sdram:avl_rdata -> mm_interconnect_0:sdram_avl_readdata
	wire         mm_interconnect_0_sdram_avl_waitrequest;                               // sdram:avl_ready -> mm_interconnect_0:sdram_avl_waitrequest
	wire  [25:0] mm_interconnect_0_sdram_avl_address;                                   // mm_interconnect_0:sdram_avl_address -> sdram:avl_addr
	wire         mm_interconnect_0_sdram_avl_read;                                      // mm_interconnect_0:sdram_avl_read -> sdram:avl_read_req
	wire   [7:0] mm_interconnect_0_sdram_avl_byteenable;                                // mm_interconnect_0:sdram_avl_byteenable -> sdram:avl_be
	wire         mm_interconnect_0_sdram_avl_readdatavalid;                             // sdram:avl_rdata_valid -> mm_interconnect_0:sdram_avl_readdatavalid
	wire         mm_interconnect_0_sdram_avl_write;                                     // mm_interconnect_0:sdram_avl_write -> sdram:avl_write_req
	wire  [63:0] mm_interconnect_0_sdram_avl_writedata;                                 // mm_interconnect_0:sdram_avl_writedata -> sdram:avl_wdata
	wire   [2:0] mm_interconnect_0_sdram_avl_burstcount;                                // mm_interconnect_0:sdram_avl_burstcount -> sdram:avl_size
	wire         sdram_afi_clk_clk;                                                     // sdram:afi_clk -> [mm_interconnect_0:sdram_afi_clk_clk, rst_controller_004:clk]
	wire  [31:0] mm_interconnect_0_sysid_qsys_0_control_slave_readdata;                 // sysid_qsys_0:readdata -> mm_interconnect_0:sysid_qsys_0_control_slave_readdata
	wire   [0:0] mm_interconnect_0_sysid_qsys_0_control_slave_address;                  // mm_interconnect_0:sysid_qsys_0_control_slave_address -> sysid_qsys_0:address
	wire  [31:0] mm_interconnect_0_nios2_debug_mem_slave_readdata;                      // nios2:debug_mem_slave_readdata -> mm_interconnect_0:nios2_debug_mem_slave_readdata
	wire         mm_interconnect_0_nios2_debug_mem_slave_waitrequest;                   // nios2:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_debug_mem_slave_waitrequest
	wire         mm_interconnect_0_nios2_debug_mem_slave_debugaccess;                   // mm_interconnect_0:nios2_debug_mem_slave_debugaccess -> nios2:debug_mem_slave_debugaccess
	wire   [8:0] mm_interconnect_0_nios2_debug_mem_slave_address;                       // mm_interconnect_0:nios2_debug_mem_slave_address -> nios2:debug_mem_slave_address
	wire         mm_interconnect_0_nios2_debug_mem_slave_read;                          // mm_interconnect_0:nios2_debug_mem_slave_read -> nios2:debug_mem_slave_read
	wire   [3:0] mm_interconnect_0_nios2_debug_mem_slave_byteenable;                    // mm_interconnect_0:nios2_debug_mem_slave_byteenable -> nios2:debug_mem_slave_byteenable
	wire         mm_interconnect_0_nios2_debug_mem_slave_write;                         // mm_interconnect_0:nios2_debug_mem_slave_write -> nios2:debug_mem_slave_write
	wire  [31:0] mm_interconnect_0_nios2_debug_mem_slave_writedata;                     // mm_interconnect_0:nios2_debug_mem_slave_writedata -> nios2:debug_mem_slave_writedata
	wire         mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_chipselect;  // mm_interconnect_0:ethernet_subsystem_descriptor_memory_s2_chipselect -> ethernet_subsystem:descriptor_memory_s2_chipselect
	wire  [31:0] mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_readdata;    // ethernet_subsystem:descriptor_memory_s2_readdata -> mm_interconnect_0:ethernet_subsystem_descriptor_memory_s2_readdata
	wire  [10:0] mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_address;     // mm_interconnect_0:ethernet_subsystem_descriptor_memory_s2_address -> ethernet_subsystem:descriptor_memory_s2_address
	wire   [3:0] mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_byteenable;  // mm_interconnect_0:ethernet_subsystem_descriptor_memory_s2_byteenable -> ethernet_subsystem:descriptor_memory_s2_byteenable
	wire         mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_write;       // mm_interconnect_0:ethernet_subsystem_descriptor_memory_s2_write -> ethernet_subsystem:descriptor_memory_s2_write
	wire  [31:0] mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_writedata;   // mm_interconnect_0:ethernet_subsystem_descriptor_memory_s2_writedata -> ethernet_subsystem:descriptor_memory_s2_writedata
	wire         mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_clken;       // mm_interconnect_0:ethernet_subsystem_descriptor_memory_s2_clken -> ethernet_subsystem:descriptor_memory_s2_clken
	wire  [31:0] mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_readdata;      // ethernet_subsystem:ethernet_bridge_s0_readdata -> mm_interconnect_0:ethernet_subsystem_ethernet_bridge_s0_readdata
	wire         mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_waitrequest;   // ethernet_subsystem:ethernet_bridge_s0_waitrequest -> mm_interconnect_0:ethernet_subsystem_ethernet_bridge_s0_waitrequest
	wire         mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_debugaccess;   // mm_interconnect_0:ethernet_subsystem_ethernet_bridge_s0_debugaccess -> ethernet_subsystem:ethernet_bridge_s0_debugaccess
	wire  [10:0] mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_address;       // mm_interconnect_0:ethernet_subsystem_ethernet_bridge_s0_address -> ethernet_subsystem:ethernet_bridge_s0_address
	wire         mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_read;          // mm_interconnect_0:ethernet_subsystem_ethernet_bridge_s0_read -> ethernet_subsystem:ethernet_bridge_s0_read
	wire   [3:0] mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_byteenable;    // mm_interconnect_0:ethernet_subsystem_ethernet_bridge_s0_byteenable -> ethernet_subsystem:ethernet_bridge_s0_byteenable
	wire         mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_readdatavalid; // ethernet_subsystem:ethernet_bridge_s0_readdatavalid -> mm_interconnect_0:ethernet_subsystem_ethernet_bridge_s0_readdatavalid
	wire         mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_write;         // mm_interconnect_0:ethernet_subsystem_ethernet_bridge_s0_write -> ethernet_subsystem:ethernet_bridge_s0_write
	wire  [31:0] mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_writedata;     // mm_interconnect_0:ethernet_subsystem_ethernet_bridge_s0_writedata -> ethernet_subsystem:ethernet_bridge_s0_writedata
	wire   [0:0] mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_burstcount;    // mm_interconnect_0:ethernet_subsystem_ethernet_bridge_s0_burstcount -> ethernet_subsystem:ethernet_bridge_s0_burstcount
	wire  [31:0] mm_interconnect_0_peripheral_peripheral_bridge_s0_readdata;            // peripheral:peripheral_bridge_s0_readdata -> mm_interconnect_0:peripheral_peripheral_bridge_s0_readdata
	wire         mm_interconnect_0_peripheral_peripheral_bridge_s0_waitrequest;         // peripheral:peripheral_bridge_s0_waitrequest -> mm_interconnect_0:peripheral_peripheral_bridge_s0_waitrequest
	wire         mm_interconnect_0_peripheral_peripheral_bridge_s0_debugaccess;         // mm_interconnect_0:peripheral_peripheral_bridge_s0_debugaccess -> peripheral:peripheral_bridge_s0_debugaccess
	wire   [7:0] mm_interconnect_0_peripheral_peripheral_bridge_s0_address;             // mm_interconnect_0:peripheral_peripheral_bridge_s0_address -> peripheral:peripheral_bridge_s0_address
	wire         mm_interconnect_0_peripheral_peripheral_bridge_s0_read;                // mm_interconnect_0:peripheral_peripheral_bridge_s0_read -> peripheral:peripheral_bridge_s0_read
	wire   [3:0] mm_interconnect_0_peripheral_peripheral_bridge_s0_byteenable;          // mm_interconnect_0:peripheral_peripheral_bridge_s0_byteenable -> peripheral:peripheral_bridge_s0_byteenable
	wire         mm_interconnect_0_peripheral_peripheral_bridge_s0_readdatavalid;       // peripheral:peripheral_bridge_s0_readdatavalid -> mm_interconnect_0:peripheral_peripheral_bridge_s0_readdatavalid
	wire         mm_interconnect_0_peripheral_peripheral_bridge_s0_write;               // mm_interconnect_0:peripheral_peripheral_bridge_s0_write -> peripheral:peripheral_bridge_s0_write
	wire  [31:0] mm_interconnect_0_peripheral_peripheral_bridge_s0_writedata;           // mm_interconnect_0:peripheral_peripheral_bridge_s0_writedata -> peripheral:peripheral_bridge_s0_writedata
	wire   [0:0] mm_interconnect_0_peripheral_peripheral_bridge_s0_burstcount;          // mm_interconnect_0:peripheral_peripheral_bridge_s0_burstcount -> peripheral:peripheral_bridge_s0_burstcount
	wire         irq_mapper_receiver0_irq;                                              // peripheral:button_pio_irq_irq -> irq_mapper:receiver0_irq
	wire         irq_mapper_receiver1_irq;                                              // peripheral:high_res_timer_irq_irq -> irq_mapper:receiver1_irq
	wire         irq_mapper_receiver2_irq;                                              // peripheral:jtag_uart_irq_irq -> irq_mapper:receiver2_irq
	wire         irq_mapper_receiver3_irq;                                              // ethernet_subsystem:sgdma_rx_csr_irq_irq -> irq_mapper:receiver3_irq
	wire         irq_mapper_receiver4_irq;                                              // ethernet_subsystem:sgdma_tx_csr_irq_irq -> irq_mapper:receiver4_irq
	wire         irq_mapper_receiver5_irq;                                              // peripheral:sys_clk_timer_irq_irq -> irq_mapper:receiver5_irq
	wire  [31:0] nios2_irq_irq;                                                         // irq_mapper:sender_irq -> nios2:irq
	wire         rst_controller_reset_out_reset;                                        // rst_controller:reset_out -> ethernet_subsystem:ethernet_subsys_reset_in_reset_n
	wire         nios2_debug_reset_request_reset;                                       // nios2:debug_reset_request -> [rst_controller:reset_in1, rst_controller_001:reset_in1, rst_controller_002:reset_in1]
	wire         rst_controller_001_reset_out_reset;                                    // rst_controller_001:reset_out -> [irq_mapper:reset, mm_interconnect_0:ethernet_subsystem_ethernet_subsys_reset_in_reset_bridge_in_reset_reset, mm_interconnect_0:nios2_reset_reset_bridge_in_reset_reset, nios2:reset_n, rst_translator:in_reset]
	wire         rst_controller_001_reset_out_reset_req;                                // rst_controller_001:reset_req -> [nios2:reset_req, rst_translator:reset_req_in]
	wire         rst_controller_002_reset_out_reset;                                    // rst_controller_002:reset_out -> peripheral:peripheral_subsys_reset_in_reset_n
	wire         rst_controller_003_reset_out_reset;                                    // rst_controller_003:reset_out -> [mm_interconnect_0:sysid_qsys_0_reset_reset_bridge_in_reset_reset, sysid_qsys_0:reset_n]
	wire         rst_controller_004_reset_out_reset;                                    // rst_controller_004:reset_out -> [mm_interconnect_0:sdram_avl_translator_reset_reset_bridge_in_reset_reset, mm_interconnect_0:sdram_soft_reset_reset_bridge_in_reset_reset]

	main_qsys_ethernet_subsystem ethernet_subsystem (
		.descriptor_memory_s2_address      (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_address),     //     descriptor_memory_s2.address
		.descriptor_memory_s2_chipselect   (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_chipselect),  //                         .chipselect
		.descriptor_memory_s2_clken        (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_clken),       //                         .clken
		.descriptor_memory_s2_write        (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_write),       //                         .write
		.descriptor_memory_s2_readdata     (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_readdata),    //                         .readdata
		.descriptor_memory_s2_writedata    (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_writedata),   //                         .writedata
		.descriptor_memory_s2_byteenable   (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_byteenable),  //                         .byteenable
		.ethernet_bridge_s0_waitrequest    (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_waitrequest),   //       ethernet_bridge_s0.waitrequest
		.ethernet_bridge_s0_readdata       (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_readdata),      //                         .readdata
		.ethernet_bridge_s0_readdatavalid  (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_readdatavalid), //                         .readdatavalid
		.ethernet_bridge_s0_burstcount     (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_burstcount),    //                         .burstcount
		.ethernet_bridge_s0_writedata      (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_writedata),     //                         .writedata
		.ethernet_bridge_s0_address        (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_address),       //                         .address
		.ethernet_bridge_s0_write          (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_write),         //                         .write
		.ethernet_bridge_s0_read           (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_read),          //                         .read
		.ethernet_bridge_s0_byteenable     (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_byteenable),    //                         .byteenable
		.ethernet_bridge_s0_debugaccess    (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_debugaccess),   //                         .debugaccess
		.ethernet_subsys_clk_in_clk        (pll_0_outclk0_clk),                                                     //   ethernet_subsys_clk_in.clk
		.ethernet_subsys_reset_in_reset_n  (~rst_controller_reset_out_reset),                                       // ethernet_subsys_reset_in.reset_n
		.mac_mdio_connection_mdc           (mac_mdio_mdc),                                                          //      mac_mdio_connection.mdc
		.mac_mdio_connection_mdio_in       (mac_mdio_mdio_in),                                                      //                         .mdio_in
		.mac_mdio_connection_mdio_out      (mac_mdio_mdio_out),                                                     //                         .mdio_out
		.mac_mdio_connection_mdio_oen      (mac_mdio_mdio_oen),                                                     //                         .mdio_oen
		.mac_misc_connection_xon_gen       (mac_misc_xon_gen),                                                      //      mac_misc_connection.xon_gen
		.mac_misc_connection_xoff_gen      (mac_misc_xoff_gen),                                                     //                         .xoff_gen
		.mac_misc_connection_ff_tx_crc_fwd (mac_misc_ff_tx_crc_fwd),                                                //                         .ff_tx_crc_fwd
		.mac_misc_connection_ff_tx_septy   (mac_misc_ff_tx_septy),                                                  //                         .ff_tx_septy
		.mac_misc_connection_tx_ff_uflow   (mac_misc_tx_ff_uflow),                                                  //                         .tx_ff_uflow
		.mac_misc_connection_ff_tx_a_full  (mac_misc_ff_tx_a_full),                                                 //                         .ff_tx_a_full
		.mac_misc_connection_ff_tx_a_empty (mac_misc_ff_tx_a_empty),                                                //                         .ff_tx_a_empty
		.mac_misc_connection_rx_err_stat   (mac_misc_rx_err_stat),                                                  //                         .rx_err_stat
		.mac_misc_connection_rx_frm_type   (mac_misc_rx_frm_type),                                                  //                         .rx_frm_type
		.mac_misc_connection_ff_rx_dsav    (mac_misc_ff_rx_dsav),                                                   //                         .ff_rx_dsav
		.mac_misc_connection_ff_rx_a_full  (mac_misc_ff_rx_a_full),                                                 //                         .ff_rx_a_full
		.mac_misc_connection_ff_rx_a_empty (mac_misc_ff_rx_a_empty),                                                //                         .ff_rx_a_empty
		.mac_rgmii_connection_rgmii_in     (mac_rgmii_rgmii_in),                                                    //     mac_rgmii_connection.rgmii_in
		.mac_rgmii_connection_rgmii_out    (mac_rgmii_rgmii_out),                                                   //                         .rgmii_out
		.mac_rgmii_connection_rx_control   (mac_rgmii_rx_control),                                                  //                         .rx_control
		.mac_rgmii_connection_tx_control   (mac_rgmii_tx_control),                                                  //                         .tx_control
		.mac_status_connection_set_10      (mac_status_set_10),                                                     //    mac_status_connection.set_10
		.mac_status_connection_set_1000    (mac_status_set_1000),                                                   //                         .set_1000
		.mac_status_connection_eth_mode    (mac_status_eth_mode),                                                   //                         .eth_mode
		.mac_status_connection_ena_10      (mac_status_ena_10),                                                     //                         .ena_10
		.rx_clock_clk                      (rx_clock_clk),                                                          //                 rx_clock.clk
		.sgdma_bridge_m0_waitrequest       (ethernet_subsystem_sgdma_bridge_m0_waitrequest),                        //          sgdma_bridge_m0.waitrequest
		.sgdma_bridge_m0_readdata          (ethernet_subsystem_sgdma_bridge_m0_readdata),                           //                         .readdata
		.sgdma_bridge_m0_readdatavalid     (ethernet_subsystem_sgdma_bridge_m0_readdatavalid),                      //                         .readdatavalid
		.sgdma_bridge_m0_burstcount        (ethernet_subsystem_sgdma_bridge_m0_burstcount),                         //                         .burstcount
		.sgdma_bridge_m0_writedata         (ethernet_subsystem_sgdma_bridge_m0_writedata),                          //                         .writedata
		.sgdma_bridge_m0_address           (ethernet_subsystem_sgdma_bridge_m0_address),                            //                         .address
		.sgdma_bridge_m0_write             (ethernet_subsystem_sgdma_bridge_m0_write),                              //                         .write
		.sgdma_bridge_m0_read              (ethernet_subsystem_sgdma_bridge_m0_read),                               //                         .read
		.sgdma_bridge_m0_byteenable        (ethernet_subsystem_sgdma_bridge_m0_byteenable),                         //                         .byteenable
		.sgdma_bridge_m0_debugaccess       (ethernet_subsystem_sgdma_bridge_m0_debugaccess),                        //                         .debugaccess
		.sgdma_rx_csr_irq_irq              (irq_mapper_receiver3_irq),                                              //         sgdma_rx_csr_irq.irq
		.sgdma_tx_csr_irq_irq              (irq_mapper_receiver4_irq),                                              //         sgdma_tx_csr_irq.irq
		.tx_clock_clk                      (tx_clock_clk)                                                           //                 tx_clock.clk
	);

	main_qsys_nios2 nios2 (
		.clk                                 (pll_0_outclk0_clk),                                   //                       clk.clk
		.reset_n                             (~rst_controller_001_reset_out_reset),                 //                     reset.reset_n
		.reset_req                           (rst_controller_001_reset_out_reset_req),              //                          .reset_req
		.d_address                           (nios2_data_master_address),                           //               data_master.address
		.d_byteenable                        (nios2_data_master_byteenable),                        //                          .byteenable
		.d_read                              (nios2_data_master_read),                              //                          .read
		.d_readdata                          (nios2_data_master_readdata),                          //                          .readdata
		.d_waitrequest                       (nios2_data_master_waitrequest),                       //                          .waitrequest
		.d_write                             (nios2_data_master_write),                             //                          .write
		.d_writedata                         (nios2_data_master_writedata),                         //                          .writedata
		.d_readdatavalid                     (nios2_data_master_readdatavalid),                     //                          .readdatavalid
		.debug_mem_slave_debugaccess_to_roms (nios2_data_master_debugaccess),                       //                          .debugaccess
		.i_address                           (nios2_instruction_master_address),                    //        instruction_master.address
		.i_read                              (nios2_instruction_master_read),                       //                          .read
		.i_readdata                          (nios2_instruction_master_readdata),                   //                          .readdata
		.i_waitrequest                       (nios2_instruction_master_waitrequest),                //                          .waitrequest
		.i_readdatavalid                     (nios2_instruction_master_readdatavalid),              //                          .readdatavalid
		.irq                                 (nios2_irq_irq),                                       //                       irq.irq
		.debug_reset_request                 (nios2_debug_reset_request_reset),                     //       debug_reset_request.reset
		.debug_mem_slave_address             (mm_interconnect_0_nios2_debug_mem_slave_address),     //           debug_mem_slave.address
		.debug_mem_slave_byteenable          (mm_interconnect_0_nios2_debug_mem_slave_byteenable),  //                          .byteenable
		.debug_mem_slave_debugaccess         (mm_interconnect_0_nios2_debug_mem_slave_debugaccess), //                          .debugaccess
		.debug_mem_slave_read                (mm_interconnect_0_nios2_debug_mem_slave_read),        //                          .read
		.debug_mem_slave_readdata            (mm_interconnect_0_nios2_debug_mem_slave_readdata),    //                          .readdata
		.debug_mem_slave_waitrequest         (mm_interconnect_0_nios2_debug_mem_slave_waitrequest), //                          .waitrequest
		.debug_mem_slave_write               (mm_interconnect_0_nios2_debug_mem_slave_write),       //                          .write
		.debug_mem_slave_writedata           (mm_interconnect_0_nios2_debug_mem_slave_writedata),   //                          .writedata
		.dummy_ci_port                       ()                                                     // custom_instruction_master.readra
	);

	main_qsys_peripheral peripheral (
		.button_pio_external_connection_export (),                                                                // button_pio_external_connection.export
		.button_pio_irq_irq                    (irq_mapper_receiver0_irq),                                        //                 button_pio_irq.irq
		.high_res_timer_irq_irq                (irq_mapper_receiver1_irq),                                        //             high_res_timer_irq.irq
		.jtag_uart_irq_irq                     (irq_mapper_receiver2_irq),                                        //                  jtag_uart_irq.irq
		.led_pio_external_connection_export    (),                                                                //    led_pio_external_connection.export
		.peripheral_bridge_s0_waitrequest      (mm_interconnect_0_peripheral_peripheral_bridge_s0_waitrequest),   //           peripheral_bridge_s0.waitrequest
		.peripheral_bridge_s0_readdata         (mm_interconnect_0_peripheral_peripheral_bridge_s0_readdata),      //                               .readdata
		.peripheral_bridge_s0_readdatavalid    (mm_interconnect_0_peripheral_peripheral_bridge_s0_readdatavalid), //                               .readdatavalid
		.peripheral_bridge_s0_burstcount       (mm_interconnect_0_peripheral_peripheral_bridge_s0_burstcount),    //                               .burstcount
		.peripheral_bridge_s0_writedata        (mm_interconnect_0_peripheral_peripheral_bridge_s0_writedata),     //                               .writedata
		.peripheral_bridge_s0_address          (mm_interconnect_0_peripheral_peripheral_bridge_s0_address),       //                               .address
		.peripheral_bridge_s0_write            (mm_interconnect_0_peripheral_peripheral_bridge_s0_write),         //                               .write
		.peripheral_bridge_s0_read             (mm_interconnect_0_peripheral_peripheral_bridge_s0_read),          //                               .read
		.peripheral_bridge_s0_byteenable       (mm_interconnect_0_peripheral_peripheral_bridge_s0_byteenable),    //                               .byteenable
		.peripheral_bridge_s0_debugaccess      (mm_interconnect_0_peripheral_peripheral_bridge_s0_debugaccess),   //                               .debugaccess
		.peripheral_subsys_clk_in_clk          (pll_0_outclk0_clk),                                               //       peripheral_subsys_clk_in.clk
		.peripheral_subsys_reset_in_reset_n    (~rst_controller_002_reset_out_reset),                             //     peripheral_subsys_reset_in.reset_n
		.sys_clk_timer_irq_irq                 (irq_mapper_receiver5_irq)                                         //              sys_clk_timer_irq.irq
	);

	main_qsys_pll_0 pll_0 (
		.refclk   (clk_clk),           //  refclk.clk
		.rst      (~reset_reset_n),    //   reset.reset
		.outclk_0 (pll_0_outclk0_clk), // outclk0.clk
		.outclk_1 (enet_125m_clk),     // outclk1.clk
		.outclk_2 (enet_25m_clk),      // outclk2.clk
		.locked   ()                   //  locked.export
	);

	main_qsys_sdram sdram (
		.pll_ref_clk               (clk_clk),                                        //      pll_ref_clk.clk
		.global_reset_n            (reset_reset_n),                                  //     global_reset.reset_n
		.soft_reset_n              (reset_reset_n),                                  //       soft_reset.reset_n
		.afi_clk                   (sdram_afi_clk_clk),                              //          afi_clk.clk
		.afi_half_clk              (),                                               //     afi_half_clk.clk
		.afi_reset_n               (),                                               //        afi_reset.reset_n
		.afi_reset_export_n        (),                                               // afi_reset_export.reset_n
		.mem_a                     (ddr3_mem_a),                                     //           memory.mem_a
		.mem_ba                    (ddr3_mem_ba),                                    //                 .mem_ba
		.mem_ck                    (ddr3_mem_ck),                                    //                 .mem_ck
		.mem_ck_n                  (ddr3_mem_ck_n),                                  //                 .mem_ck_n
		.mem_cke                   (ddr3_mem_cke),                                   //                 .mem_cke
		.mem_cs_n                  (ddr3_mem_cs_n),                                  //                 .mem_cs_n
		.mem_dm                    (ddr3_mem_dm),                                    //                 .mem_dm
		.mem_ras_n                 (ddr3_mem_ras_n),                                 //                 .mem_ras_n
		.mem_cas_n                 (ddr3_mem_cas_n),                                 //                 .mem_cas_n
		.mem_we_n                  (ddr3_mem_we_n),                                  //                 .mem_we_n
		.mem_reset_n               (ddr3_mem_reset_n),                               //                 .mem_reset_n
		.mem_dq                    (ddr3_mem_dq),                                    //                 .mem_dq
		.mem_dqs                   (ddr3_mem_dqs),                                   //                 .mem_dqs
		.mem_dqs_n                 (ddr3_mem_dqs_n),                                 //                 .mem_dqs_n
		.mem_odt                   (ddr3_mem_odt),                                   //                 .mem_odt
		.avl_ready                 (mm_interconnect_0_sdram_avl_waitrequest),        //              avl.waitrequest_n
		.avl_burstbegin            (mm_interconnect_0_sdram_avl_beginbursttransfer), //                 .beginbursttransfer
		.avl_addr                  (mm_interconnect_0_sdram_avl_address),            //                 .address
		.avl_rdata_valid           (mm_interconnect_0_sdram_avl_readdatavalid),      //                 .readdatavalid
		.avl_rdata                 (mm_interconnect_0_sdram_avl_readdata),           //                 .readdata
		.avl_wdata                 (mm_interconnect_0_sdram_avl_writedata),          //                 .writedata
		.avl_be                    (mm_interconnect_0_sdram_avl_byteenable),         //                 .byteenable
		.avl_read_req              (mm_interconnect_0_sdram_avl_read),               //                 .read
		.avl_write_req             (mm_interconnect_0_sdram_avl_write),              //                 .write
		.avl_size                  (mm_interconnect_0_sdram_avl_burstcount),         //                 .burstcount
		.local_init_done           (sdram_status_local_init_done),                   //           status.local_init_done
		.local_cal_success         (sdram_status_local_cal_success),                 //                 .local_cal_success
		.local_cal_fail            (sdram_status_local_cal_fail),                    //                 .local_cal_fail
		.oct_rzqin                 (oct_rzqin),                                      //              oct.rzqin
		.pll_mem_clk               (),                                               //      pll_sharing.pll_mem_clk
		.pll_write_clk             (),                                               //                 .pll_write_clk
		.pll_locked                (),                                               //                 .pll_locked
		.pll_write_clk_pre_phy_clk (),                                               //                 .pll_write_clk_pre_phy_clk
		.pll_addr_cmd_clk          (),                                               //                 .pll_addr_cmd_clk
		.pll_avl_clk               (),                                               //                 .pll_avl_clk
		.pll_config_clk            (),                                               //                 .pll_config_clk
		.pll_mem_phy_clk           (),                                               //                 .pll_mem_phy_clk
		.afi_phy_clk               (),                                               //                 .afi_phy_clk
		.pll_avl_phy_clk           ()                                                //                 .pll_avl_phy_clk
	);

	main_qsys_sysid_qsys_0 sysid_qsys_0 (
		.clock    (pll_0_outclk0_clk),                                     //           clk.clk
		.reset_n  (~rst_controller_003_reset_out_reset),                   //         reset.reset_n
		.readdata (mm_interconnect_0_sysid_qsys_0_control_slave_readdata), // control_slave.readdata
		.address  (mm_interconnect_0_sysid_qsys_0_control_slave_address)   //              .address
	);

	main_qsys_mm_interconnect_0 mm_interconnect_0 (
		.pll_0_outclk0_clk                                                       (pll_0_outclk0_clk),                                                     //                                                     pll_0_outclk0.clk
		.sdram_afi_clk_clk                                                       (sdram_afi_clk_clk),                                                     //                                                     sdram_afi_clk.clk
		.ethernet_subsystem_ethernet_subsys_reset_in_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset),                                    // ethernet_subsystem_ethernet_subsys_reset_in_reset_bridge_in_reset.reset
		.nios2_reset_reset_bridge_in_reset_reset                                 (rst_controller_001_reset_out_reset),                                    //                                 nios2_reset_reset_bridge_in_reset.reset
		.sdram_avl_translator_reset_reset_bridge_in_reset_reset                  (rst_controller_004_reset_out_reset),                                    //                  sdram_avl_translator_reset_reset_bridge_in_reset.reset
		.sdram_soft_reset_reset_bridge_in_reset_reset                            (rst_controller_004_reset_out_reset),                                    //                            sdram_soft_reset_reset_bridge_in_reset.reset
		.sysid_qsys_0_reset_reset_bridge_in_reset_reset                          (rst_controller_003_reset_out_reset),                                    //                          sysid_qsys_0_reset_reset_bridge_in_reset.reset
		.ethernet_subsystem_sgdma_bridge_m0_address                              (ethernet_subsystem_sgdma_bridge_m0_address),                            //                                ethernet_subsystem_sgdma_bridge_m0.address
		.ethernet_subsystem_sgdma_bridge_m0_waitrequest                          (ethernet_subsystem_sgdma_bridge_m0_waitrequest),                        //                                                                  .waitrequest
		.ethernet_subsystem_sgdma_bridge_m0_burstcount                           (ethernet_subsystem_sgdma_bridge_m0_burstcount),                         //                                                                  .burstcount
		.ethernet_subsystem_sgdma_bridge_m0_byteenable                           (ethernet_subsystem_sgdma_bridge_m0_byteenable),                         //                                                                  .byteenable
		.ethernet_subsystem_sgdma_bridge_m0_read                                 (ethernet_subsystem_sgdma_bridge_m0_read),                               //                                                                  .read
		.ethernet_subsystem_sgdma_bridge_m0_readdata                             (ethernet_subsystem_sgdma_bridge_m0_readdata),                           //                                                                  .readdata
		.ethernet_subsystem_sgdma_bridge_m0_readdatavalid                        (ethernet_subsystem_sgdma_bridge_m0_readdatavalid),                      //                                                                  .readdatavalid
		.ethernet_subsystem_sgdma_bridge_m0_write                                (ethernet_subsystem_sgdma_bridge_m0_write),                              //                                                                  .write
		.ethernet_subsystem_sgdma_bridge_m0_writedata                            (ethernet_subsystem_sgdma_bridge_m0_writedata),                          //                                                                  .writedata
		.ethernet_subsystem_sgdma_bridge_m0_debugaccess                          (ethernet_subsystem_sgdma_bridge_m0_debugaccess),                        //                                                                  .debugaccess
		.nios2_data_master_address                                               (nios2_data_master_address),                                             //                                                 nios2_data_master.address
		.nios2_data_master_waitrequest                                           (nios2_data_master_waitrequest),                                         //                                                                  .waitrequest
		.nios2_data_master_byteenable                                            (nios2_data_master_byteenable),                                          //                                                                  .byteenable
		.nios2_data_master_read                                                  (nios2_data_master_read),                                                //                                                                  .read
		.nios2_data_master_readdata                                              (nios2_data_master_readdata),                                            //                                                                  .readdata
		.nios2_data_master_readdatavalid                                         (nios2_data_master_readdatavalid),                                       //                                                                  .readdatavalid
		.nios2_data_master_write                                                 (nios2_data_master_write),                                               //                                                                  .write
		.nios2_data_master_writedata                                             (nios2_data_master_writedata),                                           //                                                                  .writedata
		.nios2_data_master_debugaccess                                           (nios2_data_master_debugaccess),                                         //                                                                  .debugaccess
		.nios2_instruction_master_address                                        (nios2_instruction_master_address),                                      //                                          nios2_instruction_master.address
		.nios2_instruction_master_waitrequest                                    (nios2_instruction_master_waitrequest),                                  //                                                                  .waitrequest
		.nios2_instruction_master_read                                           (nios2_instruction_master_read),                                         //                                                                  .read
		.nios2_instruction_master_readdata                                       (nios2_instruction_master_readdata),                                     //                                                                  .readdata
		.nios2_instruction_master_readdatavalid                                  (nios2_instruction_master_readdatavalid),                                //                                                                  .readdatavalid
		.ethernet_subsystem_descriptor_memory_s2_address                         (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_address),     //                           ethernet_subsystem_descriptor_memory_s2.address
		.ethernet_subsystem_descriptor_memory_s2_write                           (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_write),       //                                                                  .write
		.ethernet_subsystem_descriptor_memory_s2_readdata                        (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_readdata),    //                                                                  .readdata
		.ethernet_subsystem_descriptor_memory_s2_writedata                       (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_writedata),   //                                                                  .writedata
		.ethernet_subsystem_descriptor_memory_s2_byteenable                      (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_byteenable),  //                                                                  .byteenable
		.ethernet_subsystem_descriptor_memory_s2_chipselect                      (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_chipselect),  //                                                                  .chipselect
		.ethernet_subsystem_descriptor_memory_s2_clken                           (mm_interconnect_0_ethernet_subsystem_descriptor_memory_s2_clken),       //                                                                  .clken
		.ethernet_subsystem_ethernet_bridge_s0_address                           (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_address),       //                             ethernet_subsystem_ethernet_bridge_s0.address
		.ethernet_subsystem_ethernet_bridge_s0_write                             (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_write),         //                                                                  .write
		.ethernet_subsystem_ethernet_bridge_s0_read                              (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_read),          //                                                                  .read
		.ethernet_subsystem_ethernet_bridge_s0_readdata                          (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_readdata),      //                                                                  .readdata
		.ethernet_subsystem_ethernet_bridge_s0_writedata                         (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_writedata),     //                                                                  .writedata
		.ethernet_subsystem_ethernet_bridge_s0_burstcount                        (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_burstcount),    //                                                                  .burstcount
		.ethernet_subsystem_ethernet_bridge_s0_byteenable                        (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_byteenable),    //                                                                  .byteenable
		.ethernet_subsystem_ethernet_bridge_s0_readdatavalid                     (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_readdatavalid), //                                                                  .readdatavalid
		.ethernet_subsystem_ethernet_bridge_s0_waitrequest                       (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_waitrequest),   //                                                                  .waitrequest
		.ethernet_subsystem_ethernet_bridge_s0_debugaccess                       (mm_interconnect_0_ethernet_subsystem_ethernet_bridge_s0_debugaccess),   //                                                                  .debugaccess
		.nios2_debug_mem_slave_address                                           (mm_interconnect_0_nios2_debug_mem_slave_address),                       //                                             nios2_debug_mem_slave.address
		.nios2_debug_mem_slave_write                                             (mm_interconnect_0_nios2_debug_mem_slave_write),                         //                                                                  .write
		.nios2_debug_mem_slave_read                                              (mm_interconnect_0_nios2_debug_mem_slave_read),                          //                                                                  .read
		.nios2_debug_mem_slave_readdata                                          (mm_interconnect_0_nios2_debug_mem_slave_readdata),                      //                                                                  .readdata
		.nios2_debug_mem_slave_writedata                                         (mm_interconnect_0_nios2_debug_mem_slave_writedata),                     //                                                                  .writedata
		.nios2_debug_mem_slave_byteenable                                        (mm_interconnect_0_nios2_debug_mem_slave_byteenable),                    //                                                                  .byteenable
		.nios2_debug_mem_slave_waitrequest                                       (mm_interconnect_0_nios2_debug_mem_slave_waitrequest),                   //                                                                  .waitrequest
		.nios2_debug_mem_slave_debugaccess                                       (mm_interconnect_0_nios2_debug_mem_slave_debugaccess),                   //                                                                  .debugaccess
		.peripheral_peripheral_bridge_s0_address                                 (mm_interconnect_0_peripheral_peripheral_bridge_s0_address),             //                                   peripheral_peripheral_bridge_s0.address
		.peripheral_peripheral_bridge_s0_write                                   (mm_interconnect_0_peripheral_peripheral_bridge_s0_write),               //                                                                  .write
		.peripheral_peripheral_bridge_s0_read                                    (mm_interconnect_0_peripheral_peripheral_bridge_s0_read),                //                                                                  .read
		.peripheral_peripheral_bridge_s0_readdata                                (mm_interconnect_0_peripheral_peripheral_bridge_s0_readdata),            //                                                                  .readdata
		.peripheral_peripheral_bridge_s0_writedata                               (mm_interconnect_0_peripheral_peripheral_bridge_s0_writedata),           //                                                                  .writedata
		.peripheral_peripheral_bridge_s0_burstcount                              (mm_interconnect_0_peripheral_peripheral_bridge_s0_burstcount),          //                                                                  .burstcount
		.peripheral_peripheral_bridge_s0_byteenable                              (mm_interconnect_0_peripheral_peripheral_bridge_s0_byteenable),          //                                                                  .byteenable
		.peripheral_peripheral_bridge_s0_readdatavalid                           (mm_interconnect_0_peripheral_peripheral_bridge_s0_readdatavalid),       //                                                                  .readdatavalid
		.peripheral_peripheral_bridge_s0_waitrequest                             (mm_interconnect_0_peripheral_peripheral_bridge_s0_waitrequest),         //                                                                  .waitrequest
		.peripheral_peripheral_bridge_s0_debugaccess                             (mm_interconnect_0_peripheral_peripheral_bridge_s0_debugaccess),         //                                                                  .debugaccess
		.sdram_avl_address                                                       (mm_interconnect_0_sdram_avl_address),                                   //                                                         sdram_avl.address
		.sdram_avl_write                                                         (mm_interconnect_0_sdram_avl_write),                                     //                                                                  .write
		.sdram_avl_read                                                          (mm_interconnect_0_sdram_avl_read),                                      //                                                                  .read
		.sdram_avl_readdata                                                      (mm_interconnect_0_sdram_avl_readdata),                                  //                                                                  .readdata
		.sdram_avl_writedata                                                     (mm_interconnect_0_sdram_avl_writedata),                                 //                                                                  .writedata
		.sdram_avl_beginbursttransfer                                            (mm_interconnect_0_sdram_avl_beginbursttransfer),                        //                                                                  .beginbursttransfer
		.sdram_avl_burstcount                                                    (mm_interconnect_0_sdram_avl_burstcount),                                //                                                                  .burstcount
		.sdram_avl_byteenable                                                    (mm_interconnect_0_sdram_avl_byteenable),                                //                                                                  .byteenable
		.sdram_avl_readdatavalid                                                 (mm_interconnect_0_sdram_avl_readdatavalid),                             //                                                                  .readdatavalid
		.sdram_avl_waitrequest                                                   (~mm_interconnect_0_sdram_avl_waitrequest),                              //                                                                  .waitrequest
		.sysid_qsys_0_control_slave_address                                      (mm_interconnect_0_sysid_qsys_0_control_slave_address),                  //                                        sysid_qsys_0_control_slave.address
		.sysid_qsys_0_control_slave_readdata                                     (mm_interconnect_0_sysid_qsys_0_control_slave_readdata)                  //                                                                  .readdata
	);

	main_qsys_irq_mapper irq_mapper (
		.clk           (pll_0_outclk0_clk),                  //       clk.clk
		.reset         (rst_controller_001_reset_out_reset), // clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),           // receiver0.irq
		.receiver1_irq (irq_mapper_receiver1_irq),           // receiver1.irq
		.receiver2_irq (irq_mapper_receiver2_irq),           // receiver2.irq
		.receiver3_irq (irq_mapper_receiver3_irq),           // receiver3.irq
		.receiver4_irq (irq_mapper_receiver4_irq),           // receiver4.irq
		.receiver5_irq (irq_mapper_receiver5_irq),           // receiver5.irq
		.sender_irq    (nios2_irq_irq)                       //    sender.irq
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("none"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~reset_reset_n),                  // reset_in0.reset
		.reset_in1      (nios2_debug_reset_request_reset), // reset_in1.reset
		.clk            (),                                //       clk.clk
		.reset_out      (rst_controller_reset_out_reset),  // reset_out.reset
		.reset_req      (),                                // (terminated)
		.reset_req_in0  (1'b0),                            // (terminated)
		.reset_req_in1  (1'b0),                            // (terminated)
		.reset_in2      (1'b0),                            // (terminated)
		.reset_req_in2  (1'b0),                            // (terminated)
		.reset_in3      (1'b0),                            // (terminated)
		.reset_req_in3  (1'b0),                            // (terminated)
		.reset_in4      (1'b0),                            // (terminated)
		.reset_req_in4  (1'b0),                            // (terminated)
		.reset_in5      (1'b0),                            // (terminated)
		.reset_req_in5  (1'b0),                            // (terminated)
		.reset_in6      (1'b0),                            // (terminated)
		.reset_req_in6  (1'b0),                            // (terminated)
		.reset_in7      (1'b0),                            // (terminated)
		.reset_req_in7  (1'b0),                            // (terminated)
		.reset_in8      (1'b0),                            // (terminated)
		.reset_req_in8  (1'b0),                            // (terminated)
		.reset_in9      (1'b0),                            // (terminated)
		.reset_req_in9  (1'b0),                            // (terminated)
		.reset_in10     (1'b0),                            // (terminated)
		.reset_req_in10 (1'b0),                            // (terminated)
		.reset_in11     (1'b0),                            // (terminated)
		.reset_req_in11 (1'b0),                            // (terminated)
		.reset_in12     (1'b0),                            // (terminated)
		.reset_req_in12 (1'b0),                            // (terminated)
		.reset_in13     (1'b0),                            // (terminated)
		.reset_req_in13 (1'b0),                            // (terminated)
		.reset_in14     (1'b0),                            // (terminated)
		.reset_req_in14 (1'b0),                            // (terminated)
		.reset_in15     (1'b0),                            // (terminated)
		.reset_req_in15 (1'b0)                             // (terminated)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (1),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_001 (
		.reset_in0      (~reset_reset_n),                         // reset_in0.reset
		.reset_in1      (nios2_debug_reset_request_reset),        // reset_in1.reset
		.clk            (pll_0_outclk0_clk),                      //       clk.clk
		.reset_out      (rst_controller_001_reset_out_reset),     // reset_out.reset
		.reset_req      (rst_controller_001_reset_out_reset_req), //          .reset_req
		.reset_req_in0  (1'b0),                                   // (terminated)
		.reset_req_in1  (1'b0),                                   // (terminated)
		.reset_in2      (1'b0),                                   // (terminated)
		.reset_req_in2  (1'b0),                                   // (terminated)
		.reset_in3      (1'b0),                                   // (terminated)
		.reset_req_in3  (1'b0),                                   // (terminated)
		.reset_in4      (1'b0),                                   // (terminated)
		.reset_req_in4  (1'b0),                                   // (terminated)
		.reset_in5      (1'b0),                                   // (terminated)
		.reset_req_in5  (1'b0),                                   // (terminated)
		.reset_in6      (1'b0),                                   // (terminated)
		.reset_req_in6  (1'b0),                                   // (terminated)
		.reset_in7      (1'b0),                                   // (terminated)
		.reset_req_in7  (1'b0),                                   // (terminated)
		.reset_in8      (1'b0),                                   // (terminated)
		.reset_req_in8  (1'b0),                                   // (terminated)
		.reset_in9      (1'b0),                                   // (terminated)
		.reset_req_in9  (1'b0),                                   // (terminated)
		.reset_in10     (1'b0),                                   // (terminated)
		.reset_req_in10 (1'b0),                                   // (terminated)
		.reset_in11     (1'b0),                                   // (terminated)
		.reset_req_in11 (1'b0),                                   // (terminated)
		.reset_in12     (1'b0),                                   // (terminated)
		.reset_req_in12 (1'b0),                                   // (terminated)
		.reset_in13     (1'b0),                                   // (terminated)
		.reset_req_in13 (1'b0),                                   // (terminated)
		.reset_in14     (1'b0),                                   // (terminated)
		.reset_req_in14 (1'b0),                                   // (terminated)
		.reset_in15     (1'b0),                                   // (terminated)
		.reset_req_in15 (1'b0)                                    // (terminated)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("none"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_002 (
		.reset_in0      (~reset_reset_n),                     // reset_in0.reset
		.reset_in1      (nios2_debug_reset_request_reset),    // reset_in1.reset
		.clk            (),                                   //       clk.clk
		.reset_out      (rst_controller_002_reset_out_reset), // reset_out.reset
		.reset_req      (),                                   // (terminated)
		.reset_req_in0  (1'b0),                               // (terminated)
		.reset_req_in1  (1'b0),                               // (terminated)
		.reset_in2      (1'b0),                               // (terminated)
		.reset_req_in2  (1'b0),                               // (terminated)
		.reset_in3      (1'b0),                               // (terminated)
		.reset_req_in3  (1'b0),                               // (terminated)
		.reset_in4      (1'b0),                               // (terminated)
		.reset_req_in4  (1'b0),                               // (terminated)
		.reset_in5      (1'b0),                               // (terminated)
		.reset_req_in5  (1'b0),                               // (terminated)
		.reset_in6      (1'b0),                               // (terminated)
		.reset_req_in6  (1'b0),                               // (terminated)
		.reset_in7      (1'b0),                               // (terminated)
		.reset_req_in7  (1'b0),                               // (terminated)
		.reset_in8      (1'b0),                               // (terminated)
		.reset_req_in8  (1'b0),                               // (terminated)
		.reset_in9      (1'b0),                               // (terminated)
		.reset_req_in9  (1'b0),                               // (terminated)
		.reset_in10     (1'b0),                               // (terminated)
		.reset_req_in10 (1'b0),                               // (terminated)
		.reset_in11     (1'b0),                               // (terminated)
		.reset_req_in11 (1'b0),                               // (terminated)
		.reset_in12     (1'b0),                               // (terminated)
		.reset_req_in12 (1'b0),                               // (terminated)
		.reset_in13     (1'b0),                               // (terminated)
		.reset_req_in13 (1'b0),                               // (terminated)
		.reset_in14     (1'b0),                               // (terminated)
		.reset_req_in14 (1'b0),                               // (terminated)
		.reset_in15     (1'b0),                               // (terminated)
		.reset_req_in15 (1'b0)                                // (terminated)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_003 (
		.reset_in0      (~reset_reset_n),                     // reset_in0.reset
		.clk            (pll_0_outclk0_clk),                  //       clk.clk
		.reset_out      (rst_controller_003_reset_out_reset), // reset_out.reset
		.reset_req      (),                                   // (terminated)
		.reset_req_in0  (1'b0),                               // (terminated)
		.reset_in1      (1'b0),                               // (terminated)
		.reset_req_in1  (1'b0),                               // (terminated)
		.reset_in2      (1'b0),                               // (terminated)
		.reset_req_in2  (1'b0),                               // (terminated)
		.reset_in3      (1'b0),                               // (terminated)
		.reset_req_in3  (1'b0),                               // (terminated)
		.reset_in4      (1'b0),                               // (terminated)
		.reset_req_in4  (1'b0),                               // (terminated)
		.reset_in5      (1'b0),                               // (terminated)
		.reset_req_in5  (1'b0),                               // (terminated)
		.reset_in6      (1'b0),                               // (terminated)
		.reset_req_in6  (1'b0),                               // (terminated)
		.reset_in7      (1'b0),                               // (terminated)
		.reset_req_in7  (1'b0),                               // (terminated)
		.reset_in8      (1'b0),                               // (terminated)
		.reset_req_in8  (1'b0),                               // (terminated)
		.reset_in9      (1'b0),                               // (terminated)
		.reset_req_in9  (1'b0),                               // (terminated)
		.reset_in10     (1'b0),                               // (terminated)
		.reset_req_in10 (1'b0),                               // (terminated)
		.reset_in11     (1'b0),                               // (terminated)
		.reset_req_in11 (1'b0),                               // (terminated)
		.reset_in12     (1'b0),                               // (terminated)
		.reset_req_in12 (1'b0),                               // (terminated)
		.reset_in13     (1'b0),                               // (terminated)
		.reset_req_in13 (1'b0),                               // (terminated)
		.reset_in14     (1'b0),                               // (terminated)
		.reset_req_in14 (1'b0),                               // (terminated)
		.reset_in15     (1'b0),                               // (terminated)
		.reset_req_in15 (1'b0)                                // (terminated)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_004 (
		.reset_in0      (~reset_reset_n),                     // reset_in0.reset
		.clk            (sdram_afi_clk_clk),                  //       clk.clk
		.reset_out      (rst_controller_004_reset_out_reset), // reset_out.reset
		.reset_req      (),                                   // (terminated)
		.reset_req_in0  (1'b0),                               // (terminated)
		.reset_in1      (1'b0),                               // (terminated)
		.reset_req_in1  (1'b0),                               // (terminated)
		.reset_in2      (1'b0),                               // (terminated)
		.reset_req_in2  (1'b0),                               // (terminated)
		.reset_in3      (1'b0),                               // (terminated)
		.reset_req_in3  (1'b0),                               // (terminated)
		.reset_in4      (1'b0),                               // (terminated)
		.reset_req_in4  (1'b0),                               // (terminated)
		.reset_in5      (1'b0),                               // (terminated)
		.reset_req_in5  (1'b0),                               // (terminated)
		.reset_in6      (1'b0),                               // (terminated)
		.reset_req_in6  (1'b0),                               // (terminated)
		.reset_in7      (1'b0),                               // (terminated)
		.reset_req_in7  (1'b0),                               // (terminated)
		.reset_in8      (1'b0),                               // (terminated)
		.reset_req_in8  (1'b0),                               // (terminated)
		.reset_in9      (1'b0),                               // (terminated)
		.reset_req_in9  (1'b0),                               // (terminated)
		.reset_in10     (1'b0),                               // (terminated)
		.reset_req_in10 (1'b0),                               // (terminated)
		.reset_in11     (1'b0),                               // (terminated)
		.reset_req_in11 (1'b0),                               // (terminated)
		.reset_in12     (1'b0),                               // (terminated)
		.reset_req_in12 (1'b0),                               // (terminated)
		.reset_in13     (1'b0),                               // (terminated)
		.reset_req_in13 (1'b0),                               // (terminated)
		.reset_in14     (1'b0),                               // (terminated)
		.reset_req_in14 (1'b0),                               // (terminated)
		.reset_in15     (1'b0),                               // (terminated)
		.reset_req_in15 (1'b0)                                // (terminated)
	);

endmodule
