// main_qsys_ethernet_subsystem.v

// Generated using ACDS version 18.1 625

`timescale 1 ps / 1 ps
module main_qsys_ethernet_subsystem (
		input  wire [10:0] descriptor_memory_s2_address,      //     descriptor_memory_s2.address
		input  wire        descriptor_memory_s2_chipselect,   //                         .chipselect
		input  wire        descriptor_memory_s2_clken,        //                         .clken
		input  wire        descriptor_memory_s2_write,        //                         .write
		output wire [31:0] descriptor_memory_s2_readdata,     //                         .readdata
		input  wire [31:0] descriptor_memory_s2_writedata,    //                         .writedata
		input  wire [3:0]  descriptor_memory_s2_byteenable,   //                         .byteenable
		output wire        ethernet_bridge_s0_waitrequest,    //       ethernet_bridge_s0.waitrequest
		output wire [31:0] ethernet_bridge_s0_readdata,       //                         .readdata
		output wire        ethernet_bridge_s0_readdatavalid,  //                         .readdatavalid
		input  wire [0:0]  ethernet_bridge_s0_burstcount,     //                         .burstcount
		input  wire [31:0] ethernet_bridge_s0_writedata,      //                         .writedata
		input  wire [10:0] ethernet_bridge_s0_address,        //                         .address
		input  wire        ethernet_bridge_s0_write,          //                         .write
		input  wire        ethernet_bridge_s0_read,           //                         .read
		input  wire [3:0]  ethernet_bridge_s0_byteenable,     //                         .byteenable
		input  wire        ethernet_bridge_s0_debugaccess,    //                         .debugaccess
		input  wire        ethernet_subsys_clk_in_clk,        //   ethernet_subsys_clk_in.clk
		input  wire        ethernet_subsys_reset_in_reset_n,  // ethernet_subsys_reset_in.reset_n
		output wire        mac_mdio_connection_mdc,           //      mac_mdio_connection.mdc
		input  wire        mac_mdio_connection_mdio_in,       //                         .mdio_in
		output wire        mac_mdio_connection_mdio_out,      //                         .mdio_out
		output wire        mac_mdio_connection_mdio_oen,      //                         .mdio_oen
		input  wire        mac_misc_connection_xon_gen,       //      mac_misc_connection.xon_gen
		input  wire        mac_misc_connection_xoff_gen,      //                         .xoff_gen
		input  wire        mac_misc_connection_ff_tx_crc_fwd, //                         .ff_tx_crc_fwd
		output wire        mac_misc_connection_ff_tx_septy,   //                         .ff_tx_septy
		output wire        mac_misc_connection_tx_ff_uflow,   //                         .tx_ff_uflow
		output wire        mac_misc_connection_ff_tx_a_full,  //                         .ff_tx_a_full
		output wire        mac_misc_connection_ff_tx_a_empty, //                         .ff_tx_a_empty
		output wire [17:0] mac_misc_connection_rx_err_stat,   //                         .rx_err_stat
		output wire [3:0]  mac_misc_connection_rx_frm_type,   //                         .rx_frm_type
		output wire        mac_misc_connection_ff_rx_dsav,    //                         .ff_rx_dsav
		output wire        mac_misc_connection_ff_rx_a_full,  //                         .ff_rx_a_full
		output wire        mac_misc_connection_ff_rx_a_empty, //                         .ff_rx_a_empty
		input  wire [3:0]  mac_rgmii_connection_rgmii_in,     //     mac_rgmii_connection.rgmii_in
		output wire [3:0]  mac_rgmii_connection_rgmii_out,    //                         .rgmii_out
		input  wire        mac_rgmii_connection_rx_control,   //                         .rx_control
		output wire        mac_rgmii_connection_tx_control,   //                         .tx_control
		input  wire        mac_status_connection_set_10,      //    mac_status_connection.set_10
		input  wire        mac_status_connection_set_1000,    //                         .set_1000
		output wire        mac_status_connection_eth_mode,    //                         .eth_mode
		output wire        mac_status_connection_ena_10,      //                         .ena_10
		input  wire        rx_clock_clk,                      //                 rx_clock.clk
		input  wire        sgdma_bridge_m0_waitrequest,       //          sgdma_bridge_m0.waitrequest
		input  wire [31:0] sgdma_bridge_m0_readdata,          //                         .readdata
		input  wire        sgdma_bridge_m0_readdatavalid,     //                         .readdatavalid
		output wire [0:0]  sgdma_bridge_m0_burstcount,        //                         .burstcount
		output wire [31:0] sgdma_bridge_m0_writedata,         //                         .writedata
		output wire [30:0] sgdma_bridge_m0_address,           //                         .address
		output wire        sgdma_bridge_m0_write,             //                         .write
		output wire        sgdma_bridge_m0_read,              //                         .read
		output wire [3:0]  sgdma_bridge_m0_byteenable,        //                         .byteenable
		output wire        sgdma_bridge_m0_debugaccess,       //                         .debugaccess
		output wire        sgdma_rx_csr_irq_irq,              //         sgdma_rx_csr_irq.irq
		output wire        sgdma_tx_csr_irq_irq,              //         sgdma_tx_csr_irq.irq
		input  wire        tx_clock_clk                       //                 tx_clock.clk
	);

	wire         msgdma_tx_st_source_valid;                            // msgdma_tx:st_source_valid -> tse_mac:ff_tx_wren
	wire  [31:0] msgdma_tx_st_source_data;                             // msgdma_tx:st_source_data -> tse_mac:ff_tx_data
	wire         msgdma_tx_st_source_ready;                            // tse_mac:ff_tx_rdy -> msgdma_tx:st_source_ready
	wire         msgdma_tx_st_source_startofpacket;                    // msgdma_tx:st_source_startofpacket -> tse_mac:ff_tx_sop
	wire         msgdma_tx_st_source_endofpacket;                      // msgdma_tx:st_source_endofpacket -> tse_mac:ff_tx_eop
	wire         msgdma_tx_st_source_error;                            // msgdma_tx:st_source_error -> tse_mac:ff_tx_err
	wire   [1:0] msgdma_tx_st_source_empty;                            // msgdma_tx:st_source_empty -> tse_mac:ff_tx_mod
	wire  [31:0] msgdma_rx_descriptor_read_master_readdata;            // mm_interconnect_0:msgdma_rx_descriptor_read_master_readdata -> msgdma_rx:descriptor_read_master_readdata
	wire         msgdma_rx_descriptor_read_master_waitrequest;         // mm_interconnect_0:msgdma_rx_descriptor_read_master_waitrequest -> msgdma_rx:descriptor_read_master_waitrequest
	wire  [12:0] msgdma_rx_descriptor_read_master_address;             // msgdma_rx:descriptor_read_master_address -> mm_interconnect_0:msgdma_rx_descriptor_read_master_address
	wire         msgdma_rx_descriptor_read_master_read;                // msgdma_rx:descriptor_read_master_read -> mm_interconnect_0:msgdma_rx_descriptor_read_master_read
	wire         msgdma_rx_descriptor_read_master_readdatavalid;       // mm_interconnect_0:msgdma_rx_descriptor_read_master_readdatavalid -> msgdma_rx:descriptor_read_master_readdatavalid
	wire  [31:0] msgdma_tx_descriptor_read_master_readdata;            // mm_interconnect_0:msgdma_tx_descriptor_read_master_readdata -> msgdma_tx:descriptor_read_master_readdata
	wire         msgdma_tx_descriptor_read_master_waitrequest;         // mm_interconnect_0:msgdma_tx_descriptor_read_master_waitrequest -> msgdma_tx:descriptor_read_master_waitrequest
	wire  [12:0] msgdma_tx_descriptor_read_master_address;             // msgdma_tx:descriptor_read_master_address -> mm_interconnect_0:msgdma_tx_descriptor_read_master_address
	wire         msgdma_tx_descriptor_read_master_read;                // msgdma_tx:descriptor_read_master_read -> mm_interconnect_0:msgdma_tx_descriptor_read_master_read
	wire         msgdma_tx_descriptor_read_master_readdatavalid;       // mm_interconnect_0:msgdma_tx_descriptor_read_master_readdatavalid -> msgdma_tx:descriptor_read_master_readdatavalid
	wire         msgdma_rx_descriptor_write_master_waitrequest;        // mm_interconnect_0:msgdma_rx_descriptor_write_master_waitrequest -> msgdma_rx:descriptor_write_master_waitrequest
	wire  [12:0] msgdma_rx_descriptor_write_master_address;            // msgdma_rx:descriptor_write_master_address -> mm_interconnect_0:msgdma_rx_descriptor_write_master_address
	wire   [3:0] msgdma_rx_descriptor_write_master_byteenable;         // msgdma_rx:descriptor_write_master_byteenable -> mm_interconnect_0:msgdma_rx_descriptor_write_master_byteenable
	wire   [1:0] msgdma_rx_descriptor_write_master_response;           // mm_interconnect_0:msgdma_rx_descriptor_write_master_response -> msgdma_rx:descriptor_write_master_response
	wire         msgdma_rx_descriptor_write_master_write;              // msgdma_rx:descriptor_write_master_write -> mm_interconnect_0:msgdma_rx_descriptor_write_master_write
	wire  [31:0] msgdma_rx_descriptor_write_master_writedata;          // msgdma_rx:descriptor_write_master_writedata -> mm_interconnect_0:msgdma_rx_descriptor_write_master_writedata
	wire         msgdma_rx_descriptor_write_master_writeresponsevalid; // mm_interconnect_0:msgdma_rx_descriptor_write_master_writeresponsevalid -> msgdma_rx:descriptor_write_master_writeresponsevalid
	wire         msgdma_tx_descriptor_write_master_waitrequest;        // mm_interconnect_0:msgdma_tx_descriptor_write_master_waitrequest -> msgdma_tx:descriptor_write_master_waitrequest
	wire  [12:0] msgdma_tx_descriptor_write_master_address;            // msgdma_tx:descriptor_write_master_address -> mm_interconnect_0:msgdma_tx_descriptor_write_master_address
	wire   [3:0] msgdma_tx_descriptor_write_master_byteenable;         // msgdma_tx:descriptor_write_master_byteenable -> mm_interconnect_0:msgdma_tx_descriptor_write_master_byteenable
	wire   [1:0] msgdma_tx_descriptor_write_master_response;           // mm_interconnect_0:msgdma_tx_descriptor_write_master_response -> msgdma_tx:descriptor_write_master_response
	wire         msgdma_tx_descriptor_write_master_write;              // msgdma_tx:descriptor_write_master_write -> mm_interconnect_0:msgdma_tx_descriptor_write_master_write
	wire  [31:0] msgdma_tx_descriptor_write_master_writedata;          // msgdma_tx:descriptor_write_master_writedata -> mm_interconnect_0:msgdma_tx_descriptor_write_master_writedata
	wire         msgdma_tx_descriptor_write_master_writeresponsevalid; // mm_interconnect_0:msgdma_tx_descriptor_write_master_writeresponsevalid -> msgdma_tx:descriptor_write_master_writeresponsevalid
	wire         mm_interconnect_0_descriptor_memory_s1_chipselect;    // mm_interconnect_0:descriptor_memory_s1_chipselect -> descriptor_memory:chipselect
	wire  [31:0] mm_interconnect_0_descriptor_memory_s1_readdata;      // descriptor_memory:readdata -> mm_interconnect_0:descriptor_memory_s1_readdata
	wire  [10:0] mm_interconnect_0_descriptor_memory_s1_address;       // mm_interconnect_0:descriptor_memory_s1_address -> descriptor_memory:address
	wire   [3:0] mm_interconnect_0_descriptor_memory_s1_byteenable;    // mm_interconnect_0:descriptor_memory_s1_byteenable -> descriptor_memory:byteenable
	wire         mm_interconnect_0_descriptor_memory_s1_write;         // mm_interconnect_0:descriptor_memory_s1_write -> descriptor_memory:write
	wire  [31:0] mm_interconnect_0_descriptor_memory_s1_writedata;     // mm_interconnect_0:descriptor_memory_s1_writedata -> descriptor_memory:writedata
	wire         mm_interconnect_0_descriptor_memory_s1_clken;         // mm_interconnect_0:descriptor_memory_s1_clken -> descriptor_memory:clken
	wire         ethernet_bridge_m0_waitrequest;                       // mm_interconnect_1:ethernet_bridge_m0_waitrequest -> ethernet_bridge:m0_waitrequest
	wire  [31:0] ethernet_bridge_m0_readdata;                          // mm_interconnect_1:ethernet_bridge_m0_readdata -> ethernet_bridge:m0_readdata
	wire         ethernet_bridge_m0_debugaccess;                       // ethernet_bridge:m0_debugaccess -> mm_interconnect_1:ethernet_bridge_m0_debugaccess
	wire  [10:0] ethernet_bridge_m0_address;                           // ethernet_bridge:m0_address -> mm_interconnect_1:ethernet_bridge_m0_address
	wire         ethernet_bridge_m0_read;                              // ethernet_bridge:m0_read -> mm_interconnect_1:ethernet_bridge_m0_read
	wire   [3:0] ethernet_bridge_m0_byteenable;                        // ethernet_bridge:m0_byteenable -> mm_interconnect_1:ethernet_bridge_m0_byteenable
	wire         ethernet_bridge_m0_readdatavalid;                     // mm_interconnect_1:ethernet_bridge_m0_readdatavalid -> ethernet_bridge:m0_readdatavalid
	wire  [31:0] ethernet_bridge_m0_writedata;                         // ethernet_bridge:m0_writedata -> mm_interconnect_1:ethernet_bridge_m0_writedata
	wire         ethernet_bridge_m0_write;                             // ethernet_bridge:m0_write -> mm_interconnect_1:ethernet_bridge_m0_write
	wire   [0:0] ethernet_bridge_m0_burstcount;                        // ethernet_bridge:m0_burstcount -> mm_interconnect_1:ethernet_bridge_m0_burstcount
	wire  [31:0] mm_interconnect_1_tse_mac_control_port_readdata;      // tse_mac:reg_data_out -> mm_interconnect_1:tse_mac_control_port_readdata
	wire         mm_interconnect_1_tse_mac_control_port_waitrequest;   // tse_mac:reg_busy -> mm_interconnect_1:tse_mac_control_port_waitrequest
	wire   [7:0] mm_interconnect_1_tse_mac_control_port_address;       // mm_interconnect_1:tse_mac_control_port_address -> tse_mac:reg_addr
	wire         mm_interconnect_1_tse_mac_control_port_read;          // mm_interconnect_1:tse_mac_control_port_read -> tse_mac:reg_rd
	wire         mm_interconnect_1_tse_mac_control_port_write;         // mm_interconnect_1:tse_mac_control_port_write -> tse_mac:reg_wr
	wire  [31:0] mm_interconnect_1_tse_mac_control_port_writedata;     // mm_interconnect_1:tse_mac_control_port_writedata -> tse_mac:reg_data_in
	wire  [31:0] mm_interconnect_1_msgdma_rx_csr_readdata;             // msgdma_rx:csr_readdata -> mm_interconnect_1:msgdma_rx_csr_readdata
	wire   [2:0] mm_interconnect_1_msgdma_rx_csr_address;              // mm_interconnect_1:msgdma_rx_csr_address -> msgdma_rx:csr_address
	wire         mm_interconnect_1_msgdma_rx_csr_read;                 // mm_interconnect_1:msgdma_rx_csr_read -> msgdma_rx:csr_read
	wire   [3:0] mm_interconnect_1_msgdma_rx_csr_byteenable;           // mm_interconnect_1:msgdma_rx_csr_byteenable -> msgdma_rx:csr_byteenable
	wire         mm_interconnect_1_msgdma_rx_csr_write;                // mm_interconnect_1:msgdma_rx_csr_write -> msgdma_rx:csr_write
	wire  [31:0] mm_interconnect_1_msgdma_rx_csr_writedata;            // mm_interconnect_1:msgdma_rx_csr_writedata -> msgdma_rx:csr_writedata
	wire  [31:0] mm_interconnect_1_msgdma_tx_csr_readdata;             // msgdma_tx:csr_readdata -> mm_interconnect_1:msgdma_tx_csr_readdata
	wire   [2:0] mm_interconnect_1_msgdma_tx_csr_address;              // mm_interconnect_1:msgdma_tx_csr_address -> msgdma_tx:csr_address
	wire         mm_interconnect_1_msgdma_tx_csr_read;                 // mm_interconnect_1:msgdma_tx_csr_read -> msgdma_tx:csr_read
	wire   [3:0] mm_interconnect_1_msgdma_tx_csr_byteenable;           // mm_interconnect_1:msgdma_tx_csr_byteenable -> msgdma_tx:csr_byteenable
	wire         mm_interconnect_1_msgdma_tx_csr_write;                // mm_interconnect_1:msgdma_tx_csr_write -> msgdma_tx:csr_write
	wire  [31:0] mm_interconnect_1_msgdma_tx_csr_writedata;            // mm_interconnect_1:msgdma_tx_csr_writedata -> msgdma_tx:csr_writedata
	wire  [31:0] mm_interconnect_1_msgdma_rx_prefetcher_csr_readdata;  // msgdma_rx:prefetcher_csr_readdata -> mm_interconnect_1:msgdma_rx_prefetcher_csr_readdata
	wire   [2:0] mm_interconnect_1_msgdma_rx_prefetcher_csr_address;   // mm_interconnect_1:msgdma_rx_prefetcher_csr_address -> msgdma_rx:prefetcher_csr_address
	wire         mm_interconnect_1_msgdma_rx_prefetcher_csr_read;      // mm_interconnect_1:msgdma_rx_prefetcher_csr_read -> msgdma_rx:prefetcher_csr_read
	wire         mm_interconnect_1_msgdma_rx_prefetcher_csr_write;     // mm_interconnect_1:msgdma_rx_prefetcher_csr_write -> msgdma_rx:prefetcher_csr_write
	wire  [31:0] mm_interconnect_1_msgdma_rx_prefetcher_csr_writedata; // mm_interconnect_1:msgdma_rx_prefetcher_csr_writedata -> msgdma_rx:prefetcher_csr_writedata
	wire  [31:0] mm_interconnect_1_msgdma_tx_prefetcher_csr_readdata;  // msgdma_tx:prefetcher_csr_readdata -> mm_interconnect_1:msgdma_tx_prefetcher_csr_readdata
	wire   [2:0] mm_interconnect_1_msgdma_tx_prefetcher_csr_address;   // mm_interconnect_1:msgdma_tx_prefetcher_csr_address -> msgdma_tx:prefetcher_csr_address
	wire         mm_interconnect_1_msgdma_tx_prefetcher_csr_read;      // mm_interconnect_1:msgdma_tx_prefetcher_csr_read -> msgdma_tx:prefetcher_csr_read
	wire         mm_interconnect_1_msgdma_tx_prefetcher_csr_write;     // mm_interconnect_1:msgdma_tx_prefetcher_csr_write -> msgdma_tx:prefetcher_csr_write
	wire  [31:0] mm_interconnect_1_msgdma_tx_prefetcher_csr_writedata; // mm_interconnect_1:msgdma_tx_prefetcher_csr_writedata -> msgdma_tx:prefetcher_csr_writedata
	wire  [31:0] msgdma_tx_mm_read_readdata;                           // mm_interconnect_2:msgdma_tx_mm_read_readdata -> msgdma_tx:mm_read_readdata
	wire         msgdma_tx_mm_read_waitrequest;                        // mm_interconnect_2:msgdma_tx_mm_read_waitrequest -> msgdma_tx:mm_read_waitrequest
	wire  [30:0] msgdma_tx_mm_read_address;                            // msgdma_tx:mm_read_address -> mm_interconnect_2:msgdma_tx_mm_read_address
	wire         msgdma_tx_mm_read_read;                               // msgdma_tx:mm_read_read -> mm_interconnect_2:msgdma_tx_mm_read_read
	wire   [3:0] msgdma_tx_mm_read_byteenable;                         // msgdma_tx:mm_read_byteenable -> mm_interconnect_2:msgdma_tx_mm_read_byteenable
	wire         msgdma_tx_mm_read_readdatavalid;                      // mm_interconnect_2:msgdma_tx_mm_read_readdatavalid -> msgdma_tx:mm_read_readdatavalid
	wire         msgdma_rx_mm_write_waitrequest;                       // mm_interconnect_2:msgdma_rx_mm_write_waitrequest -> msgdma_rx:mm_write_waitrequest
	wire  [30:0] msgdma_rx_mm_write_address;                           // msgdma_rx:mm_write_address -> mm_interconnect_2:msgdma_rx_mm_write_address
	wire   [3:0] msgdma_rx_mm_write_byteenable;                        // msgdma_rx:mm_write_byteenable -> mm_interconnect_2:msgdma_rx_mm_write_byteenable
	wire         msgdma_rx_mm_write_write;                             // msgdma_rx:mm_write_write -> mm_interconnect_2:msgdma_rx_mm_write_write
	wire  [31:0] msgdma_rx_mm_write_writedata;                         // msgdma_rx:mm_write_writedata -> mm_interconnect_2:msgdma_rx_mm_write_writedata
	wire  [31:0] mm_interconnect_2_sgdma_bridge_s0_readdata;           // sgdma_bridge:s0_readdata -> mm_interconnect_2:sgdma_bridge_s0_readdata
	wire         mm_interconnect_2_sgdma_bridge_s0_waitrequest;        // sgdma_bridge:s0_waitrequest -> mm_interconnect_2:sgdma_bridge_s0_waitrequest
	wire         mm_interconnect_2_sgdma_bridge_s0_debugaccess;        // mm_interconnect_2:sgdma_bridge_s0_debugaccess -> sgdma_bridge:s0_debugaccess
	wire  [30:0] mm_interconnect_2_sgdma_bridge_s0_address;            // mm_interconnect_2:sgdma_bridge_s0_address -> sgdma_bridge:s0_address
	wire         mm_interconnect_2_sgdma_bridge_s0_read;               // mm_interconnect_2:sgdma_bridge_s0_read -> sgdma_bridge:s0_read
	wire   [3:0] mm_interconnect_2_sgdma_bridge_s0_byteenable;         // mm_interconnect_2:sgdma_bridge_s0_byteenable -> sgdma_bridge:s0_byteenable
	wire         mm_interconnect_2_sgdma_bridge_s0_readdatavalid;      // sgdma_bridge:s0_readdatavalid -> mm_interconnect_2:sgdma_bridge_s0_readdatavalid
	wire         mm_interconnect_2_sgdma_bridge_s0_write;              // mm_interconnect_2:sgdma_bridge_s0_write -> sgdma_bridge:s0_write
	wire  [31:0] mm_interconnect_2_sgdma_bridge_s0_writedata;          // mm_interconnect_2:sgdma_bridge_s0_writedata -> sgdma_bridge:s0_writedata
	wire   [0:0] mm_interconnect_2_sgdma_bridge_s0_burstcount;         // mm_interconnect_2:sgdma_bridge_s0_burstcount -> sgdma_bridge:s0_burstcount
	wire         tse_mac_receive_valid;                                // tse_mac:ff_rx_dval -> avalon_st_adapter:in_0_valid
	wire  [31:0] tse_mac_receive_data;                                 // tse_mac:ff_rx_data -> avalon_st_adapter:in_0_data
	wire         tse_mac_receive_ready;                                // avalon_st_adapter:in_0_ready -> tse_mac:ff_rx_rdy
	wire         tse_mac_receive_startofpacket;                        // tse_mac:ff_rx_sop -> avalon_st_adapter:in_0_startofpacket
	wire         tse_mac_receive_endofpacket;                          // tse_mac:ff_rx_eop -> avalon_st_adapter:in_0_endofpacket
	wire   [5:0] tse_mac_receive_error;                                // tse_mac:rx_err -> avalon_st_adapter:in_0_error
	wire   [1:0] tse_mac_receive_empty;                                // tse_mac:ff_rx_mod -> avalon_st_adapter:in_0_empty
	wire         avalon_st_adapter_out_0_valid;                        // avalon_st_adapter:out_0_valid -> msgdma_rx:st_sink_valid
	wire  [31:0] avalon_st_adapter_out_0_data;                         // avalon_st_adapter:out_0_data -> msgdma_rx:st_sink_data
	wire         avalon_st_adapter_out_0_ready;                        // msgdma_rx:st_sink_ready -> avalon_st_adapter:out_0_ready
	wire         avalon_st_adapter_out_0_startofpacket;                // avalon_st_adapter:out_0_startofpacket -> msgdma_rx:st_sink_startofpacket
	wire         avalon_st_adapter_out_0_endofpacket;                  // avalon_st_adapter:out_0_endofpacket -> msgdma_rx:st_sink_endofpacket
	wire   [5:0] avalon_st_adapter_out_0_error;                        // avalon_st_adapter:out_0_error -> msgdma_rx:st_sink_error
	wire   [1:0] avalon_st_adapter_out_0_empty;                        // avalon_st_adapter:out_0_empty -> msgdma_rx:st_sink_empty
	wire         rst_controller_reset_out_reset;                       // rst_controller:reset_out -> [avalon_st_adapter:in_rst_0_reset, descriptor_memory:reset, descriptor_memory:reset2, ethernet_bridge:reset, mm_interconnect_0:msgdma_rx_reset_n_reset_bridge_in_reset_reset, mm_interconnect_1:ethernet_bridge_reset_reset_bridge_in_reset_reset, mm_interconnect_2:msgdma_tx_reset_n_reset_bridge_in_reset_reset, msgdma_rx:reset_n_reset_n, msgdma_tx:reset_n_reset_n, rst_translator:in_reset, sgdma_bridge:reset, tse_mac:reset]
	wire         rst_controller_reset_out_reset_req;                   // rst_controller:reset_req -> [descriptor_memory:reset_req, descriptor_memory:reset_req2, rst_translator:reset_req_in]

	main_qsys_ethernet_subsystem_descriptor_memory descriptor_memory (
		.clk         (ethernet_subsys_clk_in_clk),                        //   clk1.clk
		.address     (mm_interconnect_0_descriptor_memory_s1_address),    //     s1.address
		.clken       (mm_interconnect_0_descriptor_memory_s1_clken),      //       .clken
		.chipselect  (mm_interconnect_0_descriptor_memory_s1_chipselect), //       .chipselect
		.write       (mm_interconnect_0_descriptor_memory_s1_write),      //       .write
		.readdata    (mm_interconnect_0_descriptor_memory_s1_readdata),   //       .readdata
		.writedata   (mm_interconnect_0_descriptor_memory_s1_writedata),  //       .writedata
		.byteenable  (mm_interconnect_0_descriptor_memory_s1_byteenable), //       .byteenable
		.reset       (rst_controller_reset_out_reset),                    // reset1.reset
		.reset_req   (rst_controller_reset_out_reset_req),                //       .reset_req
		.address2    (descriptor_memory_s2_address),                      //     s2.address
		.chipselect2 (descriptor_memory_s2_chipselect),                   //       .chipselect
		.clken2      (descriptor_memory_s2_clken),                        //       .clken
		.write2      (descriptor_memory_s2_write),                        //       .write
		.readdata2   (descriptor_memory_s2_readdata),                     //       .readdata
		.writedata2  (descriptor_memory_s2_writedata),                    //       .writedata
		.byteenable2 (descriptor_memory_s2_byteenable),                   //       .byteenable
		.clk2        (ethernet_subsys_clk_in_clk),                        //   clk2.clk
		.reset2      (rst_controller_reset_out_reset),                    // reset2.reset
		.reset_req2  (rst_controller_reset_out_reset_req),                //       .reset_req
		.freeze      (1'b0)                                               // (terminated)
	);

	altera_avalon_mm_bridge #(
		.DATA_WIDTH        (32),
		.SYMBOL_WIDTH      (8),
		.HDL_ADDR_WIDTH    (11),
		.BURSTCOUNT_WIDTH  (1),
		.PIPELINE_COMMAND  (1),
		.PIPELINE_RESPONSE (1)
	) ethernet_bridge (
		.clk              (ethernet_subsys_clk_in_clk),       //   clk.clk
		.reset            (rst_controller_reset_out_reset),   // reset.reset
		.s0_waitrequest   (ethernet_bridge_s0_waitrequest),   //    s0.waitrequest
		.s0_readdata      (ethernet_bridge_s0_readdata),      //      .readdata
		.s0_readdatavalid (ethernet_bridge_s0_readdatavalid), //      .readdatavalid
		.s0_burstcount    (ethernet_bridge_s0_burstcount),    //      .burstcount
		.s0_writedata     (ethernet_bridge_s0_writedata),     //      .writedata
		.s0_address       (ethernet_bridge_s0_address),       //      .address
		.s0_write         (ethernet_bridge_s0_write),         //      .write
		.s0_read          (ethernet_bridge_s0_read),          //      .read
		.s0_byteenable    (ethernet_bridge_s0_byteenable),    //      .byteenable
		.s0_debugaccess   (ethernet_bridge_s0_debugaccess),   //      .debugaccess
		.m0_waitrequest   (ethernet_bridge_m0_waitrequest),   //    m0.waitrequest
		.m0_readdata      (ethernet_bridge_m0_readdata),      //      .readdata
		.m0_readdatavalid (ethernet_bridge_m0_readdatavalid), //      .readdatavalid
		.m0_burstcount    (ethernet_bridge_m0_burstcount),    //      .burstcount
		.m0_writedata     (ethernet_bridge_m0_writedata),     //      .writedata
		.m0_address       (ethernet_bridge_m0_address),       //      .address
		.m0_write         (ethernet_bridge_m0_write),         //      .write
		.m0_read          (ethernet_bridge_m0_read),          //      .read
		.m0_byteenable    (ethernet_bridge_m0_byteenable),    //      .byteenable
		.m0_debugaccess   (ethernet_bridge_m0_debugaccess),   //      .debugaccess
		.s0_response      (),                                 // (terminated)
		.m0_response      (2'b00)                             // (terminated)
	);

	main_qsys_ethernet_subsystem_msgdma_rx msgdma_rx (
		.mm_write_address                           (msgdma_rx_mm_write_address),                           //                mm_write.address
		.mm_write_write                             (msgdma_rx_mm_write_write),                             //                        .write
		.mm_write_byteenable                        (msgdma_rx_mm_write_byteenable),                        //                        .byteenable
		.mm_write_writedata                         (msgdma_rx_mm_write_writedata),                         //                        .writedata
		.mm_write_waitrequest                       (msgdma_rx_mm_write_waitrequest),                       //                        .waitrequest
		.descriptor_read_master_address             (msgdma_rx_descriptor_read_master_address),             //  descriptor_read_master.address
		.descriptor_read_master_read                (msgdma_rx_descriptor_read_master_read),                //                        .read
		.descriptor_read_master_readdata            (msgdma_rx_descriptor_read_master_readdata),            //                        .readdata
		.descriptor_read_master_waitrequest         (msgdma_rx_descriptor_read_master_waitrequest),         //                        .waitrequest
		.descriptor_read_master_readdatavalid       (msgdma_rx_descriptor_read_master_readdatavalid),       //                        .readdatavalid
		.descriptor_write_master_address            (msgdma_rx_descriptor_write_master_address),            // descriptor_write_master.address
		.descriptor_write_master_write              (msgdma_rx_descriptor_write_master_write),              //                        .write
		.descriptor_write_master_byteenable         (msgdma_rx_descriptor_write_master_byteenable),         //                        .byteenable
		.descriptor_write_master_writedata          (msgdma_rx_descriptor_write_master_writedata),          //                        .writedata
		.descriptor_write_master_waitrequest        (msgdma_rx_descriptor_write_master_waitrequest),        //                        .waitrequest
		.descriptor_write_master_response           (msgdma_rx_descriptor_write_master_response),           //                        .response
		.descriptor_write_master_writeresponsevalid (msgdma_rx_descriptor_write_master_writeresponsevalid), //                        .writeresponsevalid
		.clock_clk                                  (ethernet_subsys_clk_in_clk),                           //                   clock.clk
		.reset_n_reset_n                            (~rst_controller_reset_out_reset),                      //                 reset_n.reset_n
		.csr_writedata                              (mm_interconnect_1_msgdma_rx_csr_writedata),            //                     csr.writedata
		.csr_write                                  (mm_interconnect_1_msgdma_rx_csr_write),                //                        .write
		.csr_byteenable                             (mm_interconnect_1_msgdma_rx_csr_byteenable),           //                        .byteenable
		.csr_readdata                               (mm_interconnect_1_msgdma_rx_csr_readdata),             //                        .readdata
		.csr_read                                   (mm_interconnect_1_msgdma_rx_csr_read),                 //                        .read
		.csr_address                                (mm_interconnect_1_msgdma_rx_csr_address),              //                        .address
		.prefetcher_csr_address                     (mm_interconnect_1_msgdma_rx_prefetcher_csr_address),   //          prefetcher_csr.address
		.prefetcher_csr_read                        (mm_interconnect_1_msgdma_rx_prefetcher_csr_read),      //                        .read
		.prefetcher_csr_write                       (mm_interconnect_1_msgdma_rx_prefetcher_csr_write),     //                        .write
		.prefetcher_csr_writedata                   (mm_interconnect_1_msgdma_rx_prefetcher_csr_writedata), //                        .writedata
		.prefetcher_csr_readdata                    (mm_interconnect_1_msgdma_rx_prefetcher_csr_readdata),  //                        .readdata
		.csr_irq_irq                                (sgdma_rx_csr_irq_irq),                                 //                 csr_irq.irq
		.st_sink_data                               (avalon_st_adapter_out_0_data),                         //                 st_sink.data
		.st_sink_valid                              (avalon_st_adapter_out_0_valid),                        //                        .valid
		.st_sink_ready                              (avalon_st_adapter_out_0_ready),                        //                        .ready
		.st_sink_startofpacket                      (avalon_st_adapter_out_0_startofpacket),                //                        .startofpacket
		.st_sink_endofpacket                        (avalon_st_adapter_out_0_endofpacket),                  //                        .endofpacket
		.st_sink_empty                              (avalon_st_adapter_out_0_empty),                        //                        .empty
		.st_sink_error                              (avalon_st_adapter_out_0_error)                         //                        .error
	);

	main_qsys_ethernet_subsystem_msgdma_tx msgdma_tx (
		.mm_read_address                            (msgdma_tx_mm_read_address),                            //                 mm_read.address
		.mm_read_read                               (msgdma_tx_mm_read_read),                               //                        .read
		.mm_read_byteenable                         (msgdma_tx_mm_read_byteenable),                         //                        .byteenable
		.mm_read_readdata                           (msgdma_tx_mm_read_readdata),                           //                        .readdata
		.mm_read_waitrequest                        (msgdma_tx_mm_read_waitrequest),                        //                        .waitrequest
		.mm_read_readdatavalid                      (msgdma_tx_mm_read_readdatavalid),                      //                        .readdatavalid
		.descriptor_read_master_address             (msgdma_tx_descriptor_read_master_address),             //  descriptor_read_master.address
		.descriptor_read_master_read                (msgdma_tx_descriptor_read_master_read),                //                        .read
		.descriptor_read_master_readdata            (msgdma_tx_descriptor_read_master_readdata),            //                        .readdata
		.descriptor_read_master_waitrequest         (msgdma_tx_descriptor_read_master_waitrequest),         //                        .waitrequest
		.descriptor_read_master_readdatavalid       (msgdma_tx_descriptor_read_master_readdatavalid),       //                        .readdatavalid
		.descriptor_write_master_address            (msgdma_tx_descriptor_write_master_address),            // descriptor_write_master.address
		.descriptor_write_master_write              (msgdma_tx_descriptor_write_master_write),              //                        .write
		.descriptor_write_master_byteenable         (msgdma_tx_descriptor_write_master_byteenable),         //                        .byteenable
		.descriptor_write_master_writedata          (msgdma_tx_descriptor_write_master_writedata),          //                        .writedata
		.descriptor_write_master_waitrequest        (msgdma_tx_descriptor_write_master_waitrequest),        //                        .waitrequest
		.descriptor_write_master_response           (msgdma_tx_descriptor_write_master_response),           //                        .response
		.descriptor_write_master_writeresponsevalid (msgdma_tx_descriptor_write_master_writeresponsevalid), //                        .writeresponsevalid
		.clock_clk                                  (ethernet_subsys_clk_in_clk),                           //                   clock.clk
		.reset_n_reset_n                            (~rst_controller_reset_out_reset),                      //                 reset_n.reset_n
		.csr_writedata                              (mm_interconnect_1_msgdma_tx_csr_writedata),            //                     csr.writedata
		.csr_write                                  (mm_interconnect_1_msgdma_tx_csr_write),                //                        .write
		.csr_byteenable                             (mm_interconnect_1_msgdma_tx_csr_byteenable),           //                        .byteenable
		.csr_readdata                               (mm_interconnect_1_msgdma_tx_csr_readdata),             //                        .readdata
		.csr_read                                   (mm_interconnect_1_msgdma_tx_csr_read),                 //                        .read
		.csr_address                                (mm_interconnect_1_msgdma_tx_csr_address),              //                        .address
		.prefetcher_csr_address                     (mm_interconnect_1_msgdma_tx_prefetcher_csr_address),   //          prefetcher_csr.address
		.prefetcher_csr_read                        (mm_interconnect_1_msgdma_tx_prefetcher_csr_read),      //                        .read
		.prefetcher_csr_write                       (mm_interconnect_1_msgdma_tx_prefetcher_csr_write),     //                        .write
		.prefetcher_csr_writedata                   (mm_interconnect_1_msgdma_tx_prefetcher_csr_writedata), //                        .writedata
		.prefetcher_csr_readdata                    (mm_interconnect_1_msgdma_tx_prefetcher_csr_readdata),  //                        .readdata
		.csr_irq_irq                                (sgdma_tx_csr_irq_irq),                                 //                 csr_irq.irq
		.st_source_data                             (msgdma_tx_st_source_data),                             //               st_source.data
		.st_source_valid                            (msgdma_tx_st_source_valid),                            //                        .valid
		.st_source_ready                            (msgdma_tx_st_source_ready),                            //                        .ready
		.st_source_startofpacket                    (msgdma_tx_st_source_startofpacket),                    //                        .startofpacket
		.st_source_endofpacket                      (msgdma_tx_st_source_endofpacket),                      //                        .endofpacket
		.st_source_empty                            (msgdma_tx_st_source_empty),                            //                        .empty
		.st_source_error                            (msgdma_tx_st_source_error)                             //                        .error
	);

	altera_avalon_mm_bridge #(
		.DATA_WIDTH        (32),
		.SYMBOL_WIDTH      (8),
		.HDL_ADDR_WIDTH    (31),
		.BURSTCOUNT_WIDTH  (1),
		.PIPELINE_COMMAND  (1),
		.PIPELINE_RESPONSE (1)
	) sgdma_bridge (
		.clk              (ethernet_subsys_clk_in_clk),                      //   clk.clk
		.reset            (rst_controller_reset_out_reset),                  // reset.reset
		.s0_waitrequest   (mm_interconnect_2_sgdma_bridge_s0_waitrequest),   //    s0.waitrequest
		.s0_readdata      (mm_interconnect_2_sgdma_bridge_s0_readdata),      //      .readdata
		.s0_readdatavalid (mm_interconnect_2_sgdma_bridge_s0_readdatavalid), //      .readdatavalid
		.s0_burstcount    (mm_interconnect_2_sgdma_bridge_s0_burstcount),    //      .burstcount
		.s0_writedata     (mm_interconnect_2_sgdma_bridge_s0_writedata),     //      .writedata
		.s0_address       (mm_interconnect_2_sgdma_bridge_s0_address),       //      .address
		.s0_write         (mm_interconnect_2_sgdma_bridge_s0_write),         //      .write
		.s0_read          (mm_interconnect_2_sgdma_bridge_s0_read),          //      .read
		.s0_byteenable    (mm_interconnect_2_sgdma_bridge_s0_byteenable),    //      .byteenable
		.s0_debugaccess   (mm_interconnect_2_sgdma_bridge_s0_debugaccess),   //      .debugaccess
		.m0_waitrequest   (sgdma_bridge_m0_waitrequest),                     //    m0.waitrequest
		.m0_readdata      (sgdma_bridge_m0_readdata),                        //      .readdata
		.m0_readdatavalid (sgdma_bridge_m0_readdatavalid),                   //      .readdatavalid
		.m0_burstcount    (sgdma_bridge_m0_burstcount),                      //      .burstcount
		.m0_writedata     (sgdma_bridge_m0_writedata),                       //      .writedata
		.m0_address       (sgdma_bridge_m0_address),                         //      .address
		.m0_write         (sgdma_bridge_m0_write),                           //      .write
		.m0_read          (sgdma_bridge_m0_read),                            //      .read
		.m0_byteenable    (sgdma_bridge_m0_byteenable),                      //      .byteenable
		.m0_debugaccess   (sgdma_bridge_m0_debugaccess),                     //      .debugaccess
		.s0_response      (),                                                // (terminated)
		.m0_response      (2'b00)                                            // (terminated)
	);

	main_qsys_ethernet_subsystem_tse_mac tse_mac (
		.clk           (ethernet_subsys_clk_in_clk),                         // control_port_clock_connection.clk
		.reset         (rst_controller_reset_out_reset),                     //              reset_connection.reset
		.reg_addr      (mm_interconnect_1_tse_mac_control_port_address),     //                  control_port.address
		.reg_data_out  (mm_interconnect_1_tse_mac_control_port_readdata),    //                              .readdata
		.reg_rd        (mm_interconnect_1_tse_mac_control_port_read),        //                              .read
		.reg_data_in   (mm_interconnect_1_tse_mac_control_port_writedata),   //                              .writedata
		.reg_wr        (mm_interconnect_1_tse_mac_control_port_write),       //                              .write
		.reg_busy      (mm_interconnect_1_tse_mac_control_port_waitrequest), //                              .waitrequest
		.tx_clk        (tx_clock_clk),                                       //   pcs_mac_tx_clock_connection.clk
		.rx_clk        (rx_clock_clk),                                       //   pcs_mac_rx_clock_connection.clk
		.set_10        (mac_status_connection_set_10),                       //         mac_status_connection.set_10
		.set_1000      (mac_status_connection_set_1000),                     //                              .set_1000
		.eth_mode      (mac_status_connection_eth_mode),                     //                              .eth_mode
		.ena_10        (mac_status_connection_ena_10),                       //                              .ena_10
		.rgmii_in      (mac_rgmii_connection_rgmii_in),                      //          mac_rgmii_connection.rgmii_in
		.rgmii_out     (mac_rgmii_connection_rgmii_out),                     //                              .rgmii_out
		.rx_control    (mac_rgmii_connection_rx_control),                    //                              .rx_control
		.tx_control    (mac_rgmii_connection_tx_control),                    //                              .tx_control
		.ff_rx_clk     (ethernet_subsys_clk_in_clk),                         //      receive_clock_connection.clk
		.ff_tx_clk     (ethernet_subsys_clk_in_clk),                         //     transmit_clock_connection.clk
		.ff_rx_data    (tse_mac_receive_data),                               //                       receive.data
		.ff_rx_eop     (tse_mac_receive_endofpacket),                        //                              .endofpacket
		.rx_err        (tse_mac_receive_error),                              //                              .error
		.ff_rx_mod     (tse_mac_receive_empty),                              //                              .empty
		.ff_rx_rdy     (tse_mac_receive_ready),                              //                              .ready
		.ff_rx_sop     (tse_mac_receive_startofpacket),                      //                              .startofpacket
		.ff_rx_dval    (tse_mac_receive_valid),                              //                              .valid
		.ff_tx_data    (msgdma_tx_st_source_data),                           //                      transmit.data
		.ff_tx_eop     (msgdma_tx_st_source_endofpacket),                    //                              .endofpacket
		.ff_tx_err     (msgdma_tx_st_source_error),                          //                              .error
		.ff_tx_mod     (msgdma_tx_st_source_empty),                          //                              .empty
		.ff_tx_rdy     (msgdma_tx_st_source_ready),                          //                              .ready
		.ff_tx_sop     (msgdma_tx_st_source_startofpacket),                  //                              .startofpacket
		.ff_tx_wren    (msgdma_tx_st_source_valid),                          //                              .valid
		.mdc           (mac_mdio_connection_mdc),                            //           mac_mdio_connection.mdc
		.mdio_in       (mac_mdio_connection_mdio_in),                        //                              .mdio_in
		.mdio_out      (mac_mdio_connection_mdio_out),                       //                              .mdio_out
		.mdio_oen      (mac_mdio_connection_mdio_oen),                       //                              .mdio_oen
		.xon_gen       (mac_misc_connection_xon_gen),                        //           mac_misc_connection.xon_gen
		.xoff_gen      (mac_misc_connection_xoff_gen),                       //                              .xoff_gen
		.ff_tx_crc_fwd (mac_misc_connection_ff_tx_crc_fwd),                  //                              .ff_tx_crc_fwd
		.ff_tx_septy   (mac_misc_connection_ff_tx_septy),                    //                              .ff_tx_septy
		.tx_ff_uflow   (mac_misc_connection_tx_ff_uflow),                    //                              .tx_ff_uflow
		.ff_tx_a_full  (mac_misc_connection_ff_tx_a_full),                   //                              .ff_tx_a_full
		.ff_tx_a_empty (mac_misc_connection_ff_tx_a_empty),                  //                              .ff_tx_a_empty
		.rx_err_stat   (mac_misc_connection_rx_err_stat),                    //                              .rx_err_stat
		.rx_frm_type   (mac_misc_connection_rx_frm_type),                    //                              .rx_frm_type
		.ff_rx_dsav    (mac_misc_connection_ff_rx_dsav),                     //                              .ff_rx_dsav
		.ff_rx_a_full  (mac_misc_connection_ff_rx_a_full),                   //                              .ff_rx_a_full
		.ff_rx_a_empty (mac_misc_connection_ff_rx_a_empty)                   //                              .ff_rx_a_empty
	);

	main_qsys_ethernet_subsystem_mm_interconnect_0 mm_interconnect_0 (
		.clk_clk_clk                                          (ethernet_subsys_clk_in_clk),                           //                                 clk_clk.clk
		.msgdma_rx_reset_n_reset_bridge_in_reset_reset        (rst_controller_reset_out_reset),                       // msgdma_rx_reset_n_reset_bridge_in_reset.reset
		.msgdma_rx_descriptor_read_master_address             (msgdma_rx_descriptor_read_master_address),             //        msgdma_rx_descriptor_read_master.address
		.msgdma_rx_descriptor_read_master_waitrequest         (msgdma_rx_descriptor_read_master_waitrequest),         //                                        .waitrequest
		.msgdma_rx_descriptor_read_master_read                (msgdma_rx_descriptor_read_master_read),                //                                        .read
		.msgdma_rx_descriptor_read_master_readdata            (msgdma_rx_descriptor_read_master_readdata),            //                                        .readdata
		.msgdma_rx_descriptor_read_master_readdatavalid       (msgdma_rx_descriptor_read_master_readdatavalid),       //                                        .readdatavalid
		.msgdma_rx_descriptor_write_master_address            (msgdma_rx_descriptor_write_master_address),            //       msgdma_rx_descriptor_write_master.address
		.msgdma_rx_descriptor_write_master_waitrequest        (msgdma_rx_descriptor_write_master_waitrequest),        //                                        .waitrequest
		.msgdma_rx_descriptor_write_master_byteenable         (msgdma_rx_descriptor_write_master_byteenable),         //                                        .byteenable
		.msgdma_rx_descriptor_write_master_write              (msgdma_rx_descriptor_write_master_write),              //                                        .write
		.msgdma_rx_descriptor_write_master_writedata          (msgdma_rx_descriptor_write_master_writedata),          //                                        .writedata
		.msgdma_rx_descriptor_write_master_response           (msgdma_rx_descriptor_write_master_response),           //                                        .response
		.msgdma_rx_descriptor_write_master_writeresponsevalid (msgdma_rx_descriptor_write_master_writeresponsevalid), //                                        .writeresponsevalid
		.msgdma_tx_descriptor_read_master_address             (msgdma_tx_descriptor_read_master_address),             //        msgdma_tx_descriptor_read_master.address
		.msgdma_tx_descriptor_read_master_waitrequest         (msgdma_tx_descriptor_read_master_waitrequest),         //                                        .waitrequest
		.msgdma_tx_descriptor_read_master_read                (msgdma_tx_descriptor_read_master_read),                //                                        .read
		.msgdma_tx_descriptor_read_master_readdata            (msgdma_tx_descriptor_read_master_readdata),            //                                        .readdata
		.msgdma_tx_descriptor_read_master_readdatavalid       (msgdma_tx_descriptor_read_master_readdatavalid),       //                                        .readdatavalid
		.msgdma_tx_descriptor_write_master_address            (msgdma_tx_descriptor_write_master_address),            //       msgdma_tx_descriptor_write_master.address
		.msgdma_tx_descriptor_write_master_waitrequest        (msgdma_tx_descriptor_write_master_waitrequest),        //                                        .waitrequest
		.msgdma_tx_descriptor_write_master_byteenable         (msgdma_tx_descriptor_write_master_byteenable),         //                                        .byteenable
		.msgdma_tx_descriptor_write_master_write              (msgdma_tx_descriptor_write_master_write),              //                                        .write
		.msgdma_tx_descriptor_write_master_writedata          (msgdma_tx_descriptor_write_master_writedata),          //                                        .writedata
		.msgdma_tx_descriptor_write_master_response           (msgdma_tx_descriptor_write_master_response),           //                                        .response
		.msgdma_tx_descriptor_write_master_writeresponsevalid (msgdma_tx_descriptor_write_master_writeresponsevalid), //                                        .writeresponsevalid
		.descriptor_memory_s1_address                         (mm_interconnect_0_descriptor_memory_s1_address),       //                    descriptor_memory_s1.address
		.descriptor_memory_s1_write                           (mm_interconnect_0_descriptor_memory_s1_write),         //                                        .write
		.descriptor_memory_s1_readdata                        (mm_interconnect_0_descriptor_memory_s1_readdata),      //                                        .readdata
		.descriptor_memory_s1_writedata                       (mm_interconnect_0_descriptor_memory_s1_writedata),     //                                        .writedata
		.descriptor_memory_s1_byteenable                      (mm_interconnect_0_descriptor_memory_s1_byteenable),    //                                        .byteenable
		.descriptor_memory_s1_chipselect                      (mm_interconnect_0_descriptor_memory_s1_chipselect),    //                                        .chipselect
		.descriptor_memory_s1_clken                           (mm_interconnect_0_descriptor_memory_s1_clken)          //                                        .clken
	);

	main_qsys_ethernet_subsystem_mm_interconnect_1 mm_interconnect_1 (
		.clk_clk_clk                                       (ethernet_subsys_clk_in_clk),                           //                                     clk_clk.clk
		.ethernet_bridge_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset),                       // ethernet_bridge_reset_reset_bridge_in_reset.reset
		.ethernet_bridge_m0_address                        (ethernet_bridge_m0_address),                           //                          ethernet_bridge_m0.address
		.ethernet_bridge_m0_waitrequest                    (ethernet_bridge_m0_waitrequest),                       //                                            .waitrequest
		.ethernet_bridge_m0_burstcount                     (ethernet_bridge_m0_burstcount),                        //                                            .burstcount
		.ethernet_bridge_m0_byteenable                     (ethernet_bridge_m0_byteenable),                        //                                            .byteenable
		.ethernet_bridge_m0_read                           (ethernet_bridge_m0_read),                              //                                            .read
		.ethernet_bridge_m0_readdata                       (ethernet_bridge_m0_readdata),                          //                                            .readdata
		.ethernet_bridge_m0_readdatavalid                  (ethernet_bridge_m0_readdatavalid),                     //                                            .readdatavalid
		.ethernet_bridge_m0_write                          (ethernet_bridge_m0_write),                             //                                            .write
		.ethernet_bridge_m0_writedata                      (ethernet_bridge_m0_writedata),                         //                                            .writedata
		.ethernet_bridge_m0_debugaccess                    (ethernet_bridge_m0_debugaccess),                       //                                            .debugaccess
		.msgdma_rx_csr_address                             (mm_interconnect_1_msgdma_rx_csr_address),              //                               msgdma_rx_csr.address
		.msgdma_rx_csr_write                               (mm_interconnect_1_msgdma_rx_csr_write),                //                                            .write
		.msgdma_rx_csr_read                                (mm_interconnect_1_msgdma_rx_csr_read),                 //                                            .read
		.msgdma_rx_csr_readdata                            (mm_interconnect_1_msgdma_rx_csr_readdata),             //                                            .readdata
		.msgdma_rx_csr_writedata                           (mm_interconnect_1_msgdma_rx_csr_writedata),            //                                            .writedata
		.msgdma_rx_csr_byteenable                          (mm_interconnect_1_msgdma_rx_csr_byteenable),           //                                            .byteenable
		.msgdma_rx_prefetcher_csr_address                  (mm_interconnect_1_msgdma_rx_prefetcher_csr_address),   //                    msgdma_rx_prefetcher_csr.address
		.msgdma_rx_prefetcher_csr_write                    (mm_interconnect_1_msgdma_rx_prefetcher_csr_write),     //                                            .write
		.msgdma_rx_prefetcher_csr_read                     (mm_interconnect_1_msgdma_rx_prefetcher_csr_read),      //                                            .read
		.msgdma_rx_prefetcher_csr_readdata                 (mm_interconnect_1_msgdma_rx_prefetcher_csr_readdata),  //                                            .readdata
		.msgdma_rx_prefetcher_csr_writedata                (mm_interconnect_1_msgdma_rx_prefetcher_csr_writedata), //                                            .writedata
		.msgdma_tx_csr_address                             (mm_interconnect_1_msgdma_tx_csr_address),              //                               msgdma_tx_csr.address
		.msgdma_tx_csr_write                               (mm_interconnect_1_msgdma_tx_csr_write),                //                                            .write
		.msgdma_tx_csr_read                                (mm_interconnect_1_msgdma_tx_csr_read),                 //                                            .read
		.msgdma_tx_csr_readdata                            (mm_interconnect_1_msgdma_tx_csr_readdata),             //                                            .readdata
		.msgdma_tx_csr_writedata                           (mm_interconnect_1_msgdma_tx_csr_writedata),            //                                            .writedata
		.msgdma_tx_csr_byteenable                          (mm_interconnect_1_msgdma_tx_csr_byteenable),           //                                            .byteenable
		.msgdma_tx_prefetcher_csr_address                  (mm_interconnect_1_msgdma_tx_prefetcher_csr_address),   //                    msgdma_tx_prefetcher_csr.address
		.msgdma_tx_prefetcher_csr_write                    (mm_interconnect_1_msgdma_tx_prefetcher_csr_write),     //                                            .write
		.msgdma_tx_prefetcher_csr_read                     (mm_interconnect_1_msgdma_tx_prefetcher_csr_read),      //                                            .read
		.msgdma_tx_prefetcher_csr_readdata                 (mm_interconnect_1_msgdma_tx_prefetcher_csr_readdata),  //                                            .readdata
		.msgdma_tx_prefetcher_csr_writedata                (mm_interconnect_1_msgdma_tx_prefetcher_csr_writedata), //                                            .writedata
		.tse_mac_control_port_address                      (mm_interconnect_1_tse_mac_control_port_address),       //                        tse_mac_control_port.address
		.tse_mac_control_port_write                        (mm_interconnect_1_tse_mac_control_port_write),         //                                            .write
		.tse_mac_control_port_read                         (mm_interconnect_1_tse_mac_control_port_read),          //                                            .read
		.tse_mac_control_port_readdata                     (mm_interconnect_1_tse_mac_control_port_readdata),      //                                            .readdata
		.tse_mac_control_port_writedata                    (mm_interconnect_1_tse_mac_control_port_writedata),     //                                            .writedata
		.tse_mac_control_port_waitrequest                  (mm_interconnect_1_tse_mac_control_port_waitrequest)    //                                            .waitrequest
	);

	main_qsys_ethernet_subsystem_mm_interconnect_2 mm_interconnect_2 (
		.clk_clk_clk                                   (ethernet_subsys_clk_in_clk),                      //                                 clk_clk.clk
		.msgdma_tx_reset_n_reset_bridge_in_reset_reset (rst_controller_reset_out_reset),                  // msgdma_tx_reset_n_reset_bridge_in_reset.reset
		.msgdma_rx_mm_write_address                    (msgdma_rx_mm_write_address),                      //                      msgdma_rx_mm_write.address
		.msgdma_rx_mm_write_waitrequest                (msgdma_rx_mm_write_waitrequest),                  //                                        .waitrequest
		.msgdma_rx_mm_write_byteenable                 (msgdma_rx_mm_write_byteenable),                   //                                        .byteenable
		.msgdma_rx_mm_write_write                      (msgdma_rx_mm_write_write),                        //                                        .write
		.msgdma_rx_mm_write_writedata                  (msgdma_rx_mm_write_writedata),                    //                                        .writedata
		.msgdma_tx_mm_read_address                     (msgdma_tx_mm_read_address),                       //                       msgdma_tx_mm_read.address
		.msgdma_tx_mm_read_waitrequest                 (msgdma_tx_mm_read_waitrequest),                   //                                        .waitrequest
		.msgdma_tx_mm_read_byteenable                  (msgdma_tx_mm_read_byteenable),                    //                                        .byteenable
		.msgdma_tx_mm_read_read                        (msgdma_tx_mm_read_read),                          //                                        .read
		.msgdma_tx_mm_read_readdata                    (msgdma_tx_mm_read_readdata),                      //                                        .readdata
		.msgdma_tx_mm_read_readdatavalid               (msgdma_tx_mm_read_readdatavalid),                 //                                        .readdatavalid
		.sgdma_bridge_s0_address                       (mm_interconnect_2_sgdma_bridge_s0_address),       //                         sgdma_bridge_s0.address
		.sgdma_bridge_s0_write                         (mm_interconnect_2_sgdma_bridge_s0_write),         //                                        .write
		.sgdma_bridge_s0_read                          (mm_interconnect_2_sgdma_bridge_s0_read),          //                                        .read
		.sgdma_bridge_s0_readdata                      (mm_interconnect_2_sgdma_bridge_s0_readdata),      //                                        .readdata
		.sgdma_bridge_s0_writedata                     (mm_interconnect_2_sgdma_bridge_s0_writedata),     //                                        .writedata
		.sgdma_bridge_s0_burstcount                    (mm_interconnect_2_sgdma_bridge_s0_burstcount),    //                                        .burstcount
		.sgdma_bridge_s0_byteenable                    (mm_interconnect_2_sgdma_bridge_s0_byteenable),    //                                        .byteenable
		.sgdma_bridge_s0_readdatavalid                 (mm_interconnect_2_sgdma_bridge_s0_readdatavalid), //                                        .readdatavalid
		.sgdma_bridge_s0_waitrequest                   (mm_interconnect_2_sgdma_bridge_s0_waitrequest),   //                                        .waitrequest
		.sgdma_bridge_s0_debugaccess                   (mm_interconnect_2_sgdma_bridge_s0_debugaccess)    //                                        .debugaccess
	);

	main_qsys_ethernet_subsystem_avalon_st_adapter #(
		.inBitsPerSymbol (8),
		.inUsePackets    (1),
		.inDataWidth     (32),
		.inChannelWidth  (0),
		.inErrorWidth    (6),
		.inUseEmptyPort  (1),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (2),
		.outDataWidth    (32),
		.outChannelWidth (0),
		.outErrorWidth   (6),
		.outUseEmptyPort (1),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk        (ethernet_subsys_clk_in_clk),            // in_clk_0.clk
		.in_rst_0_reset      (rst_controller_reset_out_reset),        // in_rst_0.reset
		.in_0_data           (tse_mac_receive_data),                  //     in_0.data
		.in_0_valid          (tse_mac_receive_valid),                 //         .valid
		.in_0_ready          (tse_mac_receive_ready),                 //         .ready
		.in_0_startofpacket  (tse_mac_receive_startofpacket),         //         .startofpacket
		.in_0_endofpacket    (tse_mac_receive_endofpacket),           //         .endofpacket
		.in_0_empty          (tse_mac_receive_empty),                 //         .empty
		.in_0_error          (tse_mac_receive_error),                 //         .error
		.out_0_data          (avalon_st_adapter_out_0_data),          //    out_0.data
		.out_0_valid         (avalon_st_adapter_out_0_valid),         //         .valid
		.out_0_ready         (avalon_st_adapter_out_0_ready),         //         .ready
		.out_0_startofpacket (avalon_st_adapter_out_0_startofpacket), //         .startofpacket
		.out_0_endofpacket   (avalon_st_adapter_out_0_endofpacket),   //         .endofpacket
		.out_0_empty         (avalon_st_adapter_out_0_empty),         //         .empty
		.out_0_error         (avalon_st_adapter_out_0_error)          //         .error
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (1),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~ethernet_subsys_reset_in_reset_n),  // reset_in0.reset
		.clk            (ethernet_subsys_clk_in_clk),         //       clk.clk
		.reset_out      (rst_controller_reset_out_reset),     // reset_out.reset
		.reset_req      (rst_controller_reset_out_reset_req), //          .reset_req
		.reset_req_in0  (1'b0),                               // (terminated)
		.reset_in1      (1'b0),                               // (terminated)
		.reset_req_in1  (1'b0),                               // (terminated)
		.reset_in2      (1'b0),                               // (terminated)
		.reset_req_in2  (1'b0),                               // (terminated)
		.reset_in3      (1'b0),                               // (terminated)
		.reset_req_in3  (1'b0),                               // (terminated)
		.reset_in4      (1'b0),                               // (terminated)
		.reset_req_in4  (1'b0),                               // (terminated)
		.reset_in5      (1'b0),                               // (terminated)
		.reset_req_in5  (1'b0),                               // (terminated)
		.reset_in6      (1'b0),                               // (terminated)
		.reset_req_in6  (1'b0),                               // (terminated)
		.reset_in7      (1'b0),                               // (terminated)
		.reset_req_in7  (1'b0),                               // (terminated)
		.reset_in8      (1'b0),                               // (terminated)
		.reset_req_in8  (1'b0),                               // (terminated)
		.reset_in9      (1'b0),                               // (terminated)
		.reset_req_in9  (1'b0),                               // (terminated)
		.reset_in10     (1'b0),                               // (terminated)
		.reset_req_in10 (1'b0),                               // (terminated)
		.reset_in11     (1'b0),                               // (terminated)
		.reset_req_in11 (1'b0),                               // (terminated)
		.reset_in12     (1'b0),                               // (terminated)
		.reset_req_in12 (1'b0),                               // (terminated)
		.reset_in13     (1'b0),                               // (terminated)
		.reset_req_in13 (1'b0),                               // (terminated)
		.reset_in14     (1'b0),                               // (terminated)
		.reset_req_in14 (1'b0),                               // (terminated)
		.reset_in15     (1'b0),                               // (terminated)
		.reset_req_in15 (1'b0)                                // (terminated)
	);

endmodule
