//****************************************Copyright (c)***********************************//
// 网站博客: NC 
// 版权所有, 盗版必究 
// 杭州爱科科技有限公司
// ALL right reserved
//----------------------------------------------------------------------------------------//
// File name: 		xxx.v
// Descriptions: 	
// Author: 		   Max
// Creation Date:	Wed Jan 15 2025 14:29:52 GMT+0800
//----------------------------------------------------------------------------------------//
// Note:
//
//----------------------------------------------------------------------------------------//
//****************************************************************************************//

module  demo_top(
             //system signals
      input   wire            sys_clk,//clock signal
      input   wire            sys_rst_n,//reset, active low  
             //user
    
	//FPGA-DDR3-400Mx32
	   output 			[14:0]	ddr3_fpga_a,         //SSTL15  //Address
	   output 			[2:0]   	ddr3_fpga_ba,        //SSTL15  //Bank Address
	   output 			        	ddr3_fpga_casn,      //SSTL15  //Column Address Strobe
	   output 			        	ddr3_fpga_cke,       //SSTL15  //Clock Enable
	   output 			        	ddr3_fpga_clk_n,     //SSTL15  //Diff Clock - Neg
	   output 			        	ddr3_fpga_clk_p,     //SSTL15  //Diff Clock - Pos
	   output 			        	ddr3_fpga_csn,       //SSTL15  //Chip Select
	   output 			[1:0]   	ddr3_fpga_dm,        //SSTL15  //Data Write Mask
	   inout  			[15:0]  	ddr3_fpga_dq,        //SSTL15  //Data Bus
	   inout  			[1:0]   	ddr3_fpga_dqs_n,     //SSTL15  //Diff Data Strobe - Neg
	   inout  			[1:0]   	ddr3_fpga_dqs_p,     //SSTL15  //Diff Data Strobe - Pos
	   output 			        	ddr3_fpga_odt,       //SSTL15  //On-Die Termination Enable
	   output  			        	ddr3_fpga_rasn,      //SSTL15  //Row Address Strobe
	   output  			        	ddr3_fpga_resetn,    //SSTL15  //Reset
	   output  			        	ddr3_fpga_wen,       //SSTL15  //Write Enable
	   input  			        	ddr3_fpga_rzq,        //OCT_rzqin
		
		output						enet_resetn,		//2.5V,没用
		inout							enet_mdio,			//2.5V,双向
		output						enet_mdc,			//2.5V
		//RGMII
		output						enet_gtx_clk,		//2.5V
		output			[3:0]		enet_tx_d,			//2.5V
		output 						enet_tx_en,		//2.5V
		input							enet_rx_clk,		//2.5V
		input				[3:0]		enet_rx_d,			//2.5V
		input							enet_rx_dv	//2.5V,数据    
	

);

//========================================================================\
// =========== Define Parameter and Internal signals =========== 
//========================================================================/
//先测晶振时钟
reg	led_reg;
reg   [31:0]	led_reg_cnt;
always@(posedge sys_clk )begin
		if(led_reg_cnt<32'd25_000_000-1'b1)begin
      	led_reg_cnt<=led_reg_cnt+1'b1;
		end
		else begin
		   led_reg_cnt<='d0;
		end
end
//
always@(posedge sys_clk )begin
      if(led_reg_cnt==32'd25_000_000-1'b1)begin
         led_reg<=~led_reg;
      end
end

//
reg   [31:0]	rst_cnt;
reg   rst_n=0;
always@(posedge sys_clk )begin
      if(rst_cnt<32'd3-1'b1)begin
         rst_cnt<=rst_cnt+1'b1;
      end
end
always@(posedge sys_clk )begin
      if(rst_cnt==32'd3-1'b1)begin
         rst_n<=1'b1;
      end
end

//=============================================================================
//**************    Main Code   **************
//=============================================================================
	main_qsys u0 (
		.clk_clk                        (sys_clk),                        //          clk.clk
		.reset_reset_n                  (rst_n),                  //        reset.reset_n
		
		.ddr3_mem_a                     (ddr3_fpga_a),                   //       memory.mem_a
		.ddr3_mem_ba                    (ddr3_fpga_ba),                  //             .mem_ba
		.ddr3_mem_ck                    (ddr3_fpga_clk_p),                  //             .mem_ck
		.ddr3_mem_ck_n                  (ddr3_fpga_clk_n),                //             .mem_ck_n
		.ddr3_mem_cke                   (ddr3_fpga_cke),                 //             .mem_cke
		.ddr3_mem_cs_n                  (ddr3_fpga_csn),                //             .mem_cs_n
		.ddr3_mem_dm                    (ddr3_fpga_dm),                  //             .mem_dm
		.ddr3_mem_ras_n                 (ddr3_fpga_rasn),               //             .mem_ras_n
		.ddr3_mem_cas_n                 (ddr3_fpga_casn),               //             .mem_cas_n
		.ddr3_mem_we_n                  (ddr3_fpga_wen),                //             .mem_we_n
		.ddr3_mem_reset_n               (ddr3_fpga_resetn),             //             .mem_reset_n
		.ddr3_mem_dq                    (ddr3_fpga_dq),                  //             .mem_dq
		.ddr3_mem_dqs                   (ddr3_fpga_dqs_p),                 //             .mem_dqs
		.ddr3_mem_dqs_n                 (ddr3_fpga_dqs_n),               //             .mem_dqs_n
		.ddr3_mem_odt                   (ddr3_fpga_odt),                 //             .mem_odt
		.oct_rzqin                      (ddr3_fpga_rzq),                      //          oct.rzqin
		.sdram_status_local_init_done   (),   // sdram_status.local_init_done
		.sdram_status_local_cal_success (), //             .local_cal_success
		.sdram_status_local_cal_fail    (),    //             .local_cal_fail
		
		//Ethernet
		.rx_clock_clk                   (enet_rx_clk),                   //     rx_clock.clk
		.tx_clock_clk                   (tx_clk_to_the_tse_mac),                    //     tx_clock.clk				.mac_rgmii_rgmii_in             (<connected-to-mac_rgmii_rgmii_in>),             //    mac_rgmii.rgmii_in
		.mac_rgmii_rgmii_in				  (enet_rx_d),
		.mac_rgmii_rgmii_out            (enet_tx_d),            //             .rgmii_out
		.mac_rgmii_rx_control           (enet_rx_dv),           //             .rx_control
		.mac_rgmii_tx_control           (enet_tx_en),           //             .tx_control
		//mac_config
		.mac_mdio_mdc                   (enet_mdc),                   //     mac_mdio.mdc
		.mac_mdio_mdio_in               (enet_mdio),               //             .mdio_in
		.mac_mdio_mdio_out				  (mdio_out),   
		.mac_mdio_mdio_oen				  (mdio_oen),		
		.mac_status_eth_mode            (eth_mode),            //             .eth_mode
		.mac_status_ena_10              (),              //             .ena_10
		//enet_clk	
		.enet_125m_clk						  (enet_125m_clk),
		.enet_25m_clk						  (enet_25m_clk)
	);

assign tx_clk_to_the_tse_mac =   ( eth_mode ) ? ( enet_125m_clk ) : enet_25m_clk;  // GbE Mode = 125MHz clock
                                                  // 100Mb Mode = 25MHz clock
                        
assign enet_mdio = ( !mdio_oen ) ? ( mdio_out ) : ( 1'bz );



endmodule