------------------------------------------------------------------------------
-- flash_erase_timer.vhd
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

--------------------------------------------------------------------------------
--! @brief Entity flash_erase_timer
--! @details **Description**\n
--! 1ms tick gnerator. 
--------------------------------------------------------------------------------
entity flash_erase_timer is
	generic(
		RESET_LEVEL			:std_logic := '0'
		
	);
	port( 
		CLK			:in		std_logic;								-- System Clock
		RST			:in		std_logic;								-- System Reset
		START			:in		std_logic;								-- Signal in
		TIMEOUT		:buffer	std_logic								-- Signal out
	);
end flash_erase_timer;

--------------------------------------------------------------------------------
-- RTL Architecture of template
--------------------------------------------------------------------------------
architecture rtl of flash_erase_timer is
--------------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------------
 constant c_terminal_count	:std_logic_vector(19 downto 0)	:= x"7CAA2"; --! LFSR count of 400,000
--------------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------------
signal start_d		:std_logic;									--! delayed START for edge detect
signal feedback	:std_logic;									--! lfsr feedback
signal lfsr			:std_logic_vector(19 downto 0);		--! lfsr register

-- counter to work out terminal counts in simulation
-- synthesis translate off
signal count		:natural;
-- synthesis translate on

---------------------------------------------------------------------------
-- Start of code
---------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------	
--! lfsr process
--! 20 bit Fibonacci lfsr with taps at bit 17 and bit 20
--! A comparitor is used to stop the count.
--! TIME_OUT output remains high until the timer is restarted
-------------------------------------------------------------------------------
	lfsr_register: process (RST, CLK)
	begin
		if RST = RESET_LEVEL then
			TIMEOUT		<= '0';
			lfsr			<= (others => '0');
			start_d		<= '0';
			
		elsif rising_edge(CLK) then
			--! delay sync for edge detection
			start_d <= START;
			
			--! Sync resets lfsr counter
			if (START = '1' and start_d = '0') then
				lfsr <= (others => '0');
				TIMEOUT <= '0';
				--synthesis translate off
				count <= 0;
				--synthesis translate on

			elsif TIMEOUT = '0' then

				-- Check for terminal count, generate pulse and reset lfsr
				if lfsr = c_terminal_count then
            	lfsr <= (others => '0');
					TIMEOUT <= '1';
					--synthesis translate off
					count <= 0;
					--synthesis translate on
				else
					lfsr <= lfsr(18 downto 0) & feedback;
					TIMEOUT <= '0';	
					--synthesis translate off
					count <= count + 1;
					--synthesis translate on
				end if;

			end if;

		end if;
	end process;
	
	lfsr_logic: process (lfsr)
	begin
		feedback <= lfsr(16) xnor lfsr(19);
	end process;

end rtl;