module convert_2_to_1_symbols_pb ( input write_clk, input read_clk, input reset_n, ​ input[95:0] hdmi_rx_data, input[1:0] hdmi_rx_hsync, input[1:0] hdmi_rx_vsync, input[1:0] hdmi_rx_de, output[23:0] cvi_data, output cvi_de, output cvi_hsync, output cvi_vsync ); ​ ​ reg[23:0] cvi_data_reg; reg cvi_de_reg; reg cvi_hsync_reg; reg cvi_vsync_reg; ​ reg s_count = 0; ​ reg[95:0] hdmi_rx_data_ff; reg[1:0] hdmi_rx_hsync_ff; reg[1:0] hdmi_rx_vsync_ff; reg[1:0] hdmi_rx_de_ff; ​ reg[23:0] cvi_data_1; reg cvi_de_1; reg cvi_vsync_1; reg cvi_hsync_1; ​ reg[23:0] cvi_data_0; reg cvi_de_0; reg cvi_vsync_0; reg cvi_hsync_0; ​ assign cvi_data = cvi_data_reg; assign cvi_de = cvi_de_reg; assign cvi_hsync = cvi_hsync_reg; assign cvi_vsync = cvi_vsync_reg; ​ always @(negedge read_clk) begin if (s_count == 0) begin cvi_data_reg = cvi_data_1; cvi_de_reg = cvi_de_1; cvi_vsync_reg = cvi_vsync_1; cvi_hsync_reg = cvi_hsync_1; s_count = 1; end else begin cvi_data_1 = { hdmi_rx_data_ff[ 95: 88], hdmi_rx_data_ff[ 79: 72], hdmi_rx_data_ff[ 63: 56] }; cvi_de_1 = hdmi_rx_de_ff[1]; cvi_vsync_1 = hdmi_rx_vsync_ff[1]; cvi_hsync_1 = hdmi_rx_hsync_ff[1]; cvi_data_0 = { hdmi_rx_data_ff[ 47: 40], hdmi_rx_data_ff[ 31: 24], hdmi_rx_data_ff[ 15: 8] }; ​ cvi_de_0 = hdmi_rx_de_ff[0]; cvi_vsync_0 = hdmi_rx_vsync_ff[0]; cvi_hsync_0 = hdmi_rx_hsync_ff[0]; cvi_data_reg = cvi_data_0; cvi_de_reg = cvi_de_0; cvi_vsync_reg = cvi_vsync_0; cvi_hsync_reg = cvi_hsync_0; s_count = 0; end end​ ​ wire vid_bp_ff_wrreq; wire vid_bp_ff_rdreq; wire vid_bp_ff_full; wire vid_bp_ff_empty; ​ assign vid_bp_ff_wrreq = ~vid_bp_ff_full; assign vid_bp_ff_rdreq = ~vid_bp_ff_empty; ​ dualclock_fifo dualclock_fifo_i ( .rdclk(s_count), .wrclk(write_clk), .wrreq(vid_bp_ff_wrreq), .aclr(~reset_n), .data({ hdmi_rx_data, hdmi_rx_de, hdmi_rx_vsync, hdmi_rx_hsync }), .rdreq(vid_bp_ff_rdreq), .wrfull(vid_bp_ff_full), .q({ hdmi_rx_data_ff, hdmi_rx_de_ff, hdmi_rx_vsync_ff, hdmi_rx_hsync_ff }), .rdempty(vid_bp_ff_empty) ); endmodule