# vsim -l ./transcript -L altera_mf_ver -L lpm_ver work.tb_silo 
# Start time: 21:07:32 on Nov 10,2017
# Loading sv_std.std
# Loading work.tb_silo
# Loading work.clock_gen
# Loading work.fpga_silo
# Loading work.main_pll
# Loading altera_mf_ver.altpll
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.pll_iobuf
# Loading work.flash_driver
# Loading work.phy_W25Q16CV
# Loading work.model_W25Q16CV
# Loading altera_mf_ver.MF_cycloneiii_pll
# Loading altera_mf_ver.cda_m_cntr
# Loading altera_mf_ver.cda_n_cntr
# Loading altera_mf_ver.cda_scale_cntr
# Loading work.flash_port
# hexadecimal
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body.tree
#  Note : Cyclone IV E PLL locked to incoming clock
# Time: 166400  Instance: tb_silo.m_silo.m_pll.altpll_component.cycloneiii_pll.pll3
# 
# DONE
# No errors detected
# 
# ** Note: $stop    : ../tb/tb_silo.sv(45)
#    Time: 34291983 ps  Iteration: 4  Instance: /tb_silo
# Break in Module tb_silo at ../tb/tb_silo.sv line 45
do run_sim.do
# Error 31: Unable to unlink file "C:/FPGA/projects/qspi_timing/qspi_single_clock/sim/work/_lib.qdb".
# Error 133: Unable to remove directory "C:/FPGA/projects/qspi_timing/qspi_single_clock/sim/work".
# ** Error: (vlib-35) Failed to create directory "work".
# File exists. (errno = EEXIST)
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:11:43 on Nov 10,2017
# vlog -reportprogress 300 ../src/pkg_graphics_flash.sv 
# -- Compiling package pkg_graphics_flash
# 
# Top level modules:
# 	--none--
# End time: 21:11:43 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:11:43 on Nov 10,2017
# vlog -reportprogress 300 ../src/flash_port.sv 
# -- Compiling interface flash_port
# 
# Top level modules:
# 	--none--
# End time: 21:11:43 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:11:43 on Nov 10,2017
# vlog -reportprogress 300 ../src/altera_mf/main_pll.v 
# -- Compiling module main_pll
# 
# Top level modules:
# 	main_pll
# End time: 21:11:43 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:11:43 on Nov 10,2017
# vlog -reportprogress 300 ../src/fpga_silo.sv 
# -- Compiling module fpga_silo
# 
# Top level modules:
# 	fpga_silo
# End time: 21:11:43 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:11:43 on Nov 10,2017
# vlog -reportprogress 300 ../src/phy_W25Q16CV.sv 
# -- Compiling module phy_W25Q16CV
# 
# Top level modules:
# 	phy_W25Q16CV
# End time: 21:11:43 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:11:43 on Nov 10,2017
# vlog -reportprogress 300 ../src/flash_driver.sv 
# -- Compiling module flash_driver
# 
# Top level modules:
# 	flash_driver
# End time: 21:11:43 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:11:43 on Nov 10,2017
# vlog -reportprogress 300 ../tb/tb_silo.sv 
# -- Compiling module tb_silo
# 
# Top level modules:
# 	tb_silo
# End time: 21:11:43 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:11:43 on Nov 10,2017
# vlog -reportprogress 300 ../tb/model_W25Q16CV.sv 
# -- Compiling module model_W25Q16CV
# 
# Top level modules:
# 	model_W25Q16CV
# End time: 21:11:43 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:11:43 on Nov 10,2017
# vlog -reportprogress 300 ../tb/model_testbench_helpers.sv 
# -- Compiling module clock_gen
# 
# Top level modules:
# 	clock_gen
# End time: 21:11:43 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# End time: 21:11:44 on Nov 10,2017, Elapsed time: 0:04:12
# Errors: 0, Warnings: 0
# vsim -l ./transcript -L altera_mf_ver -L lpm_ver work.tb_silo 
# Start time: 21:11:44 on Nov 10,2017
# Loading sv_std.std
# Loading work.tb_silo
# Loading work.clock_gen
# Loading work.fpga_silo
# Loading work.main_pll
# Loading altera_mf_ver.altpll
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.pll_iobuf
# Loading work.flash_driver
# Loading work.phy_W25Q16CV
# Loading work.model_W25Q16CV
# Loading altera_mf_ver.MF_cycloneiii_pll
# Loading altera_mf_ver.cda_m_cntr
# Loading altera_mf_ver.cda_n_cntr
# Loading altera_mf_ver.cda_scale_cntr
# Loading work.flash_port
# hexadecimal
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body.tree
#  Note : Cyclone IV E PLL locked to incoming clock
# Time: 166400  Instance: tb_silo.m_silo.m_pll.altpll_component.cycloneiii_pll.pll3
# 
# DONE
# No errors detected
# 
# ** Note: $stop    : ../tb/tb_silo.sv(45)
#    Time: 34291983 ps  Iteration: 4  Instance: /tb_silo
# Break in Module tb_silo at ../tb/tb_silo.sv line 45
do run_sim.do
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:38:53 on Nov 10,2017
# vlog -reportprogress 300 ../src/pkg_graphics_flash.sv 
# -- Compiling package pkg_graphics_flash
# 
# Top level modules:
# 	--none--
# End time: 21:38:54 on Nov 10,2017, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:38:54 on Nov 10,2017
# vlog -reportprogress 300 ../src/flash_port.sv 
# -- Compiling interface flash_port
# 
# Top level modules:
# 	--none--
# End time: 21:38:54 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:38:54 on Nov 10,2017
# vlog -reportprogress 300 ../src/altera_mf/main_pll.v 
# -- Compiling module main_pll
# 
# Top level modules:
# 	main_pll
# End time: 21:38:54 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:38:54 on Nov 10,2017
# vlog -reportprogress 300 ../src/fpga_silo.sv 
# -- Compiling module fpga_silo
# 
# Top level modules:
# 	fpga_silo
# End time: 21:38:54 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:38:54 on Nov 10,2017
# vlog -reportprogress 300 ../src/phy_W25Q16CV.sv 
# -- Compiling module phy_W25Q16CV
# 
# Top level modules:
# 	phy_W25Q16CV
# End time: 21:38:54 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:38:54 on Nov 10,2017
# vlog -reportprogress 300 ../src/flash_driver.sv 
# -- Compiling module flash_driver
# 
# Top level modules:
# 	flash_driver
# End time: 21:38:54 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:38:54 on Nov 10,2017
# vlog -reportprogress 300 ../tb/tb_silo.sv 
# -- Compiling module tb_silo
# 
# Top level modules:
# 	tb_silo
# End time: 21:38:54 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:38:54 on Nov 10,2017
# vlog -reportprogress 300 ../tb/model_W25Q16CV.sv 
# -- Compiling module model_W25Q16CV
# 
# Top level modules:
# 	model_W25Q16CV
# End time: 21:38:54 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:38:54 on Nov 10,2017
# vlog -reportprogress 300 ../tb/model_testbench_helpers.sv 
# -- Compiling module clock_gen
# 
# Top level modules:
# 	clock_gen
# End time: 21:38:54 on Nov 10,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# End time: 21:38:55 on Nov 10,2017, Elapsed time: 0:27:11
# Errors: 0, Warnings: 0
# vsim -l ./transcript -L altera_mf_ver -L lpm_ver work.tb_silo 
# Start time: 21:38:55 on Nov 10,2017
# Loading sv_std.std
# Loading work.tb_silo
# Loading work.clock_gen
# Loading work.fpga_silo
# Loading work.main_pll
# Loading altera_mf_ver.altpll
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.pll_iobuf
# Loading work.flash_driver
# Loading work.phy_W25Q16CV
# Loading work.model_W25Q16CV
# Loading altera_mf_ver.MF_cycloneiii_pll
# Loading altera_mf_ver.cda_m_cntr
# Loading altera_mf_ver.cda_n_cntr
# Loading altera_mf_ver.cda_scale_cntr
# Loading work.flash_port
# hexadecimal
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body.tree
#  Note : Cyclone IV E PLL locked to incoming clock
# Time: 166400  Instance: tb_silo.m_silo.m_pll.altpll_component.cycloneiii_pll.pll3
# 
# DONE
# No errors detected
# 
# ** Note: $stop    : ../tb/tb_silo.sv(45)
#    Time: 34291983 ps  Iteration: 4  Instance: /tb_silo
# Break in Module tb_silo at ../tb/tb_silo.sv line 45
# End time: 21:39:11 on Nov 10,2017, Elapsed time: 0:00:16
# Errors: 0, Warnings: 0
