## Generated SDC file "C:/Users/shauk khan/Desktop/Block1.out.sdc"

## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic 
## functions, and any output files from any of the foregoing 
## (including device programming or simulation files), and any 
## associated documentation or information are expressly subject 
## to the terms and conditions of the Altera Program License 
## Subscription Agreement, Altera MegaCore Function License 
## Agreement, or other applicable license agreement, including, 
## without limitation, that your use is for the sole purpose of 
## programming logic devices manufactured by Altera and sold by 
## Altera or its authorized distributors.  Please refer to the 
## applicable agreement for further details.


## VENDOR  "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"

## DATE    "Wed Oct 18 10:17:25 2017"

##
## DEVICE  "5M2210ZF324I5"
##


#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3



#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_clock -name {pfl_clk} -period 22.140 -waveform { 0.000 11.070 } [get_ports {pfl_clk}]


#**************************************************************
# Create Generated Clock
#**************************************************************



#**************************************************************
# Set Clock Latency
#**************************************************************



#**************************************************************
# Set Clock Uncertainty
#**************************************************************

derive_clock_uncertainty 

#**************************************************************
# Set Input Delay
#**************************************************************




#**************************************************************
# Set Output Delay
#**************************************************************


set_output_delay -add_delay  -clock [get_clocks {pfl_clk}]  2.000 [get_ports {fpga_data[0]}]
set_output_delay -add_delay  -clock [get_clocks {pfl_clk}]  2.000 [get_ports {fpga_dclk}]


#**************************************************************
# Set Clock Groups
#**************************************************************

set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 



#**************************************************************
# Set False Path
#**************************************************************

set_false_path -from [get_clocks {pfl_clk}] -to [get_ports {flash_addr[0] flash_addr[1] flash_addr[2] flash_addr[3] flash_addr[4] flash_addr[5] flash_addr[6] flash_addr[7] flash_addr[8] flash_addr[9] flash_addr[10] flash_addr[11] flash_addr[12] flash_addr[13] flash_addr[14] flash_addr[15] flash_addr[16] flash_addr[17] flash_addr[18] flash_addr[19] flash_addr[20] flash_data[0] flash_data[1] flash_data[2] flash_data[3] flash_data[4] flash_data[5] flash_data[6] flash_data[7] flash_data[8] flash_data[9] flash_data[10] flash_data[11] flash_data[12] flash_data[13] flash_data[14] flash_data[15] flash_nce flash_noe flash_nwe fpga_conf_done fpga_nconfig fpga_nstatus fpga_pgm[0] fpga_pgm[1] fpga_pgm[2] pfl_clk pfl_flash_access_granted pfl_flash_access_request pfl_nreset}]


#**************************************************************
# Set Multicycle Path
#**************************************************************



#**************************************************************
# Set Maximum Delay
#**************************************************************



#**************************************************************
# Set Minimum Delay
#**************************************************************



#**************************************************************
# Set Input Transition
#**************************************************************