library	ieee;
use		ieee.std_logic_1164.all;
use		ieee.numeric_std.all;

entity	rom is
	port(
		clk : in		std_logic;
		n_clr : in	std_logic;
		addr : in	std_logic_vector(5 downto 0);
		dato : out	std_logic_vector(7 downto 0)
		);
end entity rom;

architecture rom_imp of rom is
	constant ADDR_WIDTH : integer := 6;
	constant DATA_WIDTH : integer := 8;
	
	type mem_2d_type is array (0 to 2**ADDR_WIDTH-1)
		of std_logic_vector(DATA_WIDTH-1 downto 0);	
		
	constant	ROM_PROG : mem_2d_type :=(
		"00000001",	-- 0
		"00000000", -- 1
		"00001111", -- 2
		"00000000", -- 3
		"00001110", -- 4
		"00000001", -- 5
		"00011010", -- 6
		"00000001", -- 7
		"00001000", -- 8
		"00000100", -- 9
		"00000000", -- A
		"00000000", -- B
		"00001110", -- C
		"00000000", -- D
		"00011100", -- E
		"00000001", -- F
		"00001111", -- 10
		"00000000", -- 11
		"00000101", -- 12
		"00100000", -- 13
		"00001110", -- 14
		"00000001", -- 15
		"00011010", -- 16
		"00000001", -- 17
		"00001000", -- 18
		"00011100", -- 19
		"00000100", -- 1A
		"00010100", -- 1B
		"00000101", -- 1C
		"00100000", -- 1D
		"00000100", -- 1E
		"00000100", -- 1F
		"00001010", -- 20
		"00001100", -- 21
		"00010101", -- 22
		"00001010", -- 23
		"11111010", -- 24
		"00010101", -- 25
		"00001010", -- 26
		"11111010", -- 27
		"00000000", -- 28
		"00011000", -- 29
		"00001000", -- 2A
		"00101000", -- 2B
		"00010110", -- 2C
		"00011000", -- 2D
		"00001000", -- 2E
		"00100101", -- 2F
		"00010110", -- 30
		"00011000", -- 31
		"00001000", -- 32
		"00100010", -- 33
		"00000110", -- 34
		"11111010", -- 35
		"00000001", -- 36
		"11111010", -- 37
		"00000000", -- 38
		"00000111", -- 39
		"00000001", -- 3A
		"00001000", -- 3B
		"00011000", -- 3C
		"00011000", -- 3D
		"00010110", -- 3E
		"00000100"  -- 3F
		);		
begin
	dato <= ROM_PROG(to_integer(unsigned(addr)));
end architecture rom_imp;