-- ======================================================== -- Remote System Update Control -- Controls operation of Remote System Update entity -- ======================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use IEEE.numeric_std.all; entity RSU_Control is port ( rsu_clk : in std_logic; rsu_rst_n : in std_logic; rsu_enable : in std_logic; rsu_busy_out : out std_logic; rsu_reconfig_out : out std_logic; rsu_reset_out : out std_logic; rsu_reset_tmr_out : out std_logic; rsu_write_param_out : out std_logic ); end entity RSU_Control; architecture rtl of RSU_Control is -- ========================================= -- Remote Update IP -- ========================================= component Sprig_ImageUpdate_rmtupdt_51n is port ( --asmi_busy : IN STD_LOGIC := '0'; --asmi_data_valid : IN STD_LOGIC := '0'; --asmi_dataout : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0'); clock : IN STD_LOGIC ; data_in : IN STD_LOGIC_VECTOR (21 DOWNTO 0); param : IN STD_LOGIC_VECTOR (2 DOWNTO 0); read_param : IN STD_LOGIC ; read_source : IN STD_LOGIC_VECTOR (1 DOWNTO 0); reconfig : IN STD_LOGIC ; reset : IN STD_LOGIC ; reset_timer : IN STD_LOGIC ; write_param : IN STD_LOGIC ; --asmi_addr : OUT STD_LOGIC_VECTOR (23 DOWNTO 0); -- to parallel component --asmi_rden : OUT STD_LOGIC ; -- to parallel component --asmi_read : OUT STD_LOGIC ; -- to parallel component busy : OUT STD_LOGIC ; data_out : OUT STD_LOGIC_VECTOR (28 DOWNTO 0) --pof_error : OUT STD_LOGIC ); end component Sprig_ImageUpdate_rmtupdt_51n; -- I don't think I need this either component parallel_serial_test_altasmi_parallel_n652 IS PORT ( addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0); busy : OUT STD_LOGIC; clkin : IN STD_LOGIC; data_valid : OUT STD_LOGIC; dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); rden : IN STD_LOGIC; read : IN STD_LOGIC := '0'; reset : IN STD_LOGIC := '0' ); END component parallel_serial_test_altasmi_parallel_n652; -- ======================================== -- CONSTANTS -- ======================================== constant TIMEOUT_VALUE : std_logic_vector(21 downto 0) := "0000000000101010101010"; -- reconfigure later constant TIMEOUT_EN : std_logic_vector(21 downto 0) := "0000000000000000000001"; constant TIMEOUT_DIS : std_logic_vector(21 downto 0) := "0000000000000000000000"; --constant BOOT_ADDRESS : std_logic_vector(21 downto 0) := "0100000000000000000000"; constant BOOT_ADDRESS : std_logic_vector(21 downto 0) := "0100000000000000000000"; constant DATA_FINISH : std_logic_vector(21 downto 0) := "0000000000000000000000"; constant PARAM_TIMEOUT_VAL : std_logic_vector(2 downto 0) := "010"; constant PARAM_TIMEOUT_EN : std_logic_vector(2 downto 0) := "011"; constant PARAM_BOOT_ADDR : std_logic_vector(2 downto 0) := "100"; constant PARAM_FINISH : std_logic_vector(2 downto 0) := "000"; -- READ Source constant READ_WD_INFO : std_logic_vector(1 downto 0) := "10"; constant READ_PS1_RTCS : std_logic_vector(1 downto 0) := "11"; constant READ_BOOT_ADDR : std_logic_vector(1 downto 0) := "01"; -- REConfig constant CONFIG_PARAM : std_logic_vector(2 downto 0) := "101"; constant CONFIG_DATA : std_logic_vector(21 downto 0) := "0000000000000000000000"; -- ======================================== -- SIGNALS -- ======================================== -- FOR PORT MAPPING INTERFACE signal rsu_busy : std_logic; --: in std_logic; signal rsu_data_out : std_logic_vector(21 downto 0) := TIMEOUT_VALUE;--: out std_logic_vector(21 downto 0); -- or whatever it is signal rsu_data_in : std_logic_vector(28 downto 0);--: in std_logic_vector(28 downto 0); -- or whatever it is signal rsu_param : std_logic_vector(2 downto 0) := PARAM_TIMEOUT_VAL;--: out std_logic_vector(2 downto 0); signal rsu_read_param : std_logic;--: out std_logic; signal rsu_read_src : std_logic_vector(1 downto 0);--: out std_logic_vector(1 downto 0); signal rsu_reconfig : std_logic := '0';--: out std_logic; signal rsu_reset : std_logic;--: out std_logic; signal rsu_reset_tmr : std_logic;--: out std_logic; signal rsu_write_param : std_logic;--: out std_logic --signal write_param_tmr_cnt : integer range 0 to 10000; -- CHANGE END VALUE signal rsu_init_done : std_logic := '0'; signal toggle_rst : std_logic_vector(1 downto 0) := "00"; signal write_param_cnt : std_logic_vector(1 downto 0) := "00"; signal read_param_cnt : std_logic_vector(1 downto 0) := "00"; signal reconfig_cnt : std_logic_vector(4 downto 0) := "00000"; signal toggle_rst_done : std_logic := '0'; signal watchdog_val_set_done : std_logic := '0'; signal watchdog_val_read_done : std_logic := '0'; signal watchdog_en_done : std_logic := '0'; signal watchdog_en_read_done : std_logic := '0'; signal set_reconfig_done : std_logic := '0'; signal read_reconfig_done : std_logic := '0'; signal write_param_done : std_logic := '0'; signal read_param_done : std_logic := '0'; signal set_boot_addr_done : std_logic := '0'; signal read_boot_addr_done : std_logic := '0'; signal reconfig_done : std_logic := '0'; signal stay_in_finish : std_logic := '0'; signal read_source_sig : std_logic_vector(1 downto 0) := "00"; -- ASMI signals signal asmi_busy_sig : std_logic := '0'; signal asmi_data_valid_sig : std_logic := '0'; signal asmi_dataout_sig : STD_LOGIC_VECTOR (7 DOWNTO 0); signal asmi_addr_sig : STD_LOGIC_VECTOR (23 DOWNTO 0); signal asmi_rden_sig : std_logic := '0'; signal asmi_read_sig : std_logic := '0'; signal pof_error_sig : std_logic := '0'; type States is ( Init, Finish, ToggleReset, SetConfig, ReadConfig, SetWatchdogTimeout, ReadWatchdogTimeout, WatchdogEnable, ReadWatchdogEnable, SetBoodAddress, ReadBootAddress, SetReconfigure ); signal CurrentState, NextState : States := Init; begin -- ================================================================ -- PORT MAP: REMOTE UPDATE IP -- ================================================================ Spring_RemUp : Sprig_ImageUpdate_rmtupdt_51n port map ( --asmi_busy => asmi_busy_sig, --IN STD_LOGIC --asmi_data_valid => asmi_data_valid_sig, --IN STD_LOGIC --asmi_dataout => asmi_dataout_sig, --IN STD_LOGIC_VECTOR (7 DOWNTO 0) busy => rsu_busy, --OUT STD_LOGIC; clock => rsu_clk, --IN STD_LOGIC; data_in => rsu_data_out, --IN STD_LOGIC_VECTOR (21 DOWNTO 0) := (OTHERS => '0'); data_out => rsu_data_in, --OUT STD_LOGIC_VECTOR (28 DOWNTO 0); param => rsu_param, --IN STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0'); read_param => read_param_cnt(0), --IN STD_LOGIC := '0'; read_source => read_source_sig, --IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0'); -- for Reconfiguring --reconfig => reconfig_cnt(3), --IN STD_LOGIC := '0'; -- for SignalTap reconfig => '0', reset => toggle_rst(0), --IN STD_LOGIC; reset_timer => '0', --IN STD_LOGIC := '0' write_param => write_param_cnt(0) --IN STD_LOGIC := '0' --asmi_addr => asmi_addr_sig, --OUT STD_LOGIC_VECTOR (23 DOWNTO 0); --asmi_rden => asmi_rden_sig, --OUT STD_LOGIC --asmi_read => asmi_read_sig, --OUT STD_LOGIC --pof_error => open --OUT STD_LOGIC ); --Sprig_AltParSer : parallel_serial_test_altasmi_parallel_n652 -- port map -- ( -- addr => rsu_data_in(23 downto 0), --: IN STD_LOGIC_VECTOR (23 DOWNTO 0); -- --addr => asmi_addr_sig, --: IN STD_LOGIC_VECTOR (23 DOWNTO 0); -- busy => asmi_busy_sig, --: OUT STD_LOGIC; -- clkin => rsu_clk, --: IN STD_LOGIC; -- data_valid => asmi_data_valid_sig, --: OUT STD_LOGIC; -- dataout => asmi_dataout_sig, --: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- rden => asmi_rden_sig, --: IN STD_LOGIC; -- read => asmi_read_sig, --: IN STD_LOGIC := '0'; -- reset => rsu_reset --: IN STD_LOGIC := '0' -- ); RSU_CONTROL : process(all) begin if (rsu_rst_n = '0') then rsu_init_done <= '0'; toggle_rst <= "00"; toggle_rst_done <= '0'; watchdog_val_set_done <= '0'; write_param_cnt <= "00"; write_param_done <= '0'; read_param_cnt <= "00"; read_param_done <= '0'; read_source_sig <= "00"; elsif(falling_edge(rsu_clk)) then if (rsu_enable = '1') then if (CurrentState = Init) then rsu_init_done <= '1'; elsif(CurrentState = ToggleReset) then if (toggle_rst < "10") then --rsu_data_out <= CONFIG_DATA; --rsu_param <= CONFIG_PARAM; --read_source_sig <= READ_WD_INFO; toggle_rst_done <= '0'; toggle_rst <= toggle_rst + '1'; else toggle_rst_done <= '1'; toggle_rst <= toggle_rst; end if; -- ===================================================== -- NOT USED ... THIS PARAMETER INVALID FOR CYCLONE IV -- ===================================================== elsif(CurrentState = SetConfig) then -- rsu_data_out <= TIMEOUT_VALUE; -- rsu_param <= PARAM_TIMEOUT_VAL; if (write_param_cnt < "10") then set_reconfig_done <= '0'; write_param_done <= '0'; write_param_cnt <= write_param_cnt + '1'; else if (rsu_busy = '1') then -- rsu_data_out <= rsu_data_out; -- rsu_param <= rsu_param; set_reconfig_done <= set_reconfig_done; write_param_cnt <= write_param_cnt; write_param_done <= write_param_done; else set_reconfig_done <= '1'; write_param_done <= '1'; read_param_cnt <= "00"; write_param_cnt <= write_param_cnt; rsu_data_out <= CONFIG_DATA; rsu_param <= CONFIG_PARAM; read_source_sig <= READ_WD_INFO; end if; end if; -- ===================================================== -- NOT USED ... THIS PARAMETER INVALID FOR CYCLONE IV -- ===================================================== elsif(CurrentState = ReadConfig) then -- rsu_data_out <= TIMEOUT_VALUE; -- rsu_param <= PARAM_TIMEOUT_VAL; if (read_param_cnt < "10") then read_reconfig_done <= '0'; read_param_done <= '0'; read_param_cnt <= read_param_cnt + '1'; else if (rsu_busy = '1') then -- rsu_data_out <= rsu_data_out; -- rsu_param <= rsu_param; read_reconfig_done <= read_reconfig_done; read_param_cnt <= read_param_cnt; read_param_done <= read_param_done; else read_reconfig_done <= '1'; read_param_done <= '1'; read_param_cnt <= read_param_cnt; write_param_cnt <= "00"; rsu_data_out <= TIMEOUT_VALUE; rsu_param <= PARAM_TIMEOUT_VAL; end if; end if; elsif(CurrentState = SetWatchdogTimeout) then -- rsu_data_out <= TIMEOUT_VALUE; -- rsu_param <= PARAM_TIMEOUT_VAL; if (write_param_cnt < "10") then watchdog_val_set_done <= '0'; write_param_done <= '0'; write_param_cnt <= write_param_cnt + '1'; else if (rsu_busy = '1') then -- rsu_data_out <= rsu_data_out; -- rsu_param <= rsu_param; watchdog_val_set_done <= watchdog_val_set_done; write_param_cnt <= write_param_cnt; write_param_done <= write_param_done; else watchdog_val_set_done <= '1'; write_param_done <= '1'; read_param_cnt <= "00"; write_param_cnt <= write_param_cnt; rsu_data_out <= TIMEOUT_VALUE; rsu_param <= PARAM_TIMEOUT_VAL; read_source_sig <= READ_WD_INFO; end if; end if; elsif(CurrentState = ReadWatchdogTimeout) then -- rsu_data_out <= TIMEOUT_VALUE; -- rsu_param <= PARAM_TIMEOUT_VAL; if (read_param_cnt < "10") then watchdog_val_read_done <= '0'; read_param_done <= '0'; read_param_cnt <= read_param_cnt + '1'; else if (rsu_busy = '1') then -- rsu_data_out <= rsu_data_out; -- rsu_param <= rsu_param; watchdog_val_read_done <= watchdog_val_read_done; read_param_cnt <= read_param_cnt; read_param_done <= read_param_done; else watchdog_val_read_done <= '1'; read_param_done <= '1'; read_param_cnt <= read_param_cnt; write_param_cnt <= "00"; rsu_data_out <= TIMEOUT_EN; rsu_param <= PARAM_TIMEOUT_EN; end if; end if; elsif(CurrentState = WatchdogEnable) then -- rsu_data_out <= TIMEOUT_EN; -- rsu_param <= PARAM_TIMEOUT_EN; if (write_param_cnt < "10") then watchdog_en_done <= '0'; write_param_done <= '0'; write_param_cnt <= write_param_cnt + '1'; else if (rsu_busy = '1') then -- rsu_data_out <= rsu_data_out; -- rsu_param <= rsu_param; watchdog_en_done <= watchdog_en_done; write_param_cnt <= write_param_cnt; write_param_done <= write_param_done; else watchdog_en_done <= '1'; write_param_done <= '1'; read_param_cnt <= "00"; write_param_cnt <= write_param_cnt; rsu_data_out <= TIMEOUT_EN; rsu_param <= PARAM_TIMEOUT_EN; end if; end if; elsif(CurrentState = ReadWatchdogEnable) then -- rsu_data_out <= TIMEOUT_EN; -- rsu_param <= PARAM_TIMEOUT_EN; if (read_param_cnt < "10") then watchdog_en_read_done <= '0'; read_param_done <= '0'; read_param_cnt <= read_param_cnt + '1'; else if (rsu_busy = '1') then -- rsu_data_out <= rsu_data_out; -- rsu_param <= rsu_param; watchdog_en_read_done <= watchdog_en_read_done; read_param_cnt <= read_param_cnt; read_param_done <= read_param_done; else watchdog_en_read_done <= '1'; read_param_done <= '1'; read_param_cnt <= read_param_cnt; write_param_cnt <= "00"; rsu_data_out <= BOOT_ADDRESS; rsu_param <= PARAM_BOOT_ADDR; end if; end if; elsif(CurrentState = SetBoodAddress) then --rsu_data_out <= BOOT_ADDRESS; --rsu_param <= PARAM_BOOT_ADDR; if (write_param_cnt < "10") then set_boot_addr_done <= '0'; write_param_done <= '0'; write_param_cnt <= write_param_cnt + '1'; else if (rsu_busy = '1') then -- rsu_data_out <= rsu_data_out; -- rsu_param <= rsu_param; set_boot_addr_done <= set_boot_addr_done; write_param_cnt <= write_param_cnt; write_param_done <= write_param_done; else set_boot_addr_done <= '1'; write_param_done <= '1'; read_param_cnt <= "00"; write_param_cnt <= write_param_cnt; rsu_data_out <= BOOT_ADDRESS; rsu_param <= PARAM_BOOT_ADDR; read_source_sig <= READ_BOOT_ADDR; end if; end if; elsif(CurrentState = ReadBootAddress) then --rsu_data_out <= BOOT_ADDRESS; --rsu_param <= PARAM_BOOT_ADDR; if (read_param_cnt < "10") then read_boot_addr_done <= '0'; read_param_done <= '0'; read_param_cnt <= read_param_cnt + '1'; else if (rsu_busy = '1') then -- rsu_data_out <= rsu_data_out; -- rsu_param <= rsu_param; read_boot_addr_done <= read_boot_addr_done; read_param_cnt <= read_param_cnt; read_param_done <= read_param_done; else read_boot_addr_done <= '1'; read_param_done <= '1'; read_param_cnt <= read_param_cnt; write_param_cnt <= "00"; rsu_data_out <= BOOT_ADDRESS; rsu_param <= PARAM_BOOT_ADDR; end if; end if; elsif(CurrentState = SetReconfigure) then if (rsu_busy = '1') then -- rsu_data_out <= rsu_data_out; -- rsu_param <= rsu_param; reconfig_cnt <= reconfig_cnt; reconfig_done <= reconfig_done; else rsu_data_out <= BOOT_ADDRESS; rsu_param <= PARAM_BOOT_ADDR; if (reconfig_cnt(4 downto 3) < "10") then reconfig_done <= '0'; reconfig_cnt <= reconfig_cnt + '1'; else reconfig_done <= '1'; reconfig_cnt <= reconfig_cnt; rsu_data_out <= BOOT_ADDRESS; rsu_param <= PARAM_BOOT_ADDR; end if; end if; elsif(CurrentState = Finish) then if(rsu_busy = '1') then stay_in_finish <= '1'; else stay_in_finish <= '1'; end if; end if; -- else end if; end if; end process; STATE_ORDER_FLOW : process(all) begin case CurrentState is when Init => if (rsu_rst_n = '0') then NextState <= Init; elsif (rsu_init_done = '1') then NextState <= ToggleReset; else NextState <= Init; end if; when ToggleReset => if (rsu_rst_n = '0') then NextState <= Init; elsif (toggle_rst_done = '1') then NextState <= SetWatchdogTimeout; else NextState <= ToggleReset; end if; -- ===================================================== -- SKIPPED ... THIS PARAMETER INVALID FOR CYCLONE IV -- ===================================================== when SetConfig => if (rsu_rst_n = '0') then NextState <= Init; elsif(set_reconfig_done = '1') then NextState <= ReadConfig; else NextState <= SetConfig; end if; -- ===================================================== -- SKIPPED ... THIS PARAMETER INVALID FOR CYCLONE IV -- ===================================================== when ReadConfig => if (rsu_rst_n = '0') then NextState <= Init; elsif(read_reconfig_done = '1') then NextState <= SetWatchdogTimeout; else NextState <= ReadConfig; end if; when SetWatchdogTimeout => if (rsu_rst_n = '0') then NextState <= Init; elsif(watchdog_val_set_done = '1') then NextState <= ReadWatchdogTimeout; else NextState <= SetWatchdogTimeout; end if; when ReadWatchdogTimeout => if (rsu_rst_n = '0') then NextState <= Init; elsif(watchdog_val_read_done = '1') then NextState <= WatchdogEnable; else NextState <= ReadWatchdogTimeout; end if; when WatchdogEnable => if (rsu_rst_n = '0') then NextState <= Init; elsif(watchdog_en_done = '1') then NextState <= ReadWatchdogEnable; else NextState <= WatchdogEnable; end if; when ReadWatchdogEnable => if (rsu_rst_n = '0') then NextState <= Init; elsif(watchdog_en_read_done = '1') then NextState <= SetBoodAddress; else NextState <= ReadWatchdogEnable; end if; when SetBoodAddress => if (rsu_rst_n = '0') then NextState <= Init; elsif(set_boot_addr_done = '1') then NextState <= ReadBootAddress; else NextState <= SetBoodAddress; end if; when ReadBootAddress => if (rsu_rst_n = '0') then NextState <= Init; elsif(read_boot_addr_done = '1') then NextState <= SetReconfigure; else NextState <= ReadBootAddress; end if; when SetReconfigure => if (rsu_rst_n = '0') then NextState <= Init; elsif(reconfig_done = '1') then NextState <= Finish; else NextState <= SetReconfigure; end if; when Finish => if (rsu_rst_n = '0') then NextState <= Init; elsif(stay_in_finish = '1') then NextState <= Finish; else NextState <= Finish; end if; when others => NextState <= Init; end case; end process; CURRENT_TO_NEXT : process(all) -- ================================================================== -- Current state = next state at rising edge of system clock -- ================================================================== begin if (rsu_rst_n = '0') then CurrentState <= Init; elsif(falling_edge(rsu_clk)) then CurrentState <= NextState; end if; end process; rsu_busy_out <= rsu_busy; rsu_reconfig_out <= reconfig_cnt(3); rsu_reset_out <= toggle_rst(0); rsu_reset_tmr_out <= '0'; rsu_write_param_out <= write_param_cnt(0); end rtl;