//
// RAMB16_S36_S36 Xilinx Primitive equivalent
//
module RAMB16_S36_S36 (
    DIA,
    WEA,
    ADDRA,
    DIB,
    ADDRB,
    WEB,
    CLKA,
    ENA,
    CLKB,
    ENB,
    SSRA,
    SSRB,
    DOA,
    DOB,
    DIPA,
    DIPB,
    DOPA,
    DOPB
    );
    
input [31:0]    DIA;
input           WEA;
input [8:0]     ADDRA;
input [31:0]    DIB;
input [8:0]     ADDRB;
input           WEB;
input           CLKA;
input           ENA;
input           CLKB;
input           ENB;
input           SSRA;
input           SSRB;
input [3:0]     DIPA;
input [3:0]     DIPB;

output [31:0]   DOA;
output [31:0]   DOB;
output [3:0]    DOPA;
output [3:0]    DOPB;

// Intantiations

altsyncram altsyncram_component (  
    .clocken0 (ENA),    
    .clocken1 (ENB),    
    .wren_a (WEA),  
    .aclr0 (1'b0),  
    .clock0 (CLKA), 
    .wren_b (WEB),  
    .aclr1 (1'b0),  
    .clock1 (CLKB), 
    .address_a (ADDRA), 
    .address_b (ADDRB), 
    .data_a ({DIPA,DIA}),   
    .data_b ({DIPB,DIB}),   
    .q_a ({DOPA,DOA}),  
    .q_b ({DOPB,DOB})
    ); 

defparam
    altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
    altsyncram_component.width_a = 36,
    altsyncram_component.widthad_a = 9,
    altsyncram_component.numwords_a = 512,
    altsyncram_component.width_b = 36,
    altsyncram_component.widthad_b = 9,
    altsyncram_component.numwords_b = 512,
    altsyncram_component.width_byteena_a = 1,
    altsyncram_component.width_byteena_b = 1,
    altsyncram_component.outdata_reg_a = "UNREGISTERED",
    altsyncram_component.outdata_aclr_a = "NONE",
    altsyncram_component.outdata_reg_b = "UNREGISTERED",
    altsyncram_component.indata_aclr_a = "CLEAR0",
    altsyncram_component.wrcontrol_aclr_a = "CLEAR0",
    altsyncram_component.address_aclr_a = "CLEAR0",
    altsyncram_component.indata_reg_b = "CLOCK1",
    altsyncram_component.address_reg_b = "CLOCK1",
    altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1",
    altsyncram_component.indata_aclr_b = "CLEAR1",
    altsyncram_component.wrcontrol_aclr_b = "CLEAR1",
    altsyncram_component.address_aclr_b = "CLEAR1",
    altsyncram_component.outdata_aclr_b = "NONE",
    altsyncram_component.ram_block_type = "AUTO",
    altsyncram_component.intended_device_family = "Stratix";
    
endmodule // RAMB4_S36_S36