module Gen62_5usecPulse ( 
						 input      ClockIn50MHz , 
						 output reg PulseOut_62_5uSec);

reg [9:0] counter_16kHz_delay = 0;
always @ ( posedge ClockIn50MHz )
if ( counter_16kHz_delay === 10'd0 )
  // the needed delay is 50MHz / 16kHz that is 833,3333333
  // reload with (833 + 833 + 834) / 3 = 833,33333
  // whenever counter_16kHz_cor is 0 the reload value is 834 instead of 833
  counter_16kHz_delay <= ( counter_16kHz_cor == 2'd0 ) ? 10'd834 : 10'd833;
else
  counter_16kHz_delay <= counter_16kHz_delay - 10'd1;
  
reg [1:0] counter_16kHz_cor = 0;
always @ ( posedge ClockIn50MHz )
if ( counter_16kHz_delay === 10'd0 )
  // count each 16KHz pulse modulo 3
  if ( counter_16kHz_cor === 2'd0 )
    counter_16kHz_cor <= 2'd2; 
  else 
    counter_16kHz_cor <= counter_16kHz_cor - 2'd1;
else
  counter_16kHz_cor <= counter_16kHz_cor;
  
reg [3:0] counter_65usec = 0;
always @ ( posedge ClockIn50MHz )
if ( counter_16kHz_delay === 10'd0 )
  // counter for the complete 10 pulse period
  counter_65usec <= ( counter_65usec === 4'd0 ) ? 4'd9 : counter_65usec - 4'd1;
else
  counter_65usec <= counter_65usec;
  
always @ ( posedge ClockIn50MHz )
  // finaly the desired pulse as registered output
  PulseOut_62_5uSec <= counter_65usec === 4'd0;
  
endmodule