module	auto_config_ctrl	(
							clk				,
							rst				,
							en_n			,
							config_done_n	,
							pb0_auto		,
							pb1_auto	
							);
parameter		COUNTER_DW	=16			;
parameter		COUNTER_END	=65500		;
input					clk				;
input					rst				;
input					en_n			;
input					config_done_n	;
output	wire			pb0_auto		;
output	wire			pb1_auto    	;

//////////////////////////////////////////////
//FSM
parameter	WD	=2						;
reg			[WD-1:0]			cs,ns	;
reg			[COUNTER_DW-1:0]	counter	;
parameter	idle			=	2'd0	;					
parameter	wait_cfg_f0		=	2'd1	;					
parameter	wait_cfg_f1		=	2'd2	;					
parameter	auto_cfg_done	=	2'd3	;					
			
			
always @ (posedge clk, negedge rst)
if(!rst)
	cs	<=idle		;
else
	cs	<=ns		;
			
always @ (*)
begin
	case(cs)
	idle:	begin
				if(!en_n && counter==COUNTER_END)
				ns	=wait_cfg_f0		;
				else	
				ns	=idle		;
			end	
	wait_cfg_f0:	
			begin
				if(!config_done_n)
				ns	=wait_cfg_f1		;
				else	
				ns	=wait_cfg_f0		;
			end
	wait_cfg_f1:	
			begin
				if(!config_done_n)
				ns	=auto_cfg_done		;
				else	
				ns	=wait_cfg_f1		;
			end		
	auto_cfg_done:	begin
				ns	=auto_cfg_done		;
			end		
	default:	ns	=idle		;
	endcase
end	

always @ (posedge clk, negedge rst)
begin
	if(!rst)
	begin
		counter		<={COUNTER_DW{1'b0}}		;
	end
	else
	begin
		case(ns)
		idle:			begin counter		<=counter+1'b1		; end
		wait_cfg_f0:	begin end
		wait_cfg_f1:	begin end
		auto_cfg_done:	begin end
		default:begin
				counter		<={COUNTER_DW{1'b0}}		;
				end
		endcase
	end
end						
							
assign		pb0_auto=!((ns==wait_cfg_f0)&&(cs==idle))			;
assign		pb1_auto=!((ns==wait_cfg_f1)&&(cs==wait_cfg_f0))	;
							
endmodule