module main (clk, in1,out1);

input in1;
input clk;

output out1;


wire b_to_a;
wire a_to_out;

// Instance module a

a inst_a (.in(b_to_a),.out(a_to_out)); // connection by name

// Instance module b

//b inst_b (.clk(clk),.in(in1),.out(b_to_a));

b inst_b (in1, b_to_a, clk);

assign out1 = a_to_out;

endmodule

module a ( in, out);

input in;
output out;

assign out = !in;

endmodule

module b (in, out ,clk);

input in;
input clk;

output out;

reg reg_int;

always @(posedge clk) begin
 reg_int <= in;
end

assign out = reg_int;

endmodule
