// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2010 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
// Created on Mon Feb 21 15:54:04 2011

//  Module Declaration
module CEalu
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	dataA, dataB, fSel, qa, alb, aeb, agb
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
// Port Declaration
);
input [width - 1: 0] dataA, dataB;
input [width - 29: 0] fSel;
output [width - 1: 0] qa;
output alb, aeb, agb;
wire [width - 1: 0] add, sub, n, o, x, qa;
wire alb, aeb, agb;
reg aluout;
parameter width = 32;
always @(fSel[0] or fSel[1] or fSel[2])
begin
//if(fSel[1] == 1)

//if(fSel[1] == 0)

//end
case(fSel)
0:aluout = 0;
1:aluout = 1;
2:aluout = add;
3:aluout = sub;
4:aluout = band;
5:aluout = bor;
6:aluout = bxor;
7:aluout = 7;
endcase
end
assign add = dataA + dataB;
assign sub = dataA - dataB;
assign band = dataA & dataB;
assign bor = dataA | dataB;
assign bxor = dataA ^ dataB;
assign sub = dataA - dataB;
assign qa = add;

endmodule