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// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr1_data_fifo
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_i_llvm_fpga_sfc_exit_s_c0_out_0002c_compstr1_data_fifo (
    output wire [0:0] out_o_almost_empty,
    output wire [0:0] out_o_data_0_tpl,
    output wire [0:0] out_o_data_1_tpl,
    output wire [0:0] out_o_data_2_tpl,
    output wire [0:0] out_o_data_3_tpl,
    output wire [0:0] out_o_data_4_tpl,
    output wire [0:0] out_o_data_5_tpl,
    output wire [0:0] out_o_data_6_tpl,
    output wire [0:0] out_o_data_7_tpl,
    output wire [0:0] out_o_data_8_tpl,
    output wire [0:0] out_o_data_9_tpl,
    output wire [31:0] out_o_data_10_tpl,
    output wire [0:0] out_o_empty,
    output wire [0:0] out_o_valid,
    input wire [0:0] in_almost_empty_in,
    input wire [0:0] in_empty_in,
    input wire [0:0] in_i_data_0_tpl,
    input wire [0:0] in_i_data_1_tpl,
    input wire [0:0] in_i_data_2_tpl,
    input wire [0:0] in_i_data_3_tpl,
    input wire [0:0] in_i_data_4_tpl,
    input wire [0:0] in_i_data_5_tpl,
    input wire [0:0] in_i_data_6_tpl,
    input wire [0:0] in_i_data_7_tpl,
    input wire [0:0] in_i_data_8_tpl,
    input wire [0:0] in_i_data_9_tpl,
    input wire [31:0] in_i_data_10_tpl,
    input wire [0:0] in_i_valid,
    input wire [0:0] in_i_stall,
    output wire [0:0] out_o_stall,
    input wire clock,
    input wire resetn
    );

    wire [0:0] adapt_scalar_trunc26_in;
    wire [0:0] adapt_scalar_trunc26_q;
    wire [0:0] adapt_scalar_trunc28_in;
    wire [0:0] adapt_scalar_trunc28_q;
    wire [0:0] adapt_scalar_trunc30_in;
    wire [0:0] adapt_scalar_trunc30_q;
    wire [0:0] adapt_scalar_trunc32_in;
    wire [0:0] adapt_scalar_trunc32_q;
    wire [0:0] adapt_scalar_trunc34_in;
    wire [0:0] adapt_scalar_trunc34_q;
    wire [0:0] adapt_scalar_trunc36_in;
    wire [0:0] adapt_scalar_trunc36_q;
    wire [0:0] adapt_scalar_trunc38_in;
    wire [0:0] adapt_scalar_trunc38_q;
    wire [0:0] adapt_scalar_trunc40_in;
    wire [0:0] adapt_scalar_trunc40_q;
    wire [0:0] adapt_scalar_trunc42_in;
    wire [0:0] adapt_scalar_trunc42_q;
    wire [0:0] adapt_scalar_trunc44_in;
    wire [0:0] adapt_scalar_trunc44_q;
    wire [15:0] c_i16_023_q;
    wire [6:0] c_i7_010_q;
    wire [127:0] dsdk_ip_adapt_bitjoin1_q;
    wire [7:0] element_extension11_q;
    wire [7:0] element_extension13_q;
    wire [7:0] element_extension15_q;
    wire [7:0] element_extension17_q;
    wire [7:0] element_extension19_q;
    wire [7:0] element_extension21_q;
    wire [7:0] element_extension3_q;
    wire [7:0] element_extension5_q;
    wire [7:0] element_extension7_q;
    wire [7:0] element_extension9_q;
    wire [127:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_data;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_stall;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_stall_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_valid;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_almost_empty;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_almost_empty_bitsignaltemp;
    wire [127:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_data;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_empty;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_empty_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_stall;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_stall_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_valid;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_valid_bitsignaltemp;
    wire [0:0] ip_dsdk_adapt_bitselect25_b;
    wire [0:0] ip_dsdk_adapt_bitselect27_b;
    wire [0:0] ip_dsdk_adapt_bitselect29_b;
    wire [0:0] ip_dsdk_adapt_bitselect31_b;
    wire [0:0] ip_dsdk_adapt_bitselect33_b;
    wire [0:0] ip_dsdk_adapt_bitselect35_b;
    wire [0:0] ip_dsdk_adapt_bitselect37_b;
    wire [0:0] ip_dsdk_adapt_bitselect39_b;
    wire [0:0] ip_dsdk_adapt_bitselect41_b;
    wire [0:0] ip_dsdk_adapt_bitselect43_b;
    wire [31:0] ip_dsdk_adapt_bitselect45_b;


    // ip_dsdk_adapt_bitselect45(BITSELECT,47)
    assign ip_dsdk_adapt_bitselect45_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_data[127:96];

    // ip_dsdk_adapt_bitselect43(BITSELECT,46)
    assign ip_dsdk_adapt_bitselect43_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_data[72:72];

    // adapt_scalar_trunc44(ROUND,13)
    assign adapt_scalar_trunc44_in = ip_dsdk_adapt_bitselect43_b;
    assign adapt_scalar_trunc44_q = adapt_scalar_trunc44_in[0:0];

    // ip_dsdk_adapt_bitselect41(BITSELECT,45)
    assign ip_dsdk_adapt_bitselect41_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_data[64:64];

    // adapt_scalar_trunc42(ROUND,12)
    assign adapt_scalar_trunc42_in = ip_dsdk_adapt_bitselect41_b;
    assign adapt_scalar_trunc42_q = adapt_scalar_trunc42_in[0:0];

    // ip_dsdk_adapt_bitselect39(BITSELECT,44)
    assign ip_dsdk_adapt_bitselect39_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_data[56:56];

    // adapt_scalar_trunc40(ROUND,11)
    assign adapt_scalar_trunc40_in = ip_dsdk_adapt_bitselect39_b;
    assign adapt_scalar_trunc40_q = adapt_scalar_trunc40_in[0:0];

    // ip_dsdk_adapt_bitselect37(BITSELECT,43)
    assign ip_dsdk_adapt_bitselect37_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_data[48:48];

    // adapt_scalar_trunc38(ROUND,10)
    assign adapt_scalar_trunc38_in = ip_dsdk_adapt_bitselect37_b;
    assign adapt_scalar_trunc38_q = adapt_scalar_trunc38_in[0:0];

    // ip_dsdk_adapt_bitselect35(BITSELECT,42)
    assign ip_dsdk_adapt_bitselect35_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_data[40:40];

    // adapt_scalar_trunc36(ROUND,9)
    assign adapt_scalar_trunc36_in = ip_dsdk_adapt_bitselect35_b;
    assign adapt_scalar_trunc36_q = adapt_scalar_trunc36_in[0:0];

    // ip_dsdk_adapt_bitselect33(BITSELECT,41)
    assign ip_dsdk_adapt_bitselect33_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_data[32:32];

    // adapt_scalar_trunc34(ROUND,8)
    assign adapt_scalar_trunc34_in = ip_dsdk_adapt_bitselect33_b;
    assign adapt_scalar_trunc34_q = adapt_scalar_trunc34_in[0:0];

    // ip_dsdk_adapt_bitselect31(BITSELECT,40)
    assign ip_dsdk_adapt_bitselect31_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_data[24:24];

    // adapt_scalar_trunc32(ROUND,7)
    assign adapt_scalar_trunc32_in = ip_dsdk_adapt_bitselect31_b;
    assign adapt_scalar_trunc32_q = adapt_scalar_trunc32_in[0:0];

    // ip_dsdk_adapt_bitselect29(BITSELECT,39)
    assign ip_dsdk_adapt_bitselect29_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_data[16:16];

    // adapt_scalar_trunc30(ROUND,6)
    assign adapt_scalar_trunc30_in = ip_dsdk_adapt_bitselect29_b;
    assign adapt_scalar_trunc30_q = adapt_scalar_trunc30_in[0:0];

    // ip_dsdk_adapt_bitselect27(BITSELECT,38)
    assign ip_dsdk_adapt_bitselect27_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_data[8:8];

    // adapt_scalar_trunc28(ROUND,5)
    assign adapt_scalar_trunc28_in = ip_dsdk_adapt_bitselect27_b;
    assign adapt_scalar_trunc28_q = adapt_scalar_trunc28_in[0:0];

    // ip_dsdk_adapt_bitselect25(BITSELECT,37)
    assign ip_dsdk_adapt_bitselect25_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_data[0:0];

    // adapt_scalar_trunc26(ROUND,4)
    assign adapt_scalar_trunc26_in = ip_dsdk_adapt_bitselect25_b;
    assign adapt_scalar_trunc26_q = adapt_scalar_trunc26_in[0:0];

    // c_i16_023(CONSTANT,14)
    assign c_i16_023_q = $unsigned(16'b0000000000000000);

    // c_i7_010(CONSTANT,15)
    assign c_i7_010_q = $unsigned(7'b0000000);

    // element_extension21(BITJOIN,31)
    assign element_extension21_q = {c_i7_010_q, in_i_data_9_tpl};

    // element_extension19(BITJOIN,30)
    assign element_extension19_q = {c_i7_010_q, in_i_data_8_tpl};

    // element_extension17(BITJOIN,29)
    assign element_extension17_q = {c_i7_010_q, in_i_data_7_tpl};

    // element_extension15(BITJOIN,28)
    assign element_extension15_q = {c_i7_010_q, in_i_data_6_tpl};

    // element_extension13(BITJOIN,27)
    assign element_extension13_q = {c_i7_010_q, in_i_data_5_tpl};

    // element_extension11(BITJOIN,26)
    assign element_extension11_q = {c_i7_010_q, in_i_data_4_tpl};

    // element_extension9(BITJOIN,35)
    assign element_extension9_q = {c_i7_010_q, in_i_data_3_tpl};

    // element_extension7(BITJOIN,34)
    assign element_extension7_q = {c_i7_010_q, in_i_data_2_tpl};

    // element_extension5(BITJOIN,33)
    assign element_extension5_q = {c_i7_010_q, in_i_data_1_tpl};

    // element_extension3(BITJOIN,32)
    assign element_extension3_q = {c_i7_010_q, in_i_data_0_tpl};

    // dsdk_ip_adapt_bitjoin1(BITJOIN,25)
    assign dsdk_ip_adapt_bitjoin1_q = {in_i_data_10_tpl, c_i16_023_q, element_extension21_q, element_extension19_q, element_extension17_q, element_extension15_q, element_extension13_q, element_extension11_q, element_extension9_q, element_extension7_q, element_extension5_q, element_extension3_q};

    // i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0(EXTIFACE,36)
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_data = dsdk_ip_adapt_bitjoin1_q;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_stall = in_i_stall;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_valid = in_i_valid;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_stall_bitsignaltemp = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_stall[0];
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_valid_bitsignaltemp = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_valid[0];
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_almost_empty[0] = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_almost_empty_bitsignaltemp;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_empty[0] = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_empty_bitsignaltemp;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_stall[0] = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_stall_bitsignaltemp;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_valid[0] = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_valid_bitsignaltemp;
    hld_fifo #(
        .ALMOST_EMPTY_CUTOFF(7),
        .DEPTH(512),
        .STYLE("ms"),
        .ASYNC_RESET(0),
        .NEVER_OVERFLOWS(1),
        .RESET_EXTERNALLY_HELD(1),
        .STALL_IN_EARLINESS(3),
        .SYNCHRONIZE_RESET(0),
        .USE_STALL_LATENCY_DOWNSTREAM(1),
        .USE_STALL_LATENCY_UPSTREAM(1),
        .WIDTH(128)
    ) thei_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0 (
        .i_data(dsdk_ip_adapt_bitjoin1_q),
        .i_stall(i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_stall_bitsignaltemp),
        .i_valid(i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_i_valid_bitsignaltemp),
        .o_almost_empty(i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_almost_empty_bitsignaltemp),
        .o_data(i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_data),
        .o_empty(i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_empty_bitsignaltemp),
        .o_stall(i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_stall_bitsignaltemp),
        .o_valid(i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_valid_bitsignaltemp),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_sync_out_aunroll_x(GPOUT,2)@20000000
    assign out_o_almost_empty = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_almost_empty;
    assign out_o_data_0_tpl = adapt_scalar_trunc26_q;
    assign out_o_data_1_tpl = adapt_scalar_trunc28_q;
    assign out_o_data_2_tpl = adapt_scalar_trunc30_q;
    assign out_o_data_3_tpl = adapt_scalar_trunc32_q;
    assign out_o_data_4_tpl = adapt_scalar_trunc34_q;
    assign out_o_data_5_tpl = adapt_scalar_trunc36_q;
    assign out_o_data_6_tpl = adapt_scalar_trunc38_q;
    assign out_o_data_7_tpl = adapt_scalar_trunc40_q;
    assign out_o_data_8_tpl = adapt_scalar_trunc42_q;
    assign out_o_data_9_tpl = adapt_scalar_trunc44_q;
    assign out_o_data_10_tpl = ip_dsdk_adapt_bitselect45_b;
    assign out_o_empty = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_empty;
    assign out_o_valid = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_valid;

    // sync_out(GPOUT,50)@20000000
    assign out_o_stall = i_llvm_fpga_sfc_exit_s_c0_out_for_body20_c_compstrs_c0_exit714_c_compstr0_o_stall;

endmodule
