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// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from c_compSTR_function
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:08 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_function (
    input wire [63:0] in_arg_WStream,
    input wire [63:0] in_arg_call,
    input wire [63:0] in_arg_resStream,
    input wire [63:0] in_arg_return,
    input wire [63:0] in_arg_yStream,
    input wire [31:0] in_iord_bl_WStream_i_fifodata,
    input wire [0:0] in_iord_bl_WStream_i_fifovalid,
    input wire [0:0] in_iord_bl_call_c_compSTR_i_fifodata,
    input wire [0:0] in_iord_bl_call_c_compSTR_i_fifovalid,
    input wire [31:0] in_iord_bl_yStream_i_fifodata,
    input wire [0:0] in_iord_bl_yStream_i_fifovalid,
    input wire [0:0] in_iowr_bl_resStream_i_fifoready,
    input wire [0:0] in_iowr_bl_return_c_compSTR_i_fifoready,
    input wire [4095:0] in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdata,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdatavalid,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writeack,
    input wire [4095:0] in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdata,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdatavalid,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writeack,
    input wire [4095:0] in_memdep_17_c_compSTR_avm_readdata,
    input wire [0:0] in_memdep_17_c_compSTR_avm_readdatavalid,
    input wire [0:0] in_memdep_17_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memdep_17_c_compSTR_avm_writeack,
    input wire [4095:0] in_memdep_5_c_compSTR_avm_readdata,
    input wire [0:0] in_memdep_5_c_compSTR_avm_readdatavalid,
    input wire [0:0] in_memdep_5_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memdep_5_c_compSTR_avm_writeack,
    input wire [0:0] in_stall_in,
    input wire [0:0] in_start,
    input wire [0:0] in_valid_in,
    output wire [0:0] out_iord_bl_WStream_o_fifoalmost_full,
    output wire [0:0] out_iord_bl_WStream_o_fifoready,
    output wire [0:0] out_iord_bl_call_c_compSTR_o_fifoalmost_full,
    output wire [0:0] out_iord_bl_call_c_compSTR_o_fifoready,
    output wire [0:0] out_iord_bl_yStream_o_fifoalmost_full,
    output wire [0:0] out_iord_bl_yStream_o_fifoready,
    output wire [31:0] out_iowr_bl_resStream_o_fifodata,
    output wire [0:0] out_iowr_bl_resStream_o_fifovalid,
    output wire [0:0] out_iowr_bl_return_c_compSTR_o_fifodata,
    output wire [0:0] out_iowr_bl_return_c_compSTR_o_fifovalid,
    output wire [31:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount,
    output wire [511:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write,
    output wire [4095:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata,
    output wire [31:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount,
    output wire [511:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write,
    output wire [4095:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata,
    output wire [31:0] out_memdep_17_c_compSTR_avm_address,
    output wire [0:0] out_memdep_17_c_compSTR_avm_burstcount,
    output wire [511:0] out_memdep_17_c_compSTR_avm_byteenable,
    output wire [0:0] out_memdep_17_c_compSTR_avm_enable,
    output wire [0:0] out_memdep_17_c_compSTR_avm_read,
    output wire [0:0] out_memdep_17_c_compSTR_avm_write,
    output wire [4095:0] out_memdep_17_c_compSTR_avm_writedata,
    output wire [31:0] out_memdep_5_c_compSTR_avm_address,
    output wire [0:0] out_memdep_5_c_compSTR_avm_burstcount,
    output wire [511:0] out_memdep_5_c_compSTR_avm_byteenable,
    output wire [0:0] out_memdep_5_c_compSTR_avm_enable,
    output wire [0:0] out_memdep_5_c_compSTR_avm_read,
    output wire [0:0] out_memdep_5_c_compSTR_avm_write,
    output wire [4095:0] out_memdep_5_c_compSTR_avm_writedata,
    output wire [0:0] out_stall_out,
    output wire [0:0] out_valid_out,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    wire [0:0] bb_c_compSTR_B0_runOnce_out_stall_out_0;
    wire [0:0] bb_c_compSTR_B0_runOnce_out_valid_out_0;
    wire [0:0] bb_c_compSTR_B1_start_out_feedback_stall_out_10;
    wire [0:0] bb_c_compSTR_B1_start_out_iord_bl_call_c_compSTR_o_fifoalmost_full;
    wire [0:0] bb_c_compSTR_B1_start_out_iord_bl_call_c_compSTR_o_fifoready;
    wire [0:0] bb_c_compSTR_B1_start_out_memdep_phi_pop9;
    wire [0:0] bb_c_compSTR_B1_start_out_stall_out_0;
    wire [0:0] bb_c_compSTR_B1_start_out_valid_in_0;
    wire [0:0] bb_c_compSTR_B1_start_out_valid_out_0;
    wire [0:0] bb_c_compSTR_B2_out_stall_out_0;
    wire [0:0] bb_c_compSTR_B2_out_valid_out_0;
    wire [31:0] bb_c_compSTR_B3_out_c0_exe1697;
    wire [0:0] bb_c_compSTR_B3_out_c0_exe2698;
    wire [0:0] bb_c_compSTR_B3_out_c0_exe4;
    wire [0:0] bb_c_compSTR_B3_out_c0_exe5;
    wire [0:0] bb_c_compSTR_B3_out_c0_exe6;
    wire [0:0] bb_c_compSTR_B3_out_c0_exe7;
    wire [0:0] bb_c_compSTR_B3_out_c0_exe8;
    wire [0:0] bb_c_compSTR_B3_out_stall_out_0;
    wire [0:0] bb_c_compSTR_B3_out_valid_in_0;
    wire [0:0] bb_c_compSTR_B3_out_valid_out_0;
    wire [0:0] bb_c_compSTR_B4_out_stall_in_0;
    wire [0:0] bb_c_compSTR_B4_out_stall_out_0;
    wire [0:0] bb_c_compSTR_B4_out_valid_in_0;
    wire [0:0] bb_c_compSTR_B4_out_valid_out_0;
    wire [0:0] bb_c_compSTR_B5_out_c0_exe6720;
    wire [0:0] bb_c_compSTR_B5_out_iord_bl_WStream_o_fifoalmost_full;
    wire [0:0] bb_c_compSTR_B5_out_iord_bl_WStream_o_fifoready;
    wire [0:0] bb_c_compSTR_B5_out_iord_bl_yStream_o_fifoalmost_full;
    wire [0:0] bb_c_compSTR_B5_out_iord_bl_yStream_o_fifoready;
    wire [31:0] bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_address;
    wire [0:0] bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_burstcount;
    wire [511:0] bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_byteenable;
    wire [0:0] bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_enable;
    wire [0:0] bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_read;
    wire [0:0] bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_write;
    wire [4095:0] bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_writedata;
    wire [31:0] bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_address;
    wire [0:0] bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_burstcount;
    wire [511:0] bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_byteenable;
    wire [0:0] bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_enable;
    wire [0:0] bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_read;
    wire [0:0] bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_write;
    wire [4095:0] bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_writedata;
    wire [0:0] bb_c_compSTR_B5_out_profile_loop_o_valid;
    wire [0:0] bb_c_compSTR_B5_out_stall_in_0;
    wire [0:0] bb_c_compSTR_B5_out_stall_out_0;
    wire [0:0] bb_c_compSTR_B5_out_valid_in_0;
    wire [0:0] bb_c_compSTR_B5_out_valid_out_0;
    wire [0:0] bb_c_compSTR_B6_out_feedback_almost_empty_out_10;
    wire [0:0] bb_c_compSTR_B6_out_feedback_data_out_10;
    wire [0:0] bb_c_compSTR_B6_out_feedback_empty_out_10;
    wire [0:0] bb_c_compSTR_B6_out_iowr_bl_return_c_compSTR_o_fifodata;
    wire [0:0] bb_c_compSTR_B6_out_iowr_bl_return_c_compSTR_o_fifovalid;
    wire [0:0] bb_c_compSTR_B6_out_stall_in_0;
    wire [0:0] bb_c_compSTR_B6_out_stall_out_0;
    wire [0:0] bb_c_compSTR_B6_out_valid_in_0;
    wire [0:0] bb_c_compSTR_B6_out_valid_out_0;
    wire [0:0] bb_c_compSTR_B7_out_c0_exe1732;
    wire [31:0] bb_c_compSTR_B7_out_iowr_bl_resStream_o_fifodata;
    wire [0:0] bb_c_compSTR_B7_out_iowr_bl_resStream_o_fifovalid;
    wire [31:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address;
    wire [0:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount;
    wire [511:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable;
    wire [0:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable;
    wire [0:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read;
    wire [0:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write;
    wire [4095:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata;
    wire [31:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address;
    wire [0:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount;
    wire [511:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable;
    wire [0:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable;
    wire [0:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read;
    wire [0:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write;
    wire [4095:0] bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata;
    wire [0:0] bb_c_compSTR_B7_out_profile_loop_o_valid;
    wire [0:0] bb_c_compSTR_B7_out_stall_in_0;
    wire [0:0] bb_c_compSTR_B7_out_stall_out_0;
    wire [0:0] bb_c_compSTR_B7_out_valid_in_0;
    wire [0:0] bb_c_compSTR_B7_out_valid_out_0;
    wire [0:0] c_compSTR_B1_start_x_i_capture;
    wire c_compSTR_B1_start_x_i_capture_bitsignaltemp;
    wire [0:0] c_compSTR_B1_start_x_i_clear;
    wire c_compSTR_B1_start_x_i_clear_bitsignaltemp;
    wire [0:0] c_compSTR_B1_start_x_i_enable;
    wire c_compSTR_B1_start_x_i_enable_bitsignaltemp;
    wire [0:0] c_compSTR_B1_start_x_i_shift;
    wire c_compSTR_B1_start_x_i_shift_bitsignaltemp;
    wire [0:0] c_compSTR_B1_start_x_i_stall_pred;
    wire c_compSTR_B1_start_x_i_stall_pred_bitsignaltemp;
    wire [0:0] c_compSTR_B1_start_x_i_stall_succ;
    wire c_compSTR_B1_start_x_i_stall_succ_bitsignaltemp;
    wire [0:0] c_compSTR_B1_start_x_i_valid_loop;
    wire c_compSTR_B1_start_x_i_valid_loop_bitsignaltemp;
    wire [0:0] c_compSTR_B1_start_x_i_valid_pred;
    wire c_compSTR_B1_start_x_i_valid_pred_bitsignaltemp;
    wire [0:0] c_compSTR_B1_start_x_i_valid_succ;
    wire c_compSTR_B1_start_x_i_valid_succ_bitsignaltemp;
    wire [0:0] c_compSTR_B3_x_i_capture;
    wire c_compSTR_B3_x_i_capture_bitsignaltemp;
    wire [0:0] c_compSTR_B3_x_i_clear;
    wire c_compSTR_B3_x_i_clear_bitsignaltemp;
    wire [0:0] c_compSTR_B3_x_i_enable;
    wire c_compSTR_B3_x_i_enable_bitsignaltemp;
    wire [0:0] c_compSTR_B3_x_i_shift;
    wire c_compSTR_B3_x_i_shift_bitsignaltemp;
    wire [0:0] c_compSTR_B3_x_i_stall_pred;
    wire c_compSTR_B3_x_i_stall_pred_bitsignaltemp;
    wire [0:0] c_compSTR_B3_x_i_stall_succ;
    wire c_compSTR_B3_x_i_stall_succ_bitsignaltemp;
    wire [0:0] c_compSTR_B3_x_i_valid_loop;
    wire c_compSTR_B3_x_i_valid_loop_bitsignaltemp;
    wire [0:0] c_compSTR_B3_x_i_valid_pred;
    wire c_compSTR_B3_x_i_valid_pred_bitsignaltemp;
    wire [0:0] c_compSTR_B3_x_i_valid_succ;
    wire c_compSTR_B3_x_i_valid_succ_bitsignaltemp;
    wire [0:0] c_compSTR_B5_x_i_capture;
    wire c_compSTR_B5_x_i_capture_bitsignaltemp;
    wire [0:0] c_compSTR_B5_x_i_clear;
    wire c_compSTR_B5_x_i_clear_bitsignaltemp;
    wire [0:0] c_compSTR_B5_x_i_enable;
    wire c_compSTR_B5_x_i_enable_bitsignaltemp;
    wire [0:0] c_compSTR_B5_x_i_shift;
    wire c_compSTR_B5_x_i_shift_bitsignaltemp;
    wire [0:0] c_compSTR_B5_x_i_stall_pred;
    wire c_compSTR_B5_x_i_stall_pred_bitsignaltemp;
    wire [0:0] c_compSTR_B5_x_i_stall_succ;
    wire c_compSTR_B5_x_i_stall_succ_bitsignaltemp;
    wire [0:0] c_compSTR_B5_x_i_valid_loop;
    wire c_compSTR_B5_x_i_valid_loop_bitsignaltemp;
    wire [0:0] c_compSTR_B5_x_i_valid_pred;
    wire c_compSTR_B5_x_i_valid_pred_bitsignaltemp;
    wire [0:0] c_compSTR_B5_x_i_valid_succ;
    wire c_compSTR_B5_x_i_valid_succ_bitsignaltemp;
    wire [0:0] c_compSTR_B7_x_i_capture;
    wire c_compSTR_B7_x_i_capture_bitsignaltemp;
    wire [0:0] c_compSTR_B7_x_i_clear;
    wire c_compSTR_B7_x_i_clear_bitsignaltemp;
    wire [0:0] c_compSTR_B7_x_i_enable;
    wire c_compSTR_B7_x_i_enable_bitsignaltemp;
    wire [0:0] c_compSTR_B7_x_i_shift;
    wire c_compSTR_B7_x_i_shift_bitsignaltemp;
    wire [0:0] c_compSTR_B7_x_i_stall_pred;
    wire c_compSTR_B7_x_i_stall_pred_bitsignaltemp;
    wire [0:0] c_compSTR_B7_x_i_stall_succ;
    wire c_compSTR_B7_x_i_stall_succ_bitsignaltemp;
    wire [0:0] c_compSTR_B7_x_i_valid_loop;
    wire c_compSTR_B7_x_i_valid_loop_bitsignaltemp;
    wire [0:0] c_compSTR_B7_x_i_valid_pred;
    wire c_compSTR_B7_x_i_valid_pred_bitsignaltemp;
    wire [0:0] c_compSTR_B7_x_i_valid_succ;
    wire c_compSTR_B7_x_i_valid_succ_bitsignaltemp;
    reg [0:0] rst_sync_rst_sclrn;


    // bb_c_compSTR_B3(BLACKBOX,5)
    c_compSTR_bb_B3 thebb_c_compSTR_B3 (
        .in_memdep_phi9_pop10680_0(bb_c_compSTR_B1_start_out_memdep_phi_pop9),
        .in_memdep_phi_pop9677_0(bb_c_compSTR_B1_start_out_memdep_phi_pop9),
        .in_stall_in_0(bb_c_compSTR_B5_out_stall_out_0),
        .in_valid_in_0(bb_c_compSTR_B1_start_out_valid_out_0),
        .out_c0_exe1697(bb_c_compSTR_B3_out_c0_exe1697),
        .out_c0_exe2698(bb_c_compSTR_B3_out_c0_exe2698),
        .out_c0_exe4(bb_c_compSTR_B3_out_c0_exe4),
        .out_c0_exe5(bb_c_compSTR_B3_out_c0_exe5),
        .out_c0_exe6(bb_c_compSTR_B3_out_c0_exe6),
        .out_c0_exe7(bb_c_compSTR_B3_out_c0_exe7),
        .out_c0_exe8(bb_c_compSTR_B3_out_c0_exe8),
        .out_stall_out_0(bb_c_compSTR_B3_out_stall_out_0),
        .out_valid_in_0(bb_c_compSTR_B3_out_valid_in_0),
        .out_valid_out_0(bb_c_compSTR_B3_out_valid_out_0),
        .clock(clock),
        .resetn(resetn)
    );

    // bb_c_compSTR_B5(BLACKBOX,7)
    c_compSTR_bb_B5 thebb_c_compSTR_B5 (
        .in_cmp21684_0(bb_c_compSTR_B3_out_c0_exe2698),
        .in_flush(in_start),
        .in_i_0288_pop12683_0(bb_c_compSTR_B3_out_c0_exe1697),
        .in_iord_bl_WStream_i_fifodata(in_iord_bl_WStream_i_fifodata),
        .in_iord_bl_WStream_i_fifovalid(in_iord_bl_WStream_i_fifovalid),
        .in_iord_bl_yStream_i_fifodata(in_iord_bl_yStream_i_fifodata),
        .in_iord_bl_yStream_i_fifovalid(in_iord_bl_yStream_i_fifovalid),
        .in_memdep_17_c_compSTR_avm_readdata(in_memdep_17_c_compSTR_avm_readdata),
        .in_memdep_17_c_compSTR_avm_readdatavalid(in_memdep_17_c_compSTR_avm_readdatavalid),
        .in_memdep_17_c_compSTR_avm_waitrequest(in_memdep_17_c_compSTR_avm_waitrequest),
        .in_memdep_17_c_compSTR_avm_writeack(in_memdep_17_c_compSTR_avm_writeack),
        .in_memdep_5_c_compSTR_avm_readdata(in_memdep_5_c_compSTR_avm_readdata),
        .in_memdep_5_c_compSTR_avm_readdatavalid(in_memdep_5_c_compSTR_avm_readdatavalid),
        .in_memdep_5_c_compSTR_avm_waitrequest(in_memdep_5_c_compSTR_avm_waitrequest),
        .in_memdep_5_c_compSTR_avm_writeack(in_memdep_5_c_compSTR_avm_writeack),
        .in_memdep_phi9_pop1032_pop14687_0(bb_c_compSTR_B3_out_c0_exe6),
        .in_memdep_phi9_pop10682_0(bb_c_compSTR_B3_out_c0_exe8),
        .in_memdep_phi_pop930_pop13686_0(bb_c_compSTR_B3_out_c0_exe5),
        .in_memdep_phi_pop9679_0(bb_c_compSTR_B3_out_c0_exe7),
        .in_notcmp21685_0(bb_c_compSTR_B3_out_c0_exe4),
        .in_stall_in_0(bb_c_compSTR_B4_out_stall_out_0),
        .in_valid_in_0(bb_c_compSTR_B3_out_valid_out_0),
        .out_c0_exe6720(bb_c_compSTR_B5_out_c0_exe6720),
        .out_iord_bl_WStream_o_fifoalmost_full(bb_c_compSTR_B5_out_iord_bl_WStream_o_fifoalmost_full),
        .out_iord_bl_WStream_o_fifoready(bb_c_compSTR_B5_out_iord_bl_WStream_o_fifoready),
        .out_iord_bl_yStream_o_fifoalmost_full(bb_c_compSTR_B5_out_iord_bl_yStream_o_fifoalmost_full),
        .out_iord_bl_yStream_o_fifoready(bb_c_compSTR_B5_out_iord_bl_yStream_o_fifoready),
        .out_memdep_17_c_compSTR_avm_address(bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_address),
        .out_memdep_17_c_compSTR_avm_burstcount(bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_burstcount),
        .out_memdep_17_c_compSTR_avm_byteenable(bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_byteenable),
        .out_memdep_17_c_compSTR_avm_enable(bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_enable),
        .out_memdep_17_c_compSTR_avm_read(bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_read),
        .out_memdep_17_c_compSTR_avm_write(bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_write),
        .out_memdep_17_c_compSTR_avm_writedata(bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_writedata),
        .out_memdep_5_c_compSTR_avm_address(bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_address),
        .out_memdep_5_c_compSTR_avm_burstcount(bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_burstcount),
        .out_memdep_5_c_compSTR_avm_byteenable(bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_byteenable),
        .out_memdep_5_c_compSTR_avm_enable(bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_enable),
        .out_memdep_5_c_compSTR_avm_read(bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_read),
        .out_memdep_5_c_compSTR_avm_write(bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_write),
        .out_memdep_5_c_compSTR_avm_writedata(bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_writedata),
        .out_profile_loop_o_valid(bb_c_compSTR_B5_out_profile_loop_o_valid),
        .out_stall_in_0(bb_c_compSTR_B5_out_stall_in_0),
        .out_stall_out_0(bb_c_compSTR_B5_out_stall_out_0),
        .out_valid_in_0(bb_c_compSTR_B5_out_valid_in_0),
        .out_valid_out_0(bb_c_compSTR_B5_out_valid_out_0),
        .clock(clock),
        .resetn(resetn)
    );

    // bb_c_compSTR_B4(BLACKBOX,6)
    c_compSTR_bb_B4 thebb_c_compSTR_B4 (
        .in_c0_exe67201_0(bb_c_compSTR_B5_out_c0_exe6720),
        .in_stall_in_0(bb_c_compSTR_B2_out_stall_out_0),
        .in_valid_in_0(bb_c_compSTR_B5_out_valid_out_0),
        .out_stall_in_0(bb_c_compSTR_B4_out_stall_in_0),
        .out_stall_out_0(bb_c_compSTR_B4_out_stall_out_0),
        .out_valid_in_0(bb_c_compSTR_B4_out_valid_in_0),
        .out_valid_out_0(bb_c_compSTR_B4_out_valid_out_0),
        .clock(clock),
        .resetn(resetn)
    );

    // bb_c_compSTR_B2(BLACKBOX,4)
    c_compSTR_bb_B2 thebb_c_compSTR_B2 (
        .in_stall_in_0(bb_c_compSTR_B7_out_stall_out_0),
        .in_valid_in_0(bb_c_compSTR_B4_out_valid_out_0),
        .out_stall_out_0(bb_c_compSTR_B2_out_stall_out_0),
        .out_valid_out_0(bb_c_compSTR_B2_out_valid_out_0),
        .clock(clock),
        .resetn(resetn)
    );

    // bb_c_compSTR_B7(BLACKBOX,9)
    c_compSTR_bb_B7 thebb_c_compSTR_B7 (
        .in_flush(in_start),
        .in_iowr_bl_resStream_i_fifoready(in_iowr_bl_resStream_i_fifoready),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdata(in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdata),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdatavalid(in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdatavalid),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_waitrequest(in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_waitrequest),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writeack(in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writeack),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdata(in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdata),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdatavalid(in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdatavalid),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_waitrequest(in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_waitrequest),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writeack(in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writeack),
        .in_stall_in_0(bb_c_compSTR_B6_out_stall_out_0),
        .in_valid_in_0(bb_c_compSTR_B2_out_valid_out_0),
        .out_c0_exe1732(bb_c_compSTR_B7_out_c0_exe1732),
        .out_iowr_bl_resStream_o_fifodata(bb_c_compSTR_B7_out_iowr_bl_resStream_o_fifodata),
        .out_iowr_bl_resStream_o_fifovalid(bb_c_compSTR_B7_out_iowr_bl_resStream_o_fifovalid),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata(bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata),
        .out_profile_loop_o_valid(bb_c_compSTR_B7_out_profile_loop_o_valid),
        .out_stall_in_0(bb_c_compSTR_B7_out_stall_in_0),
        .out_stall_out_0(bb_c_compSTR_B7_out_stall_out_0),
        .out_valid_in_0(bb_c_compSTR_B7_out_valid_in_0),
        .out_valid_out_0(bb_c_compSTR_B7_out_valid_out_0),
        .clock(clock),
        .resetn(resetn)
    );

    // bb_c_compSTR_B6(BLACKBOX,8)
    c_compSTR_bb_B6 thebb_c_compSTR_B6 (
        .in_c0_exe17322_0(bb_c_compSTR_B7_out_c0_exe1732),
        .in_feedback_stall_in_10(bb_c_compSTR_B1_start_out_feedback_stall_out_10),
        .in_iowr_bl_return_c_compSTR_i_fifoready(in_iowr_bl_return_c_compSTR_i_fifoready),
        .in_stall_in_0(in_stall_in),
        .in_valid_in_0(bb_c_compSTR_B7_out_valid_out_0),
        .out_feedback_almost_empty_out_10(bb_c_compSTR_B6_out_feedback_almost_empty_out_10),
        .out_feedback_data_out_10(bb_c_compSTR_B6_out_feedback_data_out_10),
        .out_feedback_empty_out_10(bb_c_compSTR_B6_out_feedback_empty_out_10),
        .out_iowr_bl_return_c_compSTR_o_fifodata(bb_c_compSTR_B6_out_iowr_bl_return_c_compSTR_o_fifodata),
        .out_iowr_bl_return_c_compSTR_o_fifovalid(bb_c_compSTR_B6_out_iowr_bl_return_c_compSTR_o_fifovalid),
        .out_stall_in_0(bb_c_compSTR_B6_out_stall_in_0),
        .out_stall_out_0(bb_c_compSTR_B6_out_stall_out_0),
        .out_valid_in_0(bb_c_compSTR_B6_out_valid_in_0),
        .out_valid_out_0(bb_c_compSTR_B6_out_valid_out_0),
        .clock(clock),
        .resetn(resetn)
    );

    // bb_c_compSTR_B0_runOnce(BLACKBOX,2)
    c_compSTR_bb_B0_runOnce thebb_c_compSTR_B0_runOnce (
        .in_stall_in_0(bb_c_compSTR_B1_start_out_stall_out_0),
        .in_valid_in_0(in_valid_in),
        .out_stall_out_0(bb_c_compSTR_B0_runOnce_out_stall_out_0),
        .out_valid_out_0(bb_c_compSTR_B0_runOnce_out_valid_out_0),
        .clock(clock),
        .resetn(resetn)
    );

    // bb_c_compSTR_B1_start(BLACKBOX,3)
    c_compSTR_bb_B1_start thebb_c_compSTR_B1_start (
        .in_feedback_almost_empty_in_10(bb_c_compSTR_B6_out_feedback_almost_empty_out_10),
        .in_feedback_data_in_10(bb_c_compSTR_B6_out_feedback_data_out_10),
        .in_feedback_empty_in_10(bb_c_compSTR_B6_out_feedback_empty_out_10),
        .in_iord_bl_call_c_compSTR_i_fifodata(in_iord_bl_call_c_compSTR_i_fifodata),
        .in_iord_bl_call_c_compSTR_i_fifovalid(in_iord_bl_call_c_compSTR_i_fifovalid),
        .in_stall_in_0(bb_c_compSTR_B3_out_stall_out_0),
        .in_valid_in_0(bb_c_compSTR_B0_runOnce_out_valid_out_0),
        .out_feedback_stall_out_10(bb_c_compSTR_B1_start_out_feedback_stall_out_10),
        .out_iord_bl_call_c_compSTR_o_fifoalmost_full(bb_c_compSTR_B1_start_out_iord_bl_call_c_compSTR_o_fifoalmost_full),
        .out_iord_bl_call_c_compSTR_o_fifoready(bb_c_compSTR_B1_start_out_iord_bl_call_c_compSTR_o_fifoready),
        .out_memdep_phi_pop9(bb_c_compSTR_B1_start_out_memdep_phi_pop9),
        .out_stall_out_0(bb_c_compSTR_B1_start_out_stall_out_0),
        .out_valid_in_0(bb_c_compSTR_B1_start_out_valid_in_0),
        .out_valid_out_0(bb_c_compSTR_B1_start_out_valid_out_0),
        .clock(clock),
        .resetn(resetn)
    );

    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // c_compSTR_B1_start_x(EXTIFACE,10)
    assign c_compSTR_B1_start_x_i_capture = GND_q;
    assign c_compSTR_B1_start_x_i_clear = GND_q;
    assign c_compSTR_B1_start_x_i_enable = VCC_q;
    assign c_compSTR_B1_start_x_i_shift = GND_q;
    assign c_compSTR_B1_start_x_i_stall_pred = bb_c_compSTR_B1_start_out_stall_out_0;
    assign c_compSTR_B1_start_x_i_stall_succ = bb_c_compSTR_B6_out_stall_in_0;
    assign c_compSTR_B1_start_x_i_valid_loop = bb_c_compSTR_B6_out_valid_in_0;
    assign c_compSTR_B1_start_x_i_valid_pred = bb_c_compSTR_B1_start_out_valid_in_0;
    assign c_compSTR_B1_start_x_i_valid_succ = bb_c_compSTR_B6_out_valid_out_0;
    assign c_compSTR_B1_start_x_i_capture_bitsignaltemp = c_compSTR_B1_start_x_i_capture[0];
    assign c_compSTR_B1_start_x_i_clear_bitsignaltemp = c_compSTR_B1_start_x_i_clear[0];
    assign c_compSTR_B1_start_x_i_enable_bitsignaltemp = c_compSTR_B1_start_x_i_enable[0];
    assign c_compSTR_B1_start_x_i_shift_bitsignaltemp = c_compSTR_B1_start_x_i_shift[0];
    assign c_compSTR_B1_start_x_i_stall_pred_bitsignaltemp = c_compSTR_B1_start_x_i_stall_pred[0];
    assign c_compSTR_B1_start_x_i_stall_succ_bitsignaltemp = c_compSTR_B1_start_x_i_stall_succ[0];
    assign c_compSTR_B1_start_x_i_valid_loop_bitsignaltemp = c_compSTR_B1_start_x_i_valid_loop[0];
    assign c_compSTR_B1_start_x_i_valid_pred_bitsignaltemp = c_compSTR_B1_start_x_i_valid_pred[0];
    assign c_compSTR_B1_start_x_i_valid_succ_bitsignaltemp = c_compSTR_B1_start_x_i_valid_succ[0];
    hld_loop_profiler #(
        .LOOP_NAME("c_compSTR.B1.start")
    ) thec_compSTR_B1_start_x (
        .i_capture(c_compSTR_B1_start_x_i_capture_bitsignaltemp),
        .i_clear(c_compSTR_B1_start_x_i_clear_bitsignaltemp),
        .i_enable(c_compSTR_B1_start_x_i_enable_bitsignaltemp),
        .i_shift(c_compSTR_B1_start_x_i_shift_bitsignaltemp),
        .i_stall_pred(c_compSTR_B1_start_x_i_stall_pred_bitsignaltemp),
        .i_stall_succ(c_compSTR_B1_start_x_i_stall_succ_bitsignaltemp),
        .i_valid_loop(c_compSTR_B1_start_x_i_valid_loop_bitsignaltemp),
        .i_valid_pred(c_compSTR_B1_start_x_i_valid_pred_bitsignaltemp),
        .i_valid_succ(c_compSTR_B1_start_x_i_valid_succ_bitsignaltemp),
        .clock(clock),
        .resetn(rst_sync_rst_sclrn[0])
    );

    // c_compSTR_B3_x(EXTIFACE,11)
    assign c_compSTR_B3_x_i_capture = GND_q;
    assign c_compSTR_B3_x_i_clear = GND_q;
    assign c_compSTR_B3_x_i_enable = VCC_q;
    assign c_compSTR_B3_x_i_shift = GND_q;
    assign c_compSTR_B3_x_i_stall_pred = bb_c_compSTR_B3_out_stall_out_0;
    assign c_compSTR_B3_x_i_stall_succ = bb_c_compSTR_B4_out_stall_in_0;
    assign c_compSTR_B3_x_i_valid_loop = bb_c_compSTR_B4_out_valid_in_0;
    assign c_compSTR_B3_x_i_valid_pred = bb_c_compSTR_B3_out_valid_in_0;
    assign c_compSTR_B3_x_i_valid_succ = bb_c_compSTR_B4_out_valid_out_0;
    assign c_compSTR_B3_x_i_capture_bitsignaltemp = c_compSTR_B3_x_i_capture[0];
    assign c_compSTR_B3_x_i_clear_bitsignaltemp = c_compSTR_B3_x_i_clear[0];
    assign c_compSTR_B3_x_i_enable_bitsignaltemp = c_compSTR_B3_x_i_enable[0];
    assign c_compSTR_B3_x_i_shift_bitsignaltemp = c_compSTR_B3_x_i_shift[0];
    assign c_compSTR_B3_x_i_stall_pred_bitsignaltemp = c_compSTR_B3_x_i_stall_pred[0];
    assign c_compSTR_B3_x_i_stall_succ_bitsignaltemp = c_compSTR_B3_x_i_stall_succ[0];
    assign c_compSTR_B3_x_i_valid_loop_bitsignaltemp = c_compSTR_B3_x_i_valid_loop[0];
    assign c_compSTR_B3_x_i_valid_pred_bitsignaltemp = c_compSTR_B3_x_i_valid_pred[0];
    assign c_compSTR_B3_x_i_valid_succ_bitsignaltemp = c_compSTR_B3_x_i_valid_succ[0];
    hld_loop_profiler #(
        .LOOP_NAME("c_compSTR.B3")
    ) thec_compSTR_B3_x (
        .i_capture(c_compSTR_B3_x_i_capture_bitsignaltemp),
        .i_clear(c_compSTR_B3_x_i_clear_bitsignaltemp),
        .i_enable(c_compSTR_B3_x_i_enable_bitsignaltemp),
        .i_shift(c_compSTR_B3_x_i_shift_bitsignaltemp),
        .i_stall_pred(c_compSTR_B3_x_i_stall_pred_bitsignaltemp),
        .i_stall_succ(c_compSTR_B3_x_i_stall_succ_bitsignaltemp),
        .i_valid_loop(c_compSTR_B3_x_i_valid_loop_bitsignaltemp),
        .i_valid_pred(c_compSTR_B3_x_i_valid_pred_bitsignaltemp),
        .i_valid_succ(c_compSTR_B3_x_i_valid_succ_bitsignaltemp),
        .clock(clock),
        .resetn(rst_sync_rst_sclrn[0])
    );

    // c_compSTR_B5_x(EXTIFACE,12)
    assign c_compSTR_B5_x_i_capture = GND_q;
    assign c_compSTR_B5_x_i_clear = GND_q;
    assign c_compSTR_B5_x_i_enable = VCC_q;
    assign c_compSTR_B5_x_i_shift = GND_q;
    assign c_compSTR_B5_x_i_stall_pred = bb_c_compSTR_B5_out_stall_out_0;
    assign c_compSTR_B5_x_i_stall_succ = bb_c_compSTR_B5_out_stall_in_0;
    assign c_compSTR_B5_x_i_valid_loop = bb_c_compSTR_B5_out_profile_loop_o_valid;
    assign c_compSTR_B5_x_i_valid_pred = bb_c_compSTR_B5_out_valid_in_0;
    assign c_compSTR_B5_x_i_valid_succ = bb_c_compSTR_B5_out_valid_out_0;
    assign c_compSTR_B5_x_i_capture_bitsignaltemp = c_compSTR_B5_x_i_capture[0];
    assign c_compSTR_B5_x_i_clear_bitsignaltemp = c_compSTR_B5_x_i_clear[0];
    assign c_compSTR_B5_x_i_enable_bitsignaltemp = c_compSTR_B5_x_i_enable[0];
    assign c_compSTR_B5_x_i_shift_bitsignaltemp = c_compSTR_B5_x_i_shift[0];
    assign c_compSTR_B5_x_i_stall_pred_bitsignaltemp = c_compSTR_B5_x_i_stall_pred[0];
    assign c_compSTR_B5_x_i_stall_succ_bitsignaltemp = c_compSTR_B5_x_i_stall_succ[0];
    assign c_compSTR_B5_x_i_valid_loop_bitsignaltemp = c_compSTR_B5_x_i_valid_loop[0];
    assign c_compSTR_B5_x_i_valid_pred_bitsignaltemp = c_compSTR_B5_x_i_valid_pred[0];
    assign c_compSTR_B5_x_i_valid_succ_bitsignaltemp = c_compSTR_B5_x_i_valid_succ[0];
    hld_loop_profiler #(
        .LOOP_NAME("c_compSTR.B5")
    ) thec_compSTR_B5_x (
        .i_capture(c_compSTR_B5_x_i_capture_bitsignaltemp),
        .i_clear(c_compSTR_B5_x_i_clear_bitsignaltemp),
        .i_enable(c_compSTR_B5_x_i_enable_bitsignaltemp),
        .i_shift(c_compSTR_B5_x_i_shift_bitsignaltemp),
        .i_stall_pred(c_compSTR_B5_x_i_stall_pred_bitsignaltemp),
        .i_stall_succ(c_compSTR_B5_x_i_stall_succ_bitsignaltemp),
        .i_valid_loop(c_compSTR_B5_x_i_valid_loop_bitsignaltemp),
        .i_valid_pred(c_compSTR_B5_x_i_valid_pred_bitsignaltemp),
        .i_valid_succ(c_compSTR_B5_x_i_valid_succ_bitsignaltemp),
        .clock(clock),
        .resetn(rst_sync_rst_sclrn[0])
    );

    // c_compSTR_B7_x(EXTIFACE,13)
    assign c_compSTR_B7_x_i_capture = GND_q;
    assign c_compSTR_B7_x_i_clear = GND_q;
    assign c_compSTR_B7_x_i_enable = VCC_q;
    assign c_compSTR_B7_x_i_shift = GND_q;
    assign c_compSTR_B7_x_i_stall_pred = bb_c_compSTR_B7_out_stall_out_0;
    assign c_compSTR_B7_x_i_stall_succ = bb_c_compSTR_B7_out_stall_in_0;
    assign c_compSTR_B7_x_i_valid_loop = bb_c_compSTR_B7_out_profile_loop_o_valid;
    assign c_compSTR_B7_x_i_valid_pred = bb_c_compSTR_B7_out_valid_in_0;
    assign c_compSTR_B7_x_i_valid_succ = bb_c_compSTR_B7_out_valid_out_0;
    assign c_compSTR_B7_x_i_capture_bitsignaltemp = c_compSTR_B7_x_i_capture[0];
    assign c_compSTR_B7_x_i_clear_bitsignaltemp = c_compSTR_B7_x_i_clear[0];
    assign c_compSTR_B7_x_i_enable_bitsignaltemp = c_compSTR_B7_x_i_enable[0];
    assign c_compSTR_B7_x_i_shift_bitsignaltemp = c_compSTR_B7_x_i_shift[0];
    assign c_compSTR_B7_x_i_stall_pred_bitsignaltemp = c_compSTR_B7_x_i_stall_pred[0];
    assign c_compSTR_B7_x_i_stall_succ_bitsignaltemp = c_compSTR_B7_x_i_stall_succ[0];
    assign c_compSTR_B7_x_i_valid_loop_bitsignaltemp = c_compSTR_B7_x_i_valid_loop[0];
    assign c_compSTR_B7_x_i_valid_pred_bitsignaltemp = c_compSTR_B7_x_i_valid_pred[0];
    assign c_compSTR_B7_x_i_valid_succ_bitsignaltemp = c_compSTR_B7_x_i_valid_succ[0];
    hld_loop_profiler #(
        .LOOP_NAME("c_compSTR.B7")
    ) thec_compSTR_B7_x (
        .i_capture(c_compSTR_B7_x_i_capture_bitsignaltemp),
        .i_clear(c_compSTR_B7_x_i_clear_bitsignaltemp),
        .i_enable(c_compSTR_B7_x_i_enable_bitsignaltemp),
        .i_shift(c_compSTR_B7_x_i_shift_bitsignaltemp),
        .i_stall_pred(c_compSTR_B7_x_i_stall_pred_bitsignaltemp),
        .i_stall_succ(c_compSTR_B7_x_i_stall_succ_bitsignaltemp),
        .i_valid_loop(c_compSTR_B7_x_i_valid_loop_bitsignaltemp),
        .i_valid_pred(c_compSTR_B7_x_i_valid_pred_bitsignaltemp),
        .i_valid_succ(c_compSTR_B7_x_i_valid_succ_bitsignaltemp),
        .clock(clock),
        .resetn(rst_sync_rst_sclrn[0])
    );

    // out_iord_bl_WStream_o_fifoalmost_full(GPOUT,54)
    assign out_iord_bl_WStream_o_fifoalmost_full = bb_c_compSTR_B5_out_iord_bl_WStream_o_fifoalmost_full;

    // out_iord_bl_WStream_o_fifoready(GPOUT,55)
    assign out_iord_bl_WStream_o_fifoready = bb_c_compSTR_B5_out_iord_bl_WStream_o_fifoready;

    // out_iord_bl_call_c_compSTR_o_fifoalmost_full(GPOUT,56)
    assign out_iord_bl_call_c_compSTR_o_fifoalmost_full = bb_c_compSTR_B1_start_out_iord_bl_call_c_compSTR_o_fifoalmost_full;

    // out_iord_bl_call_c_compSTR_o_fifoready(GPOUT,57)
    assign out_iord_bl_call_c_compSTR_o_fifoready = bb_c_compSTR_B1_start_out_iord_bl_call_c_compSTR_o_fifoready;

    // out_iord_bl_yStream_o_fifoalmost_full(GPOUT,58)
    assign out_iord_bl_yStream_o_fifoalmost_full = bb_c_compSTR_B5_out_iord_bl_yStream_o_fifoalmost_full;

    // out_iord_bl_yStream_o_fifoready(GPOUT,59)
    assign out_iord_bl_yStream_o_fifoready = bb_c_compSTR_B5_out_iord_bl_yStream_o_fifoready;

    // out_iowr_bl_resStream_o_fifodata(GPOUT,60)
    assign out_iowr_bl_resStream_o_fifodata = bb_c_compSTR_B7_out_iowr_bl_resStream_o_fifodata;

    // out_iowr_bl_resStream_o_fifovalid(GPOUT,61)
    assign out_iowr_bl_resStream_o_fifovalid = bb_c_compSTR_B7_out_iowr_bl_resStream_o_fifovalid;

    // out_iowr_bl_return_c_compSTR_o_fifodata(GPOUT,62)
    assign out_iowr_bl_return_c_compSTR_o_fifodata = bb_c_compSTR_B6_out_iowr_bl_return_c_compSTR_o_fifodata;

    // out_iowr_bl_return_c_compSTR_o_fifovalid(GPOUT,63)
    assign out_iowr_bl_return_c_compSTR_o_fifovalid = bb_c_compSTR_B6_out_iowr_bl_return_c_compSTR_o_fifovalid;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address(GPOUT,64)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount(GPOUT,65)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable(GPOUT,66)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable(GPOUT,67)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read(GPOUT,68)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write(GPOUT,69)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata(GPOUT,70)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address(GPOUT,71)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount(GPOUT,72)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable(GPOUT,73)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable(GPOUT,74)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read(GPOUT,75)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write(GPOUT,76)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write;

    // out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata(GPOUT,77)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata = bb_c_compSTR_B7_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata;

    // out_memdep_17_c_compSTR_avm_address(GPOUT,78)
    assign out_memdep_17_c_compSTR_avm_address = bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_address;

    // out_memdep_17_c_compSTR_avm_burstcount(GPOUT,79)
    assign out_memdep_17_c_compSTR_avm_burstcount = bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_burstcount;

    // out_memdep_17_c_compSTR_avm_byteenable(GPOUT,80)
    assign out_memdep_17_c_compSTR_avm_byteenable = bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_byteenable;

    // out_memdep_17_c_compSTR_avm_enable(GPOUT,81)
    assign out_memdep_17_c_compSTR_avm_enable = bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_enable;

    // out_memdep_17_c_compSTR_avm_read(GPOUT,82)
    assign out_memdep_17_c_compSTR_avm_read = bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_read;

    // out_memdep_17_c_compSTR_avm_write(GPOUT,83)
    assign out_memdep_17_c_compSTR_avm_write = bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_write;

    // out_memdep_17_c_compSTR_avm_writedata(GPOUT,84)
    assign out_memdep_17_c_compSTR_avm_writedata = bb_c_compSTR_B5_out_memdep_17_c_compSTR_avm_writedata;

    // out_memdep_5_c_compSTR_avm_address(GPOUT,85)
    assign out_memdep_5_c_compSTR_avm_address = bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_address;

    // out_memdep_5_c_compSTR_avm_burstcount(GPOUT,86)
    assign out_memdep_5_c_compSTR_avm_burstcount = bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_burstcount;

    // out_memdep_5_c_compSTR_avm_byteenable(GPOUT,87)
    assign out_memdep_5_c_compSTR_avm_byteenable = bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_byteenable;

    // out_memdep_5_c_compSTR_avm_enable(GPOUT,88)
    assign out_memdep_5_c_compSTR_avm_enable = bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_enable;

    // out_memdep_5_c_compSTR_avm_read(GPOUT,89)
    assign out_memdep_5_c_compSTR_avm_read = bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_read;

    // out_memdep_5_c_compSTR_avm_write(GPOUT,90)
    assign out_memdep_5_c_compSTR_avm_write = bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_write;

    // out_memdep_5_c_compSTR_avm_writedata(GPOUT,91)
    assign out_memdep_5_c_compSTR_avm_writedata = bb_c_compSTR_B5_out_memdep_5_c_compSTR_avm_writedata;

    // out_stall_out(GPOUT,92)
    assign out_stall_out = bb_c_compSTR_B0_runOnce_out_stall_out_0;

    // out_valid_out(GPOUT,93)
    assign out_valid_out = bb_c_compSTR_B6_out_valid_out_0;

    // rst_sync(RESETSYNC,94)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
