// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from c_compSTR_B5_merge
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_B5_merge (
    input wire [0:0] in_cmp21684_0,
    input wire [31:0] in_i_0288_pop12683_0,
    input wire [0:0] in_memdep_phi9_pop1032_pop14687_0,
    input wire [0:0] in_memdep_phi9_pop10682_0,
    input wire [0:0] in_memdep_phi_pop930_pop13686_0,
    input wire [0:0] in_memdep_phi_pop9679_0,
    input wire [0:0] in_notcmp21685_0,
    input wire [0:0] in_stall_in,
    input wire [0:0] in_valid_in_0,
    output wire [0:0] out_almost_empty_out,
    output wire [0:0] out_cmp21684,
    output wire [0:0] out_empty_out,
    output wire [31:0] out_i_0288_pop12683,
    output wire [0:0] out_memdep_phi9_pop1032_pop14687,
    output wire [0:0] out_memdep_phi9_pop10682,
    output wire [0:0] out_memdep_phi_pop930_pop13686,
    output wire [0:0] out_memdep_phi_pop9679,
    output wire [0:0] out_notcmp21685,
    output wire [0:0] out_stall_out_0,
    output wire [0:0] out_valid_out,
    input wire clock,
    input wire resetn
    );

    wire [0:0] adapt_scalar_trunc12_in;
    wire [0:0] adapt_scalar_trunc12_q;
    wire [0:0] adapt_scalar_trunc15_in;
    wire [0:0] adapt_scalar_trunc15_q;
    wire [0:0] adapt_scalar_trunc18_in;
    wire [0:0] adapt_scalar_trunc18_q;
    wire [0:0] adapt_scalar_trunc2_in;
    wire [0:0] adapt_scalar_trunc2_q;
    wire [0:0] adapt_scalar_trunc5_in;
    wire [0:0] adapt_scalar_trunc5_q;
    wire [0:0] adapt_scalar_trunc9_in;
    wire [0:0] adapt_scalar_trunc9_q;
    wire [79:0] c_compSTR_B5_merge_data_pack_0_q;
    wire [7:0] c_compSTR_B5_merge_data_unpack_0_b;
    wire [7:0] c_compSTR_B5_merge_data_unpack_1_b;
    wire [31:0] c_compSTR_B5_merge_data_unpack_2_b;
    wire [7:0] c_compSTR_B5_merge_data_unpack_3_b;
    wire [7:0] c_compSTR_B5_merge_data_unpack_4_b;
    wire [7:0] c_compSTR_B5_merge_data_unpack_5_b;
    wire [7:0] c_compSTR_B5_merge_data_unpack_6_b;
    wire [0:0] c_compSTR_B5_merge_storage_out_o_almost_empty;
    wire [79:0] c_compSTR_B5_merge_storage_out_o_data;
    wire [0:0] c_compSTR_B5_merge_storage_out_o_empty;
    wire [0:0] c_compSTR_B5_merge_storage_out_o_stall;
    wire [0:0] c_compSTR_B5_merge_storage_out_o_valid;
    wire [1:0] c_i2_019_q;
    wire [6:0] c_i7_01_q;
    wire [7:0] element_extension0_q;
    wire [7:0] element_extension10_q;
    wire [7:0] element_extension13_q;
    wire [7:0] element_extension16_q;
    wire [7:0] element_extension3_q;
    wire [7:0] element_extension7_q;
    reg [0:0] rst_sync_rst_sclrn;


    // c_i7_01(CONSTANT,18)
    assign c_i7_01_q = $unsigned(7'b0000000);

    // element_extension16(BITJOIN,27)
    assign element_extension16_q = {c_i7_01_q, in_memdep_phi9_pop1032_pop14687_0};

    // element_extension13(BITJOIN,26)
    assign element_extension13_q = {c_i7_01_q, in_memdep_phi_pop930_pop13686_0};

    // element_extension10(BITJOIN,25)
    assign element_extension10_q = {c_i7_01_q, in_notcmp21685_0};

    // element_extension7(BITJOIN,29)
    assign element_extension7_q = {c_i7_01_q, in_cmp21684_0};

    // element_extension3(BITJOIN,28)
    assign element_extension3_q = {c_i7_01_q, in_memdep_phi9_pop10682_0};

    // element_extension0(BITJOIN,24)
    assign element_extension0_q = {c_i7_01_q, in_memdep_phi_pop9679_0};

    // c_compSTR_B5_merge_data_pack_0(BITJOIN,8)
    assign c_compSTR_B5_merge_data_pack_0_q = {element_extension16_q, element_extension13_q, element_extension10_q, element_extension7_q, in_i_0288_pop12683_0, element_extension3_q, element_extension0_q};

    // c_i2_019(CONSTANT,17)
    assign c_i2_019_q = $unsigned(2'b00);

    // c_compSTR_B5_merge_storage(BLACKBOX,16)
    c_compSTR_B5_merge_storage thec_compSTR_B5_merge_storage (
        .in_almost_empty_in(c_i2_019_q),
        .in_empty_in(c_i2_019_q),
        .in_i_data(c_compSTR_B5_merge_data_pack_0_q),
        .in_i_stall(in_stall_in),
        .in_i_valid(in_valid_in_0),
        .out_o_almost_empty(c_compSTR_B5_merge_storage_out_o_almost_empty),
        .out_o_data(c_compSTR_B5_merge_storage_out_o_data),
        .out_o_empty(c_compSTR_B5_merge_storage_out_o_empty),
        .out_o_stall(c_compSTR_B5_merge_storage_out_o_stall),
        .out_o_valid(c_compSTR_B5_merge_storage_out_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // out_almost_empty_out(GPOUT,39)
    assign out_almost_empty_out = c_compSTR_B5_merge_storage_out_o_almost_empty;

    // c_compSTR_B5_merge_data_unpack_3(BITSELECT,12)
    assign c_compSTR_B5_merge_data_unpack_3_b = c_compSTR_B5_merge_storage_out_o_data[55:48];

    // adapt_scalar_trunc9(ROUND,7)
    assign adapt_scalar_trunc9_in = c_compSTR_B5_merge_data_unpack_3_b[0:0];
    assign adapt_scalar_trunc9_q = adapt_scalar_trunc9_in[0:0];

    // out_cmp21684(GPOUT,40)
    assign out_cmp21684 = adapt_scalar_trunc9_q;

    // out_empty_out(GPOUT,41)
    assign out_empty_out = c_compSTR_B5_merge_storage_out_o_empty;

    // c_compSTR_B5_merge_data_unpack_2(BITSELECT,11)
    assign c_compSTR_B5_merge_data_unpack_2_b = c_compSTR_B5_merge_storage_out_o_data[47:16];

    // out_i_0288_pop12683(GPOUT,42)
    assign out_i_0288_pop12683 = c_compSTR_B5_merge_data_unpack_2_b;

    // c_compSTR_B5_merge_data_unpack_6(BITSELECT,15)
    assign c_compSTR_B5_merge_data_unpack_6_b = c_compSTR_B5_merge_storage_out_o_data[79:72];

    // adapt_scalar_trunc18(ROUND,4)
    assign adapt_scalar_trunc18_in = c_compSTR_B5_merge_data_unpack_6_b[0:0];
    assign adapt_scalar_trunc18_q = adapt_scalar_trunc18_in[0:0];

    // out_memdep_phi9_pop1032_pop14687(GPOUT,43)
    assign out_memdep_phi9_pop1032_pop14687 = adapt_scalar_trunc18_q;

    // c_compSTR_B5_merge_data_unpack_1(BITSELECT,10)
    assign c_compSTR_B5_merge_data_unpack_1_b = c_compSTR_B5_merge_storage_out_o_data[15:8];

    // adapt_scalar_trunc5(ROUND,6)
    assign adapt_scalar_trunc5_in = c_compSTR_B5_merge_data_unpack_1_b[0:0];
    assign adapt_scalar_trunc5_q = adapt_scalar_trunc5_in[0:0];

    // out_memdep_phi9_pop10682(GPOUT,44)
    assign out_memdep_phi9_pop10682 = adapt_scalar_trunc5_q;

    // c_compSTR_B5_merge_data_unpack_5(BITSELECT,14)
    assign c_compSTR_B5_merge_data_unpack_5_b = c_compSTR_B5_merge_storage_out_o_data[71:64];

    // adapt_scalar_trunc15(ROUND,3)
    assign adapt_scalar_trunc15_in = c_compSTR_B5_merge_data_unpack_5_b[0:0];
    assign adapt_scalar_trunc15_q = adapt_scalar_trunc15_in[0:0];

    // out_memdep_phi_pop930_pop13686(GPOUT,45)
    assign out_memdep_phi_pop930_pop13686 = adapt_scalar_trunc15_q;

    // c_compSTR_B5_merge_data_unpack_0(BITSELECT,9)
    assign c_compSTR_B5_merge_data_unpack_0_b = c_compSTR_B5_merge_storage_out_o_data[7:0];

    // adapt_scalar_trunc2(ROUND,5)
    assign adapt_scalar_trunc2_in = c_compSTR_B5_merge_data_unpack_0_b[0:0];
    assign adapt_scalar_trunc2_q = adapt_scalar_trunc2_in[0:0];

    // out_memdep_phi_pop9679(GPOUT,46)
    assign out_memdep_phi_pop9679 = adapt_scalar_trunc2_q;

    // c_compSTR_B5_merge_data_unpack_4(BITSELECT,13)
    assign c_compSTR_B5_merge_data_unpack_4_b = c_compSTR_B5_merge_storage_out_o_data[63:56];

    // adapt_scalar_trunc12(ROUND,2)
    assign adapt_scalar_trunc12_in = c_compSTR_B5_merge_data_unpack_4_b[0:0];
    assign adapt_scalar_trunc12_q = adapt_scalar_trunc12_in[0:0];

    // out_notcmp21685(GPOUT,47)
    assign out_notcmp21685 = adapt_scalar_trunc12_q;

    // out_stall_out_0(GPOUT,48)
    assign out_stall_out_0 = c_compSTR_B5_merge_storage_out_o_stall;

    // out_valid_out(GPOUT,49)
    assign out_valid_out = c_compSTR_B5_merge_storage_out_o_valid;

    // rst_sync(RESETSYNC,50)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
