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// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from i_sfc_logic_s_c1_in_wt_entry_c_compmm_ms_c1_enter_c_compmm_m0
// Created for function/kernel c_compMM_m
// SystemVerilog created on Wed Mar 26 11:59:06 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compMM_m_i_sfc_logic_s_c1_in_wt_entry_0000c1_enter_c_compmm_m0 (
    output wire [63:0] out_intel_reserved_ffwd_257_0,
    output wire [0:0] out_c1_exi4_0_tpl,
    output wire [63:0] out_c1_exi4_1_tpl,
    output wire [63:0] out_c1_exi4_2_tpl,
    output wire [63:0] out_c1_exi4_3_tpl,
    output wire [63:0] out_c1_exi4_4_tpl,
    output wire [0:0] out_o_valid,
    output wire [0:0] out_unnamed_c_compMM_m4,
    input wire [0:0] in_c1_eni1_0_tpl,
    input wire [63:0] in_c1_eni1_1_tpl,
    input wire [63:0] in_c1_eni1_2_tpl,
    input wire [63:0] in_c1_eni1_3_tpl,
    input wire [0:0] in_i_valid,
    output wire [63:0] out_intel_reserved_ffwd_0_0,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    wire [63:0] i_value_i_i155_i_32_c_compmm_m0_trunc_sel_x_b;
    wire [64:0] i_value_i_i155_i_32_c_compmm_m0_add_x_a;
    wire [64:0] i_value_i_i155_i_32_c_compmm_m0_add_x_b;
    logic [64:0] i_value_i_i155_i_32_c_compmm_m0_add_x_o;
    wire [64:0] i_value_i_i155_i_32_c_compmm_m0_add_x_q;
    wire [63:0] i_value_i_i155_i_32_c_compmm_m0_c_i64_1281_x_q;
    wire [63:0] i_value_i_i155_i_64_c_compmm_m0_trunc_sel_x_b;
    wire [64:0] i_value_i_i155_i_64_c_compmm_m0_add_x_a;
    wire [64:0] i_value_i_i155_i_64_c_compmm_m0_add_x_b;
    logic [64:0] i_value_i_i155_i_64_c_compmm_m0_add_x_o;
    wire [64:0] i_value_i_i155_i_64_c_compmm_m0_add_x_q;
    wire [63:0] i_value_i_i155_i_64_c_compmm_m0_c_i64_2561_x_q;
    wire [63:0] i_value_i_i155_i_96_c_compmm_m0_trunc_sel_x_b;
    wire [64:0] i_value_i_i155_i_96_c_compmm_m0_add_x_a;
    wire [64:0] i_value_i_i155_i_96_c_compmm_m0_add_x_b;
    logic [64:0] i_value_i_i155_i_96_c_compmm_m0_add_x_o;
    wire [64:0] i_value_i_i155_i_96_c_compmm_m0_add_x_q;
    wire [63:0] i_value_i_i155_i_96_c_compmm_m0_c_i64_3841_x_q;
    wire [63:0] i_llvm_fpga_ffwd_source_p1025s_struct_complex_fixeds_unnamed_c_compmm_m2_c_compmm_m12_out_intel_reserved_ffwd_0_0;
    wire [63:0] i_llvm_fpga_ffwd_source_p1027s_struct_complex_fixeds_unnamed_c_compmm_m3_c_compmm_m13_out_intel_reserved_ffwd_257_0;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg0_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg1_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg2_q;
    reg [63:0] redist0_sync_together18_aunroll_x_in_c1_eni1_1_tpl_1_q;
    reg [63:0] redist1_sync_together18_aunroll_x_in_c1_eni1_2_tpl_1_q;
    reg [63:0] redist2_sync_together18_aunroll_x_in_c1_eni1_3_tpl_1_q;


    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // valid_fanout_reg2(REG,25)@76 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg2_q <= $unsigned(in_i_valid);
        end
    end

    // redist2_sync_together18_aunroll_x_in_c1_eni1_3_tpl_1(DELAY,28)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist2_sync_together18_aunroll_x_in_c1_eni1_3_tpl_1_q <= $unsigned(in_c1_eni1_3_tpl);
        end
    end

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // i_llvm_fpga_ffwd_source_p1027s_struct_complex_fixeds_unnamed_c_compmm_m3_c_compmm_m13(BLACKBOX,20)@77
    // out out_intel_reserved_ffwd_257_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_p10270000ompmm_m3_c_compmm_m0 thei_llvm_fpga_ffwd_source_p1027s_struct_complex_fixeds_unnamed_c_compmm_m3_c_compmm_m13 (
        .in_predicate_in(GND_q),
        .in_src_data_in_257_0(redist2_sync_together18_aunroll_x_in_c1_eni1_3_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg2_q),
        .out_intel_reserved_ffwd_257_0(i_llvm_fpga_ffwd_source_p1027s_struct_complex_fixeds_unnamed_c_compmm_m3_c_compmm_m13_out_intel_reserved_ffwd_257_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_regfree_osync_x(GPOUT,2)
    assign out_intel_reserved_ffwd_257_0 = i_llvm_fpga_ffwd_source_p1027s_struct_complex_fixeds_unnamed_c_compmm_m3_c_compmm_m13_out_intel_reserved_ffwd_257_0;

    // valid_fanout_reg0(REG,23)@76 + 1
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            valid_fanout_reg0_q <= $unsigned(1'b0);
        end
        else
        begin
            valid_fanout_reg0_q <= $unsigned(in_i_valid);
        end
    end

    // i_value_i_i155_i_96_c_compmm_m0_c_i64_3841_x(CONSTANT,13)
    assign i_value_i_i155_i_96_c_compmm_m0_c_i64_3841_x_q = $unsigned(64'b0000000000000000000000000000000000000000000000000000000110000000);

    // i_value_i_i155_i_96_c_compmm_m0_add_x(ADD,12)@77
    assign i_value_i_i155_i_96_c_compmm_m0_add_x_a = {1'b0, redist1_sync_together18_aunroll_x_in_c1_eni1_2_tpl_1_q};
    assign i_value_i_i155_i_96_c_compmm_m0_add_x_b = {1'b0, i_value_i_i155_i_96_c_compmm_m0_c_i64_3841_x_q};
    assign i_value_i_i155_i_96_c_compmm_m0_add_x_o = $unsigned(i_value_i_i155_i_96_c_compmm_m0_add_x_a) + $unsigned(i_value_i_i155_i_96_c_compmm_m0_add_x_b);
    assign i_value_i_i155_i_96_c_compmm_m0_add_x_q = i_value_i_i155_i_96_c_compmm_m0_add_x_o[64:0];

    // i_value_i_i155_i_96_c_compmm_m0_trunc_sel_x(BITSELECT,11)@77
    assign i_value_i_i155_i_96_c_compmm_m0_trunc_sel_x_b = i_value_i_i155_i_96_c_compmm_m0_add_x_q[63:0];

    // i_value_i_i155_i_64_c_compmm_m0_c_i64_2561_x(CONSTANT,9)
    assign i_value_i_i155_i_64_c_compmm_m0_c_i64_2561_x_q = $unsigned(64'b0000000000000000000000000000000000000000000000000000000100000000);

    // i_value_i_i155_i_64_c_compmm_m0_add_x(ADD,8)@77
    assign i_value_i_i155_i_64_c_compmm_m0_add_x_a = {1'b0, redist1_sync_together18_aunroll_x_in_c1_eni1_2_tpl_1_q};
    assign i_value_i_i155_i_64_c_compmm_m0_add_x_b = {1'b0, i_value_i_i155_i_64_c_compmm_m0_c_i64_2561_x_q};
    assign i_value_i_i155_i_64_c_compmm_m0_add_x_o = $unsigned(i_value_i_i155_i_64_c_compmm_m0_add_x_a) + $unsigned(i_value_i_i155_i_64_c_compmm_m0_add_x_b);
    assign i_value_i_i155_i_64_c_compmm_m0_add_x_q = i_value_i_i155_i_64_c_compmm_m0_add_x_o[64:0];

    // i_value_i_i155_i_64_c_compmm_m0_trunc_sel_x(BITSELECT,7)@77
    assign i_value_i_i155_i_64_c_compmm_m0_trunc_sel_x_b = i_value_i_i155_i_64_c_compmm_m0_add_x_q[63:0];

    // i_value_i_i155_i_32_c_compmm_m0_c_i64_1281_x(CONSTANT,5)
    assign i_value_i_i155_i_32_c_compmm_m0_c_i64_1281_x_q = $unsigned(64'b0000000000000000000000000000000000000000000000000000000010000000);

    // i_value_i_i155_i_32_c_compmm_m0_add_x(ADD,4)@77
    assign i_value_i_i155_i_32_c_compmm_m0_add_x_a = {1'b0, redist1_sync_together18_aunroll_x_in_c1_eni1_2_tpl_1_q};
    assign i_value_i_i155_i_32_c_compmm_m0_add_x_b = {1'b0, i_value_i_i155_i_32_c_compmm_m0_c_i64_1281_x_q};
    assign i_value_i_i155_i_32_c_compmm_m0_add_x_o = $unsigned(i_value_i_i155_i_32_c_compmm_m0_add_x_a) + $unsigned(i_value_i_i155_i_32_c_compmm_m0_add_x_b);
    assign i_value_i_i155_i_32_c_compmm_m0_add_x_q = i_value_i_i155_i_32_c_compmm_m0_add_x_o[64:0];

    // i_value_i_i155_i_32_c_compmm_m0_trunc_sel_x(BITSELECT,3)@77
    assign i_value_i_i155_i_32_c_compmm_m0_trunc_sel_x_b = i_value_i_i155_i_32_c_compmm_m0_add_x_q[63:0];

    // redist1_sync_together18_aunroll_x_in_c1_eni1_2_tpl_1(DELAY,27)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1_sync_together18_aunroll_x_in_c1_eni1_2_tpl_1_q <= $unsigned(in_c1_eni1_2_tpl);
        end
    end

    // sync_out_aunroll_x(GPOUT,15)@77
    assign out_c1_exi4_0_tpl = GND_q;
    assign out_c1_exi4_1_tpl = redist1_sync_together18_aunroll_x_in_c1_eni1_2_tpl_1_q;
    assign out_c1_exi4_2_tpl = i_value_i_i155_i_32_c_compmm_m0_trunc_sel_x_b;
    assign out_c1_exi4_3_tpl = i_value_i_i155_i_64_c_compmm_m0_trunc_sel_x_b;
    assign out_c1_exi4_4_tpl = i_value_i_i155_i_96_c_compmm_m0_trunc_sel_x_b;
    assign out_o_valid = valid_fanout_reg0_q;
    assign out_unnamed_c_compMM_m4 = GND_q;

    // valid_fanout_reg1(REG,24)@76 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg1_q <= $unsigned(in_i_valid);
        end
    end

    // redist0_sync_together18_aunroll_x_in_c1_eni1_1_tpl_1(DELAY,26)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_sync_together18_aunroll_x_in_c1_eni1_1_tpl_1_q <= $unsigned(in_c1_eni1_1_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_p1025s_struct_complex_fixeds_unnamed_c_compmm_m2_c_compmm_m12(BLACKBOX,19)@77
    // out out_intel_reserved_ffwd_0_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_p10250000ompmm_m2_c_compmm_m0 thei_llvm_fpga_ffwd_source_p1025s_struct_complex_fixeds_unnamed_c_compmm_m2_c_compmm_m12 (
        .in_predicate_in(GND_q),
        .in_src_data_in_0_0(redist0_sync_together18_aunroll_x_in_c1_eni1_1_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg1_q),
        .out_intel_reserved_ffwd_0_0(i_llvm_fpga_ffwd_source_p1025s_struct_complex_fixeds_unnamed_c_compmm_m2_c_compmm_m12_out_intel_reserved_ffwd_0_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // regfree_osync(GPOUT,21)
    assign out_intel_reserved_ffwd_0_0 = i_llvm_fpga_ffwd_source_p1025s_struct_complex_fixeds_unnamed_c_compmm_m2_c_compmm_m12_out_intel_reserved_ffwd_0_0;

endmodule
