// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// the  sole  purpose of  programming  logic devices  manufactured by  Intel
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// SystemVerilog created from i_sfc_logic_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m0
// Created for function/kernel c_compMM_m
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compMM_m_i_sfc_logic_s_c0_in_for_body_0000nter9182_c_compmm_m0 (
    output wire [0:0] out_pipeline_dummy_out,
    output wire [0:0] out_pipeline_forked_out,
    output wire [0:0] out_pipeline_valid_out,
    output wire [0:0] out_c0_exi7_0_tpl,
    output wire [63:0] out_c0_exi7_1_tpl,
    output wire [63:0] out_c0_exi7_2_tpl,
    output wire [63:0] out_c0_exi7_3_tpl,
    output wire [63:0] out_c0_exi7_4_tpl,
    output wire [63:0] out_c0_exi7_5_tpl,
    output wire [0:0] out_c0_exi7_6_tpl,
    output wire [0:0] out_c0_exi7_7_tpl,
    output wire [0:0] out_c_compMM_m_B3_current_iter_isspec,
    output wire [0:0] out_o_valid,
    input wire [0:0] in_buffer_in,
    input wire [0:0] in_c0_eni1_0_tpl,
    input wire [0:0] in_c0_eni1_1_tpl,
    input wire [0:0] in_dummy_in,
    input wire [0:0] in_i_valid,
    input wire [63:0] in_intel_reserved_ffwd_0_0,
    input wire [63:0] in_intel_reserved_ffwd_257_0,
    output wire [0:0] out_exiting_valid_out,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    wire [4:0] bgTrunc_i_fpga_indvars_iv_next_c_compmm_m29_sel_x_b;
    wire [31:0] bgTrunc_i_inc_c_compmm_m22_sel_x_b;
    wire [63:0] i_arrayidx_i243_32_c_compmm_m0_trunc_sel_x_b;
    wire [64:0] i_arrayidx_i243_32_c_compmm_m0_add_x_a;
    wire [64:0] i_arrayidx_i243_32_c_compmm_m0_add_x_b;
    logic [64:0] i_arrayidx_i243_32_c_compmm_m0_add_x_o;
    wire [64:0] i_arrayidx_i243_32_c_compmm_m0_add_x_q;
    wire [63:0] i_arrayidx_i243_32_c_compmm_m0_c_i64_1281_x_q;
    wire [63:0] i_arrayidx_i243_64_c_compmm_m0_trunc_sel_x_b;
    wire [64:0] i_arrayidx_i243_64_c_compmm_m0_add_x_a;
    wire [64:0] i_arrayidx_i243_64_c_compmm_m0_add_x_b;
    logic [64:0] i_arrayidx_i243_64_c_compmm_m0_add_x_o;
    wire [64:0] i_arrayidx_i243_64_c_compmm_m0_add_x_q;
    wire [63:0] i_arrayidx_i243_64_c_compmm_m0_c_i64_2561_x_q;
    wire [63:0] i_arrayidx_i243_96_c_compmm_m0_trunc_sel_x_b;
    wire [64:0] i_arrayidx_i243_96_c_compmm_m0_add_x_a;
    wire [64:0] i_arrayidx_i243_96_c_compmm_m0_add_x_b;
    logic [64:0] i_arrayidx_i243_96_c_compmm_m0_add_x_o;
    wire [64:0] i_arrayidx_i243_96_c_compmm_m0_add_x_q;
    wire [63:0] i_arrayidx_i243_96_c_compmm_m0_c_i64_3841_x_q;
    wire [0:0] i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_s;
    reg [0:0] i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_q;
    wire [0:0] i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_s;
    reg [31:0] i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_q;
    wire [0:0] i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m0_i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m23_mux_x_s;
    reg [4:0] i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m0_i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m23_mux_x_q;
    wire [0:0] i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_adapt_scalar_trunc4_sel_x_b;
    wire [6:0] i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_c_i7_03_x_q;
    wire [7:0] i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_element_extension2_x_q;
    wire [0:0] i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_valid;
    wire i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_stall;
    wire i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_stall_bitsignaltemp;
    wire [7:0] i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_data;
    wire [7:0] i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_o_data;
    wire [0:0] i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q;
    wire [0:0] i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_valid;
    wire i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_stall;
    wire i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_stall_bitsignaltemp;
    wire [31:0] i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_data;
    wire [31:0] i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_o_data;
    wire [4:0] i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_adapt_scalar_trunc4_sel_x_b;
    wire [2:0] i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_c_i3_03_x_q;
    wire [7:0] i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_element_extension2_x_q;
    wire [0:0] i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_valid;
    wire i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_stall;
    wire i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_stall_bitsignaltemp;
    wire [7:0] i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_data;
    wire [7:0] i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_o_data;
    wire [63:0] i_mptr_bitcast_index_c_compmm_m0_dupName_0_trunc_sel_x_b;
    wire [64:0] i_mptr_bitcast_index_c_compmm_m0_add_x_a;
    wire [64:0] i_mptr_bitcast_index_c_compmm_m0_add_x_b;
    logic [64:0] i_mptr_bitcast_index_c_compmm_m0_add_x_o;
    wire [64:0] i_mptr_bitcast_index_c_compmm_m0_add_x_q;
    wire [1:0] i_mptr_bitcast_index_c_compmm_m0_c_i2_01_x_q;
    wire [61:0] i_mptr_bitcast_index_c_compmm_m0_narrow_x_b;
    wire [63:0] i_mptr_bitcast_index_c_compmm_m0_shift_join_x_q;
    wire [63:0] i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_dupName_0_trunc_sel_x_b;
    wire [64:0] i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_add_x_a;
    wire [64:0] i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_add_x_b;
    logic [64:0] i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_add_x_o;
    wire [64:0] i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_add_x_q;
    wire [63:0] i_unnamed_c_compmm_m10_sel_x_b;
    wire [31:0] c_i32_052_q;
    wire [31:0] c_i32_153_q;
    wire [4:0] c_i5_1454_q;
    wire [4:0] c_i5_156_q;
    wire [0:0] i_c_compmm_m_b3_current_iter_isspec_c_compmm_m5_q;
    wire [0:0] i_c_compmm_m_b3_next_iter_isreal_c_compmm_m7_q;
    wire [5:0] i_fpga_indvars_iv_next_c_compmm_m29_a;
    wire [5:0] i_fpga_indvars_iv_next_c_compmm_m29_b;
    logic [5:0] i_fpga_indvars_iv_next_c_compmm_m29_o;
    wire [5:0] i_fpga_indvars_iv_next_c_compmm_m29_q;
    wire [32:0] i_inc_c_compmm_m22_a;
    wire [32:0] i_inc_c_compmm_m22_b;
    logic [32:0] i_inc_c_compmm_m22_o;
    wire [32:0] i_inc_c_compmm_m22_q;
    wire [0:0] i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out;
    wire [63:0] i_llvm_fpga_ffwd_dest_p1025s_struct_complex_fixeds_mptr_bitcast25718_c_compmm_m11_out_dest_data_out_0_0;
    wire [63:0] i_llvm_fpga_ffwd_dest_p1027s_struct_complex_fixeds_mptr_bitcast255259275_c_compmm_m20_out_dest_data_out_257_0;
    wire [0:0] i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_data_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_exiting_valid_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_not_exitcond_stall_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_pipeline_dummy_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_pipeline_forked_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_pipeline_valid_out;
    wire [0:0] i_llvm_fpga_push_i1_notexitcond_c_compmm_m28_out_feedback_out_3;
    wire [0:0] i_llvm_fpga_push_i1_notexitcond_c_compmm_m28_out_feedback_valid_out_3;
    wire [0:0] i_notcmp_c_compmm_m27_q;
    wire [63:0] i_unnamed_c_compmm_m10_vt_join_q;
    wire [31:0] i_unnamed_c_compmm_m10_vt_select_31_b;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg0_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg2_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg3_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg4_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg6_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg7_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg9_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg10_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg11_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg12_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg13_q;
    wire [0:0] i_exitcond_c_compmm_m24_cmp_nsign_q;
    reg [0:0] redist0_i_exitcond_c_compmm_m24_cmp_nsign_q_2_q;
    reg [0:0] redist0_i_exitcond_c_compmm_m24_cmp_nsign_q_2_delay_0;
    reg [0:0] redist1_valid_fanout_reg0_q_1_q;
    reg [0:0] redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_q;
    reg [0:0] redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_delay_0;
    reg [0:0] redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_delay_1;
    reg [0:0] redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_delay_2;
    reg [0:0] redist3_i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out_4_q;
    reg [0:0] redist3_i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out_4_delay_0;
    reg [0:0] redist3_i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out_4_delay_1;
    reg [0:0] redist3_i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out_4_delay_2;
    reg [0:0] redist4_sync_together63_aunroll_x_in_i_valid_2_q;
    reg [0:0] redist4_sync_together63_aunroll_x_in_i_valid_2_delay_0;
    reg [0:0] redist5_sync_together63_aunroll_x_in_i_valid_3_q;
    reg [0:0] redist6_sync_together63_aunroll_x_in_i_valid_4_q;
    reg [63:0] redist7_i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_dupName_0_trunc_sel_x_b_1_q;
    reg [63:0] redist8_i_mptr_bitcast_index_c_compmm_m0_dupName_0_trunc_sel_x_b_1_q;
    reg [0:0] redist9_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q_2_q;
    reg [0:0] redist9_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q_2_delay_0;
    reg [31:0] redist10_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_q_1_q;
    reg [0:0] redist11_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_q_2_q;
    reg [0:0] redist11_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_q_2_delay_0;


    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // redist4_sync_together63_aunroll_x_in_i_valid_2(DELAY,126)
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist4_sync_together63_aunroll_x_in_i_valid_2_delay_0 <= '0;
        end
        else
        begin
            redist4_sync_together63_aunroll_x_in_i_valid_2_delay_0 <= $unsigned(in_i_valid);
        end
    end
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist4_sync_together63_aunroll_x_in_i_valid_2_q <= redist4_sync_together63_aunroll_x_in_i_valid_2_delay_0;
        end
    end

    // redist5_sync_together63_aunroll_x_in_i_valid_3(DELAY,127)
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist5_sync_together63_aunroll_x_in_i_valid_3_q <= '0;
        end
        else
        begin
            redist5_sync_together63_aunroll_x_in_i_valid_3_q <= $unsigned(redist4_sync_together63_aunroll_x_in_i_valid_2_q);
        end
    end

    // valid_fanout_reg2(REG,103)@3 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg2_q <= $unsigned(redist5_sync_together63_aunroll_x_in_i_valid_3_q);
        end
    end

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // valid_fanout_reg11(REG,112)@3 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg11_q <= $unsigned(redist5_sync_together63_aunroll_x_in_i_valid_3_q);
        end
    end

    // c_i5_1454(CONSTANT,78)
    assign c_i5_1454_q = $unsigned(5'b01110);

    // i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_c_i3_03_x(CONSTANT,34)
    assign i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_c_i3_03_x_q = $unsigned(3'b000);

    // c_i5_156(CONSTANT,79)
    assign c_i5_156_q = $unsigned(5'b11111);

    // i_fpga_indvars_iv_next_c_compmm_m29(ADD,83)@4
    assign i_fpga_indvars_iv_next_c_compmm_m29_a = {1'b0, i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m0_i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m23_mux_x_q};
    assign i_fpga_indvars_iv_next_c_compmm_m29_b = {1'b0, c_i5_156_q};
    assign i_fpga_indvars_iv_next_c_compmm_m29_o = $unsigned(i_fpga_indvars_iv_next_c_compmm_m29_a) + $unsigned(i_fpga_indvars_iv_next_c_compmm_m29_b);
    assign i_fpga_indvars_iv_next_c_compmm_m29_q = i_fpga_indvars_iv_next_c_compmm_m29_o[5:0];

    // bgTrunc_i_fpga_indvars_iv_next_c_compmm_m29_sel_x(BITSELECT,2)@4
    assign bgTrunc_i_fpga_indvars_iv_next_c_compmm_m29_sel_x_b = i_fpga_indvars_iv_next_c_compmm_m29_q[4:0];

    // i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_element_extension2_x(BITJOIN,35)@4
    assign i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_element_extension2_x_q = {i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_c_i3_03_x_q, bgTrunc_i_fpga_indvars_iv_next_c_compmm_m29_sel_x_b};

    // i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x(LOGICAL,28)@1
    assign i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q = ~ (GND_q);

    // valid_fanout_reg13(REG,114)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg13_q <= $unsigned(in_i_valid);
        end
    end

    // redist9_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q_2(DELAY,131)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist9_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q_2_delay_0 <= $unsigned(i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q);
            redist9_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q_2_q <= redist9_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q_2_delay_0;
        end
    end

    // valid_fanout_reg12(REG,113)@2 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg12_q <= $unsigned(redist4_sync_together63_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x(FIFODELAY,36)@1 + 1
    // in i_valid@3
    // in i_write_pred@3
    // in i_data@4
    // out o_data@4
    assign i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_stall = ~ (valid_fanout_reg13_q & i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q);
    assign i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_valid = valid_fanout_reg12_q & redist9_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_data = i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_element_extension2_x_q;
    assign i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_valid[0];
    assign i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(8),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x (
        .i_valid(i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_i_stall_bitsignaltemp),
        .i_data(i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_element_extension2_x_q),
        .o_data(i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_adapt_scalar_trunc4_sel_x(BITSELECT,32)@4
    assign i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_adapt_scalar_trunc4_sel_x_b = i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m1_x_o_data[4:0];

    // i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m0_i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m23_mux_x(MUX,22)@4
    assign i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m0_i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m23_mux_x_s = redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_q;
    always @(i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m0_i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m23_mux_x_s or i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_adapt_scalar_trunc4_sel_x_b or c_i5_1454_q)
    begin
        unique case (i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m0_i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m23_mux_x_s)
            1'b0 : i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m0_i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m23_mux_x_q = i_llvm_fpga_push_i5_fpga_indvars_iv_push6_c_compmm_m0_adapt_scalar_trunc4_sel_x_b;
            1'b1 : i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m0_i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m23_mux_x_q = c_i5_1454_q;
            default : i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m0_i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m23_mux_x_q = 5'b0;
        endcase
    end

    // i_exitcond_c_compmm_m24_cmp_nsign(LOGICAL,121)@4
    assign i_exitcond_c_compmm_m24_cmp_nsign_q = $unsigned(~ (i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m0_i_llvm_fpga_pop_i5_fpga_indvars_iv_pop6_c_compmm_m23_mux_x_q[4:4]));

    // i_llvm_fpga_push_i1_notexitcond_c_compmm_m28(BLACKBOX,90)@4
    // in in_empty_in@20000000
    // out out_feedback_out_3@20000000
    // out out_feedback_valid_out_3@20000000
    c_compMM_m_i_llvm_fpga_push_i1_notexitcond_c_compmm_m0 thei_llvm_fpga_push_i1_notexitcond_c_compmm_m28 (
        .in_almost_empty_in(GND_q),
        .in_data_in(i_exitcond_c_compmm_m24_cmp_nsign_q),
        .in_empty_in(GND_q),
        .in_feedback_stall_in_3(i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_not_exitcond_stall_out),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg11_q),
        .out_data_out(),
        .out_feedback_out_3(i_llvm_fpga_push_i1_notexitcond_c_compmm_m28_out_feedback_out_3),
        .out_feedback_valid_out_3(i_llvm_fpga_push_i1_notexitcond_c_compmm_m28_out_feedback_valid_out_3),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2(BLACKBOX,85)@0
    // in in_stall_in@20000000
    c_compMM_m_i_llvm_fpga_dummy_thread_c_co0000b3_dummy_c_compmm_m0 thei_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2 (
        .in_dummy_in(in_dummy_in),
        .in_stall_in(GND_q),
        .in_valid_in(in_i_valid),
        .out_dummy_out(i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist3_i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out_4(DELAY,125)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist3_i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out_4_delay_0 <= $unsigned(i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out);
            redist3_i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out_4_delay_1 <= redist3_i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out_4_delay_0;
            redist3_i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out_4_delay_2 <= redist3_i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out_4_delay_1;
            redist3_i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out_4_q <= redist3_i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out_4_delay_2;
        end
    end

    // i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3(BLACKBOX,88)@0
    // in in_stall_in@20000000
    c_compMM_m_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m0 thei_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3 (
        .in_buffer_in(in_buffer_in),
        .in_stall_in(GND_q),
        .in_valid_in(in_i_valid),
        .out_buffer_out(i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4(DELAY,124)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_delay_0 <= $unsigned(i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out);
            redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_delay_1 <= redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_delay_0;
            redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_delay_2 <= redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_delay_1;
            redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_q <= redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_delay_2;
        end
    end

    // i_llvm_fpga_pipeline_keep_going_c_compmm_m6(BLACKBOX,89)@4
    // out out_exiting_stall_out@20000000
    // out out_exiting_valid_out@20000000
    // out out_not_exitcond_stall_out@20000000
    // out out_pipeline_dummy_out@20000000
    // out out_pipeline_forked_out@20000000
    // out out_pipeline_valid_out@20000000
    c_compMM_m_i_llvm_fpga_pipeline_keep_going_c_compmm_m0 thei_llvm_fpga_pipeline_keep_going_c_compmm_m6 (
        .in_data_in(redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_q),
        .in_dummy_in(redist3_i_llvm_fpga_dummy_thread_c_compmm_m_b3_dummy_c_compmm_m2_out_dummy_out_4_q),
        .in_forked_in(redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_q),
        .in_not_exitcond_in(i_llvm_fpga_push_i1_notexitcond_c_compmm_m28_out_feedback_out_3),
        .in_not_exitcond_valid_in(i_llvm_fpga_push_i1_notexitcond_c_compmm_m28_out_feedback_valid_out_3),
        .in_pipeline_stall_in(GND_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg2_q),
        .out_data_out(i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_data_out),
        .out_exiting_stall_out(),
        .out_exiting_valid_out(i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_exiting_valid_out),
        .out_not_exitcond_stall_out(i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_not_exitcond_stall_out),
        .out_pipeline_dummy_out(i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_pipeline_dummy_out),
        .out_pipeline_forked_out(i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_pipeline_forked_out),
        .out_pipeline_valid_out(i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_pipeline_valid_out),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_regfree_osync_x(GPOUT,5)
    assign out_pipeline_dummy_out = i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_pipeline_dummy_out;

    // dupName_1_regfree_osync_x(GPOUT,6)
    assign out_pipeline_forked_out = i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_pipeline_forked_out;

    // dupName_2_regfree_osync_x(GPOUT,7)
    assign out_pipeline_valid_out = i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_pipeline_valid_out;

    // redist6_sync_together63_aunroll_x_in_i_valid_4(DELAY,128)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist6_sync_together63_aunroll_x_in_i_valid_4_q <= $unsigned(redist5_sync_together63_aunroll_x_in_i_valid_3_q);
        end
    end

    // valid_fanout_reg0(REG,101)@4 + 1
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            valid_fanout_reg0_q <= $unsigned(1'b0);
        end
        else
        begin
            valid_fanout_reg0_q <= $unsigned(redist6_sync_together63_aunroll_x_in_i_valid_4_q);
        end
    end

    // redist1_valid_fanout_reg0_q_1(DELAY,123)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1_valid_fanout_reg0_q_1_q <= $unsigned(valid_fanout_reg0_q);
        end
    end

    // i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_c_i7_03_x(CONSTANT,25)
    assign i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_c_i7_03_x_q = $unsigned(7'b0000000);

    // i_c_compmm_m_b3_next_iter_isreal_c_compmm_m7(LOGICAL,81)@4
    assign i_c_compmm_m_b3_next_iter_isreal_c_compmm_m7_q = i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_q & i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_data_out;

    // i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_element_extension2_x(BITJOIN,26)@4
    assign i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_element_extension2_x_q = {i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_c_i7_03_x_q, i_c_compmm_m_b3_next_iter_isreal_c_compmm_m7_q};

    // valid_fanout_reg4(REG,105)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg4_q <= $unsigned(in_i_valid);
        end
    end

    // valid_fanout_reg3(REG,104)@2 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg3_q <= $unsigned(redist4_sync_together63_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x(FIFODELAY,27)@1 + 1
    // in i_valid@3
    // in i_write_pred@3
    // in i_data@4
    // out o_data@4
    assign i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_stall = ~ (valid_fanout_reg4_q & i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q);
    assign i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_valid = valid_fanout_reg3_q & redist9_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_data = i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_element_extension2_x_q;
    assign i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_valid[0];
    assign i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(8),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x (
        .i_valid(i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_i_stall_bitsignaltemp),
        .i_data(i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_element_extension2_x_q),
        .o_data(i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_adapt_scalar_trunc4_sel_x(BITSELECT,23)@4
    assign i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_adapt_scalar_trunc4_sel_x_b = i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m1_x_o_data[0:0];

    // i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x(MUX,20)@4
    assign i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_s = redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_q;
    always @(i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_s or i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_adapt_scalar_trunc4_sel_x_b or VCC_q)
    begin
        unique case (i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_s)
            1'b0 : i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_q = i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_adapt_scalar_trunc4_sel_x_b;
            1'b1 : i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_q = VCC_q;
            default : i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_q = 1'b0;
        endcase
    end

    // redist11_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_q_2(DELAY,133)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist11_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_q_2_delay_0 <= $unsigned(i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_q);
            redist11_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_q_2_q <= redist11_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_q_2_delay_0;
        end
    end

    // i_c_compmm_m_b3_current_iter_isspec_c_compmm_m5(LOGICAL,80)@6
    assign i_c_compmm_m_b3_current_iter_isspec_c_compmm_m5_q = redist11_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m0_i_llvm_fpga_pop_coalesce_i1_c_compmm_m_b3_current_iter_isreal_c_compmm_m4_mux_x_q_2_q ^ VCC_q;

    // i_notcmp_c_compmm_m27(LOGICAL,91)@6
    assign i_notcmp_c_compmm_m27_q = redist0_i_exitcond_c_compmm_m24_cmp_nsign_q_2_q ^ VCC_q;

    // redist0_i_exitcond_c_compmm_m24_cmp_nsign_q_2(DELAY,122)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_exitcond_c_compmm_m24_cmp_nsign_q_2_delay_0 <= $unsigned(i_exitcond_c_compmm_m24_cmp_nsign_q);
            redist0_i_exitcond_c_compmm_m24_cmp_nsign_q_2_q <= redist0_i_exitcond_c_compmm_m24_cmp_nsign_q_2_delay_0;
        end
    end

    // c_i32_052(CONSTANT,76)
    assign c_i32_052_q = $unsigned(32'b00000000000000000000000000000000);

    // c_i32_153(CONSTANT,77)
    assign c_i32_153_q = $unsigned(32'b00000000000000000000000000000001);

    // i_inc_c_compmm_m22(ADD,84)@4
    assign i_inc_c_compmm_m22_a = {1'b0, i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_q};
    assign i_inc_c_compmm_m22_b = {1'b0, c_i32_153_q};
    assign i_inc_c_compmm_m22_o = $unsigned(i_inc_c_compmm_m22_a) + $unsigned(i_inc_c_compmm_m22_b);
    assign i_inc_c_compmm_m22_q = i_inc_c_compmm_m22_o[32:0];

    // bgTrunc_i_inc_c_compmm_m22_sel_x(BITSELECT,3)@4
    assign bgTrunc_i_inc_c_compmm_m22_sel_x_b = i_inc_c_compmm_m22_q[31:0];

    // valid_fanout_reg10(REG,111)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg10_q <= $unsigned(in_i_valid);
        end
    end

    // valid_fanout_reg9(REG,110)@2 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg9_q <= $unsigned(redist4_sync_together63_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x(FIFODELAY,29)@1 + 1
    // in i_valid@3
    // in i_write_pred@3
    // in i_data@4
    // out o_data@4
    assign i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_stall = ~ (valid_fanout_reg10_q & i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q);
    assign i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_valid = valid_fanout_reg9_q & redist9_i_llvm_fpga_push_i1_c_compmm_m_b3_next_iter_isreal_push_c_compmm_m0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_data = bgTrunc_i_inc_c_compmm_m22_sel_x_b;
    assign i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_valid[0];
    assign i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(32),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x (
        .i_valid(i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_i_stall_bitsignaltemp),
        .i_data(bgTrunc_i_inc_c_compmm_m22_sel_x_b),
        .o_data(i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x(MUX,21)@4
    assign i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_s = redist2_i_llvm_fpga_forked_c_compmm_m_b3_forked_c_compmm_m3_out_buffer_out_4_q;
    always @(i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_s or i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_o_data or c_i32_052_q)
    begin
        unique case (i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_s)
            1'b0 : i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_q = i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m0_i_llvm_fpga_push_i32_i_0252_push7_c_compmm_m1_x_o_data;
            1'b1 : i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_q = c_i32_052_q;
            default : i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_q = 32'b0;
        endcase
    end

    // redist10_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_q_1(DELAY,132)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist10_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_q_1_q <= $unsigned(i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_q);
        end
    end

    // i_unnamed_c_compmm_m10_sel_x(BITSELECT,50)@5
    assign i_unnamed_c_compmm_m10_sel_x_b = {32'b00000000000000000000000000000000, redist10_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m0_i_llvm_fpga_pop_i32_i_0252_pop7_c_compmm_m9_mux_x_q_1_q[31:0]};

    // i_unnamed_c_compmm_m10_vt_select_31(BITSELECT,95)@5
    assign i_unnamed_c_compmm_m10_vt_select_31_b = i_unnamed_c_compmm_m10_sel_x_b[31:0];

    // i_unnamed_c_compmm_m10_vt_join(BITJOIN,94)@5
    assign i_unnamed_c_compmm_m10_vt_join_q = {c_i32_052_q, i_unnamed_c_compmm_m10_vt_select_31_b};

    // i_mptr_bitcast_index_c_compmm_m0_narrow_x(BITSELECT,42)@5
    assign i_mptr_bitcast_index_c_compmm_m0_narrow_x_b = i_unnamed_c_compmm_m10_vt_join_q[61:0];

    // i_mptr_bitcast_index_c_compmm_m0_c_i2_01_x(CONSTANT,41)
    assign i_mptr_bitcast_index_c_compmm_m0_c_i2_01_x_q = $unsigned(2'b00);

    // i_mptr_bitcast_index_c_compmm_m0_shift_join_x(BITJOIN,43)@5
    assign i_mptr_bitcast_index_c_compmm_m0_shift_join_x_q = {i_mptr_bitcast_index_c_compmm_m0_narrow_x_b, i_mptr_bitcast_index_c_compmm_m0_c_i2_01_x_q};

    // valid_fanout_reg7(REG,108)@4 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg7_q <= $unsigned(redist6_sync_together63_aunroll_x_in_i_valid_4_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_p1027s_struct_complex_fixeds_mptr_bitcast255259275_c_compmm_m20(BLACKBOX,87)@5
    c_compMM_m_i_llvm_fpga_ffwd_dest_p1027s_000055259275_c_compmm_m0 thei_llvm_fpga_ffwd_dest_p1027s_struct_complex_fixeds_mptr_bitcast255259275_c_compmm_m20 (
        .in_intel_reserved_ffwd_257_0(in_intel_reserved_ffwd_257_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg7_q),
        .out_dest_data_out_257_0(i_llvm_fpga_ffwd_dest_p1027s_struct_complex_fixeds_mptr_bitcast255259275_c_compmm_m20_out_dest_data_out_257_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_add_x(ADD,46)@5
    assign i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_add_x_a = {1'b0, i_llvm_fpga_ffwd_dest_p1027s_struct_complex_fixeds_mptr_bitcast255259275_c_compmm_m20_out_dest_data_out_257_0};
    assign i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_add_x_b = {1'b0, i_mptr_bitcast_index_c_compmm_m0_shift_join_x_q};
    assign i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_add_x_o = $unsigned(i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_add_x_a) + $unsigned(i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_add_x_b);
    assign i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_add_x_q = i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_add_x_o[64:0];

    // i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_dupName_0_trunc_sel_x(BITSELECT,44)@5
    assign i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_dupName_0_trunc_sel_x_b = i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_add_x_q[63:0];

    // redist7_i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_dupName_0_trunc_sel_x_b_1(DELAY,129)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist7_i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_dupName_0_trunc_sel_x_b_1_q <= $unsigned(i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_dupName_0_trunc_sel_x_b);
        end
    end

    // i_arrayidx_i243_96_c_compmm_m0_c_i64_3841_x(CONSTANT,18)
    assign i_arrayidx_i243_96_c_compmm_m0_c_i64_3841_x_q = $unsigned(64'b0000000000000000000000000000000000000000000000000000000110000000);

    // i_arrayidx_i243_96_c_compmm_m0_add_x(ADD,17)@6
    assign i_arrayidx_i243_96_c_compmm_m0_add_x_a = {1'b0, redist8_i_mptr_bitcast_index_c_compmm_m0_dupName_0_trunc_sel_x_b_1_q};
    assign i_arrayidx_i243_96_c_compmm_m0_add_x_b = {1'b0, i_arrayidx_i243_96_c_compmm_m0_c_i64_3841_x_q};
    assign i_arrayidx_i243_96_c_compmm_m0_add_x_o = $unsigned(i_arrayidx_i243_96_c_compmm_m0_add_x_a) + $unsigned(i_arrayidx_i243_96_c_compmm_m0_add_x_b);
    assign i_arrayidx_i243_96_c_compmm_m0_add_x_q = i_arrayidx_i243_96_c_compmm_m0_add_x_o[64:0];

    // i_arrayidx_i243_96_c_compmm_m0_trunc_sel_x(BITSELECT,16)@6
    assign i_arrayidx_i243_96_c_compmm_m0_trunc_sel_x_b = i_arrayidx_i243_96_c_compmm_m0_add_x_q[63:0];

    // i_arrayidx_i243_64_c_compmm_m0_c_i64_2561_x(CONSTANT,14)
    assign i_arrayidx_i243_64_c_compmm_m0_c_i64_2561_x_q = $unsigned(64'b0000000000000000000000000000000000000000000000000000000100000000);

    // i_arrayidx_i243_64_c_compmm_m0_add_x(ADD,13)@6
    assign i_arrayidx_i243_64_c_compmm_m0_add_x_a = {1'b0, redist8_i_mptr_bitcast_index_c_compmm_m0_dupName_0_trunc_sel_x_b_1_q};
    assign i_arrayidx_i243_64_c_compmm_m0_add_x_b = {1'b0, i_arrayidx_i243_64_c_compmm_m0_c_i64_2561_x_q};
    assign i_arrayidx_i243_64_c_compmm_m0_add_x_o = $unsigned(i_arrayidx_i243_64_c_compmm_m0_add_x_a) + $unsigned(i_arrayidx_i243_64_c_compmm_m0_add_x_b);
    assign i_arrayidx_i243_64_c_compmm_m0_add_x_q = i_arrayidx_i243_64_c_compmm_m0_add_x_o[64:0];

    // i_arrayidx_i243_64_c_compmm_m0_trunc_sel_x(BITSELECT,12)@6
    assign i_arrayidx_i243_64_c_compmm_m0_trunc_sel_x_b = i_arrayidx_i243_64_c_compmm_m0_add_x_q[63:0];

    // i_arrayidx_i243_32_c_compmm_m0_c_i64_1281_x(CONSTANT,10)
    assign i_arrayidx_i243_32_c_compmm_m0_c_i64_1281_x_q = $unsigned(64'b0000000000000000000000000000000000000000000000000000000010000000);

    // i_arrayidx_i243_32_c_compmm_m0_add_x(ADD,9)@6
    assign i_arrayidx_i243_32_c_compmm_m0_add_x_a = {1'b0, redist8_i_mptr_bitcast_index_c_compmm_m0_dupName_0_trunc_sel_x_b_1_q};
    assign i_arrayidx_i243_32_c_compmm_m0_add_x_b = {1'b0, i_arrayidx_i243_32_c_compmm_m0_c_i64_1281_x_q};
    assign i_arrayidx_i243_32_c_compmm_m0_add_x_o = $unsigned(i_arrayidx_i243_32_c_compmm_m0_add_x_a) + $unsigned(i_arrayidx_i243_32_c_compmm_m0_add_x_b);
    assign i_arrayidx_i243_32_c_compmm_m0_add_x_q = i_arrayidx_i243_32_c_compmm_m0_add_x_o[64:0];

    // i_arrayidx_i243_32_c_compmm_m0_trunc_sel_x(BITSELECT,8)@6
    assign i_arrayidx_i243_32_c_compmm_m0_trunc_sel_x_b = i_arrayidx_i243_32_c_compmm_m0_add_x_q[63:0];

    // valid_fanout_reg6(REG,107)@4 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg6_q <= $unsigned(redist6_sync_together63_aunroll_x_in_i_valid_4_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_p1025s_struct_complex_fixeds_mptr_bitcast25718_c_compmm_m11(BLACKBOX,86)@5
    c_compMM_m_i_llvm_fpga_ffwd_dest_p1025s_0000ast25718_c_compmm_m0 thei_llvm_fpga_ffwd_dest_p1025s_struct_complex_fixeds_mptr_bitcast25718_c_compmm_m11 (
        .in_intel_reserved_ffwd_0_0(in_intel_reserved_ffwd_0_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg6_q),
        .out_dest_data_out_0_0(i_llvm_fpga_ffwd_dest_p1025s_struct_complex_fixeds_mptr_bitcast25718_c_compmm_m11_out_dest_data_out_0_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_mptr_bitcast_index_c_compmm_m0_add_x(ADD,40)@5
    assign i_mptr_bitcast_index_c_compmm_m0_add_x_a = {1'b0, i_llvm_fpga_ffwd_dest_p1025s_struct_complex_fixeds_mptr_bitcast25718_c_compmm_m11_out_dest_data_out_0_0};
    assign i_mptr_bitcast_index_c_compmm_m0_add_x_b = {1'b0, i_mptr_bitcast_index_c_compmm_m0_shift_join_x_q};
    assign i_mptr_bitcast_index_c_compmm_m0_add_x_o = $unsigned(i_mptr_bitcast_index_c_compmm_m0_add_x_a) + $unsigned(i_mptr_bitcast_index_c_compmm_m0_add_x_b);
    assign i_mptr_bitcast_index_c_compmm_m0_add_x_q = i_mptr_bitcast_index_c_compmm_m0_add_x_o[64:0];

    // i_mptr_bitcast_index_c_compmm_m0_dupName_0_trunc_sel_x(BITSELECT,38)@5
    assign i_mptr_bitcast_index_c_compmm_m0_dupName_0_trunc_sel_x_b = i_mptr_bitcast_index_c_compmm_m0_add_x_q[63:0];

    // redist8_i_mptr_bitcast_index_c_compmm_m0_dupName_0_trunc_sel_x_b_1(DELAY,130)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist8_i_mptr_bitcast_index_c_compmm_m0_dupName_0_trunc_sel_x_b_1_q <= $unsigned(i_mptr_bitcast_index_c_compmm_m0_dupName_0_trunc_sel_x_b);
        end
    end

    // sync_out_aunroll_x(GPOUT,51)@6
    assign out_c0_exi7_0_tpl = GND_q;
    assign out_c0_exi7_1_tpl = redist8_i_mptr_bitcast_index_c_compmm_m0_dupName_0_trunc_sel_x_b_1_q;
    assign out_c0_exi7_2_tpl = i_arrayidx_i243_32_c_compmm_m0_trunc_sel_x_b;
    assign out_c0_exi7_3_tpl = i_arrayidx_i243_64_c_compmm_m0_trunc_sel_x_b;
    assign out_c0_exi7_4_tpl = i_arrayidx_i243_96_c_compmm_m0_trunc_sel_x_b;
    assign out_c0_exi7_5_tpl = redist7_i_ref_tmp_sroa_0_0_sroa_idx_c_compmm_m0_dupName_0_trunc_sel_x_b_1_q;
    assign out_c0_exi7_6_tpl = redist0_i_exitcond_c_compmm_m24_cmp_nsign_q_2_q;
    assign out_c0_exi7_7_tpl = i_notcmp_c_compmm_m27_q;
    assign out_c_compMM_m_B3_current_iter_isspec = i_c_compmm_m_b3_current_iter_isspec_c_compmm_m5_q;
    assign out_o_valid = redist1_valid_fanout_reg0_q_1_q;

    // regfree_osync(GPOUT,99)
    assign out_exiting_valid_out = i_llvm_fpga_pipeline_keep_going_c_compmm_m6_out_exiting_valid_out;

endmodule
