// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
// Legal Notice: Copyright 2022 Intel Corporation.  All rights reserved.
// Your use of  Intel Corporation's design tools,  logic functions and other
// software and  tools, and its AMPP partner logic functions, and any output
// files any  of the foregoing (including  device programming  or simulation
// files), and  any associated  documentation  or information  are expressly
// subject  to the terms and  conditions of the  Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement,  including,  without limitation,  that your use is for
// the  sole  purpose of  programming  logic devices  manufactured by  Intel
// and  sold by Intel  or its authorized  distributors. Please refer  to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------

// SystemVerilog created from c_compSTR_B3_branch
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_B3_branch (
    input wire [0:0] in_almost_empty_in,
    input wire [31:0] in_c0_exe1697,
    input wire [0:0] in_c0_exe2698,
    input wire [0:0] in_c0_exe4,
    input wire [0:0] in_c0_exe5,
    input wire [0:0] in_c0_exe6,
    input wire [0:0] in_c0_exe7,
    input wire [0:0] in_c0_exe8,
    input wire [0:0] in_empty_in,
    input wire [0:0] in_stall_in_0,
    input wire [0:0] in_valid_in,
    output wire [31:0] out_c0_exe1697,
    output wire [0:0] out_c0_exe2698,
    output wire [0:0] out_c0_exe4,
    output wire [0:0] out_c0_exe5,
    output wire [0:0] out_c0_exe6,
    output wire [0:0] out_c0_exe7,
    output wire [0:0] out_c0_exe8,
    output wire [0:0] out_stall_out,
    output wire [0:0] out_valid_out_0,
    input wire clock,
    input wire resetn
    );

    wire [0:0] adapt_scalar_trunc12_in;
    wire [0:0] adapt_scalar_trunc12_q;
    wire [0:0] adapt_scalar_trunc15_in;
    wire [0:0] adapt_scalar_trunc15_q;
    wire [0:0] adapt_scalar_trunc18_in;
    wire [0:0] adapt_scalar_trunc18_q;
    wire [0:0] adapt_scalar_trunc3_in;
    wire [0:0] adapt_scalar_trunc3_q;
    wire [0:0] adapt_scalar_trunc6_in;
    wire [0:0] adapt_scalar_trunc6_q;
    wire [0:0] adapt_scalar_trunc9_in;
    wire [0:0] adapt_scalar_trunc9_q;
    wire [79:0] c_compSTR_B3_branch_data_pack_q;
    wire [31:0] c_compSTR_B3_branch_data_unpack_0_b;
    wire [7:0] c_compSTR_B3_branch_data_unpack_1_b;
    wire [7:0] c_compSTR_B3_branch_data_unpack_2_b;
    wire [7:0] c_compSTR_B3_branch_data_unpack_3_b;
    wire [7:0] c_compSTR_B3_branch_data_unpack_4_b;
    wire [7:0] c_compSTR_B3_branch_data_unpack_5_b;
    wire [7:0] c_compSTR_B3_branch_data_unpack_6_b;
    wire [6:0] c_i7_011_q;
    wire [7:0] element_extension1_q;
    wire [7:0] element_extension10_q;
    wire [7:0] element_extension13_q;
    wire [7:0] element_extension16_q;
    wire [7:0] element_extension4_q;
    wire [7:0] element_extension7_q;
    reg [0:0] rst_sync_rst_sclrn;


    // c_i7_011(CONSTANT,16)
    assign c_i7_011_q = $unsigned(7'b0000000);

    // element_extension16(BITJOIN,25)
    assign element_extension16_q = {c_i7_011_q, in_c0_exe8};

    // element_extension13(BITJOIN,24)
    assign element_extension13_q = {c_i7_011_q, in_c0_exe7};

    // element_extension10(BITJOIN,23)
    assign element_extension10_q = {c_i7_011_q, in_c0_exe6};

    // element_extension7(BITJOIN,27)
    assign element_extension7_q = {c_i7_011_q, in_c0_exe5};

    // element_extension4(BITJOIN,26)
    assign element_extension4_q = {c_i7_011_q, in_c0_exe4};

    // element_extension1(BITJOIN,22)
    assign element_extension1_q = {c_i7_011_q, in_c0_exe2698};

    // c_compSTR_B3_branch_data_pack(BITJOIN,8)
    assign c_compSTR_B3_branch_data_pack_q = {element_extension16_q, element_extension13_q, element_extension10_q, element_extension7_q, element_extension4_q, element_extension1_q, in_c0_exe1697};

    // c_compSTR_B3_branch_data_unpack_0(BITSELECT,9)
    assign c_compSTR_B3_branch_data_unpack_0_b = c_compSTR_B3_branch_data_pack_q[31:0];

    // out_c0_exe1697(GPOUT,39)
    assign out_c0_exe1697 = c_compSTR_B3_branch_data_unpack_0_b;

    // c_compSTR_B3_branch_data_unpack_1(BITSELECT,10)
    assign c_compSTR_B3_branch_data_unpack_1_b = c_compSTR_B3_branch_data_pack_q[39:32];

    // adapt_scalar_trunc3(ROUND,5)
    assign adapt_scalar_trunc3_in = c_compSTR_B3_branch_data_unpack_1_b[0:0];
    assign adapt_scalar_trunc3_q = adapt_scalar_trunc3_in[0:0];

    // out_c0_exe2698(GPOUT,40)
    assign out_c0_exe2698 = adapt_scalar_trunc3_q;

    // c_compSTR_B3_branch_data_unpack_2(BITSELECT,11)
    assign c_compSTR_B3_branch_data_unpack_2_b = c_compSTR_B3_branch_data_pack_q[47:40];

    // adapt_scalar_trunc6(ROUND,6)
    assign adapt_scalar_trunc6_in = c_compSTR_B3_branch_data_unpack_2_b[0:0];
    assign adapt_scalar_trunc6_q = adapt_scalar_trunc6_in[0:0];

    // out_c0_exe4(GPOUT,41)
    assign out_c0_exe4 = adapt_scalar_trunc6_q;

    // c_compSTR_B3_branch_data_unpack_3(BITSELECT,12)
    assign c_compSTR_B3_branch_data_unpack_3_b = c_compSTR_B3_branch_data_pack_q[55:48];

    // adapt_scalar_trunc9(ROUND,7)
    assign adapt_scalar_trunc9_in = c_compSTR_B3_branch_data_unpack_3_b[0:0];
    assign adapt_scalar_trunc9_q = adapt_scalar_trunc9_in[0:0];

    // out_c0_exe5(GPOUT,42)
    assign out_c0_exe5 = adapt_scalar_trunc9_q;

    // c_compSTR_B3_branch_data_unpack_4(BITSELECT,13)
    assign c_compSTR_B3_branch_data_unpack_4_b = c_compSTR_B3_branch_data_pack_q[63:56];

    // adapt_scalar_trunc12(ROUND,2)
    assign adapt_scalar_trunc12_in = c_compSTR_B3_branch_data_unpack_4_b[0:0];
    assign adapt_scalar_trunc12_q = adapt_scalar_trunc12_in[0:0];

    // out_c0_exe6(GPOUT,43)
    assign out_c0_exe6 = adapt_scalar_trunc12_q;

    // c_compSTR_B3_branch_data_unpack_5(BITSELECT,14)
    assign c_compSTR_B3_branch_data_unpack_5_b = c_compSTR_B3_branch_data_pack_q[71:64];

    // adapt_scalar_trunc15(ROUND,3)
    assign adapt_scalar_trunc15_in = c_compSTR_B3_branch_data_unpack_5_b[0:0];
    assign adapt_scalar_trunc15_q = adapt_scalar_trunc15_in[0:0];

    // out_c0_exe7(GPOUT,44)
    assign out_c0_exe7 = adapt_scalar_trunc15_q;

    // c_compSTR_B3_branch_data_unpack_6(BITSELECT,15)
    assign c_compSTR_B3_branch_data_unpack_6_b = c_compSTR_B3_branch_data_pack_q[79:72];

    // adapt_scalar_trunc18(ROUND,4)
    assign adapt_scalar_trunc18_in = c_compSTR_B3_branch_data_unpack_6_b[0:0];
    assign adapt_scalar_trunc18_q = adapt_scalar_trunc18_in[0:0];

    // out_c0_exe8(GPOUT,45)
    assign out_c0_exe8 = adapt_scalar_trunc18_q;

    // out_stall_out(GPOUT,46)
    assign out_stall_out = in_stall_in_0;

    // out_valid_out_0(GPOUT,47)
    assign out_valid_out_0 = in_valid_in;

    // rst_sync(RESETSYNC,48)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
