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// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
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// SystemVerilog created from i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m1_data_fifo
// Created for function/kernel c_compMM_m
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compMM_m_i_llvm_fpga_sfc_exit_s_c0_out0001_compmm_m1_data_fifo (
    output wire [0:0] out_o_almost_empty,
    output wire [0:0] out_o_data_0_tpl,
    output wire [63:0] out_o_data_1_tpl,
    output wire [63:0] out_o_data_2_tpl,
    output wire [63:0] out_o_data_3_tpl,
    output wire [63:0] out_o_data_4_tpl,
    output wire [63:0] out_o_data_5_tpl,
    output wire [0:0] out_o_data_6_tpl,
    output wire [0:0] out_o_data_7_tpl,
    output wire [0:0] out_o_empty,
    output wire [0:0] out_o_valid,
    input wire [0:0] in_almost_empty_in,
    input wire [0:0] in_empty_in,
    input wire [0:0] in_i_data_0_tpl,
    input wire [63:0] in_i_data_1_tpl,
    input wire [63:0] in_i_data_2_tpl,
    input wire [63:0] in_i_data_3_tpl,
    input wire [63:0] in_i_data_4_tpl,
    input wire [63:0] in_i_data_5_tpl,
    input wire [0:0] in_i_data_6_tpl,
    input wire [0:0] in_i_data_7_tpl,
    input wire [0:0] in_i_valid,
    input wire [0:0] in_i_stall,
    output wire [0:0] out_o_stall,
    input wire clock,
    input wire resetn
    );

    wire [0:0] adapt_scalar_trunc13_in;
    wire [0:0] adapt_scalar_trunc13_q;
    wire [0:0] adapt_scalar_trunc25_in;
    wire [0:0] adapt_scalar_trunc25_q;
    wire [0:0] adapt_scalar_trunc27_in;
    wire [0:0] adapt_scalar_trunc27_q;
    wire [47:0] c_i48_010_q;
    wire [55:0] c_i56_05_q;
    wire [6:0] c_i7_04_q;
    wire [447:0] dsdk_ip_adapt_bitjoin1_q;
    wire [7:0] element_extension3_q;
    wire [7:0] element_extension6_q;
    wire [7:0] element_extension8_q;
    wire [447:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_data;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_stall;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_stall_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_valid;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_almost_empty;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_almost_empty_bitsignaltemp;
    wire [447:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_data;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_empty;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_empty_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_stall;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_stall_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_valid;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_valid_bitsignaltemp;
    wire [0:0] ip_dsdk_adapt_bitselect12_b;
    wire [63:0] ip_dsdk_adapt_bitselect14_b;
    wire [63:0] ip_dsdk_adapt_bitselect16_b;
    wire [63:0] ip_dsdk_adapt_bitselect18_b;
    wire [63:0] ip_dsdk_adapt_bitselect20_b;
    wire [63:0] ip_dsdk_adapt_bitselect22_b;
    wire [0:0] ip_dsdk_adapt_bitselect24_b;
    wire [0:0] ip_dsdk_adapt_bitselect26_b;


    // ip_dsdk_adapt_bitselect26(BITSELECT,24)
    assign ip_dsdk_adapt_bitselect26_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_data[392:392];

    // adapt_scalar_trunc27(ROUND,6)
    assign adapt_scalar_trunc27_in = ip_dsdk_adapt_bitselect26_b;
    assign adapt_scalar_trunc27_q = adapt_scalar_trunc27_in[0:0];

    // ip_dsdk_adapt_bitselect24(BITSELECT,23)
    assign ip_dsdk_adapt_bitselect24_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_data[384:384];

    // adapt_scalar_trunc25(ROUND,5)
    assign adapt_scalar_trunc25_in = ip_dsdk_adapt_bitselect24_b;
    assign adapt_scalar_trunc25_q = adapt_scalar_trunc25_in[0:0];

    // ip_dsdk_adapt_bitselect22(BITSELECT,22)
    assign ip_dsdk_adapt_bitselect22_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_data[383:320];

    // ip_dsdk_adapt_bitselect20(BITSELECT,21)
    assign ip_dsdk_adapt_bitselect20_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_data[319:256];

    // ip_dsdk_adapt_bitselect18(BITSELECT,20)
    assign ip_dsdk_adapt_bitselect18_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_data[255:192];

    // ip_dsdk_adapt_bitselect16(BITSELECT,19)
    assign ip_dsdk_adapt_bitselect16_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_data[191:128];

    // ip_dsdk_adapt_bitselect14(BITSELECT,18)
    assign ip_dsdk_adapt_bitselect14_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_data[127:64];

    // ip_dsdk_adapt_bitselect12(BITSELECT,17)
    assign ip_dsdk_adapt_bitselect12_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_data[0:0];

    // adapt_scalar_trunc13(ROUND,4)
    assign adapt_scalar_trunc13_in = ip_dsdk_adapt_bitselect12_b;
    assign adapt_scalar_trunc13_q = adapt_scalar_trunc13_in[0:0];

    // c_i48_010(CONSTANT,7)
    assign c_i48_010_q = $unsigned(48'b000000000000000000000000000000000000000000000000);

    // c_i7_04(CONSTANT,9)
    assign c_i7_04_q = $unsigned(7'b0000000);

    // element_extension8(BITJOIN,15)
    assign element_extension8_q = {c_i7_04_q, in_i_data_7_tpl};

    // element_extension6(BITJOIN,14)
    assign element_extension6_q = {c_i7_04_q, in_i_data_6_tpl};

    // c_i56_05(CONSTANT,8)
    assign c_i56_05_q = $unsigned(56'b00000000000000000000000000000000000000000000000000000000);

    // element_extension3(BITJOIN,13)
    assign element_extension3_q = {c_i7_04_q, in_i_data_0_tpl};

    // dsdk_ip_adapt_bitjoin1(BITJOIN,12)
    assign dsdk_ip_adapt_bitjoin1_q = {c_i48_010_q, element_extension8_q, element_extension6_q, in_i_data_5_tpl, in_i_data_4_tpl, in_i_data_3_tpl, in_i_data_2_tpl, in_i_data_1_tpl, c_i56_05_q, element_extension3_q};

    // i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0(EXTIFACE,16)
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_data = dsdk_ip_adapt_bitjoin1_q;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_stall = in_i_stall;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_valid = in_i_valid;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_stall_bitsignaltemp = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_stall[0];
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_valid_bitsignaltemp = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_valid[0];
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_almost_empty[0] = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_almost_empty_bitsignaltemp;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_empty[0] = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_empty_bitsignaltemp;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_stall[0] = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_stall_bitsignaltemp;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_valid[0] = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_valid_bitsignaltemp;
    hld_fifo #(
        .ALMOST_EMPTY_CUTOFF(7),
        .DEPTH(512),
        .STYLE("ms"),
        .ASYNC_RESET(0),
        .NEVER_OVERFLOWS(1),
        .RESET_EXTERNALLY_HELD(1),
        .STALL_IN_EARLINESS(3),
        .SYNCHRONIZE_RESET(0),
        .USE_STALL_LATENCY_DOWNSTREAM(1),
        .USE_STALL_LATENCY_UPSTREAM(1),
        .WIDTH(448)
    ) thei_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0 (
        .i_data(dsdk_ip_adapt_bitjoin1_q),
        .i_stall(i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_stall_bitsignaltemp),
        .i_valid(i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_i_valid_bitsignaltemp),
        .o_almost_empty(i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_almost_empty_bitsignaltemp),
        .o_data(i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_data),
        .o_empty(i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_empty_bitsignaltemp),
        .o_stall(i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_stall_bitsignaltemp),
        .o_valid(i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_valid_bitsignaltemp),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_sync_out_aunroll_x(GPOUT,2)@20000000
    assign out_o_almost_empty = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_almost_empty;
    assign out_o_data_0_tpl = adapt_scalar_trunc13_q;
    assign out_o_data_1_tpl = ip_dsdk_adapt_bitselect14_b;
    assign out_o_data_2_tpl = ip_dsdk_adapt_bitselect16_b;
    assign out_o_data_3_tpl = ip_dsdk_adapt_bitselect18_b;
    assign out_o_data_4_tpl = ip_dsdk_adapt_bitselect20_b;
    assign out_o_data_5_tpl = ip_dsdk_adapt_bitselect22_b;
    assign out_o_data_6_tpl = adapt_scalar_trunc25_q;
    assign out_o_data_7_tpl = adapt_scalar_trunc27_q;
    assign out_o_empty = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_empty;
    assign out_o_valid = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_valid;

    // sync_out(GPOUT,31)@20000000
    assign out_o_stall = i_llvm_fpga_sfc_exit_s_c0_out_for_body_c_compmm_ms_c0_exit920_c_compmm_m0_o_stall;

endmodule
