// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
// Legal Notice: Copyright 2022 Intel Corporation.  All rights reserved.
// Your use of  Intel Corporation's design tools,  logic functions and other
// software and  tools, and its AMPP partner logic functions, and any output
// files any  of the foregoing (including  device programming  or simulation
// files), and  any associated  documentation  or information  are expressly
// subject  to the terms and  conditions of the  Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement,  including,  without limitation,  that your use is for
// the  sole  purpose of  programming  logic devices  manufactured by  Intel
// and  sold by Intel  or its authorized  distributors. Please refer  to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------

// SystemVerilog created from bb_c_compMM_m_B3_stall_region
// Created for function/kernel c_compMM_m
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compMM_m_bb_B3_stall_region (
    input wire [1023:0] in_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_readdata,
    input wire [0:0] in_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_writeack,
    input wire [0:0] in_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_waitrequest,
    input wire [0:0] in_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_readdatavalid,
    output wire [9:0] out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_address,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_enable,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_read,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_write,
    output wire [1023:0] out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_writedata,
    output wire [127:0] out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_byteenable,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_burstcount,
    output wire [0:0] out_almost_empty_out,
    output wire [0:0] out_c0_exe7,
    output wire [0:0] out_empty_out,
    output wire [0:0] out_profile_loop_o_valid,
    output wire [0:0] out_valid_out,
    input wire [1023:0] in_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_readdata,
    input wire [0:0] in_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_writeack,
    input wire [0:0] in_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_waitrequest,
    input wire [0:0] in_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_readdatavalid,
    output wire [9:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_address,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_enable,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_read,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_write,
    output wire [1023:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_writedata,
    output wire [127:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_byteenable,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_burstcount,
    input wire [1023:0] in_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_readdata,
    input wire [0:0] in_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_writeack,
    input wire [0:0] in_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_waitrequest,
    input wire [0:0] in_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_readdatavalid,
    output wire [9:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_address,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_enable,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_read,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_write,
    output wire [1023:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_writedata,
    output wire [127:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_byteenable,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_burstcount,
    input wire [511:0] in_memdep_17_c_compMM_m_avm_readdata,
    input wire [0:0] in_memdep_17_c_compMM_m_avm_writeack,
    input wire [0:0] in_memdep_17_c_compMM_m_avm_waitrequest,
    input wire [0:0] in_memdep_17_c_compMM_m_avm_readdatavalid,
    output wire [3:0] out_memdep_17_c_compMM_m_avm_address,
    output wire [0:0] out_memdep_17_c_compMM_m_avm_enable,
    output wire [0:0] out_memdep_17_c_compMM_m_avm_read,
    output wire [0:0] out_memdep_17_c_compMM_m_avm_write,
    output wire [511:0] out_memdep_17_c_compMM_m_avm_writedata,
    output wire [63:0] out_memdep_17_c_compMM_m_avm_byteenable,
    output wire [0:0] out_memdep_17_c_compMM_m_avm_burstcount,
    output wire [0:0] out_lsu_memdep_17_o_active,
    input wire [1023:0] in_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_readdata,
    input wire [0:0] in_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_writeack,
    input wire [0:0] in_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_waitrequest,
    input wire [0:0] in_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_readdatavalid,
    output wire [9:0] out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_address,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_enable,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_read,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_write,
    output wire [1023:0] out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_writedata,
    output wire [127:0] out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_byteenable,
    output wire [0:0] out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_burstcount,
    input wire [15:0] in_intel_reserved_ffwd_173_0,
    input wire [15:0] in_intel_reserved_ffwd_174_0,
    input wire [15:0] in_intel_reserved_ffwd_175_0,
    input wire [15:0] in_intel_reserved_ffwd_176_0,
    input wire [15:0] in_intel_reserved_ffwd_177_0,
    input wire [15:0] in_intel_reserved_ffwd_178_0,
    input wire [15:0] in_intel_reserved_ffwd_179_0,
    input wire [15:0] in_intel_reserved_ffwd_17_0,
    input wire [15:0] in_intel_reserved_ffwd_180_0,
    input wire [15:0] in_intel_reserved_ffwd_181_0,
    input wire [15:0] in_intel_reserved_ffwd_182_0,
    input wire [15:0] in_intel_reserved_ffwd_183_0,
    input wire [15:0] in_intel_reserved_ffwd_184_0,
    input wire [15:0] in_intel_reserved_ffwd_185_0,
    input wire [15:0] in_intel_reserved_ffwd_186_0,
    input wire [15:0] in_intel_reserved_ffwd_187_0,
    input wire [15:0] in_intel_reserved_ffwd_188_0,
    input wire [15:0] in_intel_reserved_ffwd_189_0,
    input wire [15:0] in_intel_reserved_ffwd_18_0,
    input wire [15:0] in_intel_reserved_ffwd_190_0,
    input wire [15:0] in_intel_reserved_ffwd_191_0,
    input wire [15:0] in_intel_reserved_ffwd_192_0,
    input wire [15:0] in_intel_reserved_ffwd_193_0,
    input wire [15:0] in_intel_reserved_ffwd_194_0,
    input wire [15:0] in_intel_reserved_ffwd_195_0,
    input wire [15:0] in_intel_reserved_ffwd_196_0,
    input wire [15:0] in_intel_reserved_ffwd_197_0,
    input wire [15:0] in_intel_reserved_ffwd_198_0,
    input wire [15:0] in_intel_reserved_ffwd_199_0,
    input wire [15:0] in_intel_reserved_ffwd_19_0,
    input wire [15:0] in_intel_reserved_ffwd_1_0,
    input wire [15:0] in_intel_reserved_ffwd_200_0,
    input wire [15:0] in_intel_reserved_ffwd_201_0,
    input wire [15:0] in_intel_reserved_ffwd_202_0,
    input wire [15:0] in_intel_reserved_ffwd_203_0,
    input wire [15:0] in_intel_reserved_ffwd_204_0,
    input wire [15:0] in_intel_reserved_ffwd_205_0,
    input wire [15:0] in_intel_reserved_ffwd_206_0,
    input wire [15:0] in_intel_reserved_ffwd_207_0,
    input wire [15:0] in_intel_reserved_ffwd_208_0,
    input wire [15:0] in_intel_reserved_ffwd_209_0,
    input wire [15:0] in_intel_reserved_ffwd_20_0,
    input wire [15:0] in_intel_reserved_ffwd_210_0,
    input wire [15:0] in_intel_reserved_ffwd_211_0,
    input wire [15:0] in_intel_reserved_ffwd_212_0,
    input wire [15:0] in_intel_reserved_ffwd_213_0,
    input wire [15:0] in_intel_reserved_ffwd_214_0,
    input wire [15:0] in_intel_reserved_ffwd_215_0,
    input wire [15:0] in_intel_reserved_ffwd_216_0,
    input wire [15:0] in_intel_reserved_ffwd_217_0,
    input wire [15:0] in_intel_reserved_ffwd_218_0,
    input wire [15:0] in_intel_reserved_ffwd_219_0,
    input wire [15:0] in_intel_reserved_ffwd_21_0,
    input wire [15:0] in_intel_reserved_ffwd_220_0,
    input wire [15:0] in_intel_reserved_ffwd_221_0,
    input wire [15:0] in_intel_reserved_ffwd_222_0,
    input wire [15:0] in_intel_reserved_ffwd_223_0,
    input wire [15:0] in_intel_reserved_ffwd_224_0,
    input wire [15:0] in_intel_reserved_ffwd_225_0,
    input wire [15:0] in_intel_reserved_ffwd_226_0,
    input wire [15:0] in_intel_reserved_ffwd_227_0,
    input wire [15:0] in_intel_reserved_ffwd_228_0,
    input wire [15:0] in_intel_reserved_ffwd_229_0,
    input wire [15:0] in_intel_reserved_ffwd_22_0,
    input wire [15:0] in_intel_reserved_ffwd_230_0,
    input wire [15:0] in_intel_reserved_ffwd_231_0,
    input wire [15:0] in_intel_reserved_ffwd_232_0,
    input wire [15:0] in_intel_reserved_ffwd_233_0,
    input wire [15:0] in_intel_reserved_ffwd_234_0,
    input wire [15:0] in_intel_reserved_ffwd_235_0,
    input wire [15:0] in_intel_reserved_ffwd_236_0,
    input wire [15:0] in_intel_reserved_ffwd_237_0,
    input wire [15:0] in_intel_reserved_ffwd_238_0,
    input wire [15:0] in_intel_reserved_ffwd_239_0,
    input wire [15:0] in_intel_reserved_ffwd_23_0,
    input wire [15:0] in_intel_reserved_ffwd_240_0,
    input wire [15:0] in_intel_reserved_ffwd_241_0,
    input wire [15:0] in_intel_reserved_ffwd_242_0,
    input wire [15:0] in_intel_reserved_ffwd_243_0,
    input wire [15:0] in_intel_reserved_ffwd_244_0,
    input wire [0:0] in_flush,
    input wire [15:0] in_intel_reserved_ffwd_245_0,
    input wire [15:0] in_intel_reserved_ffwd_246_0,
    input wire [15:0] in_intel_reserved_ffwd_247_0,
    input wire [15:0] in_intel_reserved_ffwd_248_0,
    input wire [15:0] in_intel_reserved_ffwd_249_0,
    input wire [15:0] in_intel_reserved_ffwd_24_0,
    input wire [15:0] in_intel_reserved_ffwd_250_0,
    input wire [15:0] in_intel_reserved_ffwd_251_0,
    input wire [15:0] in_intel_reserved_ffwd_252_0,
    input wire [15:0] in_intel_reserved_ffwd_253_0,
    input wire [63:0] in_intel_reserved_ffwd_0_0,
    input wire [15:0] in_intel_reserved_ffwd_254_0,
    input wire [15:0] in_intel_reserved_ffwd_255_0,
    input wire [15:0] in_intel_reserved_ffwd_256_0,
    input wire [63:0] in_intel_reserved_ffwd_257_0,
    input wire [15:0] in_intel_reserved_ffwd_25_0,
    input wire [15:0] in_intel_reserved_ffwd_26_0,
    input wire [15:0] in_intel_reserved_ffwd_27_0,
    input wire [15:0] in_intel_reserved_ffwd_28_0,
    input wire [15:0] in_intel_reserved_ffwd_29_0,
    input wire [15:0] in_intel_reserved_ffwd_2_0,
    input wire [15:0] in_intel_reserved_ffwd_100_0,
    input wire [15:0] in_intel_reserved_ffwd_30_0,
    input wire [15:0] in_intel_reserved_ffwd_31_0,
    input wire [15:0] in_intel_reserved_ffwd_32_0,
    input wire [15:0] in_intel_reserved_ffwd_33_0,
    input wire [15:0] in_intel_reserved_ffwd_34_0,
    input wire [15:0] in_intel_reserved_ffwd_35_0,
    input wire [15:0] in_intel_reserved_ffwd_36_0,
    input wire [15:0] in_intel_reserved_ffwd_37_0,
    input wire [15:0] in_intel_reserved_ffwd_38_0,
    input wire [15:0] in_intel_reserved_ffwd_39_0,
    input wire [15:0] in_intel_reserved_ffwd_101_0,
    input wire [15:0] in_intel_reserved_ffwd_3_0,
    input wire [15:0] in_intel_reserved_ffwd_40_0,
    input wire [15:0] in_intel_reserved_ffwd_41_0,
    input wire [15:0] in_intel_reserved_ffwd_42_0,
    input wire [15:0] in_intel_reserved_ffwd_43_0,
    input wire [15:0] in_intel_reserved_ffwd_44_0,
    input wire [15:0] in_intel_reserved_ffwd_45_0,
    input wire [15:0] in_intel_reserved_ffwd_46_0,
    input wire [15:0] in_intel_reserved_ffwd_47_0,
    input wire [15:0] in_intel_reserved_ffwd_48_0,
    input wire [15:0] in_intel_reserved_ffwd_102_0,
    input wire [15:0] in_intel_reserved_ffwd_49_0,
    input wire [15:0] in_intel_reserved_ffwd_4_0,
    input wire [15:0] in_intel_reserved_ffwd_50_0,
    input wire [15:0] in_intel_reserved_ffwd_51_0,
    input wire [15:0] in_intel_reserved_ffwd_52_0,
    input wire [15:0] in_intel_reserved_ffwd_53_0,
    input wire [15:0] in_intel_reserved_ffwd_54_0,
    input wire [15:0] in_intel_reserved_ffwd_55_0,
    input wire [15:0] in_intel_reserved_ffwd_56_0,
    input wire [15:0] in_intel_reserved_ffwd_57_0,
    input wire [15:0] in_intel_reserved_ffwd_103_0,
    input wire [15:0] in_intel_reserved_ffwd_58_0,
    input wire [15:0] in_intel_reserved_ffwd_59_0,
    input wire [15:0] in_intel_reserved_ffwd_5_0,
    input wire [15:0] in_intel_reserved_ffwd_60_0,
    input wire [15:0] in_intel_reserved_ffwd_61_0,
    input wire [15:0] in_intel_reserved_ffwd_62_0,
    input wire [15:0] in_intel_reserved_ffwd_63_0,
    input wire [15:0] in_intel_reserved_ffwd_64_0,
    input wire [15:0] in_intel_reserved_ffwd_65_0,
    input wire [15:0] in_intel_reserved_ffwd_66_0,
    input wire [15:0] in_intel_reserved_ffwd_104_0,
    input wire [15:0] in_intel_reserved_ffwd_67_0,
    input wire [15:0] in_intel_reserved_ffwd_68_0,
    input wire [15:0] in_intel_reserved_ffwd_69_0,
    input wire [15:0] in_intel_reserved_ffwd_6_0,
    input wire [15:0] in_intel_reserved_ffwd_70_0,
    input wire [15:0] in_intel_reserved_ffwd_71_0,
    input wire [15:0] in_intel_reserved_ffwd_72_0,
    input wire [15:0] in_intel_reserved_ffwd_73_0,
    input wire [15:0] in_intel_reserved_ffwd_74_0,
    input wire [15:0] in_intel_reserved_ffwd_75_0,
    input wire [15:0] in_intel_reserved_ffwd_105_0,
    input wire [15:0] in_intel_reserved_ffwd_76_0,
    input wire [15:0] in_intel_reserved_ffwd_77_0,
    input wire [15:0] in_intel_reserved_ffwd_78_0,
    input wire [15:0] in_intel_reserved_ffwd_79_0,
    input wire [15:0] in_intel_reserved_ffwd_7_0,
    input wire [15:0] in_intel_reserved_ffwd_80_0,
    input wire [15:0] in_intel_reserved_ffwd_81_0,
    input wire [15:0] in_intel_reserved_ffwd_82_0,
    input wire [15:0] in_intel_reserved_ffwd_83_0,
    input wire [15:0] in_intel_reserved_ffwd_84_0,
    input wire [15:0] in_intel_reserved_ffwd_106_0,
    input wire [15:0] in_intel_reserved_ffwd_85_0,
    input wire [15:0] in_intel_reserved_ffwd_86_0,
    input wire [15:0] in_intel_reserved_ffwd_87_0,
    input wire [15:0] in_intel_reserved_ffwd_88_0,
    input wire [15:0] in_intel_reserved_ffwd_89_0,
    input wire [15:0] in_intel_reserved_ffwd_8_0,
    input wire [15:0] in_intel_reserved_ffwd_90_0,
    input wire [15:0] in_intel_reserved_ffwd_91_0,
    input wire [15:0] in_intel_reserved_ffwd_92_0,
    input wire [15:0] in_intel_reserved_ffwd_93_0,
    input wire [15:0] in_intel_reserved_ffwd_107_0,
    input wire [15:0] in_intel_reserved_ffwd_94_0,
    input wire [15:0] in_intel_reserved_ffwd_95_0,
    input wire [15:0] in_intel_reserved_ffwd_96_0,
    input wire [15:0] in_intel_reserved_ffwd_97_0,
    input wire [15:0] in_intel_reserved_ffwd_98_0,
    input wire [15:0] in_intel_reserved_ffwd_99_0,
    input wire [15:0] in_intel_reserved_ffwd_9_0,
    input wire [15:0] in_intel_reserved_ffwd_108_0,
    input wire [15:0] in_intel_reserved_ffwd_109_0,
    input wire [15:0] in_intel_reserved_ffwd_10_0,
    input wire [15:0] in_intel_reserved_ffwd_110_0,
    input wire [15:0] in_intel_reserved_ffwd_111_0,
    input wire [15:0] in_intel_reserved_ffwd_112_0,
    input wire [15:0] in_intel_reserved_ffwd_113_0,
    input wire [15:0] in_intel_reserved_ffwd_114_0,
    input wire [15:0] in_intel_reserved_ffwd_115_0,
    input wire [15:0] in_intel_reserved_ffwd_116_0,
    input wire [15:0] in_intel_reserved_ffwd_117_0,
    input wire [15:0] in_intel_reserved_ffwd_118_0,
    input wire [15:0] in_intel_reserved_ffwd_119_0,
    input wire [15:0] in_intel_reserved_ffwd_11_0,
    input wire [15:0] in_intel_reserved_ffwd_120_0,
    input wire [15:0] in_intel_reserved_ffwd_121_0,
    input wire [15:0] in_intel_reserved_ffwd_122_0,
    input wire [15:0] in_intel_reserved_ffwd_123_0,
    input wire [15:0] in_intel_reserved_ffwd_124_0,
    input wire [15:0] in_intel_reserved_ffwd_125_0,
    input wire [15:0] in_intel_reserved_ffwd_126_0,
    input wire [15:0] in_intel_reserved_ffwd_127_0,
    input wire [15:0] in_intel_reserved_ffwd_128_0,
    input wire [15:0] in_intel_reserved_ffwd_129_0,
    input wire [15:0] in_intel_reserved_ffwd_12_0,
    input wire [15:0] in_intel_reserved_ffwd_130_0,
    input wire [15:0] in_intel_reserved_ffwd_131_0,
    input wire [15:0] in_intel_reserved_ffwd_132_0,
    input wire [15:0] in_intel_reserved_ffwd_133_0,
    input wire [15:0] in_intel_reserved_ffwd_134_0,
    input wire [15:0] in_intel_reserved_ffwd_135_0,
    input wire [15:0] in_intel_reserved_ffwd_136_0,
    input wire [15:0] in_intel_reserved_ffwd_137_0,
    input wire [15:0] in_intel_reserved_ffwd_138_0,
    input wire [15:0] in_intel_reserved_ffwd_139_0,
    input wire [15:0] in_intel_reserved_ffwd_13_0,
    input wire [15:0] in_intel_reserved_ffwd_140_0,
    input wire [15:0] in_intel_reserved_ffwd_141_0,
    input wire [15:0] in_intel_reserved_ffwd_142_0,
    input wire [15:0] in_intel_reserved_ffwd_143_0,
    input wire [15:0] in_intel_reserved_ffwd_144_0,
    input wire [15:0] in_intel_reserved_ffwd_145_0,
    input wire [15:0] in_intel_reserved_ffwd_146_0,
    input wire [15:0] in_intel_reserved_ffwd_147_0,
    input wire [15:0] in_intel_reserved_ffwd_148_0,
    input wire [15:0] in_intel_reserved_ffwd_149_0,
    input wire [15:0] in_intel_reserved_ffwd_14_0,
    input wire [15:0] in_intel_reserved_ffwd_150_0,
    input wire [15:0] in_intel_reserved_ffwd_151_0,
    input wire [15:0] in_intel_reserved_ffwd_152_0,
    input wire [15:0] in_intel_reserved_ffwd_153_0,
    input wire [15:0] in_intel_reserved_ffwd_154_0,
    input wire [15:0] in_intel_reserved_ffwd_155_0,
    input wire [15:0] in_intel_reserved_ffwd_156_0,
    input wire [15:0] in_intel_reserved_ffwd_157_0,
    input wire [15:0] in_intel_reserved_ffwd_158_0,
    input wire [15:0] in_intel_reserved_ffwd_159_0,
    input wire [15:0] in_intel_reserved_ffwd_15_0,
    input wire [15:0] in_intel_reserved_ffwd_160_0,
    input wire [15:0] in_intel_reserved_ffwd_161_0,
    input wire [15:0] in_intel_reserved_ffwd_162_0,
    input wire [15:0] in_intel_reserved_ffwd_163_0,
    input wire [15:0] in_intel_reserved_ffwd_164_0,
    input wire [15:0] in_intel_reserved_ffwd_165_0,
    input wire [15:0] in_intel_reserved_ffwd_166_0,
    input wire [15:0] in_intel_reserved_ffwd_167_0,
    input wire [15:0] in_intel_reserved_ffwd_168_0,
    input wire [15:0] in_intel_reserved_ffwd_169_0,
    input wire [15:0] in_intel_reserved_ffwd_16_0,
    input wire [15:0] in_intel_reserved_ffwd_170_0,
    input wire [15:0] in_intel_reserved_ffwd_171_0,
    input wire [15:0] in_intel_reserved_ffwd_172_0,
    input wire [0:0] in_stall_in,
    output wire [0:0] out_stall_out,
    input wire [0:0] in_almost_empty_in,
    input wire [0:0] in_empty_in,
    input wire [0:0] in_valid_in,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_0_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_1_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_2_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_3_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_4_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_5_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_6_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_7_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_8_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_9_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_10_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_11_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_12_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_13_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_14_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_15_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_16_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_17_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_18_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_19_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_20_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_21_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_22_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_23_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_24_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_25_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_26_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_27_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_28_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_29_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_30_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_31_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_32_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_33_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_34_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_35_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_36_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_37_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_38_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_39_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_40_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_41_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_42_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_43_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_44_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_45_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_46_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_47_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_48_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_49_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_50_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_51_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_52_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_53_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_54_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_55_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_56_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_57_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_58_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_59_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_60_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_61_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_62_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_63_tpl;
    wire [9:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_address;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_burstcount;
    wire [127:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_byteenable;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_enable;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_read;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_write;
    wire [1023:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_writedata;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_almost_empty;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_empty;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_stall;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_valid;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_0_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_1_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_2_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_3_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_4_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_5_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_6_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_7_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_8_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_9_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_10_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_11_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_12_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_13_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_14_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_15_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_16_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_17_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_18_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_19_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_20_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_21_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_22_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_23_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_24_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_25_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_26_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_27_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_28_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_29_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_30_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_31_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_32_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_33_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_34_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_35_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_36_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_37_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_38_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_39_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_40_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_41_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_42_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_43_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_44_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_45_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_46_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_47_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_48_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_49_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_50_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_51_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_52_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_53_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_54_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_55_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_56_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_57_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_58_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_59_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_60_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_61_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_62_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_63_tpl;
    wire [9:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_address;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_burstcount;
    wire [127:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_byteenable;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_enable;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_read;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_write;
    wire [1023:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_writedata;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_almost_empty;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_empty;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_stall;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_valid;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_0_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_1_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_2_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_3_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_4_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_5_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_6_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_7_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_8_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_9_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_10_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_11_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_12_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_13_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_14_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_15_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_16_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_17_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_18_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_19_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_20_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_21_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_22_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_23_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_24_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_25_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_26_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_27_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_28_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_29_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_30_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_31_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_32_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_33_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_34_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_35_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_36_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_37_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_38_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_39_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_40_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_41_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_42_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_43_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_44_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_45_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_46_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_47_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_48_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_49_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_50_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_51_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_52_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_53_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_54_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_55_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_56_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_57_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_58_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_59_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_60_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_61_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_62_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_63_tpl;
    wire [9:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_address;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_burstcount;
    wire [127:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_byteenable;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_enable;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_read;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_write;
    wire [1023:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_writedata;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_almost_empty;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_empty;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_stall;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_valid;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_0_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_1_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_2_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_3_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_4_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_5_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_6_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_7_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_8_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_9_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_10_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_11_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_12_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_13_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_14_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_15_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_16_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_17_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_18_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_19_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_20_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_21_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_22_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_23_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_24_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_25_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_26_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_27_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_28_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_29_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_30_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_31_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_32_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_33_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_34_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_35_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_36_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_37_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_38_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_39_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_40_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_41_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_42_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_43_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_44_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_45_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_46_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_47_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_48_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_49_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_50_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_51_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_52_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_53_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_54_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_55_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_56_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_57_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_58_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_59_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_60_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_61_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_62_tpl;
    wire [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_63_tpl;
    wire [9:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_address;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_burstcount;
    wire [127:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_byteenable;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_enable;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_read;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_write;
    wire [1023:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_writedata;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_almost_empty;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_empty;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_stall;
    wire [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_valid;
    wire [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_lsu_memdep_17_o_active;
    wire [3:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_address;
    wire [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_burstcount;
    wire [63:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_byteenable;
    wire [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_enable;
    wire [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_read;
    wire [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_write;
    wire [511:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_writedata;
    wire [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_almost_empty;
    wire [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_empty;
    wire [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_stall;
    wire [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_valid;
    wire [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_1_tpl;
    wire [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_2_tpl;
    wire [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_3_tpl;
    wire [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_4_tpl;
    wire [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl;
    wire [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_7_tpl;
    wire [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_almost_empty_out;
    wire [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_empty_out;
    wire [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_stall;
    wire [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_valid;
    wire [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_profile_loop_o_valid;
    wire [63:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_1_tpl;
    wire [15:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_2_tpl;
    wire [15:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_3_tpl;
    wire [0:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_almost_empty_out;
    wire [0:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_empty_out;
    wire [0:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_stall;
    wire [0:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_valid;
    wire [1:0] join_for_coalesced_delay_0_q;
    wire [0:0] sel_for_coalesced_delay_0_b;
    wire [0:0] sel_for_coalesced_delay_0_c;
    wire [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_valid;
    wire redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_valid_bitsignaltemp;
    wire [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall;
    wire redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall_bitsignaltemp;
    wire [63:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_data;
    wire [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_empty;
    wire redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_empty_bitsignaltemp;
    wire [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_almost_empty;
    wire redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_almost_empty_bitsignaltemp;
    wire [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_valid;
    wire redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_valid_bitsignaltemp;
    wire [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_stall;
    wire redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_stall_bitsignaltemp;
    wire [63:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_data;
    wire [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty;
    wire redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty_bitsignaltemp;
    wire [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty;
    wire redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_i_valid;
    wire coalesced_delay_0_fifo_i_valid_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_i_stall;
    wire coalesced_delay_0_fifo_i_stall_bitsignaltemp;
    wire [1:0] coalesced_delay_0_fifo_i_data;
    wire [0:0] coalesced_delay_0_fifo_i_empty;
    wire coalesced_delay_0_fifo_i_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_i_almost_empty;
    wire coalesced_delay_0_fifo_i_almost_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_o_valid;
    wire coalesced_delay_0_fifo_o_valid_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_o_stall;
    wire coalesced_delay_0_fifo_o_stall_bitsignaltemp;
    wire [1:0] coalesced_delay_0_fifo_o_data;
    wire [0:0] coalesced_delay_0_fifo_o_empty;
    wire coalesced_delay_0_fifo_o_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_o_almost_empty;
    wire coalesced_delay_0_fifo_o_almost_empty_bitsignaltemp;
    wire [1023:0] bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_b;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_c;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_d;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_e;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_f;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_g;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_h;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_i;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_j;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_k;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_l;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_m;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_n;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_o;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_p;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_r;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_s;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_t;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_u;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_v;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_w;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_x;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_y;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_z;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_aa;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_bb;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_cc;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_dd;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ee;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ff;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_gg;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_hh;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ii;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_jj;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_kk;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ll;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_mm;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_nn;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_oo;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_pp;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_qq;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_rr;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ss;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_tt;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_uu;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_vv;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ww;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_xx;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_yy;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_zz;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_1;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_2;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_3;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_4;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_5;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_6;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_7;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_8;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_9;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_0;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_o61;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_o62;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_o63;
    wire [1023:0] bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_b;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_c;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_d;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_e;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_f;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_g;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_h;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_i;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_j;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_k;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_l;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_m;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_n;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_o;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_p;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_r;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_s;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_t;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_u;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_v;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_w;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_x;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_y;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_z;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_aa;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_bb;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_cc;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_dd;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ee;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ff;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_gg;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_hh;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ii;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_jj;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_kk;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ll;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_mm;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_nn;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_oo;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_pp;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_qq;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_rr;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ss;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_tt;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_uu;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_vv;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ww;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_xx;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_yy;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_zz;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_1;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_2;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_3;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_4;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_5;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_6;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_7;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_8;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_9;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_0;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_o61;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_o62;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_o63;
    wire [1023:0] bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_b;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_c;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_d;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_e;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_f;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_g;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_h;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_i;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_j;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_k;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_l;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_m;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_n;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_o;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_p;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_r;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_s;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_t;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_u;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_v;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_w;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_x;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_y;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_z;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_aa;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_bb;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_cc;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_dd;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ee;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ff;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_gg;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_hh;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ii;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_jj;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_kk;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ll;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_mm;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_nn;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_oo;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_pp;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_qq;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_rr;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ss;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_tt;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_uu;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_vv;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ww;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_xx;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_yy;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_zz;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_1;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_2;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_3;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_4;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_5;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_6;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_7;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_8;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_9;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_0;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_o61;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_o62;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_o63;
    wire [1023:0] bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_b;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_c;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_d;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_e;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_f;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_g;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_h;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_i;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_j;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_k;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_l;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_m;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_n;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_o;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_p;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_r;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_s;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_t;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_u;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_v;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_w;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_x;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_y;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_z;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_aa;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_bb;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_cc;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_dd;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ee;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ff;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_gg;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_hh;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ii;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_jj;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_kk;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ll;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_mm;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_nn;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_oo;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_pp;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_qq;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_rr;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ss;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_tt;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_uu;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_vv;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ww;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_xx;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_yy;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_zz;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_1;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_2;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_3;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_4;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_5;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_6;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_7;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_8;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_9;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_0;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_o61;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_o62;
    wire [15:0] bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_o63;
    wire [321:0] bubble_join_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_q;
    wire [63:0] bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_b;
    wire [63:0] bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_c;
    wire [63:0] bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_d;
    wire [63:0] bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_e;
    wire [63:0] bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_f;
    wire [0:0] bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_g;
    wire [0:0] bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_h;
    wire [95:0] bubble_join_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_q;
    wire [63:0] bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_b;
    wire [15:0] bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_c;
    wire [15:0] bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_d;
    wire [63:0] bubble_join_redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_q;
    wire [63:0] bubble_select_redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_b;
    wire [1:0] bubble_join_coalesced_delay_0_fifo_q;
    wire [1:0] bubble_select_coalesced_delay_0_fifo_b;
    wire [0:0] merged_in_SE_stall_entry_backStall;
    wire [0:0] merged_in_SE_stall_entry_V0;
    wire [0:0] merged_in_SE_stall_entry_V1;
    wire [0:0] merged_in_SE_stall_entry_V2;
    wire [0:0] merged_in_SE_stall_entry_temp_back_stall;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_backStall;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V0;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V6;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V12;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V1;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V7;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V13;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V2;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V8;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V14;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V3;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V9;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V15;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V4;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V10;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V16;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V5;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V11;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V17;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_temp_back_stall;
    wire [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_backStall;
    wire [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0;
    wire [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V1;
    wire [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V2;
    wire [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_can_fast_read;
    wire can_fast_read_bitsignaltemp;
    wire [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_can_slow_read;
    wire can_slow_read_bitsignaltemp;
    wire [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_no_space_for_result;
    wire no_space_for_result_bitsignaltemp;
    wire [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_forced_read;
    wire forced_read_bitsignaltemp;
    wire [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_temp_back_stall;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_0_backStall;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_0_V0;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_0_V1;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_0_V2;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_0_can_fast_read;
    wire can_fast_read_bitsignaltemp_dup_name_0;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_0_can_slow_read;
    wire can_slow_read_bitsignaltemp_dup_name_0;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_0_no_space_for_result;
    wire no_space_for_result_bitsignaltemp_dup_name_0;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_0_forced_read;
    wire forced_read_bitsignaltemp_dup_name_0;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_0_temp_back_stall;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_backStall;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_V0;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_V1;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_V2;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_temp_back_stall;
    reg [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg6_q;
    reg [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg5_q;
    reg [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg4_q;
    reg [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg3_q;
    reg [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg2_q;
    reg [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg1_q;
    reg [0:0] merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg0_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg6_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg5_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg4_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg3_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg2_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg1_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_in_i_stall_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_in_i_stall_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_0_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_0_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_1_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_1_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_2_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_2_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_3_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_3_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_4_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_4_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_5_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_5_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_6_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_6_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_7_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_7_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_8_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_8_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_9_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_9_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_10_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_10_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_11_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_11_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_12_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_12_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_13_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_13_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_14_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_14_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_15_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_15_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_16_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_16_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_17_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_17_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_18_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_18_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_19_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_19_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_20_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_20_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_21_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_21_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_22_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_22_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_23_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_23_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_24_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_24_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_25_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_25_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_26_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_26_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_27_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_27_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_28_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_28_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_29_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_29_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_30_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_30_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_31_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_31_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_32_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_32_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_33_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_33_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_34_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_34_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_35_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_35_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_36_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_36_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_37_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_37_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_38_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_38_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_39_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_39_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_40_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_40_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_41_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_41_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_42_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_42_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_43_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_43_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_44_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_44_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_45_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_45_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_46_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_46_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_47_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_47_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_48_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_48_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_49_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_49_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_50_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_50_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_51_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_51_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_52_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_52_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_53_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_53_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_54_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_54_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_55_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_55_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_56_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_56_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_57_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_57_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_58_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_58_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_59_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_59_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_60_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_60_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_61_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_61_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_62_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_62_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_63_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_63_tpl_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_almost_empty_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_almost_empty_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_empty_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_empty_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_valid_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_valid_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_in_i_stall_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_in_i_stall_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_0_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_0_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_1_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_1_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_2_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_2_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_3_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_3_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_4_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_4_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_5_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_5_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_6_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_6_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_7_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_7_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_8_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_8_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_9_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_9_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_10_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_10_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_11_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_11_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_12_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_12_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_13_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_13_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_14_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_14_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_15_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_15_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_16_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_16_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_17_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_17_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_18_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_18_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_19_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_19_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_20_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_20_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_21_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_21_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_22_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_22_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_23_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_23_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_24_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_24_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_25_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_25_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_26_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_26_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_27_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_27_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_28_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_28_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_29_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_29_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_30_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_30_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_31_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_31_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_32_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_32_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_33_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_33_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_34_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_34_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_35_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_35_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_36_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_36_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_37_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_37_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_38_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_38_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_39_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_39_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_40_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_40_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_41_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_41_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_42_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_42_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_43_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_43_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_44_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_44_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_45_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_45_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_46_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_46_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_47_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_47_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_48_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_48_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_49_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_49_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_50_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_50_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_51_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_51_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_52_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_52_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_53_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_53_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_54_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_54_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_55_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_55_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_56_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_56_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_57_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_57_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_58_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_58_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_59_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_59_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_60_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_60_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_61_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_61_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_62_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_62_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_63_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_63_tpl_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_almost_empty_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_almost_empty_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_empty_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_empty_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_valid_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_valid_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_in_i_stall_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_in_i_stall_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_0_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_0_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_1_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_1_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_2_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_2_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_3_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_3_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_4_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_4_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_5_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_5_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_6_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_6_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_7_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_7_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_8_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_8_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_9_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_9_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_10_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_10_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_11_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_11_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_12_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_12_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_13_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_13_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_14_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_14_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_15_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_15_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_16_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_16_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_17_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_17_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_18_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_18_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_19_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_19_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_20_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_20_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_21_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_21_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_22_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_22_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_23_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_23_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_24_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_24_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_25_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_25_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_26_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_26_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_27_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_27_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_28_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_28_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_29_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_29_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_30_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_30_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_31_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_31_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_32_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_32_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_33_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_33_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_34_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_34_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_35_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_35_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_36_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_36_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_37_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_37_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_38_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_38_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_39_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_39_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_40_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_40_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_41_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_41_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_42_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_42_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_43_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_43_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_44_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_44_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_45_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_45_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_46_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_46_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_47_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_47_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_48_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_48_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_49_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_49_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_50_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_50_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_51_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_51_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_52_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_52_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_53_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_53_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_54_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_54_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_55_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_55_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_56_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_56_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_57_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_57_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_58_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_58_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_59_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_59_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_60_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_60_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_61_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_61_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_62_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_62_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_63_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_63_tpl_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_almost_empty_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_almost_empty_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_empty_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_empty_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_valid_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_valid_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_in_i_stall_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_in_i_stall_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_0_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_0_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_1_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_1_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_2_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_2_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_3_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_3_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_4_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_4_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_5_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_5_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_6_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_6_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_7_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_7_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_8_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_8_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_9_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_9_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_10_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_10_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_11_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_11_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_12_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_12_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_13_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_13_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_14_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_14_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_15_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_15_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_16_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_16_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_17_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_17_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_18_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_18_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_19_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_19_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_20_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_20_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_21_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_21_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_22_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_22_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_23_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_23_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_24_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_24_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_25_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_25_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_26_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_26_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_27_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_27_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_28_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_28_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_29_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_29_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_30_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_30_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_31_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_31_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_32_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_32_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_33_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_33_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_34_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_34_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_35_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_35_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_36_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_36_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_37_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_37_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_38_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_38_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_39_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_39_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_40_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_40_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_41_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_41_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_42_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_42_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_43_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_43_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_44_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_44_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_45_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_45_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_46_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_46_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_47_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_47_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_48_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_48_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_49_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_49_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_50_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_50_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_51_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_51_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_52_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_52_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_53_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_53_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_54_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_54_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_55_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_55_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_56_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_56_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_57_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_57_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_58_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_58_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_59_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_59_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_60_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_60_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_61_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_61_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_62_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_62_tpl_reg0_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_63_tpl_reg1_q;
    reg [15:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_63_tpl_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_almost_empty_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_almost_empty_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_empty_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_empty_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_valid_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_valid_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_in_i_stall_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_in_i_stall_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_almost_empty_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_almost_empty_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_empty_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_empty_reg0_q;
    reg [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_valid_reg1_q;
    reg [0:0] i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_valid_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_in_i_stall_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_in_i_stall_reg1_q;
    reg [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_1_tpl_reg1_q;
    reg [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_1_tpl_reg0_q;
    reg [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_2_tpl_reg1_q;
    reg [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_2_tpl_reg0_q;
    reg [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_3_tpl_reg1_q;
    reg [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_3_tpl_reg0_q;
    reg [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_4_tpl_reg1_q;
    reg [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_4_tpl_reg0_q;
    reg [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_reg1_q;
    reg [63:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_7_tpl_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_7_tpl_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_almost_empty_out_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_almost_empty_out_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_empty_out_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_empty_out_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_valid_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_valid_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_profile_loop_o_valid_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_profile_loop_o_valid_reg0_q;
    reg [0:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_in_i_stall_reg0_q;
    reg [0:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_in_i_stall_reg1_q;
    reg [63:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_1_tpl_reg1_q;
    reg [63:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_1_tpl_reg0_q;
    reg [15:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_2_tpl_reg1_q;
    reg [15:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_2_tpl_reg0_q;
    reg [15:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_3_tpl_reg1_q;
    reg [15:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_3_tpl_reg0_q;
    reg [0:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_almost_empty_out_reg1_q;
    reg [0:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_almost_empty_out_reg0_q;
    reg [0:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_empty_out_reg1_q;
    reg [0:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_empty_out_reg0_q;
    reg [0:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_valid_reg1_q;
    reg [0:0] i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_valid_reg0_q;
    reg [0:0] stall_entry_frontStall_reg0_q;
    reg [0:0] stall_entry_frontStall_reg1_q;
    reg [0:0] stall_entry_frontValid_reg1_q;
    reg [0:0] stall_entry_frontValid_reg0_q;
    reg [0:0] stall_entry_frontEmpty_reg1_q;
    reg [0:0] stall_entry_frontEmpty_reg0_q;
    reg [0:0] stall_entry_frontAlmostEmpty_reg1_q;
    reg [0:0] stall_entry_frontAlmostEmpty_reg0_q;
    reg [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall_reg0_q;
    reg [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall_reg1_q;
    reg [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_valid_reg1_q;
    reg [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_valid_reg0_q;
    reg [63:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_data_reg1_q;
    reg [63:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_data_reg0_q;
    reg [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty_reg1_q;
    reg [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty_reg0_q;
    reg [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty_reg1_q;
    reg [0:0] redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty_reg0_q;
    reg [0:0] coalesced_delay_0_fifo_i_stall_reg0_q;
    reg [0:0] coalesced_delay_0_fifo_i_stall_reg1_q;
    reg [0:0] coalesced_delay_0_fifo_o_valid_reg1_q;
    reg [0:0] coalesced_delay_0_fifo_o_valid_reg0_q;
    reg [1:0] coalesced_delay_0_fifo_o_data_reg1_q;
    reg [1:0] coalesced_delay_0_fifo_o_data_reg0_q;
    reg [0:0] coalesced_delay_0_fifo_o_empty_reg1_q;
    reg [0:0] coalesced_delay_0_fifo_o_empty_reg0_q;
    reg [0:0] coalesced_delay_0_fifo_o_almost_empty_reg1_q;
    reg [0:0] coalesced_delay_0_fifo_o_almost_empty_reg0_q;
    reg [0:0] rst_sync_rst_sclrn;


    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_almost_empty_reg0(REG,681)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_almost_empty_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_almost_empty);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_almost_empty_reg1(REG,680)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_almost_empty_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_almost_empty_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_in_i_stall_reg0(REG,686)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_in_i_stall_reg0_q <= $unsigned(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_backStall);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_in_i_stall_reg1(REG,687)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_in_i_stall_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_in_i_stall_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x(BLACKBOX,14)@37
    // in in_i_stall@20000000
    // out out_o_readdata_0_tpl@68
    // out out_o_readdata_1_tpl@68
    // out out_o_readdata_2_tpl@68
    // out out_o_readdata_3_tpl@68
    // out out_o_readdata_4_tpl@68
    // out out_o_readdata_5_tpl@68
    // out out_o_readdata_6_tpl@68
    // out out_o_readdata_7_tpl@68
    // out out_o_readdata_8_tpl@68
    // out out_o_readdata_9_tpl@68
    // out out_o_readdata_10_tpl@68
    // out out_o_readdata_11_tpl@68
    // out out_o_readdata_12_tpl@68
    // out out_o_readdata_13_tpl@68
    // out out_o_readdata_14_tpl@68
    // out out_o_readdata_15_tpl@68
    // out out_o_readdata_16_tpl@68
    // out out_o_readdata_17_tpl@68
    // out out_o_readdata_18_tpl@68
    // out out_o_readdata_19_tpl@68
    // out out_o_readdata_20_tpl@68
    // out out_o_readdata_21_tpl@68
    // out out_o_readdata_22_tpl@68
    // out out_o_readdata_23_tpl@68
    // out out_o_readdata_24_tpl@68
    // out out_o_readdata_25_tpl@68
    // out out_o_readdata_26_tpl@68
    // out out_o_readdata_27_tpl@68
    // out out_o_readdata_28_tpl@68
    // out out_o_readdata_29_tpl@68
    // out out_o_readdata_30_tpl@68
    // out out_o_readdata_31_tpl@68
    // out out_o_readdata_32_tpl@68
    // out out_o_readdata_33_tpl@68
    // out out_o_readdata_34_tpl@68
    // out out_o_readdata_35_tpl@68
    // out out_o_readdata_36_tpl@68
    // out out_o_readdata_37_tpl@68
    // out out_o_readdata_38_tpl@68
    // out out_o_readdata_39_tpl@68
    // out out_o_readdata_40_tpl@68
    // out out_o_readdata_41_tpl@68
    // out out_o_readdata_42_tpl@68
    // out out_o_readdata_43_tpl@68
    // out out_o_readdata_44_tpl@68
    // out out_o_readdata_45_tpl@68
    // out out_o_readdata_46_tpl@68
    // out out_o_readdata_47_tpl@68
    // out out_o_readdata_48_tpl@68
    // out out_o_readdata_49_tpl@68
    // out out_o_readdata_50_tpl@68
    // out out_o_readdata_51_tpl@68
    // out out_o_readdata_52_tpl@68
    // out out_o_readdata_53_tpl@68
    // out out_o_readdata_54_tpl@68
    // out out_o_readdata_55_tpl@68
    // out out_o_readdata_56_tpl@68
    // out out_o_readdata_57_tpl@68
    // out out_o_readdata_58_tpl@68
    // out out_o_readdata_59_tpl@68
    // out out_o_readdata_60_tpl@68
    // out out_o_readdata_61_tpl@68
    // out out_o_readdata_62_tpl@68
    // out out_o_readdata_63_tpl@68
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_address@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_burstcount@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_byteenable@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_enable@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_read@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_write@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_writedata@20000000
    // out out_o_almost_empty@68
    // out out_o_empty@68
    // out out_o_stall@20000000
    // out out_o_valid@68
    c_compMM_m_i_llvm_fpga_mem_memcoalesce_l0000que_7011_c_compmm_m0 thei_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x (
        .in_almost_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V15),
        .in_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V9),
        .in_flush(in_flush),
        .in_i_address(bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_d),
        .in_i_predicate(GND_q),
        .in_i_stall(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_in_i_stall_reg1_q),
        .in_i_valid(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V3),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_readdata(in_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_readdata),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_readdatavalid(in_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_readdatavalid),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_waitrequest(in_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_waitrequest),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_writeack(in_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_writeack),
        .out_o_readdata_0_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_0_tpl),
        .out_o_readdata_1_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_1_tpl),
        .out_o_readdata_2_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_2_tpl),
        .out_o_readdata_3_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_3_tpl),
        .out_o_readdata_4_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_4_tpl),
        .out_o_readdata_5_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_5_tpl),
        .out_o_readdata_6_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_6_tpl),
        .out_o_readdata_7_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_7_tpl),
        .out_o_readdata_8_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_8_tpl),
        .out_o_readdata_9_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_9_tpl),
        .out_o_readdata_10_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_10_tpl),
        .out_o_readdata_11_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_11_tpl),
        .out_o_readdata_12_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_12_tpl),
        .out_o_readdata_13_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_13_tpl),
        .out_o_readdata_14_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_14_tpl),
        .out_o_readdata_15_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_15_tpl),
        .out_o_readdata_16_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_16_tpl),
        .out_o_readdata_17_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_17_tpl),
        .out_o_readdata_18_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_18_tpl),
        .out_o_readdata_19_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_19_tpl),
        .out_o_readdata_20_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_20_tpl),
        .out_o_readdata_21_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_21_tpl),
        .out_o_readdata_22_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_22_tpl),
        .out_o_readdata_23_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_23_tpl),
        .out_o_readdata_24_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_24_tpl),
        .out_o_readdata_25_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_25_tpl),
        .out_o_readdata_26_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_26_tpl),
        .out_o_readdata_27_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_27_tpl),
        .out_o_readdata_28_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_28_tpl),
        .out_o_readdata_29_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_29_tpl),
        .out_o_readdata_30_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_30_tpl),
        .out_o_readdata_31_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_31_tpl),
        .out_o_readdata_32_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_32_tpl),
        .out_o_readdata_33_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_33_tpl),
        .out_o_readdata_34_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_34_tpl),
        .out_o_readdata_35_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_35_tpl),
        .out_o_readdata_36_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_36_tpl),
        .out_o_readdata_37_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_37_tpl),
        .out_o_readdata_38_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_38_tpl),
        .out_o_readdata_39_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_39_tpl),
        .out_o_readdata_40_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_40_tpl),
        .out_o_readdata_41_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_41_tpl),
        .out_o_readdata_42_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_42_tpl),
        .out_o_readdata_43_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_43_tpl),
        .out_o_readdata_44_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_44_tpl),
        .out_o_readdata_45_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_45_tpl),
        .out_o_readdata_46_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_46_tpl),
        .out_o_readdata_47_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_47_tpl),
        .out_o_readdata_48_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_48_tpl),
        .out_o_readdata_49_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_49_tpl),
        .out_o_readdata_50_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_50_tpl),
        .out_o_readdata_51_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_51_tpl),
        .out_o_readdata_52_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_52_tpl),
        .out_o_readdata_53_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_53_tpl),
        .out_o_readdata_54_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_54_tpl),
        .out_o_readdata_55_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_55_tpl),
        .out_o_readdata_56_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_56_tpl),
        .out_o_readdata_57_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_57_tpl),
        .out_o_readdata_58_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_58_tpl),
        .out_o_readdata_59_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_59_tpl),
        .out_o_readdata_60_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_60_tpl),
        .out_o_readdata_61_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_61_tpl),
        .out_o_readdata_62_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_62_tpl),
        .out_o_readdata_63_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_63_tpl),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_address(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_address),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_burstcount(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_burstcount),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_byteenable(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_byteenable),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_enable(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_enable),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_read(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_read),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_write(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_write),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_writedata(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_writedata),
        .out_o_almost_empty(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_almost_empty),
        .out_o_empty(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_empty),
        .out_o_stall(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_stall),
        .out_o_valid(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_almost_empty_reg0(REG,817)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_almost_empty_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_almost_empty);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_almost_empty_reg1(REG,816)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_almost_empty_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_almost_empty_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_in_i_stall_reg0(REG,822)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_in_i_stall_reg0_q <= $unsigned(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_backStall);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_in_i_stall_reg1(REG,823)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_in_i_stall_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_in_i_stall_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x(BLACKBOX,15)@37
    // in in_i_stall@20000000
    // out out_o_readdata_0_tpl@68
    // out out_o_readdata_1_tpl@68
    // out out_o_readdata_2_tpl@68
    // out out_o_readdata_3_tpl@68
    // out out_o_readdata_4_tpl@68
    // out out_o_readdata_5_tpl@68
    // out out_o_readdata_6_tpl@68
    // out out_o_readdata_7_tpl@68
    // out out_o_readdata_8_tpl@68
    // out out_o_readdata_9_tpl@68
    // out out_o_readdata_10_tpl@68
    // out out_o_readdata_11_tpl@68
    // out out_o_readdata_12_tpl@68
    // out out_o_readdata_13_tpl@68
    // out out_o_readdata_14_tpl@68
    // out out_o_readdata_15_tpl@68
    // out out_o_readdata_16_tpl@68
    // out out_o_readdata_17_tpl@68
    // out out_o_readdata_18_tpl@68
    // out out_o_readdata_19_tpl@68
    // out out_o_readdata_20_tpl@68
    // out out_o_readdata_21_tpl@68
    // out out_o_readdata_22_tpl@68
    // out out_o_readdata_23_tpl@68
    // out out_o_readdata_24_tpl@68
    // out out_o_readdata_25_tpl@68
    // out out_o_readdata_26_tpl@68
    // out out_o_readdata_27_tpl@68
    // out out_o_readdata_28_tpl@68
    // out out_o_readdata_29_tpl@68
    // out out_o_readdata_30_tpl@68
    // out out_o_readdata_31_tpl@68
    // out out_o_readdata_32_tpl@68
    // out out_o_readdata_33_tpl@68
    // out out_o_readdata_34_tpl@68
    // out out_o_readdata_35_tpl@68
    // out out_o_readdata_36_tpl@68
    // out out_o_readdata_37_tpl@68
    // out out_o_readdata_38_tpl@68
    // out out_o_readdata_39_tpl@68
    // out out_o_readdata_40_tpl@68
    // out out_o_readdata_41_tpl@68
    // out out_o_readdata_42_tpl@68
    // out out_o_readdata_43_tpl@68
    // out out_o_readdata_44_tpl@68
    // out out_o_readdata_45_tpl@68
    // out out_o_readdata_46_tpl@68
    // out out_o_readdata_47_tpl@68
    // out out_o_readdata_48_tpl@68
    // out out_o_readdata_49_tpl@68
    // out out_o_readdata_50_tpl@68
    // out out_o_readdata_51_tpl@68
    // out out_o_readdata_52_tpl@68
    // out out_o_readdata_53_tpl@68
    // out out_o_readdata_54_tpl@68
    // out out_o_readdata_55_tpl@68
    // out out_o_readdata_56_tpl@68
    // out out_o_readdata_57_tpl@68
    // out out_o_readdata_58_tpl@68
    // out out_o_readdata_59_tpl@68
    // out out_o_readdata_60_tpl@68
    // out out_o_readdata_61_tpl@68
    // out out_o_readdata_62_tpl@68
    // out out_o_readdata_63_tpl@68
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_address@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_burstcount@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_byteenable@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_enable@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_read@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_write@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_writedata@20000000
    // out out_o_almost_empty@68
    // out out_o_empty@68
    // out out_o_stall@20000000
    // out out_o_valid@68
    c_compMM_m_i_llvm_fpga_mem_memcoalesce_l0000que_7112_c_compmm_m0 thei_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x (
        .in_almost_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V14),
        .in_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V8),
        .in_flush(in_flush),
        .in_i_address(bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_e),
        .in_i_predicate(GND_q),
        .in_i_stall(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_in_i_stall_reg1_q),
        .in_i_valid(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V2),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_readdata(in_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_readdata),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_readdatavalid(in_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_readdatavalid),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_waitrequest(in_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_waitrequest),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_writeack(in_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_writeack),
        .out_o_readdata_0_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_0_tpl),
        .out_o_readdata_1_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_1_tpl),
        .out_o_readdata_2_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_2_tpl),
        .out_o_readdata_3_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_3_tpl),
        .out_o_readdata_4_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_4_tpl),
        .out_o_readdata_5_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_5_tpl),
        .out_o_readdata_6_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_6_tpl),
        .out_o_readdata_7_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_7_tpl),
        .out_o_readdata_8_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_8_tpl),
        .out_o_readdata_9_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_9_tpl),
        .out_o_readdata_10_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_10_tpl),
        .out_o_readdata_11_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_11_tpl),
        .out_o_readdata_12_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_12_tpl),
        .out_o_readdata_13_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_13_tpl),
        .out_o_readdata_14_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_14_tpl),
        .out_o_readdata_15_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_15_tpl),
        .out_o_readdata_16_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_16_tpl),
        .out_o_readdata_17_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_17_tpl),
        .out_o_readdata_18_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_18_tpl),
        .out_o_readdata_19_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_19_tpl),
        .out_o_readdata_20_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_20_tpl),
        .out_o_readdata_21_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_21_tpl),
        .out_o_readdata_22_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_22_tpl),
        .out_o_readdata_23_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_23_tpl),
        .out_o_readdata_24_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_24_tpl),
        .out_o_readdata_25_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_25_tpl),
        .out_o_readdata_26_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_26_tpl),
        .out_o_readdata_27_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_27_tpl),
        .out_o_readdata_28_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_28_tpl),
        .out_o_readdata_29_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_29_tpl),
        .out_o_readdata_30_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_30_tpl),
        .out_o_readdata_31_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_31_tpl),
        .out_o_readdata_32_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_32_tpl),
        .out_o_readdata_33_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_33_tpl),
        .out_o_readdata_34_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_34_tpl),
        .out_o_readdata_35_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_35_tpl),
        .out_o_readdata_36_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_36_tpl),
        .out_o_readdata_37_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_37_tpl),
        .out_o_readdata_38_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_38_tpl),
        .out_o_readdata_39_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_39_tpl),
        .out_o_readdata_40_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_40_tpl),
        .out_o_readdata_41_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_41_tpl),
        .out_o_readdata_42_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_42_tpl),
        .out_o_readdata_43_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_43_tpl),
        .out_o_readdata_44_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_44_tpl),
        .out_o_readdata_45_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_45_tpl),
        .out_o_readdata_46_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_46_tpl),
        .out_o_readdata_47_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_47_tpl),
        .out_o_readdata_48_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_48_tpl),
        .out_o_readdata_49_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_49_tpl),
        .out_o_readdata_50_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_50_tpl),
        .out_o_readdata_51_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_51_tpl),
        .out_o_readdata_52_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_52_tpl),
        .out_o_readdata_53_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_53_tpl),
        .out_o_readdata_54_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_54_tpl),
        .out_o_readdata_55_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_55_tpl),
        .out_o_readdata_56_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_56_tpl),
        .out_o_readdata_57_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_57_tpl),
        .out_o_readdata_58_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_58_tpl),
        .out_o_readdata_59_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_59_tpl),
        .out_o_readdata_60_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_60_tpl),
        .out_o_readdata_61_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_61_tpl),
        .out_o_readdata_62_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_62_tpl),
        .out_o_readdata_63_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_63_tpl),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_address(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_address),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_burstcount(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_burstcount),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_byteenable(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_byteenable),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_enable(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_enable),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_read(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_read),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_write(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_write),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_writedata(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_writedata),
        .out_o_almost_empty(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_almost_empty),
        .out_o_empty(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_empty),
        .out_o_stall(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_stall),
        .out_o_valid(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_almost_empty_reg0(REG,953)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_almost_empty_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_almost_empty);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_almost_empty_reg1(REG,952)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_almost_empty_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_almost_empty_reg0_q);
        end
    end

    // redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall_reg0(REG,1010)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall_reg0_q <= $unsigned(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_backStall);
        end
    end

    // redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall_reg1(REG,1011)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall_reg1_q <= $unsigned(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall_reg0_q);
        end
    end

    // redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo(STALLFIFO,309)
    assign redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_valid = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V0;
    assign redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall = redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall_reg1_q;
    assign redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_data = bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_f;
    assign redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_empty = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V6;
    assign redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_almost_empty = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V12;
    assign redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_valid_bitsignaltemp = redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_valid[0];
    assign redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall_bitsignaltemp = redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall[0];
    assign redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_valid[0] = redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_valid_bitsignaltemp;
    assign redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_stall[0] = redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_stall_bitsignaltemp;
    assign redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty[0] = redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty_bitsignaltemp;
    assign redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty[0] = redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty_bitsignaltemp;
    hld_fifo #(
        .DEPTH(49),
        .WIDTH(64),
        .STYLE("ms"),
        .ALMOST_FULL_CUTOFF(7),
        .ALMOST_EMPTY_CUTOFF(7),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(0),
        .USE_STALL_LATENCY_UPSTREAM(1),
        .USE_STALL_LATENCY_DOWNSTREAM(1),
        .NEVER_OVERFLOWS(1),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(1)
    ) theredist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo (
        .i_valid(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_valid_bitsignaltemp),
        .i_stall(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_i_stall_bitsignaltemp),
        .i_data(bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_f),
        .o_valid(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_valid_bitsignaltemp),
        .o_stall(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_stall_bitsignaltemp),
        .o_data(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_data),
        .o_empty(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty_bitsignaltemp),
        .o_almost_empty(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty_bitsignaltemp),
        .clock(clock),
        .resetn(resetn)
    );

    // redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty_reg0(REG,1019)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty_reg0_q <= $unsigned(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty);
        end
    end

    // redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty_reg1(REG,1018)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty_reg1_q <= $unsigned(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_in_i_stall_reg0(REG,414)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_in_i_stall_reg0_q <= $unsigned(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_backStall);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_in_i_stall_reg1(REG,415)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_in_i_stall_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_in_i_stall_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x(BLACKBOX,12)@37
    // in in_i_stall@20000000
    // out out_o_readdata_0_tpl@68
    // out out_o_readdata_1_tpl@68
    // out out_o_readdata_2_tpl@68
    // out out_o_readdata_3_tpl@68
    // out out_o_readdata_4_tpl@68
    // out out_o_readdata_5_tpl@68
    // out out_o_readdata_6_tpl@68
    // out out_o_readdata_7_tpl@68
    // out out_o_readdata_8_tpl@68
    // out out_o_readdata_9_tpl@68
    // out out_o_readdata_10_tpl@68
    // out out_o_readdata_11_tpl@68
    // out out_o_readdata_12_tpl@68
    // out out_o_readdata_13_tpl@68
    // out out_o_readdata_14_tpl@68
    // out out_o_readdata_15_tpl@68
    // out out_o_readdata_16_tpl@68
    // out out_o_readdata_17_tpl@68
    // out out_o_readdata_18_tpl@68
    // out out_o_readdata_19_tpl@68
    // out out_o_readdata_20_tpl@68
    // out out_o_readdata_21_tpl@68
    // out out_o_readdata_22_tpl@68
    // out out_o_readdata_23_tpl@68
    // out out_o_readdata_24_tpl@68
    // out out_o_readdata_25_tpl@68
    // out out_o_readdata_26_tpl@68
    // out out_o_readdata_27_tpl@68
    // out out_o_readdata_28_tpl@68
    // out out_o_readdata_29_tpl@68
    // out out_o_readdata_30_tpl@68
    // out out_o_readdata_31_tpl@68
    // out out_o_readdata_32_tpl@68
    // out out_o_readdata_33_tpl@68
    // out out_o_readdata_34_tpl@68
    // out out_o_readdata_35_tpl@68
    // out out_o_readdata_36_tpl@68
    // out out_o_readdata_37_tpl@68
    // out out_o_readdata_38_tpl@68
    // out out_o_readdata_39_tpl@68
    // out out_o_readdata_40_tpl@68
    // out out_o_readdata_41_tpl@68
    // out out_o_readdata_42_tpl@68
    // out out_o_readdata_43_tpl@68
    // out out_o_readdata_44_tpl@68
    // out out_o_readdata_45_tpl@68
    // out out_o_readdata_46_tpl@68
    // out out_o_readdata_47_tpl@68
    // out out_o_readdata_48_tpl@68
    // out out_o_readdata_49_tpl@68
    // out out_o_readdata_50_tpl@68
    // out out_o_readdata_51_tpl@68
    // out out_o_readdata_52_tpl@68
    // out out_o_readdata_53_tpl@68
    // out out_o_readdata_54_tpl@68
    // out out_o_readdata_55_tpl@68
    // out out_o_readdata_56_tpl@68
    // out out_o_readdata_57_tpl@68
    // out out_o_readdata_58_tpl@68
    // out out_o_readdata_59_tpl@68
    // out out_o_readdata_60_tpl@68
    // out out_o_readdata_61_tpl@68
    // out out_o_readdata_62_tpl@68
    // out out_o_readdata_63_tpl@68
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_address@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_burstcount@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_byteenable@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_enable@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_read@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_write@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_writedata@20000000
    // out out_o_almost_empty@68
    // out out_o_empty@68
    // out out_o_stall@20000000
    // out out_o_valid@68
    c_compMM_m_i_llvm_fpga_mem_memcoalesce_l0000ique_689_c_compmm_m0 thei_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x (
        .in_almost_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V17),
        .in_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V11),
        .in_flush(in_flush),
        .in_i_address(bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_b),
        .in_i_predicate(GND_q),
        .in_i_stall(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_in_i_stall_reg1_q),
        .in_i_valid(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V5),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_readdata(in_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_readdata),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_readdatavalid(in_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_readdatavalid),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_waitrequest(in_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_waitrequest),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_writeack(in_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_writeack),
        .out_o_readdata_0_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_0_tpl),
        .out_o_readdata_1_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_1_tpl),
        .out_o_readdata_2_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_2_tpl),
        .out_o_readdata_3_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_3_tpl),
        .out_o_readdata_4_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_4_tpl),
        .out_o_readdata_5_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_5_tpl),
        .out_o_readdata_6_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_6_tpl),
        .out_o_readdata_7_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_7_tpl),
        .out_o_readdata_8_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_8_tpl),
        .out_o_readdata_9_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_9_tpl),
        .out_o_readdata_10_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_10_tpl),
        .out_o_readdata_11_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_11_tpl),
        .out_o_readdata_12_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_12_tpl),
        .out_o_readdata_13_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_13_tpl),
        .out_o_readdata_14_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_14_tpl),
        .out_o_readdata_15_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_15_tpl),
        .out_o_readdata_16_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_16_tpl),
        .out_o_readdata_17_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_17_tpl),
        .out_o_readdata_18_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_18_tpl),
        .out_o_readdata_19_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_19_tpl),
        .out_o_readdata_20_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_20_tpl),
        .out_o_readdata_21_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_21_tpl),
        .out_o_readdata_22_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_22_tpl),
        .out_o_readdata_23_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_23_tpl),
        .out_o_readdata_24_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_24_tpl),
        .out_o_readdata_25_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_25_tpl),
        .out_o_readdata_26_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_26_tpl),
        .out_o_readdata_27_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_27_tpl),
        .out_o_readdata_28_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_28_tpl),
        .out_o_readdata_29_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_29_tpl),
        .out_o_readdata_30_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_30_tpl),
        .out_o_readdata_31_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_31_tpl),
        .out_o_readdata_32_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_32_tpl),
        .out_o_readdata_33_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_33_tpl),
        .out_o_readdata_34_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_34_tpl),
        .out_o_readdata_35_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_35_tpl),
        .out_o_readdata_36_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_36_tpl),
        .out_o_readdata_37_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_37_tpl),
        .out_o_readdata_38_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_38_tpl),
        .out_o_readdata_39_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_39_tpl),
        .out_o_readdata_40_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_40_tpl),
        .out_o_readdata_41_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_41_tpl),
        .out_o_readdata_42_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_42_tpl),
        .out_o_readdata_43_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_43_tpl),
        .out_o_readdata_44_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_44_tpl),
        .out_o_readdata_45_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_45_tpl),
        .out_o_readdata_46_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_46_tpl),
        .out_o_readdata_47_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_47_tpl),
        .out_o_readdata_48_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_48_tpl),
        .out_o_readdata_49_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_49_tpl),
        .out_o_readdata_50_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_50_tpl),
        .out_o_readdata_51_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_51_tpl),
        .out_o_readdata_52_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_52_tpl),
        .out_o_readdata_53_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_53_tpl),
        .out_o_readdata_54_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_54_tpl),
        .out_o_readdata_55_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_55_tpl),
        .out_o_readdata_56_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_56_tpl),
        .out_o_readdata_57_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_57_tpl),
        .out_o_readdata_58_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_58_tpl),
        .out_o_readdata_59_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_59_tpl),
        .out_o_readdata_60_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_60_tpl),
        .out_o_readdata_61_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_61_tpl),
        .out_o_readdata_62_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_62_tpl),
        .out_o_readdata_63_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_63_tpl),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_address(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_address),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_burstcount(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_burstcount),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_byteenable(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_byteenable),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_enable(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_enable),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_read(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_read),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_write(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_write),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_writedata(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_writedata),
        .out_o_almost_empty(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_almost_empty),
        .out_o_empty(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_empty),
        .out_o_stall(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_stall),
        .out_o_valid(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_almost_empty_reg0(REG,545)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_almost_empty_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_almost_empty);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_almost_empty_reg1(REG,544)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_almost_empty_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_almost_empty_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_empty_reg0(REG,683)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_empty_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_empty);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_empty_reg1(REG,682)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_empty_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_empty_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_empty_reg0(REG,819)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_empty_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_empty);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_empty_reg1(REG,818)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_empty_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_empty_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_empty_reg0(REG,955)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_empty_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_empty);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_empty_reg1(REG,954)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_empty_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_empty_reg0_q);
        end
    end

    // redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty_reg0(REG,1017)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty_reg0_q <= $unsigned(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty);
        end
    end

    // redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty_reg1(REG,1016)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty_reg1_q <= $unsigned(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_empty_reg0(REG,547)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_empty_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_empty);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_empty_reg1(REG,546)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_empty_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_empty_reg0_q);
        end
    end

    // merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg0(REG,406)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg0_q <= $unsigned(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0);
        end
    end

    // merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg1(REG,405)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg1_q <= $unsigned(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg0_q);
        end
    end

    // merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg2(REG,404)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg2_q <= $unsigned(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg1_q);
        end
    end

    // merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg3(REG,403)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg3_q <= $unsigned(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg2_q);
        end
    end

    // merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg4(REG,402)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg4_q <= $unsigned(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg3_q);
        end
    end

    // merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg5(REG,401)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg5_q <= $unsigned(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg4_q);
        end
    end

    // merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg6(REG,400)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg6_q <= $unsigned(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg5_q);
        end
    end

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_almost_empty_out_reg0(REG,997)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_almost_empty_out_reg0_q <= $unsigned(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_almost_empty_out);
        end
    end

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_almost_empty_out_reg1(REG,996)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_almost_empty_out_reg1_q <= $unsigned(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_almost_empty_out_reg0_q);
        end
    end

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_empty_out_reg0(REG,999)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_empty_out_reg0_q <= $unsigned(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_empty_out);
        end
    end

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_empty_out_reg1(REG,998)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_empty_out_reg1_q <= $unsigned(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_empty_out_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_almost_empty_reg0(REG,961)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_almost_empty_reg0_q <= $unsigned(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_almost_empty);
        end
    end

    // i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_almost_empty_reg1(REG,960)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_almost_empty_reg1_q <= $unsigned(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_almost_empty_reg0_q);
        end
    end

    // join_for_coalesced_delay_0(BITJOIN,307)
    assign join_for_coalesced_delay_0_q = {bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_h, bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_g};

    // coalesced_delay_0_fifo_i_stall_reg0(REG,1020)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_i_stall_reg0_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_0_backStall);
        end
    end

    // coalesced_delay_0_fifo_i_stall_reg1(REG,1021)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_i_stall_reg1_q <= $unsigned(coalesced_delay_0_fifo_i_stall_reg0_q);
        end
    end

    // coalesced_delay_0_fifo(STALLFIFO,310)
    assign coalesced_delay_0_fifo_i_valid = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V1;
    assign coalesced_delay_0_fifo_i_stall = coalesced_delay_0_fifo_i_stall_reg1_q;
    assign coalesced_delay_0_fifo_i_data = join_for_coalesced_delay_0_q;
    assign coalesced_delay_0_fifo_i_empty = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V7;
    assign coalesced_delay_0_fifo_i_almost_empty = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V13;
    assign coalesced_delay_0_fifo_i_valid_bitsignaltemp = coalesced_delay_0_fifo_i_valid[0];
    assign coalesced_delay_0_fifo_i_stall_bitsignaltemp = coalesced_delay_0_fifo_i_stall[0];
    assign coalesced_delay_0_fifo_o_valid[0] = coalesced_delay_0_fifo_o_valid_bitsignaltemp;
    assign coalesced_delay_0_fifo_o_stall[0] = coalesced_delay_0_fifo_o_stall_bitsignaltemp;
    assign coalesced_delay_0_fifo_o_empty[0] = coalesced_delay_0_fifo_o_empty_bitsignaltemp;
    assign coalesced_delay_0_fifo_o_almost_empty[0] = coalesced_delay_0_fifo_o_almost_empty_bitsignaltemp;
    hld_fifo #(
        .DEPTH(397),
        .WIDTH(2),
        .STYLE("ms"),
        .ALMOST_FULL_CUTOFF(7),
        .ALMOST_EMPTY_CUTOFF(7),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(0),
        .USE_STALL_LATENCY_UPSTREAM(1),
        .USE_STALL_LATENCY_DOWNSTREAM(1),
        .NEVER_OVERFLOWS(1),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(1)
    ) thecoalesced_delay_0_fifo (
        .i_valid(coalesced_delay_0_fifo_i_valid_bitsignaltemp),
        .i_stall(coalesced_delay_0_fifo_i_stall_bitsignaltemp),
        .i_data(join_for_coalesced_delay_0_q),
        .o_valid(coalesced_delay_0_fifo_o_valid_bitsignaltemp),
        .o_stall(coalesced_delay_0_fifo_o_stall_bitsignaltemp),
        .o_data(coalesced_delay_0_fifo_o_data),
        .o_empty(coalesced_delay_0_fifo_o_empty_bitsignaltemp),
        .o_almost_empty(coalesced_delay_0_fifo_o_almost_empty_bitsignaltemp),
        .clock(clock),
        .resetn(resetn)
    );

    // coalesced_delay_0_fifo_o_almost_empty_reg0(REG,1029)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_almost_empty_reg0_q <= $unsigned(coalesced_delay_0_fifo_o_almost_empty);
        end
    end

    // coalesced_delay_0_fifo_o_almost_empty_reg1(REG,1028)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_almost_empty_reg1_q <= $unsigned(coalesced_delay_0_fifo_o_almost_empty_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_empty_reg0(REG,963)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_empty_reg0_q <= $unsigned(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_empty);
        end
    end

    // i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_empty_reg1(REG,962)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_empty_reg1_q <= $unsigned(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_empty_reg0_q);
        end
    end

    // coalesced_delay_0_fifo_o_empty_reg0(REG,1027)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_empty_reg0_q <= $unsigned(coalesced_delay_0_fifo_o_empty);
        end
    end

    // coalesced_delay_0_fifo_o_empty_reg1(REG,1026)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_empty_reg1_q <= $unsigned(coalesced_delay_0_fifo_o_empty_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_valid_reg0(REG,965)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_valid_reg0_q <= $unsigned(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_valid);
        end
    end

    // i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_valid_reg1(REG,964)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_valid_reg1_q <= $unsigned(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_valid_reg0_q);
        end
    end

    // coalesced_delay_0_fifo_o_valid_reg0(REG,1023)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_valid_reg0_q <= $unsigned(coalesced_delay_0_fifo_o_valid);
        end
    end

    // coalesced_delay_0_fifo_o_valid_reg1(REG,1022)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_valid_reg1_q <= $unsigned(coalesced_delay_0_fifo_o_valid_reg0_q);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_0(STALLENABLE,398)
    // Sync
    assign merged_in_SE_sel_for_coalesced_delay_0_temp_back_stall = in_stall_in;
    assign merged_in_SE_sel_for_coalesced_delay_0_can_fast_read = ~ ((coalesced_delay_0_fifo_o_almost_empty_reg1_q | i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_almost_empty_reg1_q));
    assign merged_in_SE_sel_for_coalesced_delay_0_can_slow_read = ~ ((coalesced_delay_0_fifo_o_empty_reg1_q | i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_empty_reg1_q));
    assign merged_in_SE_sel_for_coalesced_delay_0_backStall = ~ (merged_in_SE_sel_for_coalesced_delay_0_forced_read);
    assign merged_in_SE_sel_for_coalesced_delay_0_no_space_for_result = merged_in_SE_sel_for_coalesced_delay_0_temp_back_stall;
    assign merged_in_SE_sel_for_coalesced_delay_0_V0 = merged_in_SE_sel_for_coalesced_delay_0_forced_read;
    assign merged_in_SE_sel_for_coalesced_delay_0_V1 = $unsigned(1'b0);
    assign merged_in_SE_sel_for_coalesced_delay_0_V2 = $unsigned(1'b0);
    assign can_fast_read_bitsignaltemp_dup_name_0 = merged_in_SE_sel_for_coalesced_delay_0_can_fast_read[0];
    assign can_slow_read_bitsignaltemp_dup_name_0 = merged_in_SE_sel_for_coalesced_delay_0_can_slow_read[0];
    assign no_space_for_result_bitsignaltemp_dup_name_0 = merged_in_SE_sel_for_coalesced_delay_0_no_space_for_result[0];
    assign merged_in_SE_sel_for_coalesced_delay_0_forced_read[0] = forced_read_bitsignaltemp_dup_name_0;
    acl_sync_stall_latency #(
        .EMPTY_PLUS_STALL_LATENCY(7),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(1),
        .RESET_EVERYTHING(0)
    ) themerged_in_SE_sel_for_coalesced_delay_0 (
        .can_fast_read(can_fast_read_bitsignaltemp_dup_name_0),
        .can_slow_read(can_slow_read_bitsignaltemp_dup_name_0),
        .no_space_for_result(no_space_for_result_bitsignaltemp_dup_name_0),
        .forced_read(forced_read_bitsignaltemp_dup_name_0),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_in_i_stall_reg0(REG,958)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_in_i_stall_reg0_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_0_backStall);
        end
    end

    // i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_in_i_stall_reg1(REG,959)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_in_i_stall_reg1_q <= $unsigned(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_in_i_stall_reg0_q);
        end
    end

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_3_tpl_reg0(REG,995)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_3_tpl_reg0_q <= $unsigned(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_3_tpl);
        end
    end

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_3_tpl_reg1(REG,994)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_3_tpl_reg1_q <= $unsigned(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_3_tpl_reg0_q);
        end
    end

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_2_tpl_reg0(REG,993)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_2_tpl_reg0_q <= $unsigned(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_2_tpl);
        end
    end

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_2_tpl_reg1(REG,992)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_2_tpl_reg1_q <= $unsigned(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_2_tpl_reg0_q);
        end
    end

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_1_tpl_reg0(REG,991)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_1_tpl_reg0_q <= $unsigned(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_1_tpl);
        end
    end

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_1_tpl_reg1(REG,990)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_1_tpl_reg1_q <= $unsigned(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_1_tpl_reg0_q);
        end
    end

    // bubble_join_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x(BITJOIN,328)
    assign bubble_join_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_q = {i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_3_tpl_reg1_q, i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_2_tpl_reg1_q, i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_1_tpl_reg1_q};

    // bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x(BITSELECT,329)
    assign bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_b = $unsigned(bubble_join_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_q[63:0]);
    assign bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_c = $unsigned(bubble_join_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_q[79:64]);
    assign bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_d = $unsigned(bubble_join_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_q[95:80]);

    // i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x(BLACKBOX,16)@360
    // in in_i_stall@20000000
    // out out_lsu_memdep_17_o_active@20000000
    // out out_memdep_17_c_compMM_m_avm_address@20000000
    // out out_memdep_17_c_compMM_m_avm_burstcount@20000000
    // out out_memdep_17_c_compMM_m_avm_byteenable@20000000
    // out out_memdep_17_c_compMM_m_avm_enable@20000000
    // out out_memdep_17_c_compMM_m_avm_read@20000000
    // out out_memdep_17_c_compMM_m_avm_write@20000000
    // out out_memdep_17_c_compMM_m_avm_writedata@20000000
    // out out_o_almost_empty@416
    // out out_o_empty@416
    // out out_o_stall@20000000
    // out out_o_valid@416
    // out out_o_writeack@416
    c_compMM_m_i_llvm_fpga_mem_memdep_17_c_compmm_m0 thei_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x (
        .in_i_writedata_0_tpl(bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_c),
        .in_i_writedata_1_tpl(bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_d),
        .in_almost_empty_in(merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_V2),
        .in_empty_in(merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_V1),
        .in_flush(in_flush),
        .in_i_address(bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_b),
        .in_i_predicate(GND_q),
        .in_i_stall(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_in_i_stall_reg1_q),
        .in_i_valid(merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_V0),
        .in_memdep_17_c_compMM_m_avm_readdata(in_memdep_17_c_compMM_m_avm_readdata),
        .in_memdep_17_c_compMM_m_avm_readdatavalid(in_memdep_17_c_compMM_m_avm_readdatavalid),
        .in_memdep_17_c_compMM_m_avm_waitrequest(in_memdep_17_c_compMM_m_avm_waitrequest),
        .in_memdep_17_c_compMM_m_avm_writeack(in_memdep_17_c_compMM_m_avm_writeack),
        .out_lsu_memdep_17_o_active(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_lsu_memdep_17_o_active),
        .out_memdep_17_c_compMM_m_avm_address(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_address),
        .out_memdep_17_c_compMM_m_avm_burstcount(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_burstcount),
        .out_memdep_17_c_compMM_m_avm_byteenable(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_byteenable),
        .out_memdep_17_c_compMM_m_avm_enable(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_enable),
        .out_memdep_17_c_compMM_m_avm_read(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_read),
        .out_memdep_17_c_compMM_m_avm_write(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_write),
        .out_memdep_17_c_compMM_m_avm_writedata(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_writedata),
        .out_o_almost_empty(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_almost_empty),
        .out_o_empty(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_empty),
        .out_o_stall(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_stall),
        .out_o_valid(i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_valid),
        .out_o_writeack(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_valid_reg0(REG,1001)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_valid_reg0_q <= $unsigned(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_valid);
        end
    end

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_valid_reg1(REG,1000)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_valid_reg1_q <= $unsigned(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_valid_reg0_q);
        end
    end

    // merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x(STALLENABLE,399)
    assign merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_backStall = i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_o_stall;
    assign merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_V0 = i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_valid_reg1_q;
    assign merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_V1 = i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_empty_out_reg1_q;
    assign merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_V2 = i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_almost_empty_out_reg1_q;

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_in_i_stall_reg0(REG,988)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_in_i_stall_reg0_q <= $unsigned(merged_in_SE_bubble_select_i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_backStall);
        end
    end

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_in_i_stall_reg1(REG,989)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_in_i_stall_reg1_q <= $unsigned(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_in_i_stall_reg0_q);
        end
    end

    // redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_data_reg0(REG,1015)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_data_reg0_q <= $unsigned(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_data);
        end
    end

    // redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_data_reg1(REG,1014)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_data_reg1_q <= $unsigned(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_data_reg0_q);
        end
    end

    // bubble_join_redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo(BITJOIN,332)
    assign bubble_join_redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_q = redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_data_reg1_q;

    // bubble_select_redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo(BITSELECT,333)
    assign bubble_select_redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_b = $unsigned(bubble_join_redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_q[63:0]);

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_63_tpl_reg0(REG,951)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_63_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_63_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_63_tpl_reg1(REG,950)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_63_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_63_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_62_tpl_reg0(REG,949)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_62_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_62_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_62_tpl_reg1(REG,948)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_62_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_62_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_61_tpl_reg0(REG,947)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_61_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_61_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_61_tpl_reg1(REG,946)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_61_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_61_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_60_tpl_reg0(REG,945)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_60_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_60_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_60_tpl_reg1(REG,944)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_60_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_60_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_59_tpl_reg0(REG,943)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_59_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_59_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_59_tpl_reg1(REG,942)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_59_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_59_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_58_tpl_reg0(REG,941)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_58_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_58_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_58_tpl_reg1(REG,940)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_58_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_58_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_57_tpl_reg0(REG,939)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_57_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_57_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_57_tpl_reg1(REG,938)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_57_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_57_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_56_tpl_reg0(REG,937)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_56_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_56_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_56_tpl_reg1(REG,936)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_56_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_56_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_55_tpl_reg0(REG,935)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_55_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_55_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_55_tpl_reg1(REG,934)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_55_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_55_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_54_tpl_reg0(REG,933)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_54_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_54_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_54_tpl_reg1(REG,932)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_54_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_54_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_53_tpl_reg0(REG,931)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_53_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_53_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_53_tpl_reg1(REG,930)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_53_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_53_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_52_tpl_reg0(REG,929)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_52_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_52_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_52_tpl_reg1(REG,928)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_52_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_52_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_51_tpl_reg0(REG,927)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_51_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_51_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_51_tpl_reg1(REG,926)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_51_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_51_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_50_tpl_reg0(REG,925)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_50_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_50_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_50_tpl_reg1(REG,924)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_50_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_50_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_49_tpl_reg0(REG,923)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_49_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_49_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_49_tpl_reg1(REG,922)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_49_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_49_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_48_tpl_reg0(REG,921)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_48_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_48_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_48_tpl_reg1(REG,920)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_48_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_48_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_47_tpl_reg0(REG,919)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_47_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_47_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_47_tpl_reg1(REG,918)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_47_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_47_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_46_tpl_reg0(REG,917)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_46_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_46_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_46_tpl_reg1(REG,916)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_46_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_46_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_45_tpl_reg0(REG,915)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_45_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_45_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_45_tpl_reg1(REG,914)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_45_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_45_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_44_tpl_reg0(REG,913)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_44_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_44_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_44_tpl_reg1(REG,912)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_44_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_44_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_43_tpl_reg0(REG,911)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_43_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_43_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_43_tpl_reg1(REG,910)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_43_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_43_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_42_tpl_reg0(REG,909)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_42_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_42_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_42_tpl_reg1(REG,908)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_42_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_42_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_41_tpl_reg0(REG,907)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_41_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_41_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_41_tpl_reg1(REG,906)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_41_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_41_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_40_tpl_reg0(REG,905)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_40_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_40_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_40_tpl_reg1(REG,904)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_40_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_40_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_39_tpl_reg0(REG,903)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_39_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_39_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_39_tpl_reg1(REG,902)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_39_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_39_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_38_tpl_reg0(REG,901)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_38_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_38_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_38_tpl_reg1(REG,900)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_38_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_38_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_37_tpl_reg0(REG,899)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_37_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_37_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_37_tpl_reg1(REG,898)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_37_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_37_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_36_tpl_reg0(REG,897)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_36_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_36_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_36_tpl_reg1(REG,896)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_36_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_36_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_35_tpl_reg0(REG,895)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_35_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_35_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_35_tpl_reg1(REG,894)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_35_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_35_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_34_tpl_reg0(REG,893)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_34_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_34_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_34_tpl_reg1(REG,892)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_34_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_34_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_33_tpl_reg0(REG,891)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_33_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_33_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_33_tpl_reg1(REG,890)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_33_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_33_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_32_tpl_reg0(REG,889)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_32_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_32_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_32_tpl_reg1(REG,888)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_32_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_32_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_31_tpl_reg0(REG,887)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_31_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_31_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_31_tpl_reg1(REG,886)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_31_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_31_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_30_tpl_reg0(REG,885)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_30_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_30_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_30_tpl_reg1(REG,884)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_30_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_30_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_29_tpl_reg0(REG,883)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_29_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_29_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_29_tpl_reg1(REG,882)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_29_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_29_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_28_tpl_reg0(REG,881)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_28_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_28_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_28_tpl_reg1(REG,880)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_28_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_28_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_27_tpl_reg0(REG,879)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_27_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_27_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_27_tpl_reg1(REG,878)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_27_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_27_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_26_tpl_reg0(REG,877)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_26_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_26_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_26_tpl_reg1(REG,876)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_26_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_26_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_25_tpl_reg0(REG,875)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_25_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_25_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_25_tpl_reg1(REG,874)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_25_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_25_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_24_tpl_reg0(REG,873)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_24_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_24_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_24_tpl_reg1(REG,872)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_24_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_24_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_23_tpl_reg0(REG,871)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_23_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_23_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_23_tpl_reg1(REG,870)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_23_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_23_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_22_tpl_reg0(REG,869)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_22_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_22_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_22_tpl_reg1(REG,868)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_22_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_22_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_21_tpl_reg0(REG,867)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_21_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_21_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_21_tpl_reg1(REG,866)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_21_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_21_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_20_tpl_reg0(REG,865)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_20_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_20_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_20_tpl_reg1(REG,864)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_20_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_20_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_19_tpl_reg0(REG,863)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_19_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_19_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_19_tpl_reg1(REG,862)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_19_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_19_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_18_tpl_reg0(REG,861)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_18_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_18_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_18_tpl_reg1(REG,860)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_18_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_18_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_17_tpl_reg0(REG,859)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_17_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_17_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_17_tpl_reg1(REG,858)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_17_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_17_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_16_tpl_reg0(REG,857)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_16_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_16_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_16_tpl_reg1(REG,856)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_16_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_16_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_15_tpl_reg0(REG,855)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_15_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_15_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_15_tpl_reg1(REG,854)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_15_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_15_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_14_tpl_reg0(REG,853)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_14_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_14_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_14_tpl_reg1(REG,852)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_14_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_14_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_13_tpl_reg0(REG,851)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_13_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_13_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_13_tpl_reg1(REG,850)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_13_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_13_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_12_tpl_reg0(REG,849)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_12_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_12_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_12_tpl_reg1(REG,848)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_12_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_12_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_11_tpl_reg0(REG,847)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_11_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_11_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_11_tpl_reg1(REG,846)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_11_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_11_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_10_tpl_reg0(REG,845)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_10_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_10_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_10_tpl_reg1(REG,844)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_10_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_10_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_9_tpl_reg0(REG,843)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_9_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_9_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_9_tpl_reg1(REG,842)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_9_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_9_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_8_tpl_reg0(REG,841)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_8_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_8_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_8_tpl_reg1(REG,840)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_8_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_8_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_7_tpl_reg0(REG,839)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_7_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_7_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_7_tpl_reg1(REG,838)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_7_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_7_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_6_tpl_reg0(REG,837)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_6_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_6_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_6_tpl_reg1(REG,836)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_6_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_6_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_5_tpl_reg0(REG,835)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_5_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_5_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_5_tpl_reg1(REG,834)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_5_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_5_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_4_tpl_reg0(REG,833)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_4_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_4_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_4_tpl_reg1(REG,832)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_4_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_4_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_3_tpl_reg0(REG,831)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_3_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_3_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_3_tpl_reg1(REG,830)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_3_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_3_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_2_tpl_reg0(REG,829)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_2_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_2_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_2_tpl_reg1(REG,828)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_2_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_2_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_1_tpl_reg0(REG,827)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_1_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_1_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_1_tpl_reg1(REG,826)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_1_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_1_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_0_tpl_reg0(REG,825)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_0_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_0_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_0_tpl_reg1(REG,824)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_0_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_0_tpl_reg0_q);
        end
    end

    // bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x(BITJOIN,321)
    assign bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q = {i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_63_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_62_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_61_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_60_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_59_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_58_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_57_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_56_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_55_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_54_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_53_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_52_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_51_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_50_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_49_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_48_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_47_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_46_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_45_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_44_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_43_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_42_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_41_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_40_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_39_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_38_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_37_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_36_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_35_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_34_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_33_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_32_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_31_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_30_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_29_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_28_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_27_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_26_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_25_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_24_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_23_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_22_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_21_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_20_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_19_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_18_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_17_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_16_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_15_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_14_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_13_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_12_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_11_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_10_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_9_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_8_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_7_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_6_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_5_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_4_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_3_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_2_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_1_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_readdata_0_tpl_reg1_q};

    // bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x(BITSELECT,322)
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_b = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[15:0]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_c = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[31:16]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_d = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[47:32]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_e = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[63:48]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_f = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[79:64]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_g = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[95:80]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_h = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[111:96]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_i = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[127:112]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_j = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[143:128]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_k = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[159:144]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_l = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[175:160]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_m = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[191:176]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_n = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[207:192]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_o = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[223:208]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_p = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[239:224]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[255:240]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_r = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[271:256]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_s = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[287:272]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_t = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[303:288]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_u = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[319:304]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_v = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[335:320]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_w = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[351:336]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_x = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[367:352]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_y = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[383:368]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_z = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[399:384]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_aa = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[415:400]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_bb = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[431:416]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_cc = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[447:432]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_dd = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[463:448]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ee = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[479:464]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ff = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[495:480]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_gg = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[511:496]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_hh = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[527:512]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ii = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[543:528]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_jj = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[559:544]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_kk = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[575:560]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ll = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[591:576]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_mm = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[607:592]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_nn = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[623:608]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_oo = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[639:624]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_pp = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[655:640]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_qq = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[671:656]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_rr = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[687:672]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ss = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[703:688]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_tt = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[719:704]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_uu = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[735:720]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_vv = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[751:736]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ww = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[767:752]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_xx = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[783:768]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_yy = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[799:784]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_zz = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[815:800]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_1 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[831:816]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_2 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[847:832]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_3 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[863:848]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_4 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[879:864]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_5 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[895:880]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_6 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[911:896]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_7 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[927:912]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_8 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[943:928]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_9 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[959:944]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_0 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[975:960]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_o61 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[991:976]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_o62 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[1007:992]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_o63 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q[1023:1008]);

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_63_tpl_reg0(REG,815)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_63_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_63_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_63_tpl_reg1(REG,814)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_63_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_63_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_62_tpl_reg0(REG,813)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_62_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_62_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_62_tpl_reg1(REG,812)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_62_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_62_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_61_tpl_reg0(REG,811)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_61_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_61_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_61_tpl_reg1(REG,810)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_61_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_61_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_60_tpl_reg0(REG,809)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_60_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_60_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_60_tpl_reg1(REG,808)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_60_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_60_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_59_tpl_reg0(REG,807)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_59_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_59_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_59_tpl_reg1(REG,806)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_59_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_59_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_58_tpl_reg0(REG,805)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_58_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_58_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_58_tpl_reg1(REG,804)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_58_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_58_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_57_tpl_reg0(REG,803)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_57_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_57_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_57_tpl_reg1(REG,802)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_57_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_57_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_56_tpl_reg0(REG,801)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_56_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_56_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_56_tpl_reg1(REG,800)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_56_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_56_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_55_tpl_reg0(REG,799)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_55_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_55_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_55_tpl_reg1(REG,798)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_55_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_55_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_54_tpl_reg0(REG,797)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_54_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_54_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_54_tpl_reg1(REG,796)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_54_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_54_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_53_tpl_reg0(REG,795)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_53_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_53_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_53_tpl_reg1(REG,794)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_53_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_53_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_52_tpl_reg0(REG,793)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_52_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_52_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_52_tpl_reg1(REG,792)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_52_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_52_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_51_tpl_reg0(REG,791)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_51_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_51_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_51_tpl_reg1(REG,790)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_51_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_51_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_50_tpl_reg0(REG,789)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_50_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_50_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_50_tpl_reg1(REG,788)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_50_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_50_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_49_tpl_reg0(REG,787)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_49_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_49_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_49_tpl_reg1(REG,786)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_49_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_49_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_48_tpl_reg0(REG,785)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_48_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_48_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_48_tpl_reg1(REG,784)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_48_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_48_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_47_tpl_reg0(REG,783)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_47_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_47_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_47_tpl_reg1(REG,782)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_47_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_47_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_46_tpl_reg0(REG,781)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_46_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_46_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_46_tpl_reg1(REG,780)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_46_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_46_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_45_tpl_reg0(REG,779)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_45_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_45_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_45_tpl_reg1(REG,778)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_45_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_45_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_44_tpl_reg0(REG,777)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_44_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_44_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_44_tpl_reg1(REG,776)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_44_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_44_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_43_tpl_reg0(REG,775)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_43_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_43_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_43_tpl_reg1(REG,774)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_43_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_43_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_42_tpl_reg0(REG,773)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_42_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_42_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_42_tpl_reg1(REG,772)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_42_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_42_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_41_tpl_reg0(REG,771)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_41_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_41_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_41_tpl_reg1(REG,770)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_41_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_41_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_40_tpl_reg0(REG,769)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_40_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_40_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_40_tpl_reg1(REG,768)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_40_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_40_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_39_tpl_reg0(REG,767)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_39_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_39_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_39_tpl_reg1(REG,766)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_39_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_39_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_38_tpl_reg0(REG,765)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_38_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_38_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_38_tpl_reg1(REG,764)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_38_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_38_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_37_tpl_reg0(REG,763)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_37_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_37_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_37_tpl_reg1(REG,762)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_37_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_37_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_36_tpl_reg0(REG,761)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_36_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_36_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_36_tpl_reg1(REG,760)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_36_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_36_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_35_tpl_reg0(REG,759)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_35_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_35_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_35_tpl_reg1(REG,758)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_35_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_35_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_34_tpl_reg0(REG,757)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_34_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_34_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_34_tpl_reg1(REG,756)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_34_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_34_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_33_tpl_reg0(REG,755)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_33_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_33_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_33_tpl_reg1(REG,754)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_33_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_33_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_32_tpl_reg0(REG,753)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_32_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_32_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_32_tpl_reg1(REG,752)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_32_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_32_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_31_tpl_reg0(REG,751)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_31_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_31_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_31_tpl_reg1(REG,750)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_31_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_31_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_30_tpl_reg0(REG,749)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_30_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_30_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_30_tpl_reg1(REG,748)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_30_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_30_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_29_tpl_reg0(REG,747)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_29_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_29_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_29_tpl_reg1(REG,746)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_29_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_29_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_28_tpl_reg0(REG,745)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_28_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_28_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_28_tpl_reg1(REG,744)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_28_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_28_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_27_tpl_reg0(REG,743)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_27_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_27_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_27_tpl_reg1(REG,742)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_27_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_27_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_26_tpl_reg0(REG,741)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_26_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_26_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_26_tpl_reg1(REG,740)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_26_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_26_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_25_tpl_reg0(REG,739)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_25_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_25_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_25_tpl_reg1(REG,738)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_25_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_25_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_24_tpl_reg0(REG,737)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_24_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_24_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_24_tpl_reg1(REG,736)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_24_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_24_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_23_tpl_reg0(REG,735)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_23_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_23_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_23_tpl_reg1(REG,734)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_23_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_23_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_22_tpl_reg0(REG,733)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_22_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_22_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_22_tpl_reg1(REG,732)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_22_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_22_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_21_tpl_reg0(REG,731)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_21_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_21_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_21_tpl_reg1(REG,730)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_21_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_21_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_20_tpl_reg0(REG,729)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_20_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_20_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_20_tpl_reg1(REG,728)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_20_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_20_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_19_tpl_reg0(REG,727)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_19_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_19_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_19_tpl_reg1(REG,726)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_19_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_19_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_18_tpl_reg0(REG,725)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_18_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_18_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_18_tpl_reg1(REG,724)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_18_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_18_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_17_tpl_reg0(REG,723)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_17_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_17_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_17_tpl_reg1(REG,722)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_17_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_17_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_16_tpl_reg0(REG,721)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_16_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_16_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_16_tpl_reg1(REG,720)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_16_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_16_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_15_tpl_reg0(REG,719)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_15_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_15_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_15_tpl_reg1(REG,718)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_15_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_15_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_14_tpl_reg0(REG,717)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_14_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_14_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_14_tpl_reg1(REG,716)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_14_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_14_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_13_tpl_reg0(REG,715)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_13_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_13_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_13_tpl_reg1(REG,714)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_13_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_13_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_12_tpl_reg0(REG,713)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_12_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_12_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_12_tpl_reg1(REG,712)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_12_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_12_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_11_tpl_reg0(REG,711)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_11_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_11_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_11_tpl_reg1(REG,710)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_11_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_11_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_10_tpl_reg0(REG,709)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_10_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_10_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_10_tpl_reg1(REG,708)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_10_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_10_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_9_tpl_reg0(REG,707)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_9_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_9_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_9_tpl_reg1(REG,706)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_9_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_9_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_8_tpl_reg0(REG,705)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_8_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_8_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_8_tpl_reg1(REG,704)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_8_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_8_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_7_tpl_reg0(REG,703)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_7_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_7_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_7_tpl_reg1(REG,702)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_7_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_7_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_6_tpl_reg0(REG,701)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_6_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_6_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_6_tpl_reg1(REG,700)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_6_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_6_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_5_tpl_reg0(REG,699)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_5_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_5_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_5_tpl_reg1(REG,698)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_5_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_5_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_4_tpl_reg0(REG,697)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_4_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_4_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_4_tpl_reg1(REG,696)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_4_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_4_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_3_tpl_reg0(REG,695)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_3_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_3_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_3_tpl_reg1(REG,694)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_3_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_3_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_2_tpl_reg0(REG,693)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_2_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_2_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_2_tpl_reg1(REG,692)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_2_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_2_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_1_tpl_reg0(REG,691)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_1_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_1_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_1_tpl_reg1(REG,690)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_1_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_1_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_0_tpl_reg0(REG,689)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_0_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_0_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_0_tpl_reg1(REG,688)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_0_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_0_tpl_reg0_q);
        end
    end

    // bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x(BITJOIN,318)
    assign bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q = {i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_63_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_62_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_61_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_60_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_59_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_58_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_57_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_56_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_55_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_54_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_53_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_52_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_51_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_50_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_49_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_48_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_47_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_46_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_45_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_44_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_43_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_42_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_41_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_40_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_39_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_38_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_37_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_36_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_35_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_34_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_33_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_32_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_31_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_30_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_29_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_28_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_27_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_26_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_25_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_24_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_23_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_22_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_21_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_20_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_19_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_18_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_17_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_16_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_15_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_14_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_13_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_12_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_11_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_10_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_9_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_8_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_7_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_6_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_5_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_4_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_3_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_2_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_1_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_readdata_0_tpl_reg1_q};

    // bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x(BITSELECT,319)
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_b = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[15:0]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_c = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[31:16]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_d = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[47:32]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_e = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[63:48]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_f = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[79:64]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_g = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[95:80]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_h = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[111:96]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_i = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[127:112]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_j = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[143:128]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_k = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[159:144]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_l = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[175:160]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_m = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[191:176]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_n = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[207:192]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_o = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[223:208]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_p = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[239:224]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[255:240]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_r = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[271:256]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_s = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[287:272]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_t = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[303:288]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_u = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[319:304]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_v = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[335:320]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_w = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[351:336]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_x = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[367:352]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_y = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[383:368]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_z = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[399:384]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_aa = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[415:400]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_bb = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[431:416]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_cc = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[447:432]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_dd = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[463:448]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ee = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[479:464]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ff = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[495:480]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_gg = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[511:496]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_hh = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[527:512]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ii = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[543:528]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_jj = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[559:544]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_kk = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[575:560]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ll = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[591:576]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_mm = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[607:592]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_nn = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[623:608]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_oo = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[639:624]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_pp = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[655:640]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_qq = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[671:656]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_rr = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[687:672]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ss = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[703:688]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_tt = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[719:704]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_uu = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[735:720]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_vv = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[751:736]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ww = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[767:752]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_xx = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[783:768]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_yy = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[799:784]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_zz = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[815:800]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_1 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[831:816]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_2 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[847:832]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_3 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[863:848]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_4 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[879:864]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_5 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[895:880]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_6 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[911:896]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_7 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[927:912]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_8 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[943:928]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_9 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[959:944]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_0 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[975:960]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_o61 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[991:976]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_o62 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[1007:992]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_o63 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q[1023:1008]);

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_63_tpl_reg0(REG,679)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_63_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_63_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_63_tpl_reg1(REG,678)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_63_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_63_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_62_tpl_reg0(REG,677)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_62_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_62_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_62_tpl_reg1(REG,676)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_62_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_62_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_61_tpl_reg0(REG,675)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_61_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_61_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_61_tpl_reg1(REG,674)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_61_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_61_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_60_tpl_reg0(REG,673)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_60_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_60_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_60_tpl_reg1(REG,672)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_60_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_60_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_59_tpl_reg0(REG,671)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_59_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_59_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_59_tpl_reg1(REG,670)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_59_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_59_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_58_tpl_reg0(REG,669)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_58_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_58_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_58_tpl_reg1(REG,668)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_58_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_58_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_57_tpl_reg0(REG,667)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_57_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_57_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_57_tpl_reg1(REG,666)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_57_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_57_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_56_tpl_reg0(REG,665)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_56_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_56_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_56_tpl_reg1(REG,664)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_56_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_56_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_55_tpl_reg0(REG,663)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_55_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_55_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_55_tpl_reg1(REG,662)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_55_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_55_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_54_tpl_reg0(REG,661)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_54_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_54_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_54_tpl_reg1(REG,660)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_54_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_54_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_53_tpl_reg0(REG,659)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_53_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_53_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_53_tpl_reg1(REG,658)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_53_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_53_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_52_tpl_reg0(REG,657)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_52_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_52_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_52_tpl_reg1(REG,656)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_52_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_52_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_51_tpl_reg0(REG,655)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_51_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_51_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_51_tpl_reg1(REG,654)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_51_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_51_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_50_tpl_reg0(REG,653)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_50_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_50_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_50_tpl_reg1(REG,652)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_50_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_50_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_49_tpl_reg0(REG,651)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_49_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_49_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_49_tpl_reg1(REG,650)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_49_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_49_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_48_tpl_reg0(REG,649)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_48_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_48_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_48_tpl_reg1(REG,648)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_48_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_48_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_47_tpl_reg0(REG,647)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_47_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_47_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_47_tpl_reg1(REG,646)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_47_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_47_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_46_tpl_reg0(REG,645)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_46_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_46_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_46_tpl_reg1(REG,644)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_46_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_46_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_45_tpl_reg0(REG,643)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_45_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_45_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_45_tpl_reg1(REG,642)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_45_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_45_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_44_tpl_reg0(REG,641)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_44_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_44_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_44_tpl_reg1(REG,640)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_44_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_44_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_43_tpl_reg0(REG,639)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_43_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_43_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_43_tpl_reg1(REG,638)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_43_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_43_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_42_tpl_reg0(REG,637)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_42_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_42_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_42_tpl_reg1(REG,636)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_42_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_42_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_41_tpl_reg0(REG,635)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_41_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_41_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_41_tpl_reg1(REG,634)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_41_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_41_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_40_tpl_reg0(REG,633)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_40_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_40_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_40_tpl_reg1(REG,632)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_40_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_40_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_39_tpl_reg0(REG,631)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_39_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_39_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_39_tpl_reg1(REG,630)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_39_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_39_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_38_tpl_reg0(REG,629)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_38_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_38_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_38_tpl_reg1(REG,628)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_38_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_38_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_37_tpl_reg0(REG,627)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_37_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_37_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_37_tpl_reg1(REG,626)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_37_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_37_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_36_tpl_reg0(REG,625)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_36_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_36_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_36_tpl_reg1(REG,624)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_36_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_36_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_35_tpl_reg0(REG,623)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_35_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_35_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_35_tpl_reg1(REG,622)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_35_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_35_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_34_tpl_reg0(REG,621)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_34_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_34_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_34_tpl_reg1(REG,620)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_34_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_34_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_33_tpl_reg0(REG,619)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_33_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_33_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_33_tpl_reg1(REG,618)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_33_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_33_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_32_tpl_reg0(REG,617)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_32_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_32_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_32_tpl_reg1(REG,616)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_32_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_32_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_31_tpl_reg0(REG,615)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_31_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_31_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_31_tpl_reg1(REG,614)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_31_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_31_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_30_tpl_reg0(REG,613)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_30_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_30_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_30_tpl_reg1(REG,612)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_30_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_30_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_29_tpl_reg0(REG,611)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_29_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_29_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_29_tpl_reg1(REG,610)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_29_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_29_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_28_tpl_reg0(REG,609)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_28_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_28_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_28_tpl_reg1(REG,608)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_28_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_28_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_27_tpl_reg0(REG,607)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_27_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_27_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_27_tpl_reg1(REG,606)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_27_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_27_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_26_tpl_reg0(REG,605)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_26_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_26_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_26_tpl_reg1(REG,604)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_26_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_26_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_25_tpl_reg0(REG,603)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_25_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_25_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_25_tpl_reg1(REG,602)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_25_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_25_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_24_tpl_reg0(REG,601)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_24_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_24_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_24_tpl_reg1(REG,600)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_24_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_24_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_23_tpl_reg0(REG,599)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_23_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_23_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_23_tpl_reg1(REG,598)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_23_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_23_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_22_tpl_reg0(REG,597)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_22_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_22_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_22_tpl_reg1(REG,596)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_22_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_22_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_21_tpl_reg0(REG,595)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_21_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_21_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_21_tpl_reg1(REG,594)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_21_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_21_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_20_tpl_reg0(REG,593)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_20_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_20_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_20_tpl_reg1(REG,592)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_20_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_20_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_19_tpl_reg0(REG,591)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_19_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_19_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_19_tpl_reg1(REG,590)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_19_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_19_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_18_tpl_reg0(REG,589)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_18_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_18_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_18_tpl_reg1(REG,588)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_18_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_18_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_17_tpl_reg0(REG,587)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_17_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_17_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_17_tpl_reg1(REG,586)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_17_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_17_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_16_tpl_reg0(REG,585)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_16_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_16_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_16_tpl_reg1(REG,584)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_16_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_16_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_15_tpl_reg0(REG,583)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_15_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_15_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_15_tpl_reg1(REG,582)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_15_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_15_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_14_tpl_reg0(REG,581)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_14_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_14_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_14_tpl_reg1(REG,580)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_14_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_14_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_13_tpl_reg0(REG,579)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_13_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_13_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_13_tpl_reg1(REG,578)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_13_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_13_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_12_tpl_reg0(REG,577)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_12_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_12_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_12_tpl_reg1(REG,576)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_12_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_12_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_11_tpl_reg0(REG,575)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_11_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_11_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_11_tpl_reg1(REG,574)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_11_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_11_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_10_tpl_reg0(REG,573)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_10_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_10_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_10_tpl_reg1(REG,572)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_10_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_10_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_9_tpl_reg0(REG,571)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_9_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_9_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_9_tpl_reg1(REG,570)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_9_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_9_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_8_tpl_reg0(REG,569)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_8_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_8_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_8_tpl_reg1(REG,568)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_8_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_8_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_7_tpl_reg0(REG,567)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_7_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_7_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_7_tpl_reg1(REG,566)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_7_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_7_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_6_tpl_reg0(REG,565)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_6_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_6_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_6_tpl_reg1(REG,564)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_6_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_6_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_5_tpl_reg0(REG,563)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_5_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_5_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_5_tpl_reg1(REG,562)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_5_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_5_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_4_tpl_reg0(REG,561)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_4_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_4_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_4_tpl_reg1(REG,560)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_4_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_4_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_3_tpl_reg0(REG,559)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_3_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_3_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_3_tpl_reg1(REG,558)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_3_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_3_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_2_tpl_reg0(REG,557)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_2_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_2_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_2_tpl_reg1(REG,556)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_2_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_2_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_1_tpl_reg0(REG,555)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_1_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_1_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_1_tpl_reg1(REG,554)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_1_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_1_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_0_tpl_reg0(REG,553)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_0_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_0_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_0_tpl_reg1(REG,552)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_0_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_0_tpl_reg0_q);
        end
    end

    // bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x(BITJOIN,315)
    assign bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q = {i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_63_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_62_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_61_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_60_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_59_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_58_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_57_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_56_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_55_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_54_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_53_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_52_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_51_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_50_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_49_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_48_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_47_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_46_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_45_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_44_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_43_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_42_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_41_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_40_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_39_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_38_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_37_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_36_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_35_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_34_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_33_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_32_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_31_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_30_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_29_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_28_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_27_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_26_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_25_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_24_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_23_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_22_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_21_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_20_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_19_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_18_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_17_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_16_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_15_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_14_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_13_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_12_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_11_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_10_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_9_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_8_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_7_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_6_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_5_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_4_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_3_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_2_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_1_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_0_tpl_reg1_q};

    // bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x(BITSELECT,316)
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_b = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[15:0]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_c = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[31:16]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_d = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[47:32]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_e = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[63:48]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_f = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[79:64]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_g = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[95:80]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_h = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[111:96]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_i = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[127:112]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_j = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[143:128]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_k = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[159:144]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_l = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[175:160]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_m = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[191:176]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_n = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[207:192]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_o = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[223:208]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_p = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[239:224]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[255:240]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_r = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[271:256]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_s = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[287:272]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_t = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[303:288]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_u = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[319:304]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_v = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[335:320]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_w = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[351:336]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_x = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[367:352]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_y = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[383:368]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_z = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[399:384]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_aa = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[415:400]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_bb = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[431:416]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_cc = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[447:432]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_dd = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[463:448]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ee = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[479:464]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ff = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[495:480]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_gg = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[511:496]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_hh = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[527:512]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ii = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[543:528]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_jj = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[559:544]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_kk = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[575:560]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ll = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[591:576]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_mm = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[607:592]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_nn = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[623:608]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_oo = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[639:624]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_pp = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[655:640]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_qq = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[671:656]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_rr = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[687:672]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ss = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[703:688]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_tt = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[719:704]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_uu = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[735:720]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_vv = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[751:736]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ww = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[767:752]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_xx = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[783:768]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_yy = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[799:784]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_zz = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[815:800]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_1 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[831:816]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_2 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[847:832]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_3 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[863:848]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_4 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[879:864]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_5 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[895:880]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_6 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[911:896]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_7 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[927:912]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_8 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[943:928]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_9 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[959:944]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_0 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[975:960]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_o61 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[991:976]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_o62 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[1007:992]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_o63 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q[1023:1008]);

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_63_tpl_reg0(REG,543)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_63_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_63_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_63_tpl_reg1(REG,542)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_63_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_63_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_62_tpl_reg0(REG,541)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_62_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_62_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_62_tpl_reg1(REG,540)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_62_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_62_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_61_tpl_reg0(REG,539)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_61_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_61_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_61_tpl_reg1(REG,538)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_61_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_61_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_60_tpl_reg0(REG,537)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_60_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_60_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_60_tpl_reg1(REG,536)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_60_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_60_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_59_tpl_reg0(REG,535)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_59_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_59_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_59_tpl_reg1(REG,534)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_59_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_59_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_58_tpl_reg0(REG,533)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_58_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_58_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_58_tpl_reg1(REG,532)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_58_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_58_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_57_tpl_reg0(REG,531)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_57_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_57_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_57_tpl_reg1(REG,530)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_57_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_57_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_56_tpl_reg0(REG,529)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_56_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_56_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_56_tpl_reg1(REG,528)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_56_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_56_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_55_tpl_reg0(REG,527)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_55_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_55_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_55_tpl_reg1(REG,526)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_55_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_55_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_54_tpl_reg0(REG,525)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_54_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_54_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_54_tpl_reg1(REG,524)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_54_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_54_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_53_tpl_reg0(REG,523)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_53_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_53_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_53_tpl_reg1(REG,522)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_53_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_53_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_52_tpl_reg0(REG,521)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_52_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_52_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_52_tpl_reg1(REG,520)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_52_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_52_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_51_tpl_reg0(REG,519)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_51_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_51_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_51_tpl_reg1(REG,518)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_51_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_51_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_50_tpl_reg0(REG,517)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_50_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_50_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_50_tpl_reg1(REG,516)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_50_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_50_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_49_tpl_reg0(REG,515)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_49_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_49_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_49_tpl_reg1(REG,514)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_49_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_49_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_48_tpl_reg0(REG,513)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_48_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_48_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_48_tpl_reg1(REG,512)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_48_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_48_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_47_tpl_reg0(REG,511)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_47_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_47_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_47_tpl_reg1(REG,510)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_47_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_47_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_46_tpl_reg0(REG,509)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_46_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_46_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_46_tpl_reg1(REG,508)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_46_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_46_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_45_tpl_reg0(REG,507)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_45_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_45_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_45_tpl_reg1(REG,506)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_45_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_45_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_44_tpl_reg0(REG,505)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_44_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_44_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_44_tpl_reg1(REG,504)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_44_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_44_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_43_tpl_reg0(REG,503)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_43_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_43_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_43_tpl_reg1(REG,502)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_43_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_43_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_42_tpl_reg0(REG,501)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_42_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_42_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_42_tpl_reg1(REG,500)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_42_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_42_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_41_tpl_reg0(REG,499)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_41_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_41_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_41_tpl_reg1(REG,498)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_41_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_41_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_40_tpl_reg0(REG,497)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_40_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_40_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_40_tpl_reg1(REG,496)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_40_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_40_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_39_tpl_reg0(REG,495)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_39_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_39_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_39_tpl_reg1(REG,494)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_39_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_39_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_38_tpl_reg0(REG,493)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_38_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_38_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_38_tpl_reg1(REG,492)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_38_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_38_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_37_tpl_reg0(REG,491)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_37_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_37_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_37_tpl_reg1(REG,490)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_37_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_37_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_36_tpl_reg0(REG,489)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_36_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_36_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_36_tpl_reg1(REG,488)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_36_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_36_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_35_tpl_reg0(REG,487)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_35_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_35_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_35_tpl_reg1(REG,486)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_35_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_35_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_34_tpl_reg0(REG,485)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_34_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_34_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_34_tpl_reg1(REG,484)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_34_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_34_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_33_tpl_reg0(REG,483)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_33_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_33_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_33_tpl_reg1(REG,482)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_33_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_33_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_32_tpl_reg0(REG,481)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_32_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_32_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_32_tpl_reg1(REG,480)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_32_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_32_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_31_tpl_reg0(REG,479)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_31_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_31_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_31_tpl_reg1(REG,478)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_31_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_31_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_30_tpl_reg0(REG,477)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_30_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_30_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_30_tpl_reg1(REG,476)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_30_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_30_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_29_tpl_reg0(REG,475)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_29_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_29_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_29_tpl_reg1(REG,474)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_29_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_29_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_28_tpl_reg0(REG,473)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_28_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_28_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_28_tpl_reg1(REG,472)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_28_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_28_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_27_tpl_reg0(REG,471)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_27_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_27_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_27_tpl_reg1(REG,470)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_27_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_27_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_26_tpl_reg0(REG,469)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_26_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_26_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_26_tpl_reg1(REG,468)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_26_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_26_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_25_tpl_reg0(REG,467)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_25_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_25_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_25_tpl_reg1(REG,466)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_25_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_25_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_24_tpl_reg0(REG,465)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_24_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_24_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_24_tpl_reg1(REG,464)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_24_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_24_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_23_tpl_reg0(REG,463)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_23_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_23_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_23_tpl_reg1(REG,462)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_23_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_23_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_22_tpl_reg0(REG,461)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_22_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_22_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_22_tpl_reg1(REG,460)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_22_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_22_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_21_tpl_reg0(REG,459)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_21_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_21_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_21_tpl_reg1(REG,458)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_21_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_21_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_20_tpl_reg0(REG,457)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_20_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_20_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_20_tpl_reg1(REG,456)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_20_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_20_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_19_tpl_reg0(REG,455)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_19_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_19_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_19_tpl_reg1(REG,454)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_19_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_19_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_18_tpl_reg0(REG,453)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_18_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_18_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_18_tpl_reg1(REG,452)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_18_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_18_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_17_tpl_reg0(REG,451)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_17_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_17_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_17_tpl_reg1(REG,450)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_17_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_17_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_16_tpl_reg0(REG,449)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_16_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_16_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_16_tpl_reg1(REG,448)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_16_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_16_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_15_tpl_reg0(REG,447)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_15_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_15_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_15_tpl_reg1(REG,446)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_15_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_15_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_14_tpl_reg0(REG,445)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_14_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_14_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_14_tpl_reg1(REG,444)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_14_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_14_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_13_tpl_reg0(REG,443)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_13_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_13_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_13_tpl_reg1(REG,442)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_13_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_13_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_12_tpl_reg0(REG,441)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_12_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_12_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_12_tpl_reg1(REG,440)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_12_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_12_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_11_tpl_reg0(REG,439)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_11_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_11_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_11_tpl_reg1(REG,438)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_11_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_11_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_10_tpl_reg0(REG,437)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_10_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_10_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_10_tpl_reg1(REG,436)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_10_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_10_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_9_tpl_reg0(REG,435)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_9_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_9_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_9_tpl_reg1(REG,434)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_9_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_9_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_8_tpl_reg0(REG,433)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_8_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_8_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_8_tpl_reg1(REG,432)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_8_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_8_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_7_tpl_reg0(REG,431)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_7_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_7_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_7_tpl_reg1(REG,430)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_7_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_7_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_6_tpl_reg0(REG,429)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_6_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_6_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_6_tpl_reg1(REG,428)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_6_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_6_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_5_tpl_reg0(REG,427)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_5_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_5_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_5_tpl_reg1(REG,426)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_5_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_5_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_4_tpl_reg0(REG,425)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_4_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_4_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_4_tpl_reg1(REG,424)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_4_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_4_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_3_tpl_reg0(REG,423)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_3_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_3_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_3_tpl_reg1(REG,422)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_3_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_3_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_2_tpl_reg0(REG,421)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_2_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_2_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_2_tpl_reg1(REG,420)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_2_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_2_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_1_tpl_reg0(REG,419)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_1_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_1_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_1_tpl_reg1(REG,418)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_1_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_1_tpl_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_0_tpl_reg0(REG,417)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_0_tpl_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_0_tpl);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_0_tpl_reg1(REG,416)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_0_tpl_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_0_tpl_reg0_q);
        end
    end

    // bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x(BITJOIN,312)
    assign bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q = {i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_63_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_62_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_61_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_60_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_59_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_58_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_57_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_56_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_55_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_54_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_53_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_52_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_51_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_50_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_49_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_48_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_47_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_46_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_45_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_44_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_43_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_42_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_41_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_40_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_39_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_38_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_37_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_36_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_35_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_34_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_33_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_32_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_31_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_30_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_29_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_28_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_27_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_26_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_25_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_24_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_23_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_22_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_21_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_20_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_19_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_18_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_17_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_16_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_15_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_14_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_13_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_12_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_11_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_10_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_9_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_8_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_7_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_6_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_5_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_4_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_3_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_2_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_1_tpl_reg1_q, i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_readdata_0_tpl_reg1_q};

    // bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x(BITSELECT,313)
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_b = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[15:0]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_c = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[31:16]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_d = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[47:32]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_e = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[63:48]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_f = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[79:64]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_g = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[95:80]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_h = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[111:96]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_i = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[127:112]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_j = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[143:128]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_k = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[159:144]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_l = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[175:160]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_m = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[191:176]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_n = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[207:192]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_o = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[223:208]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_p = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[239:224]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[255:240]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_r = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[271:256]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_s = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[287:272]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_t = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[303:288]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_u = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[319:304]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_v = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[335:320]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_w = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[351:336]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_x = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[367:352]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_y = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[383:368]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_z = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[399:384]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_aa = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[415:400]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_bb = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[431:416]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_cc = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[447:432]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_dd = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[463:448]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ee = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[479:464]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ff = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[495:480]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_gg = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[511:496]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_hh = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[527:512]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ii = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[543:528]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_jj = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[559:544]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_kk = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[575:560]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ll = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[591:576]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_mm = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[607:592]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_nn = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[623:608]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_oo = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[639:624]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_pp = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[655:640]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_qq = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[671:656]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_rr = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[687:672]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ss = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[703:688]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_tt = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[719:704]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_uu = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[735:720]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_vv = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[751:736]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ww = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[767:752]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_xx = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[783:768]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_yy = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[799:784]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_zz = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[815:800]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_1 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[831:816]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_2 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[847:832]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_3 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[863:848]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_4 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[879:864]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_5 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[895:880]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_6 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[911:896]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_7 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[927:912]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_8 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[943:928]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_9 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[959:944]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_0 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[975:960]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_o61 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[991:976]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_o62 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[1007:992]);
    assign bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_o63 = $unsigned(bubble_join_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q[1023:1008]);

    // i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x(BLACKBOX,18)@68
    // in in_i_stall@20000000
    // out out_c1_exit927_0_tpl@360
    // out out_c1_exit927_1_tpl@360
    // out out_c1_exit927_2_tpl@360
    // out out_c1_exit927_3_tpl@360
    // out out_almost_empty_out@360
    // out out_empty_out@360
    // out out_o_stall@20000000
    // out out_o_valid@360
    c_compMM_m_i_sfc_s_c1_in_for_body_c_comp0000enter923_c_compmm_m8 thei_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x (
        .in_c1_eni5_0_tpl(GND_q),
        .in_c1_eni5_1_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_b),
        .in_c1_eni5_2_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_c),
        .in_c1_eni5_3_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_d),
        .in_c1_eni5_4_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_e),
        .in_c1_eni5_5_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_f),
        .in_c1_eni5_6_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_g),
        .in_c1_eni5_7_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_h),
        .in_c1_eni5_8_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_i),
        .in_c1_eni5_9_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_j),
        .in_c1_eni5_10_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_k),
        .in_c1_eni5_11_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_l),
        .in_c1_eni5_12_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_m),
        .in_c1_eni5_13_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_n),
        .in_c1_eni5_14_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_o),
        .in_c1_eni5_15_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_p),
        .in_c1_eni5_16_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_q),
        .in_c1_eni5_17_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_r),
        .in_c1_eni5_18_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_s),
        .in_c1_eni5_19_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_t),
        .in_c1_eni5_20_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_u),
        .in_c1_eni5_21_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_v),
        .in_c1_eni5_22_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_w),
        .in_c1_eni5_23_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_x),
        .in_c1_eni5_24_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_y),
        .in_c1_eni5_25_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_z),
        .in_c1_eni5_26_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_aa),
        .in_c1_eni5_27_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_bb),
        .in_c1_eni5_28_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_cc),
        .in_c1_eni5_29_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_dd),
        .in_c1_eni5_30_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ee),
        .in_c1_eni5_31_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ff),
        .in_c1_eni5_32_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_gg),
        .in_c1_eni5_33_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_hh),
        .in_c1_eni5_34_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ii),
        .in_c1_eni5_35_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_jj),
        .in_c1_eni5_36_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_kk),
        .in_c1_eni5_37_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ll),
        .in_c1_eni5_38_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_mm),
        .in_c1_eni5_39_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_nn),
        .in_c1_eni5_40_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_oo),
        .in_c1_eni5_41_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_pp),
        .in_c1_eni5_42_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_qq),
        .in_c1_eni5_43_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_rr),
        .in_c1_eni5_44_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ss),
        .in_c1_eni5_45_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_tt),
        .in_c1_eni5_46_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_uu),
        .in_c1_eni5_47_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_vv),
        .in_c1_eni5_48_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_ww),
        .in_c1_eni5_49_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_xx),
        .in_c1_eni5_50_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_yy),
        .in_c1_eni5_51_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_zz),
        .in_c1_eni5_52_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_1),
        .in_c1_eni5_53_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_2),
        .in_c1_eni5_54_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_3),
        .in_c1_eni5_55_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_4),
        .in_c1_eni5_56_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_5),
        .in_c1_eni5_57_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_6),
        .in_c1_eni5_58_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_7),
        .in_c1_eni5_59_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_8),
        .in_c1_eni5_60_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_9),
        .in_c1_eni5_61_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_0),
        .in_c1_eni5_62_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_o61),
        .in_c1_eni5_63_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_o62),
        .in_c1_eni5_64_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_o63),
        .in_c1_eni5_65_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_b),
        .in_c1_eni5_66_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_c),
        .in_c1_eni5_67_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_d),
        .in_c1_eni5_68_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_e),
        .in_c1_eni5_69_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_f),
        .in_c1_eni5_70_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_g),
        .in_c1_eni5_71_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_h),
        .in_c1_eni5_72_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_i),
        .in_c1_eni5_73_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_j),
        .in_c1_eni5_74_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_k),
        .in_c1_eni5_75_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_l),
        .in_c1_eni5_76_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_m),
        .in_c1_eni5_77_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_n),
        .in_c1_eni5_78_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_o),
        .in_c1_eni5_79_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_p),
        .in_c1_eni5_80_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_q),
        .in_c1_eni5_81_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_r),
        .in_c1_eni5_82_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_s),
        .in_c1_eni5_83_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_t),
        .in_c1_eni5_84_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_u),
        .in_c1_eni5_85_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_v),
        .in_c1_eni5_86_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_w),
        .in_c1_eni5_87_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_x),
        .in_c1_eni5_88_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_y),
        .in_c1_eni5_89_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_z),
        .in_c1_eni5_90_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_aa),
        .in_c1_eni5_91_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_bb),
        .in_c1_eni5_92_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_cc),
        .in_c1_eni5_93_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_dd),
        .in_c1_eni5_94_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ee),
        .in_c1_eni5_95_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ff),
        .in_c1_eni5_96_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_gg),
        .in_c1_eni5_97_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_hh),
        .in_c1_eni5_98_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ii),
        .in_c1_eni5_99_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_jj),
        .in_c1_eni5_100_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_kk),
        .in_c1_eni5_101_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ll),
        .in_c1_eni5_102_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_mm),
        .in_c1_eni5_103_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_nn),
        .in_c1_eni5_104_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_oo),
        .in_c1_eni5_105_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_pp),
        .in_c1_eni5_106_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_qq),
        .in_c1_eni5_107_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_rr),
        .in_c1_eni5_108_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ss),
        .in_c1_eni5_109_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_tt),
        .in_c1_eni5_110_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_uu),
        .in_c1_eni5_111_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_vv),
        .in_c1_eni5_112_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_ww),
        .in_c1_eni5_113_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_xx),
        .in_c1_eni5_114_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_yy),
        .in_c1_eni5_115_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_zz),
        .in_c1_eni5_116_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_1),
        .in_c1_eni5_117_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_2),
        .in_c1_eni5_118_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_3),
        .in_c1_eni5_119_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_4),
        .in_c1_eni5_120_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_5),
        .in_c1_eni5_121_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_6),
        .in_c1_eni5_122_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_7),
        .in_c1_eni5_123_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_8),
        .in_c1_eni5_124_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_9),
        .in_c1_eni5_125_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_0),
        .in_c1_eni5_126_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_o61),
        .in_c1_eni5_127_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_o62),
        .in_c1_eni5_128_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_o63),
        .in_c1_eni5_129_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_b),
        .in_c1_eni5_130_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_c),
        .in_c1_eni5_131_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_d),
        .in_c1_eni5_132_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_e),
        .in_c1_eni5_133_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_f),
        .in_c1_eni5_134_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_g),
        .in_c1_eni5_135_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_h),
        .in_c1_eni5_136_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_i),
        .in_c1_eni5_137_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_j),
        .in_c1_eni5_138_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_k),
        .in_c1_eni5_139_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_l),
        .in_c1_eni5_140_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_m),
        .in_c1_eni5_141_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_n),
        .in_c1_eni5_142_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_o),
        .in_c1_eni5_143_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_p),
        .in_c1_eni5_144_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_q),
        .in_c1_eni5_145_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_r),
        .in_c1_eni5_146_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_s),
        .in_c1_eni5_147_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_t),
        .in_c1_eni5_148_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_u),
        .in_c1_eni5_149_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_v),
        .in_c1_eni5_150_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_w),
        .in_c1_eni5_151_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_x),
        .in_c1_eni5_152_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_y),
        .in_c1_eni5_153_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_z),
        .in_c1_eni5_154_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_aa),
        .in_c1_eni5_155_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_bb),
        .in_c1_eni5_156_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_cc),
        .in_c1_eni5_157_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_dd),
        .in_c1_eni5_158_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ee),
        .in_c1_eni5_159_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ff),
        .in_c1_eni5_160_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_gg),
        .in_c1_eni5_161_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_hh),
        .in_c1_eni5_162_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ii),
        .in_c1_eni5_163_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_jj),
        .in_c1_eni5_164_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_kk),
        .in_c1_eni5_165_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ll),
        .in_c1_eni5_166_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_mm),
        .in_c1_eni5_167_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_nn),
        .in_c1_eni5_168_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_oo),
        .in_c1_eni5_169_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_pp),
        .in_c1_eni5_170_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_qq),
        .in_c1_eni5_171_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_rr),
        .in_c1_eni5_172_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ss),
        .in_c1_eni5_173_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_tt),
        .in_c1_eni5_174_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_uu),
        .in_c1_eni5_175_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_vv),
        .in_c1_eni5_176_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_ww),
        .in_c1_eni5_177_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_xx),
        .in_c1_eni5_178_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_yy),
        .in_c1_eni5_179_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_zz),
        .in_c1_eni5_180_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_1),
        .in_c1_eni5_181_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_2),
        .in_c1_eni5_182_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_3),
        .in_c1_eni5_183_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_4),
        .in_c1_eni5_184_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_5),
        .in_c1_eni5_185_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_6),
        .in_c1_eni5_186_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_7),
        .in_c1_eni5_187_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_8),
        .in_c1_eni5_188_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_9),
        .in_c1_eni5_189_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_0),
        .in_c1_eni5_190_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_o61),
        .in_c1_eni5_191_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_o62),
        .in_c1_eni5_192_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_o63),
        .in_c1_eni5_193_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_b),
        .in_c1_eni5_194_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_c),
        .in_c1_eni5_195_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_d),
        .in_c1_eni5_196_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_e),
        .in_c1_eni5_197_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_f),
        .in_c1_eni5_198_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_g),
        .in_c1_eni5_199_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_h),
        .in_c1_eni5_200_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_i),
        .in_c1_eni5_201_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_j),
        .in_c1_eni5_202_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_k),
        .in_c1_eni5_203_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_l),
        .in_c1_eni5_204_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_m),
        .in_c1_eni5_205_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_n),
        .in_c1_eni5_206_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_o),
        .in_c1_eni5_207_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_p),
        .in_c1_eni5_208_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_q),
        .in_c1_eni5_209_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_r),
        .in_c1_eni5_210_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_s),
        .in_c1_eni5_211_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_t),
        .in_c1_eni5_212_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_u),
        .in_c1_eni5_213_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_v),
        .in_c1_eni5_214_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_w),
        .in_c1_eni5_215_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_x),
        .in_c1_eni5_216_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_y),
        .in_c1_eni5_217_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_z),
        .in_c1_eni5_218_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_aa),
        .in_c1_eni5_219_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_bb),
        .in_c1_eni5_220_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_cc),
        .in_c1_eni5_221_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_dd),
        .in_c1_eni5_222_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ee),
        .in_c1_eni5_223_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ff),
        .in_c1_eni5_224_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_gg),
        .in_c1_eni5_225_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_hh),
        .in_c1_eni5_226_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ii),
        .in_c1_eni5_227_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_jj),
        .in_c1_eni5_228_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_kk),
        .in_c1_eni5_229_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ll),
        .in_c1_eni5_230_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_mm),
        .in_c1_eni5_231_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_nn),
        .in_c1_eni5_232_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_oo),
        .in_c1_eni5_233_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_pp),
        .in_c1_eni5_234_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_qq),
        .in_c1_eni5_235_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_rr),
        .in_c1_eni5_236_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ss),
        .in_c1_eni5_237_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_tt),
        .in_c1_eni5_238_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_uu),
        .in_c1_eni5_239_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_vv),
        .in_c1_eni5_240_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_ww),
        .in_c1_eni5_241_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_xx),
        .in_c1_eni5_242_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_yy),
        .in_c1_eni5_243_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_zz),
        .in_c1_eni5_244_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_1),
        .in_c1_eni5_245_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_2),
        .in_c1_eni5_246_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_3),
        .in_c1_eni5_247_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_4),
        .in_c1_eni5_248_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_5),
        .in_c1_eni5_249_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_6),
        .in_c1_eni5_250_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_7),
        .in_c1_eni5_251_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_8),
        .in_c1_eni5_252_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_9),
        .in_c1_eni5_253_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_0),
        .in_c1_eni5_254_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_o61),
        .in_c1_eni5_255_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_o62),
        .in_c1_eni5_256_tpl(bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_o63),
        .in_c1_eni5_257_tpl(bubble_select_redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_b),
        .in_almost_empty_in(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V2),
        .in_empty_in(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V1),
        .in_i_stall(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_in_i_stall_reg1_q),
        .in_i_valid(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0_sync_valid_reg6_q),
        .in_intel_reserved_ffwd_100_0(in_intel_reserved_ffwd_100_0),
        .in_intel_reserved_ffwd_101_0(in_intel_reserved_ffwd_101_0),
        .in_intel_reserved_ffwd_102_0(in_intel_reserved_ffwd_102_0),
        .in_intel_reserved_ffwd_103_0(in_intel_reserved_ffwd_103_0),
        .in_intel_reserved_ffwd_104_0(in_intel_reserved_ffwd_104_0),
        .in_intel_reserved_ffwd_105_0(in_intel_reserved_ffwd_105_0),
        .in_intel_reserved_ffwd_106_0(in_intel_reserved_ffwd_106_0),
        .in_intel_reserved_ffwd_107_0(in_intel_reserved_ffwd_107_0),
        .in_intel_reserved_ffwd_108_0(in_intel_reserved_ffwd_108_0),
        .in_intel_reserved_ffwd_109_0(in_intel_reserved_ffwd_109_0),
        .in_intel_reserved_ffwd_10_0(in_intel_reserved_ffwd_10_0),
        .in_intel_reserved_ffwd_110_0(in_intel_reserved_ffwd_110_0),
        .in_intel_reserved_ffwd_111_0(in_intel_reserved_ffwd_111_0),
        .in_intel_reserved_ffwd_112_0(in_intel_reserved_ffwd_112_0),
        .in_intel_reserved_ffwd_113_0(in_intel_reserved_ffwd_113_0),
        .in_intel_reserved_ffwd_114_0(in_intel_reserved_ffwd_114_0),
        .in_intel_reserved_ffwd_115_0(in_intel_reserved_ffwd_115_0),
        .in_intel_reserved_ffwd_116_0(in_intel_reserved_ffwd_116_0),
        .in_intel_reserved_ffwd_117_0(in_intel_reserved_ffwd_117_0),
        .in_intel_reserved_ffwd_118_0(in_intel_reserved_ffwd_118_0),
        .in_intel_reserved_ffwd_119_0(in_intel_reserved_ffwd_119_0),
        .in_intel_reserved_ffwd_11_0(in_intel_reserved_ffwd_11_0),
        .in_intel_reserved_ffwd_120_0(in_intel_reserved_ffwd_120_0),
        .in_intel_reserved_ffwd_121_0(in_intel_reserved_ffwd_121_0),
        .in_intel_reserved_ffwd_122_0(in_intel_reserved_ffwd_122_0),
        .in_intel_reserved_ffwd_123_0(in_intel_reserved_ffwd_123_0),
        .in_intel_reserved_ffwd_124_0(in_intel_reserved_ffwd_124_0),
        .in_intel_reserved_ffwd_125_0(in_intel_reserved_ffwd_125_0),
        .in_intel_reserved_ffwd_126_0(in_intel_reserved_ffwd_126_0),
        .in_intel_reserved_ffwd_127_0(in_intel_reserved_ffwd_127_0),
        .in_intel_reserved_ffwd_128_0(in_intel_reserved_ffwd_128_0),
        .in_intel_reserved_ffwd_129_0(in_intel_reserved_ffwd_129_0),
        .in_intel_reserved_ffwd_12_0(in_intel_reserved_ffwd_12_0),
        .in_intel_reserved_ffwd_130_0(in_intel_reserved_ffwd_130_0),
        .in_intel_reserved_ffwd_131_0(in_intel_reserved_ffwd_131_0),
        .in_intel_reserved_ffwd_132_0(in_intel_reserved_ffwd_132_0),
        .in_intel_reserved_ffwd_133_0(in_intel_reserved_ffwd_133_0),
        .in_intel_reserved_ffwd_134_0(in_intel_reserved_ffwd_134_0),
        .in_intel_reserved_ffwd_135_0(in_intel_reserved_ffwd_135_0),
        .in_intel_reserved_ffwd_136_0(in_intel_reserved_ffwd_136_0),
        .in_intel_reserved_ffwd_137_0(in_intel_reserved_ffwd_137_0),
        .in_intel_reserved_ffwd_138_0(in_intel_reserved_ffwd_138_0),
        .in_intel_reserved_ffwd_139_0(in_intel_reserved_ffwd_139_0),
        .in_intel_reserved_ffwd_13_0(in_intel_reserved_ffwd_13_0),
        .in_intel_reserved_ffwd_140_0(in_intel_reserved_ffwd_140_0),
        .in_intel_reserved_ffwd_141_0(in_intel_reserved_ffwd_141_0),
        .in_intel_reserved_ffwd_142_0(in_intel_reserved_ffwd_142_0),
        .in_intel_reserved_ffwd_143_0(in_intel_reserved_ffwd_143_0),
        .in_intel_reserved_ffwd_144_0(in_intel_reserved_ffwd_144_0),
        .in_intel_reserved_ffwd_145_0(in_intel_reserved_ffwd_145_0),
        .in_intel_reserved_ffwd_146_0(in_intel_reserved_ffwd_146_0),
        .in_intel_reserved_ffwd_147_0(in_intel_reserved_ffwd_147_0),
        .in_intel_reserved_ffwd_148_0(in_intel_reserved_ffwd_148_0),
        .in_intel_reserved_ffwd_149_0(in_intel_reserved_ffwd_149_0),
        .in_intel_reserved_ffwd_14_0(in_intel_reserved_ffwd_14_0),
        .in_intel_reserved_ffwd_150_0(in_intel_reserved_ffwd_150_0),
        .in_intel_reserved_ffwd_151_0(in_intel_reserved_ffwd_151_0),
        .in_intel_reserved_ffwd_152_0(in_intel_reserved_ffwd_152_0),
        .in_intel_reserved_ffwd_153_0(in_intel_reserved_ffwd_153_0),
        .in_intel_reserved_ffwd_154_0(in_intel_reserved_ffwd_154_0),
        .in_intel_reserved_ffwd_155_0(in_intel_reserved_ffwd_155_0),
        .in_intel_reserved_ffwd_156_0(in_intel_reserved_ffwd_156_0),
        .in_intel_reserved_ffwd_157_0(in_intel_reserved_ffwd_157_0),
        .in_intel_reserved_ffwd_158_0(in_intel_reserved_ffwd_158_0),
        .in_intel_reserved_ffwd_159_0(in_intel_reserved_ffwd_159_0),
        .in_intel_reserved_ffwd_15_0(in_intel_reserved_ffwd_15_0),
        .in_intel_reserved_ffwd_160_0(in_intel_reserved_ffwd_160_0),
        .in_intel_reserved_ffwd_161_0(in_intel_reserved_ffwd_161_0),
        .in_intel_reserved_ffwd_162_0(in_intel_reserved_ffwd_162_0),
        .in_intel_reserved_ffwd_163_0(in_intel_reserved_ffwd_163_0),
        .in_intel_reserved_ffwd_164_0(in_intel_reserved_ffwd_164_0),
        .in_intel_reserved_ffwd_165_0(in_intel_reserved_ffwd_165_0),
        .in_intel_reserved_ffwd_166_0(in_intel_reserved_ffwd_166_0),
        .in_intel_reserved_ffwd_167_0(in_intel_reserved_ffwd_167_0),
        .in_intel_reserved_ffwd_168_0(in_intel_reserved_ffwd_168_0),
        .in_intel_reserved_ffwd_169_0(in_intel_reserved_ffwd_169_0),
        .in_intel_reserved_ffwd_16_0(in_intel_reserved_ffwd_16_0),
        .in_intel_reserved_ffwd_170_0(in_intel_reserved_ffwd_170_0),
        .in_intel_reserved_ffwd_171_0(in_intel_reserved_ffwd_171_0),
        .in_intel_reserved_ffwd_172_0(in_intel_reserved_ffwd_172_0),
        .in_intel_reserved_ffwd_173_0(in_intel_reserved_ffwd_173_0),
        .in_intel_reserved_ffwd_174_0(in_intel_reserved_ffwd_174_0),
        .in_intel_reserved_ffwd_175_0(in_intel_reserved_ffwd_175_0),
        .in_intel_reserved_ffwd_176_0(in_intel_reserved_ffwd_176_0),
        .in_intel_reserved_ffwd_177_0(in_intel_reserved_ffwd_177_0),
        .in_intel_reserved_ffwd_178_0(in_intel_reserved_ffwd_178_0),
        .in_intel_reserved_ffwd_179_0(in_intel_reserved_ffwd_179_0),
        .in_intel_reserved_ffwd_17_0(in_intel_reserved_ffwd_17_0),
        .in_intel_reserved_ffwd_180_0(in_intel_reserved_ffwd_180_0),
        .in_intel_reserved_ffwd_181_0(in_intel_reserved_ffwd_181_0),
        .in_intel_reserved_ffwd_182_0(in_intel_reserved_ffwd_182_0),
        .in_intel_reserved_ffwd_183_0(in_intel_reserved_ffwd_183_0),
        .in_intel_reserved_ffwd_184_0(in_intel_reserved_ffwd_184_0),
        .in_intel_reserved_ffwd_185_0(in_intel_reserved_ffwd_185_0),
        .in_intel_reserved_ffwd_186_0(in_intel_reserved_ffwd_186_0),
        .in_intel_reserved_ffwd_187_0(in_intel_reserved_ffwd_187_0),
        .in_intel_reserved_ffwd_188_0(in_intel_reserved_ffwd_188_0),
        .in_intel_reserved_ffwd_189_0(in_intel_reserved_ffwd_189_0),
        .in_intel_reserved_ffwd_18_0(in_intel_reserved_ffwd_18_0),
        .in_intel_reserved_ffwd_190_0(in_intel_reserved_ffwd_190_0),
        .in_intel_reserved_ffwd_191_0(in_intel_reserved_ffwd_191_0),
        .in_intel_reserved_ffwd_192_0(in_intel_reserved_ffwd_192_0),
        .in_intel_reserved_ffwd_193_0(in_intel_reserved_ffwd_193_0),
        .in_intel_reserved_ffwd_194_0(in_intel_reserved_ffwd_194_0),
        .in_intel_reserved_ffwd_195_0(in_intel_reserved_ffwd_195_0),
        .in_intel_reserved_ffwd_196_0(in_intel_reserved_ffwd_196_0),
        .in_intel_reserved_ffwd_197_0(in_intel_reserved_ffwd_197_0),
        .in_intel_reserved_ffwd_198_0(in_intel_reserved_ffwd_198_0),
        .in_intel_reserved_ffwd_199_0(in_intel_reserved_ffwd_199_0),
        .in_intel_reserved_ffwd_19_0(in_intel_reserved_ffwd_19_0),
        .in_intel_reserved_ffwd_1_0(in_intel_reserved_ffwd_1_0),
        .in_intel_reserved_ffwd_200_0(in_intel_reserved_ffwd_200_0),
        .in_intel_reserved_ffwd_201_0(in_intel_reserved_ffwd_201_0),
        .in_intel_reserved_ffwd_202_0(in_intel_reserved_ffwd_202_0),
        .in_intel_reserved_ffwd_203_0(in_intel_reserved_ffwd_203_0),
        .in_intel_reserved_ffwd_204_0(in_intel_reserved_ffwd_204_0),
        .in_intel_reserved_ffwd_205_0(in_intel_reserved_ffwd_205_0),
        .in_intel_reserved_ffwd_206_0(in_intel_reserved_ffwd_206_0),
        .in_intel_reserved_ffwd_207_0(in_intel_reserved_ffwd_207_0),
        .in_intel_reserved_ffwd_208_0(in_intel_reserved_ffwd_208_0),
        .in_intel_reserved_ffwd_209_0(in_intel_reserved_ffwd_209_0),
        .in_intel_reserved_ffwd_20_0(in_intel_reserved_ffwd_20_0),
        .in_intel_reserved_ffwd_210_0(in_intel_reserved_ffwd_210_0),
        .in_intel_reserved_ffwd_211_0(in_intel_reserved_ffwd_211_0),
        .in_intel_reserved_ffwd_212_0(in_intel_reserved_ffwd_212_0),
        .in_intel_reserved_ffwd_213_0(in_intel_reserved_ffwd_213_0),
        .in_intel_reserved_ffwd_214_0(in_intel_reserved_ffwd_214_0),
        .in_intel_reserved_ffwd_215_0(in_intel_reserved_ffwd_215_0),
        .in_intel_reserved_ffwd_216_0(in_intel_reserved_ffwd_216_0),
        .in_intel_reserved_ffwd_217_0(in_intel_reserved_ffwd_217_0),
        .in_intel_reserved_ffwd_218_0(in_intel_reserved_ffwd_218_0),
        .in_intel_reserved_ffwd_219_0(in_intel_reserved_ffwd_219_0),
        .in_intel_reserved_ffwd_21_0(in_intel_reserved_ffwd_21_0),
        .in_intel_reserved_ffwd_220_0(in_intel_reserved_ffwd_220_0),
        .in_intel_reserved_ffwd_221_0(in_intel_reserved_ffwd_221_0),
        .in_intel_reserved_ffwd_222_0(in_intel_reserved_ffwd_222_0),
        .in_intel_reserved_ffwd_223_0(in_intel_reserved_ffwd_223_0),
        .in_intel_reserved_ffwd_224_0(in_intel_reserved_ffwd_224_0),
        .in_intel_reserved_ffwd_225_0(in_intel_reserved_ffwd_225_0),
        .in_intel_reserved_ffwd_226_0(in_intel_reserved_ffwd_226_0),
        .in_intel_reserved_ffwd_227_0(in_intel_reserved_ffwd_227_0),
        .in_intel_reserved_ffwd_228_0(in_intel_reserved_ffwd_228_0),
        .in_intel_reserved_ffwd_229_0(in_intel_reserved_ffwd_229_0),
        .in_intel_reserved_ffwd_22_0(in_intel_reserved_ffwd_22_0),
        .in_intel_reserved_ffwd_230_0(in_intel_reserved_ffwd_230_0),
        .in_intel_reserved_ffwd_231_0(in_intel_reserved_ffwd_231_0),
        .in_intel_reserved_ffwd_232_0(in_intel_reserved_ffwd_232_0),
        .in_intel_reserved_ffwd_233_0(in_intel_reserved_ffwd_233_0),
        .in_intel_reserved_ffwd_234_0(in_intel_reserved_ffwd_234_0),
        .in_intel_reserved_ffwd_235_0(in_intel_reserved_ffwd_235_0),
        .in_intel_reserved_ffwd_236_0(in_intel_reserved_ffwd_236_0),
        .in_intel_reserved_ffwd_237_0(in_intel_reserved_ffwd_237_0),
        .in_intel_reserved_ffwd_238_0(in_intel_reserved_ffwd_238_0),
        .in_intel_reserved_ffwd_239_0(in_intel_reserved_ffwd_239_0),
        .in_intel_reserved_ffwd_23_0(in_intel_reserved_ffwd_23_0),
        .in_intel_reserved_ffwd_240_0(in_intel_reserved_ffwd_240_0),
        .in_intel_reserved_ffwd_241_0(in_intel_reserved_ffwd_241_0),
        .in_intel_reserved_ffwd_242_0(in_intel_reserved_ffwd_242_0),
        .in_intel_reserved_ffwd_243_0(in_intel_reserved_ffwd_243_0),
        .in_intel_reserved_ffwd_244_0(in_intel_reserved_ffwd_244_0),
        .in_intel_reserved_ffwd_245_0(in_intel_reserved_ffwd_245_0),
        .in_intel_reserved_ffwd_246_0(in_intel_reserved_ffwd_246_0),
        .in_intel_reserved_ffwd_247_0(in_intel_reserved_ffwd_247_0),
        .in_intel_reserved_ffwd_248_0(in_intel_reserved_ffwd_248_0),
        .in_intel_reserved_ffwd_249_0(in_intel_reserved_ffwd_249_0),
        .in_intel_reserved_ffwd_24_0(in_intel_reserved_ffwd_24_0),
        .in_intel_reserved_ffwd_250_0(in_intel_reserved_ffwd_250_0),
        .in_intel_reserved_ffwd_251_0(in_intel_reserved_ffwd_251_0),
        .in_intel_reserved_ffwd_252_0(in_intel_reserved_ffwd_252_0),
        .in_intel_reserved_ffwd_253_0(in_intel_reserved_ffwd_253_0),
        .in_intel_reserved_ffwd_254_0(in_intel_reserved_ffwd_254_0),
        .in_intel_reserved_ffwd_255_0(in_intel_reserved_ffwd_255_0),
        .in_intel_reserved_ffwd_256_0(in_intel_reserved_ffwd_256_0),
        .in_intel_reserved_ffwd_25_0(in_intel_reserved_ffwd_25_0),
        .in_intel_reserved_ffwd_26_0(in_intel_reserved_ffwd_26_0),
        .in_intel_reserved_ffwd_27_0(in_intel_reserved_ffwd_27_0),
        .in_intel_reserved_ffwd_28_0(in_intel_reserved_ffwd_28_0),
        .in_intel_reserved_ffwd_29_0(in_intel_reserved_ffwd_29_0),
        .in_intel_reserved_ffwd_2_0(in_intel_reserved_ffwd_2_0),
        .in_intel_reserved_ffwd_30_0(in_intel_reserved_ffwd_30_0),
        .in_intel_reserved_ffwd_31_0(in_intel_reserved_ffwd_31_0),
        .in_intel_reserved_ffwd_32_0(in_intel_reserved_ffwd_32_0),
        .in_intel_reserved_ffwd_33_0(in_intel_reserved_ffwd_33_0),
        .in_intel_reserved_ffwd_34_0(in_intel_reserved_ffwd_34_0),
        .in_intel_reserved_ffwd_35_0(in_intel_reserved_ffwd_35_0),
        .in_intel_reserved_ffwd_36_0(in_intel_reserved_ffwd_36_0),
        .in_intel_reserved_ffwd_37_0(in_intel_reserved_ffwd_37_0),
        .in_intel_reserved_ffwd_38_0(in_intel_reserved_ffwd_38_0),
        .in_intel_reserved_ffwd_39_0(in_intel_reserved_ffwd_39_0),
        .in_intel_reserved_ffwd_3_0(in_intel_reserved_ffwd_3_0),
        .in_intel_reserved_ffwd_40_0(in_intel_reserved_ffwd_40_0),
        .in_intel_reserved_ffwd_41_0(in_intel_reserved_ffwd_41_0),
        .in_intel_reserved_ffwd_42_0(in_intel_reserved_ffwd_42_0),
        .in_intel_reserved_ffwd_43_0(in_intel_reserved_ffwd_43_0),
        .in_intel_reserved_ffwd_44_0(in_intel_reserved_ffwd_44_0),
        .in_intel_reserved_ffwd_45_0(in_intel_reserved_ffwd_45_0),
        .in_intel_reserved_ffwd_46_0(in_intel_reserved_ffwd_46_0),
        .in_intel_reserved_ffwd_47_0(in_intel_reserved_ffwd_47_0),
        .in_intel_reserved_ffwd_48_0(in_intel_reserved_ffwd_48_0),
        .in_intel_reserved_ffwd_49_0(in_intel_reserved_ffwd_49_0),
        .in_intel_reserved_ffwd_4_0(in_intel_reserved_ffwd_4_0),
        .in_intel_reserved_ffwd_50_0(in_intel_reserved_ffwd_50_0),
        .in_intel_reserved_ffwd_51_0(in_intel_reserved_ffwd_51_0),
        .in_intel_reserved_ffwd_52_0(in_intel_reserved_ffwd_52_0),
        .in_intel_reserved_ffwd_53_0(in_intel_reserved_ffwd_53_0),
        .in_intel_reserved_ffwd_54_0(in_intel_reserved_ffwd_54_0),
        .in_intel_reserved_ffwd_55_0(in_intel_reserved_ffwd_55_0),
        .in_intel_reserved_ffwd_56_0(in_intel_reserved_ffwd_56_0),
        .in_intel_reserved_ffwd_57_0(in_intel_reserved_ffwd_57_0),
        .in_intel_reserved_ffwd_58_0(in_intel_reserved_ffwd_58_0),
        .in_intel_reserved_ffwd_59_0(in_intel_reserved_ffwd_59_0),
        .in_intel_reserved_ffwd_5_0(in_intel_reserved_ffwd_5_0),
        .in_intel_reserved_ffwd_60_0(in_intel_reserved_ffwd_60_0),
        .in_intel_reserved_ffwd_61_0(in_intel_reserved_ffwd_61_0),
        .in_intel_reserved_ffwd_62_0(in_intel_reserved_ffwd_62_0),
        .in_intel_reserved_ffwd_63_0(in_intel_reserved_ffwd_63_0),
        .in_intel_reserved_ffwd_64_0(in_intel_reserved_ffwd_64_0),
        .in_intel_reserved_ffwd_65_0(in_intel_reserved_ffwd_65_0),
        .in_intel_reserved_ffwd_66_0(in_intel_reserved_ffwd_66_0),
        .in_intel_reserved_ffwd_67_0(in_intel_reserved_ffwd_67_0),
        .in_intel_reserved_ffwd_68_0(in_intel_reserved_ffwd_68_0),
        .in_intel_reserved_ffwd_69_0(in_intel_reserved_ffwd_69_0),
        .in_intel_reserved_ffwd_6_0(in_intel_reserved_ffwd_6_0),
        .in_intel_reserved_ffwd_70_0(in_intel_reserved_ffwd_70_0),
        .in_intel_reserved_ffwd_71_0(in_intel_reserved_ffwd_71_0),
        .in_intel_reserved_ffwd_72_0(in_intel_reserved_ffwd_72_0),
        .in_intel_reserved_ffwd_73_0(in_intel_reserved_ffwd_73_0),
        .in_intel_reserved_ffwd_74_0(in_intel_reserved_ffwd_74_0),
        .in_intel_reserved_ffwd_75_0(in_intel_reserved_ffwd_75_0),
        .in_intel_reserved_ffwd_76_0(in_intel_reserved_ffwd_76_0),
        .in_intel_reserved_ffwd_77_0(in_intel_reserved_ffwd_77_0),
        .in_intel_reserved_ffwd_78_0(in_intel_reserved_ffwd_78_0),
        .in_intel_reserved_ffwd_79_0(in_intel_reserved_ffwd_79_0),
        .in_intel_reserved_ffwd_7_0(in_intel_reserved_ffwd_7_0),
        .in_intel_reserved_ffwd_80_0(in_intel_reserved_ffwd_80_0),
        .in_intel_reserved_ffwd_81_0(in_intel_reserved_ffwd_81_0),
        .in_intel_reserved_ffwd_82_0(in_intel_reserved_ffwd_82_0),
        .in_intel_reserved_ffwd_83_0(in_intel_reserved_ffwd_83_0),
        .in_intel_reserved_ffwd_84_0(in_intel_reserved_ffwd_84_0),
        .in_intel_reserved_ffwd_85_0(in_intel_reserved_ffwd_85_0),
        .in_intel_reserved_ffwd_86_0(in_intel_reserved_ffwd_86_0),
        .in_intel_reserved_ffwd_87_0(in_intel_reserved_ffwd_87_0),
        .in_intel_reserved_ffwd_88_0(in_intel_reserved_ffwd_88_0),
        .in_intel_reserved_ffwd_89_0(in_intel_reserved_ffwd_89_0),
        .in_intel_reserved_ffwd_8_0(in_intel_reserved_ffwd_8_0),
        .in_intel_reserved_ffwd_90_0(in_intel_reserved_ffwd_90_0),
        .in_intel_reserved_ffwd_91_0(in_intel_reserved_ffwd_91_0),
        .in_intel_reserved_ffwd_92_0(in_intel_reserved_ffwd_92_0),
        .in_intel_reserved_ffwd_93_0(in_intel_reserved_ffwd_93_0),
        .in_intel_reserved_ffwd_94_0(in_intel_reserved_ffwd_94_0),
        .in_intel_reserved_ffwd_95_0(in_intel_reserved_ffwd_95_0),
        .in_intel_reserved_ffwd_96_0(in_intel_reserved_ffwd_96_0),
        .in_intel_reserved_ffwd_97_0(in_intel_reserved_ffwd_97_0),
        .in_intel_reserved_ffwd_98_0(in_intel_reserved_ffwd_98_0),
        .in_intel_reserved_ffwd_99_0(in_intel_reserved_ffwd_99_0),
        .in_intel_reserved_ffwd_9_0(in_intel_reserved_ffwd_9_0),
        .out_c1_exit927_0_tpl(),
        .out_c1_exit927_1_tpl(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_1_tpl),
        .out_c1_exit927_2_tpl(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_2_tpl),
        .out_c1_exit927_3_tpl(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_c1_exit927_3_tpl),
        .out_almost_empty_out(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_almost_empty_out),
        .out_empty_out(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_empty_out),
        .out_o_stall(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_stall),
        .out_o_valid(i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_valid_reg0(REG,685)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_valid_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_valid);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_valid_reg1(REG,684)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_valid_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_valid_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_valid_reg0(REG,821)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_valid_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_valid);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_valid_reg1(REG,820)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_valid_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_valid_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_valid_reg0(REG,957)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_valid_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_valid);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_valid_reg1(REG,956)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_valid_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_valid_reg0_q);
        end
    end

    // redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_valid_reg0(REG,1013)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_valid_reg0_q <= $unsigned(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_valid);
        end
    end

    // redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_valid_reg1(REG,1012)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_valid_reg1_q <= $unsigned(redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_valid_reg0_q);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_valid_reg0(REG,549)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_valid_reg0_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_valid);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_valid_reg1(REG,548)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_valid_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_valid_reg0_q);
        end
    end

    // merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x(STALLENABLE,397)
    // Sync
    assign merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_temp_back_stall = i_sfc_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m8_aunroll_x_out_o_stall;
    assign merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_can_fast_read = ~ ((i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_almost_empty_reg1_q | redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_almost_empty_reg1_q | i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_almost_empty_reg1_q | i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_almost_empty_reg1_q | i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_almost_empty_reg1_q));
    assign merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_can_slow_read = ~ ((i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_empty_reg1_q | redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_empty_reg1_q | i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_empty_reg1_q | i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_empty_reg1_q | i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_empty_reg1_q));
    assign merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_backStall = ~ (merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_forced_read);
    assign merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_no_space_for_result = merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_temp_back_stall;
    assign merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V0 = merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_forced_read;
    assign merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V1 = $unsigned(1'b0);
    assign merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_V2 = $unsigned(1'b0);
    assign can_fast_read_bitsignaltemp = merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_can_fast_read[0];
    assign can_slow_read_bitsignaltemp = merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_can_slow_read[0];
    assign no_space_for_result_bitsignaltemp = merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_no_space_for_result[0];
    assign merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_forced_read[0] = forced_read_bitsignaltemp;
    acl_sync_stall_latency #(
        .EMPTY_PLUS_STALL_LATENCY(7),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(1),
        .RESET_EVERYTHING(0)
    ) themerged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x (
        .can_fast_read(can_fast_read_bitsignaltemp),
        .can_slow_read(can_slow_read_bitsignaltemp),
        .no_space_for_result(no_space_for_result_bitsignaltemp),
        .forced_read(forced_read_bitsignaltemp),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_in_i_stall_reg0(REG,550)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_in_i_stall_reg0_q <= $unsigned(merged_in_SE_bubble_select_i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_backStall);
        end
    end

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_in_i_stall_reg1(REG,551)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_in_i_stall_reg1_q <= $unsigned(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_in_i_stall_reg0_q);
        end
    end

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_in_i_stall_reg0(REG,966)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_in_i_stall_reg0_q <= $unsigned(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_backStall);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_in_i_stall_reg1(REG,967)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_in_i_stall_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_in_i_stall_reg0_q);
        end
    end

    // stall_entry_frontAlmostEmpty_reg0(REG,1009)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontAlmostEmpty_reg0_q <= $unsigned(in_almost_empty_in);
        end
    end

    // stall_entry_frontAlmostEmpty_reg1(REG,1008)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontAlmostEmpty_reg1_q <= $unsigned(stall_entry_frontAlmostEmpty_reg0_q);
        end
    end

    // stall_entry_frontEmpty_reg0(REG,1007)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontEmpty_reg0_q <= $unsigned(in_empty_in);
        end
    end

    // stall_entry_frontEmpty_reg1(REG,1006)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontEmpty_reg1_q <= $unsigned(stall_entry_frontEmpty_reg0_q);
        end
    end

    // stall_entry_frontValid_reg0(REG,1005)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontValid_reg0_q <= $unsigned(in_valid_in);
        end
    end

    // stall_entry_frontValid_reg1(REG,1004)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontValid_reg1_q <= $unsigned(stall_entry_frontValid_reg0_q);
        end
    end

    // merged_in_SE_stall_entry(STALLENABLE,395)
    assign merged_in_SE_stall_entry_backStall = i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_stall;
    assign merged_in_SE_stall_entry_V0 = stall_entry_frontValid_reg1_q;
    assign merged_in_SE_stall_entry_V1 = stall_entry_frontEmpty_reg1_q;
    assign merged_in_SE_stall_entry_V2 = stall_entry_frontAlmostEmpty_reg1_q;

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x(BLACKBOX,17)@0
    // in in_i_stall@20000000
    // out out_c0_exit920_0_tpl@37
    // out out_c0_exit920_1_tpl@37
    // out out_c0_exit920_2_tpl@37
    // out out_c0_exit920_3_tpl@37
    // out out_c0_exit920_4_tpl@37
    // out out_c0_exit920_5_tpl@37
    // out out_c0_exit920_6_tpl@37
    // out out_c0_exit920_7_tpl@37
    // out out_almost_empty_out@37
    // out out_empty_out@37
    // out out_o_stall@20000000
    // out out_o_valid@37
    // out out_profile_loop_o_valid@37
    c_compMM_m_i_sfc_s_c0_in_for_body_c_comp0000nter9182_c_compmm_m1 thei_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x (
        .in_c0_eni1_0_tpl(GND_q),
        .in_c0_eni1_1_tpl(GND_q),
        .in_almost_empty_in(merged_in_SE_stall_entry_V2),
        .in_empty_in(merged_in_SE_stall_entry_V1),
        .in_i_stall(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_in_i_stall_reg1_q),
        .in_i_valid(merged_in_SE_stall_entry_V0),
        .in_intel_reserved_ffwd_0_0(in_intel_reserved_ffwd_0_0),
        .in_intel_reserved_ffwd_257_0(in_intel_reserved_ffwd_257_0),
        .out_c0_exit920_0_tpl(),
        .out_c0_exit920_1_tpl(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_1_tpl),
        .out_c0_exit920_2_tpl(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_2_tpl),
        .out_c0_exit920_3_tpl(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_3_tpl),
        .out_c0_exit920_4_tpl(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_4_tpl),
        .out_c0_exit920_5_tpl(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl),
        .out_c0_exit920_6_tpl(),
        .out_c0_exit920_7_tpl(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_7_tpl),
        .out_almost_empty_out(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_almost_empty_out),
        .out_empty_out(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_empty_out),
        .out_o_stall(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_stall),
        .out_o_valid(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_valid),
        .out_profile_loop_o_valid(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_profile_loop_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_profile_loop_o_valid_reg0(REG,987)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_profile_loop_o_valid_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_profile_loop_o_valid);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_profile_loop_o_valid_reg1(REG,986)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_profile_loop_o_valid_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_profile_loop_o_valid_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_7_tpl_reg0(REG,979)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_7_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_7_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_7_tpl_reg1(REG,978)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_7_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_7_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_reg0(REG,977)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_reg1(REG,976)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_4_tpl_reg0(REG,975)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_4_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_4_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_4_tpl_reg1(REG,974)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_4_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_4_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_3_tpl_reg0(REG,973)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_3_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_3_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_3_tpl_reg1(REG,972)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_3_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_3_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_2_tpl_reg0(REG,971)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_2_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_2_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_2_tpl_reg1(REG,970)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_2_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_2_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_1_tpl_reg0(REG,969)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_1_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_1_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_1_tpl_reg1(REG,968)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_1_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_1_tpl_reg0_q);
        end
    end

    // bubble_join_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x(BITJOIN,325)
    assign bubble_join_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_q = {i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_profile_loop_o_valid_reg1_q, i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_7_tpl_reg1_q, i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_reg1_q, i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_4_tpl_reg1_q, i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_3_tpl_reg1_q, i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_2_tpl_reg1_q, i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_1_tpl_reg1_q};

    // bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x(BITSELECT,326)
    assign bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_b = $unsigned(bubble_join_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_q[63:0]);
    assign bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_c = $unsigned(bubble_join_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_q[127:64]);
    assign bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_d = $unsigned(bubble_join_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_q[191:128]);
    assign bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_e = $unsigned(bubble_join_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_q[255:192]);
    assign bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_f = $unsigned(bubble_join_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_q[319:256]);
    assign bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_g = $unsigned(bubble_join_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_q[320:320]);
    assign bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_h = $unsigned(bubble_join_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_q[321:321]);

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_almost_empty_out_reg0(REG,981)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_almost_empty_out_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_almost_empty_out);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_almost_empty_out_reg1(REG,980)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_almost_empty_out_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_almost_empty_out_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_empty_out_reg0(REG,983)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_empty_out_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_empty_out);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_empty_out_reg1(REG,982)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_empty_out_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_empty_out_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_valid_reg0(REG,985)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_valid_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_valid);
        end
    end

    // i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_valid_reg1(REG,984)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_valid_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_valid_reg0_q);
        end
    end

    // merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x(STALLENABLE,396)
    // Desync
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_temp_back_stall = redist0_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_c0_exit920_5_tpl_31_fifo_o_stall | coalesced_delay_0_fifo_o_stall | i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_o_stall | i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_o_stall | i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_stall | i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_o_stall;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_backStall = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_temp_back_stall;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V0 = i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_o_valid_reg1_q;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V6 = i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_empty_out_reg1_q;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V12 = i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_out_almost_empty_out_reg1_q;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V1 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V0;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V7 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V6;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V13 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V12;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V2 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V0;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V8 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V6;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V14 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V12;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V3 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V0;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V9 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V6;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V15 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V12;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V4 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V0;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V10 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V6;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V16 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V12;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V5 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V0;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V11 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V6;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V17 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V12;

    // i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x(BLACKBOX,13)@37
    // in in_i_stall@20000000
    // out out_o_readdata_0_tpl@68
    // out out_o_readdata_1_tpl@68
    // out out_o_readdata_2_tpl@68
    // out out_o_readdata_3_tpl@68
    // out out_o_readdata_4_tpl@68
    // out out_o_readdata_5_tpl@68
    // out out_o_readdata_6_tpl@68
    // out out_o_readdata_7_tpl@68
    // out out_o_readdata_8_tpl@68
    // out out_o_readdata_9_tpl@68
    // out out_o_readdata_10_tpl@68
    // out out_o_readdata_11_tpl@68
    // out out_o_readdata_12_tpl@68
    // out out_o_readdata_13_tpl@68
    // out out_o_readdata_14_tpl@68
    // out out_o_readdata_15_tpl@68
    // out out_o_readdata_16_tpl@68
    // out out_o_readdata_17_tpl@68
    // out out_o_readdata_18_tpl@68
    // out out_o_readdata_19_tpl@68
    // out out_o_readdata_20_tpl@68
    // out out_o_readdata_21_tpl@68
    // out out_o_readdata_22_tpl@68
    // out out_o_readdata_23_tpl@68
    // out out_o_readdata_24_tpl@68
    // out out_o_readdata_25_tpl@68
    // out out_o_readdata_26_tpl@68
    // out out_o_readdata_27_tpl@68
    // out out_o_readdata_28_tpl@68
    // out out_o_readdata_29_tpl@68
    // out out_o_readdata_30_tpl@68
    // out out_o_readdata_31_tpl@68
    // out out_o_readdata_32_tpl@68
    // out out_o_readdata_33_tpl@68
    // out out_o_readdata_34_tpl@68
    // out out_o_readdata_35_tpl@68
    // out out_o_readdata_36_tpl@68
    // out out_o_readdata_37_tpl@68
    // out out_o_readdata_38_tpl@68
    // out out_o_readdata_39_tpl@68
    // out out_o_readdata_40_tpl@68
    // out out_o_readdata_41_tpl@68
    // out out_o_readdata_42_tpl@68
    // out out_o_readdata_43_tpl@68
    // out out_o_readdata_44_tpl@68
    // out out_o_readdata_45_tpl@68
    // out out_o_readdata_46_tpl@68
    // out out_o_readdata_47_tpl@68
    // out out_o_readdata_48_tpl@68
    // out out_o_readdata_49_tpl@68
    // out out_o_readdata_50_tpl@68
    // out out_o_readdata_51_tpl@68
    // out out_o_readdata_52_tpl@68
    // out out_o_readdata_53_tpl@68
    // out out_o_readdata_54_tpl@68
    // out out_o_readdata_55_tpl@68
    // out out_o_readdata_56_tpl@68
    // out out_o_readdata_57_tpl@68
    // out out_o_readdata_58_tpl@68
    // out out_o_readdata_59_tpl@68
    // out out_o_readdata_60_tpl@68
    // out out_o_readdata_61_tpl@68
    // out out_o_readdata_62_tpl@68
    // out out_o_readdata_63_tpl@68
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_address@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_burstcount@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_byteenable@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_enable@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_read@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_write@20000000
    // out out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_writedata@20000000
    // out out_o_almost_empty@68
    // out out_o_empty@68
    // out out_o_stall@20000000
    // out out_o_valid@68
    c_compMM_m_i_llvm_fpga_mem_memcoalesce_l0000que_6910_c_compmm_m0 thei_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x (
        .in_almost_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V16),
        .in_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V10),
        .in_flush(in_flush),
        .in_i_address(bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_c),
        .in_i_predicate(GND_q),
        .in_i_stall(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_in_i_stall_reg1_q),
        .in_i_valid(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body_c_compmm_ms_c0_enter9182_c_compmm_m1_aunroll_x_V4),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_readdata(in_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_readdata),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_readdatavalid(in_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_readdatavalid),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_waitrequest(in_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_waitrequest),
        .in_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_writeack(in_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_writeack),
        .out_o_readdata_0_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_0_tpl),
        .out_o_readdata_1_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_1_tpl),
        .out_o_readdata_2_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_2_tpl),
        .out_o_readdata_3_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_3_tpl),
        .out_o_readdata_4_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_4_tpl),
        .out_o_readdata_5_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_5_tpl),
        .out_o_readdata_6_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_6_tpl),
        .out_o_readdata_7_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_7_tpl),
        .out_o_readdata_8_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_8_tpl),
        .out_o_readdata_9_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_9_tpl),
        .out_o_readdata_10_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_10_tpl),
        .out_o_readdata_11_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_11_tpl),
        .out_o_readdata_12_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_12_tpl),
        .out_o_readdata_13_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_13_tpl),
        .out_o_readdata_14_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_14_tpl),
        .out_o_readdata_15_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_15_tpl),
        .out_o_readdata_16_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_16_tpl),
        .out_o_readdata_17_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_17_tpl),
        .out_o_readdata_18_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_18_tpl),
        .out_o_readdata_19_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_19_tpl),
        .out_o_readdata_20_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_20_tpl),
        .out_o_readdata_21_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_21_tpl),
        .out_o_readdata_22_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_22_tpl),
        .out_o_readdata_23_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_23_tpl),
        .out_o_readdata_24_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_24_tpl),
        .out_o_readdata_25_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_25_tpl),
        .out_o_readdata_26_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_26_tpl),
        .out_o_readdata_27_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_27_tpl),
        .out_o_readdata_28_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_28_tpl),
        .out_o_readdata_29_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_29_tpl),
        .out_o_readdata_30_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_30_tpl),
        .out_o_readdata_31_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_31_tpl),
        .out_o_readdata_32_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_32_tpl),
        .out_o_readdata_33_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_33_tpl),
        .out_o_readdata_34_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_34_tpl),
        .out_o_readdata_35_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_35_tpl),
        .out_o_readdata_36_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_36_tpl),
        .out_o_readdata_37_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_37_tpl),
        .out_o_readdata_38_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_38_tpl),
        .out_o_readdata_39_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_39_tpl),
        .out_o_readdata_40_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_40_tpl),
        .out_o_readdata_41_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_41_tpl),
        .out_o_readdata_42_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_42_tpl),
        .out_o_readdata_43_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_43_tpl),
        .out_o_readdata_44_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_44_tpl),
        .out_o_readdata_45_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_45_tpl),
        .out_o_readdata_46_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_46_tpl),
        .out_o_readdata_47_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_47_tpl),
        .out_o_readdata_48_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_48_tpl),
        .out_o_readdata_49_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_49_tpl),
        .out_o_readdata_50_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_50_tpl),
        .out_o_readdata_51_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_51_tpl),
        .out_o_readdata_52_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_52_tpl),
        .out_o_readdata_53_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_53_tpl),
        .out_o_readdata_54_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_54_tpl),
        .out_o_readdata_55_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_55_tpl),
        .out_o_readdata_56_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_56_tpl),
        .out_o_readdata_57_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_57_tpl),
        .out_o_readdata_58_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_58_tpl),
        .out_o_readdata_59_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_59_tpl),
        .out_o_readdata_60_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_60_tpl),
        .out_o_readdata_61_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_61_tpl),
        .out_o_readdata_62_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_62_tpl),
        .out_o_readdata_63_tpl(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_readdata_63_tpl),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_address(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_address),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_burstcount(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_burstcount),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_byteenable(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_byteenable),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_enable(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_enable),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_read(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_read),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_write(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_write),
        .out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_writedata(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_writedata),
        .out_o_almost_empty(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_almost_empty),
        .out_o_empty(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_empty),
        .out_o_stall(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_stall),
        .out_o_valid(i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_ext_sig_sync_out_x(GPOUT,3)
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_address = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_address;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_enable = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_enable;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_read = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_read;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_write = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_write;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_writedata = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_writedata;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_byteenable = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_byteenable;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_burstcount = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_6910_c_compmm_m4_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_6910_c_compMM_m_avm_burstcount;

    // merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg0(REG,413)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg0_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_0_V0);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg1(REG,412)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg1_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg0_q);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg2(REG,411)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg2_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg1_q);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg3(REG,410)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg3_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg2_q);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg4(REG,409)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg4_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg3_q);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg5(REG,408)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg5_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg4_q);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg6(REG,407)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg6_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg5_q);
        end
    end

    // coalesced_delay_0_fifo_o_data_reg0(REG,1025)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_data_reg0_q <= $unsigned(coalesced_delay_0_fifo_o_data);
        end
    end

    // coalesced_delay_0_fifo_o_data_reg1(REG,1024)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_data_reg1_q <= $unsigned(coalesced_delay_0_fifo_o_data_reg0_q);
        end
    end

    // bubble_join_coalesced_delay_0_fifo(BITJOIN,335)
    assign bubble_join_coalesced_delay_0_fifo_q = coalesced_delay_0_fifo_o_data_reg1_q;

    // bubble_select_coalesced_delay_0_fifo(BITSELECT,336)
    assign bubble_select_coalesced_delay_0_fifo_b = $unsigned(bubble_join_coalesced_delay_0_fifo_q[1:0]);

    // sel_for_coalesced_delay_0(BITSELECT,308)
    assign sel_for_coalesced_delay_0_b = $unsigned(bubble_select_coalesced_delay_0_fifo_b[0:0]);
    assign sel_for_coalesced_delay_0_c = $unsigned(bubble_select_coalesced_delay_0_fifo_b[1:1]);

    // dupName_0_sync_out_x(GPOUT,4)@416
    assign out_almost_empty_out = merged_in_SE_sel_for_coalesced_delay_0_V2;
    assign out_c0_exe7 = sel_for_coalesced_delay_0_b;
    assign out_empty_out = merged_in_SE_sel_for_coalesced_delay_0_V1;
    assign out_profile_loop_o_valid = sel_for_coalesced_delay_0_c;
    assign out_valid_out = merged_in_SE_sel_for_coalesced_delay_0_V0_sync_valid_reg6_q;

    // dupName_1_ext_sig_sync_out_x(GPOUT,6)
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_address = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_address;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_enable = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_enable;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_read = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_read;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_write = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_write;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_writedata = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_writedata;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_byteenable = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_byteenable;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_burstcount = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7011_c_compmm_m5_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7011_c_compMM_m_avm_burstcount;

    // dupName_2_ext_sig_sync_out_x(GPOUT,8)
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_address = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_address;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_enable = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_enable;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_read = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_read;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_write = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_write;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_writedata = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_writedata;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_byteenable = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_byteenable;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_burstcount = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_7112_c_compmm_m6_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_7112_c_compMM_m_avm_burstcount;

    // dupName_3_ext_sig_sync_out_x(GPOUT,10)
    assign out_memdep_17_c_compMM_m_avm_address = i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_address;
    assign out_memdep_17_c_compMM_m_avm_enable = i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_enable;
    assign out_memdep_17_c_compMM_m_avm_read = i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_read;
    assign out_memdep_17_c_compMM_m_avm_write = i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_write;
    assign out_memdep_17_c_compMM_m_avm_writedata = i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_writedata;
    assign out_memdep_17_c_compMM_m_avm_byteenable = i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_byteenable;
    assign out_memdep_17_c_compMM_m_avm_burstcount = i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_memdep_17_c_compMM_m_avm_burstcount;

    // dupName_4_ext_sig_sync_out_x(GPOUT,11)
    assign out_lsu_memdep_17_o_active = i_llvm_fpga_mem_memdep_17_c_compmm_m10_aunroll_x_out_lsu_memdep_17_o_active;

    // ext_sig_sync_out(GPOUT,24)
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_address = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_address;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_enable = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_enable;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_read = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_read;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_write = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_write;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_writedata = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_writedata;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_byteenable = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_byteenable;
    assign out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_burstcount = i_llvm_fpga_mem_memcoalesce_load_c_compmm_m_fpgaunique_689_c_compmm_m3_aunroll_x_out_memcoalesce_load_c_compMM_m_fpgaunique_689_c_compMM_m_avm_burstcount;

    // stall_entry_frontStall_reg0(REG,1002)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontStall_reg0_q <= $unsigned(merged_in_SE_stall_entry_backStall);
        end
    end

    // stall_entry_frontStall_reg1(REG,1003)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontStall_reg1_q <= $unsigned(stall_entry_frontStall_reg0_q);
        end
    end

    // sync_out(GPOUT,301)@0
    assign out_stall_out = stall_entry_frontStall_reg1_q;

    // rst_sync(RESETSYNC,1030)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
