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// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr1_data_fifo
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_i_llvm_fpga_sfc_exit_s_c0_out_0003c_compstr1_data_fifo (
    output wire [0:0] out_o_almost_empty,
    output wire [0:0] out_o_data_0_tpl,
    output wire [0:0] out_o_data_1_tpl,
    output wire [0:0] out_o_data_2_tpl,
    output wire [15:0] out_o_data_3_tpl,
    output wire [15:0] out_o_data_4_tpl,
    output wire [0:0] out_o_data_5_tpl,
    output wire [0:0] out_o_data_6_tpl,
    output wire [0:0] out_o_empty,
    output wire [0:0] out_o_valid,
    input wire [0:0] in_almost_empty_in,
    input wire [0:0] in_empty_in,
    input wire [0:0] in_i_data_0_tpl,
    input wire [0:0] in_i_data_1_tpl,
    input wire [0:0] in_i_data_2_tpl,
    input wire [15:0] in_i_data_3_tpl,
    input wire [15:0] in_i_data_4_tpl,
    input wire [0:0] in_i_data_5_tpl,
    input wire [0:0] in_i_data_6_tpl,
    input wire [0:0] in_i_valid,
    input wire [0:0] in_i_stall,
    output wire [0:0] out_o_stall,
    input wire clock,
    input wire resetn
    );

    wire [0:0] adapt_scalar_trunc31_in;
    wire [0:0] adapt_scalar_trunc31_q;
    wire [0:0] adapt_scalar_trunc33_in;
    wire [0:0] adapt_scalar_trunc33_q;
    wire [0:0] adapt_scalar_trunc35_in;
    wire [0:0] adapt_scalar_trunc35_q;
    wire [0:0] adapt_scalar_trunc51_in;
    wire [0:0] adapt_scalar_trunc51_q;
    wire [0:0] adapt_scalar_trunc53_in;
    wire [0:0] adapt_scalar_trunc53_q;
    wire [6:0] c_i7_026_q;
    wire [7:0] c_i8_09_q;
    wire [79:0] dsdk_ip_adapt_bitjoin1_q;
    wire [31:0] dsdk_ip_adapt_bitjoin10_q;
    wire [15:0] dsdk_ip_adapt_bitjoin12_q;
    wire [15:0] dsdk_ip_adapt_bitjoin14_q;
    wire [15:0] dsdk_ip_adapt_bitjoin18_q;
    wire [15:0] dsdk_ip_adapt_bitjoin20_q;
    wire [7:0] element_extension25_q;
    wire [7:0] element_extension27_q;
    wire [7:0] element_extension3_q;
    wire [7:0] element_extension5_q;
    wire [7:0] element_extension7_q;
    wire [79:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_data;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_stall;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_stall_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_valid;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_almost_empty;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_almost_empty_bitsignaltemp;
    wire [79:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_data;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_empty;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_empty_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_stall;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_stall_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_valid;
    wire i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_valid_bitsignaltemp;
    wire [0:0] ip_dsdk_adapt_bitselect30_b;
    wire [0:0] ip_dsdk_adapt_bitselect32_b;
    wire [0:0] ip_dsdk_adapt_bitselect34_b;
    wire [31:0] ip_dsdk_adapt_bitselect36_b;
    wire [15:0] ip_dsdk_adapt_bitselect38_b;
    wire [15:0] ip_dsdk_adapt_bitselect44_b;
    wire [0:0] ip_dsdk_adapt_bitselect50_b;
    wire [0:0] ip_dsdk_adapt_bitselect52_b;


    // ip_dsdk_adapt_bitselect52(BITSELECT,43)
    assign ip_dsdk_adapt_bitselect52_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_data[72:72];

    // adapt_scalar_trunc53(ROUND,8)
    assign adapt_scalar_trunc53_in = ip_dsdk_adapt_bitselect52_b;
    assign adapt_scalar_trunc53_q = adapt_scalar_trunc53_in[0:0];

    // ip_dsdk_adapt_bitselect50(BITSELECT,42)
    assign ip_dsdk_adapt_bitselect50_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_data[64:64];

    // adapt_scalar_trunc51(ROUND,7)
    assign adapt_scalar_trunc51_in = ip_dsdk_adapt_bitselect50_b;
    assign adapt_scalar_trunc51_q = adapt_scalar_trunc51_in[0:0];

    // ip_dsdk_adapt_bitselect36(BITSELECT,35)
    assign ip_dsdk_adapt_bitselect36_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_data[63:32];

    // ip_dsdk_adapt_bitselect44(BITSELECT,39)
    assign ip_dsdk_adapt_bitselect44_b = ip_dsdk_adapt_bitselect36_b[31:16];

    // ip_dsdk_adapt_bitselect38(BITSELECT,36)
    assign ip_dsdk_adapt_bitselect38_b = ip_dsdk_adapt_bitselect36_b[15:0];

    // ip_dsdk_adapt_bitselect34(BITSELECT,34)
    assign ip_dsdk_adapt_bitselect34_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_data[16:16];

    // adapt_scalar_trunc35(ROUND,6)
    assign adapt_scalar_trunc35_in = ip_dsdk_adapt_bitselect34_b;
    assign adapt_scalar_trunc35_q = adapt_scalar_trunc35_in[0:0];

    // ip_dsdk_adapt_bitselect32(BITSELECT,33)
    assign ip_dsdk_adapt_bitselect32_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_data[8:8];

    // adapt_scalar_trunc33(ROUND,5)
    assign adapt_scalar_trunc33_in = ip_dsdk_adapt_bitselect32_b;
    assign adapt_scalar_trunc33_q = adapt_scalar_trunc33_in[0:0];

    // ip_dsdk_adapt_bitselect30(BITSELECT,32)
    assign ip_dsdk_adapt_bitselect30_b = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_data[0:0];

    // adapt_scalar_trunc31(ROUND,4)
    assign adapt_scalar_trunc31_in = ip_dsdk_adapt_bitselect30_b;
    assign adapt_scalar_trunc31_q = adapt_scalar_trunc31_in[0:0];

    // c_i7_026(CONSTANT,14)
    assign c_i7_026_q = $unsigned(7'b0000000);

    // element_extension27(BITJOIN,27)
    assign element_extension27_q = {c_i7_026_q, in_i_data_6_tpl};

    // element_extension25(BITJOIN,26)
    assign element_extension25_q = {c_i7_026_q, in_i_data_5_tpl};

    // dsdk_ip_adapt_bitjoin20(BITJOIN,25)
    assign dsdk_ip_adapt_bitjoin20_q = in_i_data_4_tpl;

    // dsdk_ip_adapt_bitjoin18(BITJOIN,24)
    assign dsdk_ip_adapt_bitjoin18_q = dsdk_ip_adapt_bitjoin20_q;

    // dsdk_ip_adapt_bitjoin14(BITJOIN,23)
    assign dsdk_ip_adapt_bitjoin14_q = in_i_data_3_tpl;

    // dsdk_ip_adapt_bitjoin12(BITJOIN,22)
    assign dsdk_ip_adapt_bitjoin12_q = dsdk_ip_adapt_bitjoin14_q;

    // dsdk_ip_adapt_bitjoin10(BITJOIN,21)
    assign dsdk_ip_adapt_bitjoin10_q = {dsdk_ip_adapt_bitjoin18_q, dsdk_ip_adapt_bitjoin12_q};

    // c_i8_09(CONSTANT,19)
    assign c_i8_09_q = $unsigned(8'b00000000);

    // element_extension7(BITJOIN,30)
    assign element_extension7_q = {c_i7_026_q, in_i_data_2_tpl};

    // element_extension5(BITJOIN,29)
    assign element_extension5_q = {c_i7_026_q, in_i_data_1_tpl};

    // element_extension3(BITJOIN,28)
    assign element_extension3_q = {c_i7_026_q, in_i_data_0_tpl};

    // dsdk_ip_adapt_bitjoin1(BITJOIN,20)
    assign dsdk_ip_adapt_bitjoin1_q = {element_extension27_q, element_extension25_q, dsdk_ip_adapt_bitjoin10_q, c_i8_09_q, element_extension7_q, element_extension5_q, element_extension3_q};

    // i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0(EXTIFACE,31)
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_data = dsdk_ip_adapt_bitjoin1_q;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_stall = in_i_stall;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_valid = in_i_valid;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_stall_bitsignaltemp = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_stall[0];
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_valid_bitsignaltemp = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_valid[0];
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_almost_empty[0] = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_almost_empty_bitsignaltemp;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_empty[0] = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_empty_bitsignaltemp;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_stall[0] = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_stall_bitsignaltemp;
    assign i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_valid[0] = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_valid_bitsignaltemp;
    hld_fifo #(
        .ALMOST_EMPTY_CUTOFF(7),
        .DEPTH(512),
        .STYLE("ms"),
        .ASYNC_RESET(0),
        .NEVER_OVERFLOWS(1),
        .RESET_EXTERNALLY_HELD(1),
        .STALL_IN_EARLINESS(3),
        .SYNCHRONIZE_RESET(0),
        .USE_STALL_LATENCY_DOWNSTREAM(1),
        .USE_STALL_LATENCY_UPSTREAM(1),
        .WIDTH(80)
    ) thei_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0 (
        .i_data(dsdk_ip_adapt_bitjoin1_q),
        .i_stall(i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_stall_bitsignaltemp),
        .i_valid(i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_i_valid_bitsignaltemp),
        .o_almost_empty(i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_almost_empty_bitsignaltemp),
        .o_data(i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_data),
        .o_empty(i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_empty_bitsignaltemp),
        .o_stall(i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_stall_bitsignaltemp),
        .o_valid(i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_valid_bitsignaltemp),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_sync_out_aunroll_x(GPOUT,2)@20000000
    assign out_o_almost_empty = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_almost_empty;
    assign out_o_data_0_tpl = adapt_scalar_trunc31_q;
    assign out_o_data_1_tpl = adapt_scalar_trunc33_q;
    assign out_o_data_2_tpl = adapt_scalar_trunc35_q;
    assign out_o_data_3_tpl = ip_dsdk_adapt_bitselect38_b;
    assign out_o_data_4_tpl = ip_dsdk_adapt_bitselect44_b;
    assign out_o_data_5_tpl = adapt_scalar_trunc51_q;
    assign out_o_data_6_tpl = adapt_scalar_trunc53_q;
    assign out_o_empty = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_empty;
    assign out_o_valid = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_valid;

    // sync_out(GPOUT,47)@20000000
    assign out_o_stall = i_llvm_fpga_sfc_exit_s_c0_out_for_body34_c_compstrs_c0_exit731_c_compstr0_o_stall;

endmodule
