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// SystemVerilog created from i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m1_data_fifo
// Created for function/kernel c_compMM_m
// SystemVerilog created on Wed Mar 26 11:59:06 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compMM_m_i_llvm_fpga_sfc_exit_s_c2_out0000_compmm_m1_data_fifo (
    output wire [0:0] out_o_almost_empty,
    output wire [0:0] out_o_data_0_tpl,
    output wire [0:0] out_o_empty,
    output wire [0:0] out_o_valid,
    input wire [0:0] in_almost_empty_in,
    input wire [0:0] in_empty_in,
    input wire [0:0] in_i_data_0_tpl,
    input wire [0:0] in_i_valid,
    input wire [0:0] in_i_stall,
    output wire [0:0] out_o_stall,
    input wire clock,
    input wire resetn
    );

    wire [0:0] adapt_scalar_trunc7_in;
    wire [0:0] adapt_scalar_trunc7_q;
    wire [6:0] c_i7_04_q;
    wire [7:0] dsdk_ip_adapt_bitjoin1_q;
    wire [7:0] element_extension3_q;
    wire [7:0] i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_data;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_stall;
    wire i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_stall_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_valid;
    wire i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_almost_empty;
    wire i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_almost_empty_bitsignaltemp;
    wire [7:0] i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_data;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_empty;
    wire i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_empty_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_stall;
    wire i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_stall_bitsignaltemp;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_valid;
    wire i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_valid_bitsignaltemp;
    wire [0:0] ip_dsdk_adapt_bitselect6_b;


    // ip_dsdk_adapt_bitselect6(BITSELECT,9)
    assign ip_dsdk_adapt_bitselect6_b = i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_data[0:0];

    // adapt_scalar_trunc7(ROUND,4)
    assign adapt_scalar_trunc7_in = ip_dsdk_adapt_bitselect6_b;
    assign adapt_scalar_trunc7_q = adapt_scalar_trunc7_in[0:0];

    // c_i7_04(CONSTANT,5)
    assign c_i7_04_q = $unsigned(7'b0000000);

    // element_extension3(BITJOIN,7)
    assign element_extension3_q = {c_i7_04_q, in_i_data_0_tpl};

    // dsdk_ip_adapt_bitjoin1(BITJOIN,6)
    assign dsdk_ip_adapt_bitjoin1_q = element_extension3_q;

    // i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0(EXTIFACE,8)
    assign i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_data = dsdk_ip_adapt_bitjoin1_q;
    assign i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_stall = in_i_stall;
    assign i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_valid = in_i_valid;
    assign i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_stall_bitsignaltemp = i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_stall[0];
    assign i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_valid_bitsignaltemp = i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_valid[0];
    assign i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_almost_empty[0] = i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_almost_empty_bitsignaltemp;
    assign i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_empty[0] = i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_empty_bitsignaltemp;
    assign i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_stall[0] = i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_stall_bitsignaltemp;
    assign i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_valid[0] = i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_valid_bitsignaltemp;
    hld_fifo #(
        .ALMOST_EMPTY_CUTOFF(7),
        .DEPTH(512),
        .STYLE("ms"),
        .ASYNC_RESET(0),
        .NEVER_OVERFLOWS(1),
        .RESET_EXTERNALLY_HELD(1),
        .STALL_IN_EARLINESS(3),
        .SYNCHRONIZE_RESET(0),
        .USE_STALL_LATENCY_DOWNSTREAM(1),
        .USE_STALL_LATENCY_UPSTREAM(1),
        .WIDTH(8)
    ) thei_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0 (
        .i_data(dsdk_ip_adapt_bitjoin1_q),
        .i_stall(i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_stall_bitsignaltemp),
        .i_valid(i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_i_valid_bitsignaltemp),
        .o_almost_empty(i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_almost_empty_bitsignaltemp),
        .o_data(i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_data),
        .o_empty(i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_empty_bitsignaltemp),
        .o_stall(i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_stall_bitsignaltemp),
        .o_valid(i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_valid_bitsignaltemp),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_sync_out_aunroll_x(GPOUT,2)@20000000
    assign out_o_almost_empty = i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_almost_empty;
    assign out_o_data_0_tpl = adapt_scalar_trunc7_q;
    assign out_o_empty = i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_empty;
    assign out_o_valid = i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_valid;

    // sync_out(GPOUT,11)@20000000
    assign out_o_stall = i_llvm_fpga_sfc_exit_s_c2_out_wt_entry_c_compmm_ms_c2_exit_c_compmm_m0_o_stall;

endmodule
