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// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m0
// Created for function/kernel c_compMM_m
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m166_c_compmm_m0 (
    output wire [0:0] out_valid_out,
    output wire [15:0] out_intel_reserved_ffwd_160_0,
    input wire [0:0] in_stall_in,
    output wire [0:0] out_stall_out,
    input wire [0:0] in_predicate_in,
    input wire [15:0] in_src_data_in_160_0,
    input wire [0:0] in_valid_in,
    input wire clock,
    input wire resetn
    );

    wire [0:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_predicate_in;
    wire i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_predicate_in_bitsignaltemp;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_source_in;
    wire [0:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_valid_in;
    wire i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_valid_in_bitsignaltemp;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_source_out;


    // dupName_0_sync_out_x(GPOUT,2)@110
    assign out_valid_out = in_valid_in;

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1(EXTIFACE,3)@110
    assign i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_predicate_in = in_predicate_in;
    assign i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_source_in = in_src_data_in_160_0;
    assign i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_valid_in = in_valid_in;
    assign i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_predicate_in_bitsignaltemp = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_predicate_in[0];
    assign i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_valid_in_bitsignaltemp = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_valid_in[0];
    acl_ffwdsrc #(
        .MAX_LATENCY(1),
        .MIN_CAPACITY(1),
        .WIDTH(16)
    ) thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1 (
        .predicate_in(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_predicate_in_bitsignaltemp),
        .source_in(in_src_data_in_160_0),
        .valid_in(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_valid_in_bitsignaltemp),
        .source_out(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_source_out),
        .clock(clock)
    );

    // regfree_osync(GPOUT,5)
    assign out_intel_reserved_ffwd_160_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m166_c_compmm_m1_source_out;

    // sync_out(GPOUT,7)@110
    assign out_stall_out = in_stall_in;

endmodule
