// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// Your use of  Intel Corporation's design tools,  logic functions and other
// software and  tools, and its AMPP partner logic functions, and any output
// files any  of the foregoing (including  device programming  or simulation
// files), and  any associated  documentation  or information  are expressly
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement,  including,  without limitation,  that your use is for
// the  sole  purpose of  programming  logic devices  manufactured by  Intel
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// ---------------------------------------------------------------------------

// SystemVerilog created from bb_c_compSTR_B5
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_bb_B5 (
    input wire [0:0] in_cmp21684_0,
    input wire [0:0] in_flush,
    input wire [31:0] in_i_0288_pop12683_0,
    input wire [31:0] in_iord_bl_WStream_i_fifodata,
    input wire [0:0] in_iord_bl_WStream_i_fifovalid,
    input wire [31:0] in_iord_bl_yStream_i_fifodata,
    input wire [0:0] in_iord_bl_yStream_i_fifovalid,
    input wire [4095:0] in_memdep_17_c_compSTR_avm_readdata,
    input wire [0:0] in_memdep_17_c_compSTR_avm_readdatavalid,
    input wire [0:0] in_memdep_17_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memdep_17_c_compSTR_avm_writeack,
    input wire [4095:0] in_memdep_5_c_compSTR_avm_readdata,
    input wire [0:0] in_memdep_5_c_compSTR_avm_readdatavalid,
    input wire [0:0] in_memdep_5_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memdep_5_c_compSTR_avm_writeack,
    input wire [0:0] in_memdep_phi9_pop1032_pop14687_0,
    input wire [0:0] in_memdep_phi9_pop10682_0,
    input wire [0:0] in_memdep_phi_pop930_pop13686_0,
    input wire [0:0] in_memdep_phi_pop9679_0,
    input wire [0:0] in_notcmp21685_0,
    input wire [0:0] in_stall_in_0,
    input wire [0:0] in_valid_in_0,
    output wire [0:0] out_c0_exe6720,
    output wire [0:0] out_iord_bl_WStream_o_fifoalmost_full,
    output wire [0:0] out_iord_bl_WStream_o_fifoready,
    output wire [0:0] out_iord_bl_yStream_o_fifoalmost_full,
    output wire [0:0] out_iord_bl_yStream_o_fifoready,
    output wire [31:0] out_memdep_17_c_compSTR_avm_address,
    output wire [0:0] out_memdep_17_c_compSTR_avm_burstcount,
    output wire [511:0] out_memdep_17_c_compSTR_avm_byteenable,
    output wire [0:0] out_memdep_17_c_compSTR_avm_enable,
    output wire [0:0] out_memdep_17_c_compSTR_avm_read,
    output wire [0:0] out_memdep_17_c_compSTR_avm_write,
    output wire [4095:0] out_memdep_17_c_compSTR_avm_writedata,
    output wire [31:0] out_memdep_5_c_compSTR_avm_address,
    output wire [0:0] out_memdep_5_c_compSTR_avm_burstcount,
    output wire [511:0] out_memdep_5_c_compSTR_avm_byteenable,
    output wire [0:0] out_memdep_5_c_compSTR_avm_enable,
    output wire [0:0] out_memdep_5_c_compSTR_avm_read,
    output wire [0:0] out_memdep_5_c_compSTR_avm_write,
    output wire [4095:0] out_memdep_5_c_compSTR_avm_writedata,
    output wire [0:0] out_profile_loop_o_valid,
    output wire [0:0] out_stall_in_0,
    output wire [0:0] out_stall_out_0,
    output wire [0:0] out_valid_in_0,
    output wire [0:0] out_valid_out_0,
    input wire clock,
    input wire resetn
    );

    wire [0:0] bb_c_compSTR_B5_stall_region_out_almost_empty_out;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_c0_exe5719;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_c0_exe6720;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_empty_out;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_iord_bl_WStream_o_fifoalmost_full;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_iord_bl_WStream_o_fifoready;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_iord_bl_yStream_o_fifoalmost_full;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_iord_bl_yStream_o_fifoready;
    wire [31:0] bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_address;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_burstcount;
    wire [511:0] bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_byteenable;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_enable;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_read;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_write;
    wire [4095:0] bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_writedata;
    wire [31:0] bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_address;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_burstcount;
    wire [511:0] bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_byteenable;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_enable;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_read;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_write;
    wire [4095:0] bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_writedata;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_profile_loop_o_valid;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_stall_out;
    wire [0:0] bb_c_compSTR_B5_stall_region_out_valid_out;
    wire [0:0] c_compSTR_B5_branch_out_c0_exe6720;
    wire [0:0] c_compSTR_B5_branch_out_stall_out;
    wire [0:0] c_compSTR_B5_branch_out_valid_out_0;
    wire [0:0] c_compSTR_B5_merge_out_almost_empty_out;
    wire [0:0] c_compSTR_B5_merge_out_cmp21684;
    wire [0:0] c_compSTR_B5_merge_out_empty_out;
    wire [31:0] c_compSTR_B5_merge_out_i_0288_pop12683;
    wire [0:0] c_compSTR_B5_merge_out_memdep_phi9_pop1032_pop14687;
    wire [0:0] c_compSTR_B5_merge_out_memdep_phi9_pop10682;
    wire [0:0] c_compSTR_B5_merge_out_memdep_phi_pop930_pop13686;
    wire [0:0] c_compSTR_B5_merge_out_memdep_phi_pop9679;
    wire [0:0] c_compSTR_B5_merge_out_notcmp21685;
    wire [0:0] c_compSTR_B5_merge_out_stall_out_0;
    wire [0:0] c_compSTR_B5_merge_out_valid_out;
    reg [0:0] rst_sync_rst_sclrn;


    // c_compSTR_B5_merge(BLACKBOX,4)
    c_compSTR_B5_merge thec_compSTR_B5_merge (
        .in_cmp21684_0(in_cmp21684_0),
        .in_i_0288_pop12683_0(in_i_0288_pop12683_0),
        .in_memdep_phi9_pop1032_pop14687_0(in_memdep_phi9_pop1032_pop14687_0),
        .in_memdep_phi9_pop10682_0(in_memdep_phi9_pop10682_0),
        .in_memdep_phi_pop930_pop13686_0(in_memdep_phi_pop930_pop13686_0),
        .in_memdep_phi_pop9679_0(in_memdep_phi_pop9679_0),
        .in_notcmp21685_0(in_notcmp21685_0),
        .in_stall_in(bb_c_compSTR_B5_stall_region_out_stall_out),
        .in_valid_in_0(in_valid_in_0),
        .out_almost_empty_out(c_compSTR_B5_merge_out_almost_empty_out),
        .out_cmp21684(c_compSTR_B5_merge_out_cmp21684),
        .out_empty_out(c_compSTR_B5_merge_out_empty_out),
        .out_i_0288_pop12683(c_compSTR_B5_merge_out_i_0288_pop12683),
        .out_memdep_phi9_pop1032_pop14687(c_compSTR_B5_merge_out_memdep_phi9_pop1032_pop14687),
        .out_memdep_phi9_pop10682(c_compSTR_B5_merge_out_memdep_phi9_pop10682),
        .out_memdep_phi_pop930_pop13686(c_compSTR_B5_merge_out_memdep_phi_pop930_pop13686),
        .out_memdep_phi_pop9679(c_compSTR_B5_merge_out_memdep_phi_pop9679),
        .out_notcmp21685(c_compSTR_B5_merge_out_notcmp21685),
        .out_stall_out_0(c_compSTR_B5_merge_out_stall_out_0),
        .out_valid_out(c_compSTR_B5_merge_out_valid_out),
        .clock(clock),
        .resetn(resetn)
    );

    // bb_c_compSTR_B5_stall_region(BLACKBOX,2)
    c_compSTR_bb_B5_stall_region thebb_c_compSTR_B5_stall_region (
        .in_almost_empty_in(c_compSTR_B5_merge_out_almost_empty_out),
        .in_cmp21684(c_compSTR_B5_merge_out_cmp21684),
        .in_empty_in(c_compSTR_B5_merge_out_empty_out),
        .in_flush(in_flush),
        .in_i_0288_pop12683(c_compSTR_B5_merge_out_i_0288_pop12683),
        .in_iord_bl_WStream_i_fifodata(in_iord_bl_WStream_i_fifodata),
        .in_iord_bl_WStream_i_fifovalid(in_iord_bl_WStream_i_fifovalid),
        .in_iord_bl_yStream_i_fifodata(in_iord_bl_yStream_i_fifodata),
        .in_iord_bl_yStream_i_fifovalid(in_iord_bl_yStream_i_fifovalid),
        .in_memdep_17_c_compSTR_avm_readdata(in_memdep_17_c_compSTR_avm_readdata),
        .in_memdep_17_c_compSTR_avm_readdatavalid(in_memdep_17_c_compSTR_avm_readdatavalid),
        .in_memdep_17_c_compSTR_avm_waitrequest(in_memdep_17_c_compSTR_avm_waitrequest),
        .in_memdep_17_c_compSTR_avm_writeack(in_memdep_17_c_compSTR_avm_writeack),
        .in_memdep_5_c_compSTR_avm_readdata(in_memdep_5_c_compSTR_avm_readdata),
        .in_memdep_5_c_compSTR_avm_readdatavalid(in_memdep_5_c_compSTR_avm_readdatavalid),
        .in_memdep_5_c_compSTR_avm_waitrequest(in_memdep_5_c_compSTR_avm_waitrequest),
        .in_memdep_5_c_compSTR_avm_writeack(in_memdep_5_c_compSTR_avm_writeack),
        .in_memdep_phi9_pop1032_pop14687(c_compSTR_B5_merge_out_memdep_phi9_pop1032_pop14687),
        .in_memdep_phi9_pop10682(c_compSTR_B5_merge_out_memdep_phi9_pop10682),
        .in_memdep_phi_pop930_pop13686(c_compSTR_B5_merge_out_memdep_phi_pop930_pop13686),
        .in_memdep_phi_pop9679(c_compSTR_B5_merge_out_memdep_phi_pop9679),
        .in_notcmp21685(c_compSTR_B5_merge_out_notcmp21685),
        .in_stall_in(c_compSTR_B5_branch_out_stall_out),
        .in_valid_in(c_compSTR_B5_merge_out_valid_out),
        .out_almost_empty_out(bb_c_compSTR_B5_stall_region_out_almost_empty_out),
        .out_c0_exe5719(bb_c_compSTR_B5_stall_region_out_c0_exe5719),
        .out_c0_exe6720(bb_c_compSTR_B5_stall_region_out_c0_exe6720),
        .out_empty_out(bb_c_compSTR_B5_stall_region_out_empty_out),
        .out_iord_bl_WStream_o_fifoalmost_full(bb_c_compSTR_B5_stall_region_out_iord_bl_WStream_o_fifoalmost_full),
        .out_iord_bl_WStream_o_fifoready(bb_c_compSTR_B5_stall_region_out_iord_bl_WStream_o_fifoready),
        .out_iord_bl_yStream_o_fifoalmost_full(bb_c_compSTR_B5_stall_region_out_iord_bl_yStream_o_fifoalmost_full),
        .out_iord_bl_yStream_o_fifoready(bb_c_compSTR_B5_stall_region_out_iord_bl_yStream_o_fifoready),
        .out_memdep_17_c_compSTR_avm_address(bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_address),
        .out_memdep_17_c_compSTR_avm_burstcount(bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_burstcount),
        .out_memdep_17_c_compSTR_avm_byteenable(bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_byteenable),
        .out_memdep_17_c_compSTR_avm_enable(bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_enable),
        .out_memdep_17_c_compSTR_avm_read(bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_read),
        .out_memdep_17_c_compSTR_avm_write(bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_write),
        .out_memdep_17_c_compSTR_avm_writedata(bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_writedata),
        .out_memdep_5_c_compSTR_avm_address(bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_address),
        .out_memdep_5_c_compSTR_avm_burstcount(bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_burstcount),
        .out_memdep_5_c_compSTR_avm_byteenable(bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_byteenable),
        .out_memdep_5_c_compSTR_avm_enable(bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_enable),
        .out_memdep_5_c_compSTR_avm_read(bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_read),
        .out_memdep_5_c_compSTR_avm_write(bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_write),
        .out_memdep_5_c_compSTR_avm_writedata(bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_writedata),
        .out_profile_loop_o_valid(bb_c_compSTR_B5_stall_region_out_profile_loop_o_valid),
        .out_stall_out(bb_c_compSTR_B5_stall_region_out_stall_out),
        .out_valid_out(bb_c_compSTR_B5_stall_region_out_valid_out),
        .clock(clock),
        .resetn(resetn)
    );

    // c_compSTR_B5_branch(BLACKBOX,3)
    c_compSTR_B5_branch thec_compSTR_B5_branch (
        .in_almost_empty_in(bb_c_compSTR_B5_stall_region_out_almost_empty_out),
        .in_c0_exe5719(bb_c_compSTR_B5_stall_region_out_c0_exe5719),
        .in_c0_exe6720(bb_c_compSTR_B5_stall_region_out_c0_exe6720),
        .in_empty_in(bb_c_compSTR_B5_stall_region_out_empty_out),
        .in_stall_in_0(in_stall_in_0),
        .in_valid_in(bb_c_compSTR_B5_stall_region_out_valid_out),
        .out_c0_exe6720(c_compSTR_B5_branch_out_c0_exe6720),
        .out_stall_out(c_compSTR_B5_branch_out_stall_out),
        .out_valid_out_0(c_compSTR_B5_branch_out_valid_out_0),
        .clock(clock),
        .resetn(resetn)
    );

    // out_c0_exe6720(GPOUT,27)
    assign out_c0_exe6720 = c_compSTR_B5_branch_out_c0_exe6720;

    // out_iord_bl_WStream_o_fifoalmost_full(GPOUT,28)
    assign out_iord_bl_WStream_o_fifoalmost_full = bb_c_compSTR_B5_stall_region_out_iord_bl_WStream_o_fifoalmost_full;

    // out_iord_bl_WStream_o_fifoready(GPOUT,29)
    assign out_iord_bl_WStream_o_fifoready = bb_c_compSTR_B5_stall_region_out_iord_bl_WStream_o_fifoready;

    // out_iord_bl_yStream_o_fifoalmost_full(GPOUT,30)
    assign out_iord_bl_yStream_o_fifoalmost_full = bb_c_compSTR_B5_stall_region_out_iord_bl_yStream_o_fifoalmost_full;

    // out_iord_bl_yStream_o_fifoready(GPOUT,31)
    assign out_iord_bl_yStream_o_fifoready = bb_c_compSTR_B5_stall_region_out_iord_bl_yStream_o_fifoready;

    // out_memdep_17_c_compSTR_avm_address(GPOUT,32)
    assign out_memdep_17_c_compSTR_avm_address = bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_address;

    // out_memdep_17_c_compSTR_avm_burstcount(GPOUT,33)
    assign out_memdep_17_c_compSTR_avm_burstcount = bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_burstcount;

    // out_memdep_17_c_compSTR_avm_byteenable(GPOUT,34)
    assign out_memdep_17_c_compSTR_avm_byteenable = bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_byteenable;

    // out_memdep_17_c_compSTR_avm_enable(GPOUT,35)
    assign out_memdep_17_c_compSTR_avm_enable = bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_enable;

    // out_memdep_17_c_compSTR_avm_read(GPOUT,36)
    assign out_memdep_17_c_compSTR_avm_read = bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_read;

    // out_memdep_17_c_compSTR_avm_write(GPOUT,37)
    assign out_memdep_17_c_compSTR_avm_write = bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_write;

    // out_memdep_17_c_compSTR_avm_writedata(GPOUT,38)
    assign out_memdep_17_c_compSTR_avm_writedata = bb_c_compSTR_B5_stall_region_out_memdep_17_c_compSTR_avm_writedata;

    // out_memdep_5_c_compSTR_avm_address(GPOUT,39)
    assign out_memdep_5_c_compSTR_avm_address = bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_address;

    // out_memdep_5_c_compSTR_avm_burstcount(GPOUT,40)
    assign out_memdep_5_c_compSTR_avm_burstcount = bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_burstcount;

    // out_memdep_5_c_compSTR_avm_byteenable(GPOUT,41)
    assign out_memdep_5_c_compSTR_avm_byteenable = bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_byteenable;

    // out_memdep_5_c_compSTR_avm_enable(GPOUT,42)
    assign out_memdep_5_c_compSTR_avm_enable = bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_enable;

    // out_memdep_5_c_compSTR_avm_read(GPOUT,43)
    assign out_memdep_5_c_compSTR_avm_read = bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_read;

    // out_memdep_5_c_compSTR_avm_write(GPOUT,44)
    assign out_memdep_5_c_compSTR_avm_write = bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_write;

    // out_memdep_5_c_compSTR_avm_writedata(GPOUT,45)
    assign out_memdep_5_c_compSTR_avm_writedata = bb_c_compSTR_B5_stall_region_out_memdep_5_c_compSTR_avm_writedata;

    // out_profile_loop_o_valid(GPOUT,46)
    assign out_profile_loop_o_valid = bb_c_compSTR_B5_stall_region_out_profile_loop_o_valid;

    // out_stall_in_0(GPOUT,47)
    assign out_stall_in_0 = in_stall_in_0;

    // out_stall_out_0(GPOUT,48)
    assign out_stall_out_0 = c_compSTR_B5_merge_out_stall_out_0;

    // out_valid_in_0(GPOUT,49)
    assign out_valid_in_0 = in_valid_in_0;

    // out_valid_out_0(GPOUT,50)
    assign out_valid_out_0 = c_compSTR_B5_branch_out_valid_out_0;

    // rst_sync(RESETSYNC,51)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
