// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
// Legal Notice: Copyright 2022 Intel Corporation.  All rights reserved.
// Your use of  Intel Corporation's design tools,  logic functions and other
// software and  tools, and its AMPP partner logic functions, and any output
// files any  of the foregoing (including  device programming  or simulation
// files), and  any associated  documentation  or information  are expressly
// subject  to the terms and  conditions of the  Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement,  including,  without limitation,  that your use is for
// the  sole  purpose of  programming  logic devices  manufactured by  Intel
// and  sold by Intel  or its authorized  distributors. Please refer  to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------

// SystemVerilog created from i_sfc_logic_s_c3_in_wt_entry_c_compmm_ms_c3_enter_c_compmm_m0
// Created for function/kernel c_compMM_m
// SystemVerilog created on Wed Mar 26 11:59:06 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compMM_m_i_sfc_logic_s_c3_in_wt_entry_0000c3_enter_c_compmm_m0 (
    output wire [15:0] out_intel_reserved_ffwd_101_0,
    output wire [15:0] out_intel_reserved_ffwd_102_0,
    output wire [15:0] out_intel_reserved_ffwd_103_0,
    output wire [15:0] out_intel_reserved_ffwd_104_0,
    output wire [15:0] out_intel_reserved_ffwd_105_0,
    output wire [15:0] out_intel_reserved_ffwd_106_0,
    output wire [15:0] out_intel_reserved_ffwd_107_0,
    output wire [15:0] out_intel_reserved_ffwd_108_0,
    output wire [15:0] out_intel_reserved_ffwd_109_0,
    output wire [15:0] out_intel_reserved_ffwd_110_0,
    output wire [15:0] out_intel_reserved_ffwd_111_0,
    output wire [15:0] out_intel_reserved_ffwd_112_0,
    output wire [15:0] out_intel_reserved_ffwd_113_0,
    output wire [15:0] out_intel_reserved_ffwd_114_0,
    output wire [15:0] out_intel_reserved_ffwd_115_0,
    output wire [15:0] out_intel_reserved_ffwd_116_0,
    output wire [15:0] out_intel_reserved_ffwd_117_0,
    output wire [15:0] out_intel_reserved_ffwd_118_0,
    output wire [15:0] out_intel_reserved_ffwd_119_0,
    output wire [15:0] out_intel_reserved_ffwd_120_0,
    output wire [15:0] out_intel_reserved_ffwd_121_0,
    output wire [15:0] out_intel_reserved_ffwd_122_0,
    output wire [15:0] out_intel_reserved_ffwd_123_0,
    output wire [15:0] out_intel_reserved_ffwd_124_0,
    output wire [15:0] out_intel_reserved_ffwd_125_0,
    output wire [15:0] out_intel_reserved_ffwd_126_0,
    output wire [15:0] out_intel_reserved_ffwd_127_0,
    output wire [15:0] out_intel_reserved_ffwd_128_0,
    output wire [15:0] out_intel_reserved_ffwd_65_0,
    output wire [15:0] out_intel_reserved_ffwd_66_0,
    output wire [15:0] out_intel_reserved_ffwd_67_0,
    output wire [15:0] out_intel_reserved_ffwd_68_0,
    output wire [15:0] out_intel_reserved_ffwd_69_0,
    output wire [15:0] out_intel_reserved_ffwd_70_0,
    output wire [15:0] out_intel_reserved_ffwd_71_0,
    output wire [15:0] out_intel_reserved_ffwd_72_0,
    output wire [15:0] out_intel_reserved_ffwd_73_0,
    output wire [15:0] out_intel_reserved_ffwd_74_0,
    output wire [15:0] out_intel_reserved_ffwd_75_0,
    output wire [15:0] out_intel_reserved_ffwd_76_0,
    output wire [15:0] out_intel_reserved_ffwd_77_0,
    output wire [15:0] out_intel_reserved_ffwd_78_0,
    output wire [15:0] out_intel_reserved_ffwd_79_0,
    output wire [15:0] out_intel_reserved_ffwd_80_0,
    output wire [15:0] out_intel_reserved_ffwd_81_0,
    output wire [15:0] out_intel_reserved_ffwd_82_0,
    output wire [15:0] out_intel_reserved_ffwd_83_0,
    output wire [15:0] out_intel_reserved_ffwd_84_0,
    output wire [15:0] out_intel_reserved_ffwd_85_0,
    output wire [15:0] out_intel_reserved_ffwd_86_0,
    output wire [15:0] out_intel_reserved_ffwd_87_0,
    output wire [15:0] out_intel_reserved_ffwd_88_0,
    output wire [15:0] out_intel_reserved_ffwd_89_0,
    output wire [15:0] out_intel_reserved_ffwd_90_0,
    output wire [15:0] out_intel_reserved_ffwd_91_0,
    output wire [15:0] out_intel_reserved_ffwd_92_0,
    output wire [15:0] out_intel_reserved_ffwd_93_0,
    output wire [15:0] out_intel_reserved_ffwd_94_0,
    output wire [15:0] out_intel_reserved_ffwd_95_0,
    output wire [15:0] out_intel_reserved_ffwd_96_0,
    output wire [15:0] out_intel_reserved_ffwd_97_0,
    output wire [15:0] out_intel_reserved_ffwd_98_0,
    output wire [15:0] out_intel_reserved_ffwd_99_0,
    output wire [0:0] out_o_valid,
    output wire [0:0] out_unnamed_c_compMM_m134_0_tpl,
    output wire [0:0] out_unnamed_c_compMM_m4,
    input wire [0:0] in_c3_eni1_0_tpl,
    input wire [15:0] in_c3_eni1_1_tpl,
    input wire [15:0] in_c3_eni1_2_tpl,
    input wire [15:0] in_c3_eni1_3_tpl,
    input wire [15:0] in_c3_eni1_4_tpl,
    input wire [15:0] in_c3_eni1_5_tpl,
    input wire [15:0] in_c3_eni1_6_tpl,
    input wire [15:0] in_c3_eni1_7_tpl,
    input wire [15:0] in_c3_eni1_8_tpl,
    input wire [15:0] in_c3_eni1_9_tpl,
    input wire [15:0] in_c3_eni1_10_tpl,
    input wire [15:0] in_c3_eni1_11_tpl,
    input wire [15:0] in_c3_eni1_12_tpl,
    input wire [15:0] in_c3_eni1_13_tpl,
    input wire [15:0] in_c3_eni1_14_tpl,
    input wire [15:0] in_c3_eni1_15_tpl,
    input wire [15:0] in_c3_eni1_16_tpl,
    input wire [15:0] in_c3_eni1_17_tpl,
    input wire [15:0] in_c3_eni1_18_tpl,
    input wire [15:0] in_c3_eni1_19_tpl,
    input wire [15:0] in_c3_eni1_20_tpl,
    input wire [15:0] in_c3_eni1_21_tpl,
    input wire [15:0] in_c3_eni1_22_tpl,
    input wire [15:0] in_c3_eni1_23_tpl,
    input wire [15:0] in_c3_eni1_24_tpl,
    input wire [15:0] in_c3_eni1_25_tpl,
    input wire [15:0] in_c3_eni1_26_tpl,
    input wire [15:0] in_c3_eni1_27_tpl,
    input wire [15:0] in_c3_eni1_28_tpl,
    input wire [15:0] in_c3_eni1_29_tpl,
    input wire [15:0] in_c3_eni1_30_tpl,
    input wire [15:0] in_c3_eni1_31_tpl,
    input wire [15:0] in_c3_eni1_32_tpl,
    input wire [15:0] in_c3_eni1_33_tpl,
    input wire [15:0] in_c3_eni1_34_tpl,
    input wire [15:0] in_c3_eni1_35_tpl,
    input wire [15:0] in_c3_eni1_36_tpl,
    input wire [15:0] in_c3_eni1_37_tpl,
    input wire [15:0] in_c3_eni1_38_tpl,
    input wire [15:0] in_c3_eni1_39_tpl,
    input wire [15:0] in_c3_eni1_40_tpl,
    input wire [15:0] in_c3_eni1_41_tpl,
    input wire [15:0] in_c3_eni1_42_tpl,
    input wire [15:0] in_c3_eni1_43_tpl,
    input wire [15:0] in_c3_eni1_44_tpl,
    input wire [15:0] in_c3_eni1_45_tpl,
    input wire [15:0] in_c3_eni1_46_tpl,
    input wire [15:0] in_c3_eni1_47_tpl,
    input wire [15:0] in_c3_eni1_48_tpl,
    input wire [15:0] in_c3_eni1_49_tpl,
    input wire [15:0] in_c3_eni1_50_tpl,
    input wire [15:0] in_c3_eni1_51_tpl,
    input wire [15:0] in_c3_eni1_52_tpl,
    input wire [15:0] in_c3_eni1_53_tpl,
    input wire [15:0] in_c3_eni1_54_tpl,
    input wire [15:0] in_c3_eni1_55_tpl,
    input wire [15:0] in_c3_eni1_56_tpl,
    input wire [15:0] in_c3_eni1_57_tpl,
    input wire [15:0] in_c3_eni1_58_tpl,
    input wire [15:0] in_c3_eni1_59_tpl,
    input wire [15:0] in_c3_eni1_60_tpl,
    input wire [15:0] in_c3_eni1_61_tpl,
    input wire [15:0] in_c3_eni1_62_tpl,
    input wire [15:0] in_c3_eni1_63_tpl,
    input wire [15:0] in_c3_eni1_64_tpl,
    input wire [0:0] in_i_valid,
    output wire [15:0] out_intel_reserved_ffwd_100_0,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m100_c_compmm_m33_out_intel_reserved_ffwd_95_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m101_c_compmm_m34_out_intel_reserved_ffwd_96_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m102_c_compmm_m35_out_intel_reserved_ffwd_97_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m103_c_compmm_m36_out_intel_reserved_ffwd_98_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m104_c_compmm_m37_out_intel_reserved_ffwd_99_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m105_c_compmm_m38_out_intel_reserved_ffwd_100_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m106_c_compmm_m39_out_intel_reserved_ffwd_101_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m107_c_compmm_m40_out_intel_reserved_ffwd_102_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m108_c_compmm_m41_out_intel_reserved_ffwd_103_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m109_c_compmm_m42_out_intel_reserved_ffwd_104_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m110_c_compmm_m43_out_intel_reserved_ffwd_105_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m111_c_compmm_m44_out_intel_reserved_ffwd_106_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m112_c_compmm_m45_out_intel_reserved_ffwd_107_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m113_c_compmm_m46_out_intel_reserved_ffwd_108_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m114_c_compmm_m47_out_intel_reserved_ffwd_109_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m115_c_compmm_m48_out_intel_reserved_ffwd_110_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m116_c_compmm_m49_out_intel_reserved_ffwd_111_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m117_c_compmm_m50_out_intel_reserved_ffwd_112_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m118_c_compmm_m51_out_intel_reserved_ffwd_113_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m119_c_compmm_m52_out_intel_reserved_ffwd_114_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m120_c_compmm_m53_out_intel_reserved_ffwd_115_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m121_c_compmm_m54_out_intel_reserved_ffwd_116_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m122_c_compmm_m55_out_intel_reserved_ffwd_117_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m123_c_compmm_m56_out_intel_reserved_ffwd_118_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m124_c_compmm_m57_out_intel_reserved_ffwd_119_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m125_c_compmm_m58_out_intel_reserved_ffwd_120_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m126_c_compmm_m59_out_intel_reserved_ffwd_121_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m127_c_compmm_m60_out_intel_reserved_ffwd_122_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m128_c_compmm_m61_out_intel_reserved_ffwd_123_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m129_c_compmm_m62_out_intel_reserved_ffwd_124_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m130_c_compmm_m63_out_intel_reserved_ffwd_125_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m131_c_compmm_m64_out_intel_reserved_ffwd_126_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m132_c_compmm_m65_out_intel_reserved_ffwd_127_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m133_c_compmm_m66_out_intel_reserved_ffwd_128_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m70_c_compmm_m3_out_intel_reserved_ffwd_65_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m71_c_compmm_m4_out_intel_reserved_ffwd_66_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m72_c_compmm_m5_out_intel_reserved_ffwd_67_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m73_c_compmm_m6_out_intel_reserved_ffwd_68_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m74_c_compmm_m7_out_intel_reserved_ffwd_69_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m75_c_compmm_m8_out_intel_reserved_ffwd_70_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m76_c_compmm_m9_out_intel_reserved_ffwd_71_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m77_c_compmm_m10_out_intel_reserved_ffwd_72_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m78_c_compmm_m11_out_intel_reserved_ffwd_73_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m79_c_compmm_m12_out_intel_reserved_ffwd_74_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m80_c_compmm_m13_out_intel_reserved_ffwd_75_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m81_c_compmm_m14_out_intel_reserved_ffwd_76_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m82_c_compmm_m15_out_intel_reserved_ffwd_77_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m83_c_compmm_m16_out_intel_reserved_ffwd_78_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m84_c_compmm_m17_out_intel_reserved_ffwd_79_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m85_c_compmm_m18_out_intel_reserved_ffwd_80_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m86_c_compmm_m19_out_intel_reserved_ffwd_81_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m87_c_compmm_m20_out_intel_reserved_ffwd_82_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m88_c_compmm_m21_out_intel_reserved_ffwd_83_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m89_c_compmm_m22_out_intel_reserved_ffwd_84_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m90_c_compmm_m23_out_intel_reserved_ffwd_85_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m91_c_compmm_m24_out_intel_reserved_ffwd_86_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m92_c_compmm_m25_out_intel_reserved_ffwd_87_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m93_c_compmm_m26_out_intel_reserved_ffwd_88_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m94_c_compmm_m27_out_intel_reserved_ffwd_89_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m95_c_compmm_m28_out_intel_reserved_ffwd_90_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m96_c_compmm_m29_out_intel_reserved_ffwd_91_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m97_c_compmm_m30_out_intel_reserved_ffwd_92_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m98_c_compmm_m31_out_intel_reserved_ffwd_93_0;
    wire [15:0] i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m99_c_compmm_m32_out_intel_reserved_ffwd_94_0;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg0_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg1_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg2_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg3_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg4_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg5_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg6_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg7_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg8_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg9_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg10_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg11_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg12_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg13_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg14_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg15_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg16_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg17_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg18_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg19_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg20_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg21_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg22_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg23_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg24_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg25_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg26_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg27_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg28_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg29_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg30_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg31_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg32_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg33_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg34_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg35_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg36_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg37_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg38_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg39_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg40_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg41_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg42_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg43_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg44_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg45_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg46_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg47_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg48_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg49_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg50_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg51_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg52_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg53_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg54_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg55_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg56_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg57_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg58_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg59_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg60_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg61_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg62_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg63_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg64_q;
    reg [15:0] redist0_sync_together132_aunroll_x_in_c3_eni1_1_tpl_1_q;
    reg [15:0] redist1_sync_together132_aunroll_x_in_c3_eni1_2_tpl_1_q;
    reg [15:0] redist2_sync_together132_aunroll_x_in_c3_eni1_3_tpl_1_q;
    reg [15:0] redist3_sync_together132_aunroll_x_in_c3_eni1_4_tpl_1_q;
    reg [15:0] redist4_sync_together132_aunroll_x_in_c3_eni1_5_tpl_1_q;
    reg [15:0] redist5_sync_together132_aunroll_x_in_c3_eni1_6_tpl_1_q;
    reg [15:0] redist6_sync_together132_aunroll_x_in_c3_eni1_7_tpl_1_q;
    reg [15:0] redist7_sync_together132_aunroll_x_in_c3_eni1_8_tpl_1_q;
    reg [15:0] redist8_sync_together132_aunroll_x_in_c3_eni1_9_tpl_1_q;
    reg [15:0] redist9_sync_together132_aunroll_x_in_c3_eni1_10_tpl_1_q;
    reg [15:0] redist10_sync_together132_aunroll_x_in_c3_eni1_11_tpl_1_q;
    reg [15:0] redist11_sync_together132_aunroll_x_in_c3_eni1_12_tpl_1_q;
    reg [15:0] redist12_sync_together132_aunroll_x_in_c3_eni1_13_tpl_1_q;
    reg [15:0] redist13_sync_together132_aunroll_x_in_c3_eni1_14_tpl_1_q;
    reg [15:0] redist14_sync_together132_aunroll_x_in_c3_eni1_15_tpl_1_q;
    reg [15:0] redist15_sync_together132_aunroll_x_in_c3_eni1_16_tpl_1_q;
    reg [15:0] redist16_sync_together132_aunroll_x_in_c3_eni1_17_tpl_1_q;
    reg [15:0] redist17_sync_together132_aunroll_x_in_c3_eni1_18_tpl_1_q;
    reg [15:0] redist18_sync_together132_aunroll_x_in_c3_eni1_19_tpl_1_q;
    reg [15:0] redist19_sync_together132_aunroll_x_in_c3_eni1_20_tpl_1_q;
    reg [15:0] redist20_sync_together132_aunroll_x_in_c3_eni1_21_tpl_1_q;
    reg [15:0] redist21_sync_together132_aunroll_x_in_c3_eni1_22_tpl_1_q;
    reg [15:0] redist22_sync_together132_aunroll_x_in_c3_eni1_23_tpl_1_q;
    reg [15:0] redist23_sync_together132_aunroll_x_in_c3_eni1_24_tpl_1_q;
    reg [15:0] redist24_sync_together132_aunroll_x_in_c3_eni1_25_tpl_1_q;
    reg [15:0] redist25_sync_together132_aunroll_x_in_c3_eni1_26_tpl_1_q;
    reg [15:0] redist26_sync_together132_aunroll_x_in_c3_eni1_27_tpl_1_q;
    reg [15:0] redist27_sync_together132_aunroll_x_in_c3_eni1_28_tpl_1_q;
    reg [15:0] redist28_sync_together132_aunroll_x_in_c3_eni1_29_tpl_1_q;
    reg [15:0] redist29_sync_together132_aunroll_x_in_c3_eni1_30_tpl_1_q;
    reg [15:0] redist30_sync_together132_aunroll_x_in_c3_eni1_31_tpl_1_q;
    reg [15:0] redist31_sync_together132_aunroll_x_in_c3_eni1_32_tpl_1_q;
    reg [15:0] redist32_sync_together132_aunroll_x_in_c3_eni1_33_tpl_1_q;
    reg [15:0] redist33_sync_together132_aunroll_x_in_c3_eni1_34_tpl_1_q;
    reg [15:0] redist34_sync_together132_aunroll_x_in_c3_eni1_35_tpl_1_q;
    reg [15:0] redist35_sync_together132_aunroll_x_in_c3_eni1_36_tpl_1_q;
    reg [15:0] redist36_sync_together132_aunroll_x_in_c3_eni1_37_tpl_1_q;
    reg [15:0] redist37_sync_together132_aunroll_x_in_c3_eni1_38_tpl_1_q;
    reg [15:0] redist38_sync_together132_aunroll_x_in_c3_eni1_39_tpl_1_q;
    reg [15:0] redist39_sync_together132_aunroll_x_in_c3_eni1_40_tpl_1_q;
    reg [15:0] redist40_sync_together132_aunroll_x_in_c3_eni1_41_tpl_1_q;
    reg [15:0] redist41_sync_together132_aunroll_x_in_c3_eni1_42_tpl_1_q;
    reg [15:0] redist42_sync_together132_aunroll_x_in_c3_eni1_43_tpl_1_q;
    reg [15:0] redist43_sync_together132_aunroll_x_in_c3_eni1_44_tpl_1_q;
    reg [15:0] redist44_sync_together132_aunroll_x_in_c3_eni1_45_tpl_1_q;
    reg [15:0] redist45_sync_together132_aunroll_x_in_c3_eni1_46_tpl_1_q;
    reg [15:0] redist46_sync_together132_aunroll_x_in_c3_eni1_47_tpl_1_q;
    reg [15:0] redist47_sync_together132_aunroll_x_in_c3_eni1_48_tpl_1_q;
    reg [15:0] redist48_sync_together132_aunroll_x_in_c3_eni1_49_tpl_1_q;
    reg [15:0] redist49_sync_together132_aunroll_x_in_c3_eni1_50_tpl_1_q;
    reg [15:0] redist50_sync_together132_aunroll_x_in_c3_eni1_51_tpl_1_q;
    reg [15:0] redist51_sync_together132_aunroll_x_in_c3_eni1_52_tpl_1_q;
    reg [15:0] redist52_sync_together132_aunroll_x_in_c3_eni1_53_tpl_1_q;
    reg [15:0] redist53_sync_together132_aunroll_x_in_c3_eni1_54_tpl_1_q;
    reg [15:0] redist54_sync_together132_aunroll_x_in_c3_eni1_55_tpl_1_q;
    reg [15:0] redist55_sync_together132_aunroll_x_in_c3_eni1_56_tpl_1_q;
    reg [15:0] redist56_sync_together132_aunroll_x_in_c3_eni1_57_tpl_1_q;
    reg [15:0] redist57_sync_together132_aunroll_x_in_c3_eni1_58_tpl_1_q;
    reg [15:0] redist58_sync_together132_aunroll_x_in_c3_eni1_59_tpl_1_q;
    reg [15:0] redist59_sync_together132_aunroll_x_in_c3_eni1_60_tpl_1_q;
    reg [15:0] redist60_sync_together132_aunroll_x_in_c3_eni1_61_tpl_1_q;
    reg [15:0] redist61_sync_together132_aunroll_x_in_c3_eni1_62_tpl_1_q;
    reg [15:0] redist62_sync_together132_aunroll_x_in_c3_eni1_63_tpl_1_q;
    reg [15:0] redist63_sync_together132_aunroll_x_in_c3_eni1_64_tpl_1_q;


    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // valid_fanout_reg37(REG,234)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg37_q <= $unsigned(in_i_valid);
        end
    end

    // redist36_sync_together132_aunroll_x_in_c3_eni1_37_tpl_1(DELAY,298)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist36_sync_together132_aunroll_x_in_c3_eni1_37_tpl_1_q <= $unsigned(in_c3_eni1_37_tpl);
        end
    end

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m106_c_compmm_m39(BLACKBOX,137)@110
    // out out_intel_reserved_ffwd_101_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m106_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m106_c_compmm_m39 (
        .in_predicate_in(GND_q),
        .in_src_data_in_101_0(redist36_sync_together132_aunroll_x_in_c3_eni1_37_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg37_q),
        .out_intel_reserved_ffwd_101_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m106_c_compmm_m39_out_intel_reserved_ffwd_101_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_regfree_osync_x(GPOUT,2)
    assign out_intel_reserved_ffwd_101_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m106_c_compmm_m39_out_intel_reserved_ffwd_101_0;

    // valid_fanout_reg38(REG,235)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg38_q <= $unsigned(in_i_valid);
        end
    end

    // redist37_sync_together132_aunroll_x_in_c3_eni1_38_tpl_1(DELAY,299)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist37_sync_together132_aunroll_x_in_c3_eni1_38_tpl_1_q <= $unsigned(in_c3_eni1_38_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m107_c_compmm_m40(BLACKBOX,138)@110
    // out out_intel_reserved_ffwd_102_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m107_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m107_c_compmm_m40 (
        .in_predicate_in(GND_q),
        .in_src_data_in_102_0(redist37_sync_together132_aunroll_x_in_c3_eni1_38_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg38_q),
        .out_intel_reserved_ffwd_102_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m107_c_compmm_m40_out_intel_reserved_ffwd_102_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_1_regfree_osync_x(GPOUT,3)
    assign out_intel_reserved_ffwd_102_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m107_c_compmm_m40_out_intel_reserved_ffwd_102_0;

    // valid_fanout_reg39(REG,236)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg39_q <= $unsigned(in_i_valid);
        end
    end

    // redist38_sync_together132_aunroll_x_in_c3_eni1_39_tpl_1(DELAY,300)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist38_sync_together132_aunroll_x_in_c3_eni1_39_tpl_1_q <= $unsigned(in_c3_eni1_39_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m108_c_compmm_m41(BLACKBOX,139)@110
    // out out_intel_reserved_ffwd_103_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m108_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m108_c_compmm_m41 (
        .in_predicate_in(GND_q),
        .in_src_data_in_103_0(redist38_sync_together132_aunroll_x_in_c3_eni1_39_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg39_q),
        .out_intel_reserved_ffwd_103_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m108_c_compmm_m41_out_intel_reserved_ffwd_103_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_2_regfree_osync_x(GPOUT,4)
    assign out_intel_reserved_ffwd_103_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m108_c_compmm_m41_out_intel_reserved_ffwd_103_0;

    // valid_fanout_reg40(REG,237)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg40_q <= $unsigned(in_i_valid);
        end
    end

    // redist39_sync_together132_aunroll_x_in_c3_eni1_40_tpl_1(DELAY,301)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist39_sync_together132_aunroll_x_in_c3_eni1_40_tpl_1_q <= $unsigned(in_c3_eni1_40_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m109_c_compmm_m42(BLACKBOX,140)@110
    // out out_intel_reserved_ffwd_104_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m109_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m109_c_compmm_m42 (
        .in_predicate_in(GND_q),
        .in_src_data_in_104_0(redist39_sync_together132_aunroll_x_in_c3_eni1_40_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg40_q),
        .out_intel_reserved_ffwd_104_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m109_c_compmm_m42_out_intel_reserved_ffwd_104_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_3_regfree_osync_x(GPOUT,5)
    assign out_intel_reserved_ffwd_104_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m109_c_compmm_m42_out_intel_reserved_ffwd_104_0;

    // valid_fanout_reg41(REG,238)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg41_q <= $unsigned(in_i_valid);
        end
    end

    // redist40_sync_together132_aunroll_x_in_c3_eni1_41_tpl_1(DELAY,302)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist40_sync_together132_aunroll_x_in_c3_eni1_41_tpl_1_q <= $unsigned(in_c3_eni1_41_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m110_c_compmm_m43(BLACKBOX,141)@110
    // out out_intel_reserved_ffwd_105_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m110_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m110_c_compmm_m43 (
        .in_predicate_in(GND_q),
        .in_src_data_in_105_0(redist40_sync_together132_aunroll_x_in_c3_eni1_41_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg41_q),
        .out_intel_reserved_ffwd_105_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m110_c_compmm_m43_out_intel_reserved_ffwd_105_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_4_regfree_osync_x(GPOUT,6)
    assign out_intel_reserved_ffwd_105_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m110_c_compmm_m43_out_intel_reserved_ffwd_105_0;

    // valid_fanout_reg42(REG,239)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg42_q <= $unsigned(in_i_valid);
        end
    end

    // redist41_sync_together132_aunroll_x_in_c3_eni1_42_tpl_1(DELAY,303)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist41_sync_together132_aunroll_x_in_c3_eni1_42_tpl_1_q <= $unsigned(in_c3_eni1_42_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m111_c_compmm_m44(BLACKBOX,142)@110
    // out out_intel_reserved_ffwd_106_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m111_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m111_c_compmm_m44 (
        .in_predicate_in(GND_q),
        .in_src_data_in_106_0(redist41_sync_together132_aunroll_x_in_c3_eni1_42_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg42_q),
        .out_intel_reserved_ffwd_106_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m111_c_compmm_m44_out_intel_reserved_ffwd_106_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_5_regfree_osync_x(GPOUT,7)
    assign out_intel_reserved_ffwd_106_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m111_c_compmm_m44_out_intel_reserved_ffwd_106_0;

    // valid_fanout_reg43(REG,240)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg43_q <= $unsigned(in_i_valid);
        end
    end

    // redist42_sync_together132_aunroll_x_in_c3_eni1_43_tpl_1(DELAY,304)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist42_sync_together132_aunroll_x_in_c3_eni1_43_tpl_1_q <= $unsigned(in_c3_eni1_43_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m112_c_compmm_m45(BLACKBOX,143)@110
    // out out_intel_reserved_ffwd_107_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m112_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m112_c_compmm_m45 (
        .in_predicate_in(GND_q),
        .in_src_data_in_107_0(redist42_sync_together132_aunroll_x_in_c3_eni1_43_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg43_q),
        .out_intel_reserved_ffwd_107_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m112_c_compmm_m45_out_intel_reserved_ffwd_107_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_6_regfree_osync_x(GPOUT,8)
    assign out_intel_reserved_ffwd_107_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m112_c_compmm_m45_out_intel_reserved_ffwd_107_0;

    // valid_fanout_reg44(REG,241)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg44_q <= $unsigned(in_i_valid);
        end
    end

    // redist43_sync_together132_aunroll_x_in_c3_eni1_44_tpl_1(DELAY,305)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist43_sync_together132_aunroll_x_in_c3_eni1_44_tpl_1_q <= $unsigned(in_c3_eni1_44_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m113_c_compmm_m46(BLACKBOX,144)@110
    // out out_intel_reserved_ffwd_108_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m113_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m113_c_compmm_m46 (
        .in_predicate_in(GND_q),
        .in_src_data_in_108_0(redist43_sync_together132_aunroll_x_in_c3_eni1_44_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg44_q),
        .out_intel_reserved_ffwd_108_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m113_c_compmm_m46_out_intel_reserved_ffwd_108_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_7_regfree_osync_x(GPOUT,9)
    assign out_intel_reserved_ffwd_108_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m113_c_compmm_m46_out_intel_reserved_ffwd_108_0;

    // valid_fanout_reg45(REG,242)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg45_q <= $unsigned(in_i_valid);
        end
    end

    // redist44_sync_together132_aunroll_x_in_c3_eni1_45_tpl_1(DELAY,306)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist44_sync_together132_aunroll_x_in_c3_eni1_45_tpl_1_q <= $unsigned(in_c3_eni1_45_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m114_c_compmm_m47(BLACKBOX,145)@110
    // out out_intel_reserved_ffwd_109_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m114_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m114_c_compmm_m47 (
        .in_predicate_in(GND_q),
        .in_src_data_in_109_0(redist44_sync_together132_aunroll_x_in_c3_eni1_45_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg45_q),
        .out_intel_reserved_ffwd_109_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m114_c_compmm_m47_out_intel_reserved_ffwd_109_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_8_regfree_osync_x(GPOUT,10)
    assign out_intel_reserved_ffwd_109_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m114_c_compmm_m47_out_intel_reserved_ffwd_109_0;

    // valid_fanout_reg46(REG,243)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg46_q <= $unsigned(in_i_valid);
        end
    end

    // redist45_sync_together132_aunroll_x_in_c3_eni1_46_tpl_1(DELAY,307)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist45_sync_together132_aunroll_x_in_c3_eni1_46_tpl_1_q <= $unsigned(in_c3_eni1_46_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m115_c_compmm_m48(BLACKBOX,146)@110
    // out out_intel_reserved_ffwd_110_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m115_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m115_c_compmm_m48 (
        .in_predicate_in(GND_q),
        .in_src_data_in_110_0(redist45_sync_together132_aunroll_x_in_c3_eni1_46_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg46_q),
        .out_intel_reserved_ffwd_110_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m115_c_compmm_m48_out_intel_reserved_ffwd_110_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_9_regfree_osync_x(GPOUT,11)
    assign out_intel_reserved_ffwd_110_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m115_c_compmm_m48_out_intel_reserved_ffwd_110_0;

    // valid_fanout_reg47(REG,244)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg47_q <= $unsigned(in_i_valid);
        end
    end

    // redist46_sync_together132_aunroll_x_in_c3_eni1_47_tpl_1(DELAY,308)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist46_sync_together132_aunroll_x_in_c3_eni1_47_tpl_1_q <= $unsigned(in_c3_eni1_47_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m116_c_compmm_m49(BLACKBOX,147)@110
    // out out_intel_reserved_ffwd_111_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m116_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m116_c_compmm_m49 (
        .in_predicate_in(GND_q),
        .in_src_data_in_111_0(redist46_sync_together132_aunroll_x_in_c3_eni1_47_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg47_q),
        .out_intel_reserved_ffwd_111_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m116_c_compmm_m49_out_intel_reserved_ffwd_111_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_10_regfree_osync_x(GPOUT,12)
    assign out_intel_reserved_ffwd_111_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m116_c_compmm_m49_out_intel_reserved_ffwd_111_0;

    // valid_fanout_reg48(REG,245)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg48_q <= $unsigned(in_i_valid);
        end
    end

    // redist47_sync_together132_aunroll_x_in_c3_eni1_48_tpl_1(DELAY,309)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist47_sync_together132_aunroll_x_in_c3_eni1_48_tpl_1_q <= $unsigned(in_c3_eni1_48_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m117_c_compmm_m50(BLACKBOX,148)@110
    // out out_intel_reserved_ffwd_112_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m117_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m117_c_compmm_m50 (
        .in_predicate_in(GND_q),
        .in_src_data_in_112_0(redist47_sync_together132_aunroll_x_in_c3_eni1_48_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg48_q),
        .out_intel_reserved_ffwd_112_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m117_c_compmm_m50_out_intel_reserved_ffwd_112_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_11_regfree_osync_x(GPOUT,13)
    assign out_intel_reserved_ffwd_112_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m117_c_compmm_m50_out_intel_reserved_ffwd_112_0;

    // valid_fanout_reg49(REG,246)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg49_q <= $unsigned(in_i_valid);
        end
    end

    // redist48_sync_together132_aunroll_x_in_c3_eni1_49_tpl_1(DELAY,310)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist48_sync_together132_aunroll_x_in_c3_eni1_49_tpl_1_q <= $unsigned(in_c3_eni1_49_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m118_c_compmm_m51(BLACKBOX,149)@110
    // out out_intel_reserved_ffwd_113_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m118_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m118_c_compmm_m51 (
        .in_predicate_in(GND_q),
        .in_src_data_in_113_0(redist48_sync_together132_aunroll_x_in_c3_eni1_49_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg49_q),
        .out_intel_reserved_ffwd_113_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m118_c_compmm_m51_out_intel_reserved_ffwd_113_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_12_regfree_osync_x(GPOUT,14)
    assign out_intel_reserved_ffwd_113_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m118_c_compmm_m51_out_intel_reserved_ffwd_113_0;

    // valid_fanout_reg50(REG,247)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg50_q <= $unsigned(in_i_valid);
        end
    end

    // redist49_sync_together132_aunroll_x_in_c3_eni1_50_tpl_1(DELAY,311)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist49_sync_together132_aunroll_x_in_c3_eni1_50_tpl_1_q <= $unsigned(in_c3_eni1_50_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m119_c_compmm_m52(BLACKBOX,150)@110
    // out out_intel_reserved_ffwd_114_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m119_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m119_c_compmm_m52 (
        .in_predicate_in(GND_q),
        .in_src_data_in_114_0(redist49_sync_together132_aunroll_x_in_c3_eni1_50_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg50_q),
        .out_intel_reserved_ffwd_114_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m119_c_compmm_m52_out_intel_reserved_ffwd_114_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_13_regfree_osync_x(GPOUT,15)
    assign out_intel_reserved_ffwd_114_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m119_c_compmm_m52_out_intel_reserved_ffwd_114_0;

    // valid_fanout_reg51(REG,248)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg51_q <= $unsigned(in_i_valid);
        end
    end

    // redist50_sync_together132_aunroll_x_in_c3_eni1_51_tpl_1(DELAY,312)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist50_sync_together132_aunroll_x_in_c3_eni1_51_tpl_1_q <= $unsigned(in_c3_eni1_51_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m120_c_compmm_m53(BLACKBOX,151)@110
    // out out_intel_reserved_ffwd_115_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m120_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m120_c_compmm_m53 (
        .in_predicate_in(GND_q),
        .in_src_data_in_115_0(redist50_sync_together132_aunroll_x_in_c3_eni1_51_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg51_q),
        .out_intel_reserved_ffwd_115_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m120_c_compmm_m53_out_intel_reserved_ffwd_115_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_14_regfree_osync_x(GPOUT,16)
    assign out_intel_reserved_ffwd_115_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m120_c_compmm_m53_out_intel_reserved_ffwd_115_0;

    // valid_fanout_reg52(REG,249)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg52_q <= $unsigned(in_i_valid);
        end
    end

    // redist51_sync_together132_aunroll_x_in_c3_eni1_52_tpl_1(DELAY,313)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist51_sync_together132_aunroll_x_in_c3_eni1_52_tpl_1_q <= $unsigned(in_c3_eni1_52_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m121_c_compmm_m54(BLACKBOX,152)@110
    // out out_intel_reserved_ffwd_116_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m121_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m121_c_compmm_m54 (
        .in_predicate_in(GND_q),
        .in_src_data_in_116_0(redist51_sync_together132_aunroll_x_in_c3_eni1_52_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg52_q),
        .out_intel_reserved_ffwd_116_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m121_c_compmm_m54_out_intel_reserved_ffwd_116_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_15_regfree_osync_x(GPOUT,17)
    assign out_intel_reserved_ffwd_116_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m121_c_compmm_m54_out_intel_reserved_ffwd_116_0;

    // valid_fanout_reg53(REG,250)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg53_q <= $unsigned(in_i_valid);
        end
    end

    // redist52_sync_together132_aunroll_x_in_c3_eni1_53_tpl_1(DELAY,314)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist52_sync_together132_aunroll_x_in_c3_eni1_53_tpl_1_q <= $unsigned(in_c3_eni1_53_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m122_c_compmm_m55(BLACKBOX,153)@110
    // out out_intel_reserved_ffwd_117_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m122_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m122_c_compmm_m55 (
        .in_predicate_in(GND_q),
        .in_src_data_in_117_0(redist52_sync_together132_aunroll_x_in_c3_eni1_53_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg53_q),
        .out_intel_reserved_ffwd_117_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m122_c_compmm_m55_out_intel_reserved_ffwd_117_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_16_regfree_osync_x(GPOUT,18)
    assign out_intel_reserved_ffwd_117_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m122_c_compmm_m55_out_intel_reserved_ffwd_117_0;

    // valid_fanout_reg54(REG,251)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg54_q <= $unsigned(in_i_valid);
        end
    end

    // redist53_sync_together132_aunroll_x_in_c3_eni1_54_tpl_1(DELAY,315)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist53_sync_together132_aunroll_x_in_c3_eni1_54_tpl_1_q <= $unsigned(in_c3_eni1_54_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m123_c_compmm_m56(BLACKBOX,154)@110
    // out out_intel_reserved_ffwd_118_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m123_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m123_c_compmm_m56 (
        .in_predicate_in(GND_q),
        .in_src_data_in_118_0(redist53_sync_together132_aunroll_x_in_c3_eni1_54_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg54_q),
        .out_intel_reserved_ffwd_118_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m123_c_compmm_m56_out_intel_reserved_ffwd_118_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_17_regfree_osync_x(GPOUT,19)
    assign out_intel_reserved_ffwd_118_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m123_c_compmm_m56_out_intel_reserved_ffwd_118_0;

    // valid_fanout_reg55(REG,252)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg55_q <= $unsigned(in_i_valid);
        end
    end

    // redist54_sync_together132_aunroll_x_in_c3_eni1_55_tpl_1(DELAY,316)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist54_sync_together132_aunroll_x_in_c3_eni1_55_tpl_1_q <= $unsigned(in_c3_eni1_55_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m124_c_compmm_m57(BLACKBOX,155)@110
    // out out_intel_reserved_ffwd_119_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m124_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m124_c_compmm_m57 (
        .in_predicate_in(GND_q),
        .in_src_data_in_119_0(redist54_sync_together132_aunroll_x_in_c3_eni1_55_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg55_q),
        .out_intel_reserved_ffwd_119_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m124_c_compmm_m57_out_intel_reserved_ffwd_119_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_18_regfree_osync_x(GPOUT,20)
    assign out_intel_reserved_ffwd_119_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m124_c_compmm_m57_out_intel_reserved_ffwd_119_0;

    // valid_fanout_reg56(REG,253)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg56_q <= $unsigned(in_i_valid);
        end
    end

    // redist55_sync_together132_aunroll_x_in_c3_eni1_56_tpl_1(DELAY,317)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist55_sync_together132_aunroll_x_in_c3_eni1_56_tpl_1_q <= $unsigned(in_c3_eni1_56_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m125_c_compmm_m58(BLACKBOX,156)@110
    // out out_intel_reserved_ffwd_120_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m125_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m125_c_compmm_m58 (
        .in_predicate_in(GND_q),
        .in_src_data_in_120_0(redist55_sync_together132_aunroll_x_in_c3_eni1_56_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg56_q),
        .out_intel_reserved_ffwd_120_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m125_c_compmm_m58_out_intel_reserved_ffwd_120_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_19_regfree_osync_x(GPOUT,21)
    assign out_intel_reserved_ffwd_120_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m125_c_compmm_m58_out_intel_reserved_ffwd_120_0;

    // valid_fanout_reg57(REG,254)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg57_q <= $unsigned(in_i_valid);
        end
    end

    // redist56_sync_together132_aunroll_x_in_c3_eni1_57_tpl_1(DELAY,318)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist56_sync_together132_aunroll_x_in_c3_eni1_57_tpl_1_q <= $unsigned(in_c3_eni1_57_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m126_c_compmm_m59(BLACKBOX,157)@110
    // out out_intel_reserved_ffwd_121_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m126_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m126_c_compmm_m59 (
        .in_predicate_in(GND_q),
        .in_src_data_in_121_0(redist56_sync_together132_aunroll_x_in_c3_eni1_57_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg57_q),
        .out_intel_reserved_ffwd_121_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m126_c_compmm_m59_out_intel_reserved_ffwd_121_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_20_regfree_osync_x(GPOUT,22)
    assign out_intel_reserved_ffwd_121_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m126_c_compmm_m59_out_intel_reserved_ffwd_121_0;

    // valid_fanout_reg58(REG,255)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg58_q <= $unsigned(in_i_valid);
        end
    end

    // redist57_sync_together132_aunroll_x_in_c3_eni1_58_tpl_1(DELAY,319)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist57_sync_together132_aunroll_x_in_c3_eni1_58_tpl_1_q <= $unsigned(in_c3_eni1_58_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m127_c_compmm_m60(BLACKBOX,158)@110
    // out out_intel_reserved_ffwd_122_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m127_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m127_c_compmm_m60 (
        .in_predicate_in(GND_q),
        .in_src_data_in_122_0(redist57_sync_together132_aunroll_x_in_c3_eni1_58_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg58_q),
        .out_intel_reserved_ffwd_122_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m127_c_compmm_m60_out_intel_reserved_ffwd_122_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_21_regfree_osync_x(GPOUT,23)
    assign out_intel_reserved_ffwd_122_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m127_c_compmm_m60_out_intel_reserved_ffwd_122_0;

    // valid_fanout_reg59(REG,256)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg59_q <= $unsigned(in_i_valid);
        end
    end

    // redist58_sync_together132_aunroll_x_in_c3_eni1_59_tpl_1(DELAY,320)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist58_sync_together132_aunroll_x_in_c3_eni1_59_tpl_1_q <= $unsigned(in_c3_eni1_59_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m128_c_compmm_m61(BLACKBOX,159)@110
    // out out_intel_reserved_ffwd_123_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m128_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m128_c_compmm_m61 (
        .in_predicate_in(GND_q),
        .in_src_data_in_123_0(redist58_sync_together132_aunroll_x_in_c3_eni1_59_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg59_q),
        .out_intel_reserved_ffwd_123_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m128_c_compmm_m61_out_intel_reserved_ffwd_123_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_22_regfree_osync_x(GPOUT,24)
    assign out_intel_reserved_ffwd_123_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m128_c_compmm_m61_out_intel_reserved_ffwd_123_0;

    // valid_fanout_reg60(REG,257)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg60_q <= $unsigned(in_i_valid);
        end
    end

    // redist59_sync_together132_aunroll_x_in_c3_eni1_60_tpl_1(DELAY,321)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist59_sync_together132_aunroll_x_in_c3_eni1_60_tpl_1_q <= $unsigned(in_c3_eni1_60_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m129_c_compmm_m62(BLACKBOX,160)@110
    // out out_intel_reserved_ffwd_124_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m129_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m129_c_compmm_m62 (
        .in_predicate_in(GND_q),
        .in_src_data_in_124_0(redist59_sync_together132_aunroll_x_in_c3_eni1_60_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg60_q),
        .out_intel_reserved_ffwd_124_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m129_c_compmm_m62_out_intel_reserved_ffwd_124_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_23_regfree_osync_x(GPOUT,25)
    assign out_intel_reserved_ffwd_124_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m129_c_compmm_m62_out_intel_reserved_ffwd_124_0;

    // valid_fanout_reg61(REG,258)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg61_q <= $unsigned(in_i_valid);
        end
    end

    // redist60_sync_together132_aunroll_x_in_c3_eni1_61_tpl_1(DELAY,322)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist60_sync_together132_aunroll_x_in_c3_eni1_61_tpl_1_q <= $unsigned(in_c3_eni1_61_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m130_c_compmm_m63(BLACKBOX,161)@110
    // out out_intel_reserved_ffwd_125_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m130_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m130_c_compmm_m63 (
        .in_predicate_in(GND_q),
        .in_src_data_in_125_0(redist60_sync_together132_aunroll_x_in_c3_eni1_61_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg61_q),
        .out_intel_reserved_ffwd_125_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m130_c_compmm_m63_out_intel_reserved_ffwd_125_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_24_regfree_osync_x(GPOUT,26)
    assign out_intel_reserved_ffwd_125_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m130_c_compmm_m63_out_intel_reserved_ffwd_125_0;

    // valid_fanout_reg62(REG,259)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg62_q <= $unsigned(in_i_valid);
        end
    end

    // redist61_sync_together132_aunroll_x_in_c3_eni1_62_tpl_1(DELAY,323)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist61_sync_together132_aunroll_x_in_c3_eni1_62_tpl_1_q <= $unsigned(in_c3_eni1_62_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m131_c_compmm_m64(BLACKBOX,162)@110
    // out out_intel_reserved_ffwd_126_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m131_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m131_c_compmm_m64 (
        .in_predicate_in(GND_q),
        .in_src_data_in_126_0(redist61_sync_together132_aunroll_x_in_c3_eni1_62_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg62_q),
        .out_intel_reserved_ffwd_126_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m131_c_compmm_m64_out_intel_reserved_ffwd_126_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_25_regfree_osync_x(GPOUT,27)
    assign out_intel_reserved_ffwd_126_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m131_c_compmm_m64_out_intel_reserved_ffwd_126_0;

    // valid_fanout_reg63(REG,260)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg63_q <= $unsigned(in_i_valid);
        end
    end

    // redist62_sync_together132_aunroll_x_in_c3_eni1_63_tpl_1(DELAY,324)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist62_sync_together132_aunroll_x_in_c3_eni1_63_tpl_1_q <= $unsigned(in_c3_eni1_63_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m132_c_compmm_m65(BLACKBOX,163)@110
    // out out_intel_reserved_ffwd_127_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m132_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m132_c_compmm_m65 (
        .in_predicate_in(GND_q),
        .in_src_data_in_127_0(redist62_sync_together132_aunroll_x_in_c3_eni1_63_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg63_q),
        .out_intel_reserved_ffwd_127_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m132_c_compmm_m65_out_intel_reserved_ffwd_127_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_26_regfree_osync_x(GPOUT,28)
    assign out_intel_reserved_ffwd_127_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m132_c_compmm_m65_out_intel_reserved_ffwd_127_0;

    // valid_fanout_reg64(REG,261)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg64_q <= $unsigned(in_i_valid);
        end
    end

    // redist63_sync_together132_aunroll_x_in_c3_eni1_64_tpl_1(DELAY,325)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist63_sync_together132_aunroll_x_in_c3_eni1_64_tpl_1_q <= $unsigned(in_c3_eni1_64_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m133_c_compmm_m66(BLACKBOX,164)@110
    // out out_intel_reserved_ffwd_128_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m133_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m133_c_compmm_m66 (
        .in_predicate_in(GND_q),
        .in_src_data_in_128_0(redist63_sync_together132_aunroll_x_in_c3_eni1_64_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg64_q),
        .out_intel_reserved_ffwd_128_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m133_c_compmm_m66_out_intel_reserved_ffwd_128_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_27_regfree_osync_x(GPOUT,29)
    assign out_intel_reserved_ffwd_128_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m133_c_compmm_m66_out_intel_reserved_ffwd_128_0;

    // valid_fanout_reg1(REG,198)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg1_q <= $unsigned(in_i_valid);
        end
    end

    // redist0_sync_together132_aunroll_x_in_c3_eni1_1_tpl_1(DELAY,262)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_sync_together132_aunroll_x_in_c3_eni1_1_tpl_1_q <= $unsigned(in_c3_eni1_1_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m70_c_compmm_m3(BLACKBOX,165)@110
    // out out_intel_reserved_ffwd_65_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m70_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m70_c_compmm_m3 (
        .in_predicate_in(GND_q),
        .in_src_data_in_65_0(redist0_sync_together132_aunroll_x_in_c3_eni1_1_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg1_q),
        .out_intel_reserved_ffwd_65_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m70_c_compmm_m3_out_intel_reserved_ffwd_65_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_28_regfree_osync_x(GPOUT,30)
    assign out_intel_reserved_ffwd_65_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m70_c_compmm_m3_out_intel_reserved_ffwd_65_0;

    // valid_fanout_reg2(REG,199)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg2_q <= $unsigned(in_i_valid);
        end
    end

    // redist1_sync_together132_aunroll_x_in_c3_eni1_2_tpl_1(DELAY,263)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1_sync_together132_aunroll_x_in_c3_eni1_2_tpl_1_q <= $unsigned(in_c3_eni1_2_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m71_c_compmm_m4(BLACKBOX,166)@110
    // out out_intel_reserved_ffwd_66_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m71_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m71_c_compmm_m4 (
        .in_predicate_in(GND_q),
        .in_src_data_in_66_0(redist1_sync_together132_aunroll_x_in_c3_eni1_2_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg2_q),
        .out_intel_reserved_ffwd_66_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m71_c_compmm_m4_out_intel_reserved_ffwd_66_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_29_regfree_osync_x(GPOUT,31)
    assign out_intel_reserved_ffwd_66_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m71_c_compmm_m4_out_intel_reserved_ffwd_66_0;

    // valid_fanout_reg3(REG,200)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg3_q <= $unsigned(in_i_valid);
        end
    end

    // redist2_sync_together132_aunroll_x_in_c3_eni1_3_tpl_1(DELAY,264)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist2_sync_together132_aunroll_x_in_c3_eni1_3_tpl_1_q <= $unsigned(in_c3_eni1_3_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m72_c_compmm_m5(BLACKBOX,167)@110
    // out out_intel_reserved_ffwd_67_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m72_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m72_c_compmm_m5 (
        .in_predicate_in(GND_q),
        .in_src_data_in_67_0(redist2_sync_together132_aunroll_x_in_c3_eni1_3_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg3_q),
        .out_intel_reserved_ffwd_67_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m72_c_compmm_m5_out_intel_reserved_ffwd_67_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_30_regfree_osync_x(GPOUT,32)
    assign out_intel_reserved_ffwd_67_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m72_c_compmm_m5_out_intel_reserved_ffwd_67_0;

    // valid_fanout_reg4(REG,201)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg4_q <= $unsigned(in_i_valid);
        end
    end

    // redist3_sync_together132_aunroll_x_in_c3_eni1_4_tpl_1(DELAY,265)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist3_sync_together132_aunroll_x_in_c3_eni1_4_tpl_1_q <= $unsigned(in_c3_eni1_4_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m73_c_compmm_m6(BLACKBOX,168)@110
    // out out_intel_reserved_ffwd_68_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m73_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m73_c_compmm_m6 (
        .in_predicate_in(GND_q),
        .in_src_data_in_68_0(redist3_sync_together132_aunroll_x_in_c3_eni1_4_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg4_q),
        .out_intel_reserved_ffwd_68_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m73_c_compmm_m6_out_intel_reserved_ffwd_68_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_31_regfree_osync_x(GPOUT,33)
    assign out_intel_reserved_ffwd_68_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m73_c_compmm_m6_out_intel_reserved_ffwd_68_0;

    // valid_fanout_reg5(REG,202)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg5_q <= $unsigned(in_i_valid);
        end
    end

    // redist4_sync_together132_aunroll_x_in_c3_eni1_5_tpl_1(DELAY,266)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist4_sync_together132_aunroll_x_in_c3_eni1_5_tpl_1_q <= $unsigned(in_c3_eni1_5_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m74_c_compmm_m7(BLACKBOX,169)@110
    // out out_intel_reserved_ffwd_69_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m74_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m74_c_compmm_m7 (
        .in_predicate_in(GND_q),
        .in_src_data_in_69_0(redist4_sync_together132_aunroll_x_in_c3_eni1_5_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg5_q),
        .out_intel_reserved_ffwd_69_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m74_c_compmm_m7_out_intel_reserved_ffwd_69_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_32_regfree_osync_x(GPOUT,34)
    assign out_intel_reserved_ffwd_69_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m74_c_compmm_m7_out_intel_reserved_ffwd_69_0;

    // valid_fanout_reg6(REG,203)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg6_q <= $unsigned(in_i_valid);
        end
    end

    // redist5_sync_together132_aunroll_x_in_c3_eni1_6_tpl_1(DELAY,267)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist5_sync_together132_aunroll_x_in_c3_eni1_6_tpl_1_q <= $unsigned(in_c3_eni1_6_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m75_c_compmm_m8(BLACKBOX,170)@110
    // out out_intel_reserved_ffwd_70_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m75_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m75_c_compmm_m8 (
        .in_predicate_in(GND_q),
        .in_src_data_in_70_0(redist5_sync_together132_aunroll_x_in_c3_eni1_6_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg6_q),
        .out_intel_reserved_ffwd_70_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m75_c_compmm_m8_out_intel_reserved_ffwd_70_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_33_regfree_osync_x(GPOUT,35)
    assign out_intel_reserved_ffwd_70_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m75_c_compmm_m8_out_intel_reserved_ffwd_70_0;

    // valid_fanout_reg7(REG,204)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg7_q <= $unsigned(in_i_valid);
        end
    end

    // redist6_sync_together132_aunroll_x_in_c3_eni1_7_tpl_1(DELAY,268)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist6_sync_together132_aunroll_x_in_c3_eni1_7_tpl_1_q <= $unsigned(in_c3_eni1_7_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m76_c_compmm_m9(BLACKBOX,171)@110
    // out out_intel_reserved_ffwd_71_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m76_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m76_c_compmm_m9 (
        .in_predicate_in(GND_q),
        .in_src_data_in_71_0(redist6_sync_together132_aunroll_x_in_c3_eni1_7_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg7_q),
        .out_intel_reserved_ffwd_71_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m76_c_compmm_m9_out_intel_reserved_ffwd_71_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_34_regfree_osync_x(GPOUT,36)
    assign out_intel_reserved_ffwd_71_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m76_c_compmm_m9_out_intel_reserved_ffwd_71_0;

    // valid_fanout_reg8(REG,205)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg8_q <= $unsigned(in_i_valid);
        end
    end

    // redist7_sync_together132_aunroll_x_in_c3_eni1_8_tpl_1(DELAY,269)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist7_sync_together132_aunroll_x_in_c3_eni1_8_tpl_1_q <= $unsigned(in_c3_eni1_8_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m77_c_compmm_m10(BLACKBOX,172)@110
    // out out_intel_reserved_ffwd_72_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m77_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m77_c_compmm_m10 (
        .in_predicate_in(GND_q),
        .in_src_data_in_72_0(redist7_sync_together132_aunroll_x_in_c3_eni1_8_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg8_q),
        .out_intel_reserved_ffwd_72_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m77_c_compmm_m10_out_intel_reserved_ffwd_72_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_35_regfree_osync_x(GPOUT,37)
    assign out_intel_reserved_ffwd_72_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m77_c_compmm_m10_out_intel_reserved_ffwd_72_0;

    // valid_fanout_reg9(REG,206)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg9_q <= $unsigned(in_i_valid);
        end
    end

    // redist8_sync_together132_aunroll_x_in_c3_eni1_9_tpl_1(DELAY,270)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist8_sync_together132_aunroll_x_in_c3_eni1_9_tpl_1_q <= $unsigned(in_c3_eni1_9_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m78_c_compmm_m11(BLACKBOX,173)@110
    // out out_intel_reserved_ffwd_73_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m78_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m78_c_compmm_m11 (
        .in_predicate_in(GND_q),
        .in_src_data_in_73_0(redist8_sync_together132_aunroll_x_in_c3_eni1_9_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg9_q),
        .out_intel_reserved_ffwd_73_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m78_c_compmm_m11_out_intel_reserved_ffwd_73_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_36_regfree_osync_x(GPOUT,38)
    assign out_intel_reserved_ffwd_73_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m78_c_compmm_m11_out_intel_reserved_ffwd_73_0;

    // valid_fanout_reg10(REG,207)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg10_q <= $unsigned(in_i_valid);
        end
    end

    // redist9_sync_together132_aunroll_x_in_c3_eni1_10_tpl_1(DELAY,271)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist9_sync_together132_aunroll_x_in_c3_eni1_10_tpl_1_q <= $unsigned(in_c3_eni1_10_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m79_c_compmm_m12(BLACKBOX,174)@110
    // out out_intel_reserved_ffwd_74_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m79_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m79_c_compmm_m12 (
        .in_predicate_in(GND_q),
        .in_src_data_in_74_0(redist9_sync_together132_aunroll_x_in_c3_eni1_10_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg10_q),
        .out_intel_reserved_ffwd_74_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m79_c_compmm_m12_out_intel_reserved_ffwd_74_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_37_regfree_osync_x(GPOUT,39)
    assign out_intel_reserved_ffwd_74_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m79_c_compmm_m12_out_intel_reserved_ffwd_74_0;

    // valid_fanout_reg11(REG,208)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg11_q <= $unsigned(in_i_valid);
        end
    end

    // redist10_sync_together132_aunroll_x_in_c3_eni1_11_tpl_1(DELAY,272)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist10_sync_together132_aunroll_x_in_c3_eni1_11_tpl_1_q <= $unsigned(in_c3_eni1_11_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m80_c_compmm_m13(BLACKBOX,175)@110
    // out out_intel_reserved_ffwd_75_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m80_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m80_c_compmm_m13 (
        .in_predicate_in(GND_q),
        .in_src_data_in_75_0(redist10_sync_together132_aunroll_x_in_c3_eni1_11_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg11_q),
        .out_intel_reserved_ffwd_75_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m80_c_compmm_m13_out_intel_reserved_ffwd_75_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_38_regfree_osync_x(GPOUT,40)
    assign out_intel_reserved_ffwd_75_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m80_c_compmm_m13_out_intel_reserved_ffwd_75_0;

    // valid_fanout_reg12(REG,209)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg12_q <= $unsigned(in_i_valid);
        end
    end

    // redist11_sync_together132_aunroll_x_in_c3_eni1_12_tpl_1(DELAY,273)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist11_sync_together132_aunroll_x_in_c3_eni1_12_tpl_1_q <= $unsigned(in_c3_eni1_12_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m81_c_compmm_m14(BLACKBOX,176)@110
    // out out_intel_reserved_ffwd_76_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m81_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m81_c_compmm_m14 (
        .in_predicate_in(GND_q),
        .in_src_data_in_76_0(redist11_sync_together132_aunroll_x_in_c3_eni1_12_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg12_q),
        .out_intel_reserved_ffwd_76_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m81_c_compmm_m14_out_intel_reserved_ffwd_76_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_39_regfree_osync_x(GPOUT,41)
    assign out_intel_reserved_ffwd_76_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m81_c_compmm_m14_out_intel_reserved_ffwd_76_0;

    // valid_fanout_reg13(REG,210)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg13_q <= $unsigned(in_i_valid);
        end
    end

    // redist12_sync_together132_aunroll_x_in_c3_eni1_13_tpl_1(DELAY,274)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist12_sync_together132_aunroll_x_in_c3_eni1_13_tpl_1_q <= $unsigned(in_c3_eni1_13_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m82_c_compmm_m15(BLACKBOX,177)@110
    // out out_intel_reserved_ffwd_77_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m82_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m82_c_compmm_m15 (
        .in_predicate_in(GND_q),
        .in_src_data_in_77_0(redist12_sync_together132_aunroll_x_in_c3_eni1_13_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg13_q),
        .out_intel_reserved_ffwd_77_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m82_c_compmm_m15_out_intel_reserved_ffwd_77_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_40_regfree_osync_x(GPOUT,42)
    assign out_intel_reserved_ffwd_77_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m82_c_compmm_m15_out_intel_reserved_ffwd_77_0;

    // valid_fanout_reg14(REG,211)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg14_q <= $unsigned(in_i_valid);
        end
    end

    // redist13_sync_together132_aunroll_x_in_c3_eni1_14_tpl_1(DELAY,275)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist13_sync_together132_aunroll_x_in_c3_eni1_14_tpl_1_q <= $unsigned(in_c3_eni1_14_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m83_c_compmm_m16(BLACKBOX,178)@110
    // out out_intel_reserved_ffwd_78_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m83_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m83_c_compmm_m16 (
        .in_predicate_in(GND_q),
        .in_src_data_in_78_0(redist13_sync_together132_aunroll_x_in_c3_eni1_14_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg14_q),
        .out_intel_reserved_ffwd_78_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m83_c_compmm_m16_out_intel_reserved_ffwd_78_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_41_regfree_osync_x(GPOUT,43)
    assign out_intel_reserved_ffwd_78_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m83_c_compmm_m16_out_intel_reserved_ffwd_78_0;

    // valid_fanout_reg15(REG,212)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg15_q <= $unsigned(in_i_valid);
        end
    end

    // redist14_sync_together132_aunroll_x_in_c3_eni1_15_tpl_1(DELAY,276)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist14_sync_together132_aunroll_x_in_c3_eni1_15_tpl_1_q <= $unsigned(in_c3_eni1_15_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m84_c_compmm_m17(BLACKBOX,179)@110
    // out out_intel_reserved_ffwd_79_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m84_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m84_c_compmm_m17 (
        .in_predicate_in(GND_q),
        .in_src_data_in_79_0(redist14_sync_together132_aunroll_x_in_c3_eni1_15_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg15_q),
        .out_intel_reserved_ffwd_79_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m84_c_compmm_m17_out_intel_reserved_ffwd_79_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_42_regfree_osync_x(GPOUT,44)
    assign out_intel_reserved_ffwd_79_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m84_c_compmm_m17_out_intel_reserved_ffwd_79_0;

    // valid_fanout_reg16(REG,213)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg16_q <= $unsigned(in_i_valid);
        end
    end

    // redist15_sync_together132_aunroll_x_in_c3_eni1_16_tpl_1(DELAY,277)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist15_sync_together132_aunroll_x_in_c3_eni1_16_tpl_1_q <= $unsigned(in_c3_eni1_16_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m85_c_compmm_m18(BLACKBOX,180)@110
    // out out_intel_reserved_ffwd_80_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m85_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m85_c_compmm_m18 (
        .in_predicate_in(GND_q),
        .in_src_data_in_80_0(redist15_sync_together132_aunroll_x_in_c3_eni1_16_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg16_q),
        .out_intel_reserved_ffwd_80_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m85_c_compmm_m18_out_intel_reserved_ffwd_80_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_43_regfree_osync_x(GPOUT,45)
    assign out_intel_reserved_ffwd_80_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m85_c_compmm_m18_out_intel_reserved_ffwd_80_0;

    // valid_fanout_reg17(REG,214)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg17_q <= $unsigned(in_i_valid);
        end
    end

    // redist16_sync_together132_aunroll_x_in_c3_eni1_17_tpl_1(DELAY,278)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist16_sync_together132_aunroll_x_in_c3_eni1_17_tpl_1_q <= $unsigned(in_c3_eni1_17_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m86_c_compmm_m19(BLACKBOX,181)@110
    // out out_intel_reserved_ffwd_81_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m86_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m86_c_compmm_m19 (
        .in_predicate_in(GND_q),
        .in_src_data_in_81_0(redist16_sync_together132_aunroll_x_in_c3_eni1_17_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg17_q),
        .out_intel_reserved_ffwd_81_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m86_c_compmm_m19_out_intel_reserved_ffwd_81_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_44_regfree_osync_x(GPOUT,46)
    assign out_intel_reserved_ffwd_81_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m86_c_compmm_m19_out_intel_reserved_ffwd_81_0;

    // valid_fanout_reg18(REG,215)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg18_q <= $unsigned(in_i_valid);
        end
    end

    // redist17_sync_together132_aunroll_x_in_c3_eni1_18_tpl_1(DELAY,279)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist17_sync_together132_aunroll_x_in_c3_eni1_18_tpl_1_q <= $unsigned(in_c3_eni1_18_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m87_c_compmm_m20(BLACKBOX,182)@110
    // out out_intel_reserved_ffwd_82_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m87_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m87_c_compmm_m20 (
        .in_predicate_in(GND_q),
        .in_src_data_in_82_0(redist17_sync_together132_aunroll_x_in_c3_eni1_18_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg18_q),
        .out_intel_reserved_ffwd_82_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m87_c_compmm_m20_out_intel_reserved_ffwd_82_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_45_regfree_osync_x(GPOUT,47)
    assign out_intel_reserved_ffwd_82_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m87_c_compmm_m20_out_intel_reserved_ffwd_82_0;

    // valid_fanout_reg19(REG,216)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg19_q <= $unsigned(in_i_valid);
        end
    end

    // redist18_sync_together132_aunroll_x_in_c3_eni1_19_tpl_1(DELAY,280)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist18_sync_together132_aunroll_x_in_c3_eni1_19_tpl_1_q <= $unsigned(in_c3_eni1_19_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m88_c_compmm_m21(BLACKBOX,183)@110
    // out out_intel_reserved_ffwd_83_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m88_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m88_c_compmm_m21 (
        .in_predicate_in(GND_q),
        .in_src_data_in_83_0(redist18_sync_together132_aunroll_x_in_c3_eni1_19_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg19_q),
        .out_intel_reserved_ffwd_83_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m88_c_compmm_m21_out_intel_reserved_ffwd_83_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_46_regfree_osync_x(GPOUT,48)
    assign out_intel_reserved_ffwd_83_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m88_c_compmm_m21_out_intel_reserved_ffwd_83_0;

    // valid_fanout_reg20(REG,217)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg20_q <= $unsigned(in_i_valid);
        end
    end

    // redist19_sync_together132_aunroll_x_in_c3_eni1_20_tpl_1(DELAY,281)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist19_sync_together132_aunroll_x_in_c3_eni1_20_tpl_1_q <= $unsigned(in_c3_eni1_20_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m89_c_compmm_m22(BLACKBOX,184)@110
    // out out_intel_reserved_ffwd_84_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m89_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m89_c_compmm_m22 (
        .in_predicate_in(GND_q),
        .in_src_data_in_84_0(redist19_sync_together132_aunroll_x_in_c3_eni1_20_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg20_q),
        .out_intel_reserved_ffwd_84_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m89_c_compmm_m22_out_intel_reserved_ffwd_84_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_47_regfree_osync_x(GPOUT,49)
    assign out_intel_reserved_ffwd_84_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m89_c_compmm_m22_out_intel_reserved_ffwd_84_0;

    // valid_fanout_reg21(REG,218)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg21_q <= $unsigned(in_i_valid);
        end
    end

    // redist20_sync_together132_aunroll_x_in_c3_eni1_21_tpl_1(DELAY,282)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist20_sync_together132_aunroll_x_in_c3_eni1_21_tpl_1_q <= $unsigned(in_c3_eni1_21_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m90_c_compmm_m23(BLACKBOX,185)@110
    // out out_intel_reserved_ffwd_85_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m90_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m90_c_compmm_m23 (
        .in_predicate_in(GND_q),
        .in_src_data_in_85_0(redist20_sync_together132_aunroll_x_in_c3_eni1_21_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg21_q),
        .out_intel_reserved_ffwd_85_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m90_c_compmm_m23_out_intel_reserved_ffwd_85_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_48_regfree_osync_x(GPOUT,50)
    assign out_intel_reserved_ffwd_85_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m90_c_compmm_m23_out_intel_reserved_ffwd_85_0;

    // valid_fanout_reg22(REG,219)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg22_q <= $unsigned(in_i_valid);
        end
    end

    // redist21_sync_together132_aunroll_x_in_c3_eni1_22_tpl_1(DELAY,283)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist21_sync_together132_aunroll_x_in_c3_eni1_22_tpl_1_q <= $unsigned(in_c3_eni1_22_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m91_c_compmm_m24(BLACKBOX,186)@110
    // out out_intel_reserved_ffwd_86_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m91_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m91_c_compmm_m24 (
        .in_predicate_in(GND_q),
        .in_src_data_in_86_0(redist21_sync_together132_aunroll_x_in_c3_eni1_22_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg22_q),
        .out_intel_reserved_ffwd_86_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m91_c_compmm_m24_out_intel_reserved_ffwd_86_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_49_regfree_osync_x(GPOUT,51)
    assign out_intel_reserved_ffwd_86_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m91_c_compmm_m24_out_intel_reserved_ffwd_86_0;

    // valid_fanout_reg23(REG,220)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg23_q <= $unsigned(in_i_valid);
        end
    end

    // redist22_sync_together132_aunroll_x_in_c3_eni1_23_tpl_1(DELAY,284)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist22_sync_together132_aunroll_x_in_c3_eni1_23_tpl_1_q <= $unsigned(in_c3_eni1_23_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m92_c_compmm_m25(BLACKBOX,187)@110
    // out out_intel_reserved_ffwd_87_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m92_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m92_c_compmm_m25 (
        .in_predicate_in(GND_q),
        .in_src_data_in_87_0(redist22_sync_together132_aunroll_x_in_c3_eni1_23_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg23_q),
        .out_intel_reserved_ffwd_87_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m92_c_compmm_m25_out_intel_reserved_ffwd_87_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_50_regfree_osync_x(GPOUT,52)
    assign out_intel_reserved_ffwd_87_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m92_c_compmm_m25_out_intel_reserved_ffwd_87_0;

    // valid_fanout_reg24(REG,221)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg24_q <= $unsigned(in_i_valid);
        end
    end

    // redist23_sync_together132_aunroll_x_in_c3_eni1_24_tpl_1(DELAY,285)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist23_sync_together132_aunroll_x_in_c3_eni1_24_tpl_1_q <= $unsigned(in_c3_eni1_24_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m93_c_compmm_m26(BLACKBOX,188)@110
    // out out_intel_reserved_ffwd_88_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m93_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m93_c_compmm_m26 (
        .in_predicate_in(GND_q),
        .in_src_data_in_88_0(redist23_sync_together132_aunroll_x_in_c3_eni1_24_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg24_q),
        .out_intel_reserved_ffwd_88_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m93_c_compmm_m26_out_intel_reserved_ffwd_88_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_51_regfree_osync_x(GPOUT,53)
    assign out_intel_reserved_ffwd_88_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m93_c_compmm_m26_out_intel_reserved_ffwd_88_0;

    // valid_fanout_reg25(REG,222)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg25_q <= $unsigned(in_i_valid);
        end
    end

    // redist24_sync_together132_aunroll_x_in_c3_eni1_25_tpl_1(DELAY,286)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist24_sync_together132_aunroll_x_in_c3_eni1_25_tpl_1_q <= $unsigned(in_c3_eni1_25_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m94_c_compmm_m27(BLACKBOX,189)@110
    // out out_intel_reserved_ffwd_89_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m94_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m94_c_compmm_m27 (
        .in_predicate_in(GND_q),
        .in_src_data_in_89_0(redist24_sync_together132_aunroll_x_in_c3_eni1_25_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg25_q),
        .out_intel_reserved_ffwd_89_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m94_c_compmm_m27_out_intel_reserved_ffwd_89_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_52_regfree_osync_x(GPOUT,54)
    assign out_intel_reserved_ffwd_89_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m94_c_compmm_m27_out_intel_reserved_ffwd_89_0;

    // valid_fanout_reg26(REG,223)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg26_q <= $unsigned(in_i_valid);
        end
    end

    // redist25_sync_together132_aunroll_x_in_c3_eni1_26_tpl_1(DELAY,287)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist25_sync_together132_aunroll_x_in_c3_eni1_26_tpl_1_q <= $unsigned(in_c3_eni1_26_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m95_c_compmm_m28(BLACKBOX,190)@110
    // out out_intel_reserved_ffwd_90_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m95_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m95_c_compmm_m28 (
        .in_predicate_in(GND_q),
        .in_src_data_in_90_0(redist25_sync_together132_aunroll_x_in_c3_eni1_26_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg26_q),
        .out_intel_reserved_ffwd_90_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m95_c_compmm_m28_out_intel_reserved_ffwd_90_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_53_regfree_osync_x(GPOUT,55)
    assign out_intel_reserved_ffwd_90_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m95_c_compmm_m28_out_intel_reserved_ffwd_90_0;

    // valid_fanout_reg27(REG,224)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg27_q <= $unsigned(in_i_valid);
        end
    end

    // redist26_sync_together132_aunroll_x_in_c3_eni1_27_tpl_1(DELAY,288)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist26_sync_together132_aunroll_x_in_c3_eni1_27_tpl_1_q <= $unsigned(in_c3_eni1_27_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m96_c_compmm_m29(BLACKBOX,191)@110
    // out out_intel_reserved_ffwd_91_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m96_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m96_c_compmm_m29 (
        .in_predicate_in(GND_q),
        .in_src_data_in_91_0(redist26_sync_together132_aunroll_x_in_c3_eni1_27_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg27_q),
        .out_intel_reserved_ffwd_91_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m96_c_compmm_m29_out_intel_reserved_ffwd_91_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_54_regfree_osync_x(GPOUT,56)
    assign out_intel_reserved_ffwd_91_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m96_c_compmm_m29_out_intel_reserved_ffwd_91_0;

    // valid_fanout_reg28(REG,225)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg28_q <= $unsigned(in_i_valid);
        end
    end

    // redist27_sync_together132_aunroll_x_in_c3_eni1_28_tpl_1(DELAY,289)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist27_sync_together132_aunroll_x_in_c3_eni1_28_tpl_1_q <= $unsigned(in_c3_eni1_28_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m97_c_compmm_m30(BLACKBOX,192)@110
    // out out_intel_reserved_ffwd_92_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m97_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m97_c_compmm_m30 (
        .in_predicate_in(GND_q),
        .in_src_data_in_92_0(redist27_sync_together132_aunroll_x_in_c3_eni1_28_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg28_q),
        .out_intel_reserved_ffwd_92_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m97_c_compmm_m30_out_intel_reserved_ffwd_92_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_55_regfree_osync_x(GPOUT,57)
    assign out_intel_reserved_ffwd_92_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m97_c_compmm_m30_out_intel_reserved_ffwd_92_0;

    // valid_fanout_reg29(REG,226)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg29_q <= $unsigned(in_i_valid);
        end
    end

    // redist28_sync_together132_aunroll_x_in_c3_eni1_29_tpl_1(DELAY,290)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist28_sync_together132_aunroll_x_in_c3_eni1_29_tpl_1_q <= $unsigned(in_c3_eni1_29_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m98_c_compmm_m31(BLACKBOX,193)@110
    // out out_intel_reserved_ffwd_93_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m98_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m98_c_compmm_m31 (
        .in_predicate_in(GND_q),
        .in_src_data_in_93_0(redist28_sync_together132_aunroll_x_in_c3_eni1_29_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg29_q),
        .out_intel_reserved_ffwd_93_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m98_c_compmm_m31_out_intel_reserved_ffwd_93_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_56_regfree_osync_x(GPOUT,58)
    assign out_intel_reserved_ffwd_93_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m98_c_compmm_m31_out_intel_reserved_ffwd_93_0;

    // valid_fanout_reg30(REG,227)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg30_q <= $unsigned(in_i_valid);
        end
    end

    // redist29_sync_together132_aunroll_x_in_c3_eni1_30_tpl_1(DELAY,291)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist29_sync_together132_aunroll_x_in_c3_eni1_30_tpl_1_q <= $unsigned(in_c3_eni1_30_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m99_c_compmm_m32(BLACKBOX,194)@110
    // out out_intel_reserved_ffwd_94_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000mpmm_m99_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m99_c_compmm_m32 (
        .in_predicate_in(GND_q),
        .in_src_data_in_94_0(redist29_sync_together132_aunroll_x_in_c3_eni1_30_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg30_q),
        .out_intel_reserved_ffwd_94_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m99_c_compmm_m32_out_intel_reserved_ffwd_94_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_57_regfree_osync_x(GPOUT,59)
    assign out_intel_reserved_ffwd_94_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m99_c_compmm_m32_out_intel_reserved_ffwd_94_0;

    // valid_fanout_reg31(REG,228)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg31_q <= $unsigned(in_i_valid);
        end
    end

    // redist30_sync_together132_aunroll_x_in_c3_eni1_31_tpl_1(DELAY,292)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist30_sync_together132_aunroll_x_in_c3_eni1_31_tpl_1_q <= $unsigned(in_c3_eni1_31_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m100_c_compmm_m33(BLACKBOX,131)@110
    // out out_intel_reserved_ffwd_95_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m100_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m100_c_compmm_m33 (
        .in_predicate_in(GND_q),
        .in_src_data_in_95_0(redist30_sync_together132_aunroll_x_in_c3_eni1_31_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg31_q),
        .out_intel_reserved_ffwd_95_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m100_c_compmm_m33_out_intel_reserved_ffwd_95_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_58_regfree_osync_x(GPOUT,60)
    assign out_intel_reserved_ffwd_95_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m100_c_compmm_m33_out_intel_reserved_ffwd_95_0;

    // valid_fanout_reg32(REG,229)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg32_q <= $unsigned(in_i_valid);
        end
    end

    // redist31_sync_together132_aunroll_x_in_c3_eni1_32_tpl_1(DELAY,293)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist31_sync_together132_aunroll_x_in_c3_eni1_32_tpl_1_q <= $unsigned(in_c3_eni1_32_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m101_c_compmm_m34(BLACKBOX,132)@110
    // out out_intel_reserved_ffwd_96_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m101_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m101_c_compmm_m34 (
        .in_predicate_in(GND_q),
        .in_src_data_in_96_0(redist31_sync_together132_aunroll_x_in_c3_eni1_32_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg32_q),
        .out_intel_reserved_ffwd_96_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m101_c_compmm_m34_out_intel_reserved_ffwd_96_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_59_regfree_osync_x(GPOUT,61)
    assign out_intel_reserved_ffwd_96_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m101_c_compmm_m34_out_intel_reserved_ffwd_96_0;

    // valid_fanout_reg33(REG,230)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg33_q <= $unsigned(in_i_valid);
        end
    end

    // redist32_sync_together132_aunroll_x_in_c3_eni1_33_tpl_1(DELAY,294)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist32_sync_together132_aunroll_x_in_c3_eni1_33_tpl_1_q <= $unsigned(in_c3_eni1_33_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m102_c_compmm_m35(BLACKBOX,133)@110
    // out out_intel_reserved_ffwd_97_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m102_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m102_c_compmm_m35 (
        .in_predicate_in(GND_q),
        .in_src_data_in_97_0(redist32_sync_together132_aunroll_x_in_c3_eni1_33_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg33_q),
        .out_intel_reserved_ffwd_97_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m102_c_compmm_m35_out_intel_reserved_ffwd_97_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_60_regfree_osync_x(GPOUT,62)
    assign out_intel_reserved_ffwd_97_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m102_c_compmm_m35_out_intel_reserved_ffwd_97_0;

    // valid_fanout_reg34(REG,231)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg34_q <= $unsigned(in_i_valid);
        end
    end

    // redist33_sync_together132_aunroll_x_in_c3_eni1_34_tpl_1(DELAY,295)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist33_sync_together132_aunroll_x_in_c3_eni1_34_tpl_1_q <= $unsigned(in_c3_eni1_34_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m103_c_compmm_m36(BLACKBOX,134)@110
    // out out_intel_reserved_ffwd_98_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m103_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m103_c_compmm_m36 (
        .in_predicate_in(GND_q),
        .in_src_data_in_98_0(redist33_sync_together132_aunroll_x_in_c3_eni1_34_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg34_q),
        .out_intel_reserved_ffwd_98_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m103_c_compmm_m36_out_intel_reserved_ffwd_98_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_61_regfree_osync_x(GPOUT,63)
    assign out_intel_reserved_ffwd_98_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m103_c_compmm_m36_out_intel_reserved_ffwd_98_0;

    // valid_fanout_reg35(REG,232)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg35_q <= $unsigned(in_i_valid);
        end
    end

    // redist34_sync_together132_aunroll_x_in_c3_eni1_35_tpl_1(DELAY,296)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist34_sync_together132_aunroll_x_in_c3_eni1_35_tpl_1_q <= $unsigned(in_c3_eni1_35_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m104_c_compmm_m37(BLACKBOX,135)@110
    // out out_intel_reserved_ffwd_99_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m104_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m104_c_compmm_m37 (
        .in_predicate_in(GND_q),
        .in_src_data_in_99_0(redist34_sync_together132_aunroll_x_in_c3_eni1_35_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg35_q),
        .out_intel_reserved_ffwd_99_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m104_c_compmm_m37_out_intel_reserved_ffwd_99_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_62_regfree_osync_x(GPOUT,64)
    assign out_intel_reserved_ffwd_99_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m104_c_compmm_m37_out_intel_reserved_ffwd_99_0;

    // valid_fanout_reg0(REG,197)@109 + 1
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            valid_fanout_reg0_q <= $unsigned(1'b0);
        end
        else
        begin
            valid_fanout_reg0_q <= $unsigned(in_i_valid);
        end
    end

    // sync_out_aunroll_x(GPOUT,65)@110
    assign out_o_valid = valid_fanout_reg0_q;
    assign out_unnamed_c_compMM_m134_0_tpl = GND_q;
    assign out_unnamed_c_compMM_m4 = GND_q;

    // valid_fanout_reg36(REG,233)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg36_q <= $unsigned(in_i_valid);
        end
    end

    // redist35_sync_together132_aunroll_x_in_c3_eni1_36_tpl_1(DELAY,297)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist35_sync_together132_aunroll_x_in_c3_eni1_36_tpl_1_q <= $unsigned(in_c3_eni1_36_tpl);
        end
    end

    // i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m105_c_compmm_m38(BLACKBOX,136)@110
    // out out_intel_reserved_ffwd_100_0@20000000
    c_compMM_m_i_llvm_fpga_ffwd_source_i16_u0000pmm_m105_c_compmm_m0 thei_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m105_c_compmm_m38 (
        .in_predicate_in(GND_q),
        .in_src_data_in_100_0(redist35_sync_together132_aunroll_x_in_c3_eni1_36_tpl_1_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg36_q),
        .out_intel_reserved_ffwd_100_0(i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m105_c_compmm_m38_out_intel_reserved_ffwd_100_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // regfree_osync(GPOUT,195)
    assign out_intel_reserved_ffwd_100_0 = i_llvm_fpga_ffwd_source_i16_unnamed_c_compmm_m105_c_compmm_m38_out_intel_reserved_ffwd_100_0;

endmodule
