// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// Your use of  Intel Corporation's design tools,  logic functions and other
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// files any  of the foregoing (including  device programming  or simulation
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement,  including,  without limitation,  that your use is for
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// ---------------------------------------------------------------------------

// SystemVerilog created from bb_c_compSTR_B7_stall_region
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:08 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_bb_B7_stall_region (
    input wire [4095:0] in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdata,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writeack,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdatavalid,
    output wire [31:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write,
    output wire [4095:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata,
    output wire [511:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount,
    output wire [0:0] out_almost_empty_out,
    output wire [0:0] out_c0_exe1732,
    output wire [0:0] out_c0_exe5736,
    output wire [0:0] out_empty_out,
    output wire [0:0] out_profile_loop_o_valid,
    output wire [0:0] out_valid_out,
    input wire [0:0] in_iowr_bl_resStream_i_fifoready,
    output wire [31:0] out_iowr_bl_resStream_o_fifodata,
    output wire [0:0] out_iowr_bl_resStream_o_fifovalid,
    input wire [4095:0] in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdata,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writeack,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdatavalid,
    output wire [31:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write,
    output wire [4095:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata,
    output wire [511:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable,
    output wire [0:0] out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount,
    input wire [0:0] in_flush,
    input wire [0:0] in_stall_in,
    output wire [0:0] out_stall_out,
    input wire [0:0] in_almost_empty_in,
    input wire [0:0] in_empty_in,
    input wire [0:0] in_valid_in,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [31:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_iowr_bl_resStream_o_fifodata;
    wire [0:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_iowr_bl_resStream_o_fifovalid;
    wire [0:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_almost_empty;
    wire [0:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_empty;
    wire [0:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_stall;
    wire [0:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_valid;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_1_tpl;
    wire [15:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_3_tpl;
    wire [15:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_4_tpl;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_6_tpl;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_almost_empty_out;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_empty_out;
    wire [31:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount;
    wire [511:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write;
    wire [4095:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata;
    wire [31:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount;
    wire [511:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write;
    wire [4095:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_stall;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_valid;
    wire [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_profile_loop_o_valid;
    wire [2:0] join_for_coalesced_delay_0_q;
    wire [0:0] sel_for_coalesced_delay_0_b;
    wire [0:0] sel_for_coalesced_delay_0_c;
    wire [0:0] sel_for_coalesced_delay_0_d;
    wire [0:0] coalesced_delay_0_fifo_i_valid;
    wire coalesced_delay_0_fifo_i_valid_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_i_stall;
    wire coalesced_delay_0_fifo_i_stall_bitsignaltemp;
    wire [2:0] coalesced_delay_0_fifo_i_data;
    wire [0:0] coalesced_delay_0_fifo_i_empty;
    wire coalesced_delay_0_fifo_i_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_i_almost_empty;
    wire coalesced_delay_0_fifo_i_almost_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_o_valid;
    wire coalesced_delay_0_fifo_o_valid_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_o_stall;
    wire coalesced_delay_0_fifo_o_stall_bitsignaltemp;
    wire [2:0] coalesced_delay_0_fifo_o_data;
    wire [0:0] coalesced_delay_0_fifo_o_empty;
    wire coalesced_delay_0_fifo_o_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_o_almost_empty;
    wire coalesced_delay_0_fifo_o_almost_empty_bitsignaltemp;
    wire [34:0] bubble_join_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_q;
    wire [0:0] bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_b;
    wire [15:0] bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_c;
    wire [15:0] bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_d;
    wire [0:0] bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_e;
    wire [0:0] bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_f;
    wire [2:0] bubble_join_coalesced_delay_0_fifo_q;
    wire [2:0] bubble_select_coalesced_delay_0_fifo_b;
    wire [0:0] merged_in_SE_stall_entry_backStall;
    wire [0:0] merged_in_SE_stall_entry_V0;
    wire [0:0] merged_in_SE_stall_entry_V1;
    wire [0:0] merged_in_SE_stall_entry_V2;
    wire [0:0] merged_in_SE_stall_entry_temp_back_stall;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_backStall;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V0;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V2;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V4;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V1;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V3;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V5;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_temp_back_stall;
    wire [0:0] merged_in_SE_stall_exit_backStall;
    wire [0:0] merged_in_SE_stall_exit_V0;
    wire [0:0] merged_in_SE_stall_exit_V1;
    wire [0:0] merged_in_SE_stall_exit_V2;
    wire [0:0] merged_in_SE_stall_exit_can_fast_read;
    wire can_fast_read_bitsignaltemp;
    wire [0:0] merged_in_SE_stall_exit_can_slow_read;
    wire can_slow_read_bitsignaltemp;
    wire [0:0] merged_in_SE_stall_exit_no_space_for_result;
    wire no_space_for_result_bitsignaltemp;
    wire [0:0] merged_in_SE_stall_exit_forced_read;
    wire forced_read_bitsignaltemp;
    wire [0:0] merged_in_SE_stall_exit_temp_back_stall;
    reg [0:0] merged_in_SE_stall_exit_V0_sync_valid_reg6_q;
    reg [0:0] merged_in_SE_stall_exit_V0_sync_valid_reg5_q;
    reg [0:0] merged_in_SE_stall_exit_V0_sync_valid_reg4_q;
    reg [0:0] merged_in_SE_stall_exit_V0_sync_valid_reg3_q;
    reg [0:0] merged_in_SE_stall_exit_V0_sync_valid_reg2_q;
    reg [0:0] merged_in_SE_stall_exit_V0_sync_valid_reg1_q;
    reg [0:0] merged_in_SE_stall_exit_V0_sync_valid_reg0_q;
    reg [0:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_in_i_stall_reg0_q;
    reg [0:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_in_i_stall_reg1_q;
    reg [0:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_almost_empty_reg1_q;
    reg [0:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_almost_empty_reg0_q;
    reg [0:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_empty_reg1_q;
    reg [0:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_empty_reg0_q;
    reg [0:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_valid_reg1_q;
    reg [0:0] i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_valid_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_in_i_stall_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_in_i_stall_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_1_tpl_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_1_tpl_reg0_q;
    reg [15:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_3_tpl_reg1_q;
    reg [15:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_3_tpl_reg0_q;
    reg [15:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_4_tpl_reg1_q;
    reg [15:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_4_tpl_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_6_tpl_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_6_tpl_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_almost_empty_out_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_almost_empty_out_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_empty_out_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_empty_out_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_valid_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_valid_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_profile_loop_o_valid_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_profile_loop_o_valid_reg0_q;
    reg [0:0] stall_entry_frontStall_reg0_q;
    reg [0:0] stall_entry_frontStall_reg1_q;
    reg [0:0] stall_entry_frontValid_reg1_q;
    reg [0:0] stall_entry_frontValid_reg0_q;
    reg [0:0] stall_entry_frontEmpty_reg1_q;
    reg [0:0] stall_entry_frontEmpty_reg0_q;
    reg [0:0] stall_entry_frontAlmostEmpty_reg1_q;
    reg [0:0] stall_entry_frontAlmostEmpty_reg0_q;
    reg [0:0] coalesced_delay_0_fifo_i_stall_reg0_q;
    reg [0:0] coalesced_delay_0_fifo_i_stall_reg1_q;
    reg [0:0] coalesced_delay_0_fifo_o_valid_reg1_q;
    reg [0:0] coalesced_delay_0_fifo_o_valid_reg0_q;
    reg [2:0] coalesced_delay_0_fifo_o_data_reg1_q;
    reg [2:0] coalesced_delay_0_fifo_o_data_reg0_q;
    reg [0:0] coalesced_delay_0_fifo_o_empty_reg1_q;
    reg [0:0] coalesced_delay_0_fifo_o_empty_reg0_q;
    reg [0:0] coalesced_delay_0_fifo_o_almost_empty_reg1_q;
    reg [0:0] coalesced_delay_0_fifo_o_almost_empty_reg0_q;
    reg [0:0] rst_sync_rst_sclrn;


    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_almost_empty_out_reg0(REG,91)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_almost_empty_out_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_almost_empty_out);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_almost_empty_out_reg1(REG,90)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_almost_empty_out_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_almost_empty_out_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_empty_out_reg0(REG,93)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_empty_out_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_empty_out);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_empty_out_reg1(REG,92)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_empty_out_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_empty_out_reg0_q);
        end
    end

    // coalesced_delay_0_fifo_o_almost_empty_reg0(REG,115)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_almost_empty_reg0_q <= $unsigned(coalesced_delay_0_fifo_o_almost_empty);
        end
    end

    // coalesced_delay_0_fifo_o_almost_empty_reg1(REG,114)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_almost_empty_reg1_q <= $unsigned(coalesced_delay_0_fifo_o_almost_empty_reg0_q);
        end
    end

    // i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_almost_empty_reg0(REG,75)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_almost_empty_reg0_q <= $unsigned(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_almost_empty);
        end
    end

    // i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_almost_empty_reg1(REG,74)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_almost_empty_reg1_q <= $unsigned(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_almost_empty_reg0_q);
        end
    end

    // coalesced_delay_0_fifo_o_empty_reg0(REG,113)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_empty_reg0_q <= $unsigned(coalesced_delay_0_fifo_o_empty);
        end
    end

    // coalesced_delay_0_fifo_o_empty_reg1(REG,112)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_empty_reg1_q <= $unsigned(coalesced_delay_0_fifo_o_empty_reg0_q);
        end
    end

    // i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_empty_reg0(REG,77)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_empty_reg0_q <= $unsigned(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_empty);
        end
    end

    // i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_empty_reg1(REG,76)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_empty_reg1_q <= $unsigned(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_empty_reg0_q);
        end
    end

    // coalesced_delay_0_fifo_o_valid_reg0(REG,109)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_valid_reg0_q <= $unsigned(coalesced_delay_0_fifo_o_valid);
        end
    end

    // coalesced_delay_0_fifo_o_valid_reg1(REG,108)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_valid_reg1_q <= $unsigned(coalesced_delay_0_fifo_o_valid_reg0_q);
        end
    end

    // i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_valid_reg0(REG,79)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_valid_reg0_q <= $unsigned(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_valid);
        end
    end

    // i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_valid_reg1(REG,78)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_valid_reg1_q <= $unsigned(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_valid_reg0_q);
        end
    end

    // merged_in_SE_stall_exit(STALLENABLE,64)
    // Sync
    assign merged_in_SE_stall_exit_temp_back_stall = in_stall_in;
    assign merged_in_SE_stall_exit_can_fast_read = ~ ((i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_almost_empty_reg1_q | coalesced_delay_0_fifo_o_almost_empty_reg1_q));
    assign merged_in_SE_stall_exit_can_slow_read = ~ ((i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_empty_reg1_q | coalesced_delay_0_fifo_o_empty_reg1_q));
    assign merged_in_SE_stall_exit_backStall = ~ (merged_in_SE_stall_exit_forced_read);
    assign merged_in_SE_stall_exit_no_space_for_result = merged_in_SE_stall_exit_temp_back_stall;
    assign merged_in_SE_stall_exit_V0 = merged_in_SE_stall_exit_forced_read;
    assign merged_in_SE_stall_exit_V1 = $unsigned(1'b0);
    assign merged_in_SE_stall_exit_V2 = $unsigned(1'b0);
    assign can_fast_read_bitsignaltemp = merged_in_SE_stall_exit_can_fast_read[0];
    assign can_slow_read_bitsignaltemp = merged_in_SE_stall_exit_can_slow_read[0];
    assign no_space_for_result_bitsignaltemp = merged_in_SE_stall_exit_no_space_for_result[0];
    assign merged_in_SE_stall_exit_forced_read[0] = forced_read_bitsignaltemp;
    acl_sync_stall_latency #(
        .EMPTY_PLUS_STALL_LATENCY(7),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(1),
        .RESET_EVERYTHING(0)
    ) themerged_in_SE_stall_exit (
        .can_fast_read(can_fast_read_bitsignaltemp),
        .can_slow_read(can_slow_read_bitsignaltemp),
        .no_space_for_result(no_space_for_result_bitsignaltemp),
        .forced_read(forced_read_bitsignaltemp),
        .clock(clock),
        .resetn(resetn)
    );

    // i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_in_i_stall_reg0(REG,72)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_in_i_stall_reg0_q <= $unsigned(merged_in_SE_stall_exit_backStall);
        end
    end

    // i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_in_i_stall_reg1(REG,73)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_in_i_stall_reg1_q <= $unsigned(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_in_i_stall_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_profile_loop_o_valid_reg0(REG,97)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_profile_loop_o_valid_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_profile_loop_o_valid);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_profile_loop_o_valid_reg1(REG,96)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_profile_loop_o_valid_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_profile_loop_o_valid_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_6_tpl_reg0(REG,89)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_6_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_6_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_6_tpl_reg1(REG,88)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_6_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_6_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_4_tpl_reg0(REG,87)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_4_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_4_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_4_tpl_reg1(REG,86)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_4_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_4_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_3_tpl_reg0(REG,85)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_3_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_3_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_3_tpl_reg1(REG,84)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_3_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_3_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_1_tpl_reg0(REG,83)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_1_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_1_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_1_tpl_reg1(REG,82)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_1_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_1_tpl_reg0_q);
        end
    end

    // bubble_join_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x(BITJOIN,34)
    assign bubble_join_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_q = {i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_profile_loop_o_valid_reg1_q, i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_6_tpl_reg1_q, i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_4_tpl_reg1_q, i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_3_tpl_reg1_q, i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_1_tpl_reg1_q};

    // bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x(BITSELECT,35)
    assign bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_b = $unsigned(bubble_join_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_q[0:0]);
    assign bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_c = $unsigned(bubble_join_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_q[16:1]);
    assign bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_d = $unsigned(bubble_join_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_q[32:17]);
    assign bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_e = $unsigned(bubble_join_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_q[33:33]);
    assign bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_f = $unsigned(bubble_join_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_q[34:34]);

    // i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x(BLACKBOX,7)@299
    // in in_i_stall@20000000
    // out out_iowr_bl_resStream_o_fifodata@20000000
    // out out_iowr_bl_resStream_o_fifovalid@20000000
    // out out_o_ack@323
    // out out_o_almost_empty@323
    // out out_o_empty@323
    // out out_o_stall@20000000
    // out out_o_valid@323
    c_compSTR_i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr0 thei_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x (
        .in_i_data_0_tpl(bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_c),
        .in_i_data_1_tpl(bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_d),
        .in_almost_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V5),
        .in_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V3),
        .in_i_stall(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_in_i_stall_reg1_q),
        .in_i_valid(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V1),
        .in_iowr_bl_resStream_i_fifoready(in_iowr_bl_resStream_i_fifoready),
        .out_iowr_bl_resStream_o_fifodata(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_iowr_bl_resStream_o_fifodata),
        .out_iowr_bl_resStream_o_fifovalid(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_iowr_bl_resStream_o_fifovalid),
        .out_o_ack(),
        .out_o_almost_empty(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_almost_empty),
        .out_o_empty(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_empty),
        .out_o_stall(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_stall),
        .out_o_valid(i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // join_for_coalesced_delay_0(BITJOIN,29)
    assign join_for_coalesced_delay_0_q = {bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_f, bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_e, bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_b};

    // coalesced_delay_0_fifo_i_stall_reg0(REG,106)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_i_stall_reg0_q <= $unsigned(merged_in_SE_stall_exit_backStall);
        end
    end

    // coalesced_delay_0_fifo_i_stall_reg1(REG,107)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_i_stall_reg1_q <= $unsigned(coalesced_delay_0_fifo_i_stall_reg0_q);
        end
    end

    // coalesced_delay_0_fifo(STALLFIFO,31)
    assign coalesced_delay_0_fifo_i_valid = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V0;
    assign coalesced_delay_0_fifo_i_stall = coalesced_delay_0_fifo_i_stall_reg1_q;
    assign coalesced_delay_0_fifo_i_data = join_for_coalesced_delay_0_q;
    assign coalesced_delay_0_fifo_i_empty = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V2;
    assign coalesced_delay_0_fifo_i_almost_empty = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V4;
    assign coalesced_delay_0_fifo_i_valid_bitsignaltemp = coalesced_delay_0_fifo_i_valid[0];
    assign coalesced_delay_0_fifo_i_stall_bitsignaltemp = coalesced_delay_0_fifo_i_stall[0];
    assign coalesced_delay_0_fifo_o_valid[0] = coalesced_delay_0_fifo_o_valid_bitsignaltemp;
    assign coalesced_delay_0_fifo_o_stall[0] = coalesced_delay_0_fifo_o_stall_bitsignaltemp;
    assign coalesced_delay_0_fifo_o_empty[0] = coalesced_delay_0_fifo_o_empty_bitsignaltemp;
    assign coalesced_delay_0_fifo_o_almost_empty[0] = coalesced_delay_0_fifo_o_almost_empty_bitsignaltemp;
    hld_fifo #(
        .DEPTH(42),
        .WIDTH(3),
        .STYLE("ms"),
        .ALMOST_FULL_CUTOFF(7),
        .ALMOST_EMPTY_CUTOFF(7),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(0),
        .USE_STALL_LATENCY_UPSTREAM(1),
        .USE_STALL_LATENCY_DOWNSTREAM(1),
        .NEVER_OVERFLOWS(1),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(1)
    ) thecoalesced_delay_0_fifo (
        .i_valid(coalesced_delay_0_fifo_i_valid_bitsignaltemp),
        .i_stall(coalesced_delay_0_fifo_i_stall_bitsignaltemp),
        .i_data(join_for_coalesced_delay_0_q),
        .o_valid(coalesced_delay_0_fifo_o_valid_bitsignaltemp),
        .o_stall(coalesced_delay_0_fifo_o_stall_bitsignaltemp),
        .o_data(coalesced_delay_0_fifo_o_data),
        .o_empty(coalesced_delay_0_fifo_o_empty_bitsignaltemp),
        .o_almost_empty(coalesced_delay_0_fifo_o_almost_empty_bitsignaltemp),
        .clock(clock),
        .resetn(resetn)
    );

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_valid_reg0(REG,95)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_valid_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_valid);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_valid_reg1(REG,94)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_valid_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_valid_reg0_q);
        end
    end

    // merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x(STALLENABLE,63)
    // Desync
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_temp_back_stall = coalesced_delay_0_fifo_o_stall | i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_o_stall;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_backStall = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_temp_back_stall;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V0 = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_valid_reg1_q;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V2 = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_empty_out_reg1_q;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V4 = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_almost_empty_out_reg1_q;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V1 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V0;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V3 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V2;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V5 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_V4;

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_in_i_stall_reg0(REG,80)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_in_i_stall_reg0_q <= $unsigned(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_backStall);
        end
    end

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_in_i_stall_reg1(REG,81)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_in_i_stall_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_in_i_stall_reg0_q);
        end
    end

    // stall_entry_frontAlmostEmpty_reg0(REG,105)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontAlmostEmpty_reg0_q <= $unsigned(in_almost_empty_in);
        end
    end

    // stall_entry_frontAlmostEmpty_reg1(REG,104)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontAlmostEmpty_reg1_q <= $unsigned(stall_entry_frontAlmostEmpty_reg0_q);
        end
    end

    // stall_entry_frontEmpty_reg0(REG,103)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontEmpty_reg0_q <= $unsigned(in_empty_in);
        end
    end

    // stall_entry_frontEmpty_reg1(REG,102)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontEmpty_reg1_q <= $unsigned(stall_entry_frontEmpty_reg0_q);
        end
    end

    // stall_entry_frontValid_reg0(REG,101)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontValid_reg0_q <= $unsigned(in_valid_in);
        end
    end

    // stall_entry_frontValid_reg1(REG,100)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontValid_reg1_q <= $unsigned(stall_entry_frontValid_reg0_q);
        end
    end

    // merged_in_SE_stall_entry(STALLENABLE,62)
    assign merged_in_SE_stall_entry_backStall = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_stall;
    assign merged_in_SE_stall_entry_V0 = stall_entry_frontValid_reg1_q;
    assign merged_in_SE_stall_entry_V1 = stall_entry_frontEmpty_reg1_q;
    assign merged_in_SE_stall_entry_V2 = stall_entry_frontAlmostEmpty_reg1_q;

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x(BLACKBOX,8)@0
    // in in_i_stall@20000000
    // out out_c0_exit731_0_tpl@299
    // out out_c0_exit731_1_tpl@299
    // out out_c0_exit731_2_tpl@299
    // out out_c0_exit731_3_tpl@299
    // out out_c0_exit731_4_tpl@299
    // out out_c0_exit731_5_tpl@299
    // out out_c0_exit731_6_tpl@299
    // out out_almost_empty_out@299
    // out out_empty_out@299
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write@20000000
    // out out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata@20000000
    // out out_o_stall@20000000
    // out out_o_valid@299
    // out out_profile_loop_o_valid@299
    c_compSTR_i_sfc_s_c0_in_for_body34_c_com0000enter7245_c_compstr1 thei_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x (
        .in_c0_eni1723_0_tpl(GND_q),
        .in_c0_eni1723_1_tpl(GND_q),
        .in_almost_empty_in(merged_in_SE_stall_entry_V2),
        .in_empty_in(merged_in_SE_stall_entry_V1),
        .in_flush(in_flush),
        .in_i_stall(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_in_i_stall_reg1_q),
        .in_i_valid(merged_in_SE_stall_entry_V0),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdata(in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdata),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdatavalid(in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_readdatavalid),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_waitrequest(in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_waitrequest),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writeack(in_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writeack),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdata(in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdata),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdatavalid(in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_readdatavalid),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_waitrequest(in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_waitrequest),
        .in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writeack(in_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writeack),
        .out_c0_exit731_0_tpl(),
        .out_c0_exit731_1_tpl(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_1_tpl),
        .out_c0_exit731_2_tpl(),
        .out_c0_exit731_3_tpl(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_3_tpl),
        .out_c0_exit731_4_tpl(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_4_tpl),
        .out_c0_exit731_5_tpl(),
        .out_c0_exit731_6_tpl(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_c0_exit731_6_tpl),
        .out_almost_empty_out(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_almost_empty_out),
        .out_empty_out(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_empty_out),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write),
        .out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata),
        .out_o_stall(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_stall),
        .out_o_valid(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_o_valid),
        .out_profile_loop_o_valid(i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_profile_loop_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_ext_sig_sync_out_x(GPOUT,3)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_address;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_enable;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_read;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_write;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_writedata;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_byteenable;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5138_c_compSTR_avm_burstcount;

    // merged_in_SE_stall_exit_V0_sync_valid_reg0(REG,71)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_stall_exit_V0_sync_valid_reg0_q <= $unsigned(merged_in_SE_stall_exit_V0);
        end
    end

    // merged_in_SE_stall_exit_V0_sync_valid_reg1(REG,70)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_stall_exit_V0_sync_valid_reg1_q <= $unsigned(merged_in_SE_stall_exit_V0_sync_valid_reg0_q);
        end
    end

    // merged_in_SE_stall_exit_V0_sync_valid_reg2(REG,69)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_stall_exit_V0_sync_valid_reg2_q <= $unsigned(merged_in_SE_stall_exit_V0_sync_valid_reg1_q);
        end
    end

    // merged_in_SE_stall_exit_V0_sync_valid_reg3(REG,68)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_stall_exit_V0_sync_valid_reg3_q <= $unsigned(merged_in_SE_stall_exit_V0_sync_valid_reg2_q);
        end
    end

    // merged_in_SE_stall_exit_V0_sync_valid_reg4(REG,67)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_stall_exit_V0_sync_valid_reg4_q <= $unsigned(merged_in_SE_stall_exit_V0_sync_valid_reg3_q);
        end
    end

    // merged_in_SE_stall_exit_V0_sync_valid_reg5(REG,66)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_stall_exit_V0_sync_valid_reg5_q <= $unsigned(merged_in_SE_stall_exit_V0_sync_valid_reg4_q);
        end
    end

    // merged_in_SE_stall_exit_V0_sync_valid_reg6(REG,65)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_stall_exit_V0_sync_valid_reg6_q <= $unsigned(merged_in_SE_stall_exit_V0_sync_valid_reg5_q);
        end
    end

    // coalesced_delay_0_fifo_o_data_reg0(REG,111)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_data_reg0_q <= $unsigned(coalesced_delay_0_fifo_o_data);
        end
    end

    // coalesced_delay_0_fifo_o_data_reg1(REG,110)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_data_reg1_q <= $unsigned(coalesced_delay_0_fifo_o_data_reg0_q);
        end
    end

    // bubble_join_coalesced_delay_0_fifo(BITJOIN,38)
    assign bubble_join_coalesced_delay_0_fifo_q = coalesced_delay_0_fifo_o_data_reg1_q;

    // bubble_select_coalesced_delay_0_fifo(BITSELECT,39)
    assign bubble_select_coalesced_delay_0_fifo_b = $unsigned(bubble_join_coalesced_delay_0_fifo_q[2:0]);

    // sel_for_coalesced_delay_0(BITSELECT,30)
    assign sel_for_coalesced_delay_0_b = $unsigned(bubble_select_coalesced_delay_0_fifo_b[0:0]);
    assign sel_for_coalesced_delay_0_c = $unsigned(bubble_select_coalesced_delay_0_fifo_b[1:1]);
    assign sel_for_coalesced_delay_0_d = $unsigned(bubble_select_coalesced_delay_0_fifo_b[2:2]);

    // dupName_0_sync_out_x(GPOUT,4)@323
    assign out_almost_empty_out = merged_in_SE_stall_exit_V2;
    assign out_c0_exe1732 = sel_for_coalesced_delay_0_b;
    assign out_c0_exe5736 = sel_for_coalesced_delay_0_c;
    assign out_empty_out = merged_in_SE_stall_exit_V1;
    assign out_profile_loop_o_valid = sel_for_coalesced_delay_0_d;
    assign out_valid_out = merged_in_SE_stall_exit_V0_sync_valid_reg6_q;

    // dupName_1_ext_sig_sync_out_x(GPOUT,6)
    assign out_iowr_bl_resStream_o_fifodata = i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_iowr_bl_resStream_o_fifodata;
    assign out_iowr_bl_resStream_o_fifovalid = i_iowr_bl_resstream_unnamed_c_compstr6_c_compstr3_aunroll_x_out_iowr_bl_resStream_o_fifovalid;

    // ext_sig_sync_out(GPOUT,14)
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_address;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_enable;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_read;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_write;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_writedata;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_byteenable;
    assign out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount = i_sfc_s_c0_in_for_body34_c_compstrs_c0_enter7245_c_compstr1_aunroll_x_out_memcoalesce_load_c_compSTR_fpgaunique_5126_c_compSTR_avm_burstcount;

    // stall_entry_frontStall_reg0(REG,98)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontStall_reg0_q <= $unsigned(merged_in_SE_stall_entry_backStall);
        end
    end

    // stall_entry_frontStall_reg1(REG,99)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontStall_reg1_q <= $unsigned(stall_entry_frontStall_reg0_q);
        end
    end

    // sync_out(GPOUT,23)@0
    assign out_stall_out = stall_entry_frontStall_reg1_q;

    // rst_sync(RESETSYNC,116)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
