// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
// Legal Notice: Copyright 2022 Intel Corporation.  All rights reserved.
// Your use of  Intel Corporation's design tools,  logic functions and other
// software and  tools, and its AMPP partner logic functions, and any output
// files any  of the foregoing (including  device programming  or simulation
// files), and  any associated  documentation  or information  are expressly
// subject  to the terms and  conditions of the  Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement,  including,  without limitation,  that your use is for
// the  sole  purpose of  programming  logic devices  manufactured by  Intel
// and  sold by Intel  or its authorized  distributors. Please refer  to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------

// SystemVerilog created from bb_c_compSTR_B5_stall_region
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_bb_B5_stall_region (
    input wire [31:0] in_iord_bl_yStream_i_fifodata,
    input wire [0:0] in_iord_bl_yStream_i_fifovalid,
    output wire [0:0] out_iord_bl_yStream_o_fifoready,
    output wire [0:0] out_iord_bl_yStream_o_fifoalmost_full,
    output wire [0:0] out_almost_empty_out,
    output wire [0:0] out_c0_exe5719,
    output wire [0:0] out_c0_exe6720,
    output wire [0:0] out_empty_out,
    output wire [0:0] out_profile_loop_o_valid,
    output wire [0:0] out_valid_out,
    input wire [4095:0] in_memdep_5_c_compSTR_avm_readdata,
    input wire [0:0] in_memdep_5_c_compSTR_avm_writeack,
    input wire [0:0] in_memdep_5_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memdep_5_c_compSTR_avm_readdatavalid,
    output wire [31:0] out_memdep_5_c_compSTR_avm_address,
    output wire [0:0] out_memdep_5_c_compSTR_avm_enable,
    output wire [0:0] out_memdep_5_c_compSTR_avm_read,
    output wire [0:0] out_memdep_5_c_compSTR_avm_write,
    output wire [4095:0] out_memdep_5_c_compSTR_avm_writedata,
    output wire [511:0] out_memdep_5_c_compSTR_avm_byteenable,
    output wire [0:0] out_memdep_5_c_compSTR_avm_burstcount,
    input wire [4095:0] in_memdep_17_c_compSTR_avm_readdata,
    input wire [0:0] in_memdep_17_c_compSTR_avm_writeack,
    input wire [0:0] in_memdep_17_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memdep_17_c_compSTR_avm_readdatavalid,
    output wire [31:0] out_memdep_17_c_compSTR_avm_address,
    output wire [0:0] out_memdep_17_c_compSTR_avm_enable,
    output wire [0:0] out_memdep_17_c_compSTR_avm_read,
    output wire [0:0] out_memdep_17_c_compSTR_avm_write,
    output wire [4095:0] out_memdep_17_c_compSTR_avm_writedata,
    output wire [511:0] out_memdep_17_c_compSTR_avm_byteenable,
    output wire [0:0] out_memdep_17_c_compSTR_avm_burstcount,
    input wire [31:0] in_iord_bl_WStream_i_fifodata,
    input wire [0:0] in_iord_bl_WStream_i_fifovalid,
    output wire [0:0] out_iord_bl_WStream_o_fifoready,
    output wire [0:0] out_iord_bl_WStream_o_fifoalmost_full,
    input wire [0:0] in_flush,
    input wire [0:0] in_stall_in,
    output wire [0:0] out_stall_out,
    input wire [0:0] in_almost_empty_in,
    input wire [0:0] in_cmp21684,
    input wire [0:0] in_empty_in,
    input wire [31:0] in_i_0288_pop12683,
    input wire [0:0] in_memdep_phi9_pop1032_pop14687,
    input wire [0:0] in_memdep_phi9_pop10682,
    input wire [0:0] in_memdep_phi_pop930_pop13686,
    input wire [0:0] in_memdep_phi_pop9679,
    input wire [0:0] in_notcmp21685,
    input wire [0:0] in_valid_in,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [15:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_0_tpl;
    wire [15:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_1_tpl;
    wire [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_iord_bl_WStream_o_fifoalmost_full;
    wire [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_iord_bl_WStream_o_fifoready;
    wire [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_almost_empty;
    wire [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_empty;
    wire [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_stall;
    wire [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_valid;
    wire [15:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_0_tpl;
    wire [15:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_1_tpl;
    wire [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_iord_bl_yStream_o_fifoalmost_full;
    wire [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_iord_bl_yStream_o_fifoready;
    wire [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_almost_empty;
    wire [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_empty;
    wire [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_stall;
    wire [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_valid;
    wire [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_1_tpl;
    wire [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_2_tpl;
    wire [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_3_tpl;
    wire [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_4_tpl;
    wire [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_5_tpl;
    wire [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_6_tpl;
    wire [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_7_tpl;
    wire [31:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_10_tpl;
    wire [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_almost_empty_out;
    wire [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_empty_out;
    wire [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_stall;
    wire [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_valid;
    wire [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_profile_loop_o_valid;
    wire [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_almost_empty_out;
    wire [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_empty_out;
    wire [31:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_address;
    wire [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_burstcount;
    wire [511:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_byteenable;
    wire [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_enable;
    wire [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_read;
    wire [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_write;
    wire [4095:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_writedata;
    wire [31:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_address;
    wire [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_burstcount;
    wire [511:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_byteenable;
    wire [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_enable;
    wire [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_read;
    wire [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_write;
    wire [4095:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_writedata;
    wire [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_o_stall;
    wire [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_o_valid;
    wire [36:0] join_for_coalesced_delay_0_q;
    wire [31:0] sel_for_coalesced_delay_0_b;
    wire [0:0] sel_for_coalesced_delay_0_c;
    wire [0:0] sel_for_coalesced_delay_0_d;
    wire [0:0] sel_for_coalesced_delay_0_e;
    wire [0:0] sel_for_coalesced_delay_0_f;
    wire [0:0] sel_for_coalesced_delay_0_g;
    wire [2:0] join_for_coalesced_delay_1_q;
    wire [0:0] sel_for_coalesced_delay_1_b;
    wire [0:0] sel_for_coalesced_delay_1_c;
    wire [0:0] sel_for_coalesced_delay_1_d;
    wire [0:0] coalesced_delay_0_fifo_i_valid;
    wire coalesced_delay_0_fifo_i_valid_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_i_stall;
    wire coalesced_delay_0_fifo_i_stall_bitsignaltemp;
    wire [36:0] coalesced_delay_0_fifo_i_data;
    wire [0:0] coalesced_delay_0_fifo_i_empty;
    wire coalesced_delay_0_fifo_i_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_i_almost_empty;
    wire coalesced_delay_0_fifo_i_almost_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_o_valid;
    wire coalesced_delay_0_fifo_o_valid_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_o_stall;
    wire coalesced_delay_0_fifo_o_stall_bitsignaltemp;
    wire [36:0] coalesced_delay_0_fifo_o_data;
    wire [0:0] coalesced_delay_0_fifo_o_empty;
    wire coalesced_delay_0_fifo_o_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_0_fifo_o_almost_empty;
    wire coalesced_delay_0_fifo_o_almost_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_1_fifo_i_valid;
    wire coalesced_delay_1_fifo_i_valid_bitsignaltemp;
    wire [0:0] coalesced_delay_1_fifo_i_stall;
    wire coalesced_delay_1_fifo_i_stall_bitsignaltemp;
    wire [2:0] coalesced_delay_1_fifo_i_data;
    wire [0:0] coalesced_delay_1_fifo_i_empty;
    wire coalesced_delay_1_fifo_i_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_1_fifo_i_almost_empty;
    wire coalesced_delay_1_fifo_i_almost_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_1_fifo_o_valid;
    wire coalesced_delay_1_fifo_o_valid_bitsignaltemp;
    wire [0:0] coalesced_delay_1_fifo_o_stall;
    wire coalesced_delay_1_fifo_o_stall_bitsignaltemp;
    wire [2:0] coalesced_delay_1_fifo_o_data;
    wire [0:0] coalesced_delay_1_fifo_o_empty;
    wire coalesced_delay_1_fifo_o_empty_bitsignaltemp;
    wire [0:0] coalesced_delay_1_fifo_o_almost_empty;
    wire coalesced_delay_1_fifo_o_almost_empty_bitsignaltemp;
    wire [31:0] bubble_join_i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_q;
    wire [15:0] bubble_select_i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_b;
    wire [15:0] bubble_select_i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_c;
    wire [31:0] bubble_join_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_q;
    wire [15:0] bubble_select_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_b;
    wire [15:0] bubble_select_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_c;
    wire [39:0] bubble_join_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_q;
    wire [0:0] bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_b;
    wire [0:0] bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_c;
    wire [0:0] bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_d;
    wire [0:0] bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_e;
    wire [0:0] bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_f;
    wire [0:0] bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_g;
    wire [0:0] bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_h;
    wire [31:0] bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_i;
    wire [0:0] bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_j;
    wire [37:0] bubble_join_stall_entry_q;
    wire [0:0] bubble_select_stall_entry_b;
    wire [31:0] bubble_select_stall_entry_c;
    wire [0:0] bubble_select_stall_entry_d;
    wire [0:0] bubble_select_stall_entry_e;
    wire [0:0] bubble_select_stall_entry_f;
    wire [0:0] bubble_select_stall_entry_g;
    wire [0:0] bubble_select_stall_entry_h;
    wire [36:0] bubble_join_coalesced_delay_0_fifo_q;
    wire [36:0] bubble_select_coalesced_delay_0_fifo_b;
    wire [2:0] bubble_join_coalesced_delay_1_fifo_q;
    wire [2:0] bubble_select_coalesced_delay_1_fifo_b;
    wire [0:0] merged_in_SE_bubble_join_stall_entry_backStall;
    wire [0:0] merged_in_SE_bubble_join_stall_entry_V0;
    wire [0:0] merged_in_SE_bubble_join_stall_entry_V1;
    wire [0:0] merged_in_SE_bubble_join_stall_entry_V2;
    wire [0:0] merged_in_SE_bubble_join_stall_entry_temp_back_stall;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_backStall;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V0;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V4;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V8;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V1;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V5;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V9;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V2;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V6;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V10;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V3;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V7;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V11;
    wire [0:0] merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_temp_back_stall;
    wire [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_backStall;
    wire [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0;
    wire [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V1;
    wire [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V2;
    wire [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_can_fast_read;
    wire can_fast_read_bitsignaltemp;
    wire [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_can_slow_read;
    wire can_slow_read_bitsignaltemp;
    wire [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_no_space_for_result;
    wire no_space_for_result_bitsignaltemp;
    wire [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_forced_read;
    wire forced_read_bitsignaltemp;
    wire [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_temp_back_stall;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_1_backStall;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_1_V0;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_1_V1;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_1_V2;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_1_can_fast_read;
    wire can_fast_read_bitsignaltemp_dup_name_0;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_1_can_slow_read;
    wire can_slow_read_bitsignaltemp_dup_name_0;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_1_no_space_for_result;
    wire no_space_for_result_bitsignaltemp_dup_name_0;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_1_forced_read;
    wire forced_read_bitsignaltemp_dup_name_0;
    wire [0:0] merged_in_SE_sel_for_coalesced_delay_1_temp_back_stall;
    reg [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg6_q;
    reg [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg5_q;
    reg [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg4_q;
    reg [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg3_q;
    reg [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg2_q;
    reg [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg1_q;
    reg [0:0] merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg0_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg6_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg5_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg4_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg3_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg2_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg1_q;
    reg [0:0] merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg0_q;
    reg [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_in_i_stall_reg0_q;
    reg [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_in_i_stall_reg1_q;
    reg [15:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_0_tpl_reg1_q;
    reg [15:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_0_tpl_reg0_q;
    reg [15:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_1_tpl_reg1_q;
    reg [15:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_1_tpl_reg0_q;
    reg [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_almost_empty_reg1_q;
    reg [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_almost_empty_reg0_q;
    reg [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_empty_reg1_q;
    reg [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_empty_reg0_q;
    reg [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_valid_reg1_q;
    reg [0:0] i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_valid_reg0_q;
    reg [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_in_i_stall_reg0_q;
    reg [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_in_i_stall_reg1_q;
    reg [15:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_0_tpl_reg1_q;
    reg [15:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_0_tpl_reg0_q;
    reg [15:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_1_tpl_reg1_q;
    reg [15:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_1_tpl_reg0_q;
    reg [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_almost_empty_reg1_q;
    reg [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_almost_empty_reg0_q;
    reg [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_empty_reg1_q;
    reg [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_empty_reg0_q;
    reg [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_valid_reg1_q;
    reg [0:0] i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_valid_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_in_i_stall_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_in_i_stall_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_1_tpl_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_1_tpl_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_2_tpl_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_2_tpl_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_3_tpl_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_3_tpl_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_4_tpl_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_4_tpl_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_5_tpl_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_5_tpl_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_6_tpl_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_6_tpl_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_7_tpl_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_7_tpl_reg0_q;
    reg [31:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_10_tpl_reg1_q;
    reg [31:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_10_tpl_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_almost_empty_out_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_almost_empty_out_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_empty_out_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_empty_out_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_valid_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_valid_reg0_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_profile_loop_o_valid_reg1_q;
    reg [0:0] i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_profile_loop_o_valid_reg0_q;
    reg [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_in_i_stall_reg0_q;
    reg [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_in_i_stall_reg1_q;
    reg [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_almost_empty_out_reg1_q;
    reg [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_almost_empty_out_reg0_q;
    reg [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_empty_out_reg1_q;
    reg [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_empty_out_reg0_q;
    reg [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_o_valid_reg1_q;
    reg [0:0] i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_o_valid_reg0_q;
    reg [0:0] stall_entry_frontStall_reg0_q;
    reg [0:0] stall_entry_frontStall_reg1_q;
    reg [0:0] stall_entry_frontValid_reg1_q;
    reg [0:0] stall_entry_frontValid_reg0_q;
    reg [0:0] stall_entry_frontEmpty_reg1_q;
    reg [0:0] stall_entry_frontEmpty_reg0_q;
    reg [0:0] stall_entry_frontAlmostEmpty_reg1_q;
    reg [0:0] stall_entry_frontAlmostEmpty_reg0_q;
    reg [0:0] stall_entry_o4_reg1_q;
    reg [0:0] stall_entry_o4_reg0_q;
    reg [31:0] stall_entry_o5_reg1_q;
    reg [31:0] stall_entry_o5_reg0_q;
    reg [0:0] stall_entry_o6_reg1_q;
    reg [0:0] stall_entry_o6_reg0_q;
    reg [0:0] stall_entry_o7_reg1_q;
    reg [0:0] stall_entry_o7_reg0_q;
    reg [0:0] stall_entry_o8_reg1_q;
    reg [0:0] stall_entry_o8_reg0_q;
    reg [0:0] stall_entry_o9_reg1_q;
    reg [0:0] stall_entry_o9_reg0_q;
    reg [0:0] stall_entry_o10_reg1_q;
    reg [0:0] stall_entry_o10_reg0_q;
    reg [0:0] coalesced_delay_0_fifo_i_stall_reg0_q;
    reg [0:0] coalesced_delay_0_fifo_i_stall_reg1_q;
    reg [0:0] coalesced_delay_0_fifo_o_valid_reg1_q;
    reg [0:0] coalesced_delay_0_fifo_o_valid_reg0_q;
    reg [36:0] coalesced_delay_0_fifo_o_data_reg1_q;
    reg [36:0] coalesced_delay_0_fifo_o_data_reg0_q;
    reg [0:0] coalesced_delay_0_fifo_o_empty_reg1_q;
    reg [0:0] coalesced_delay_0_fifo_o_empty_reg0_q;
    reg [0:0] coalesced_delay_0_fifo_o_almost_empty_reg1_q;
    reg [0:0] coalesced_delay_0_fifo_o_almost_empty_reg0_q;
    reg [0:0] coalesced_delay_1_fifo_i_stall_reg0_q;
    reg [0:0] coalesced_delay_1_fifo_i_stall_reg1_q;
    reg [0:0] coalesced_delay_1_fifo_o_valid_reg1_q;
    reg [0:0] coalesced_delay_1_fifo_o_valid_reg0_q;
    reg [2:0] coalesced_delay_1_fifo_o_data_reg1_q;
    reg [2:0] coalesced_delay_1_fifo_o_data_reg0_q;
    reg [0:0] coalesced_delay_1_fifo_o_empty_reg1_q;
    reg [0:0] coalesced_delay_1_fifo_o_empty_reg0_q;
    reg [0:0] coalesced_delay_1_fifo_o_almost_empty_reg1_q;
    reg [0:0] coalesced_delay_1_fifo_o_almost_empty_reg0_q;
    reg [0:0] rst_sync_rst_sclrn;


    // join_for_coalesced_delay_0(BITJOIN,43)
    assign join_for_coalesced_delay_0_q = {bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_h, bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_e, bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_d, bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_c, bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_b, bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_i};

    // coalesced_delay_0_fifo_i_stall_reg0(REG,217)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_i_stall_reg0_q <= $unsigned(merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_backStall);
        end
    end

    // coalesced_delay_0_fifo_i_stall_reg1(REG,218)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_i_stall_reg1_q <= $unsigned(coalesced_delay_0_fifo_i_stall_reg0_q);
        end
    end

    // coalesced_delay_0_fifo(STALLFIFO,48)
    assign coalesced_delay_0_fifo_i_valid = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V2;
    assign coalesced_delay_0_fifo_i_stall = coalesced_delay_0_fifo_i_stall_reg1_q;
    assign coalesced_delay_0_fifo_i_data = join_for_coalesced_delay_0_q;
    assign coalesced_delay_0_fifo_i_empty = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V6;
    assign coalesced_delay_0_fifo_i_almost_empty = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V10;
    assign coalesced_delay_0_fifo_i_valid_bitsignaltemp = coalesced_delay_0_fifo_i_valid[0];
    assign coalesced_delay_0_fifo_i_stall_bitsignaltemp = coalesced_delay_0_fifo_i_stall[0];
    assign coalesced_delay_0_fifo_o_valid[0] = coalesced_delay_0_fifo_o_valid_bitsignaltemp;
    assign coalesced_delay_0_fifo_o_stall[0] = coalesced_delay_0_fifo_o_stall_bitsignaltemp;
    assign coalesced_delay_0_fifo_o_empty[0] = coalesced_delay_0_fifo_o_empty_bitsignaltemp;
    assign coalesced_delay_0_fifo_o_almost_empty[0] = coalesced_delay_0_fifo_o_almost_empty_bitsignaltemp;
    hld_fifo #(
        .DEPTH(42),
        .WIDTH(37),
        .STYLE("ms"),
        .ALMOST_FULL_CUTOFF(7),
        .ALMOST_EMPTY_CUTOFF(7),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(0),
        .USE_STALL_LATENCY_UPSTREAM(1),
        .USE_STALL_LATENCY_DOWNSTREAM(1),
        .NEVER_OVERFLOWS(1),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(1)
    ) thecoalesced_delay_0_fifo (
        .i_valid(coalesced_delay_0_fifo_i_valid_bitsignaltemp),
        .i_stall(coalesced_delay_0_fifo_i_stall_bitsignaltemp),
        .i_data(join_for_coalesced_delay_0_q),
        .o_valid(coalesced_delay_0_fifo_o_valid_bitsignaltemp),
        .o_stall(coalesced_delay_0_fifo_o_stall_bitsignaltemp),
        .o_data(coalesced_delay_0_fifo_o_data),
        .o_empty(coalesced_delay_0_fifo_o_empty_bitsignaltemp),
        .o_almost_empty(coalesced_delay_0_fifo_o_almost_empty_bitsignaltemp),
        .clock(clock),
        .resetn(resetn)
    );

    // coalesced_delay_0_fifo_o_almost_empty_reg0(REG,226)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_almost_empty_reg0_q <= $unsigned(coalesced_delay_0_fifo_o_almost_empty);
        end
    end

    // coalesced_delay_0_fifo_o_almost_empty_reg1(REG,225)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_almost_empty_reg1_q <= $unsigned(coalesced_delay_0_fifo_o_almost_empty_reg0_q);
        end
    end

    // i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_in_i_stall_reg0(REG,137)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_in_i_stall_reg0_q <= $unsigned(merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_backStall);
        end
    end

    // i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_in_i_stall_reg1(REG,138)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_in_i_stall_reg1_q <= $unsigned(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_in_i_stall_reg0_q);
        end
    end

    // i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x(BLACKBOX,9)@35
    // in in_i_stall@20000000
    // out out_o_data_0_tpl@59
    // out out_o_data_1_tpl@59
    // out out_iord_bl_WStream_o_fifoalmost_full@20000000
    // out out_iord_bl_WStream_o_fifoready@20000000
    // out out_o_almost_empty@59
    // out out_o_empty@59
    // out out_o_stall@20000000
    // out out_o_valid@59
    c_compSTR_i_iord_bl_wstream_unnamed_c_compstr1_c_compstr0 thei_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x (
        .in_almost_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V8),
        .in_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V4),
        .in_i_stall(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_in_i_stall_reg1_q),
        .in_i_valid(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V0),
        .in_iord_bl_WStream_i_fifodata(in_iord_bl_WStream_i_fifodata),
        .in_iord_bl_WStream_i_fifovalid(in_iord_bl_WStream_i_fifovalid),
        .out_o_data_0_tpl(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_0_tpl),
        .out_o_data_1_tpl(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_1_tpl),
        .out_iord_bl_WStream_o_fifoalmost_full(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_iord_bl_WStream_o_fifoalmost_full),
        .out_iord_bl_WStream_o_fifoready(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_iord_bl_WStream_o_fifoready),
        .out_o_almost_empty(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_almost_empty),
        .out_o_empty(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_empty),
        .out_o_stall(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_stall),
        .out_o_valid(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_almost_empty_reg0(REG,144)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_almost_empty_reg0_q <= $unsigned(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_almost_empty);
        end
    end

    // i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_almost_empty_reg1(REG,143)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_almost_empty_reg1_q <= $unsigned(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_almost_empty_reg0_q);
        end
    end

    // i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_almost_empty_reg0(REG,156)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_almost_empty_reg0_q <= $unsigned(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_almost_empty);
        end
    end

    // i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_almost_empty_reg1(REG,155)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_almost_empty_reg1_q <= $unsigned(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_almost_empty_reg0_q);
        end
    end

    // coalesced_delay_0_fifo_o_empty_reg0(REG,224)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_empty_reg0_q <= $unsigned(coalesced_delay_0_fifo_o_empty);
        end
    end

    // coalesced_delay_0_fifo_o_empty_reg1(REG,223)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_empty_reg1_q <= $unsigned(coalesced_delay_0_fifo_o_empty_reg0_q);
        end
    end

    // i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_empty_reg0(REG,146)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_empty_reg0_q <= $unsigned(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_empty);
        end
    end

    // i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_empty_reg1(REG,145)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_empty_reg1_q <= $unsigned(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_empty_reg0_q);
        end
    end

    // i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_empty_reg0(REG,158)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_empty_reg0_q <= $unsigned(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_empty);
        end
    end

    // i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_empty_reg1(REG,157)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_empty_reg1_q <= $unsigned(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_empty_reg0_q);
        end
    end

    // merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg0(REG,129)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg0_q <= $unsigned(merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0);
        end
    end

    // merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg1(REG,128)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg1_q <= $unsigned(merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg0_q);
        end
    end

    // merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg2(REG,127)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg2_q <= $unsigned(merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg1_q);
        end
    end

    // merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg3(REG,126)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg3_q <= $unsigned(merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg2_q);
        end
    end

    // merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg4(REG,125)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg4_q <= $unsigned(merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg3_q);
        end
    end

    // merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg5(REG,124)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg5_q <= $unsigned(merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg4_q);
        end
    end

    // merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg6(REG,123)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg6_q <= $unsigned(merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg5_q);
        end
    end

    // i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_almost_empty_out_reg0(REG,190)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_almost_empty_out_reg0_q <= $unsigned(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_almost_empty_out);
        end
    end

    // i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_almost_empty_out_reg1(REG,189)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_almost_empty_out_reg1_q <= $unsigned(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_almost_empty_out_reg0_q);
        end
    end

    // join_for_coalesced_delay_1(BITJOIN,46)
    assign join_for_coalesced_delay_1_q = {bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_j, bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_g, bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_f};

    // coalesced_delay_1_fifo_i_stall_reg0(REG,227)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_1_fifo_i_stall_reg0_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_1_backStall);
        end
    end

    // coalesced_delay_1_fifo_i_stall_reg1(REG,228)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_1_fifo_i_stall_reg1_q <= $unsigned(coalesced_delay_1_fifo_i_stall_reg0_q);
        end
    end

    // coalesced_delay_1_fifo(STALLFIFO,49)
    assign coalesced_delay_1_fifo_i_valid = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V1;
    assign coalesced_delay_1_fifo_i_stall = coalesced_delay_1_fifo_i_stall_reg1_q;
    assign coalesced_delay_1_fifo_i_data = join_for_coalesced_delay_1_q;
    assign coalesced_delay_1_fifo_i_empty = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V5;
    assign coalesced_delay_1_fifo_i_almost_empty = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V9;
    assign coalesced_delay_1_fifo_i_valid_bitsignaltemp = coalesced_delay_1_fifo_i_valid[0];
    assign coalesced_delay_1_fifo_i_stall_bitsignaltemp = coalesced_delay_1_fifo_i_stall[0];
    assign coalesced_delay_1_fifo_o_valid[0] = coalesced_delay_1_fifo_o_valid_bitsignaltemp;
    assign coalesced_delay_1_fifo_o_stall[0] = coalesced_delay_1_fifo_o_stall_bitsignaltemp;
    assign coalesced_delay_1_fifo_o_empty[0] = coalesced_delay_1_fifo_o_empty_bitsignaltemp;
    assign coalesced_delay_1_fifo_o_almost_empty[0] = coalesced_delay_1_fifo_o_almost_empty_bitsignaltemp;
    hld_fifo #(
        .DEPTH(79),
        .WIDTH(3),
        .STYLE("ms"),
        .ALMOST_FULL_CUTOFF(7),
        .ALMOST_EMPTY_CUTOFF(7),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(0),
        .USE_STALL_LATENCY_UPSTREAM(1),
        .USE_STALL_LATENCY_DOWNSTREAM(1),
        .NEVER_OVERFLOWS(1),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(1)
    ) thecoalesced_delay_1_fifo (
        .i_valid(coalesced_delay_1_fifo_i_valid_bitsignaltemp),
        .i_stall(coalesced_delay_1_fifo_i_stall_bitsignaltemp),
        .i_data(join_for_coalesced_delay_1_q),
        .o_valid(coalesced_delay_1_fifo_o_valid_bitsignaltemp),
        .o_stall(coalesced_delay_1_fifo_o_stall_bitsignaltemp),
        .o_data(coalesced_delay_1_fifo_o_data),
        .o_empty(coalesced_delay_1_fifo_o_empty_bitsignaltemp),
        .o_almost_empty(coalesced_delay_1_fifo_o_almost_empty_bitsignaltemp),
        .clock(clock),
        .resetn(resetn)
    );

    // coalesced_delay_1_fifo_o_almost_empty_reg0(REG,236)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_1_fifo_o_almost_empty_reg0_q <= $unsigned(coalesced_delay_1_fifo_o_almost_empty);
        end
    end

    // coalesced_delay_1_fifo_o_almost_empty_reg1(REG,235)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_1_fifo_o_almost_empty_reg1_q <= $unsigned(coalesced_delay_1_fifo_o_almost_empty_reg0_q);
        end
    end

    // i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_empty_out_reg0(REG,192)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_empty_out_reg0_q <= $unsigned(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_empty_out);
        end
    end

    // i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_empty_out_reg1(REG,191)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_empty_out_reg1_q <= $unsigned(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_empty_out_reg0_q);
        end
    end

    // coalesced_delay_1_fifo_o_empty_reg0(REG,234)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_1_fifo_o_empty_reg0_q <= $unsigned(coalesced_delay_1_fifo_o_empty);
        end
    end

    // coalesced_delay_1_fifo_o_empty_reg1(REG,233)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_1_fifo_o_empty_reg1_q <= $unsigned(coalesced_delay_1_fifo_o_empty_reg0_q);
        end
    end

    // i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_o_valid_reg0(REG,194)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_o_valid_reg0_q <= $unsigned(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_o_valid);
        end
    end

    // i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_o_valid_reg1(REG,193)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_o_valid_reg1_q <= $unsigned(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_o_valid_reg0_q);
        end
    end

    // coalesced_delay_1_fifo_o_valid_reg0(REG,230)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_1_fifo_o_valid_reg0_q <= $unsigned(coalesced_delay_1_fifo_o_valid);
        end
    end

    // coalesced_delay_1_fifo_o_valid_reg1(REG,229)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_1_fifo_o_valid_reg1_q <= $unsigned(coalesced_delay_1_fifo_o_valid_reg0_q);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_1(STALLENABLE,122)
    // Sync
    assign merged_in_SE_sel_for_coalesced_delay_1_temp_back_stall = in_stall_in;
    assign merged_in_SE_sel_for_coalesced_delay_1_can_fast_read = ~ ((coalesced_delay_1_fifo_o_almost_empty_reg1_q | i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_almost_empty_out_reg1_q));
    assign merged_in_SE_sel_for_coalesced_delay_1_can_slow_read = ~ ((coalesced_delay_1_fifo_o_empty_reg1_q | i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_empty_out_reg1_q));
    assign merged_in_SE_sel_for_coalesced_delay_1_backStall = ~ (merged_in_SE_sel_for_coalesced_delay_1_forced_read);
    assign merged_in_SE_sel_for_coalesced_delay_1_no_space_for_result = merged_in_SE_sel_for_coalesced_delay_1_temp_back_stall;
    assign merged_in_SE_sel_for_coalesced_delay_1_V0 = merged_in_SE_sel_for_coalesced_delay_1_forced_read;
    assign merged_in_SE_sel_for_coalesced_delay_1_V1 = $unsigned(1'b0);
    assign merged_in_SE_sel_for_coalesced_delay_1_V2 = $unsigned(1'b0);
    assign can_fast_read_bitsignaltemp_dup_name_0 = merged_in_SE_sel_for_coalesced_delay_1_can_fast_read[0];
    assign can_slow_read_bitsignaltemp_dup_name_0 = merged_in_SE_sel_for_coalesced_delay_1_can_slow_read[0];
    assign no_space_for_result_bitsignaltemp_dup_name_0 = merged_in_SE_sel_for_coalesced_delay_1_no_space_for_result[0];
    assign merged_in_SE_sel_for_coalesced_delay_1_forced_read[0] = forced_read_bitsignaltemp_dup_name_0;
    acl_sync_stall_latency #(
        .EMPTY_PLUS_STALL_LATENCY(7),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(1),
        .RESET_EVERYTHING(0)
    ) themerged_in_SE_sel_for_coalesced_delay_1 (
        .can_fast_read(can_fast_read_bitsignaltemp_dup_name_0),
        .can_slow_read(can_slow_read_bitsignaltemp_dup_name_0),
        .no_space_for_result(no_space_for_result_bitsignaltemp_dup_name_0),
        .forced_read(forced_read_bitsignaltemp_dup_name_0),
        .clock(clock),
        .resetn(resetn)
    );

    // i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_in_i_stall_reg0(REG,187)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_in_i_stall_reg0_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_1_backStall);
        end
    end

    // i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_in_i_stall_reg1(REG,188)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_in_i_stall_reg1_q <= $unsigned(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_in_i_stall_reg0_q);
        end
    end

    // i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_1_tpl_reg0(REG,142)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_1_tpl_reg0_q <= $unsigned(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_1_tpl);
        end
    end

    // i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_1_tpl_reg1(REG,141)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_1_tpl_reg1_q <= $unsigned(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_1_tpl_reg0_q);
        end
    end

    // i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_0_tpl_reg0(REG,140)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_0_tpl_reg0_q <= $unsigned(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_0_tpl);
        end
    end

    // i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_0_tpl_reg1(REG,139)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_0_tpl_reg1_q <= $unsigned(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_0_tpl_reg0_q);
        end
    end

    // bubble_join_i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x(BITJOIN,51)
    assign bubble_join_i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_q = {i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_1_tpl_reg1_q, i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_data_0_tpl_reg1_q};

    // bubble_select_i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x(BITSELECT,52)
    assign bubble_select_i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_b = $unsigned(bubble_join_i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_q[15:0]);
    assign bubble_select_i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_c = $unsigned(bubble_join_i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_q[31:16]);

    // i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_1_tpl_reg0(REG,154)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_1_tpl_reg0_q <= $unsigned(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_1_tpl);
        end
    end

    // i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_1_tpl_reg1(REG,153)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_1_tpl_reg1_q <= $unsigned(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_1_tpl_reg0_q);
        end
    end

    // i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_0_tpl_reg0(REG,152)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_0_tpl_reg0_q <= $unsigned(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_0_tpl);
        end
    end

    // i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_0_tpl_reg1(REG,151)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_0_tpl_reg1_q <= $unsigned(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_0_tpl_reg0_q);
        end
    end

    // bubble_join_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x(BITJOIN,54)
    assign bubble_join_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_q = {i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_1_tpl_reg1_q, i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_0_tpl_reg1_q};

    // bubble_select_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x(BITSELECT,55)
    assign bubble_select_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_b = $unsigned(bubble_join_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_q[15:0]);
    assign bubble_select_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_c = $unsigned(bubble_join_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_q[31:16]);

    // coalesced_delay_0_fifo_o_data_reg0(REG,222)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_data_reg0_q <= $unsigned(coalesced_delay_0_fifo_o_data);
        end
    end

    // coalesced_delay_0_fifo_o_data_reg1(REG,221)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_data_reg1_q <= $unsigned(coalesced_delay_0_fifo_o_data_reg0_q);
        end
    end

    // bubble_join_coalesced_delay_0_fifo(BITJOIN,66)
    assign bubble_join_coalesced_delay_0_fifo_q = coalesced_delay_0_fifo_o_data_reg1_q;

    // bubble_select_coalesced_delay_0_fifo(BITSELECT,67)
    assign bubble_select_coalesced_delay_0_fifo_b = $unsigned(bubble_join_coalesced_delay_0_fifo_q[36:0]);

    // sel_for_coalesced_delay_0(BITSELECT,44)
    assign sel_for_coalesced_delay_0_b = $unsigned(bubble_select_coalesced_delay_0_fifo_b[31:0]);
    assign sel_for_coalesced_delay_0_c = $unsigned(bubble_select_coalesced_delay_0_fifo_b[32:32]);
    assign sel_for_coalesced_delay_0_d = $unsigned(bubble_select_coalesced_delay_0_fifo_b[33:33]);
    assign sel_for_coalesced_delay_0_e = $unsigned(bubble_select_coalesced_delay_0_fifo_b[34:34]);
    assign sel_for_coalesced_delay_0_f = $unsigned(bubble_select_coalesced_delay_0_fifo_b[35:35]);
    assign sel_for_coalesced_delay_0_g = $unsigned(bubble_select_coalesced_delay_0_fifo_b[36:36]);

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x(BLACKBOX,12)@59
    // in in_i_stall@20000000
    // out out_c1_exit_0_tpl@96
    // out out_almost_empty_out@96
    // out out_empty_out@96
    // out out_memdep_17_c_compSTR_avm_address@20000000
    // out out_memdep_17_c_compSTR_avm_burstcount@20000000
    // out out_memdep_17_c_compSTR_avm_byteenable@20000000
    // out out_memdep_17_c_compSTR_avm_enable@20000000
    // out out_memdep_17_c_compSTR_avm_read@20000000
    // out out_memdep_17_c_compSTR_avm_write@20000000
    // out out_memdep_17_c_compSTR_avm_writedata@20000000
    // out out_memdep_5_c_compSTR_avm_address@20000000
    // out out_memdep_5_c_compSTR_avm_burstcount@20000000
    // out out_memdep_5_c_compSTR_avm_byteenable@20000000
    // out out_memdep_5_c_compSTR_avm_enable@20000000
    // out out_memdep_5_c_compSTR_avm_read@20000000
    // out out_memdep_5_c_compSTR_avm_write@20000000
    // out out_memdep_5_c_compSTR_avm_writedata@20000000
    // out out_o_stall@20000000
    // out out_o_valid@96
    c_compSTR_i_sfc_s_c1_in_for_body20_c_com0000c1_enter_c_compstr13 thei_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x (
        .in_c1_eni8_0_tpl(GND_q),
        .in_c1_eni8_1_tpl(sel_for_coalesced_delay_0_b),
        .in_c1_eni8_2_tpl(sel_for_coalesced_delay_0_g),
        .in_c1_eni8_3_tpl(bubble_select_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_b),
        .in_c1_eni8_4_tpl(bubble_select_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_c),
        .in_c1_eni8_5_tpl(sel_for_coalesced_delay_0_c),
        .in_c1_eni8_6_tpl(sel_for_coalesced_delay_0_d),
        .in_c1_eni8_7_tpl(bubble_select_i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_b),
        .in_c1_eni8_8_tpl(bubble_select_i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_c),
        .in_c1_eni8_9_tpl(sel_for_coalesced_delay_0_e),
        .in_c1_eni8_10_tpl(sel_for_coalesced_delay_0_f),
        .in_almost_empty_in(merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V2),
        .in_c0_exe4718(sel_for_coalesced_delay_0_f),
        .in_c0_exe7721(sel_for_coalesced_delay_0_g),
        .in_empty_in(merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V1),
        .in_flush(in_flush),
        .in_i_stall(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_in_i_stall_reg1_q),
        .in_i_valid(merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0_sync_valid_reg6_q),
        .in_memdep_17_c_compSTR_avm_readdata(in_memdep_17_c_compSTR_avm_readdata),
        .in_memdep_17_c_compSTR_avm_readdatavalid(in_memdep_17_c_compSTR_avm_readdatavalid),
        .in_memdep_17_c_compSTR_avm_waitrequest(in_memdep_17_c_compSTR_avm_waitrequest),
        .in_memdep_17_c_compSTR_avm_writeack(in_memdep_17_c_compSTR_avm_writeack),
        .in_memdep_5_c_compSTR_avm_readdata(in_memdep_5_c_compSTR_avm_readdata),
        .in_memdep_5_c_compSTR_avm_readdatavalid(in_memdep_5_c_compSTR_avm_readdatavalid),
        .in_memdep_5_c_compSTR_avm_waitrequest(in_memdep_5_c_compSTR_avm_waitrequest),
        .in_memdep_5_c_compSTR_avm_writeack(in_memdep_5_c_compSTR_avm_writeack),
        .out_c1_exit_0_tpl(),
        .out_almost_empty_out(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_almost_empty_out),
        .out_empty_out(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_empty_out),
        .out_memdep_17_c_compSTR_avm_address(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_address),
        .out_memdep_17_c_compSTR_avm_burstcount(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_burstcount),
        .out_memdep_17_c_compSTR_avm_byteenable(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_byteenable),
        .out_memdep_17_c_compSTR_avm_enable(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_enable),
        .out_memdep_17_c_compSTR_avm_read(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_read),
        .out_memdep_17_c_compSTR_avm_write(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_write),
        .out_memdep_17_c_compSTR_avm_writedata(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_writedata),
        .out_memdep_5_c_compSTR_avm_address(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_address),
        .out_memdep_5_c_compSTR_avm_burstcount(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_burstcount),
        .out_memdep_5_c_compSTR_avm_byteenable(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_byteenable),
        .out_memdep_5_c_compSTR_avm_enable(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_enable),
        .out_memdep_5_c_compSTR_avm_read(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_read),
        .out_memdep_5_c_compSTR_avm_write(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_write),
        .out_memdep_5_c_compSTR_avm_writedata(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_writedata),
        .out_o_stall(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_o_stall),
        .out_o_valid(i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // coalesced_delay_0_fifo_o_valid_reg0(REG,220)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_valid_reg0_q <= $unsigned(coalesced_delay_0_fifo_o_valid);
        end
    end

    // coalesced_delay_0_fifo_o_valid_reg1(REG,219)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_0_fifo_o_valid_reg1_q <= $unsigned(coalesced_delay_0_fifo_o_valid_reg0_q);
        end
    end

    // i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_valid_reg0(REG,148)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_valid_reg0_q <= $unsigned(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_valid);
        end
    end

    // i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_valid_reg1(REG,147)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_valid_reg1_q <= $unsigned(i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_valid_reg0_q);
        end
    end

    // i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_valid_reg0(REG,160)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_valid_reg0_q <= $unsigned(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_valid);
        end
    end

    // i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_valid_reg1(REG,159)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_valid_reg1_q <= $unsigned(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_valid_reg0_q);
        end
    end

    // merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x(STALLENABLE,121)
    // Sync
    assign merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_temp_back_stall = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_o_stall;
    assign merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_can_fast_read = ~ ((i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_almost_empty_reg1_q | i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_almost_empty_reg1_q | coalesced_delay_0_fifo_o_almost_empty_reg1_q));
    assign merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_can_slow_read = ~ ((i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_empty_reg1_q | i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_empty_reg1_q | coalesced_delay_0_fifo_o_empty_reg1_q));
    assign merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_backStall = ~ (merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_forced_read);
    assign merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_no_space_for_result = merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_temp_back_stall;
    assign merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V0 = merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_forced_read;
    assign merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V1 = $unsigned(1'b0);
    assign merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_V2 = $unsigned(1'b0);
    assign can_fast_read_bitsignaltemp = merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_can_fast_read[0];
    assign can_slow_read_bitsignaltemp = merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_can_slow_read[0];
    assign no_space_for_result_bitsignaltemp = merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_no_space_for_result[0];
    assign merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_forced_read[0] = forced_read_bitsignaltemp;
    acl_sync_stall_latency #(
        .EMPTY_PLUS_STALL_LATENCY(7),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(1),
        .RESET_EVERYTHING(0)
    ) themerged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x (
        .can_fast_read(can_fast_read_bitsignaltemp),
        .can_slow_read(can_slow_read_bitsignaltemp),
        .no_space_for_result(no_space_for_result_bitsignaltemp),
        .forced_read(forced_read_bitsignaltemp),
        .clock(clock),
        .resetn(resetn)
    );

    // i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_in_i_stall_reg0(REG,149)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_in_i_stall_reg0_q <= $unsigned(merged_in_SE_in_i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_backStall);
        end
    end

    // i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_in_i_stall_reg1(REG,150)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_in_i_stall_reg1_q <= $unsigned(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_in_i_stall_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_in_i_stall_reg0(REG,161)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_in_i_stall_reg0_q <= $unsigned(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_backStall);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_in_i_stall_reg1(REG,162)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_in_i_stall_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_in_i_stall_reg0_q);
        end
    end

    // stall_entry_frontAlmostEmpty_reg0(REG,202)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontAlmostEmpty_reg0_q <= $unsigned(in_almost_empty_in);
        end
    end

    // stall_entry_frontAlmostEmpty_reg1(REG,201)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontAlmostEmpty_reg1_q <= $unsigned(stall_entry_frontAlmostEmpty_reg0_q);
        end
    end

    // stall_entry_frontEmpty_reg0(REG,200)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontEmpty_reg0_q <= $unsigned(in_empty_in);
        end
    end

    // stall_entry_frontEmpty_reg1(REG,199)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontEmpty_reg1_q <= $unsigned(stall_entry_frontEmpty_reg0_q);
        end
    end

    // stall_entry_frontValid_reg0(REG,198)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontValid_reg0_q <= $unsigned(in_valid_in);
        end
    end

    // stall_entry_frontValid_reg1(REG,197)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontValid_reg1_q <= $unsigned(stall_entry_frontValid_reg0_q);
        end
    end

    // merged_in_SE_bubble_join_stall_entry(STALLENABLE,119)
    assign merged_in_SE_bubble_join_stall_entry_backStall = i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_stall;
    assign merged_in_SE_bubble_join_stall_entry_V0 = stall_entry_frontValid_reg1_q;
    assign merged_in_SE_bubble_join_stall_entry_V1 = stall_entry_frontEmpty_reg1_q;
    assign merged_in_SE_bubble_join_stall_entry_V2 = stall_entry_frontAlmostEmpty_reg1_q;

    // stall_entry_o10_reg0(REG,216)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o10_reg0_q <= $unsigned(in_notcmp21685);
        end
    end

    // stall_entry_o10_reg1(REG,215)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o10_reg1_q <= $unsigned(stall_entry_o10_reg0_q);
        end
    end

    // stall_entry_o9_reg0(REG,214)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o9_reg0_q <= $unsigned(in_memdep_phi_pop9679);
        end
    end

    // stall_entry_o9_reg1(REG,213)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o9_reg1_q <= $unsigned(stall_entry_o9_reg0_q);
        end
    end

    // stall_entry_o8_reg0(REG,212)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o8_reg0_q <= $unsigned(in_memdep_phi_pop930_pop13686);
        end
    end

    // stall_entry_o8_reg1(REG,211)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o8_reg1_q <= $unsigned(stall_entry_o8_reg0_q);
        end
    end

    // stall_entry_o7_reg0(REG,210)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o7_reg0_q <= $unsigned(in_memdep_phi9_pop10682);
        end
    end

    // stall_entry_o7_reg1(REG,209)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o7_reg1_q <= $unsigned(stall_entry_o7_reg0_q);
        end
    end

    // stall_entry_o6_reg0(REG,208)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o6_reg0_q <= $unsigned(in_memdep_phi9_pop1032_pop14687);
        end
    end

    // stall_entry_o6_reg1(REG,207)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o6_reg1_q <= $unsigned(stall_entry_o6_reg0_q);
        end
    end

    // stall_entry_o5_reg0(REG,206)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o5_reg0_q <= $unsigned(in_i_0288_pop12683);
        end
    end

    // stall_entry_o5_reg1(REG,205)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o5_reg1_q <= $unsigned(stall_entry_o5_reg0_q);
        end
    end

    // stall_entry_o4_reg0(REG,204)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o4_reg0_q <= $unsigned(in_cmp21684);
        end
    end

    // stall_entry_o4_reg1(REG,203)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_o4_reg1_q <= $unsigned(stall_entry_o4_reg0_q);
        end
    end

    // bubble_join_stall_entry(BITJOIN,62)
    assign bubble_join_stall_entry_q = {stall_entry_o10_reg1_q, stall_entry_o9_reg1_q, stall_entry_o8_reg1_q, stall_entry_o7_reg1_q, stall_entry_o6_reg1_q, stall_entry_o5_reg1_q, stall_entry_o4_reg1_q};

    // bubble_select_stall_entry(BITSELECT,63)
    assign bubble_select_stall_entry_b = $unsigned(bubble_join_stall_entry_q[0:0]);
    assign bubble_select_stall_entry_c = $unsigned(bubble_join_stall_entry_q[32:1]);
    assign bubble_select_stall_entry_d = $unsigned(bubble_join_stall_entry_q[33:33]);
    assign bubble_select_stall_entry_e = $unsigned(bubble_join_stall_entry_q[34:34]);
    assign bubble_select_stall_entry_f = $unsigned(bubble_join_stall_entry_q[35:35]);
    assign bubble_select_stall_entry_g = $unsigned(bubble_join_stall_entry_q[36:36]);
    assign bubble_select_stall_entry_h = $unsigned(bubble_join_stall_entry_q[37:37]);

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x(BLACKBOX,11)@0
    // in in_i_stall@20000000
    // out out_c0_exit714_0_tpl@35
    // out out_c0_exit714_1_tpl@35
    // out out_c0_exit714_2_tpl@35
    // out out_c0_exit714_3_tpl@35
    // out out_c0_exit714_4_tpl@35
    // out out_c0_exit714_5_tpl@35
    // out out_c0_exit714_6_tpl@35
    // out out_c0_exit714_7_tpl@35
    // out out_c0_exit714_8_tpl@35
    // out out_c0_exit714_9_tpl@35
    // out out_c0_exit714_10_tpl@35
    // out out_almost_empty_out@35
    // out out_empty_out@35
    // out out_o_stall@20000000
    // out out_o_valid@35
    // out out_profile_loop_o_valid@35
    c_compSTR_i_sfc_s_c0_in_for_body20_c_com0000enter7026_c_compstr8 thei_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x (
        .in_c0_eni8_0_tpl(GND_q),
        .in_c0_eni8_1_tpl(bubble_select_stall_entry_b),
        .in_c0_eni8_2_tpl(GND_q),
        .in_c0_eni8_3_tpl(bubble_select_stall_entry_f),
        .in_c0_eni8_4_tpl(bubble_select_stall_entry_d),
        .in_c0_eni8_5_tpl(bubble_select_stall_entry_h),
        .in_c0_eni8_6_tpl(bubble_select_stall_entry_g),
        .in_c0_eni8_7_tpl(bubble_select_stall_entry_e),
        .in_c0_eni8_8_tpl(bubble_select_stall_entry_c),
        .in_almost_empty_in(merged_in_SE_bubble_join_stall_entry_V2),
        .in_empty_in(merged_in_SE_bubble_join_stall_entry_V1),
        .in_i_stall(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_in_i_stall_reg1_q),
        .in_i_valid(merged_in_SE_bubble_join_stall_entry_V0),
        .out_c0_exit714_0_tpl(),
        .out_c0_exit714_1_tpl(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_1_tpl),
        .out_c0_exit714_2_tpl(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_2_tpl),
        .out_c0_exit714_3_tpl(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_3_tpl),
        .out_c0_exit714_4_tpl(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_4_tpl),
        .out_c0_exit714_5_tpl(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_5_tpl),
        .out_c0_exit714_6_tpl(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_6_tpl),
        .out_c0_exit714_7_tpl(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_7_tpl),
        .out_c0_exit714_8_tpl(),
        .out_c0_exit714_9_tpl(),
        .out_c0_exit714_10_tpl(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_10_tpl),
        .out_almost_empty_out(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_almost_empty_out),
        .out_empty_out(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_empty_out),
        .out_o_stall(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_stall),
        .out_o_valid(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_valid),
        .out_profile_loop_o_valid(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_profile_loop_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_profile_loop_o_valid_reg0(REG,186)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_profile_loop_o_valid_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_profile_loop_o_valid);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_profile_loop_o_valid_reg1(REG,185)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_profile_loop_o_valid_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_profile_loop_o_valid_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_10_tpl_reg0(REG,178)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_10_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_10_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_10_tpl_reg1(REG,177)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_10_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_10_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_7_tpl_reg0(REG,176)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_7_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_7_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_7_tpl_reg1(REG,175)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_7_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_7_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_6_tpl_reg0(REG,174)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_6_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_6_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_6_tpl_reg1(REG,173)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_6_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_6_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_5_tpl_reg0(REG,172)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_5_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_5_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_5_tpl_reg1(REG,171)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_5_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_5_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_4_tpl_reg0(REG,170)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_4_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_4_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_4_tpl_reg1(REG,169)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_4_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_4_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_3_tpl_reg0(REG,168)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_3_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_3_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_3_tpl_reg1(REG,167)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_3_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_3_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_2_tpl_reg0(REG,166)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_2_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_2_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_2_tpl_reg1(REG,165)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_2_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_2_tpl_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_1_tpl_reg0(REG,164)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_1_tpl_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_1_tpl);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_1_tpl_reg1(REG,163)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_1_tpl_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_1_tpl_reg0_q);
        end
    end

    // bubble_join_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x(BITJOIN,57)
    assign bubble_join_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_q = {i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_profile_loop_o_valid_reg1_q, i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_10_tpl_reg1_q, i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_7_tpl_reg1_q, i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_6_tpl_reg1_q, i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_5_tpl_reg1_q, i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_4_tpl_reg1_q, i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_3_tpl_reg1_q, i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_2_tpl_reg1_q, i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_c0_exit714_1_tpl_reg1_q};

    // bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x(BITSELECT,58)
    assign bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_b = $unsigned(bubble_join_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_q[0:0]);
    assign bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_c = $unsigned(bubble_join_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_q[1:1]);
    assign bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_d = $unsigned(bubble_join_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_q[2:2]);
    assign bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_e = $unsigned(bubble_join_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_q[3:3]);
    assign bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_f = $unsigned(bubble_join_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_q[4:4]);
    assign bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_g = $unsigned(bubble_join_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_q[5:5]);
    assign bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_h = $unsigned(bubble_join_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_q[6:6]);
    assign bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_i = $unsigned(bubble_join_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_q[38:7]);
    assign bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_j = $unsigned(bubble_join_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_q[39:39]);

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_almost_empty_out_reg0(REG,180)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_almost_empty_out_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_almost_empty_out);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_almost_empty_out_reg1(REG,179)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_almost_empty_out_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_almost_empty_out_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_empty_out_reg0(REG,182)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_empty_out_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_empty_out);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_empty_out_reg1(REG,181)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_empty_out_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_empty_out_reg0_q);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_valid_reg0(REG,184)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_valid_reg0_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_valid);
        end
    end

    // i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_valid_reg1(REG,183)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_valid_reg1_q <= $unsigned(i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_valid_reg0_q);
        end
    end

    // merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x(STALLENABLE,120)
    // Desync
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_temp_back_stall = i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_o_stall | coalesced_delay_1_fifo_o_stall | coalesced_delay_0_fifo_o_stall | i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_stall;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_backStall = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_temp_back_stall;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V0 = i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_o_valid_reg1_q;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V4 = i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_empty_out_reg1_q;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V8 = i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_out_almost_empty_out_reg1_q;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V1 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V0;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V5 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V4;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V9 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V8;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V2 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V0;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V6 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V4;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V10 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V8;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V3 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V0;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V7 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V4;
    assign merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V11 = merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V8;

    // i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x(BLACKBOX,10)@35
    // in in_i_stall@20000000
    // out out_o_data_0_tpl@59
    // out out_o_data_1_tpl@59
    // out out_iord_bl_yStream_o_fifoalmost_full@20000000
    // out out_iord_bl_yStream_o_fifoready@20000000
    // out out_o_almost_empty@59
    // out out_o_empty@59
    // out out_o_stall@20000000
    // out out_o_valid@59
    c_compSTR_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr0 thei_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x (
        .in_almost_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V11),
        .in_c0_exe1715(bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_b),
        .in_empty_in(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V7),
        .in_i_stall(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_in_i_stall_reg1_q),
        .in_i_valid(merged_in_SE_bubble_select_i_sfc_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr8_aunroll_x_V3),
        .in_iord_bl_yStream_i_fifodata(in_iord_bl_yStream_i_fifodata),
        .in_iord_bl_yStream_i_fifovalid(in_iord_bl_yStream_i_fifovalid),
        .out_o_data_0_tpl(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_0_tpl),
        .out_o_data_1_tpl(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_data_1_tpl),
        .out_iord_bl_yStream_o_fifoalmost_full(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_iord_bl_yStream_o_fifoalmost_full),
        .out_iord_bl_yStream_o_fifoready(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_iord_bl_yStream_o_fifoready),
        .out_o_almost_empty(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_almost_empty),
        .out_o_empty(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_empty),
        .out_o_stall(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_stall),
        .out_o_valid(i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_ext_sig_sync_out_x(GPOUT,3)
    assign out_iord_bl_yStream_o_fifoready = i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_iord_bl_yStream_o_fifoready;
    assign out_iord_bl_yStream_o_fifoalmost_full = i_iord_bl_ystream_unnamed_c_compstr2_c_compstr11_aunroll_x_out_iord_bl_yStream_o_fifoalmost_full;

    // merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg0(REG,136)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg0_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_1_V0);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg1(REG,135)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg1_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg0_q);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg2(REG,134)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg2_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg1_q);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg3(REG,133)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg3_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg2_q);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg4(REG,132)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg4_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg3_q);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg5(REG,131)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg5_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg4_q);
        end
    end

    // merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg6(REG,130)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg6_q <= $unsigned(merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg5_q);
        end
    end

    // coalesced_delay_1_fifo_o_data_reg0(REG,232)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_1_fifo_o_data_reg0_q <= $unsigned(coalesced_delay_1_fifo_o_data);
        end
    end

    // coalesced_delay_1_fifo_o_data_reg1(REG,231)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            coalesced_delay_1_fifo_o_data_reg1_q <= $unsigned(coalesced_delay_1_fifo_o_data_reg0_q);
        end
    end

    // bubble_join_coalesced_delay_1_fifo(BITJOIN,69)
    assign bubble_join_coalesced_delay_1_fifo_q = coalesced_delay_1_fifo_o_data_reg1_q;

    // bubble_select_coalesced_delay_1_fifo(BITSELECT,70)
    assign bubble_select_coalesced_delay_1_fifo_b = $unsigned(bubble_join_coalesced_delay_1_fifo_q[2:0]);

    // sel_for_coalesced_delay_1(BITSELECT,47)
    assign sel_for_coalesced_delay_1_b = $unsigned(bubble_select_coalesced_delay_1_fifo_b[0:0]);
    assign sel_for_coalesced_delay_1_c = $unsigned(bubble_select_coalesced_delay_1_fifo_b[1:1]);
    assign sel_for_coalesced_delay_1_d = $unsigned(bubble_select_coalesced_delay_1_fifo_b[2:2]);

    // dupName_0_sync_out_x(GPOUT,4)@96
    assign out_almost_empty_out = merged_in_SE_sel_for_coalesced_delay_1_V2;
    assign out_c0_exe5719 = sel_for_coalesced_delay_1_b;
    assign out_c0_exe6720 = sel_for_coalesced_delay_1_c;
    assign out_empty_out = merged_in_SE_sel_for_coalesced_delay_1_V1;
    assign out_profile_loop_o_valid = sel_for_coalesced_delay_1_d;
    assign out_valid_out = merged_in_SE_sel_for_coalesced_delay_1_V0_sync_valid_reg6_q;

    // dupName_1_ext_sig_sync_out_x(GPOUT,6)
    assign out_memdep_5_c_compSTR_avm_address = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_address;
    assign out_memdep_5_c_compSTR_avm_enable = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_enable;
    assign out_memdep_5_c_compSTR_avm_read = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_read;
    assign out_memdep_5_c_compSTR_avm_write = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_write;
    assign out_memdep_5_c_compSTR_avm_writedata = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_writedata;
    assign out_memdep_5_c_compSTR_avm_byteenable = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_byteenable;
    assign out_memdep_5_c_compSTR_avm_burstcount = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_5_c_compSTR_avm_burstcount;

    // dupName_2_ext_sig_sync_out_x(GPOUT,8)
    assign out_memdep_17_c_compSTR_avm_address = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_address;
    assign out_memdep_17_c_compSTR_avm_enable = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_enable;
    assign out_memdep_17_c_compSTR_avm_read = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_read;
    assign out_memdep_17_c_compSTR_avm_write = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_write;
    assign out_memdep_17_c_compSTR_avm_writedata = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_writedata;
    assign out_memdep_17_c_compSTR_avm_byteenable = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_byteenable;
    assign out_memdep_17_c_compSTR_avm_burstcount = i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13_aunroll_x_out_memdep_17_c_compSTR_avm_burstcount;

    // ext_sig_sync_out(GPOUT,18)
    assign out_iord_bl_WStream_o_fifoready = i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_iord_bl_WStream_o_fifoready;
    assign out_iord_bl_WStream_o_fifoalmost_full = i_iord_bl_wstream_unnamed_c_compstr1_c_compstr10_aunroll_x_out_iord_bl_WStream_o_fifoalmost_full;

    // stall_entry_frontStall_reg0(REG,195)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontStall_reg0_q <= $unsigned(merged_in_SE_bubble_join_stall_entry_backStall);
        end
    end

    // stall_entry_frontStall_reg1(REG,196)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            stall_entry_frontStall_reg1_q <= $unsigned(stall_entry_frontStall_reg0_q);
        end
    end

    // sync_out(GPOUT,31)@0
    assign out_stall_out = stall_entry_frontStall_reg1_q;

    // rst_sync(RESETSYNC,237)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
