// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from c_compSTR_B5_branch
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_B5_branch (
    input wire [0:0] in_almost_empty_in,
    input wire [0:0] in_c0_exe5719,
    input wire [0:0] in_c0_exe6720,
    input wire [0:0] in_empty_in,
    input wire [0:0] in_stall_in_0,
    input wire [0:0] in_valid_in,
    output wire [0:0] out_c0_exe6720,
    output wire [0:0] out_stall_out,
    output wire [0:0] out_valid_out_0,
    input wire clock,
    input wire resetn
    );

    wire [0:0] adapt_scalar_trunc2_in;
    wire [0:0] adapt_scalar_trunc2_q;
    wire [7:0] c_compSTR_B5_branch_data_pack_q;
    wire [0:0] c_compSTR_B5_branch_valid_and_q;
    wire [6:0] c_i7_01_q;
    wire [7:0] element_extension0_q;
    reg [0:0] rst_sync_rst_sclrn;


    // c_i7_01(CONSTANT,6)
    assign c_i7_01_q = $unsigned(7'b0000000);

    // element_extension0(BITJOIN,7)
    assign element_extension0_q = {c_i7_01_q, in_c0_exe6720};

    // c_compSTR_B5_branch_data_pack(BITJOIN,3)
    assign c_compSTR_B5_branch_data_pack_q = element_extension0_q;

    // adapt_scalar_trunc2(ROUND,2)
    assign adapt_scalar_trunc2_in = c_compSTR_B5_branch_data_pack_q[0:0];
    assign adapt_scalar_trunc2_q = adapt_scalar_trunc2_in[0:0];

    // out_c0_exe6720(GPOUT,14)
    assign out_c0_exe6720 = adapt_scalar_trunc2_q;

    // out_stall_out(GPOUT,15)
    assign out_stall_out = in_stall_in_0;

    // c_compSTR_B5_branch_valid_and(LOGICAL,5)
    assign c_compSTR_B5_branch_valid_and_q = in_valid_in & in_c0_exe5719;

    // out_valid_out_0(GPOUT,16)
    assign out_valid_out_0 = c_compSTR_B5_branch_valid_and_q;

    // rst_sync(RESETSYNC,17)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
