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// SystemVerilog created from i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr0
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_i_llvm_fpga_sfc_exit_s_c0_out_0000s_c0_exit_c_compstr0 (
    output wire [0:0] out_almost_empty_out,
    output wire [0:0] out_data_out_0_tpl,
    output wire [0:0] out_data_out_1_tpl,
    output wire [0:0] out_data_out_2_tpl,
    output wire [0:0] out_empty_out,
    output wire [0:0] out_valid_out,
    input wire [0:0] in_data_in_0_tpl,
    input wire [0:0] in_data_in_1_tpl,
    input wire [0:0] in_data_in_2_tpl,
    input wire [0:0] in_input_accepted,
    input wire [0:0] in_mask_valid,
    input wire [0:0] in_valid_in,
    input wire [0:0] in_stall_in,
    output wire [0:0] out_stall_entry,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    reg [0:0] before_fifo_0_x_q;
    reg [0:0] before_fifo_1_x_q;
    reg [0:0] before_fifo_2_x_q;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_data_0_tpl;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_data_1_tpl;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_data_2_tpl;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_almost_empty;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_empty;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_stall;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_valid;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_full_detector_out_full;
    wire [0:0] masked_valid_q;
    wire [0:0] not_mask_valid_q;
    wire [0:0] stall_out_or_q;
    wire [0:0] valid_and_masked_q;
    reg [0:0] valid_before_fifo_q;


    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // not_mask_valid(LOGICAL,13)
    assign not_mask_valid_q = ~ (in_mask_valid);

    // masked_valid(LOGICAL,12)
    assign masked_valid_q = in_valid_in & not_mask_valid_q;

    // valid_before_fifo(REG,18)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_before_fifo_q <= masked_valid_q;
        end
    end

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // before_fifo_2_x(REG,5)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            before_fifo_2_x_q <= in_data_in_2_tpl;
        end
    end

    // before_fifo_1_x(REG,4)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            before_fifo_1_x_q <= in_data_in_1_tpl;
        end
    end

    // before_fifo_0_x(REG,3)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            before_fifo_0_x_q <= in_data_in_0_tpl;
        end
    end

    // i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x(BLACKBOX,6)@19999970
    // in in_i_stall@20000000
    // out out_o_data_0_tpl@20000000
    // out out_o_data_1_tpl@20000000
    // out out_o_data_2_tpl@20000000
    // out out_o_almost_empty@20000000
    // out out_o_empty@20000000
    // out out_o_stall@20000000
    // out out_o_valid@20000000
    c_compSTR_i_llvm_fpga_sfc_exit_s_c0_out_0000c_compstr1_data_fifo thei_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x (
        .in_i_data_0_tpl(before_fifo_0_x_q),
        .in_i_data_1_tpl(before_fifo_1_x_q),
        .in_i_data_2_tpl(before_fifo_2_x_q),
        .in_almost_empty_in(GND_q),
        .in_empty_in(GND_q),
        .in_i_stall(in_stall_in),
        .in_i_valid(valid_before_fifo_q),
        .out_o_data_0_tpl(i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_data_0_tpl),
        .out_o_data_1_tpl(i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_data_1_tpl),
        .out_o_data_2_tpl(i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_data_2_tpl),
        .out_o_almost_empty(i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_almost_empty),
        .out_o_empty(i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_empty),
        .out_o_stall(i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_stall),
        .out_o_valid(i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_valid),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_sync_out_aunroll_x(GPOUT,2)@35
    assign out_almost_empty_out = i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_almost_empty;
    assign out_data_out_0_tpl = i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_data_0_tpl;
    assign out_data_out_1_tpl = i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_data_1_tpl;
    assign out_data_out_2_tpl = i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_data_2_tpl;
    assign out_empty_out = i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_empty;
    assign out_valid_out = i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_valid;

    // valid_and_masked(LOGICAL,17)
    assign valid_and_masked_q = in_mask_valid & in_valid_in;

    // i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_full_detector(BLACKBOX,11)@20000000
    c_compSTR_i_llvm_fpga_sfc_exit_s_c0_out_0000mpstr1_full_detector thei_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_full_detector (
        .in_dec_pipelined_thread(GND_q),
        .in_decrement(i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_valid),
        .in_decrement2(valid_and_masked_q),
        .in_inc_pipelined_thread(GND_q),
        .in_increment(in_input_accepted),
        .out_full(i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_full_detector_out_full),
        .out_throttle(),
        .clock(clock),
        .resetn(resetn)
    );

    // stall_out_or(LOGICAL,15)
    assign stall_out_or_q = i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_full_detector_out_full | i_llvm_fpga_sfc_exit_s_c0_out_wt_entry_c_compstrs_c0_exit_c_compstr1_data_fifo_aunroll_x_out_o_stall;

    // sync_out(GPOUT,16)@20000000
    assign out_stall_entry = stall_out_or_q;

endmodule
