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// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from dupName_0_wait_pulse_extender_inst_3616i0061663662c62i65o64u60uq0cx5gv9sqcz
// Created for function/kernel c_compMM_m
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compMM_m_dupName_0_wait_pulse_extender00005o64u60uq0cx5gv9sqcz (
    output wire [0:0] out_o_sclrn,
    input wire clock,
    input wire resetn
    );

    wire [0:0] wait_pulse_extender_inst_o_sclrn;


    // wait_pulse_extender_inst(EXTIFACE,3)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .PIPE_DEPTH(0),
        .PULSE_EXTENSION(70),
        .USE_SYNCHRONIZER(0)
    ) thewait_pulse_extender_inst (
        .o_sclrn(wait_pulse_extender_inst_o_sclrn),
        .clk(clock),
        .i_resetn(resetn)
    );

    // out_o_sclrn(GPOUT,2)
    assign out_o_sclrn = wait_pulse_extender_inst_o_sclrn;

endmodule
