// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
// Legal Notice: Copyright 2022 Intel Corporation.  All rights reserved.
// Your use of  Intel Corporation's design tools,  logic functions and other
// software and  tools, and its AMPP partner logic functions, and any output
// files any  of the foregoing (including  device programming  or simulation
// files), and  any associated  documentation  or information  are expressly
// subject  to the terms and  conditions of the  Intel FPGA Software License
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement,  including,  without limitation,  that your use is for
// the  sole  purpose of  programming  logic devices  manufactured by  Intel
// and  sold by Intel  or its authorized  distributors. Please refer  to the
// applicable agreement for further details.
// ---------------------------------------------------------------------------

// SystemVerilog created from i_sfc_logic_s_c0_in_for_body20_c_compstrs_c0_enter7026_c_compstr0
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_i_sfc_logic_s_c0_in_for_body200000enter7026_c_compstr0 (
    output wire [0:0] out_pipeline_dummy_out,
    output wire [0:0] out_pipeline_forked_out,
    output wire [0:0] out_pipeline_valid_out,
    output wire [0:0] out_c0_exi10_0_tpl,
    output wire [0:0] out_c0_exi10_1_tpl,
    output wire [0:0] out_c0_exi10_2_tpl,
    output wire [0:0] out_c0_exi10_3_tpl,
    output wire [0:0] out_c0_exi10_4_tpl,
    output wire [0:0] out_c0_exi10_5_tpl,
    output wire [0:0] out_c0_exi10_6_tpl,
    output wire [0:0] out_c0_exi10_7_tpl,
    output wire [0:0] out_c0_exi10_8_tpl,
    output wire [0:0] out_c0_exi10_9_tpl,
    output wire [31:0] out_c0_exi10_10_tpl,
    output wire [0:0] out_c_compSTR_B5_current_iter_isspec,
    output wire [0:0] out_o_valid,
    input wire [0:0] in_buffer_in,
    input wire [0:0] in_c0_eni8_0_tpl,
    input wire [0:0] in_c0_eni8_1_tpl,
    input wire [0:0] in_c0_eni8_2_tpl,
    input wire [0:0] in_c0_eni8_3_tpl,
    input wire [0:0] in_c0_eni8_4_tpl,
    input wire [0:0] in_c0_eni8_5_tpl,
    input wire [0:0] in_c0_eni8_6_tpl,
    input wire [0:0] in_c0_eni8_7_tpl,
    input wire [31:0] in_c0_eni8_8_tpl,
    input wire [0:0] in_dummy_in,
    input wire [0:0] in_i_valid,
    output wire [0:0] out_exiting_valid_out,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    wire [7:0] bgTrunc_i_fpga_indvars_iv_next_c_compstr20_sel_x_b;
    wire [0:0] i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr4_mux_x_s;
    reg [0:0] i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr4_mux_x_q;
    wire [0:0] i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr0_i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr9_mux_x_s;
    reg [0:0] i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr0_i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr9_mux_x_q;
    wire [0:0] i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr11_mux_x_s;
    reg [0:0] i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr11_mux_x_q;
    wire [0:0] i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr10_mux_x_s;
    reg [0:0] i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr10_mux_x_q;
    wire [0:0] i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr0_i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr22_mux_x_s;
    reg [0:0] i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr0_i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr22_mux_x_q;
    wire [0:0] i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr0_i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr12_mux_x_s;
    reg [7:0] i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr0_i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr12_mux_x_q;
    wire [0:0] i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_adapt_scalar_trunc4_sel_x_b;
    wire [6:0] i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_c_i7_03_x_q;
    wire [7:0] i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_element_extension2_x_q;
    wire [0:0] i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_valid;
    wire i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_stall;
    wire i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_stall_bitsignaltemp;
    wire [7:0] i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_data;
    wire [7:0] i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_o_data;
    wire [0:0] i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q;
    wire [0:0] i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_adapt_scalar_trunc4_sel_x_b;
    wire [7:0] i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_element_extension2_x_q;
    wire [0:0] i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_valid;
    wire i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_stall;
    wire i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_stall_bitsignaltemp;
    wire [7:0] i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_data;
    wire [7:0] i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_o_data;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_adapt_scalar_trunc4_sel_x_b;
    wire [7:0] i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_element_extension2_x_q;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_valid;
    wire i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_stall;
    wire i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_stall_bitsignaltemp;
    wire [7:0] i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_data;
    wire [7:0] i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_o_data;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_adapt_scalar_trunc4_sel_x_b;
    wire [7:0] i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_element_extension2_x_q;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_valid;
    wire i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_stall;
    wire i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_stall_bitsignaltemp;
    wire [7:0] i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_data;
    wire [7:0] i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_o_data;
    wire [0:0] i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_adapt_scalar_trunc4_sel_x_b;
    wire [7:0] i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_element_extension2_x_q;
    wire [0:0] i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_valid;
    wire i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_stall;
    wire i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_stall_bitsignaltemp;
    wire [7:0] i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_data;
    wire [7:0] i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_o_data;
    wire [0:0] i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_valid;
    wire i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_stall;
    wire i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_stall_bitsignaltemp;
    wire [7:0] i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_data;
    wire [7:0] i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_o_data;
    wire [7:0] c_i8_12655_q;
    wire [7:0] c_i8_157_q;
    wire [0:0] i_c_compstr_b5_current_iter_isspec_c_compstr5_q;
    wire [0:0] i_c_compstr_b5_next_iter_isreal_c_compstr7_q;
    wire [8:0] i_fpga_indvars_iv_next_c_compstr20_a;
    wire [8:0] i_fpga_indvars_iv_next_c_compstr20_b;
    logic [8:0] i_fpga_indvars_iv_next_c_compstr20_o;
    wire [8:0] i_fpga_indvars_iv_next_c_compstr20_q;
    wire [0:0] i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out;
    wire [0:0] i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_data_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_exiting_valid_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_not_exitcond_stall_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_pipeline_dummy_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_pipeline_forked_out;
    wire [0:0] i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_pipeline_valid_out;
    wire [0:0] i_llvm_fpga_push_i1_notexitcond19_c_compstr19_out_feedback_out_4;
    wire [0:0] i_llvm_fpga_push_i1_notexitcond19_c_compstr19_out_feedback_valid_out_4;
    wire [0:0] i_notcmp16_c_compstr18_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg0_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg2_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg3_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg4_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg9_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg10_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg11_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg12_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg13_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg14_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg15_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg16_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg17_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg19_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg20_q;
    wire [0:0] i_exitcond_c_compstr13_cmp_nsign_q;
    reg [0:0] redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_q;
    reg [0:0] redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_delay_0;
    reg [0:0] redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_delay_1;
    reg [0:0] redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_delay_2;
    reg [0:0] redist1_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out_4_q;
    reg [0:0] redist1_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out_4_delay_0;
    reg [0:0] redist1_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out_4_delay_1;
    reg [0:0] redist1_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out_4_delay_2;
    reg [0:0] redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4_q;
    reg [0:0] redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4_delay_0;
    reg [0:0] redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4_delay_1;
    reg [0:0] redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4_delay_2;
    reg [0:0] redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4_q;
    reg [0:0] redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4_delay_0;
    reg [0:0] redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4_delay_1;
    reg [0:0] redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4_delay_2;
    reg [0:0] redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4_q;
    reg [0:0] redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4_delay_0;
    reg [0:0] redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4_delay_1;
    reg [0:0] redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4_delay_2;
    reg [0:0] redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4_q;
    reg [0:0] redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4_delay_0;
    reg [0:0] redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4_delay_1;
    reg [0:0] redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4_delay_2;
    reg [0:0] redist6_sync_together63_aunroll_x_in_c0_eni8_6_tpl_4_q;
    reg [0:0] redist6_sync_together63_aunroll_x_in_c0_eni8_6_tpl_4_delay_0;
    reg [0:0] redist6_sync_together63_aunroll_x_in_c0_eni8_6_tpl_4_delay_1;
    reg [0:0] redist6_sync_together63_aunroll_x_in_c0_eni8_6_tpl_4_delay_2;
    reg [0:0] redist7_sync_together63_aunroll_x_in_c0_eni8_7_tpl_4_q;
    reg [0:0] redist7_sync_together63_aunroll_x_in_c0_eni8_7_tpl_4_delay_0;
    reg [0:0] redist7_sync_together63_aunroll_x_in_c0_eni8_7_tpl_4_delay_1;
    reg [0:0] redist7_sync_together63_aunroll_x_in_c0_eni8_7_tpl_4_delay_2;
    reg [31:0] redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4_q;
    reg [31:0] redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4_delay_0;
    reg [31:0] redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4_delay_1;
    reg [0:0] redist9_sync_together63_aunroll_x_in_i_valid_2_q;
    reg [0:0] redist9_sync_together63_aunroll_x_in_i_valid_2_delay_0;
    reg [0:0] redist10_sync_together63_aunroll_x_in_i_valid_3_q;
    reg [0:0] redist11_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_q;
    reg [0:0] redist11_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_delay_0;
    reg [31:0] redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4_inputreg0_q;


    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // redist9_sync_together63_aunroll_x_in_i_valid_2(DELAY,132)
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist9_sync_together63_aunroll_x_in_i_valid_2_delay_0 <= '0;
        end
        else
        begin
            redist9_sync_together63_aunroll_x_in_i_valid_2_delay_0 <= $unsigned(in_i_valid);
        end
    end
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist9_sync_together63_aunroll_x_in_i_valid_2_q <= redist9_sync_together63_aunroll_x_in_i_valid_2_delay_0;
        end
    end

    // redist10_sync_together63_aunroll_x_in_i_valid_3(DELAY,133)
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist10_sync_together63_aunroll_x_in_i_valid_3_q <= '0;
        end
        else
        begin
            redist10_sync_together63_aunroll_x_in_i_valid_3_q <= $unsigned(redist9_sync_together63_aunroll_x_in_i_valid_2_q);
        end
    end

    // valid_fanout_reg2(REG,96)@3 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg2_q <= $unsigned(redist10_sync_together63_aunroll_x_in_i_valid_3_q);
        end
    end

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // valid_fanout_reg15(REG,109)@3 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg15_q <= $unsigned(redist10_sync_together63_aunroll_x_in_i_valid_3_q);
        end
    end

    // c_i8_12655(CONSTANT,80)
    assign c_i8_12655_q = $unsigned(8'b01111110);

    // c_i8_157(CONSTANT,81)
    assign c_i8_157_q = $unsigned(8'b11111111);

    // i_fpga_indvars_iv_next_c_compstr20(ADD,85)@4
    assign i_fpga_indvars_iv_next_c_compstr20_a = {1'b0, i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr0_i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr12_mux_x_q};
    assign i_fpga_indvars_iv_next_c_compstr20_b = {1'b0, c_i8_157_q};
    assign i_fpga_indvars_iv_next_c_compstr20_o = $unsigned(i_fpga_indvars_iv_next_c_compstr20_a) + $unsigned(i_fpga_indvars_iv_next_c_compstr20_b);
    assign i_fpga_indvars_iv_next_c_compstr20_q = i_fpga_indvars_iv_next_c_compstr20_o[8:0];

    // bgTrunc_i_fpga_indvars_iv_next_c_compstr20_sel_x(BITSELECT,2)@4
    assign bgTrunc_i_fpga_indvars_iv_next_c_compstr20_sel_x_b = i_fpga_indvars_iv_next_c_compstr20_q[7:0];

    // i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x(LOGICAL,18)@1
    assign i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q = ~ (GND_q);

    // valid_fanout_reg17(REG,111)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg17_q <= $unsigned(in_i_valid);
        end
    end

    // redist11_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2(DELAY,134)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist11_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_delay_0 <= $unsigned(i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q);
            redist11_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_q <= redist11_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_delay_0;
        end
    end

    // valid_fanout_reg16(REG,110)@2 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg16_q <= $unsigned(redist9_sync_together63_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x(FIFODELAY,43)@1 + 1
    // in i_valid@3
    // in i_write_pred@3
    // in i_data@4
    // out o_data@4
    assign i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_stall = ~ (valid_fanout_reg17_q & i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q);
    assign i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_valid = valid_fanout_reg16_q & redist11_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_data = bgTrunc_i_fpga_indvars_iv_next_c_compstr20_sel_x_b;
    assign i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_valid[0];
    assign i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(8),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x (
        .i_valid(i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_i_stall_bitsignaltemp),
        .i_data(bgTrunc_i_fpga_indvars_iv_next_c_compstr20_sel_x_b),
        .o_data(i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr0_i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr12_mux_x(MUX,12)@4
    assign i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr0_i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr12_mux_x_s = redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_q;
    always @(i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr0_i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr12_mux_x_s or i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_o_data or c_i8_12655_q)
    begin
        unique case (i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr0_i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr12_mux_x_s)
            1'b0 : i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr0_i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr12_mux_x_q = i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr0_i_llvm_fpga_push_i8_fpga_indvars_iv_push17_c_compstr1_x_o_data;
            1'b1 : i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr0_i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr12_mux_x_q = c_i8_12655_q;
            default : i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr0_i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr12_mux_x_q = 8'b0;
        endcase
    end

    // i_exitcond_c_compstr13_cmp_nsign(LOGICAL,122)@4
    assign i_exitcond_c_compstr13_cmp_nsign_q = $unsigned(~ (i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr0_i_llvm_fpga_pop_i8_fpga_indvars_iv_pop17_c_compstr12_mux_x_q[7:7]));

    // i_llvm_fpga_push_i1_notexitcond19_c_compstr19(BLACKBOX,89)@4
    // in in_empty_in@20000000
    // out out_feedback_out_4@20000000
    // out out_feedback_valid_out_4@20000000
    c_compSTR_i_llvm_fpga_push_i1_notexitcond19_c_compstr0 thei_llvm_fpga_push_i1_notexitcond19_c_compstr19 (
        .in_almost_empty_in(GND_q),
        .in_data_in(i_exitcond_c_compstr13_cmp_nsign_q),
        .in_empty_in(GND_q),
        .in_feedback_stall_in_4(i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_not_exitcond_stall_out),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg15_q),
        .out_data_out(),
        .out_feedback_out_4(i_llvm_fpga_push_i1_notexitcond19_c_compstr19_out_feedback_out_4),
        .out_feedback_valid_out_4(i_llvm_fpga_push_i1_notexitcond19_c_compstr19_out_feedback_valid_out_4),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2(BLACKBOX,86)@0
    // in in_stall_in@20000000
    c_compSTR_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr0 thei_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2 (
        .in_dummy_in(in_dummy_in),
        .in_stall_in(GND_q),
        .in_valid_in(in_i_valid),
        .out_dummy_out(i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist1_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out_4(DELAY,124)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out_4_delay_0 <= $unsigned(i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out);
            redist1_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out_4_delay_1 <= redist1_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out_4_delay_0;
            redist1_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out_4_delay_2 <= redist1_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out_4_delay_1;
            redist1_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out_4_q <= redist1_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out_4_delay_2;
        end
    end

    // i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3(BLACKBOX,87)@0
    // in in_stall_in@20000000
    c_compSTR_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr0 thei_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3 (
        .in_buffer_in(in_buffer_in),
        .in_stall_in(GND_q),
        .in_valid_in(in_i_valid),
        .out_buffer_out(i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4(DELAY,123)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_delay_0 <= $unsigned(i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out);
            redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_delay_1 <= redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_delay_0;
            redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_delay_2 <= redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_delay_1;
            redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_q <= redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_delay_2;
        end
    end

    // i_llvm_fpga_pipeline_keep_going18_c_compstr6(BLACKBOX,88)@4
    // out out_exiting_stall_out@20000000
    // out out_exiting_valid_out@20000000
    // out out_not_exitcond_stall_out@20000000
    // out out_pipeline_dummy_out@20000000
    // out out_pipeline_forked_out@20000000
    // out out_pipeline_valid_out@20000000
    c_compSTR_i_llvm_fpga_pipeline_keep_going18_c_compstr0 thei_llvm_fpga_pipeline_keep_going18_c_compstr6 (
        .in_data_in(redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_q),
        .in_dummy_in(redist1_i_llvm_fpga_dummy_thread_c_compstr_b5_dummy_c_compstr2_out_dummy_out_4_q),
        .in_forked_in(redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_q),
        .in_not_exitcond_in(i_llvm_fpga_push_i1_notexitcond19_c_compstr19_out_feedback_out_4),
        .in_not_exitcond_valid_in(i_llvm_fpga_push_i1_notexitcond19_c_compstr19_out_feedback_valid_out_4),
        .in_pipeline_stall_in(GND_q),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg2_q),
        .out_data_out(i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_data_out),
        .out_exiting_stall_out(),
        .out_exiting_valid_out(i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_exiting_valid_out),
        .out_not_exitcond_stall_out(i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_not_exitcond_stall_out),
        .out_pipeline_dummy_out(i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_pipeline_dummy_out),
        .out_pipeline_forked_out(i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_pipeline_forked_out),
        .out_pipeline_valid_out(i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_pipeline_valid_out),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_regfree_osync_x(GPOUT,4)
    assign out_pipeline_dummy_out = i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_pipeline_dummy_out;

    // dupName_1_regfree_osync_x(GPOUT,5)
    assign out_pipeline_forked_out = i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_pipeline_forked_out;

    // dupName_2_regfree_osync_x(GPOUT,6)
    assign out_pipeline_valid_out = i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_pipeline_valid_out;

    // valid_fanout_reg0(REG,94)@3 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg0_q <= $unsigned(redist10_sync_together63_aunroll_x_in_i_valid_3_q);
        end
    end

    // i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_c_i7_03_x(CONSTANT,15)
    assign i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_c_i7_03_x_q = $unsigned(7'b0000000);

    // i_c_compstr_b5_next_iter_isreal_c_compstr7(LOGICAL,83)@4
    assign i_c_compstr_b5_next_iter_isreal_c_compstr7_q = i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr4_mux_x_q & i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_data_out;

    // i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_element_extension2_x(BITJOIN,16)@4
    assign i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_element_extension2_x_q = {i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_c_i7_03_x_q, i_c_compstr_b5_next_iter_isreal_c_compstr7_q};

    // valid_fanout_reg4(REG,98)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg4_q <= $unsigned(in_i_valid);
        end
    end

    // valid_fanout_reg3(REG,97)@2 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg3_q <= $unsigned(redist9_sync_together63_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x(FIFODELAY,17)@1 + 1
    // in i_valid@3
    // in i_write_pred@3
    // in i_data@4
    // out o_data@4
    assign i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_stall = ~ (valid_fanout_reg4_q & i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q);
    assign i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_valid = valid_fanout_reg3_q & redist11_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_data = i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_element_extension2_x_q;
    assign i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_valid[0];
    assign i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(8),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x (
        .i_valid(i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_i_stall_bitsignaltemp),
        .i_data(i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_element_extension2_x_q),
        .o_data(i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_adapt_scalar_trunc4_sel_x(BITSELECT,13)@4
    assign i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_adapt_scalar_trunc4_sel_x_b = i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr1_x_o_data[0:0];

    // i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr4_mux_x(MUX,7)@4
    assign i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr4_mux_x_s = redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_q;
    always @(i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr4_mux_x_s or i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_adapt_scalar_trunc4_sel_x_b or VCC_q)
    begin
        unique case (i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr4_mux_x_s)
            1'b0 : i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr4_mux_x_q = i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_adapt_scalar_trunc4_sel_x_b;
            1'b1 : i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr4_mux_x_q = VCC_q;
            default : i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr4_mux_x_q = 1'b0;
        endcase
    end

    // i_c_compstr_b5_current_iter_isspec_c_compstr5(LOGICAL,82)@4
    assign i_c_compstr_b5_current_iter_isspec_c_compstr5_q = i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr0_i_llvm_fpga_pop_coalesce_i1_c_compstr_b5_current_iter_isreal_c_compstr4_mux_x_q ^ VCC_q;

    // redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4_inputreg0(DELAY,135)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4_inputreg0_q <= $unsigned(in_c0_eni8_8_tpl);
        end
    end

    // redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4(DELAY,131)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4_delay_0 <= $unsigned(redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4_inputreg0_q);
            redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4_delay_1 <= redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4_delay_0;
            redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4_q <= redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4_delay_1;
        end
    end

    // redist7_sync_together63_aunroll_x_in_c0_eni8_7_tpl_4(DELAY,130)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist7_sync_together63_aunroll_x_in_c0_eni8_7_tpl_4_delay_0 <= $unsigned(in_c0_eni8_7_tpl);
            redist7_sync_together63_aunroll_x_in_c0_eni8_7_tpl_4_delay_1 <= redist7_sync_together63_aunroll_x_in_c0_eni8_7_tpl_4_delay_0;
            redist7_sync_together63_aunroll_x_in_c0_eni8_7_tpl_4_delay_2 <= redist7_sync_together63_aunroll_x_in_c0_eni8_7_tpl_4_delay_1;
            redist7_sync_together63_aunroll_x_in_c0_eni8_7_tpl_4_q <= redist7_sync_together63_aunroll_x_in_c0_eni8_7_tpl_4_delay_2;
        end
    end

    // redist6_sync_together63_aunroll_x_in_c0_eni8_6_tpl_4(DELAY,129)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist6_sync_together63_aunroll_x_in_c0_eni8_6_tpl_4_delay_0 <= $unsigned(in_c0_eni8_6_tpl);
            redist6_sync_together63_aunroll_x_in_c0_eni8_6_tpl_4_delay_1 <= redist6_sync_together63_aunroll_x_in_c0_eni8_6_tpl_4_delay_0;
            redist6_sync_together63_aunroll_x_in_c0_eni8_6_tpl_4_delay_2 <= redist6_sync_together63_aunroll_x_in_c0_eni8_6_tpl_4_delay_1;
            redist6_sync_together63_aunroll_x_in_c0_eni8_6_tpl_4_q <= redist6_sync_together63_aunroll_x_in_c0_eni8_6_tpl_4_delay_2;
        end
    end

    // redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4(DELAY,128)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4_delay_0 <= $unsigned(in_c0_eni8_5_tpl);
            redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4_delay_1 <= redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4_delay_0;
            redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4_delay_2 <= redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4_delay_1;
            redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4_q <= redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4_delay_2;
        end
    end

    // i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_element_extension2_x(BITJOIN,40)@4
    assign i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_element_extension2_x_q = {i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_c_i7_03_x_q, i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr0_i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr22_mux_x_q};

    // valid_fanout_reg20(REG,114)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg20_q <= $unsigned(in_i_valid);
        end
    end

    // valid_fanout_reg19(REG,113)@2 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg19_q <= $unsigned(redist9_sync_together63_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x(FIFODELAY,41)@1 + 1
    // in i_valid@3
    // in i_write_pred@3
    // in i_data@4
    // out o_data@4
    assign i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_stall = ~ (valid_fanout_reg20_q & i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q);
    assign i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_valid = valid_fanout_reg19_q & redist11_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_data = i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_element_extension2_x_q;
    assign i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_valid[0];
    assign i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(8),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x (
        .i_valid(i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_i_stall_bitsignaltemp),
        .i_data(i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_element_extension2_x_q),
        .o_data(i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_adapt_scalar_trunc4_sel_x(BITSELECT,37)@4
    assign i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_adapt_scalar_trunc4_sel_x_b = i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr1_x_o_data[0:0];

    // i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr0_i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr22_mux_x(MUX,11)@4
    assign i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr0_i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr22_mux_x_s = redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_q;
    always @(i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr0_i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr22_mux_x_s or i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_adapt_scalar_trunc4_sel_x_b or redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4_q)
    begin
        unique case (i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr0_i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr22_mux_x_s)
            1'b0 : i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr0_i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr22_mux_x_q = i_llvm_fpga_push_i1_notcmp2138_push23_c_compstr0_adapt_scalar_trunc4_sel_x_b;
            1'b1 : i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr0_i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr22_mux_x_q = redist5_sync_together63_aunroll_x_in_c0_eni8_5_tpl_4_q;
            default : i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr0_i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr22_mux_x_q = 1'b0;
        endcase
    end

    // i_notcmp16_c_compstr18(LOGICAL,90)@4
    assign i_notcmp16_c_compstr18_q = i_exitcond_c_compstr13_cmp_nsign_q ^ VCC_q;

    // redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4(DELAY,127)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4_delay_0 <= $unsigned(in_c0_eni8_4_tpl);
            redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4_delay_1 <= redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4_delay_0;
            redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4_delay_2 <= redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4_delay_1;
            redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4_q <= redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4_delay_2;
        end
    end

    // i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_element_extension2_x(BITJOIN,28)@4
    assign i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_element_extension2_x_q = {i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_c_i7_03_x_q, i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr11_mux_x_q};

    // valid_fanout_reg12(REG,106)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg12_q <= $unsigned(in_i_valid);
        end
    end

    // valid_fanout_reg11(REG,105)@2 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg11_q <= $unsigned(redist9_sync_together63_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x(FIFODELAY,29)@1 + 1
    // in i_valid@3
    // in i_write_pred@3
    // in i_data@4
    // out o_data@4
    assign i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_stall = ~ (valid_fanout_reg12_q & i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q);
    assign i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_valid = valid_fanout_reg11_q & redist11_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_data = i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_element_extension2_x_q;
    assign i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_valid[0];
    assign i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(8),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x (
        .i_valid(i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_i_stall_bitsignaltemp),
        .i_data(i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_element_extension2_x_q),
        .o_data(i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_adapt_scalar_trunc4_sel_x(BITSELECT,25)@4
    assign i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_adapt_scalar_trunc4_sel_x_b = i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr1_x_o_data[0:0];

    // i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr11_mux_x(MUX,9)@4
    assign i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr11_mux_x_s = redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_q;
    always @(i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr11_mux_x_s or i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_adapt_scalar_trunc4_sel_x_b or redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4_q)
    begin
        unique case (i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr11_mux_x_s)
            1'b0 : i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr11_mux_x_q = i_llvm_fpga_push_i1_memdep_phi9_pop1033_push20_c_compstr0_adapt_scalar_trunc4_sel_x_b;
            1'b1 : i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr11_mux_x_q = redist4_sync_together63_aunroll_x_in_c0_eni8_4_tpl_4_q;
            default : i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr11_mux_x_q = 1'b0;
        endcase
    end

    // redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4(DELAY,126)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4_delay_0 <= $unsigned(in_c0_eni8_3_tpl);
            redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4_delay_1 <= redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4_delay_0;
            redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4_delay_2 <= redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4_delay_1;
            redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4_q <= redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4_delay_2;
        end
    end

    // i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_element_extension2_x(BITJOIN,34)@4
    assign i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_element_extension2_x_q = {i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_c_i7_03_x_q, i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr10_mux_x_q};

    // valid_fanout_reg14(REG,108)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg14_q <= $unsigned(in_i_valid);
        end
    end

    // valid_fanout_reg13(REG,107)@2 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg13_q <= $unsigned(redist9_sync_together63_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x(FIFODELAY,35)@1 + 1
    // in i_valid@3
    // in i_write_pred@3
    // in i_data@4
    // out o_data@4
    assign i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_stall = ~ (valid_fanout_reg14_q & i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q);
    assign i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_valid = valid_fanout_reg13_q & redist11_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_data = i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_element_extension2_x_q;
    assign i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_valid[0];
    assign i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(8),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x (
        .i_valid(i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_i_stall_bitsignaltemp),
        .i_data(i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_element_extension2_x_q),
        .o_data(i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_adapt_scalar_trunc4_sel_x(BITSELECT,31)@4
    assign i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_adapt_scalar_trunc4_sel_x_b = i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr1_x_o_data[0:0];

    // i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr10_mux_x(MUX,10)@4
    assign i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr10_mux_x_s = redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_q;
    always @(i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr10_mux_x_s or i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_adapt_scalar_trunc4_sel_x_b or redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4_q)
    begin
        unique case (i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr10_mux_x_s)
            1'b0 : i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr10_mux_x_q = i_llvm_fpga_push_i1_memdep_phi_pop931_push19_c_compstr0_adapt_scalar_trunc4_sel_x_b;
            1'b1 : i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr10_mux_x_q = redist3_sync_together63_aunroll_x_in_c0_eni8_3_tpl_4_q;
            default : i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr10_mux_x_q = 1'b0;
        endcase
    end

    // redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4(DELAY,125)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4_delay_0 <= $unsigned(in_c0_eni8_1_tpl);
            redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4_delay_1 <= redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4_delay_0;
            redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4_delay_2 <= redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4_delay_1;
            redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4_q <= redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4_delay_2;
        end
    end

    // i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_element_extension2_x(BITJOIN,22)@4
    assign i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_element_extension2_x_q = {i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_c_i7_03_x_q, i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr0_i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr9_mux_x_q};

    // valid_fanout_reg10(REG,104)@0 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg10_q <= $unsigned(in_i_valid);
        end
    end

    // valid_fanout_reg9(REG,103)@2 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg9_q <= $unsigned(redist9_sync_together63_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x(FIFODELAY,23)@1 + 1
    // in i_valid@3
    // in i_write_pred@3
    // in i_data@4
    // out o_data@4
    assign i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_stall = ~ (valid_fanout_reg10_q & i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q);
    assign i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_valid = valid_fanout_reg9_q & redist11_i_llvm_fpga_push_i1_c_compstr_b5_next_iter_isreal_push_c_compstr0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_data = i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_element_extension2_x_q;
    assign i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_valid[0];
    assign i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(8),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x (
        .i_valid(i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_i_stall_bitsignaltemp),
        .i_data(i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_element_extension2_x_q),
        .o_data(i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_adapt_scalar_trunc4_sel_x(BITSELECT,19)@4
    assign i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_adapt_scalar_trunc4_sel_x_b = i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_i_llvm_fpga_push_i1_cmp2137_push22_c_compstr1_x_o_data[0:0];

    // i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr0_i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr9_mux_x(MUX,8)@4
    assign i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr0_i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr9_mux_x_s = redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_q;
    always @(i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr0_i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr9_mux_x_s or i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_adapt_scalar_trunc4_sel_x_b or redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4_q)
    begin
        unique case (i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr0_i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr9_mux_x_s)
            1'b0 : i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr0_i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr9_mux_x_q = i_llvm_fpga_push_i1_cmp2137_push22_c_compstr0_adapt_scalar_trunc4_sel_x_b;
            1'b1 : i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr0_i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr9_mux_x_q = redist2_sync_together63_aunroll_x_in_c0_eni8_1_tpl_4_q;
            default : i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr0_i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr9_mux_x_q = 1'b0;
        endcase
    end

    // sync_out_aunroll_x(GPOUT,46)@4
    assign out_c0_exi10_0_tpl = GND_q;
    assign out_c0_exi10_1_tpl = i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr0_i_llvm_fpga_pop_i1_cmp2137_pop22_c_compstr9_mux_x_q;
    assign out_c0_exi10_2_tpl = i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi_pop931_pop19_c_compstr10_mux_x_q;
    assign out_c0_exi10_3_tpl = i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr0_i_llvm_fpga_pop_i1_memdep_phi9_pop1033_pop20_c_compstr11_mux_x_q;
    assign out_c0_exi10_4_tpl = i_exitcond_c_compstr13_cmp_nsign_q;
    assign out_c0_exi10_5_tpl = i_notcmp16_c_compstr18_q;
    assign out_c0_exi10_6_tpl = i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr0_i_llvm_fpga_pop_i1_notcmp2138_pop23_c_compstr22_mux_x_q;
    assign out_c0_exi10_7_tpl = redist0_i_llvm_fpga_forked_c_compstr_b5_forked_c_compstr3_out_buffer_out_4_q;
    assign out_c0_exi10_8_tpl = redist6_sync_together63_aunroll_x_in_c0_eni8_6_tpl_4_q;
    assign out_c0_exi10_9_tpl = redist7_sync_together63_aunroll_x_in_c0_eni8_7_tpl_4_q;
    assign out_c0_exi10_10_tpl = redist8_sync_together63_aunroll_x_in_c0_eni8_8_tpl_4_q;
    assign out_c_compSTR_B5_current_iter_isspec = i_c_compstr_b5_current_iter_isspec_c_compstr5_q;
    assign out_o_valid = valid_fanout_reg0_q;

    // regfree_osync(GPOUT,92)
    assign out_exiting_valid_out = i_llvm_fpga_pipeline_keep_going18_c_compstr6_out_exiting_valid_out;

endmodule
