// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from bb_c_compSTR_B4
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_bb_B4 (
    input wire [0:0] in_c0_exe67201_0,
    input wire [0:0] in_stall_in_0,
    input wire [0:0] in_valid_in_0,
    output wire [0:0] out_stall_in_0,
    output wire [0:0] out_stall_out_0,
    output wire [0:0] out_valid_in_0,
    output wire [0:0] out_valid_out_0,
    input wire clock,
    input wire resetn
    );

    wire [0:0] bb_c_compSTR_B4_stall_region_out_almost_empty_out;
    wire [0:0] bb_c_compSTR_B4_stall_region_out_c0_exe67201;
    wire [0:0] bb_c_compSTR_B4_stall_region_out_empty_out;
    wire [0:0] bb_c_compSTR_B4_stall_region_out_stall_out;
    wire [0:0] bb_c_compSTR_B4_stall_region_out_valid_out;
    wire [0:0] c_compSTR_B4_branch_out_stall_out;
    wire [0:0] c_compSTR_B4_branch_out_valid_out_0;
    wire [0:0] c_compSTR_B4_merge_out_almost_empty_out;
    wire [0:0] c_compSTR_B4_merge_out_c0_exe67201;
    wire [0:0] c_compSTR_B4_merge_out_empty_out;
    wire [0:0] c_compSTR_B4_merge_out_stall_out_0;
    wire [0:0] c_compSTR_B4_merge_out_valid_out;
    reg [0:0] rst_sync_rst_sclrn;


    // out_stall_in_0(GPOUT,8)
    assign out_stall_in_0 = in_stall_in_0;

    // c_compSTR_B4_branch(BLACKBOX,3)
    c_compSTR_B4_branch thec_compSTR_B4_branch (
        .in_almost_empty_in(bb_c_compSTR_B4_stall_region_out_almost_empty_out),
        .in_c0_exe67201(bb_c_compSTR_B4_stall_region_out_c0_exe67201),
        .in_empty_in(bb_c_compSTR_B4_stall_region_out_empty_out),
        .in_stall_in_0(in_stall_in_0),
        .in_valid_in(bb_c_compSTR_B4_stall_region_out_valid_out),
        .out_stall_out(c_compSTR_B4_branch_out_stall_out),
        .out_valid_out_0(c_compSTR_B4_branch_out_valid_out_0),
        .clock(clock),
        .resetn(resetn)
    );

    // bb_c_compSTR_B4_stall_region(BLACKBOX,2)
    c_compSTR_bb_B4_stall_region thebb_c_compSTR_B4_stall_region (
        .in_almost_empty_in(c_compSTR_B4_merge_out_almost_empty_out),
        .in_c0_exe67201(c_compSTR_B4_merge_out_c0_exe67201),
        .in_empty_in(c_compSTR_B4_merge_out_empty_out),
        .in_stall_in(c_compSTR_B4_branch_out_stall_out),
        .in_valid_in(c_compSTR_B4_merge_out_valid_out),
        .out_almost_empty_out(bb_c_compSTR_B4_stall_region_out_almost_empty_out),
        .out_c0_exe67201(bb_c_compSTR_B4_stall_region_out_c0_exe67201),
        .out_empty_out(bb_c_compSTR_B4_stall_region_out_empty_out),
        .out_stall_out(bb_c_compSTR_B4_stall_region_out_stall_out),
        .out_valid_out(bb_c_compSTR_B4_stall_region_out_valid_out),
        .clock(clock),
        .resetn(resetn)
    );

    // c_compSTR_B4_merge(BLACKBOX,4)
    c_compSTR_B4_merge thec_compSTR_B4_merge (
        .in_c0_exe67201_0(in_c0_exe67201_0),
        .in_stall_in(bb_c_compSTR_B4_stall_region_out_stall_out),
        .in_valid_in_0(in_valid_in_0),
        .out_almost_empty_out(c_compSTR_B4_merge_out_almost_empty_out),
        .out_c0_exe67201(c_compSTR_B4_merge_out_c0_exe67201),
        .out_empty_out(c_compSTR_B4_merge_out_empty_out),
        .out_stall_out_0(c_compSTR_B4_merge_out_stall_out_0),
        .out_valid_out(c_compSTR_B4_merge_out_valid_out),
        .clock(clock),
        .resetn(resetn)
    );

    // out_stall_out_0(GPOUT,9)
    assign out_stall_out_0 = c_compSTR_B4_merge_out_stall_out_0;

    // out_valid_in_0(GPOUT,10)
    assign out_valid_in_0 = in_valid_in_0;

    // out_valid_out_0(GPOUT,11)
    assign out_valid_out_0 = c_compSTR_B4_branch_out_valid_out_0;

    // rst_sync(RESETSYNC,12)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
