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// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from i_iord_bl_ystream_unnamed_c_compstr2_c_compstr0
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_i_iord_bl_ystream_unnamed_c_compstr2_c_compstr0 (
    output wire [0:0] out_o_almost_empty,
    output wire [15:0] out_o_data_0_tpl,
    output wire [15:0] out_o_data_1_tpl,
    output wire [0:0] out_o_empty,
    output wire [0:0] out_o_valid,
    output wire [0:0] out_iord_bl_yStream_o_fifoready,
    input wire [31:0] in_iord_bl_yStream_i_fifodata,
    input wire [0:0] in_iord_bl_yStream_i_fifovalid,
    output wire [0:0] out_iord_bl_yStream_o_fifoalmost_full,
    input wire [0:0] in_i_stall,
    output wire [0:0] out_o_stall,
    input wire [0:0] in_almost_empty_in,
    input wire [0:0] in_c0_exe1715,
    input wire [0:0] in_empty_in,
    input wire [0:0] in_i_valid,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [31:0] c32_0_q;
    wire [31:0] iord_i_fifodata;
    wire [0:0] iord_i_fifoempty;
    wire iord_i_fifoempty_bitsignaltemp;
    wire [0:0] iord_i_fifoendofpacket;
    wire iord_i_fifoendofpacket_bitsignaltemp;
    wire [31:0] iord_i_fifosize;
    wire [0:0] iord_i_fifostartofpacket;
    wire iord_i_fifostartofpacket_bitsignaltemp;
    wire [0:0] iord_i_fifovalid;
    wire iord_i_fifovalid_bitsignaltemp;
    wire [0:0] iord_i_predicate;
    wire iord_i_predicate_bitsignaltemp;
    wire [0:0] iord_i_stall;
    wire iord_i_stall_bitsignaltemp;
    wire [0:0] iord_i_valid;
    wire iord_i_valid_bitsignaltemp;
    wire [0:0] iord_o_almost_empty;
    wire iord_o_almost_empty_bitsignaltemp;
    wire [31:0] iord_o_data;
    wire [0:0] iord_o_empty;
    wire iord_o_empty_bitsignaltemp;
    wire [0:0] iord_o_fifoalmost_full;
    wire iord_o_fifoalmost_full_bitsignaltemp;
    wire [0:0] iord_o_fifoready;
    wire iord_o_fifoready_bitsignaltemp;
    wire [0:0] iord_o_stall;
    wire iord_o_stall_bitsignaltemp;
    wire [0:0] iord_o_valid;
    wire iord_o_valid_bitsignaltemp;
    wire [31:0] iord_profile_total_fifo_size_incr;
    wire [15:0] ip_dsdk_adapt_bitselect2_b;
    wire [15:0] ip_dsdk_adapt_bitselect8_b;
    reg [0:0] rst_sync_rst_sclrn;


    // ip_dsdk_adapt_bitselect8(BITSELECT,12)
    assign ip_dsdk_adapt_bitselect8_b = iord_o_data[31:16];

    // ip_dsdk_adapt_bitselect2(BITSELECT,9)
    assign ip_dsdk_adapt_bitselect2_b = iord_o_data[15:0];

    // c32_0(CONSTANT,5)
    assign c32_0_q = $unsigned(32'b00000000000000000000000000000000);

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // iord(EXTIFACE,6)
    assign iord_i_fifodata = in_iord_bl_yStream_i_fifodata;
    assign iord_i_fifoempty = GND_q;
    assign iord_i_fifoendofpacket = GND_q;
    assign iord_i_fifosize = c32_0_q;
    assign iord_i_fifostartofpacket = GND_q;
    assign iord_i_fifovalid = in_iord_bl_yStream_i_fifovalid;
    assign iord_i_predicate = in_c0_exe1715;
    assign iord_i_stall = in_i_stall;
    assign iord_i_valid = in_i_valid;
    assign iord_i_fifoempty_bitsignaltemp = iord_i_fifoempty[0];
    assign iord_i_fifoendofpacket_bitsignaltemp = iord_i_fifoendofpacket[0];
    assign iord_i_fifostartofpacket_bitsignaltemp = iord_i_fifostartofpacket[0];
    assign iord_i_fifovalid_bitsignaltemp = iord_i_fifovalid[0];
    assign iord_i_predicate_bitsignaltemp = iord_i_predicate[0];
    assign iord_i_stall_bitsignaltemp = iord_i_stall[0];
    assign iord_i_valid_bitsignaltemp = iord_i_valid[0];
    assign iord_o_almost_empty[0] = iord_o_almost_empty_bitsignaltemp;
    assign iord_o_empty[0] = iord_o_empty_bitsignaltemp;
    assign iord_o_fifoalmost_full[0] = iord_o_fifoalmost_full_bitsignaltemp;
    assign iord_o_fifoready[0] = iord_o_fifoready_bitsignaltemp;
    assign iord_o_stall[0] = iord_o_stall_bitsignaltemp;
    assign iord_o_valid[0] = iord_o_valid_bitsignaltemp;
    hld_iord #(
        .ADD_CAPACITY_UPSTREAM(0),
        .ALMOST_EMPTY_CUTOFF_DOWNSTREAM(7),
        .ALMOST_FULL_CUTOFF_SIDEPATH(0),
        .ALMOST_FULL_CUTOFF_UPSTREAM(7),
        .CAPACITY_FROM_CHANNEL(0),
        .DISCONNECT_UPSTREAM(0),
        .INTER_KERNEL_PIPELINING(1),
        .STAGING_CAPACITY(0),
        .USE_STALL_LATENCY_SIDEPATH(0),
        .ALLOW_HIGH_SPEED_FIFO_USAGE(0),
        .ASYNC_RESET(0),
        .CUTPATHS(0),
        .DATA_WIDTH(32),
        .EMPTY_WIDTH(0),
        .NON_BLOCKING(0),
        .STALL_IN_EARLINESS_DOWNSTREAM(3),
        .SYNCHRONIZE_RESET(0),
        .USE_STALL_LATENCY_DOWNSTREAM(1),
        .USE_STALL_LATENCY_UPSTREAM(1)
    ) theiord (
        .i_fifodata(in_iord_bl_yStream_i_fifodata),
        .i_fifoempty(iord_i_fifoempty_bitsignaltemp),
        .i_fifoendofpacket(iord_i_fifoendofpacket_bitsignaltemp),
        .i_fifosize(c32_0_q),
        .i_fifostartofpacket(iord_i_fifostartofpacket_bitsignaltemp),
        .i_fifovalid(iord_i_fifovalid_bitsignaltemp),
        .i_predicate(iord_i_predicate_bitsignaltemp),
        .i_stall(iord_i_stall_bitsignaltemp),
        .i_valid(iord_i_valid_bitsignaltemp),
        .o_almost_empty(iord_o_almost_empty_bitsignaltemp),
        .o_data(iord_o_data),
        .o_empty(iord_o_empty_bitsignaltemp),
        .o_fifoalmost_full(iord_o_fifoalmost_full_bitsignaltemp),
        .o_fifoready(iord_o_fifoready_bitsignaltemp),
        .o_stall(iord_o_stall_bitsignaltemp),
        .o_valid(iord_o_valid_bitsignaltemp),
        .profile_total_fifo_size_incr(),
        .clock(clock),
        .resetn(rst_sync_rst_sclrn[0])
    );

    // dupName_0_sync_out_aunroll_x(GPOUT,2)@59
    assign out_o_almost_empty = iord_o_almost_empty;
    assign out_o_data_0_tpl = ip_dsdk_adapt_bitselect2_b;
    assign out_o_data_1_tpl = ip_dsdk_adapt_bitselect8_b;
    assign out_o_empty = iord_o_empty;
    assign out_o_valid = iord_o_valid;

    // dupName_0_regfree_osync_x(GPOUT,3)
    assign out_iord_bl_yStream_o_fifoready = iord_o_fifoready;

    // regfree_osync(GPOUT,17)
    assign out_iord_bl_yStream_o_fifoalmost_full = iord_o_fifoalmost_full;

    // sync_out(GPOUT,19)@20000000
    assign out_o_stall = iord_o_stall;

    // rst_sync(RESETSYNC,21)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
