// ------------------------------------------------------------------------- 
// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// Your use of  Intel Corporation's design tools,  logic functions and other
// software and  tools, and its AMPP partner logic functions, and any output
// files any  of the foregoing (including  device programming  or simulation
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement,  including,  without limitation,  that your use is for
// the  sole  purpose of  programming  logic devices  manufactured by  Intel
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// ---------------------------------------------------------------------------

// SystemVerilog created from i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_i_sfc_logic_s_c1_in_for_body200000_c1_enter_c_compstr0 (
    input wire [4095:0] in_memdep_17_c_compSTR_avm_readdata,
    input wire [0:0] in_memdep_17_c_compSTR_avm_writeack,
    input wire [0:0] in_memdep_17_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memdep_17_c_compSTR_avm_readdatavalid,
    output wire [31:0] out_memdep_17_c_compSTR_avm_address,
    output wire [0:0] out_memdep_17_c_compSTR_avm_enable,
    output wire [0:0] out_memdep_17_c_compSTR_avm_read,
    output wire [0:0] out_memdep_17_c_compSTR_avm_write,
    output wire [4095:0] out_memdep_17_c_compSTR_avm_writedata,
    output wire [511:0] out_memdep_17_c_compSTR_avm_byteenable,
    output wire [0:0] out_memdep_17_c_compSTR_avm_burstcount,
    output wire [0:0] out_o_valid,
    output wire [0:0] out_unnamed_c_compSTR3_0_tpl,
    output wire [0:0] out_unnamed_c_compSTR4,
    input wire [0:0] in_c1_eni8_0_tpl,
    input wire [31:0] in_c1_eni8_1_tpl,
    input wire [0:0] in_c1_eni8_2_tpl,
    input wire [15:0] in_c1_eni8_3_tpl,
    input wire [15:0] in_c1_eni8_4_tpl,
    input wire [0:0] in_c1_eni8_5_tpl,
    input wire [0:0] in_c1_eni8_6_tpl,
    input wire [15:0] in_c1_eni8_7_tpl,
    input wire [15:0] in_c1_eni8_8_tpl,
    input wire [0:0] in_c1_eni8_9_tpl,
    input wire [0:0] in_c1_eni8_10_tpl,
    input wire [0:0] in_i_valid,
    input wire [4095:0] in_memdep_5_c_compSTR_avm_readdata,
    input wire [0:0] in_memdep_5_c_compSTR_avm_writeack,
    input wire [0:0] in_memdep_5_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memdep_5_c_compSTR_avm_readdatavalid,
    output wire [31:0] out_memdep_5_c_compSTR_avm_address,
    output wire [0:0] out_memdep_5_c_compSTR_avm_enable,
    output wire [0:0] out_memdep_5_c_compSTR_avm_read,
    output wire [0:0] out_memdep_5_c_compSTR_avm_write,
    output wire [4095:0] out_memdep_5_c_compSTR_avm_writedata,
    output wire [511:0] out_memdep_5_c_compSTR_avm_byteenable,
    output wire [0:0] out_memdep_5_c_compSTR_avm_burstcount,
    input wire [0:0] in_flush,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    wire [31:0] bgTrunc_i_inc_c_compstr24_sel_x_b;
    wire [63:0] i_idxprom23_c_compstr3_sel_x_b;
    wire [63:0] i_idxprom_c_compstr10_sel_x_b;
    wire [31:0] i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_address;
    wire [0:0] i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_burstcount;
    wire [511:0] i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_byteenable;
    wire [0:0] i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_enable;
    wire [0:0] i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_read;
    wire [0:0] i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_write;
    wire [4095:0] i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_writedata;
    wire [31:0] i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_address;
    wire [0:0] i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_burstcount;
    wire [511:0] i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_byteenable;
    wire [0:0] i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_enable;
    wire [0:0] i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_read;
    wire [0:0] i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_write;
    wire [4095:0] i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_writedata;
    wire [0:0] i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr0_i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr2_mux_x_s;
    reg [31:0] i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr0_i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr2_mux_x_q;
    wire [0:0] i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr0_i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr9_mux_x_s;
    reg [31:0] i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr0_i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr9_mux_x_q;
    wire [0:0] i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_valid;
    wire i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_stall;
    wire i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_stall_bitsignaltemp;
    wire [31:0] i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_data;
    wire [31:0] i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_o_data;
    wire [0:0] i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x_q;
    wire [0:0] i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_valid;
    wire i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_valid_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_stall;
    wire i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_stall_bitsignaltemp;
    wire [31:0] i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_data;
    wire [31:0] i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_o_data;
    wire [12:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_trunc_sel_x_b;
    wire [12:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_2_trunc_sel_x_b;
    wire [12:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_3_trunc_sel_x_b;
    wire [12:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_5_trunc_sel_x_b;
    wire [13:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_add_x_a;
    wire [13:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_add_x_b;
    logic [13:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_add_x_o;
    wire [13:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_add_x_q;
    wire [10:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_narrow_x_b;
    wire [12:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_shift_join_x_q;
    wire [13:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_add_x_a;
    wire [13:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_add_x_b;
    logic [13:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_add_x_o;
    wire [13:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_add_x_q;
    wire [63:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_append_upper_bits_x_q;
    wire [1:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_c_i2_02_x_q;
    wire [8:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_c_i9_01_x_q;
    wire [3:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_narrow_x_b;
    wire [12:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_shift_join_x_q;
    wire [8:0] i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_dupName_0_trunc_sel_x_b;
    wire [8:0] i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_dupName_2_trunc_sel_x_b;
    wire [9:0] i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_add_x_a;
    wire [9:0] i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_add_x_b;
    logic [9:0] i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_add_x_o;
    wire [9:0] i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_add_x_q;
    wire [63:0] i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_append_upper_bits_x_q;
    wire [6:0] i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_narrow_x_b;
    wire [8:0] i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_shift_join_x_q;
    wire [63:0] c_c_compSTR_W_pmem_q;
    wire [63:0] c_c_compSTR_y_pmem_q;
    wire [31:0] c_i32_040_q;
    wire [31:0] c_i32_143_q;
    wire [63:0] i_idxprom23_c_compstr3_vt_join_q;
    wire [31:0] i_idxprom23_c_compstr3_vt_select_31_b;
    wire [63:0] i_idxprom_c_compstr10_vt_join_q;
    wire [31:0] i_idxprom_c_compstr10_vt_select_31_b;
    wire [32:0] i_inc_c_compstr24_a;
    wire [32:0] i_inc_c_compstr24_b;
    logic [32:0] i_inc_c_compstr24_o;
    wire [32:0] i_inc_c_compstr24_q;
    wire [63:0] i_memcoalesce_bitcast_c_compstr_fpgaunique_530_c_compstr13_vt_join_q;
    wire [61:0] i_memcoalesce_bitcast_c_compstr_fpgaunique_530_c_compstr13_vt_select_63_b;
    wire [63:0] i_memcoalesce_bitcast_c_compstr_fpgaunique_531_c_compstr22_vt_join_q;
    wire [61:0] i_memcoalesce_bitcast_c_compstr_fpgaunique_531_c_compstr22_vt_select_63_b;
    wire [63:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr20_vt_join_q;
    wire [61:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr20_vt_select_63_b;
    wire [63:0] i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr11_vt_join_q;
    wire [61:0] i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr11_vt_select_63_b;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg0_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg3_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg4_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg5_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg6_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg7_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg8_q;
    wire [12:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_trunc_sel_x_merged_bit_select_b;
    wire [50:0] i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_trunc_sel_x_merged_bit_select_c;
    wire [8:0] i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_trunc_sel_x_merged_bit_select_b;
    wire [54:0] i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_trunc_sel_x_merged_bit_select_c;
    reg [50:0] redist0_i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_trunc_sel_x_merged_bit_select_c_1_q;
    reg [31:0] redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_q;
    reg [31:0] redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_delay_0;
    reg [31:0] redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_delay_1;
    reg [0:0] redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4_q;
    reg [0:0] redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4_delay_0;
    reg [0:0] redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4_delay_1;
    reg [0:0] redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4_delay_2;
    reg [15:0] redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4_q;
    reg [15:0] redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4_delay_0;
    reg [15:0] redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4_delay_1;
    reg [15:0] redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4_q;
    reg [15:0] redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4_delay_0;
    reg [15:0] redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4_delay_1;
    reg [0:0] redist5_sync_together45_aunroll_x_in_c1_eni8_5_tpl_4_q;
    reg [0:0] redist5_sync_together45_aunroll_x_in_c1_eni8_5_tpl_4_delay_0;
    reg [0:0] redist5_sync_together45_aunroll_x_in_c1_eni8_5_tpl_4_delay_1;
    reg [0:0] redist5_sync_together45_aunroll_x_in_c1_eni8_5_tpl_4_delay_2;
    reg [0:0] redist6_sync_together45_aunroll_x_in_c1_eni8_6_tpl_4_q;
    reg [0:0] redist6_sync_together45_aunroll_x_in_c1_eni8_6_tpl_4_delay_0;
    reg [0:0] redist6_sync_together45_aunroll_x_in_c1_eni8_6_tpl_4_delay_1;
    reg [0:0] redist6_sync_together45_aunroll_x_in_c1_eni8_6_tpl_4_delay_2;
    reg [15:0] redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_q;
    reg [15:0] redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_delay_0;
    reg [15:0] redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_delay_1;
    reg [15:0] redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_q;
    reg [15:0] redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_delay_0;
    reg [15:0] redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_delay_1;
    reg [0:0] redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_q;
    reg [0:0] redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_delay_0;
    reg [0:0] redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_delay_1;
    reg [0:0] redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_delay_2;
    reg [0:0] redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_delay_3;
    reg [0:0] redist10_sync_together45_aunroll_x_in_i_valid_2_q;
    reg [0:0] redist10_sync_together45_aunroll_x_in_i_valid_2_delay_0;
    reg [0:0] redist11_sync_together45_aunroll_x_in_i_valid_3_q;
    reg [0:0] redist12_sync_together45_aunroll_x_in_i_valid_4_q;
    reg [0:0] redist13_sync_together45_aunroll_x_in_i_valid_5_q;
    reg [10:0] redist14_i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_narrow_x_b_1_q;
    reg [12:0] redist15_i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_2_trunc_sel_x_b_1_q;
    reg [0:0] redist16_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x_q_2_q;
    reg [0:0] redist16_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x_q_2_delay_0;
    reg [31:0] redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_inputreg0_q;
    reg [15:0] redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4_inputreg0_q;
    reg [15:0] redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4_inputreg0_q;
    reg [15:0] redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_inputreg0_q;
    reg [15:0] redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_outputreg0_q;
    reg [15:0] redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_inputreg0_q;
    reg [15:0] redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_outputreg0_q;


    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // redist10_sync_together45_aunroll_x_in_i_valid_2(DELAY,117)
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist10_sync_together45_aunroll_x_in_i_valid_2_delay_0 <= '0;
        end
        else
        begin
            redist10_sync_together45_aunroll_x_in_i_valid_2_delay_0 <= $unsigned(in_i_valid);
        end
    end
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist10_sync_together45_aunroll_x_in_i_valid_2_q <= redist10_sync_together45_aunroll_x_in_i_valid_2_delay_0;
        end
    end

    // redist11_sync_together45_aunroll_x_in_i_valid_3(DELAY,118)
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist11_sync_together45_aunroll_x_in_i_valid_3_q <= '0;
        end
        else
        begin
            redist11_sync_together45_aunroll_x_in_i_valid_3_q <= $unsigned(redist10_sync_together45_aunroll_x_in_i_valid_2_q);
        end
    end

    // redist12_sync_together45_aunroll_x_in_i_valid_4(DELAY,119)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist12_sync_together45_aunroll_x_in_i_valid_4_q <= $unsigned(redist11_sync_together45_aunroll_x_in_i_valid_3_q);
        end
    end

    // valid_fanout_reg4(REG,97)@63 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg4_q <= $unsigned(redist12_sync_together45_aunroll_x_in_i_valid_4_q);
        end
    end

    // redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5(DELAY,116)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_delay_0 <= $unsigned(in_c1_eni8_9_tpl);
            redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_delay_1 <= redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_delay_0;
            redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_delay_2 <= redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_delay_1;
            redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_delay_3 <= redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_delay_2;
            redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_q <= redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_delay_3;
        end
    end

    // c_c_compSTR_W_pmem(CONSTANT,52)
    assign c_c_compSTR_W_pmem_q = $unsigned(64'b0100000001000001000000000000000000000000000000000000000000000000);

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_trunc_sel_x_merged_bit_select(BITSELECT,105)@63
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_trunc_sel_x_merged_bit_select_b = c_c_compSTR_W_pmem_q[12:0];
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_trunc_sel_x_merged_bit_select_c = c_c_compSTR_W_pmem_q[63:13];

    // redist0_i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_trunc_sel_x_merged_bit_select_c_1(DELAY,107)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_trunc_sel_x_merged_bit_select_c_1_q <= $unsigned(i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_trunc_sel_x_merged_bit_select_c);
        end
    end

    // c_i32_040(CONSTANT,66)
    assign c_i32_040_q = $unsigned(32'b00000000000000000000000000000000);

    // c_i32_143(CONSTANT,67)
    assign c_i32_143_q = $unsigned(32'b00000000000000000000000000000001);

    // i_inc_c_compstr24(ADD,78)@63
    assign i_inc_c_compstr24_a = {1'b0, i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr0_i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr9_mux_x_q};
    assign i_inc_c_compstr24_b = {1'b0, c_i32_143_q};
    assign i_inc_c_compstr24_o = $unsigned(i_inc_c_compstr24_a) + $unsigned(i_inc_c_compstr24_b);
    assign i_inc_c_compstr24_q = i_inc_c_compstr24_o[32:0];

    // bgTrunc_i_inc_c_compstr24_sel_x(BITSELECT,2)@63
    assign bgTrunc_i_inc_c_compstr24_sel_x_b = i_inc_c_compstr24_q[31:0];

    // i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x(LOGICAL,12)@60
    assign i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x_q = ~ (GND_q);

    // valid_fanout_reg8(REG,101)@59 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg8_q <= $unsigned(in_i_valid);
        end
    end

    // redist16_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x_q_2(DELAY,123)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist16_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x_q_2_delay_0 <= $unsigned(i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x_q);
            redist16_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x_q_2_q <= redist16_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x_q_2_delay_0;
        end
    end

    // valid_fanout_reg7(REG,100)@61 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg7_q <= $unsigned(redist10_sync_together45_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x(FIFODELAY,14)@60 + 1
    // in i_valid@62
    // in i_write_pred@62
    // in i_data@63
    // out o_data@63
    assign i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_stall = ~ (valid_fanout_reg8_q & i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x_q);
    assign i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_valid = valid_fanout_reg7_q & redist16_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_data = bgTrunc_i_inc_c_compstr24_sel_x_b;
    assign i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_valid[0];
    assign i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(32),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x (
        .i_valid(i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_i_stall_bitsignaltemp),
        .i_data(bgTrunc_i_inc_c_compstr24_sel_x_b),
        .o_data(i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4(DELAY,109)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4_delay_0 <= $unsigned(in_c1_eni8_2_tpl);
            redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4_delay_1 <= redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4_delay_0;
            redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4_delay_2 <= redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4_delay_1;
            redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4_q <= redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4_delay_2;
        end
    end

    // i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr0_i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr9_mux_x(MUX,10)@63
    assign i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr0_i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr9_mux_x_s = redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4_q;
    always @(i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr0_i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr9_mux_x_s or i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_o_data or c_i32_040_q)
    begin
        unique case (i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr0_i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr9_mux_x_s)
            1'b0 : i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr0_i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr9_mux_x_q = i_llvm_fpga_push_i32_j_0286_push18_c_compstr0_i_llvm_fpga_push_i32_j_0286_push18_c_compstr1_x_o_data;
            1'b1 : i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr0_i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr9_mux_x_q = c_i32_040_q;
            default : i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr0_i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr9_mux_x_q = 32'b0;
        endcase
    end

    // i_idxprom_c_compstr10_sel_x(BITSELECT,6)@63
    assign i_idxprom_c_compstr10_sel_x_b = {32'b00000000000000000000000000000000, i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr0_i_llvm_fpga_pop_i32_j_0286_pop18_c_compstr9_mux_x_q[31:0]};

    // i_idxprom_c_compstr10_vt_select_31(BITSELECT,77)@63
    assign i_idxprom_c_compstr10_vt_select_31_b = i_idxprom_c_compstr10_sel_x_b[31:0];

    // i_idxprom_c_compstr10_vt_join(BITJOIN,76)@63
    assign i_idxprom_c_compstr10_vt_join_q = {c_i32_040_q, i_idxprom_c_compstr10_vt_select_31_b};

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_3_trunc_sel_x(BITSELECT,19)@63
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_3_trunc_sel_x_b = i_idxprom_c_compstr10_vt_join_q[12:0];

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_narrow_x(BITSELECT,22)@63
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_narrow_x_b = i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_3_trunc_sel_x_b[10:0];

    // redist14_i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_narrow_x_b_1(DELAY,121)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist14_i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_narrow_x_b_1_q <= $unsigned(i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_narrow_x_b);
        end
    end

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_shift_join_x(BITJOIN,23)@64
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_shift_join_x_q = {redist14_i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_narrow_x_b_1_q, i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_c_i2_02_x_q};

    // redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_inputreg0(DELAY,124)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_inputreg0_q <= $unsigned(in_c1_eni8_1_tpl);
        end
    end

    // redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4(DELAY,108)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_delay_0 <= $unsigned(redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_inputreg0_q);
            redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_delay_1 <= redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_delay_0;
            redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_q <= redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_delay_1;
        end
    end

    // valid_fanout_reg6(REG,99)@59 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg6_q <= $unsigned(in_i_valid);
        end
    end

    // valid_fanout_reg5(REG,98)@61 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg5_q <= $unsigned(redist10_sync_together45_aunroll_x_in_i_valid_2_q);
        end
    end

    // i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x(FIFODELAY,11)@60 + 1
    // in i_valid@62
    // in i_write_pred@62
    // in i_data@63
    // out o_data@63
    assign i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_stall = ~ (valid_fanout_reg6_q & i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x_q);
    assign i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_valid = valid_fanout_reg5_q & redist16_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_inv_pred_x_q_2_q;
    assign i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_data = i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr0_i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr2_mux_x_q;
    assign i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_valid_bitsignaltemp = i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_valid[0];
    assign i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_stall_bitsignaltemp = i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_stall[0];
    hld_fifo #(
        .DEPTH(1),
        .WIDTH(32),
        .STYLE("ll"),
        .ALMOST_FULL_CUTOFF(0),
        .ALMOST_EMPTY_CUTOFF(0),
        .USE_STALL_LATENCY_UPSTREAM(0),
        .USE_STALL_LATENCY_DOWNSTREAM(0),
        .RESET_EXTERNALLY_HELD(1),
        .ASYNC_RESET(0),
        .SYNCHRONIZE_RESET(0),
        .NEVER_OVERFLOWS(1),
        .INITIAL_OCCUPANCY(1),
        .WRITE_AND_READ_DURING_FULL(1),
        .STALL_IN_EARLINESS(3),
        .VALID_IN_EARLINESS(1)
    ) thei_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x (
        .i_valid(i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_valid_bitsignaltemp),
        .i_stall(i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_i_stall_bitsignaltemp),
        .i_data(i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr0_i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr2_mux_x_q),
        .o_data(i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_o_data),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr0_i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr2_mux_x(MUX,9)@63
    assign i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr0_i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr2_mux_x_s = redist2_sync_together45_aunroll_x_in_c1_eni8_2_tpl_4_q;
    always @(i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr0_i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr2_mux_x_s or i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_o_data or redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_q)
    begin
        unique case (i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr0_i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr2_mux_x_s)
            1'b0 : i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr0_i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr2_mux_x_q = i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr0_i_llvm_fpga_push_i32_i_0288_pop1236_push21_c_compstr1_x_o_data;
            1'b1 : i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr0_i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr2_mux_x_q = redist1_sync_together45_aunroll_x_in_c1_eni8_1_tpl_4_q;
            default : i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr0_i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr2_mux_x_q = 32'b0;
        endcase
    end

    // i_idxprom23_c_compstr3_sel_x(BITSELECT,5)@63
    assign i_idxprom23_c_compstr3_sel_x_b = {32'b00000000000000000000000000000000, i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr0_i_llvm_fpga_pop_i32_i_0288_pop1236_pop21_c_compstr2_mux_x_q[31:0]};

    // i_idxprom23_c_compstr3_vt_select_31(BITSELECT,73)@63
    assign i_idxprom23_c_compstr3_vt_select_31_b = i_idxprom23_c_compstr3_sel_x_b[31:0];

    // i_idxprom23_c_compstr3_vt_join(BITJOIN,72)@63
    assign i_idxprom23_c_compstr3_vt_join_q = {c_i32_040_q, i_idxprom23_c_compstr3_vt_select_31_b};

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_trunc_sel_x(BITSELECT,17)@63
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_trunc_sel_x_b = i_idxprom23_c_compstr3_vt_join_q[12:0];

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_narrow_x(BITSELECT,33)@63
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_narrow_x_b = i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_trunc_sel_x_b[3:0];

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_c_i9_01_x(CONSTANT,32)
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_c_i9_01_x_q = $unsigned(9'b000000000);

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_shift_join_x(BITJOIN,34)@63
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_shift_join_x_q = {i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_narrow_x_b, i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_c_i9_01_x_q};

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_add_x(ADD,29)@63
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_add_x_a = {1'b0, i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_trunc_sel_x_merged_bit_select_b};
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_add_x_b = {1'b0, i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_shift_join_x_q};
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_add_x_o = $unsigned(i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_add_x_a) + $unsigned(i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_add_x_b);
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_add_x_q = i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_add_x_o[13:0];

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_2_trunc_sel_x(BITSELECT,18)@63
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_2_trunc_sel_x_b = i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_add_x_q[12:0];

    // redist15_i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_2_trunc_sel_x_b_1(DELAY,122)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist15_i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_2_trunc_sel_x_b_1_q <= $unsigned(i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_2_trunc_sel_x_b);
        end
    end

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_add_x(ADD,21)@64
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_add_x_a = {1'b0, redist15_i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_2_trunc_sel_x_b_1_q};
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_add_x_b = {1'b0, i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_shift_join_x_q};
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_add_x_o = $unsigned(i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_add_x_a) + $unsigned(i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_add_x_b);
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_add_x_q = i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_add_x_o[13:0];

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_5_trunc_sel_x(BITSELECT,20)@64
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_5_trunc_sel_x_b = i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_0_add_x_q[12:0];

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_append_upper_bits_x(BITJOIN,30)@64
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_append_upper_bits_x_q = {redist0_i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_trunc_sel_x_merged_bit_select_c_1_q, i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_dupName_5_trunc_sel_x_b};

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr20_vt_select_63(BITSELECT,87)@64
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr20_vt_select_63_b = i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_append_upper_bits_x_q[63:2];

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr20_vt_join(BITJOIN,86)@64
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr20_vt_join_q = {i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr20_vt_select_63_b, i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_c_i2_02_x_q};

    // i_memcoalesce_bitcast_c_compstr_fpgaunique_531_c_compstr22_vt_select_63(BITSELECT,84)@64
    assign i_memcoalesce_bitcast_c_compstr_fpgaunique_531_c_compstr22_vt_select_63_b = i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr20_vt_join_q[63:2];

    // i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_c_i2_02_x(CONSTANT,31)
    assign i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_c_i2_02_x_q = $unsigned(2'b00);

    // i_memcoalesce_bitcast_c_compstr_fpgaunique_531_c_compstr22_vt_join(BITJOIN,83)@64
    assign i_memcoalesce_bitcast_c_compstr_fpgaunique_531_c_compstr22_vt_join_q = {i_memcoalesce_bitcast_c_compstr_fpgaunique_531_c_compstr22_vt_select_63_b, i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_c_i2_02_x_q};

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_inputreg0(DELAY,129)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_inputreg0_q <= $unsigned(in_c1_eni8_8_tpl);
        end
    end

    // redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5(DELAY,115)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_delay_0 <= $unsigned(redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_inputreg0_q);
            redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_delay_1 <= redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_delay_0;
            redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_q <= redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_delay_1;
        end
    end

    // redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_outputreg0(DELAY,130)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_outputreg0_q <= $unsigned(redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_q);
        end
    end

    // redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_inputreg0(DELAY,127)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_inputreg0_q <= $unsigned(in_c1_eni8_7_tpl);
        end
    end

    // redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5(DELAY,114)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_delay_0 <= $unsigned(redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_inputreg0_q);
            redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_delay_1 <= redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_delay_0;
            redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_q <= redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_delay_1;
        end
    end

    // redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_outputreg0(DELAY,128)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_outputreg0_q <= $unsigned(redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_q);
        end
    end

    // i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x(BLACKBOX,7)@64
    // out out_memdep_17_c_compSTR_avm_address@20000000
    // out out_memdep_17_c_compSTR_avm_burstcount@20000000
    // out out_memdep_17_c_compSTR_avm_byteenable@20000000
    // out out_memdep_17_c_compSTR_avm_enable@20000000
    // out out_memdep_17_c_compSTR_avm_read@20000000
    // out out_memdep_17_c_compSTR_avm_write@20000000
    // out out_memdep_17_c_compSTR_avm_writedata@20000000
    // out out_o_almost_empty@65
    // out out_o_empty@65
    // out out_o_stall@65
    // out out_o_valid@65
    // out out_o_writeack@65
    c_compSTR_i_llvm_fpga_mem_memdep_17_c_compstr0 thei_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x (
        .in_i_writedata_0_tpl(redist7_sync_together45_aunroll_x_in_c1_eni8_7_tpl_5_outputreg0_q),
        .in_i_writedata_1_tpl(redist8_sync_together45_aunroll_x_in_c1_eni8_8_tpl_5_outputreg0_q),
        .in_almost_empty_in(GND_q),
        .in_empty_in(GND_q),
        .in_flush(in_flush),
        .in_i_address(i_memcoalesce_bitcast_c_compstr_fpgaunique_531_c_compstr22_vt_join_q),
        .in_i_dependence(redist9_sync_together45_aunroll_x_in_c1_eni8_9_tpl_5_q),
        .in_i_predicate(GND_q),
        .in_i_stall(GND_q),
        .in_i_valid(valid_fanout_reg4_q),
        .in_memdep_17_c_compSTR_avm_readdata(in_memdep_17_c_compSTR_avm_readdata),
        .in_memdep_17_c_compSTR_avm_readdatavalid(in_memdep_17_c_compSTR_avm_readdatavalid),
        .in_memdep_17_c_compSTR_avm_waitrequest(in_memdep_17_c_compSTR_avm_waitrequest),
        .in_memdep_17_c_compSTR_avm_writeack(in_memdep_17_c_compSTR_avm_writeack),
        .out_memdep_17_c_compSTR_avm_address(i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_address),
        .out_memdep_17_c_compSTR_avm_burstcount(i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_burstcount),
        .out_memdep_17_c_compSTR_avm_byteenable(i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_byteenable),
        .out_memdep_17_c_compSTR_avm_enable(i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_enable),
        .out_memdep_17_c_compSTR_avm_read(i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_read),
        .out_memdep_17_c_compSTR_avm_write(i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_write),
        .out_memdep_17_c_compSTR_avm_writedata(i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_writedata),
        .out_o_almost_empty(),
        .out_o_empty(),
        .out_o_stall(),
        .out_o_valid(),
        .out_o_writeack(),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_ext_sig_sync_out_x(GPOUT,4)
    assign out_memdep_17_c_compSTR_avm_address = i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_address;
    assign out_memdep_17_c_compSTR_avm_enable = i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_enable;
    assign out_memdep_17_c_compSTR_avm_read = i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_read;
    assign out_memdep_17_c_compSTR_avm_write = i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_write;
    assign out_memdep_17_c_compSTR_avm_writedata = i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_writedata;
    assign out_memdep_17_c_compSTR_avm_byteenable = i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_byteenable;
    assign out_memdep_17_c_compSTR_avm_burstcount = i_llvm_fpga_mem_memdep_17_c_compstr23_aunroll_x_out_memdep_17_c_compSTR_avm_burstcount;

    // redist13_sync_together45_aunroll_x_in_i_valid_5(DELAY,120)
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist13_sync_together45_aunroll_x_in_i_valid_5_q <= '0;
        end
        else
        begin
            redist13_sync_together45_aunroll_x_in_i_valid_5_q <= $unsigned(redist12_sync_together45_aunroll_x_in_i_valid_4_q);
        end
    end

    // valid_fanout_reg0(REG,93)@64 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg0_q <= $unsigned(redist13_sync_together45_aunroll_x_in_i_valid_5_q);
        end
    end

    // sync_out_aunroll_x(GPOUT,49)@65
    assign out_o_valid = valid_fanout_reg0_q;
    assign out_unnamed_c_compSTR3_0_tpl = GND_q;
    assign out_unnamed_c_compSTR4 = GND_q;

    // valid_fanout_reg3(REG,96)@62 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg3_q <= $unsigned(redist11_sync_together45_aunroll_x_in_i_valid_3_q);
        end
    end

    // redist5_sync_together45_aunroll_x_in_c1_eni8_5_tpl_4(DELAY,112)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist5_sync_together45_aunroll_x_in_c1_eni8_5_tpl_4_delay_0 <= $unsigned(in_c1_eni8_5_tpl);
            redist5_sync_together45_aunroll_x_in_c1_eni8_5_tpl_4_delay_1 <= redist5_sync_together45_aunroll_x_in_c1_eni8_5_tpl_4_delay_0;
            redist5_sync_together45_aunroll_x_in_c1_eni8_5_tpl_4_delay_2 <= redist5_sync_together45_aunroll_x_in_c1_eni8_5_tpl_4_delay_1;
            redist5_sync_together45_aunroll_x_in_c1_eni8_5_tpl_4_q <= redist5_sync_together45_aunroll_x_in_c1_eni8_5_tpl_4_delay_2;
        end
    end

    // redist6_sync_together45_aunroll_x_in_c1_eni8_6_tpl_4(DELAY,113)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist6_sync_together45_aunroll_x_in_c1_eni8_6_tpl_4_delay_0 <= $unsigned(in_c1_eni8_6_tpl);
            redist6_sync_together45_aunroll_x_in_c1_eni8_6_tpl_4_delay_1 <= redist6_sync_together45_aunroll_x_in_c1_eni8_6_tpl_4_delay_0;
            redist6_sync_together45_aunroll_x_in_c1_eni8_6_tpl_4_delay_2 <= redist6_sync_together45_aunroll_x_in_c1_eni8_6_tpl_4_delay_1;
            redist6_sync_together45_aunroll_x_in_c1_eni8_6_tpl_4_q <= redist6_sync_together45_aunroll_x_in_c1_eni8_6_tpl_4_delay_2;
        end
    end

    // c_c_compSTR_y_pmem(CONSTANT,53)
    assign c_c_compSTR_y_pmem_q = $unsigned(64'b0100000001000000000000000000000000000000000000000000000000000000);

    // i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_trunc_sel_x_merged_bit_select(BITSELECT,106)@63
    assign i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_trunc_sel_x_merged_bit_select_b = c_c_compSTR_y_pmem_q[8:0];
    assign i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_trunc_sel_x_merged_bit_select_c = c_c_compSTR_y_pmem_q[63:9];

    // i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_dupName_0_trunc_sel_x(BITSELECT,37)@63
    assign i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_dupName_0_trunc_sel_x_b = i_idxprom_c_compstr10_vt_join_q[8:0];

    // i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_narrow_x(BITSELECT,45)@63
    assign i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_narrow_x_b = i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_dupName_0_trunc_sel_x_b[6:0];

    // i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_shift_join_x(BITJOIN,46)@63
    assign i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_shift_join_x_q = {i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_narrow_x_b, i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_c_i2_02_x_q};

    // i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_add_x(ADD,42)@63
    assign i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_add_x_a = {1'b0, i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_trunc_sel_x_merged_bit_select_b};
    assign i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_add_x_b = {1'b0, i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_shift_join_x_q};
    assign i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_add_x_o = $unsigned(i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_add_x_a) + $unsigned(i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_add_x_b);
    assign i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_add_x_q = i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_add_x_o[9:0];

    // i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_dupName_2_trunc_sel_x(BITSELECT,38)@63
    assign i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_dupName_2_trunc_sel_x_b = i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_add_x_q[8:0];

    // i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_append_upper_bits_x(BITJOIN,43)@63
    assign i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_append_upper_bits_x_q = {i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_trunc_sel_x_merged_bit_select_c, i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_dupName_2_trunc_sel_x_b};

    // i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr11_vt_select_63(BITSELECT,90)@63
    assign i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr11_vt_select_63_b = i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr0_append_upper_bits_x_q[63:2];

    // i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr11_vt_join(BITJOIN,89)@63
    assign i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr11_vt_join_q = {i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr11_vt_select_63_b, i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_c_i2_02_x_q};

    // i_memcoalesce_bitcast_c_compstr_fpgaunique_530_c_compstr13_vt_select_63(BITSELECT,81)@63
    assign i_memcoalesce_bitcast_c_compstr_fpgaunique_530_c_compstr13_vt_select_63_b = i_ref_tmp_sroa_0_0_sroa_idx282_c_compstr11_vt_join_q[63:2];

    // i_memcoalesce_bitcast_c_compstr_fpgaunique_530_c_compstr13_vt_join(BITJOIN,80)@63
    assign i_memcoalesce_bitcast_c_compstr_fpgaunique_530_c_compstr13_vt_join_q = {i_memcoalesce_bitcast_c_compstr_fpgaunique_530_c_compstr13_vt_select_63_b, i_ref_tmp22_sroa_0_0_sroa_idx1_c_compstr0_c_i2_02_x_q};

    // redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4_inputreg0(DELAY,126)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4_inputreg0_q <= $unsigned(in_c1_eni8_4_tpl);
        end
    end

    // redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4(DELAY,111)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4_delay_0 <= $unsigned(redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4_inputreg0_q);
            redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4_delay_1 <= redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4_delay_0;
            redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4_q <= redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4_delay_1;
        end
    end

    // redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4_inputreg0(DELAY,125)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4_inputreg0_q <= $unsigned(in_c1_eni8_3_tpl);
        end
    end

    // redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4(DELAY,110)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4_delay_0 <= $unsigned(redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4_inputreg0_q);
            redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4_delay_1 <= redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4_delay_0;
            redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4_q <= redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4_delay_1;
        end
    end

    // i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x(BLACKBOX,8)@63
    // out out_memdep_5_c_compSTR_avm_address@20000000
    // out out_memdep_5_c_compSTR_avm_burstcount@20000000
    // out out_memdep_5_c_compSTR_avm_byteenable@20000000
    // out out_memdep_5_c_compSTR_avm_enable@20000000
    // out out_memdep_5_c_compSTR_avm_read@20000000
    // out out_memdep_5_c_compSTR_avm_write@20000000
    // out out_memdep_5_c_compSTR_avm_writedata@20000000
    // out out_o_almost_empty@64
    // out out_o_empty@64
    // out out_o_stall@64
    // out out_o_valid@64
    // out out_o_writeack@64
    c_compSTR_i_llvm_fpga_mem_memdep_5_c_compstr0 thei_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x (
        .in_i_writedata_0_tpl(redist3_sync_together45_aunroll_x_in_c1_eni8_3_tpl_4_q),
        .in_i_writedata_1_tpl(redist4_sync_together45_aunroll_x_in_c1_eni8_4_tpl_4_q),
        .in_almost_empty_in(GND_q),
        .in_empty_in(GND_q),
        .in_flush(in_flush),
        .in_i_address(i_memcoalesce_bitcast_c_compstr_fpgaunique_530_c_compstr13_vt_join_q),
        .in_i_dependence(redist6_sync_together45_aunroll_x_in_c1_eni8_6_tpl_4_q),
        .in_i_predicate(redist5_sync_together45_aunroll_x_in_c1_eni8_5_tpl_4_q),
        .in_i_stall(GND_q),
        .in_i_valid(valid_fanout_reg3_q),
        .in_memdep_5_c_compSTR_avm_readdata(in_memdep_5_c_compSTR_avm_readdata),
        .in_memdep_5_c_compSTR_avm_readdatavalid(in_memdep_5_c_compSTR_avm_readdatavalid),
        .in_memdep_5_c_compSTR_avm_waitrequest(in_memdep_5_c_compSTR_avm_waitrequest),
        .in_memdep_5_c_compSTR_avm_writeack(in_memdep_5_c_compSTR_avm_writeack),
        .out_memdep_5_c_compSTR_avm_address(i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_address),
        .out_memdep_5_c_compSTR_avm_burstcount(i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_burstcount),
        .out_memdep_5_c_compSTR_avm_byteenable(i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_byteenable),
        .out_memdep_5_c_compSTR_avm_enable(i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_enable),
        .out_memdep_5_c_compSTR_avm_read(i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_read),
        .out_memdep_5_c_compSTR_avm_write(i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_write),
        .out_memdep_5_c_compSTR_avm_writedata(i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_writedata),
        .out_o_almost_empty(),
        .out_o_empty(),
        .out_o_stall(),
        .out_o_valid(),
        .out_o_writeack(),
        .clock(clock),
        .resetn(resetn)
    );

    // ext_sig_sync_out(GPOUT,69)
    assign out_memdep_5_c_compSTR_avm_address = i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_address;
    assign out_memdep_5_c_compSTR_avm_enable = i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_enable;
    assign out_memdep_5_c_compSTR_avm_read = i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_read;
    assign out_memdep_5_c_compSTR_avm_write = i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_write;
    assign out_memdep_5_c_compSTR_avm_writedata = i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_writedata;
    assign out_memdep_5_c_compSTR_avm_byteenable = i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_byteenable;
    assign out_memdep_5_c_compSTR_avm_burstcount = i_llvm_fpga_mem_memdep_5_c_compstr14_aunroll_x_out_memdep_5_c_compSTR_avm_burstcount;

endmodule
