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// SystemVerilog created from i_sfc_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr13
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_i_sfc_s_c1_in_for_body20_c_com0000c1_enter_c_compstr13 (
    output wire [0:0] out_almost_empty_out,
    output wire [0:0] out_c1_exit_0_tpl,
    output wire [0:0] out_empty_out,
    output wire [0:0] out_o_valid,
    output wire [0:0] out_memdep_17_c_compSTR_avm_burstcount,
    output wire [511:0] out_memdep_17_c_compSTR_avm_byteenable,
    output wire [0:0] out_memdep_17_c_compSTR_avm_enable,
    output wire [0:0] out_memdep_17_c_compSTR_avm_read,
    output wire [0:0] out_memdep_17_c_compSTR_avm_write,
    output wire [4095:0] out_memdep_17_c_compSTR_avm_writedata,
    output wire [31:0] out_memdep_5_c_compSTR_avm_address,
    output wire [0:0] out_memdep_5_c_compSTR_avm_burstcount,
    output wire [511:0] out_memdep_5_c_compSTR_avm_byteenable,
    output wire [0:0] out_memdep_5_c_compSTR_avm_enable,
    output wire [0:0] out_memdep_5_c_compSTR_avm_read,
    output wire [0:0] out_memdep_5_c_compSTR_avm_write,
    output wire [4095:0] out_memdep_5_c_compSTR_avm_writedata,
    input wire [0:0] in_almost_empty_in,
    input wire [0:0] in_c0_exe4718,
    input wire [0:0] in_c0_exe7721,
    input wire [0:0] in_c1_eni8_0_tpl,
    input wire [31:0] in_c1_eni8_1_tpl,
    input wire [0:0] in_c1_eni8_2_tpl,
    input wire [15:0] in_c1_eni8_3_tpl,
    input wire [15:0] in_c1_eni8_4_tpl,
    input wire [0:0] in_c1_eni8_5_tpl,
    input wire [0:0] in_c1_eni8_6_tpl,
    input wire [15:0] in_c1_eni8_7_tpl,
    input wire [15:0] in_c1_eni8_8_tpl,
    input wire [0:0] in_c1_eni8_9_tpl,
    input wire [0:0] in_c1_eni8_10_tpl,
    input wire [0:0] in_empty_in,
    input wire [0:0] in_i_valid,
    input wire [0:0] in_memdep_17_c_compSTR_avm_writeack,
    input wire [4095:0] in_memdep_5_c_compSTR_avm_readdata,
    input wire [0:0] in_memdep_5_c_compSTR_avm_readdatavalid,
    input wire [0:0] in_memdep_5_c_compSTR_avm_waitrequest,
    input wire [0:0] in_memdep_5_c_compSTR_avm_writeack,
    input wire [0:0] in_flush,
    input wire [4095:0] in_memdep_17_c_compSTR_avm_readdata,
    input wire [0:0] in_memdep_17_c_compSTR_avm_readdatavalid,
    input wire [0:0] in_memdep_17_c_compSTR_avm_waitrequest,
    output wire [31:0] out_memdep_17_c_compSTR_avm_address,
    input wire [0:0] in_i_stall,
    output wire [0:0] out_o_stall,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_data_out_0_tpl;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_almost_empty_out;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_empty_out;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_stall_entry;
    wire [0:0] i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_valid_out;
    wire [31:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_address;
    wire [0:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_burstcount;
    wire [511:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_byteenable;
    wire [0:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_enable;
    wire [0:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_read;
    wire [0:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_write;
    wire [4095:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_writedata;
    wire [31:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_address;
    wire [0:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_burstcount;
    wire [511:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_byteenable;
    wire [0:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_enable;
    wire [0:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_read;
    wire [0:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_write;
    wire [4095:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_writedata;
    wire [0:0] i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_o_valid;
    wire [0:0] input_accepted_and_q;
    reg [0:0] rst_sync_rst_sclrn;


    // i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x(BLACKBOX,17)@59
    // out out_unnamed_c_compSTR3_0_tpl@65
    // out out_memdep_17_c_compSTR_avm_address@20000000
    // out out_memdep_17_c_compSTR_avm_burstcount@20000000
    // out out_memdep_17_c_compSTR_avm_byteenable@20000000
    // out out_memdep_17_c_compSTR_avm_enable@20000000
    // out out_memdep_17_c_compSTR_avm_read@20000000
    // out out_memdep_17_c_compSTR_avm_write@20000000
    // out out_memdep_17_c_compSTR_avm_writedata@20000000
    // out out_memdep_5_c_compSTR_avm_address@20000000
    // out out_memdep_5_c_compSTR_avm_burstcount@20000000
    // out out_memdep_5_c_compSTR_avm_byteenable@20000000
    // out out_memdep_5_c_compSTR_avm_enable@20000000
    // out out_memdep_5_c_compSTR_avm_read@20000000
    // out out_memdep_5_c_compSTR_avm_write@20000000
    // out out_memdep_5_c_compSTR_avm_writedata@20000000
    // out out_o_valid@65
    // out out_unnamed_c_compSTR4@65
    c_compSTR_i_sfc_logic_s_c1_in_for_body200000_c1_enter_c_compstr0 thei_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x (
        .in_c1_eni8_0_tpl(in_c1_eni8_0_tpl),
        .in_c1_eni8_1_tpl(in_c1_eni8_1_tpl),
        .in_c1_eni8_2_tpl(in_c1_eni8_2_tpl),
        .in_c1_eni8_3_tpl(in_c1_eni8_3_tpl),
        .in_c1_eni8_4_tpl(in_c1_eni8_4_tpl),
        .in_c1_eni8_5_tpl(in_c1_eni8_5_tpl),
        .in_c1_eni8_6_tpl(in_c1_eni8_6_tpl),
        .in_c1_eni8_7_tpl(in_c1_eni8_7_tpl),
        .in_c1_eni8_8_tpl(in_c1_eni8_8_tpl),
        .in_c1_eni8_9_tpl(in_c1_eni8_9_tpl),
        .in_c1_eni8_10_tpl(in_c1_eni8_10_tpl),
        .in_flush(in_flush),
        .in_i_valid(input_accepted_and_q),
        .in_memdep_17_c_compSTR_avm_readdata(in_memdep_17_c_compSTR_avm_readdata),
        .in_memdep_17_c_compSTR_avm_readdatavalid(in_memdep_17_c_compSTR_avm_readdatavalid),
        .in_memdep_17_c_compSTR_avm_waitrequest(in_memdep_17_c_compSTR_avm_waitrequest),
        .in_memdep_17_c_compSTR_avm_writeack(in_memdep_17_c_compSTR_avm_writeack),
        .in_memdep_5_c_compSTR_avm_readdata(in_memdep_5_c_compSTR_avm_readdata),
        .in_memdep_5_c_compSTR_avm_readdatavalid(in_memdep_5_c_compSTR_avm_readdatavalid),
        .in_memdep_5_c_compSTR_avm_waitrequest(in_memdep_5_c_compSTR_avm_waitrequest),
        .in_memdep_5_c_compSTR_avm_writeack(in_memdep_5_c_compSTR_avm_writeack),
        .out_unnamed_c_compSTR3_0_tpl(),
        .out_memdep_17_c_compSTR_avm_address(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_address),
        .out_memdep_17_c_compSTR_avm_burstcount(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_burstcount),
        .out_memdep_17_c_compSTR_avm_byteenable(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_byteenable),
        .out_memdep_17_c_compSTR_avm_enable(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_enable),
        .out_memdep_17_c_compSTR_avm_read(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_read),
        .out_memdep_17_c_compSTR_avm_write(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_write),
        .out_memdep_17_c_compSTR_avm_writedata(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_writedata),
        .out_memdep_5_c_compSTR_avm_address(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_address),
        .out_memdep_5_c_compSTR_avm_burstcount(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_burstcount),
        .out_memdep_5_c_compSTR_avm_byteenable(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_byteenable),
        .out_memdep_5_c_compSTR_avm_enable(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_enable),
        .out_memdep_5_c_compSTR_avm_read(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_read),
        .out_memdep_5_c_compSTR_avm_write(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_write),
        .out_memdep_5_c_compSTR_avm_writedata(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_writedata),
        .out_o_valid(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_o_valid),
        .out_unnamed_c_compSTR4(),
        .clock(clock),
        .resetn(rst_sync_rst_sclrn[0])
    );

    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // input_accepted_and(LOGICAL,21)
    assign input_accepted_and_q = in_i_valid & VCC_q;

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x(BLACKBOX,16)@65
    // in in_mask_valid@20000000
    // in in_stall_in@20000000
    // out out_data_out_0_tpl@96
    // out out_almost_empty_out@96
    // out out_empty_out@96
    // out out_stall_entry@20000000
    // out out_valid_out@96
    c_compSTR_i_llvm_fpga_sfc_exit_s_c1_out_0000s_c1_exit_c_compstr0 thei_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x (
        .in_data_in_0_tpl(GND_q),
        .in_dec_pipelined_thread(in_c0_exe4718),
        .in_inc_pipelined_thread(in_c0_exe7721),
        .in_input_accepted(input_accepted_and_q),
        .in_mask_valid(GND_q),
        .in_stall_in(in_i_stall),
        .in_valid_in(i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_o_valid),
        .out_data_out_0_tpl(i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_data_out_0_tpl),
        .out_almost_empty_out(i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_almost_empty_out),
        .out_empty_out(i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_empty_out),
        .out_stall_entry(i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_stall_entry),
        .out_valid_out(i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_valid_out),
        .clock(clock),
        .resetn(rst_sync_rst_sclrn[0])
    );

    // dupName_0_sync_out_aunroll_x(GPOUT,2)@96
    assign out_almost_empty_out = i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_almost_empty_out;
    assign out_c1_exit_0_tpl = i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_data_out_0_tpl;
    assign out_empty_out = i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_empty_out;
    assign out_o_valid = i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_valid_out;

    // dupName_0_regfree_osync_x(GPOUT,3)
    assign out_memdep_17_c_compSTR_avm_burstcount = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_burstcount;

    // dupName_1_regfree_osync_x(GPOUT,4)
    assign out_memdep_17_c_compSTR_avm_byteenable = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_byteenable;

    // dupName_2_regfree_osync_x(GPOUT,5)
    assign out_memdep_17_c_compSTR_avm_enable = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_enable;

    // dupName_3_regfree_osync_x(GPOUT,6)
    assign out_memdep_17_c_compSTR_avm_read = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_read;

    // dupName_4_regfree_osync_x(GPOUT,7)
    assign out_memdep_17_c_compSTR_avm_write = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_write;

    // dupName_5_regfree_osync_x(GPOUT,8)
    assign out_memdep_17_c_compSTR_avm_writedata = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_writedata;

    // dupName_6_regfree_osync_x(GPOUT,9)
    assign out_memdep_5_c_compSTR_avm_address = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_address;

    // dupName_7_regfree_osync_x(GPOUT,10)
    assign out_memdep_5_c_compSTR_avm_burstcount = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_burstcount;

    // dupName_8_regfree_osync_x(GPOUT,11)
    assign out_memdep_5_c_compSTR_avm_byteenable = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_byteenable;

    // dupName_9_regfree_osync_x(GPOUT,12)
    assign out_memdep_5_c_compSTR_avm_enable = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_enable;

    // dupName_10_regfree_osync_x(GPOUT,13)
    assign out_memdep_5_c_compSTR_avm_read = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_read;

    // dupName_11_regfree_osync_x(GPOUT,14)
    assign out_memdep_5_c_compSTR_avm_write = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_write;

    // dupName_12_regfree_osync_x(GPOUT,15)
    assign out_memdep_5_c_compSTR_avm_writedata = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_5_c_compSTR_avm_writedata;

    // regfree_osync(GPOUT,31)
    assign out_memdep_17_c_compSTR_avm_address = i_sfc_logic_s_c1_in_for_body20_c_compstrs_c1_enter_c_compstr0_aunroll_x_out_memdep_17_c_compSTR_avm_address;

    // sync_out(GPOUT,33)@20000000
    assign out_o_stall = i_llvm_fpga_sfc_exit_s_c1_out_for_body20_c_compstrs_c1_exit_c_compstr1_aunroll_x_out_stall_entry;

    // rst_sync(RESETSYNC,34)
    acl_reset_handler #(
        .ASYNC_RESET(0),
        .USE_SYNCHRONIZER(1),
        .PULSE_EXTENSION(0),
        .PIPE_DEPTH(3),
        .DUPLICATE(1)
    ) therst_sync (
        .clk(clock),
        .i_resetn(resetn),
        .o_sclrn(rst_sync_rst_sclrn)
    );

endmodule
