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// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
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// SystemVerilog created from i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr0
// Created for function/kernel c_compSTR
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compSTR_i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr0 (
    output wire [0:0] out_almost_empty_out,
    output wire [0:0] out_data_out,
    output wire [0:0] out_empty_out,
    output wire [0:0] out_valid_out,
    input wire [0:0] in_feedback_stall_in_10,
    output wire [0:0] out_feedback_data_out_10,
    output wire [0:0] out_feedback_empty_out_10,
    output wire [0:0] out_feedback_almost_empty_out_10,
    input wire [0:0] in_stall_in,
    output wire [0:0] out_stall_out,
    input wire [0:0] in_almost_empty_in,
    input wire [0:0] in_data_in,
    input wire [0:0] in_empty_in,
    input wire [0:0] in_valid_in,
    input wire clock,
    input wire resetn
    );

    wire [0:0] adapt_scalar_trunc4_in;
    wire [0:0] adapt_scalar_trunc4_q;
    wire [6:0] c_i7_03_q;
    wire [7:0] element_extension2_q;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_data_in;
    wire i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_data_in_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_stall_in;
    wire i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_stall_in_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_stall_in;
    wire i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_stall_in_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_valid_in;
    wire i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_valid_in_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_almost_empty_out;
    wire i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_almost_empty_out_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_data_out;
    wire i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_data_out_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_empty_out;
    wire i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_empty_out_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_almost_empty_out;
    wire i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_almost_empty_out_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_data_out;
    wire i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_data_out_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_empty_out;
    wire i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_empty_out_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_stall_out;
    wire i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_stall_out_bitsignaltemp;
    wire [0:0] i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_valid_out;
    wire i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_valid_out_bitsignaltemp;


    // adapt_scalar_trunc4(ROUND,3)
    assign adapt_scalar_trunc4_in = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_data_out;
    assign adapt_scalar_trunc4_q = adapt_scalar_trunc4_in[0:0];

    // c_i7_03(CONSTANT,4)
    assign c_i7_03_q = $unsigned(7'b0000000);

    // element_extension2(BITJOIN,5)
    assign element_extension2_q = {c_i7_03_q, in_data_in};

    // i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1(EXTIFACE,8)
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_data_in = element_extension2_q[0:0];
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_stall_in = in_feedback_stall_in_10;
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_stall_in = in_stall_in;
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_valid_in = in_valid_in;
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_data_in_bitsignaltemp = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_data_in[0];
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_stall_in_bitsignaltemp = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_stall_in[0];
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_stall_in_bitsignaltemp = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_stall_in[0];
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_valid_in_bitsignaltemp = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_valid_in[0];
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_almost_empty_out[0] = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_almost_empty_out_bitsignaltemp;
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_data_out[0] = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_data_out_bitsignaltemp;
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_empty_out[0] = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_empty_out_bitsignaltemp;
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_almost_empty_out[0] = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_almost_empty_out_bitsignaltemp;
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_data_out[0] = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_data_out_bitsignaltemp;
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_empty_out[0] = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_empty_out_bitsignaltemp;
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_stall_out[0] = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_stall_out_bitsignaltemp;
    assign i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_valid_out[0] = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_valid_out_bitsignaltemp;
    acl_push_stall_latency_zero_width #(
        .DOWN_ALMOST_EMPTY_CUTOFF(4),
        .FIFO_DEPTH(2),
        .INITIAL_OCCUPANCY(1),
        .STYLE("COALESCE"),
        .UP_ALMOST_FULL_CUTOFF(4),
        .ALLOW_HIGH_SPEED_FIFO_USAGE(0),
        .ASYNC_RESET(0),
        .DATA_WIDTH(1),
        .NO_PREDICATION(1),
        .SYNCHRONIZE_RESET(0)
    ) thei_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1 (
        .data_in(i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_data_in_bitsignaltemp),
        .feedback_stall_in(i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_stall_in_bitsignaltemp),
        .stall_in(i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_stall_in_bitsignaltemp),
        .valid_in(i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_valid_in_bitsignaltemp),
        .almost_empty_out(i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_almost_empty_out_bitsignaltemp),
        .data_out(i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_data_out_bitsignaltemp),
        .empty_out(i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_empty_out_bitsignaltemp),
        .feedback_almost_empty_out(i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_almost_empty_out_bitsignaltemp),
        .feedback_data_out(i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_data_out_bitsignaltemp),
        .feedback_empty_out(i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_empty_out_bitsignaltemp),
        .stall_out(i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_stall_out_bitsignaltemp),
        .valid_out(i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_valid_out_bitsignaltemp),
        .clock(clock),
        .resetn(resetn)
    );

    // dupName_0_sync_out_x(GPOUT,2)@17
    assign out_almost_empty_out = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_almost_empty_out;
    assign out_data_out = adapt_scalar_trunc4_q;
    assign out_empty_out = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_empty_out;
    assign out_valid_out = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_valid_out;

    // feedback_sync_out(GPOUT,7)
    assign out_feedback_data_out_10 = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_data_out;
    assign out_feedback_empty_out_10 = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_empty_out;
    assign out_feedback_almost_empty_out_10 = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_feedback_almost_empty_out;

    // sync_out(GPOUT,10)@20000000
    assign out_stall_out = i_llvm_fpga_push_i1_memdep_phi_push9_c_compstr1_stall_out;

endmodule
