*******************************************************
 i++ debug log file                                    
 This file contains diagnostic information. Any errors 
 or unexpected behavior encountered when running i++   
 should be reported as bugs. Thank you.                
*******************************************************

Compiler Command: i++ -march=Arria10 --quartus-compile -ghdl part_1_implemented_using_memory_module.cpp -o part_1_implemented_using_memory_module

***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries.  Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at
http://fpgasoftware.intel.com/eula.
***************************************************************

2022.10.24.11:37:57 Info: Doing: qsys-script --script=design_v1.tcl --quartus-project=none
2022.10.24.11:38:00 Info: create_system design_v1
2022.10.24.11:38:00 Info: set_project_property HIDE_FROM_IP_CATALOG false
2022.10.24.11:38:00 Info: set_project_property DEVICE_FAMILY Arria10
2022.10.24.11:38:00 Info: Info: The device and speed grade is changed to the defaults of the device family, Arria10.
2022.10.24.11:38:00 Info: set_project_property DEVICE 10AX115U1F45I1SG
2022.10.24.11:38:00 Info: add_instance design_v1_internal_inst design_v1_internal
2022.10.24.11:38:01 Info: set_instance_property design_v1_internal_inst AUTO_EXPORT true
2022.10.24.11:38:01 Info: save_system design_v1.ip
***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries.  Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at
http://fpgasoftware.intel.com/eula.
***************************************************************

2022.10.24.11:38:06 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/design_v1_generation.rpt
2022.10.24.11:38:06 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:06 Info: Starting: Create HDL design files for synthesis
2022.10.24.11:38:06 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1.ip --synthesis=VERILOG --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1 --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:06 Info: design_v1: "Transforming system: design_v1"
2022.10.24.11:38:07 Info: design_v1: "Naming system components in system: design_v1"
2022.10.24.11:38:07 Info: design_v1: "Processing generation queue"
2022.10.24.11:38:07 Info: design_v1: "Generating: design_v1"
2022.10.24.11:38:07 Info: design_v1: "Generating: design_v1_internal"
2022.10.24.11:38:07 Info: design_v1: Done "design_v1" with 2 modules, 214 files
2022.10.24.11:38:07 Info: qsys-generate succeeded.
2022.10.24.11:38:07 Info: Finished: Create HDL design files for synthesis
2022.10.24.11:38:07 Info: Starting: IP-XACT
2022.10.24.11:38:07 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1.ip --synthesis=VERILOG --ipxact --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1 --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:07 Info: Finished: IP-XACT
***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries.  Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at
http://fpgasoftware.intel.com/eula.
***************************************************************

Generating qsys simulation system: tb
2022.10.24.11:38:08 Info: Doing: qsys-script --quartus-project=none --search-path=/opt/intelFPGA_pro/21.4/hls/ip/,.,../components/**/*,$ --script=/opt/intelFPGA_pro/21.4/hls/share/lib/tcl/hls_sim_generate_qsys.tcl --cmd=set quartus_pro 1; set num_reset_cycles 4; set sim_qsys tb; set component_list design_v1; set component_call_count_filename .
2022.10.24.11:38:11 Info: create_system tb
2022.10.24.11:38:11 Info: add_component clock_reset_inst clock_reset.ip hls_sim_clock_reset clock_reset
2022.10.24.11:38:12 Info: clock_reset_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:12 Info: load_component clock_reset_inst
2022.10.24.11:38:12 Info: set_component_parameter_value RESET_CYCLE_HOLD 4
2022.10.24.11:38:12 Info: save_component 
2022.10.24.11:38:13 Info: add_instance design_v1_inst altera_generic_component
2022.10.24.11:38:13 Info: load_instantiation design_v1_inst
2022.10.24.11:38:13 Info: set_instantiation_property IP_FILE ../components/design_v1/design_v1.ip
2022.10.24.11:38:13 Info: set_instantiation_property HDL_ENTITY_NAME design_v1
2022.10.24.11:38:13 Info: set_instantiation_property HDL_COMPILATION_LIBRARY design_v1
2022.10.24.11:38:13 Info: save_instantiation 
2022.10.24.11:38:13 Info: reload_component_footprint design_v1_inst
2022.10.24.11:38:13 Info: design_v1_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:13 Info: load_component design_v1_inst
2022.10.24.11:38:14 Info: get_component_assignment hls.compressed.name
2022.10.24.11:38:14 Info: add_component main_dpi_controller_inst main_dpi_controller.ip hls_sim_main_dpi_controller main_dpi_controller
2022.10.24.11:38:14 Info: main_dpi_controller_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:14 Info: load_component main_dpi_controller_inst
2022.10.24.11:38:14 Info: set_component_parameter_value NUM_COMPONENTS 1
2022.10.24.11:38:14 Info: set_component_parameter_value COMPONENT_NAMES_STR design_v1
2022.10.24.11:38:14 Info: save_component 
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.clock main_dpi_controller_inst.clock
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.clock2x main_dpi_controller_inst.clock2x
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.reset main_dpi_controller_inst.reset
2022.10.24.11:38:14 Info: add_connection main_dpi_controller_inst.reset_ctrl clock_reset_inst.reset_ctrl
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.clock design_v1_inst.clock
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.reset design_v1_inst.reset
2022.10.24.11:38:14 Info: get_instance_interfaces design_v1_inst
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst clock DESCRIPTION
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst clock CLASS_NAME
2022.10.24.11:38:14 Info: get_instance_interface_ports design_v1_inst clock
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst reset DESCRIPTION
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst reset CLASS_NAME
2022.10.24.11:38:14 Info: get_instance_interface_ports design_v1_inst reset
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst A DESCRIPTION
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst A CLASS_NAME
2022.10.24.11:38:14 Info: get_instance_interface_ports design_v1_inst A
2022.10.24.11:38:14 Info: load_component design_v1_inst
2022.10.24.11:38:14 Info: get_component_assignment hls.compressed.name
2022.10.24.11:38:14 Info: get_instance_interface_assignment design_v1_inst A hls.cosim.name
2022.10.24.11:38:14 Info: add_component stream_source_dpi_bfm_design_v1_A_inst sso_design_v1_A.ip hls_sim_stream_source_dpi_bfm sso_design_v1_A
2022.10.24.11:38:14 Info: stream_source_dpi_bfm_design_v1_A_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.clock stream_source_dpi_bfm_design_v1_A_inst.clock
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.clock2x stream_source_dpi_bfm_design_v1_A_inst.clock2x
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.reset stream_source_dpi_bfm_design_v1_A_inst.reset
2022.10.24.11:38:14 Info: get_instance_interface_port_property design_v1_inst A A_data WIDTH
2022.10.24.11:38:14 Info: get_instance_interface_ports design_v1_inst A
2022.10.24.11:38:14 Info: load_component stream_source_dpi_bfm_design_v1_A_inst
2022.10.24.11:38:14 Info: set_component_parameter_value STREAM_DATAWIDTH 64
2022.10.24.11:38:14 Info: set_component_parameter_value INTERFACE_NAME A
2022.10.24.11:38:14 Info: set_component_parameter_value COMPONENT_NAME design_v1
2022.10.24.11:38:14 Info: save_component 
2022.10.24.11:38:14 Info: get_instance_interface_parameter_value design_v1_inst A dataBitsPerSymbol
2022.10.24.11:38:14 Info: load_component stream_source_dpi_bfm_design_v1_A_inst
2022.10.24.11:38:14 Info: set_component_parameter_value STREAM_BITSPERSYMBOL 64
2022.10.24.11:38:14 Info: save_component 
2022.10.24.11:38:14 Info: get_instance_interface_parameter_value design_v1_inst A firstSymbolInHighOrderBits
2022.10.24.11:38:14 Info: load_component stream_source_dpi_bfm_design_v1_A_inst
2022.10.24.11:38:14 Info: set_component_parameter_value FIRST_SYMBOL_IN_HIGH_ORDER_BITS 0
2022.10.24.11:38:14 Info: save_component 
2022.10.24.11:38:14 Info: add_connection stream_source_dpi_bfm_design_v1_A_inst.source design_v1_inst.A
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst B DESCRIPTION
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst B CLASS_NAME
2022.10.24.11:38:14 Info: get_instance_interface_ports design_v1_inst B
2022.10.24.11:38:14 Info: load_component design_v1_inst
2022.10.24.11:38:14 Info: get_component_assignment hls.compressed.name
2022.10.24.11:38:14 Info: get_instance_interface_assignment design_v1_inst B hls.cosim.name
2022.10.24.11:38:14 Info: get_instance_interface_port_property design_v1_inst B B_data WIDTH
2022.10.24.11:38:14 Info: get_instance_interface_parameter_value design_v1_inst B readyLatency
2022.10.24.11:38:14 Info: get_instance_interface_ports design_v1_inst B
2022.10.24.11:38:14 Info: add_component stream_sink_dpi_bfm_design_v1_B_inst ssi_design_v1_B.ip hls_sim_stream_sink_dpi_bfm ssi_design_v1_B
2022.10.24.11:38:14 Info: stream_sink_dpi_bfm_design_v1_B_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.clock stream_sink_dpi_bfm_design_v1_B_inst.clock
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.clock2x stream_sink_dpi_bfm_design_v1_B_inst.clock2x
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.reset stream_sink_dpi_bfm_design_v1_B_inst.reset
2022.10.24.11:38:14 Info: load_component stream_sink_dpi_bfm_design_v1_B_inst
2022.10.24.11:38:14 Info: set_component_parameter_value STREAM_DATAWIDTH 64
2022.10.24.11:38:14 Info: set_component_parameter_value READY_LATENCY 0
2022.10.24.11:38:14 Info: set_component_parameter_value INTERFACE_NAME B
2022.10.24.11:38:14 Info: set_component_parameter_value COMPONENT_NAME design_v1
2022.10.24.11:38:14 Info: save_component 
2022.10.24.11:38:14 Info: get_instance_interface_parameter_value design_v1_inst B dataBitsPerSymbol
2022.10.24.11:38:14 Info: load_component stream_sink_dpi_bfm_design_v1_B_inst
2022.10.24.11:38:14 Info: set_component_parameter_value STREAM_BITSPERSYMBOL 64
2022.10.24.11:38:14 Info: save_component 
2022.10.24.11:38:14 Info: get_instance_interface_parameter_value design_v1_inst B firstSymbolInHighOrderBits
2022.10.24.11:38:14 Info: load_component stream_sink_dpi_bfm_design_v1_B_inst
2022.10.24.11:38:14 Info: set_component_parameter_value FIRST_SYMBOL_IN_HIGH_ORDER_BITS 0
2022.10.24.11:38:14 Info: save_component 
2022.10.24.11:38:14 Info: add_connection design_v1_inst.B stream_sink_dpi_bfm_design_v1_B_inst.sink
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst call DESCRIPTION
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst call CLASS_NAME
2022.10.24.11:38:14 Info: get_instance_interface_ports design_v1_inst call
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst return DESCRIPTION
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst return CLASS_NAME
2022.10.24.11:38:14 Info: get_instance_interface_ports design_v1_inst return
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst N DESCRIPTION
2022.10.24.11:38:14 Info: get_instance_interface_property design_v1_inst N CLASS_NAME
2022.10.24.11:38:14 Info: get_instance_interface_ports design_v1_inst N
2022.10.24.11:38:14 Info: load_component design_v1_inst
2022.10.24.11:38:14 Info: get_component_assignment hls.compressed.name
2022.10.24.11:38:14 Info: get_instance_interface_assignment design_v1_inst N hls.cosim.name
2022.10.24.11:38:14 Info: add_component stream_source_dpi_bfm_design_v1_N_inst sso_design_v1_N.ip hls_sim_stream_source_dpi_bfm sso_design_v1_N
2022.10.24.11:38:14 Info: stream_source_dpi_bfm_design_v1_N_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.clock stream_source_dpi_bfm_design_v1_N_inst.clock
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.clock2x stream_source_dpi_bfm_design_v1_N_inst.clock2x
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.reset stream_source_dpi_bfm_design_v1_N_inst.reset
2022.10.24.11:38:14 Info: get_instance_interface_port_property design_v1_inst N N WIDTH
2022.10.24.11:38:14 Info: load_component stream_source_dpi_bfm_design_v1_N_inst
2022.10.24.11:38:14 Info: set_component_parameter_value FORCE_STREAM_CONDUIT 1
2022.10.24.11:38:14 Info: set_component_parameter_value STREAM_DATAWIDTH 32
2022.10.24.11:38:14 Info: set_component_parameter_value INTERFACE_NAME N
2022.10.24.11:38:14 Info: set_component_parameter_value COMPONENT_NAME design_v1
2022.10.24.11:38:14 Info: save_component 
2022.10.24.11:38:14 Info: add_connection stream_source_dpi_bfm_design_v1_N_inst.source_data design_v1_inst.N
2022.10.24.11:38:14 Info: load_component design_v1_inst
2022.10.24.11:38:14 Info: get_component_assignment hls.cosim.name
2022.10.24.11:38:14 Info: load_component design_v1_inst
2022.10.24.11:38:14 Info: get_component_assignment hls.compressed.name
2022.10.24.11:38:14 Info: add_component component_dpi_controller_design_v1_inst dpic_design_v1.ip hls_sim_component_dpi_controller dpic_design_v1
2022.10.24.11:38:14 Info: component_dpi_controller_design_v1_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.clock component_dpi_controller_design_v1_inst.clock
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.clock2x component_dpi_controller_design_v1_inst.clock2x
2022.10.24.11:38:14 Info: add_connection clock_reset_inst.reset component_dpi_controller_design_v1_inst.reset
2022.10.24.11:38:14 Info: add_connection component_dpi_controller_design_v1_inst.component_call design_v1_inst.call
2022.10.24.11:38:14 Info: add_connection design_v1_inst.return component_dpi_controller_design_v1_inst.component_return
2022.10.24.11:38:14 Info: get_instance_interfaces design_v1_inst
2022.10.24.11:38:14 Info: load_component component_dpi_controller_design_v1_inst
2022.10.24.11:38:14 Info: set_component_parameter_value COMPONENT_NAME design_v1
2022.10.24.11:38:14 Info: save_component 
2022.10.24.11:38:14 Info: load_component component_dpi_controller_design_v1_inst
2022.10.24.11:38:14 Info: set_component_parameter_value COMPONENT_MANGLED_NAME _Z9design_v1RN3ihc9stream_inISt4pairIiiEJEEERNS_10stream_outIS2_JEEEi
2022.10.24.11:38:14 Info: save_component 
2022.10.24.11:38:14 Info: add_component design_v1_component_dpi_controller_bind_conduit_fanout_inst design_v1_cfan.ip avalon_conduit_fanout design_v1_cfan
2022.10.24.11:38:14 Info: design_v1_component_dpi_controller_bind_conduit_fanout_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:14 Info: load_component design_v1_component_dpi_controller_bind_conduit_fanout_inst
2022.10.24.11:38:15 Info: set_component_parameter_value numFanOut 3
2022.10.24.11:38:15 Info: save_component 
2022.10.24.11:38:15 Info: add_component design_v1_component_dpi_controller_enable_conduit_fanout_inst design_v1_en_cfan.ip avalon_conduit_fanout design_v1_en_cfan
2022.10.24.11:38:15 Info: design_v1_component_dpi_controller_enable_conduit_fanout_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:15 Info: load_component design_v1_component_dpi_controller_enable_conduit_fanout_inst
2022.10.24.11:38:15 Info: set_component_parameter_value numFanOut 3
2022.10.24.11:38:15 Info: save_component 
2022.10.24.11:38:15 Info: add_component design_v1_component_dpi_controller_implicit_ready_conduit_fanout_inst design_v1_ir_cfan.ip avalon_conduit_fanout design_v1_ir_cfan
2022.10.24.11:38:15 Info: design_v1_component_dpi_controller_implicit_ready_conduit_fanout_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:15 Info: load_component design_v1_component_dpi_controller_implicit_ready_conduit_fanout_inst
2022.10.24.11:38:15 Info: set_component_parameter_value numFanOut 1
2022.10.24.11:38:15 Info: save_component 
2022.10.24.11:38:15 Info: add_connection component_dpi_controller_design_v1_inst.read_implicit_streams design_v1_component_dpi_controller_implicit_ready_conduit_fanout_inst.in_conduit
2022.10.24.11:38:15 Info: add_connection component_dpi_controller_design_v1_inst.dpi_control_bind design_v1_component_dpi_controller_bind_conduit_fanout_inst.in_conduit
2022.10.24.11:38:15 Info: add_connection component_dpi_controller_design_v1_inst.dpi_control_enable design_v1_component_dpi_controller_enable_conduit_fanout_inst.in_conduit
2022.10.24.11:38:15 Info: add_component design_v1_component_dpi_controller_stream_active_concatenate_inst design_v1_osacat.ip avalon_concatenate_singlebit_conduits design_v1_osacat
2022.10.24.11:38:15 Info: design_v1_component_dpi_controller_stream_active_concatenate_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:15 Info: load_component design_v1_component_dpi_controller_stream_active_concatenate_inst
2022.10.24.11:38:15 Info: set_component_parameter_value multibit_width 1
2022.10.24.11:38:15 Info: save_component 
2022.10.24.11:38:15 Info: load_component component_dpi_controller_design_v1_inst
2022.10.24.11:38:15 Info: set_component_parameter_value COMPONENT_NUM_OUTPUT_STREAMS 1
2022.10.24.11:38:15 Info: save_component 
2022.10.24.11:38:15 Info: add_connection design_v1_component_dpi_controller_stream_active_concatenate_inst.out_conduit component_dpi_controller_design_v1_inst.dpi_control_stream_writes_active
2022.10.24.11:38:15 Info: get_instance_interfaces design_v1_inst
2022.10.24.11:38:15 Info: get_instance_interface_ports design_v1_inst clock
2022.10.24.11:38:15 Info: get_instance_interface_ports design_v1_inst reset
2022.10.24.11:38:15 Info: get_instance_interface_ports design_v1_inst A
2022.10.24.11:38:15 Info: get_instance_interface_property design_v1_inst A CLASS_NAME
2022.10.24.11:38:15 Info: add_connection design_v1_component_dpi_controller_bind_conduit_fanout_inst.out_conduit_0 stream_source_dpi_bfm_design_v1_A_inst.dpi_control_bind
2022.10.24.11:38:15 Info: add_connection design_v1_component_dpi_controller_enable_conduit_fanout_inst.out_conduit_0 stream_source_dpi_bfm_design_v1_A_inst.dpi_control_enable
2022.10.24.11:38:15 Info: get_instance_interface_ports design_v1_inst B
2022.10.24.11:38:15 Info: get_instance_interface_property design_v1_inst B CLASS_NAME
2022.10.24.11:38:15 Info: add_connection design_v1_component_dpi_controller_bind_conduit_fanout_inst.out_conduit_1 stream_sink_dpi_bfm_design_v1_B_inst.dpi_control_bind
2022.10.24.11:38:15 Info: add_connection design_v1_component_dpi_controller_enable_conduit_fanout_inst.out_conduit_1 stream_sink_dpi_bfm_design_v1_B_inst.dpi_control_enable
2022.10.24.11:38:15 Info: add_connection stream_sink_dpi_bfm_design_v1_B_inst.dpi_control_stream_active design_v1_component_dpi_controller_stream_active_concatenate_inst.in_conduit_0
2022.10.24.11:38:15 Info: get_instance_interface_ports design_v1_inst call
2022.10.24.11:38:15 Info: get_instance_interface_ports design_v1_inst return
2022.10.24.11:38:15 Info: get_instance_interface_ports design_v1_inst N
2022.10.24.11:38:15 Info: get_instance_interface_property design_v1_inst N CLASS_NAME
2022.10.24.11:38:15 Info: add_connection design_v1_component_dpi_controller_bind_conduit_fanout_inst.out_conduit_2 stream_source_dpi_bfm_design_v1_N_inst.dpi_control_bind
2022.10.24.11:38:15 Info: add_connection design_v1_component_dpi_controller_enable_conduit_fanout_inst.out_conduit_2 stream_source_dpi_bfm_design_v1_N_inst.dpi_control_enable
2022.10.24.11:38:15 Info: add_connection design_v1_component_dpi_controller_implicit_ready_conduit_fanout_inst.out_conduit_0 stream_source_dpi_bfm_design_v1_N_inst.source_ready
2022.10.24.11:38:15 Info: add_component split_component_start_inst sp_cstart.ip avalon_split_multibit_conduit sp_cstart
2022.10.24.11:38:15 Info: split_component_start_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:15 Info: load_component split_component_start_inst
2022.10.24.11:38:15 Info: set_component_parameter_value multibit_width 1
2022.10.24.11:38:15 Info: save_component 
2022.10.24.11:38:15 Info: add_connection main_dpi_controller_inst.component_enabled split_component_start_inst.in_conduit
2022.10.24.11:38:15 Info: add_connection split_component_start_inst.out_conduit_0 component_dpi_controller_design_v1_inst.component_enabled
2022.10.24.11:38:15 Info: add_component concatenate_component_done_inst cat_done.ip avalon_concatenate_singlebit_conduits cat_done
2022.10.24.11:38:15 Info: concatenate_component_done_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:15 Info: load_component concatenate_component_done_inst
2022.10.24.11:38:15 Info: set_component_parameter_value multibit_width 1
2022.10.24.11:38:15 Info: save_component 
2022.10.24.11:38:15 Info: add_connection concatenate_component_done_inst.out_conduit main_dpi_controller_inst.component_done
2022.10.24.11:38:15 Info: add_component concatenate_component_wait_for_stream_writes_inst cat_cwfsw.ip avalon_concatenate_singlebit_conduits cat_cwfsw
2022.10.24.11:38:15 Info: concatenate_component_wait_for_stream_writes_inst: Generic Component instance footprint reloaded.
2022.10.24.11:38:15 Info: load_component concatenate_component_wait_for_stream_writes_inst
2022.10.24.11:38:15 Info: set_component_parameter_value multibit_width 1
2022.10.24.11:38:15 Info: save_component 
2022.10.24.11:38:15 Info: add_connection concatenate_component_wait_for_stream_writes_inst.out_conduit main_dpi_controller_inst.component_wait_for_stream_writes
2022.10.24.11:38:15 Info: add_connection component_dpi_controller_design_v1_inst.component_done concatenate_component_done_inst.in_conduit_0
2022.10.24.11:38:15 Info: add_connection component_dpi_controller_design_v1_inst.component_wait_for_stream_writes concatenate_component_wait_for_stream_writes_inst.in_conduit_0
2022.10.24.11:38:15 Info: save_system tb.qsys
2022.10.24.11:38:15 Info: Info: All modules have been converted to Generic Components.
***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries.  Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at
http://fpgasoftware.intel.com/eula.
***************************************************************

2022.10.24.11:38:17 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:20 Info: Parallel IP Generation is enabled. 
2022.10.24.11:38:20 Info: Platform Designer will attempt to use 6 processors for parallel IP generation based on available number of processors and the total number of IP to be generated.
2022.10.24.11:38:20 Info: 
2022.10.24.11:38:20 Info: Starting: Platform Designer system generation
2022.10.24.11:38:32 Info: 
2022.10.24.11:38:32 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:32 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/design_v1_osacat_generation.rpt
2022.10.24.11:38:32 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:32 Info: Starting: Create simulation model
2022.10.24.11:38:32 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:32 Info: design_v1_osacat: "Transforming system: design_v1_osacat"
2022.10.24.11:38:32 Info: design_v1_osacat: "Naming system components in system: design_v1_osacat"
2022.10.24.11:38:32 Info: design_v1_osacat: "Processing generation queue"
2022.10.24.11:38:32 Info: design_v1_osacat: "Generating: design_v1_osacat"
2022.10.24.11:38:32 Info: design_v1_osacat: "Generating: design_v1_osacat_avalon_concatenate_singlebit_conduits_10_bjzeuhq"
2022.10.24.11:38:32 Info: design_v1_osacat: Done "design_v1_osacat" with 2 modules, 2 files
2022.10.24.11:38:32 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/sim/ directory:
2022.10.24.11:38:32 Info: common/vcs_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/sim/ directory:
2022.10.24.11:38:32 Info: common/modelsim_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/sim/ directory:
2022.10.24.11:38:32 Info: common/riviera_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/sim/ directory:
2022.10.24.11:38:32 Info: common/vcsmx_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/sim/ directory:
2022.10.24.11:38:32 Info: common/xcelium_files.tcl
2022.10.24.11:38:32 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/sim/.
2022.10.24.11:38:32 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:32 Info: qsys-generate succeeded.
2022.10.24.11:38:32 Info: Finished: Create simulation model
2022.10.24.11:38:32 Info: Starting: Create simulation script
2022.10.24.11:38:32 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/sim/ --use-relative-paths=true
2022.10.24.11:38:32 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/sim/ directory:
2022.10.24.11:38:32 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:32 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/sim/ directory:
2022.10.24.11:38:32 Info: mentor/msim_setup.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/sim/ directory:
2022.10.24.11:38:32 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/sim/ directory:
2022.10.24.11:38:32 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:32 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:32 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/sim/ directory:
2022.10.24.11:38:32 Info: xcelium/cds.lib
2022.10.24.11:38:32 Info: xcelium/hdl.var
2022.10.24.11:38:32 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:32 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:32 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_osacat/sim/.
2022.10.24.11:38:32 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:32 Info: Finished: Create simulation script
2022.10.24.11:38:32 Info: 
2022.10.24.11:38:32 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:32 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/clock_reset_generation.rpt
2022.10.24.11:38:32 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:32 Info: Starting: Create simulation model
2022.10.24.11:38:32 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:32 Info: clock_reset: "Transforming system: clock_reset"
2022.10.24.11:38:32 Info: clock_reset: "Naming system components in system: clock_reset"
2022.10.24.11:38:32 Info: clock_reset: "Processing generation queue"
2022.10.24.11:38:32 Info: clock_reset: "Generating: clock_reset"
2022.10.24.11:38:32 Info: clock_reset: "Generating: hls_sim_clock_reset"
2022.10.24.11:38:32 Info: clock_reset: Done "clock_reset" with 2 modules, 2 files
2022.10.24.11:38:32 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/sim/ directory:
2022.10.24.11:38:32 Info: common/modelsim_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/sim/ directory:
2022.10.24.11:38:32 Info: common/riviera_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/sim/ directory:
2022.10.24.11:38:32 Info: common/vcsmx_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/sim/ directory:
2022.10.24.11:38:32 Info: common/xcelium_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/sim/ directory:
2022.10.24.11:38:32 Info: common/vcs_files.tcl
2022.10.24.11:38:32 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/sim/.
2022.10.24.11:38:32 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:32 Info: qsys-generate succeeded.
2022.10.24.11:38:32 Info: Finished: Create simulation model
2022.10.24.11:38:32 Info: Starting: Create simulation script
2022.10.24.11:38:32 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/sim/ --use-relative-paths=true
2022.10.24.11:38:32 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/sim/ directory:
2022.10.24.11:38:32 Info: mentor/msim_setup.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/sim/ directory:
2022.10.24.11:38:32 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/sim/ directory:
2022.10.24.11:38:32 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:32 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:32 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/sim/ directory:
2022.10.24.11:38:32 Info: xcelium/cds.lib
2022.10.24.11:38:32 Info: xcelium/hdl.var
2022.10.24.11:38:32 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:32 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:32 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/sim/ directory:
2022.10.24.11:38:32 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:32 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/clock_reset/sim/.
2022.10.24.11:38:32 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:32 Info: Finished: Create simulation script
2022.10.24.11:38:32 Info: 
2022.10.24.11:38:32 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:32 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sp_cstart_generation.rpt
2022.10.24.11:38:32 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:32 Info: Starting: Create simulation model
2022.10.24.11:38:32 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:32 Info: sp_cstart: "Transforming system: sp_cstart"
2022.10.24.11:38:32 Info: sp_cstart: "Naming system components in system: sp_cstart"
2022.10.24.11:38:32 Info: sp_cstart: "Processing generation queue"
2022.10.24.11:38:32 Info: sp_cstart: "Generating: sp_cstart"
2022.10.24.11:38:32 Info: sp_cstart: "Generating: sp_cstart_avalon_split_multibit_conduit_10_dlmo3na"
2022.10.24.11:38:32 Info: sp_cstart: Done "sp_cstart" with 2 modules, 2 files
2022.10.24.11:38:32 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sim/ directory:
2022.10.24.11:38:32 Info: common/vcs_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sim/ directory:
2022.10.24.11:38:32 Info: common/modelsim_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sim/ directory:
2022.10.24.11:38:32 Info: common/riviera_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sim/ directory:
2022.10.24.11:38:32 Info: common/vcsmx_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sim/ directory:
2022.10.24.11:38:32 Info: common/xcelium_files.tcl
2022.10.24.11:38:32 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sim/.
2022.10.24.11:38:32 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:32 Info: qsys-generate succeeded.
2022.10.24.11:38:32 Info: Finished: Create simulation model
2022.10.24.11:38:32 Info: Starting: Create simulation script
2022.10.24.11:38:32 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sim/ --use-relative-paths=true
2022.10.24.11:38:32 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sim/ directory:
2022.10.24.11:38:32 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:32 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sim/ directory:
2022.10.24.11:38:32 Info: mentor/msim_setup.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sim/ directory:
2022.10.24.11:38:32 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sim/ directory:
2022.10.24.11:38:32 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:32 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:32 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sim/ directory:
2022.10.24.11:38:32 Info: xcelium/cds.lib
2022.10.24.11:38:32 Info: xcelium/hdl.var
2022.10.24.11:38:32 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:32 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:32 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sp_cstart/sim/.
2022.10.24.11:38:32 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:32 Info: Finished: Create simulation script
2022.10.24.11:38:32 Info: 
2022.10.24.11:38:32 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:32 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/design_v1_ir_cfan_generation.rpt
2022.10.24.11:38:32 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:32 Info: Starting: Create simulation model
2022.10.24.11:38:32 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:32 Info: design_v1_ir_cfan: "Transforming system: design_v1_ir_cfan"
2022.10.24.11:38:32 Info: design_v1_ir_cfan: "Naming system components in system: design_v1_ir_cfan"
2022.10.24.11:38:32 Info: design_v1_ir_cfan: "Processing generation queue"
2022.10.24.11:38:32 Info: design_v1_ir_cfan: "Generating: design_v1_ir_cfan"
2022.10.24.11:38:32 Info: design_v1_ir_cfan: "Generating: design_v1_ir_cfan_avalon_conduit_fanout_10_kjtx3wq"
2022.10.24.11:38:32 Info: design_v1_ir_cfan: Done "design_v1_ir_cfan" with 2 modules, 2 files
2022.10.24.11:38:32 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/sim/ directory:
2022.10.24.11:38:32 Info: common/vcs_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/sim/ directory:
2022.10.24.11:38:32 Info: common/modelsim_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/sim/ directory:
2022.10.24.11:38:32 Info: common/riviera_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/sim/ directory:
2022.10.24.11:38:32 Info: common/vcsmx_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/sim/ directory:
2022.10.24.11:38:32 Info: common/xcelium_files.tcl
2022.10.24.11:38:32 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/sim/.
2022.10.24.11:38:32 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:32 Info: qsys-generate succeeded.
2022.10.24.11:38:32 Info: Finished: Create simulation model
2022.10.24.11:38:32 Info: Starting: Create simulation script
2022.10.24.11:38:32 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/sim/ --use-relative-paths=true
2022.10.24.11:38:32 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/sim/ directory:
2022.10.24.11:38:32 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:32 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/sim/ directory:
2022.10.24.11:38:32 Info: mentor/msim_setup.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/sim/ directory:
2022.10.24.11:38:32 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/sim/ directory:
2022.10.24.11:38:32 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:32 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:32 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/sim/ directory:
2022.10.24.11:38:32 Info: xcelium/cds.lib
2022.10.24.11:38:32 Info: xcelium/hdl.var
2022.10.24.11:38:32 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:32 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:32 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_ir_cfan/sim/.
2022.10.24.11:38:32 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:32 Info: Finished: Create simulation script
2022.10.24.11:38:32 Info: 
2022.10.24.11:38:32 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:32 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/ssi_design_v1_B_generation.rpt
2022.10.24.11:38:32 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:32 Info: Starting: Create simulation model
2022.10.24.11:38:32 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:32 Info: ssi_design_v1_B: "Transforming system: ssi_design_v1_B"
2022.10.24.11:38:32 Info: ssi_design_v1_B: "Naming system components in system: ssi_design_v1_B"
2022.10.24.11:38:32 Info: ssi_design_v1_B: "Processing generation queue"
2022.10.24.11:38:32 Info: ssi_design_v1_B: "Generating: ssi_design_v1_B"
2022.10.24.11:38:32 Info: ssi_design_v1_B: "Generating: hls_sim_stream_sink_dpi_bfm"
2022.10.24.11:38:32 Info: ssi_design_v1_B: Done "ssi_design_v1_B" with 2 modules, 2 files
2022.10.24.11:38:32 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/sim/ directory:
2022.10.24.11:38:32 Info: common/xcelium_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/sim/ directory:
2022.10.24.11:38:32 Info: common/vcs_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/sim/ directory:
2022.10.24.11:38:32 Info: common/riviera_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/sim/ directory:
2022.10.24.11:38:32 Info: common/vcsmx_files.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/sim/ directory:
2022.10.24.11:38:32 Info: common/modelsim_files.tcl
2022.10.24.11:38:32 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/sim/.
2022.10.24.11:38:32 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:32 Info: qsys-generate succeeded.
2022.10.24.11:38:32 Info: Finished: Create simulation model
2022.10.24.11:38:32 Info: Starting: Create simulation script
2022.10.24.11:38:32 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/sim/ --use-relative-paths=true
2022.10.24.11:38:32 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/sim/ directory:
2022.10.24.11:38:32 Info: xcelium/cds.lib
2022.10.24.11:38:32 Info: xcelium/hdl.var
2022.10.24.11:38:32 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:32 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:32 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/sim/ directory:
2022.10.24.11:38:32 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:32 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/sim/ directory:
2022.10.24.11:38:32 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:32 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/sim/ directory:
2022.10.24.11:38:32 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:32 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:32 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/sim/ directory:
2022.10.24.11:38:32 Info: mentor/msim_setup.tcl
2022.10.24.11:38:32 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/ssi_design_v1_B/sim/.
2022.10.24.11:38:32 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:32 Info: Finished: Create simulation script
2022.10.24.11:38:33 Info: 
2022.10.24.11:38:33 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:33 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sso_design_v1_N_generation.rpt
2022.10.24.11:38:33 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:33 Info: Starting: Create simulation model
2022.10.24.11:38:33 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:33 Info: sso_design_v1_N: "Transforming system: sso_design_v1_N"
2022.10.24.11:38:33 Info: sso_design_v1_N: "Naming system components in system: sso_design_v1_N"
2022.10.24.11:38:33 Info: sso_design_v1_N: "Processing generation queue"
2022.10.24.11:38:33 Info: sso_design_v1_N: "Generating: sso_design_v1_N"
2022.10.24.11:38:33 Info: sso_design_v1_N: "Generating: hls_sim_stream_source_dpi_bfm"
2022.10.24.11:38:33 Info: sso_design_v1_N: Done "sso_design_v1_N" with 2 modules, 2 files
2022.10.24.11:38:33 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sim/ directory:
2022.10.24.11:38:33 Info: common/riviera_files.tcl
2022.10.24.11:38:33 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sim/ directory:
2022.10.24.11:38:33 Info: common/xcelium_files.tcl
2022.10.24.11:38:33 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sim/ directory:
2022.10.24.11:38:33 Info: common/modelsim_files.tcl
2022.10.24.11:38:33 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sim/ directory:
2022.10.24.11:38:33 Info: common/vcs_files.tcl
2022.10.24.11:38:33 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sim/ directory:
2022.10.24.11:38:33 Info: common/vcsmx_files.tcl
2022.10.24.11:38:33 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sim/.
2022.10.24.11:38:33 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:33 Info: qsys-generate succeeded.
2022.10.24.11:38:33 Info: Finished: Create simulation model
2022.10.24.11:38:33 Info: Starting: Create simulation script
2022.10.24.11:38:33 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sim/ --use-relative-paths=true
2022.10.24.11:38:33 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sim/ directory:
2022.10.24.11:38:33 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:33 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sim/ directory:
2022.10.24.11:38:33 Info: xcelium/cds.lib
2022.10.24.11:38:33 Info: xcelium/hdl.var
2022.10.24.11:38:33 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:33 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:33 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sim/ directory:
2022.10.24.11:38:33 Info: mentor/msim_setup.tcl
2022.10.24.11:38:33 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sim/ directory:
2022.10.24.11:38:33 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:33 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sim/ directory:
2022.10.24.11:38:33 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:33 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:33 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_N/sim/.
2022.10.24.11:38:33 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:33 Info: Finished: Create simulation script
2022.10.24.11:38:34 Info: 
2022.10.24.11:38:34 Info: 
2022.10.24.11:38:34 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:34 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/main_dpi_controller_generation.rpt
2022.10.24.11:38:34 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:34 Info: Starting: Create simulation model
2022.10.24.11:38:34 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:34 Info: main_dpi_controller: "Transforming system: main_dpi_controller"
2022.10.24.11:38:34 Info: main_dpi_controller: "Naming system components in system: main_dpi_controller"
2022.10.24.11:38:34 Info: main_dpi_controller: "Processing generation queue"
2022.10.24.11:38:34 Info: main_dpi_controller: "Generating: main_dpi_controller"
2022.10.24.11:38:34 Info: main_dpi_controller: "Generating: hls_sim_main_dpi_controller"
2022.10.24.11:38:34 Info: main_dpi_controller: Done "main_dpi_controller" with 2 modules, 2 files
2022.10.24.11:38:34 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/sim/ directory:
2022.10.24.11:38:34 Info: common/vcs_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/sim/ directory:
2022.10.24.11:38:34 Info: common/modelsim_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/sim/ directory:
2022.10.24.11:38:34 Info: common/riviera_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/sim/ directory:
2022.10.24.11:38:34 Info: common/vcsmx_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/sim/ directory:
2022.10.24.11:38:34 Info: common/xcelium_files.tcl
2022.10.24.11:38:34 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/sim/.
2022.10.24.11:38:34 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:34 Info: qsys-generate succeeded.
2022.10.24.11:38:34 Info: Finished: Create simulation model
2022.10.24.11:38:34 Info: Starting: Create simulation script
2022.10.24.11:38:34 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/sim/ --use-relative-paths=true
2022.10.24.11:38:34 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/sim/ directory:
2022.10.24.11:38:34 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:34 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/sim/ directory:
2022.10.24.11:38:34 Info: mentor/msim_setup.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/sim/ directory:
2022.10.24.11:38:34 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/sim/ directory:
2022.10.24.11:38:34 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:34 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:34 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/sim/ directory:
2022.10.24.11:38:34 Info: xcelium/cds.lib
2022.10.24.11:38:34 Info: xcelium/hdl.var
2022.10.24.11:38:34 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:34 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:34 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/main_dpi_controller/sim/.
2022.10.24.11:38:34 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:34 Info: Finished: Create simulation script
2022.10.24.11:38:34 Info: 
2022.10.24.11:38:34 Info: 
2022.10.24.11:38:34 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:34 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/design_v1_cfan_generation.rpt
2022.10.24.11:38:34 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:34 Info: Starting: Create simulation model
2022.10.24.11:38:34 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:34 Info: design_v1_cfan: "Transforming system: design_v1_cfan"
2022.10.24.11:38:34 Info: design_v1_cfan: "Naming system components in system: design_v1_cfan"
2022.10.24.11:38:34 Info: design_v1_cfan: "Processing generation queue"
2022.10.24.11:38:34 Info: design_v1_cfan: "Generating: design_v1_cfan"
2022.10.24.11:38:34 Info: design_v1_cfan: "Generating: design_v1_cfan_avalon_conduit_fanout_10_ak2cvai"
2022.10.24.11:38:34 Info: design_v1_cfan: Done "design_v1_cfan" with 2 modules, 2 files
2022.10.24.11:38:34 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/sim/ directory:
2022.10.24.11:38:34 Info: common/vcs_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/sim/ directory:
2022.10.24.11:38:34 Info: common/modelsim_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/sim/ directory:
2022.10.24.11:38:34 Info: common/riviera_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/sim/ directory:
2022.10.24.11:38:34 Info: common/vcsmx_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/sim/ directory:
2022.10.24.11:38:34 Info: common/xcelium_files.tcl
2022.10.24.11:38:34 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/sim/.
2022.10.24.11:38:34 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:34 Info: qsys-generate succeeded.
2022.10.24.11:38:34 Info: Finished: Create simulation model
2022.10.24.11:38:34 Info: Starting: Create simulation script
2022.10.24.11:38:34 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/sim/ --use-relative-paths=true
2022.10.24.11:38:34 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/sim/ directory:
2022.10.24.11:38:34 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:34 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/sim/ directory:
2022.10.24.11:38:34 Info: mentor/msim_setup.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/sim/ directory:
2022.10.24.11:38:34 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/sim/ directory:
2022.10.24.11:38:34 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:34 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:34 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/sim/ directory:
2022.10.24.11:38:34 Info: xcelium/cds.lib
2022.10.24.11:38:34 Info: xcelium/hdl.var
2022.10.24.11:38:34 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:34 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:34 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_cfan/sim/.
2022.10.24.11:38:34 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:34 Info: Finished: Create simulation script
2022.10.24.11:38:34 Info: 
2022.10.24.11:38:34 Info: 
2022.10.24.11:38:34 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:34 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/design_v1_en_cfan_generation.rpt
2022.10.24.11:38:34 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:34 Info: Starting: Create simulation model
2022.10.24.11:38:34 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:34 Info: design_v1_en_cfan: "Transforming system: design_v1_en_cfan"
2022.10.24.11:38:34 Info: design_v1_en_cfan: "Naming system components in system: design_v1_en_cfan"
2022.10.24.11:38:34 Info: design_v1_en_cfan: "Processing generation queue"
2022.10.24.11:38:34 Info: design_v1_en_cfan: "Generating: design_v1_en_cfan"
2022.10.24.11:38:34 Info: design_v1_en_cfan: "Generating: design_v1_en_cfan_avalon_conduit_fanout_10_ak2cvai"
2022.10.24.11:38:34 Info: design_v1_en_cfan: Done "design_v1_en_cfan" with 2 modules, 2 files
2022.10.24.11:38:34 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/sim/ directory:
2022.10.24.11:38:34 Info: common/vcs_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/sim/ directory:
2022.10.24.11:38:34 Info: common/modelsim_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/sim/ directory:
2022.10.24.11:38:34 Info: common/riviera_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/sim/ directory:
2022.10.24.11:38:34 Info: common/vcsmx_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/sim/ directory:
2022.10.24.11:38:34 Info: common/xcelium_files.tcl
2022.10.24.11:38:34 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/sim/.
2022.10.24.11:38:34 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:34 Info: qsys-generate succeeded.
2022.10.24.11:38:34 Info: Finished: Create simulation model
2022.10.24.11:38:34 Info: Starting: Create simulation script
2022.10.24.11:38:34 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/sim/ --use-relative-paths=true
2022.10.24.11:38:34 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/sim/ directory:
2022.10.24.11:38:34 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:34 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/sim/ directory:
2022.10.24.11:38:34 Info: mentor/msim_setup.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/sim/ directory:
2022.10.24.11:38:34 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/sim/ directory:
2022.10.24.11:38:34 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:34 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:34 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/sim/ directory:
2022.10.24.11:38:34 Info: xcelium/cds.lib
2022.10.24.11:38:34 Info: xcelium/hdl.var
2022.10.24.11:38:34 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:34 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:34 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/design_v1_en_cfan/sim/.
2022.10.24.11:38:34 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:34 Info: Finished: Create simulation script
2022.10.24.11:38:34 Info: 
2022.10.24.11:38:34 Info: 
2022.10.24.11:38:34 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:34 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/dpic_design_v1_generation.rpt
2022.10.24.11:38:34 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:34 Info: Starting: Create simulation model
2022.10.24.11:38:34 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1 --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:34 Warning: dpic_design_v1.dpic_design_v1.dpi_control_agents_ready: Interface has no signals
2022.10.24.11:38:34 Warning: dpic_design_v1.dpic_design_v1.dpi_control_agents_done: Interface has no signals
2022.10.24.11:38:34 Info: dpic_design_v1: "Transforming system: dpic_design_v1"
2022.10.24.11:38:34 Info: dpic_design_v1: "Naming system components in system: dpic_design_v1"
2022.10.24.11:38:34 Info: dpic_design_v1: "Processing generation queue"
2022.10.24.11:38:34 Info: dpic_design_v1: "Generating: dpic_design_v1"
2022.10.24.11:38:34 Info: dpic_design_v1: "Generating: hls_sim_component_dpi_controller"
2022.10.24.11:38:34 Info: dpic_design_v1: Done "dpic_design_v1" with 2 modules, 5 files
2022.10.24.11:38:34 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/sim/ directory:
2022.10.24.11:38:34 Info: common/xcelium_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/sim/ directory:
2022.10.24.11:38:34 Info: common/vcs_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/sim/ directory:
2022.10.24.11:38:34 Info: common/riviera_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/sim/ directory:
2022.10.24.11:38:34 Info: common/vcsmx_files.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/sim/ directory:
2022.10.24.11:38:34 Info: common/modelsim_files.tcl
2022.10.24.11:38:34 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/sim/.
2022.10.24.11:38:34 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:34 Info: qsys-generate succeeded.
2022.10.24.11:38:34 Info: Finished: Create simulation model
2022.10.24.11:38:34 Info: Starting: Create simulation script
2022.10.24.11:38:34 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/sim/ --use-relative-paths=true
2022.10.24.11:38:34 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/sim/ directory:
2022.10.24.11:38:34 Info: xcelium/cds.lib
2022.10.24.11:38:34 Info: xcelium/hdl.var
2022.10.24.11:38:34 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:34 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:34 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/sim/ directory:
2022.10.24.11:38:34 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:34 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/sim/ directory:
2022.10.24.11:38:34 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:34 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/sim/ directory:
2022.10.24.11:38:34 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:34 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:34 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/sim/ directory:
2022.10.24.11:38:34 Info: mentor/msim_setup.tcl
2022.10.24.11:38:34 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/dpic_design_v1/sim/.
2022.10.24.11:38:34 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:34 Info: Finished: Create simulation script
2022.10.24.11:38:35 Info: 
2022.10.24.11:38:35 Info: 
2022.10.24.11:38:35 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:35 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/design_v1_generation.rpt
2022.10.24.11:38:35 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:35 Info: Starting: Create simulation model
2022.10.24.11:38:35 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1 --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:35 Info: design_v1: "Transforming system: design_v1"
2022.10.24.11:38:35 Info: design_v1: "Naming system components in system: design_v1"
2022.10.24.11:38:35 Info: design_v1: "Processing generation queue"
2022.10.24.11:38:35 Info: design_v1: "Generating: design_v1"
2022.10.24.11:38:35 Info: design_v1: "Generating: design_v1_internal"
2022.10.24.11:38:35 Info: design_v1: Done "design_v1" with 2 modules, 214 files
2022.10.24.11:38:35 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/sim/ directory:
2022.10.24.11:38:35 Info: common/riviera_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/sim/ directory:
2022.10.24.11:38:35 Info: common/xcelium_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/sim/ directory:
2022.10.24.11:38:35 Info: common/modelsim_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/sim/ directory:
2022.10.24.11:38:35 Info: common/vcs_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/sim/ directory:
2022.10.24.11:38:35 Info: common/vcsmx_files.tcl
2022.10.24.11:38:35 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/sim/.
2022.10.24.11:38:35 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:35 Info: qsys-generate succeeded.
2022.10.24.11:38:35 Info: Finished: Create simulation model
2022.10.24.11:38:35 Info: Starting: Create simulation script
2022.10.24.11:38:35 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/sim/ --use-relative-paths=true
2022.10.24.11:38:35 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/sim/ directory:
2022.10.24.11:38:35 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/sim/ directory:
2022.10.24.11:38:35 Info: xcelium/cds.lib
2022.10.24.11:38:35 Info: xcelium/hdl.var
2022.10.24.11:38:35 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:35 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:35 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/sim/ directory:
2022.10.24.11:38:35 Info: mentor/msim_setup.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/sim/ directory:
2022.10.24.11:38:35 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:35 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/sim/ directory:
2022.10.24.11:38:35 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:35 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:35 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1/sim/.
2022.10.24.11:38:35 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:35 Info: Finished: Create simulation script
2022.10.24.11:38:35 Info: 
2022.10.24.11:38:35 Info: 
2022.10.24.11:38:35 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:35 Info: tb: All Generic Component instances match their respective ip files.
2022.10.24.11:38:35 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/tb_generation.rpt
2022.10.24.11:38:35 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:35 Info: Starting: Create simulation model
2022.10.24.11:38:35 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:35 Info: Loading verification/tb.qsys
2022.10.24.11:38:35 Info: Reading input file
2022.10.24.11:38:35 Info: Parameterizing module clock_reset_inst
2022.10.24.11:38:35 Info: Parameterizing module component_dpi_controller_design_v1_inst
2022.10.24.11:38:35 Info: Parameterizing module concatenate_component_done_inst
2022.10.24.11:38:35 Info: Parameterizing module concatenate_component_wait_for_stream_writes_inst
2022.10.24.11:38:35 Info: Parameterizing module design_v1_component_dpi_controller_bind_conduit_fanout_inst
2022.10.24.11:38:35 Info: Parameterizing module design_v1_component_dpi_controller_enable_conduit_fanout_inst
2022.10.24.11:38:35 Info: Parameterizing module design_v1_component_dpi_controller_implicit_ready_conduit_fanout_inst
2022.10.24.11:38:35 Info: Parameterizing module design_v1_component_dpi_controller_stream_active_concatenate_inst
2022.10.24.11:38:35 Info: Parameterizing module design_v1_inst
2022.10.24.11:38:35 Info: Parameterizing module main_dpi_controller_inst
2022.10.24.11:38:35 Info: Parameterizing module split_component_start_inst
2022.10.24.11:38:35 Info: Parameterizing module stream_sink_dpi_bfm_design_v1_B_inst
2022.10.24.11:38:35 Info: Parameterizing module stream_source_dpi_bfm_design_v1_A_inst
2022.10.24.11:38:35 Info: Parameterizing module stream_source_dpi_bfm_design_v1_N_inst
2022.10.24.11:38:35 Info: Building connections
2022.10.24.11:38:35 Info: Parameterizing connections
2022.10.24.11:38:35 Info: Validating
2022.10.24.11:38:35 Info: Done reading input file
2022.10.24.11:38:35 Warning: tb.clock_reset_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2022.10.24.11:38:35 Warning: tb.component_dpi_controller_design_v1_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2022.10.24.11:38:35 Warning: tb.component_dpi_controller_design_v1_inst: Warnings found in IP parameterization.
2022.10.24.11:38:35 Warning: tb.component_dpi_controller_design_v1_inst.dpi_control_agents_ready: Interface has no signals
2022.10.24.11:38:35 Warning: tb.component_dpi_controller_design_v1_inst.dpi_control_agents_done: Interface has no signals
2022.10.24.11:38:35 Warning: tb.concatenate_component_done_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2022.10.24.11:38:35 Warning: tb.concatenate_component_wait_for_stream_writes_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2022.10.24.11:38:35 Warning: tb.design_v1_component_dpi_controller_bind_conduit_fanout_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2022.10.24.11:38:35 Warning: tb.design_v1_component_dpi_controller_enable_conduit_fanout_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2022.10.24.11:38:35 Warning: tb.design_v1_component_dpi_controller_implicit_ready_conduit_fanout_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2022.10.24.11:38:35 Warning: tb.design_v1_component_dpi_controller_stream_active_concatenate_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2022.10.24.11:38:35 Warning: tb.main_dpi_controller_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2022.10.24.11:38:35 Warning: tb.split_component_start_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2022.10.24.11:38:35 Warning: tb.stream_sink_dpi_bfm_design_v1_B_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2022.10.24.11:38:35 Warning: tb.stream_source_dpi_bfm_design_v1_A_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2022.10.24.11:38:35 Warning: tb.stream_source_dpi_bfm_design_v1_N_inst: Project Setting information doesn't match IP Variant file. Double-click to open System Info tab.
2022.10.24.11:38:35 Warning: tb.component_dpi_controller_design_v1_inst: component_dpi_controller_design_v1_inst.agent_busy must be exported, or connected to a matching conduit as it has unconnected inputs.
2022.10.24.11:38:35 Warning: tb.component_dpi_controller_design_v1_inst: component_dpi_controller_design_v1_inst.returndata must be exported, or connected to a matching conduit as it has unconnected inputs.
2022.10.24.11:38:35 Info: tb: "Transforming system: tb"
2022.10.24.11:38:35 Info: tb: "Naming system components in system: tb"
2022.10.24.11:38:35 Info: tb: "Processing generation queue"
2022.10.24.11:38:35 Info: tb: "Generating: tb"
2022.10.24.11:38:35 Info: tb: "Generating: clock_reset"
2022.10.24.11:38:35 Info: tb: "Generating: dpic_design_v1"
2022.10.24.11:38:35 Info: tb: "Generating: cat_done"
2022.10.24.11:38:35 Info: tb: "Generating: cat_cwfsw"
2022.10.24.11:38:35 Info: tb: "Generating: design_v1_cfan"
2022.10.24.11:38:35 Info: tb: "Generating: design_v1_en_cfan"
2022.10.24.11:38:35 Info: tb: "Generating: design_v1_ir_cfan"
2022.10.24.11:38:35 Info: tb: "Generating: design_v1_osacat"
2022.10.24.11:38:35 Info: tb: "Generating: design_v1"
2022.10.24.11:38:35 Info: tb: "Generating: main_dpi_controller"
2022.10.24.11:38:35 Info: tb: "Generating: sp_cstart"
2022.10.24.11:38:35 Info: tb: "Generating: ssi_design_v1_B"
2022.10.24.11:38:35 Info: tb: "Generating: sso_design_v1_A"
2022.10.24.11:38:35 Info: tb: "Generating: sso_design_v1_N"
2022.10.24.11:38:35 Info: tb: "Generating: tb_altera_irq_mapper_1920_trjgw7i"
2022.10.24.11:38:35 Info: tb: Done "tb" with 16 modules, 2 files
2022.10.24.11:38:35 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/sim/ directory:
2022.10.24.11:38:35 Info: common/modelsim_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/sim/ directory:
2022.10.24.11:38:35 Info: common/riviera_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/sim/ directory:
2022.10.24.11:38:35 Info: common/vcsmx_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/sim/ directory:
2022.10.24.11:38:35 Info: common/xcelium_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/sim/ directory:
2022.10.24.11:38:35 Info: common/vcs_files.tcl
2022.10.24.11:38:35 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/sim/.
2022.10.24.11:38:35 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:35 Info: qsys-generate succeeded.
2022.10.24.11:38:35 Info: Finished: Create simulation model
2022.10.24.11:38:35 Info: Starting: Create simulation script
2022.10.24.11:38:35 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb.qsys --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/sim/ --use-relative-paths=true
2022.10.24.11:38:35 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/sim/ directory:
2022.10.24.11:38:35 Info: mentor/msim_setup.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/sim/ directory:
2022.10.24.11:38:35 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/sim/ directory:
2022.10.24.11:38:35 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:35 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:35 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/sim/ directory:
2022.10.24.11:38:35 Info: xcelium/cds.lib
2022.10.24.11:38:35 Info: xcelium/hdl.var
2022.10.24.11:38:35 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:35 Info: 1 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:35 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/sim/ directory:
2022.10.24.11:38:35 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:35 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/tb/sim/.
2022.10.24.11:38:35 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:35 Info: Finished: Create simulation script
2022.10.24.11:38:35 Info: 
2022.10.24.11:38:35 Info: 
2022.10.24.11:38:35 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:35 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/cat_done_generation.rpt
2022.10.24.11:38:35 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:35 Info: Starting: Create simulation model
2022.10.24.11:38:35 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:35 Info: cat_done: "Transforming system: cat_done"
2022.10.24.11:38:35 Info: cat_done: "Naming system components in system: cat_done"
2022.10.24.11:38:35 Info: cat_done: "Processing generation queue"
2022.10.24.11:38:35 Info: cat_done: "Generating: cat_done"
2022.10.24.11:38:35 Info: cat_done: "Generating: cat_done_avalon_concatenate_singlebit_conduits_10_bjzeuhq"
2022.10.24.11:38:35 Info: cat_done: Done "cat_done" with 2 modules, 2 files
2022.10.24.11:38:35 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/sim/ directory:
2022.10.24.11:38:35 Info: common/vcs_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/sim/ directory:
2022.10.24.11:38:35 Info: common/modelsim_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/sim/ directory:
2022.10.24.11:38:35 Info: common/riviera_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/sim/ directory:
2022.10.24.11:38:35 Info: common/vcsmx_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/sim/ directory:
2022.10.24.11:38:35 Info: common/xcelium_files.tcl
2022.10.24.11:38:35 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/sim/.
2022.10.24.11:38:35 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:35 Info: qsys-generate succeeded.
2022.10.24.11:38:35 Info: Finished: Create simulation model
2022.10.24.11:38:35 Info: Starting: Create simulation script
2022.10.24.11:38:35 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/sim/ --use-relative-paths=true
2022.10.24.11:38:35 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/sim/ directory:
2022.10.24.11:38:35 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:35 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/sim/ directory:
2022.10.24.11:38:35 Info: mentor/msim_setup.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/sim/ directory:
2022.10.24.11:38:35 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/sim/ directory:
2022.10.24.11:38:35 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:35 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:35 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/sim/ directory:
2022.10.24.11:38:35 Info: xcelium/cds.lib
2022.10.24.11:38:35 Info: xcelium/hdl.var
2022.10.24.11:38:35 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:35 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:35 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_done/sim/.
2022.10.24.11:38:35 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:35 Info: Finished: Create simulation script
2022.10.24.11:38:35 Info: 
2022.10.24.11:38:35 Info: 
2022.10.24.11:38:35 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:35 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sso_design_v1_A_generation.rpt
2022.10.24.11:38:35 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:35 Info: Starting: Create simulation model
2022.10.24.11:38:35 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:35 Info: sso_design_v1_A: "Transforming system: sso_design_v1_A"
2022.10.24.11:38:35 Info: sso_design_v1_A: "Naming system components in system: sso_design_v1_A"
2022.10.24.11:38:35 Info: sso_design_v1_A: "Processing generation queue"
2022.10.24.11:38:35 Info: sso_design_v1_A: "Generating: sso_design_v1_A"
2022.10.24.11:38:35 Info: sso_design_v1_A: "Generating: hls_sim_stream_source_dpi_bfm"
2022.10.24.11:38:35 Info: sso_design_v1_A: Done "sso_design_v1_A" with 2 modules, 2 files
2022.10.24.11:38:35 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sim/ directory:
2022.10.24.11:38:35 Info: common/vcs_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sim/ directory:
2022.10.24.11:38:35 Info: common/modelsim_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sim/ directory:
2022.10.24.11:38:35 Info: common/riviera_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sim/ directory:
2022.10.24.11:38:35 Info: common/vcsmx_files.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sim/ directory:
2022.10.24.11:38:35 Info: common/xcelium_files.tcl
2022.10.24.11:38:35 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sim/.
2022.10.24.11:38:35 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:35 Info: qsys-generate succeeded.
2022.10.24.11:38:35 Info: Finished: Create simulation model
2022.10.24.11:38:35 Info: Starting: Create simulation script
2022.10.24.11:38:35 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sim/ --use-relative-paths=true
2022.10.24.11:38:35 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sim/ directory:
2022.10.24.11:38:35 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:35 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sim/ directory:
2022.10.24.11:38:35 Info: mentor/msim_setup.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sim/ directory:
2022.10.24.11:38:35 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:35 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sim/ directory:
2022.10.24.11:38:35 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:35 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:35 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sim/ directory:
2022.10.24.11:38:35 Info: xcelium/cds.lib
2022.10.24.11:38:35 Info: xcelium/hdl.var
2022.10.24.11:38:35 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:35 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:35 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/sso_design_v1_A/sim/.
2022.10.24.11:38:35 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:35 Info: Finished: Create simulation script
2022.10.24.11:38:36 Info: 
2022.10.24.11:38:36 Info: 
2022.10.24.11:38:36 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2022.10.24.11:38:36 Info: Saving generation log to /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/cat_cwfsw_generation.rpt
2022.10.24.11:38:36 Info: Generated by version: 21.4 build 67
2022.10.24.11:38:36 Info: Starting: Create simulation model
2022.10.24.11:38:36 Info: qsys-generate /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw --family="Arria 10" --part=10AX115U1F45I1SG
2022.10.24.11:38:36 Info: cat_cwfsw: "Transforming system: cat_cwfsw"
2022.10.24.11:38:36 Info: cat_cwfsw: "Naming system components in system: cat_cwfsw"
2022.10.24.11:38:36 Info: cat_cwfsw: "Processing generation queue"
2022.10.24.11:38:36 Info: cat_cwfsw: "Generating: cat_cwfsw"
2022.10.24.11:38:36 Info: cat_cwfsw: "Generating: cat_cwfsw_avalon_concatenate_singlebit_conduits_10_bjzeuhq"
2022.10.24.11:38:36 Info: cat_cwfsw: Done "cat_cwfsw" with 2 modules, 2 files
2022.10.24.11:38:36 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/sim/ directory:
2022.10.24.11:38:36 Info: common/xcelium_files.tcl
2022.10.24.11:38:36 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/sim/ directory:
2022.10.24.11:38:36 Info: common/vcs_files.tcl
2022.10.24.11:38:36 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/sim/ directory:
2022.10.24.11:38:36 Info: common/riviera_files.tcl
2022.10.24.11:38:36 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/sim/ directory:
2022.10.24.11:38:36 Info: common/vcsmx_files.tcl
2022.10.24.11:38:36 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/sim/ directory:
2022.10.24.11:38:36 Info: common/modelsim_files.tcl
2022.10.24.11:38:36 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/sim/.
2022.10.24.11:38:36 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:36 Info: qsys-generate succeeded.
2022.10.24.11:38:36 Info: Finished: Create simulation model
2022.10.24.11:38:36 Info: Starting: Create simulation script
2022.10.24.11:38:36 Info: sim-script-gen --system-file=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw.ip --output-directory=/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/sim/ --use-relative-paths=true
2022.10.24.11:38:36 Info: Generating the following file(s) for XCELIUM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/sim/ directory:
2022.10.24.11:38:36 Info: xcelium/cds.lib
2022.10.24.11:38:36 Info: xcelium/hdl.var
2022.10.24.11:38:36 Info: xcelium/xcelium_setup.sh
2022.10.24.11:38:36 Info: 2 .cds.lib files in xcelium/cds_libs/ directory
2022.10.24.11:38:36 Info: Generating the following file(s) for VCS simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/sim/ directory:
2022.10.24.11:38:36 Info: synopsys/vcs/vcs_setup.sh
2022.10.24.11:38:36 Info: Generating the following file(s) for RIVIERA simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/sim/ directory:
2022.10.24.11:38:36 Info: aldec/rivierapro_setup.tcl
2022.10.24.11:38:36 Info: Generating the following file(s) for VCSMX simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/sim/ directory:
2022.10.24.11:38:36 Info: synopsys/vcsmx/synopsys_sim.setup
2022.10.24.11:38:36 Info: synopsys/vcsmx/vcsmx_setup.sh
2022.10.24.11:38:36 Info: Generating the following file(s) for MODELSIM simulator in /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/sim/ directory:
2022.10.24.11:38:36 Info: mentor/msim_setup.tcl
2022.10.24.11:38:36 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/verification/ip/tb/cat_cwfsw/sim/.
2022.10.24.11:38:36 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
2022.10.24.11:38:36 Info: Finished: Create simulation script
2022.10.24.11:38:36 Info: Finished: Platform Designer system generation
# 
# do msim_compile.tcl
# Questa  Intel FPGA Edition-64 vsim 2021.3 Simulator 2021.07 Jul 13 2021
# .
# [exec] file_copy
# List Of Command Line Aliases
# 
# file_copy                                         -- Copy ROM/RAM files to simulation directory
# 
# dev_com                                           -- Compile device library files
# 
# com                                               -- Compile the design files in correct order
# 
# elab                                              -- Elaborate top level design
# 
# elab_debug                                        -- Elaborate the top level design with -voptargs=+acc option
# 
# ld                                                -- Compile all the design files and elaborate the top level design
# 
# ld_debug                                          -- Compile all the design files and elaborate the top level design with  -voptargs=+acc
# 
# 
# 
# List Of Variables
# 
# TOP_LEVEL_NAME                                    -- Top level module name.
#                                                      For most designs, this should be overridden
#                                                      to enable the elab/elab_debug aliases.
# 
# SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
# 
# QSYS_SIMDIR                                       -- Qsys base simulation directory.
# 
# QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
# 
# USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
# 
# SILENCE                                           -- Set to true to suppress all informational and/or warning messages in the generated simulation script. 
# 
# FORCE_MODELSIM_AE_SELECTION                       -- Set to true to force to select Modelsim AE always.
# +incdir+. +define+COSIM_LIB -suppress 14408
# [exec] dev_com
# [exec] com
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:39 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/sp_cstart/avalon_split_multibit_conduit_10/sim/sp_cstart_avalon_split_multibit_conduit_10_dlmo3na.sv -work avalon_split_multibit_conduit_10 
# -- Compiling module sp_cstart_avalon_split_multibit_conduit_10_dlmo3na
# 
# Top level modules:
# 	sp_cstart_avalon_split_multibit_conduit_10_dlmo3na
# End time: 11:38:39 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:39 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/sp_cstart/sim/sp_cstart.v -work sp_cstart 
# -- Compiling module sp_cstart
# 
# Top level modules:
# 	sp_cstart
# End time: 11:38:39 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:39 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/ssi_design_v1_B/hls_sim_stream_sink_dpi_bfm_10/sim/hls_sim_stream_sink_dpi_bfm.sv -work hls_sim_stream_sink_dpi_bfm_10 
# -- Compiling module hls_sim_stream_sink_dpi_bfm
# 
# Top level modules:
# 	hls_sim_stream_sink_dpi_bfm
# End time: 11:38:39 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:39 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/ssi_design_v1_B/sim/ssi_design_v1_B.v -work ssi_design_v1_B 
# -- Compiling module ssi_design_v1_B
# 
# Top level modules:
# 	ssi_design_v1_B
# End time: 11:38:39 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:39 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/design_v1_ir_cfan/avalon_conduit_fanout_10/sim/design_v1_ir_cfan_avalon_conduit_fanout_10_kjtx3wq.sv -work avalon_conduit_fanout_10 
# -- Compiling module design_v1_ir_cfan_avalon_conduit_fanout_10_kjtx3wq
# 
# Top level modules:
# 	design_v1_ir_cfan_avalon_conduit_fanout_10_kjtx3wq
# End time: 11:38:39 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:39 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/design_v1_ir_cfan/sim/design_v1_ir_cfan.v -work design_v1_ir_cfan 
# -- Compiling module design_v1_ir_cfan
# 
# Top level modules:
# 	design_v1_ir_cfan
# End time: 11:38:39 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:39 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/design_v1_osacat/avalon_concatenate_singlebit_conduits_10/sim/design_v1_osacat_avalon_concatenate_singlebit_conduits_10_bjzeuhq.sv -work avalon_concatenate_singlebit_conduits_10 
# -- Compiling module design_v1_osacat_avalon_concatenate_singlebit_conduits_10_bjzeuhq
# 
# Top level modules:
# 	design_v1_osacat_avalon_concatenate_singlebit_conduits_10_bjzeuhq
# End time: 11:38:39 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:39 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/design_v1_osacat/sim/design_v1_osacat.v -work design_v1_osacat 
# -- Compiling module design_v1_osacat
# 
# Top level modules:
# 	design_v1_osacat
# End time: 11:38:40 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:40 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/sso_design_v1_N/hls_sim_stream_source_dpi_bfm_10/sim/hls_sim_stream_source_dpi_bfm.sv -work hls_sim_stream_source_dpi_bfm_10 
# -- Compiling module hls_sim_stream_source_dpi_bfm
# 
# Top level modules:
# 	hls_sim_stream_source_dpi_bfm
# End time: 11:38:40 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:40 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/sso_design_v1_N/sim/sso_design_v1_N.v -work sso_design_v1_N 
# -- Compiling module sso_design_v1_N
# 
# Top level modules:
# 	sso_design_v1_N
# End time: 11:38:40 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:40 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/clock_reset/hls_sim_clock_reset_10/sim/hls_sim_clock_reset.sv -work hls_sim_clock_reset_10 
# -- Compiling module hls_sim_clock_reset
# 
# Top level modules:
# 	hls_sim_clock_reset
# End time: 11:38:40 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:40 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/clock_reset/sim/clock_reset.v -work clock_reset 
# -- Compiling module clock_reset
# 
# Top level modules:
# 	clock_reset
# End time: 11:38:40 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:40 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/design_v1_cfan/avalon_conduit_fanout_10/sim/design_v1_cfan_avalon_conduit_fanout_10_ak2cvai.sv -work avalon_conduit_fanout_10 
# -- Compiling module design_v1_cfan_avalon_conduit_fanout_10_ak2cvai
# 
# Top level modules:
# 	design_v1_cfan_avalon_conduit_fanout_10_ak2cvai
# End time: 11:38:40 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:40 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/design_v1_cfan/sim/design_v1_cfan.v -work design_v1_cfan 
# -- Compiling module design_v1_cfan
# 
# Top level modules:
# 	design_v1_cfan
# End time: 11:38:40 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:40 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/dpic_design_v1/hls_sim_component_dpi_controller_10/sim/hls_sim_stream_sink_dpi_bfm.sv -work hls_sim_component_dpi_controller_10 
# -- Compiling module hls_sim_stream_sink_dpi_bfm
# 
# Top level modules:
# 	hls_sim_stream_sink_dpi_bfm
# End time: 11:38:40 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:40 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/dpic_design_v1/hls_sim_component_dpi_controller_10/sim/hls_sim_stream_source_dpi_bfm.sv -work hls_sim_component_dpi_controller_10 
# -- Compiling module hls_sim_stream_source_dpi_bfm
# 
# Top level modules:
# 	hls_sim_stream_source_dpi_bfm
# End time: 11:38:40 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:40 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/dpic_design_v1/hls_sim_component_dpi_controller_10/sim/hld_sim_latency_tracker.sv -work hls_sim_component_dpi_controller_10 
# -- Compiling module hld_sim_latency_tracker
# 
# Top level modules:
# 	hld_sim_latency_tracker
# End time: 11:38:41 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:41 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/dpic_design_v1/hls_sim_component_dpi_controller_10/sim/hls_sim_component_dpi_controller.sv -work hls_sim_component_dpi_controller_10 
# -- Compiling module hls_sim_component_dpi_controller
# 
# Top level modules:
# 	hls_sim_component_dpi_controller
# End time: 11:38:41 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:41 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/dpic_design_v1/sim/dpic_design_v1.v -work dpic_design_v1 
# -- Compiling module dpic_design_v1
# 
# Top level modules:
# 	dpic_design_v1
# End time: 11:38:41 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:41 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/design_v1_en_cfan/avalon_conduit_fanout_10/sim/design_v1_en_cfan_avalon_conduit_fanout_10_ak2cvai.sv -work avalon_conduit_fanout_10 
# -- Compiling module design_v1_en_cfan_avalon_conduit_fanout_10_ak2cvai
# 
# Top level modules:
# 	design_v1_en_cfan_avalon_conduit_fanout_10_ak2cvai
# End time: 11:38:41 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:41 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/design_v1_en_cfan/sim/design_v1_en_cfan.v -work design_v1_en_cfan 
# -- Compiling module design_v1_en_cfan
# 
# Top level modules:
# 	design_v1_en_cfan
# End time: 11:38:41 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:41 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/dspba_library_ver.sv -work design_v1_internal_10 
# -- Compiling module dspba_delay_ver
# -- Compiling module dspba_sync_reg_ver
# -- Compiling module dspba_pipe
# -- Compiling module dspba_dcfifo_mixed_widths
# 
# Top level modules:
# 	dspba_delay_ver
# 	dspba_sync_reg_ver
# 	dspba_pipe
# 	dspba_dcfifo_mixed_widths
# End time: 11:38:41 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:41 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ecc_pkg.sv -work design_v1_internal_10 
# -- Compiling package acl_ecc_pkg
# 
# Top level modules:
# 	--none--
# End time: 11:38:41 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:41 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_data_fifo.v -work design_v1_internal_10 
# -- Compiling module acl_data_fifo
# 
# Top level modules:
# 	--none--
# End time: 11:38:41 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:41 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_fifo.v -work design_v1_internal_10 
# -- Compiling module acl_fifo
# 
# Top level modules:
# 	acl_fifo
# End time: 11:38:41 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:41 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_altera_syncram_wrapped.sv -work design_v1_internal_10 
# -- Compiling module acl_altera_syncram_wrapped
# -- Importing package acl_ecc_pkg
# 
# Top level modules:
# 	acl_altera_syncram_wrapped
# End time: 11:38:42 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:42 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_scfifo_wrapped.sv -work design_v1_internal_10 
# -- Compiling module acl_scfifo_wrapped
# -- Importing package acl_ecc_pkg
# 
# Top level modules:
# 	acl_scfifo_wrapped
# End time: 11:38:42 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:42 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ecc_decoder.sv -work design_v1_internal_10 
# -- Compiling module acl_ecc_decoder
# -- Importing package acl_ecc_pkg
# -- Compiling module secded_decoder
# 
# Top level modules:
# 	acl_ecc_decoder
# End time: 11:38:42 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:42 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ecc_encoder.sv -work design_v1_internal_10 
# -- Compiling module acl_ecc_encoder
# -- Importing package acl_ecc_pkg
# -- Compiling module secded_encoder
# 
# Top level modules:
# 	acl_ecc_encoder
# End time: 11:38:42 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:42 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ll_fifo.v -work design_v1_internal_10 
# -- Compiling module acl_ll_fifo
# 
# Top level modules:
# 	acl_ll_fifo
# End time: 11:38:42 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:42 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ll_ram_fifo.v -work design_v1_internal_10 
# -- Compiling module acl_ll_ram_fifo
# 
# Top level modules:
# 	acl_ll_ram_fifo
# End time: 11:38:42 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:42 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_valid_fifo_counter.v -work design_v1_internal_10 
# -- Compiling module acl_valid_fifo_counter
# 
# Top level modules:
# 	acl_valid_fifo_counter
# End time: 11:38:42 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:42 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_dspba_valid_fifo_counter.v -work design_v1_internal_10 
# -- Compiling module acl_dspba_valid_fifo_counter
# 
# Top level modules:
# 	acl_dspba_valid_fifo_counter
# End time: 11:38:42 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:42 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_staging_reg.v -work design_v1_internal_10 
# -- Compiling module acl_staging_reg
# 
# Top level modules:
# 	acl_staging_reg
# End time: 11:38:42 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:42 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_fifo.sv -work design_v1_internal_10 
# -- Compiling module hld_fifo
# 
# Top level modules:
# 	--none--
# End time: 11:38:42 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:43 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_mid_speed_fifo.sv -work design_v1_internal_10 
# -- Compiling module acl_mid_speed_fifo
# 
# Top level modules:
# 	acl_mid_speed_fifo
# End time: 11:38:43 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:43 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_latency_one_ram_fifo.sv -work design_v1_internal_10 
# -- Compiling module acl_latency_one_ram_fifo
# 
# Top level modules:
# 	acl_latency_one_ram_fifo
# End time: 11:38:43 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:43 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_latency_zero_ram_fifo.sv -work design_v1_internal_10 
# -- Compiling module acl_latency_zero_ram_fifo
# 
# Top level modules:
# 	acl_latency_zero_ram_fifo
# End time: 11:38:43 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:43 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_fifo_zero_width.sv -work design_v1_internal_10 
# -- Compiling module hld_fifo_zero_width
# 
# Top level modules:
# 	hld_fifo_zero_width
# End time: 11:38:43 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:43 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_high_speed_fifo.sv -work design_v1_internal_10 
# -- Compiling module acl_high_speed_fifo
# -- Compiling module scfifo_to_acl_high_speed_fifo
# 
# Top level modules:
# 	scfifo_to_acl_high_speed_fifo
# End time: 11:38:43 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:43 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv -work design_v1_internal_10 
# -- Compiling module acl_low_latency_fifo
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(418): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(419): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(419): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(420): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(423): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(426): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(490): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(491): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(492): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(493): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(494): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(549): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(613): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(614): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(615): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(688): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(689): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(690): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(691): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(736): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(761): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(762): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(763): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(786): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(787): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(788): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(851): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(852): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(853): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(879): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(880): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(881): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_low_latency_fifo.sv(882): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# 
# Top level modules:
# 	acl_low_latency_fifo
# End time: 11:38:43 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 33
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:43 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_zero_latency_fifo.sv -work design_v1_internal_10 
# -- Compiling module acl_zero_latency_fifo
# 
# Top level modules:
# 	acl_zero_latency_fifo
# End time: 11:38:43 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:43 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_fanout_pipeline.sv -work design_v1_internal_10 
# -- Compiling module acl_fanout_pipeline
# 
# Top level modules:
# 	acl_fanout_pipeline
# End time: 11:38:43 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:43 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_std_synchronizer_nocut.v -work design_v1_internal_10 
# -- Compiling module acl_std_synchronizer_nocut
# 
# Top level modules:
# 	acl_std_synchronizer_nocut
# End time: 11:38:44 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:44 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_tessellated_incr_decr_threshold.sv -work design_v1_internal_10 
# -- Compiling module acl_tessellated_incr_decr_threshold
# 
# Top level modules:
# 	acl_tessellated_incr_decr_threshold
# End time: 11:38:44 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:44 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_tessellated_incr_lookahead.sv -work design_v1_internal_10 
# -- Compiling module acl_tessellated_incr_lookahead
# 
# Top level modules:
# 	acl_tessellated_incr_lookahead
# End time: 11:38:44 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:44 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_reset_handler.sv -work design_v1_internal_10 
# -- Compiling module acl_reset_handler
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_reset_handler.sv(258): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_reset_handler.sv(259): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_reset_handler.sv(263): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_reset_handler.sv(264): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_reset_handler.sv(267): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_reset_handler.sv(268): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# 
# Top level modules:
# 	acl_reset_handler
# End time: 11:38:44 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 6
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:44 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_lfsr.sv -work design_v1_internal_10 
# -- Compiling module acl_lfsr
# -- Compiling module galois_lfsr
# -- Compiling module fibonacci_lfsr
# 
# Top level modules:
# 	acl_lfsr
# End time: 11:38:44 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:44 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_mlab_fifo.sv -work design_v1_internal_10 
# -- Compiling module acl_mlab_fifo
# 
# Top level modules:
# 	acl_mlab_fifo
# End time: 11:38:44 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:44 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_parameter_assert.svh -work design_v1_internal_10 
# End time: 11:38:44 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:44 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_pop.v -work design_v1_internal_10 
# -- Compiling module acl_pop
# 
# Top level modules:
# 	acl_pop
# End time: 11:38:44 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:44 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v -work design_v1_internal_10 
# -- Compiling module acl_push
# 
# Top level modules:
# 	acl_push
# End time: 11:38:44 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:44 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_token_fifo_counter.v -work design_v1_internal_10 
# -- Compiling module acl_token_fifo_counter
# 
# Top level modules:
# 	acl_token_fifo_counter
# End time: 11:38:45 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:45 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_pipeline.v -work design_v1_internal_10 
# -- Compiling module acl_pipeline
# 
# Top level modules:
# 	acl_pipeline
# End time: 11:38:45 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:45 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_dspba_buffer.v -work design_v1_internal_10 
# -- Compiling module acl_dspba_buffer
# 
# Top level modules:
# 	acl_dspba_buffer
# End time: 11:38:45 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:45 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_enable_sink.v -work design_v1_internal_10 
# -- Compiling module acl_enable_sink
# 
# Top level modules:
# 	acl_enable_sink
# End time: 11:38:45 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:45 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_memory_depth_quantization_pkg.sv -work design_v1_internal_10 
# -- Compiling package hld_memory_depth_quantization_pkg
# 
# Top level modules:
# 	--none--
# End time: 11:38:45 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:45 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iord.sv -work design_v1_internal_10 
# -- Compiling module hld_iord
# 
# Top level modules:
# 	hld_iord
# End time: 11:38:45 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:45 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iord_stall_latency.sv -work design_v1_internal_10 
# -- Compiling module hld_iord_stall_latency
# -- Importing package hld_memory_depth_quantization_pkg
# 
# Top level modules:
# 	hld_iord_stall_latency
# End time: 11:38:45 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:45 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iord_stall_valid.sv -work design_v1_internal_10 
# -- Compiling module hld_iord_stall_valid
# -- Importing package hld_memory_depth_quantization_pkg
# 
# Top level modules:
# 	hld_iord_stall_valid
# End time: 11:38:45 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:45 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_shift_register_no_reset.sv -work design_v1_internal_10 
# -- Compiling module acl_shift_register_no_reset
# 
# Top level modules:
# 	acl_shift_register_no_reset
# End time: 11:38:45 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:45 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_top.v -work design_v1_internal_10 
# -- Compiling module lsu_top
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_top.v(492): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_top.v(493): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_top.v(494): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_top.v(495): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_top.v(522): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# 
# Top level modules:
# 	lsu_top
# End time: 11:38:46 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 5
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:46 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_permute_address.v -work design_v1_internal_10 
# -- Compiling module lsu_permute_address
# 
# Top level modules:
# 	lsu_permute_address
# End time: 11:38:46 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:46 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_pipelined.v -work design_v1_internal_10 
# -- Compiling module lsu_pipelined_read
# -- Compiling module lsu_pipelined_write
# 
# Top level modules:
# 	lsu_pipelined_read
# 	lsu_pipelined_write
# End time: 11:38:46 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:46 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_enabled.v -work design_v1_internal_10 
# -- Compiling module lsu_enabled_read
# -- Compiling module lsu_enabled_write
# 
# Top level modules:
# 	lsu_enabled_read
# 	lsu_enabled_write
# End time: 11:38:46 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:46 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_basic_coalescer.v -work design_v1_internal_10 
# -- Compiling module lsu_basic_coalesced_read
# -- Compiling module lsu_basic_coalesced_write
# -- Compiling module lookahead_fifo
# -- Compiling module basic_coalescer
# 
# Top level modules:
# 	lsu_basic_coalesced_read
# 	lsu_basic_coalesced_write
# End time: 11:38:46 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:46 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_simple.v -work design_v1_internal_10 
# -- Compiling module lsu_simple_read
# -- Compiling module lsu_simple_write
# 
# Top level modules:
# 	lsu_simple_read
# 	lsu_simple_write
# End time: 11:38:46 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:46 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_streaming.v -work design_v1_internal_10 
# -- Compiling module lsu_streaming_read
# -- Compiling module lsu_streaming_write
# 
# Top level modules:
# 	lsu_streaming_read
# 	lsu_streaming_write
# End time: 11:38:46 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:46 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_burst_host.v -work design_v1_internal_10 
# -- Compiling module lsu_burst_read_host
# 
# Top level modules:
# 	lsu_burst_read_host
# End time: 11:38:46 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:46 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_bursting_load_stores.v -work design_v1_internal_10 
# -- Compiling module lsu_bursting_read
# -- Compiling module acl_io_pipeline
# -- Compiling module lsu_bursting_pipelined_read
# -- Compiling module acl_stall_free_coalescer
# -- Compiling module lsu_bursting_write
# -- Compiling module lsu_bursting_write_internal
# -- Compiling module bursting_coalescer
# 
# Top level modules:
# 	lsu_bursting_read
# 	lsu_bursting_write
# End time: 11:38:46 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:46 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_non_aligned_write.v -work design_v1_internal_10 
# -- Compiling module lsu_non_aligned_write
# -- Compiling module lsu_non_aligned_write_internal
# 
# Top level modules:
# 	lsu_non_aligned_write
# End time: 11:38:47 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:47 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_read_cache.v -work design_v1_internal_10 
# -- Compiling module lsu_read_cache
# 
# Top level modules:
# 	lsu_read_cache
# End time: 11:38:47 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:47 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_atomic.v -work design_v1_internal_10 
# -- Compiling module lsu_atomic_pipelined
# 
# Top level modules:
# 	lsu_atomic_pipelined
# End time: 11:38:47 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:47 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_prefetch_block.v -work design_v1_internal_10 
# -- Compiling module lsu_prefetch_block
# 
# Top level modules:
# 	lsu_prefetch_block
# End time: 11:38:47 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:47 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_wide_wrapper.v -work design_v1_internal_10 
# -- Compiling module lsu_wide_wrapper
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_wide_wrapper.v(367): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_wide_wrapper.v(466): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_wide_wrapper.v(467): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# 
# Top level modules:
# 	lsu_wide_wrapper
# End time: 11:38:47 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 3
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:47 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_streaming_prefetch.v -work design_v1_internal_10 
# -- Compiling module lsu_streaming_prefetch_read
# -- Compiling module lsu_streaming_prefetch_fifo
# -- Compiling module lsu_streaming_prefetch_avalon_burst_host
# 
# Top level modules:
# 	lsu_streaming_prefetch_read
# End time: 11:38:47 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:47 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_aligned_burst_coalesced_lsu.v -work design_v1_internal_10 
# -- Compiling module acl_aligned_burst_coalesced_lsu
# -- Compiling module avalon_interface
# -- Compiling module valid_generator
# -- Compiling module acl_lsu_buffers
# -- Compiling module acl_burst_coalescer
# -- Compiling module acl_registered_comparison
# 
# Top level modules:
# 	acl_aligned_burst_coalesced_lsu
# End time: 11:38:47 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:47 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_toggle_detect.v -work design_v1_internal_10 
# -- Compiling module acl_toggle_detect
# 
# Top level modules:
# 	acl_toggle_detect
# End time: 11:38:47 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:47 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_debug_mem.v -work design_v1_internal_10 
# -- Compiling module acl_debug_mem
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_debug_mem.v(38): (vlog-13314) Defaulting port 'data' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# 
# Top level modules:
# 	acl_debug_mem
# End time: 11:38:47 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:47 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_burst_coalesced_pipelined_write.sv -work design_v1_internal_10 
# -- Compiling module lsu_burst_coalesced_pipelined_write
# 
# Top level modules:
# 	lsu_burst_coalesced_pipelined_write
# End time: 11:38:48 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:48 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_burst_coalesced_pipelined_read.sv -work design_v1_internal_10 
# -- Compiling module lsu_burst_coalesced_pipelined_read
# 
# Top level modules:
# 	lsu_burst_coalesced_pipelined_read
# End time: 11:38:48 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:48 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_fifo_stall_valid_lookahead.sv -work design_v1_internal_10 
# -- Compiling module acl_fifo_stall_valid_lookahead
# 
# Top level modules:
# 	acl_fifo_stall_valid_lookahead
# End time: 11:38:48 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:48 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_global_load_store.sv -work design_v1_internal_10 
# -- Compiling module hld_global_load_store
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_global_load_store.sv(799): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_global_load_store.sv(799): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_global_load_store.sv(800): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# 
# Top level modules:
# 	hld_global_load_store
# End time: 11:38:48 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 3
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:48 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu.sv -work design_v1_internal_10 
# -- Compiling module hld_lsu
# 
# Top level modules:
# 	hld_lsu
# End time: 11:38:48 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:48 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_burst_coalescer.sv -work design_v1_internal_10 
# -- Compiling module hld_lsu_burst_coalescer
# 
# Top level modules:
# 	hld_lsu_burst_coalescer
# End time: 11:38:48 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:48 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_coalescer_dynamic_timeout.sv -work design_v1_internal_10 
# -- Compiling module hld_lsu_coalescer_dynamic_timeout
# 
# Top level modules:
# 	hld_lsu_coalescer_dynamic_timeout
# End time: 11:38:48 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:48 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_data_aligner.sv -work design_v1_internal_10 
# -- Compiling module hld_lsu_data_aligner
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_data_aligner.sv(76): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_data_aligner.sv(77): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_data_aligner.sv(90): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_data_aligner.sv(91): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_data_aligner.sv(91): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_data_aligner.sv(92): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_data_aligner.sv(98): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_data_aligner.sv(99): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_data_aligner.sv(99): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_data_aligner.sv(100): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# 
# Top level modules:
# 	hld_lsu_data_aligner
# End time: 11:38:48 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 10
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:48 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_read_cache.sv -work design_v1_internal_10 
# -- Compiling module hld_lsu_read_cache
# -- Compiling module hld_lsu_read_cache_simple_dual_port_ram
# 
# Top level modules:
# 	hld_lsu_read_cache
# End time: 11:38:48 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:48 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_read_data_alignment.sv -work design_v1_internal_10 
# -- Compiling module hld_lsu_read_data_alignment
# 
# Top level modules:
# 	hld_lsu_read_data_alignment
# End time: 11:38:49 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:49 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_unaligned_controller.sv -work design_v1_internal_10 
# -- Compiling module hld_lsu_unaligned_controller
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_unaligned_controller.sv(143): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_unaligned_controller.sv(144): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_unaligned_controller.sv(149): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_unaligned_controller.sv(150): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_unaligned_controller.sv(151): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# 
# Top level modules:
# 	hld_lsu_unaligned_controller
# End time: 11:38:49 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 5
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:49 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_word_coalescer.sv -work design_v1_internal_10 
# -- Compiling module hld_lsu_word_coalescer
# 
# Top level modules:
# 	hld_lsu_word_coalescer
# End time: 11:38:49 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:49 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_write_data_alignment.sv -work design_v1_internal_10 
# -- Compiling module hld_lsu_write_data_alignment
# 
# Top level modules:
# 	hld_lsu_write_data_alignment
# End time: 11:38:49 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:49 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_lsu_write_kernel_downstream.sv -work design_v1_internal_10 
# -- Compiling module hld_lsu_write_kernel_downstream
# 
# Top level modules:
# 	hld_lsu_write_kernel_downstream
# End time: 11:38:49 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:49 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ffwdsrc.v -work design_v1_internal_10 
# -- Compiling module acl_ffwdsrc
# 
# Top level modules:
# 	acl_ffwdsrc
# End time: 11:38:49 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:49 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ffwddst.sv -work design_v1_internal_10 
# -- Compiling module acl_ffwddst
# 
# Top level modules:
# 	acl_ffwddst
# End time: 11:38:49 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:49 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_full_detector.v -work design_v1_internal_10 
# -- Compiling module acl_full_detector
# 
# Top level modules:
# 	acl_full_detector
# End time: 11:38:49 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:49 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_tessellated_incr_decr_decr.sv -work design_v1_internal_10 
# -- Compiling module acl_tessellated_incr_decr_decr
# -- Compiling module acl_tessellated_incr_decr
# 
# Top level modules:
# 	acl_tessellated_incr_decr_decr
# End time: 11:38:49 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:49 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iowr.sv -work design_v1_internal_10 
# -- Compiling module hld_iowr
# 
# Top level modules:
# 	hld_iowr
# End time: 11:38:50 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:50 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iowr_stall_latency.sv -work design_v1_internal_10 
# -- Compiling module hld_iowr_stall_latency
# -- Importing package hld_memory_depth_quantization_pkg
# 
# Top level modules:
# 	hld_iowr_stall_latency
# End time: 11:38:50 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:50 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iowr_stall_valid.sv -work design_v1_internal_10 
# -- Compiling module hld_iowr_stall_valid
# 
# Top level modules:
# 	hld_iowr_stall_valid
# End time: 11:38:50 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:50 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_loop_profiler.sv -work design_v1_internal_10 
# -- Compiling module hld_loop_profiler
# 
# Top level modules:
# 	hld_loop_profiler
# End time: 11:38:50 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:50 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_sim_latency_tracker.sv -work design_v1_internal_10 
# -- Compiling module hld_sim_latency_tracker
# 
# Top level modules:
# 	hld_sim_latency_tracker
# End time: 11:38:50 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:50 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_loop_limiter.v -work design_v1_internal_10 
# -- Compiling module acl_loop_limiter
# 
# Top level modules:
# 	acl_loop_limiter
# End time: 11:38:50 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:50 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_reset_wire.v -work design_v1_internal_10 
# -- Compiling module acl_reset_wire
# 
# Top level modules:
# 	acl_reset_wire
# End time: 11:38:50 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:50 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function_wrapper.sv -work design_v1_internal_10 
# -- Compiling module design_v1_function_wrapper
# 
# Top level modules:
# 	design_v1_function_wrapper
# End time: 11:38:50 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:50 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function.sv -work design_v1_internal_10 
# -- Compiling module design_v1_function
# 
# Top level modules:
# 	design_v1_function
# End time: 11:38:50 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:50 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B0_runOnce.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B0_runOnce
# 
# Top level modules:
# 	design_v1_bb_B0_runOnce
# End time: 11:38:51 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:51 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B0_runOnce_stall_region.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B0_runOnce_stall_region
# 
# Top level modules:
# 	design_v1_bb_B0_runOnce_stall_region
# End time: 11:38:51 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:51 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B0_runOnce_merge_reg.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B0_runOnce_merge_reg
# 
# Top level modules:
# 	design_v1_B0_runOnce_merge_reg
# End time: 11:38:51 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:51 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pop_token_i1_wt_limpop_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pop_token_i1_wt_limpop_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pop_token_i1_wt_limpop_0
# End time: 11:38:51 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:51 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pop_token_i1_wt_limpop_0_reg.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pop_token_i1_wt_limpop_0_reg
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pop_token_i1_wt_limpop_0_reg
# End time: 11:38:51 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:51 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_token_i1_wt_limpush_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_token_i1_wt_limpush_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_token_i1_wt_limpush_0
# End time: 11:38:51 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:51 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_token_i1_wt_limpush_1_reg.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_token_i1_wt_limpush_1_reg
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_token_i1_wt_limpush_1_reg
# End time: 11:38:51 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:51 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B0_runOnce_branch.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B0_runOnce_branch
# 
# Top level modules:
# 	design_v1_B0_runOnce_branch
# End time: 11:38:51 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:51 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B0_runOnce_merge.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B0_runOnce_merge
# 
# Top level modules:
# 	design_v1_B0_runOnce_merge
# End time: 11:38:51 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:51 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B1_start.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B1_start
# 
# Top level modules:
# 	design_v1_bb_B1_start
# End time: 11:38:52 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:52 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B1_start_stall_region.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B1_start_stall_region
# 
# Top level modules:
# 	design_v1_bb_B1_start_stall_region
# End time: 11:38:52 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:52 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B1_start_merge_reg.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B1_start_merge_reg
# 
# Top level modules:
# 	design_v1_B1_start_merge_reg
# End time: 11:38:52 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:52 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_ffwd_source_i1_unnamed_3_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_ffwd_source_i1_unnamed_3_design_v10
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_ffwd_source_i1_unnamed_3_design_v10
# End time: 11:38:52 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:52 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_ffwd_source_i33_unnamed_4_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_ffwd_source_i33_unnamed_4_design_v10
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_ffwd_source_i33_unnamed_4_design_v10
# End time: 11:38:52 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:52 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pop_throttle_i1_throttle_pop_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pop_throttle_i1_throttle_pop_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pop_throttle_i1_throttle_pop_0
# End time: 11:38:52 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:52 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pop_throttle_i1_throttle_pop_1_reg.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pop_throttle_i1_throttle_pop_1_reg
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pop_throttle_i1_throttle_pop_1_reg
# End time: 11:38:52 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:52 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_iord_bl_call_unnamed_design_v12_design_v10
# 
# Top level modules:
# 	design_v1_i_iord_bl_call_unnamed_design_v12_design_v10
# End time: 11:38:52 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:52 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_mem_memdep_1_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_mem_memdep_1_0
# End time: 11:38:52 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:52 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_sfc_s_c0_in_wt_entry_s_c0_enter1_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_sfc_s_c0_in_wt_entry_s_c0_enter1_design_v10
# 
# Top level modules:
# 	design_v1_i_sfc_s_c0_in_wt_entry_s_c0_enter1_design_v10
# End time: 11:38:53 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:53 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000s_c0_exit_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000s_c0_exit_design_v10
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000s_c0_exit_design_v10
# End time: 11:38:53 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:53 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_sfc_logic_s_c0_in_wt_entry_s_c0_enter1_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_sfc_logic_s_c0_in_wt_entry_s_c0_enter1_design_v10
# 
# Top level modules:
# 	design_v1_i_sfc_logic_s_c0_in_wt_entry_s_c0_enter1_design_v10
# End time: 11:38:53 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:53 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going27_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pipeline_keep_going27_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pipeline_keep_going27_0
# End time: 11:38:53 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:53 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_notexitcond28_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_i1_notexitcond28_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_i1_notexitcond28_0
# End time: 11:38:53 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:53 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B1_start_branch.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B1_start_branch
# 
# Top level modules:
# 	design_v1_B1_start_branch
# End time: 11:38:53 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:53 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B1_start_merge.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B1_start_merge
# 
# Top level modules:
# 	design_v1_B1_start_merge
# End time: 11:38:53 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:53 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B2.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B2
# 
# Top level modules:
# 	design_v1_bb_B2
# End time: 11:38:53 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:53 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B2_stall_region.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B2_stall_region
# 
# Top level modules:
# 	design_v1_bb_B2_stall_region
# End time: 11:38:53 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:53 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B2_branch.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B2_branch
# 
# Top level modules:
# 	design_v1_B2_branch
# End time: 11:38:54 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:54 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B2_merge.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B2_merge
# 
# Top level modules:
# 	design_v1_B2_merge
# End time: 11:38:54 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:54 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B3.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B3
# 
# Top level modules:
# 	design_v1_bb_B3
# End time: 11:38:54 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:54 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B3_stall_region.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B3_stall_region
# 
# Top level modules:
# 	design_v1_bb_B3_stall_region
# End time: 11:38:54 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:54 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B3_merge_reg.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B3_merge_reg
# 
# Top level modules:
# 	design_v1_B3_merge_reg
# End time: 11:38:54 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:54 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_iord_bl_a_unnamed_6_design_v10
# 
# Top level modules:
# 	design_v1_i_iord_bl_a_unnamed_6_design_v10
# End time: 11:38:54 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:54 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_sfc_s_c0_in_for_body5_s_c0_enter302_design_v11.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_sfc_s_c0_in_for_body5_s_c0_enter302_design_v11
# 
# Top level modules:
# 	design_v1_i_sfc_s_c0_in_for_body5_s_c0_enter302_design_v11
# End time: 11:38:54 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:54 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000c0_exit32_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000c0_exit32_design_v10
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000c0_exit32_design_v10
# End time: 11:38:54 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:54 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000gn_v11_full_detector.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000gn_v11_full_detector
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000gn_v11_full_detector
# End time: 11:38:54 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:54 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000design_v11_data_fifo.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000design_v11_data_fifo
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000design_v11_data_fifo
# End time: 11:38:55 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:55 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_sfc_logic_s_c0_in_for_body5_s_c0_enter302_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_sfc_logic_s_c0_in_for_body5_s_c0_enter302_design_v10
# 
# Top level modules:
# 	design_v1_i_sfc_logic_s_c0_in_for_body5_s_c0_enter302_design_v10
# End time: 11:38:55 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:55 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_ffwd_dest_i1_cmp3236_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_ffwd_dest_i1_cmp3236_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_ffwd_dest_i1_cmp3236_0
# End time: 11:38:55 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:55 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_ffwd_dest_i1_cmp3237_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_ffwd_dest_i1_cmp3237_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_ffwd_dest_i1_cmp3237_0
# End time: 11:38:55 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:55 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_ffwd_dest_i33_unnamed_5_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_ffwd_dest_i33_unnamed_5_design_v10
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_ffwd_dest_i33_unnamed_5_design_v10
# End time: 11:38:55 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:55 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going12_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pipeline_keep_going12_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pipeline_keep_going12_0
# End time: 11:38:55 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:55 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pop_i33_fpga_indvars_iv_pop8_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pop_i33_fpga_indvars_iv_pop8_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pop_i33_fpga_indvars_iv_pop8_0
# End time: 11:38:55 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:55 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pop_i4_cleanups15_pop11_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pop_i4_cleanups15_pop11_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pop_i4_cleanups15_pop11_0
# End time: 11:38:55 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:55 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pop_i4_initerations10_pop10_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pop_i4_initerations10_pop10_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pop_i4_initerations10_pop10_0
# End time: 11:38:55 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:55 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_lastiniteration14_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_i1_lastiniteration14_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_i1_lastiniteration14_0
# End time: 11:38:56 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:56 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_notexitcond22_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_i1_notexitcond22_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_i1_notexitcond22_0
# End time: 11:38:56 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:56 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i33_fpga_indvars_iv_push8_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_i33_fpga_indvars_iv_push8_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_i33_fpga_indvars_iv_push8_0
# End time: 11:38:56 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:56 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i4_cleanups15_push11_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_i4_cleanups15_push11_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_i4_cleanups15_push11_0
# End time: 11:38:56 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:56 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i4_initerations10_push10_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_i4_initerations10_push10_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_i4_initerations10_push10_0
# End time: 11:38:56 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:56 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_sfc_s_c1_in_for_body5_s_c1_enter_design_v15.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_sfc_s_c1_in_for_body5_s_c1_enter_design_v15
# 
# Top level modules:
# 	design_v1_i_sfc_s_c1_in_for_body5_s_c1_enter_design_v15
# End time: 11:38:56 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:56 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000s_c1_exit_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000s_c1_exit_design_v10
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000s_c1_exit_design_v10
# End time: 11:38:56 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:56 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000gn_v11_full_detector.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000gn_v11_full_detector
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000gn_v11_full_detector
# End time: 11:38:56 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:56 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000design_v11_data_fifo.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000design_v11_data_fifo
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000design_v11_data_fifo
# End time: 11:38:56 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:56 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_sfc_logic_s_c1_in_for_body5_s_c1_enter_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_sfc_logic_s_c1_in_for_body5_s_c1_enter_design_v10
# 
# Top level modules:
# 	design_v1_i_sfc_logic_s_c1_in_for_body5_s_c1_enter_design_v10
# End time: 11:38:57 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:57 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_mem_lm2_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_mem_lm2_0
# End time: 11:38:57 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:57 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_mem_memdep_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_mem_memdep_0
# End time: 11:38:57 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:57 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pop_i1_memdep_phi_pop9_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pop_i1_memdep_phi_pop9_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pop_i1_memdep_phi_pop9_0
# End time: 11:38:57 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:57 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_memdep_phi_push9_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_i1_memdep_phi_push9_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_i1_memdep_phi_push9_0
# End time: 11:38:57 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:57 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B3_branch.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B3_branch
# 
# Top level modules:
# 	design_v1_B3_branch
# End time: 11:38:57 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:57 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B3_merge.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B3_merge
# 
# Top level modules:
# 	design_v1_B3_merge
# End time: 11:38:57 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:57 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B4.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B4
# 
# Top level modules:
# 	design_v1_bb_B4
# End time: 11:38:57 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:57 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B4_stall_region.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B4_stall_region
# 
# Top level modules:
# 	design_v1_bb_B4_stall_region
# End time: 11:38:57 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:57 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10
# 
# Top level modules:
# 	design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10
# End time: 11:38:58 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:58 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_token_i1_throttle_push_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_token_i1_throttle_push_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_token_i1_throttle_push_0
# End time: 11:38:58 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:58 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_token_i1_throttle_push_1_reg.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_token_i1_throttle_push_1_reg
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_token_i1_throttle_push_1_reg
# End time: 11:38:58 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:58 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B4_branch.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B4_branch
# 
# Top level modules:
# 	design_v1_B4_branch
# End time: 11:38:58 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:58 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B4_merge.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B4_merge
# 
# Top level modules:
# 	design_v1_B4_merge
# End time: 11:38:58 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:58 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B5.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B5
# 
# Top level modules:
# 	design_v1_bb_B5
# End time: 11:38:58 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:58 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B5_stall_region.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B5_stall_region
# 
# Top level modules:
# 	design_v1_bb_B5_stall_region
# End time: 11:38:58 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:58 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B5_merge_reg.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B5_merge_reg
# 
# Top level modules:
# 	design_v1_B5_merge_reg
# End time: 11:38:58 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:58 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_iowr_bl_b_unnamed_10_design_v10
# 
# Top level modules:
# 	design_v1_i_iowr_bl_b_unnamed_10_design_v10
# End time: 11:38:58 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:58 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_sfc_s_c0_in_for_body15_s_c0_enter353_design_v11.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_sfc_s_c0_in_for_body15_s_c0_enter353_design_v11
# 
# Top level modules:
# 	design_v1_i_sfc_s_c0_in_for_body15_s_c0_enter353_design_v11
# End time: 11:38:59 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:59 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000c0_exit41_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000c0_exit41_design_v10
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000c0_exit41_design_v10
# End time: 11:38:59 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:59 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0001gn_v11_full_detector.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0001gn_v11_full_detector
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0001gn_v11_full_detector
# End time: 11:38:59 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:59 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0001design_v11_data_fifo.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0001design_v11_data_fifo
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0001design_v11_data_fifo
# End time: 11:38:59 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:59 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_sfc_logic_s_c0_in_for_body150000_enter353_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_sfc_logic_s_c0_in_for_body150000_enter353_design_v10
# 
# Top level modules:
# 	design_v1_i_sfc_logic_s_c0_in_for_body150000_enter353_design_v10
# End time: 11:38:59 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:59 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_mem_unnamed_9_design_v10
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_mem_unnamed_9_design_v10
# End time: 11:38:59 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:59 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pipeline_keep_going_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pipeline_keep_going_0
# End time: 11:38:59 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:59 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pop_i32_i11_022_pop13_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pop_i32_i11_022_pop13_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pop_i32_i11_022_pop13_0
# End time: 11:38:59 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:59 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pop_i4_cleanups_pop15_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pop_i4_cleanups_pop15_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pop_i4_cleanups_pop15_0
# End time: 11:38:59 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:38:59 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pop_i4_initerations_pop14_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pop_i4_initerations_pop14_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pop_i4_initerations_pop14_0
# End time: 11:39:00 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:00 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pop_i6_fpga_indvars_iv3_pop12_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pop_i6_fpga_indvars_iv3_pop12_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pop_i6_fpga_indvars_iv3_pop12_0
# End time: 11:39:00 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:00 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_lastiniteration_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_i1_lastiniteration_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_i1_lastiniteration_0
# End time: 11:39:00 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:00 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_notexitcond_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_i1_notexitcond_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_i1_notexitcond_0
# End time: 11:39:00 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:00 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i32_i11_022_push13_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_i32_i11_022_push13_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_i32_i11_022_push13_0
# End time: 11:39:00 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:00 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i4_cleanups_push15_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_i4_cleanups_push15_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_i4_cleanups_push15_0
# End time: 11:39:00 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:00 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i4_initerations_push14_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_i4_initerations_push14_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_i4_initerations_push14_0
# End time: 11:39:00 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:00 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i6_fpga_indvars_iv3_push12_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_push_i6_fpga_indvars_iv3_push12_0
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_push_i6_fpga_indvars_iv3_push12_0
# End time: 11:39:00 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:00 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B5_branch.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B5_branch
# 
# Top level modules:
# 	design_v1_B5_branch
# End time: 11:39:01 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:01 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_B5_merge.sv -work design_v1_internal_10 
# -- Compiling module design_v1_B5_merge
# 
# Top level modules:
# 	design_v1_B5_merge
# End time: 11:39:01 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:01 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going12_6_sr.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pipeline_keep_going12_6_sr
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pipeline_keep_going12_6_sr
# End time: 11:39:01 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:01 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going12_6_valid_fifo.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pipeline_keep_going12_6_valid_fifo
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pipeline_keep_going12_6_valid_fifo
# End time: 11:39:01 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:01 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going27_1_sr.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pipeline_keep_going27_1_sr
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pipeline_keep_going27_1_sr
# End time: 11:39:01 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:01 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going27_1_valid_fifo.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pipeline_keep_going27_1_valid_fifo
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pipeline_keep_going27_1_valid_fifo
# End time: 11:39:01 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:01 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going_6_sr.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pipeline_keep_going_6_sr
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pipeline_keep_going_6_sr
# End time: 11:39:01 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:01 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going_6_valid_fifo.sv -work design_v1_internal_10 
# -- Compiling module design_v1_i_llvm_fpga_pipeline_keep_going_6_valid_fifo
# 
# Top level modules:
# 	design_v1_i_llvm_fpga_pipeline_keep_going_6_valid_fifo
# End time: 11:39:01 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:01 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_loop_limiter_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_loop_limiter_0
# 
# Top level modules:
# 	design_v1_loop_limiter_0
# End time: 11:39:01 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:01 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_loop_limiter_1.sv -work design_v1_internal_10 
# -- Compiling module design_v1_loop_limiter_1
# 
# Top level modules:
# 	design_v1_loop_limiter_1
# End time: 11:39:02 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:02 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B2_sr_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B2_sr_0
# 
# Top level modules:
# 	design_v1_bb_B2_sr_0
# End time: 11:39:02 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:02 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B3_sr_1.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B3_sr_1
# 
# Top level modules:
# 	design_v1_bb_B3_sr_1
# End time: 11:39:02 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:02 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B4_sr_0.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B4_sr_0
# 
# Top level modules:
# 	design_v1_bb_B4_sr_0
# End time: 11:39:02 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:02 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_bb_B5_sr_1.sv -work design_v1_internal_10 
# -- Compiling module design_v1_bb_B5_sr_1
# 
# Top level modules:
# 	design_v1_bb_B5_sr_1
# End time: 11:39:02 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:02 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_avm_to_ic.v -work design_v1_internal_10 
# -- Compiling module acl_avm_to_ic
# 
# Top level modules:
# 	acl_avm_to_ic
# End time: 11:39:02 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:02 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_mem1x.v -work design_v1_internal_10 
# -- Compiling module acl_mem1x
# 
# Top level modules:
# 	acl_mem1x
# End time: 11:39:02 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:02 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram.sv -work design_v1_internal_10 
# -- Compiling module hld_ram
# 
# Top level modules:
# 	hld_ram
# End time: 11:39:02 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:02 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_ecc.sv -work design_v1_internal_10 
# -- Compiling module hld_ram_ecc
# -- Importing package acl_ecc_pkg
# -- Compiling module hld_ram_ecc_pulse_stretch_and_sticky
# 
# Top level modules:
# 	hld_ram_ecc
# End time: 11:39:02 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:02 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_tall_depth_stitch.sv -work design_v1_internal_10 
# -- Compiling module hld_ram_tall_depth_stitch
# 
# Top level modules:
# 	hld_ram_tall_depth_stitch
# End time: 11:39:03 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:03 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_remaining_width.sv -work design_v1_internal_10 
# -- Compiling module hld_ram_remaining_width
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_remaining_width.sv(190): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_remaining_width.sv(190): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_remaining_width.sv(191): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_remaining_width.sv(192): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_remaining_width.sv(193): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_remaining_width.sv(194): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# 
# Top level modules:
# 	hld_ram_remaining_width
# End time: 11:39:03 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 6
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:03 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_bits_per_enable.sv -work design_v1_internal_10 
# -- Compiling module hld_ram_bits_per_enable
# 
# Top level modules:
# 	hld_ram_bits_per_enable
# End time: 11:39:03 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:03 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_generic_two_way_depth_stitch.sv -work design_v1_internal_10 
# -- Compiling module hld_ram_generic_two_way_depth_stitch
# 
# Top level modules:
# 	hld_ram_generic_two_way_depth_stitch
# End time: 11:39:03 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:03 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_generic_three_way_depth_stitch.sv -work design_v1_internal_10 
# -- Compiling module hld_ram_generic_three_way_depth_stitch
# 
# Top level modules:
# 	hld_ram_generic_three_way_depth_stitch
# End time: 11:39:03 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:03 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_short_depth_stitch.sv -work design_v1_internal_10 
# -- Compiling module hld_ram_short_depth_stitch
# 
# Top level modules:
# 	hld_ram_short_depth_stitch
# End time: 11:39:03 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:03 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_bottom_width_stitch.sv -work design_v1_internal_10 
# -- Compiling module hld_ram_bottom_width_stitch
# 
# Top level modules:
# 	hld_ram_bottom_width_stitch
# End time: 11:39:03 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:03 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_bottom_depth_stitch.sv -work design_v1_internal_10 
# -- Compiling module hld_ram_bottom_depth_stitch
# 
# Top level modules:
# 	hld_ram_bottom_depth_stitch
# End time: 11:39:03 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:03 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_lower.sv -work design_v1_internal_10 
# -- Compiling module hld_ram_lower
# 
# Top level modules:
# 	hld_ram_lower
# End time: 11:39:03 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:03 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_lower_mlab_simple_dual_port.sv -work design_v1_internal_10 
# -- Compiling module hld_ram_lower_mlab_simple_dual_port
# 
# Top level modules:
# 	hld_ram_lower_mlab_simple_dual_port
# End time: 11:39:04 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:04 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_lower_m20k_simple_dual_port.sv -work design_v1_internal_10 
# -- Compiling module hld_ram_lower_m20k_simple_dual_port
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_lower_m20k_simple_dual_port.sv(205): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_lower_m20k_simple_dual_port.sv(205): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_lower_m20k_simple_dual_port.sv(206): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# 
# Top level modules:
# 	hld_ram_lower_m20k_simple_dual_port
# End time: 11:39:04 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 3
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:04 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_lower_m20k_true_dual_port.sv -work design_v1_internal_10 
# -- Compiling module hld_ram_lower_m20k_true_dual_port
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_lower_m20k_true_dual_port.sv(304): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_lower_m20k_true_dual_port.sv(304): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_lower_m20k_true_dual_port.sv(305): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_ram_lower_m20k_true_dual_port.sv(306): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# 
# Top level modules:
# 	hld_ram_lower_m20k_true_dual_port
# End time: 11:39:04 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 4
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:04 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_local_mem_router.v -work design_v1_internal_10 
# -- Compiling module acl_ic_local_mem_router
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_local_mem_router.v(64): (vlog-13314) Defaulting port 'b_arb_stall' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_local_mem_router.v(66): (vlog-13314) Defaulting port 'b_wrp_ack' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_local_mem_router.v(68): (vlog-13314) Defaulting port 'b_rrp_datavalid' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_local_mem_router.v(69): (vlog-13314) Defaulting port 'b_rrp_data' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# 
# Top level modules:
# 	acl_ic_local_mem_router
# End time: 11:39:04 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 4
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:04 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_host_endpoint.v -work design_v1_internal_10 
# -- Compiling module acl_ic_host_endpoint
# 
# Top level modules:
# 	acl_ic_host_endpoint
# End time: 11:39:04 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:04 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_arb_intf.v -work design_v1_internal_10 
# -- Compiling interface acl_arb_data
# -- Compiling interface acl_arb_intf
# 
# Top level modules:
# 	--none--
# End time: 11:39:04 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:04 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_intf.v -work design_v1_internal_10 
# -- Compiling interface acl_ic_wrp_intf
# -- Compiling interface acl_ic_rrp_intf
# -- Compiling interface acl_ic_host_intf
# 
# Top level modules:
# 	--none--
# End time: 11:39:04 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:04 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_agent_endpoint.v -work design_v1_internal_10 
# -- Compiling module acl_ic_agent_endpoint
# 
# Top level modules:
# 	acl_ic_agent_endpoint
# End time: 11:39:04 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:04 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_agent_rrp.v -work design_v1_internal_10 
# -- Compiling module acl_ic_agent_rrp
# 
# Top level modules:
# 	acl_ic_agent_rrp
# End time: 11:39:04 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:04 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_agent_wrp.v -work design_v1_internal_10 
# -- Compiling module acl_ic_agent_wrp
# 
# Top level modules:
# 	acl_ic_agent_wrp
# End time: 11:39:05 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:05 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_arb2.v -work design_v1_internal_10 
# -- Compiling module acl_arb2
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_arb2.v(114): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_arb2.v(116): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_arb2.v(118): (vlog-2583) [SVCHK] - Extra checking for conflicts with always_comb and always_latch variables is done at vopt time.
# -- Compiling module acl_arb_pipeline_reg
# -- Compiling module acl_arb_staging_reg
# 
# Top level modules:
# 	acl_arb2
# End time: 11:39:05 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 3
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:05 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v -work design_v1_internal_10 
# -- Compiling module design_v1_internal
# -- Compiling module design_v1_internal_ic_7924124493167283643
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(507): (vlog-13314) Defaulting port 'm_arb_request' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(508): (vlog-13314) Defaulting port 'm_arb_enable' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(509): (vlog-13314) Defaulting port 'm_arb_read' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(510): (vlog-13314) Defaulting port 'm_arb_write' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(511): (vlog-13314) Defaulting port 'm_arb_burstcount' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(512): (vlog-13314) Defaulting port 'm_arb_address' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(513): (vlog-13314) Defaulting port 'm_arb_writedata' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(514): (vlog-13314) Defaulting port 'm_arb_byteenable' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# -- Compiling module design_v1_internal_ic_1676122696945765857
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(763): (vlog-13314) Defaulting port 'm_arb_request' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(764): (vlog-13314) Defaulting port 'm_arb_enable' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(765): (vlog-13314) Defaulting port 'm_arb_read' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(766): (vlog-13314) Defaulting port 'm_arb_write' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(767): (vlog-13314) Defaulting port 'm_arb_burstcount' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(768): (vlog-13314) Defaulting port 'm_arb_address' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(769): (vlog-13314) Defaulting port 'm_arb_writedata' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(770): (vlog-13314) Defaulting port 'm_arb_byteenable' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# 
# Top level modules:
# 	design_v1_internal
# End time: 11:39:05 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 16
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:05 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../../components/design_v1/design_v1/sim/design_v1.v -work design_v1 
# -- Compiling module design_v1
# 
# Top level modules:
# 	design_v1
# End time: 11:39:05 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:05 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/main_dpi_controller/hls_sim_main_dpi_controller_10/sim/hls_sim_main_dpi_controller.sv -work hls_sim_main_dpi_controller_10 
# -- Compiling module hls_sim_main_dpi_controller
# 
# Top level modules:
# 	hls_sim_main_dpi_controller
# End time: 11:39:05 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:05 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/main_dpi_controller/sim/main_dpi_controller.v -work main_dpi_controller 
# -- Compiling module main_dpi_controller
# 
# Top level modules:
# 	main_dpi_controller
# End time: 11:39:05 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:05 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/cat_done/avalon_concatenate_singlebit_conduits_10/sim/cat_done_avalon_concatenate_singlebit_conduits_10_bjzeuhq.sv -work avalon_concatenate_singlebit_conduits_10 
# -- Compiling module cat_done_avalon_concatenate_singlebit_conduits_10_bjzeuhq
# 
# Top level modules:
# 	cat_done_avalon_concatenate_singlebit_conduits_10_bjzeuhq
# End time: 11:39:05 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:05 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/cat_done/sim/cat_done.v -work cat_done 
# -- Compiling module cat_done
# 
# Top level modules:
# 	cat_done
# End time: 11:39:05 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:05 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/cat_cwfsw/avalon_concatenate_singlebit_conduits_10/sim/cat_cwfsw_avalon_concatenate_singlebit_conduits_10_bjzeuhq.sv -work avalon_concatenate_singlebit_conduits_10 
# -- Compiling module cat_cwfsw_avalon_concatenate_singlebit_conduits_10_bjzeuhq
# 
# Top level modules:
# 	cat_cwfsw_avalon_concatenate_singlebit_conduits_10_bjzeuhq
# End time: 11:39:05 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:05 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/cat_cwfsw/sim/cat_cwfsw.v -work cat_cwfsw 
# -- Compiling module cat_cwfsw
# 
# Top level modules:
# 	cat_cwfsw
# End time: 11:39:06 on Oct 24,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:06 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/sso_design_v1_A/hls_sim_stream_source_dpi_bfm_10/sim/hls_sim_stream_source_dpi_bfm.sv -work hls_sim_stream_source_dpi_bfm_10 
# -- Compiling module hls_sim_stream_source_dpi_bfm
# 
# Top level modules:
# 	hls_sim_stream_source_dpi_bfm
# End time: 11:39:06 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:06 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../../ip/tb/sso_design_v1_A/sim/sso_design_v1_A.v -work sso_design_v1_A 
# -- Compiling module sso_design_v1_A
# 
# Top level modules:
# 	sso_design_v1_A
# End time: 11:39:06 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:06 on Oct 24,2022
# vlog -sv "+incdir+." "+define+COSIM_LIB" -suppress 14408 ../altera_irq_mapper_1920/sim/tb_altera_irq_mapper_1920_trjgw7i.sv -work altera_irq_mapper_1920 
# -- Compiling module tb_altera_irq_mapper_1920_trjgw7i
# 
# Top level modules:
# 	tb_altera_irq_mapper_1920_trjgw7i
# End time: 11:39:06 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Questa Intel FPGA Edition-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
# Start time: 11:39:06 on Oct 24,2022
# vlog "+incdir+." "+define+COSIM_LIB" -suppress 14408 tb.v -work tb 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 11:39:06 on Oct 24,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# /opt/intelFPGA_pro/21.4/hls/host/linux64/lib/libhls_cosim_msim
# -dpioutoftheblue 1 -sv_lib /opt/intelFPGA_pro/21.4/hls/host/linux64/lib/libhls_cosim_msim -voptargs=+acc
# [exec] elab
# vsim -dpioutoftheblue 1 -sv_lib /opt/intelFPGA_pro/21.4/hls/host/linux64/lib/libhls_cosim_msim -voptargs="+acc" -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L twentynm_ver -L twentynm_hssi_ver -L twentynm_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L twentynm -L twentynm_hssi -L twentynm_hip -L avalon_split_multibit_conduit_10 -L sp_cstart -L hls_sim_stream_sink_dpi_bfm_10 -L ssi_design_v1_B -L avalon_conduit_fanout_10 -L design_v1_ir_cfan -L avalon_concatenate_singlebit_conduits_10 -L design_v1_osacat -L hls_sim_stream_source_dpi_bfm_10 -L sso_design_v1_N -L hls_sim_clock_reset_10 -L clock_reset -L design_v1_cfan -L hls_sim_component_dpi_controller_10 -L dpic_design_v1 -L design_v1_en_cfan -L design_v1_internal_10 -L design_v1 -L hls_sim_main_dpi_controller_10 -L main_dpi_controller -L cat_done -L cat_cwfsw -L sso_design_v1_A -L altera_irq_mapper_1920 -L tb tb.tb 
# Start time: 11:38:37 on Oct 24,2022
# Loading /tmp/jlrainbolt@eshop4_dpi_186110/linux_x86_64_gcc-7.4.0/export_tramp.so
# ** Note: (vsim-3812) Design is being optimized...
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_token_i1_wt_limpush_0.sv(126): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_token_i1_wt_limpush_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_token_i1_wt_limpush_0.sv(126): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2685) [TFMPC] - Too few port connections for 'theiowr'.  Expected 34, found 18.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'o_fifosize'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_fifo_size'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_fifo_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_req'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_idle'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_o_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_i_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_i_valid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared_control'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'o_fifoendofpacket'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'o_fifostartofpacket'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'i_fifochannel_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'o_almost_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_b_unnamed_10_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'o_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2685) [TFMPC] - Too few port connections for 'theiowr'.  Expected 34, found 18.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'o_fifosize'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_fifo_size'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'profile_fifo_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_req'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'profile_idle'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'profile_o_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'profile_i_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'profile_i_valid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared_control'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'o_fifoendofpacket'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'o_fifostartofpacket'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'i_fifochannel_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'o_almost_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10.sv(116): (vopt-2718) [TFMPC] - Missing connection for port 'o_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2685) [TFMPC] - Too few port connections for 'theiord'.  Expected 35, found 17.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'o_fifosize'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_fifo_size'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'profile_fifo_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_req'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'profile_idle'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'profile_o_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'profile_i_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'profile_i_valid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared_control'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'o_fifochannel_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'o_packetempty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'o_endofpacket'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'o_startofpacket'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'o_datavalid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'o_almost_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_call_unnamed_design_v12_design_v10.sv(111): (vopt-2718) [TFMPC] - Missing connection for port 'o_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_notexitcond28_0.sv(107): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_i1_notexitcond28_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_notexitcond28_0.sv(107): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_notexitcond_0.sv(104): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_i1_notexitcond_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_notexitcond_0.sv(104): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_lastiniteration_0.sv(104): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_i1_lastiniteration_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_lastiniteration_0.sv(104): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_memdep_phi_push9_0.sv(104): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_i1_memdep_phi_push9_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_memdep_phi_push9_0.sv(104): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_notexitcond22_0.sv(104): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_i1_notexitcond22_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_notexitcond22_0.sv(104): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_lastiniteration14_0.sv(104): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_i1_lastiniteration14_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i1_lastiniteration14_0.sv(104): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i4_cleanups_push15_0.sv(99): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_i4_cleanups_push15_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i4_cleanups_push15_0.sv(99): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i6_fpga_indvars_iv3_push12_0.sv(99): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_i6_fpga_indvars_iv3_push12_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i6_fpga_indvars_iv3_push12_0.sv(99): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i4_initerations_push14_0.sv(99): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_i4_initerations_push14_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i4_initerations_push14_0.sv(99): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i4_cleanups15_push11_0.sv(99): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_i4_cleanups15_push11_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i4_cleanups15_push11_0.sv(99): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i33_fpga_indvars_iv_push8_0.sv(99): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_i33_fpga_indvars_iv_push8_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i33_fpga_indvars_iv_push8_0.sv(99): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i4_initerations10_push10_0.sv(99): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_i4_initerations10_push10_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i4_initerations10_push10_0.sv(99): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i32_i11_022_push13_0.sv(90): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_i32_i11_022_push13_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_i32_i11_022_push13_0.sv(90): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000design_v11_data_fifo.sv(81): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_sfc_exit_s_c1_out_for_body5_design_v1s_c1_exit_design_v10'.  Expected 12, found 9.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000design_v11_data_fifo.sv(81): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000design_v11_data_fifo.sv(81): (vopt-2718) [TFMPC] - Missing connection for port 'o_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000design_v11_data_fifo.sv(81): (vopt-2718) [TFMPC] - Missing connection for port 'o_almost_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going27_1_valid_fifo.sv(64): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_pipeline_keep_going27_design_v11_valid_fifo'.  Expected 12, found 9.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going27_1_valid_fifo.sv(64): (vopt-2718) [TFMPC] - Missing connection for port 'full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going27_1_valid_fifo.sv(64): (vopt-2718) [TFMPC] - Missing connection for port 'empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going27_1_valid_fifo.sv(64): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going12_6_valid_fifo.sv(64): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_pipeline_keep_going12_design_v16_valid_fifo'.  Expected 12, found 9.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going12_6_valid_fifo.sv(64): (vopt-2718) [TFMPC] - Missing connection for port 'full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going12_6_valid_fifo.sv(64): (vopt-2718) [TFMPC] - Missing connection for port 'empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going12_6_valid_fifo.sv(64): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going_6_valid_fifo.sv(64): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_pipeline_keep_going_design_v16_valid_fifo'.  Expected 12, found 9.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going_6_valid_fifo.sv(64): (vopt-2718) [TFMPC] - Missing connection for port 'full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going_6_valid_fifo.sv(64): (vopt-2718) [TFMPC] - Missing connection for port 'empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going_6_valid_fifo.sv(64): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../ip/tb/dpic_design_v1/sim/dpic_design_v1.v(34): (vopt-2685) [TFMPC] - Too few port connections for 'dpic_design_v1'.  Expected 20, found 18.
# ** Warning: ../../ip/tb/dpic_design_v1/sim/dpic_design_v1.v(34): (vopt-2718) [TFMPC] - Missing connection for port 'agents_done'.
# ** Warning: ../../ip/tb/dpic_design_v1/sim/dpic_design_v1.v(34): (vopt-2718) [TFMPC] - Missing connection for port 'agents_ready'.
# ** Warning: ../../ip/tb/sso_design_v1_A/sim/sso_design_v1_A.v(31): (vopt-2685) [TFMPC] - Too few port connections for 'sso_design_v1_a'.  Expected 11, found 8.
# ** Warning: ../../ip/tb/sso_design_v1_A/sim/sso_design_v1_A.v(31): (vopt-2718) [TFMPC] - Missing connection for port 'source_empty'.
# ** Warning: ../../ip/tb/sso_design_v1_A/sim/sso_design_v1_A.v(31): (vopt-2718) [TFMPC] - Missing connection for port 'source_endofpacket'.
# ** Warning: ../../ip/tb/sso_design_v1_A/sim/sso_design_v1_A.v(31): (vopt-2718) [TFMPC] - Missing connection for port 'source_startofpacket'.
# ** Warning: ../../ip/tb/sso_design_v1_N/sim/sso_design_v1_N.v(31): (vopt-2685) [TFMPC] - Too few port connections for 'sso_design_v1_n'.  Expected 11, found 8.
# ** Warning: ../../ip/tb/sso_design_v1_N/sim/sso_design_v1_N.v(31): (vopt-2718) [TFMPC] - Missing connection for port 'source_empty'.
# ** Warning: ../../ip/tb/sso_design_v1_N/sim/sso_design_v1_N.v(31): (vopt-2718) [TFMPC] - Missing connection for port 'source_endofpacket'.
# ** Warning: ../../ip/tb/sso_design_v1_N/sim/sso_design_v1_N.v(31): (vopt-2718) [TFMPC] - Missing connection for port 'source_startofpacket'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_mem_unnamed_design_v19_design_v11'.  Expected 51, found 34.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'profile_idle'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'profile_avm_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'profile_extra_unaligned_reqs'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'profile_req_cache_hit_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'profile_avm_burstcount_total'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'profile_avm_readwrite_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'profile_o_stall_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'profile_i_stall_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_req'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_ivalid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'profile_bw'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared_control'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'o_active'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'o_almost_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_unnamed_9_design_v10.sv(190): (vopt-2718) [TFMPC] - Missing connection for port 'o_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_local_mem_router.v(64): (vopt-13314) Defaulting port 'b_arb_stall' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_local_mem_router.v(66): (vopt-13314) Defaulting port 'b_wrp_ack' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_local_mem_router.v(68): (vopt-13314) Defaulting port 'b_rrp_datavalid' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_ic_local_mem_router.v(69): (vopt-13314) Defaulting port 'b_rrp_data' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_pipeline.v(181): (vopt-2685) [TFMPC] - Too few port connections for 'asr'.  Expected 8, found 6.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_pipeline.v(181): (vopt-2718) [TFMPC] - Missing connection for port 'o_data'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_pipeline.v(181): (vopt-2718) [TFMPC] - Missing connection for port 'i_data'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_mem_lm2_design_v11'.  Expected 51, found 34.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_idle'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_avm_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_extra_unaligned_reqs'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_req_cache_hit_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_avm_burstcount_total'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_avm_readwrite_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_o_stall_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_i_stall_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_req'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_ivalid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_bw'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared_control'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'o_active'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'o_almost_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_lm2_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'o_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_mem_memdep_design_v11'.  Expected 51, found 34.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_idle'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_avm_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_extra_unaligned_reqs'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_req_cache_hit_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_avm_burstcount_total'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_avm_readwrite_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_o_stall_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_i_stall_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_req'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_ivalid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_bw'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared_control'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'o_active'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'o_almost_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_0.sv(188): (vopt-2718) [TFMPC] - Missing connection for port 'o_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0001design_v11_data_fifo.sv(127): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_sfc_exit_s_c0_out_for_body15_design_v1s_c0_exit41_design_v10'.  Expected 12, found 9.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0001design_v11_data_fifo.sv(127): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0001design_v11_data_fifo.sv(127): (vopt-2718) [TFMPC] - Missing connection for port 'o_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0001design_v11_data_fifo.sv(127): (vopt-2718) [TFMPC] - Missing connection for port 'o_almost_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000design_v11_data_fifo.sv(117): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_sfc_exit_s_c0_out_for_body5_design_v1s_c0_exit32_design_v10'.  Expected 12, found 9.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000design_v11_data_fifo.sv(117): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000design_v11_data_fifo.sv(117): (vopt-2718) [TFMPC] - Missing connection for port 'o_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000design_v11_data_fifo.sv(117): (vopt-2718) [TFMPC] - Missing connection for port 'o_almost_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going_0.sv(124): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_pipeline_keep_going_design_v11'.  Expected 18, found 17.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going_0.sv(124): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going12_0.sv(124): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_pipeline_keep_going12_design_v11'.  Expected 18, found 17.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going12_0.sv(124): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going27_0.sv(124): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_pipeline_keep_going27_design_v11'.  Expected 18, found 17.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_pipeline_keep_going27_0.sv(124): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2685) [TFMPC] - Too few port connections for 'theiord'.  Expected 35, found 17.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'o_fifosize'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_fifo_size'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_fifo_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_req'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_idle'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_o_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_i_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_i_valid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared_control'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'o_fifochannel_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'o_packetempty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'o_endofpacket'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'o_startofpacket'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'o_datavalid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'o_almost_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_iord_bl_a_unnamed_6_design_v10.sv(113): (vopt-2718) [TFMPC] - Missing connection for port 'o_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_token_i1_throttle_push_0.sv(130): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_push_token_i1_throttle_push_design_v11'.  Expected 14, found 13.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_push_token_i1_throttle_push_0.sv(130): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2685) [TFMPC] - Too few port connections for 'fifo'.  Expected 12, found 9.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'almost_full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2685) [TFMPC] - Too few port connections for 'fifo'.  Expected 12, found 9.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'almost_full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2685) [TFMPC] - Too few port connections for 'fifo'.  Expected 12, found 9.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'almost_full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(216): (vopt-2685) [TFMPC] - Too few port connections for 'fifo'.  Expected 9, found 7.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(216): (vopt-2718) [TFMPC] - Missing connection for port 'full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(216): (vopt-2718) [TFMPC] - Missing connection for port 'empty'.
# ** Warning: ../../ip/tb/dpic_design_v1/hls_sim_component_dpi_controller_10/sim/hls_sim_component_dpi_controller.sv(88): (vopt-2685) [TFMPC] - Too few port connections for 'implicit_input_stream'.  Expected 11, found 8.
# ** Warning: ../../ip/tb/dpic_design_v1/hls_sim_component_dpi_controller_10/sim/hls_sim_component_dpi_controller.sv(88): (vopt-2718) [TFMPC] - Missing connection for port 'source_empty'.
# ** Warning: ../../ip/tb/dpic_design_v1/hls_sim_component_dpi_controller_10/sim/hls_sim_component_dpi_controller.sv(88): (vopt-2718) [TFMPC] - Missing connection for port 'source_endofpacket'.
# ** Warning: ../../ip/tb/dpic_design_v1/hls_sim_component_dpi_controller_10/sim/hls_sim_component_dpi_controller.sv(88): (vopt-2718) [TFMPC] - Missing connection for port 'source_startofpacket'.
# ** Warning: ../../ip/tb/dpic_design_v1/hls_sim_component_dpi_controller_10/sim/hls_sim_component_dpi_controller.sv(109): (vopt-2685) [TFMPC] - Too few port connections for 'implicit_output_stream'.  Expected 12, found 8.
# ** Warning: ../../ip/tb/dpic_design_v1/hls_sim_component_dpi_controller_10/sim/hls_sim_component_dpi_controller.sv(109): (vopt-2718) [TFMPC] - Missing connection for port 'stream_active'.
# ** Warning: ../../ip/tb/dpic_design_v1/hls_sim_component_dpi_controller_10/sim/hls_sim_component_dpi_controller.sv(109): (vopt-2718) [TFMPC] - Missing connection for port 'sink_empty'.
# ** Warning: ../../ip/tb/dpic_design_v1/hls_sim_component_dpi_controller_10/sim/hls_sim_component_dpi_controller.sv(109): (vopt-2718) [TFMPC] - Missing connection for port 'sink_endofpacket'.
# ** Warning: ../../ip/tb/dpic_design_v1/hls_sim_component_dpi_controller_10/sim/hls_sim_component_dpi_controller.sv(109): (vopt-2718) [TFMPC] - Missing connection for port 'sink_startofpacket'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2685) [TFMPC] - Too few port connections for 'thei_llvm_fpga_mem_memdep_1_design_v11'.  Expected 51, found 34.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'profile_idle'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'profile_avm_stall'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'profile_extra_unaligned_reqs'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'profile_req_cache_hit_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'profile_avm_burstcount_total'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'profile_avm_readwrite_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'profile_o_stall_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'profile_i_stall_count'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_req'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'profile_total_ivalid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'profile_bw'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'profile_shared_control'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'o_active'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'o_almost_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_i_llvm_fpga_mem_memdep_1_0.sv(230): (vopt-2718) [TFMPC] - Missing connection for port 'o_empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(763): (vopt-13314) Defaulting port 'm_arb_request' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(764): (vopt-13314) Defaulting port 'm_arb_enable' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(765): (vopt-13314) Defaulting port 'm_arb_read' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(766): (vopt-13314) Defaulting port 'm_arb_write' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(767): (vopt-13314) Defaulting port 'm_arb_burstcount' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(768): (vopt-13314) Defaulting port 'm_arb_address' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(769): (vopt-13314) Defaulting port 'm_arb_writedata' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(770): (vopt-13314) Defaulting port 'm_arb_byteenable' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(507): (vopt-13314) Defaulting port 'm_arb_request' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(508): (vopt-13314) Defaulting port 'm_arb_enable' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(509): (vopt-13314) Defaulting port 'm_arb_read' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(510): (vopt-13314) Defaulting port 'm_arb_write' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(511): (vopt-13314) Defaulting port 'm_arb_burstcount' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(512): (vopt-13314) Defaulting port 'm_arb_address' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(513): (vopt-13314) Defaulting port 'm_arb_writedata' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(514): (vopt-13314) Defaulting port 'm_arb_byteenable' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(55): (vopt-2685) [TFMPC] - Too few port connections for 'design_v1_internal'.  Expected 69, found 57.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(55): (vopt-2718) [TFMPC] - Missing connection for port 'avst_iowr_bl_return_design_v1_valid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(55): (vopt-2718) [TFMPC] - Missing connection for port 'avst_iowr_bl_return_design_v1_data'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(55): (vopt-2718) [TFMPC] - Missing connection for port 'avst_iord_bl_call_design_v1_ready'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(55): (vopt-2718) [TFMPC] - Missing connection for port 'avst_iord_bl_call_design_v1_almost_full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(55): (vopt-2718) [TFMPC] - Missing connection for port 'avst_iord_bl_A_almost_full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(55): (vopt-2718) [TFMPC] - Missing connection for port 'valid_in'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(55): (vopt-2718) [TFMPC] - Missing connection for port 'stall_in'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(55): (vopt-2718) [TFMPC] - Missing connection for port 'avst_iowr_bl_return_design_v1_ready'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(55): (vopt-2718) [TFMPC] - Missing connection for port 'avst_iowr_bl_return_design_v1_almostfull'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(55): (vopt-2718) [TFMPC] - Missing connection for port 'avst_iowr_bl_B_almostfull'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(55): (vopt-2718) [TFMPC] - Missing connection for port 'avst_iord_bl_call_design_v1_valid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(55): (vopt-2718) [TFMPC] - Missing connection for port 'avst_iord_bl_call_design_v1_data'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(150): (vopt-2685) [TFMPC] - Too few port connections for 'avm_to_ic'.  Expected 24, found 23.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(150): (vopt-2718) [TFMPC] - Missing connection for port 'ic_arb_id'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(150): (vopt-2685) [TFMPC] - Too few port connections for 'avm_to_ic'.  Expected 24, found 23.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(150): (vopt-2718) [TFMPC] - Missing connection for port 'ic_arb_id'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(150): (vopt-2685) [TFMPC] - Too few port connections for 'avm_to_ic'.  Expected 24, found 23.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(150): (vopt-2718) [TFMPC] - Missing connection for port 'ic_arb_id'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(150): (vopt-2685) [TFMPC] - Too few port connections for 'avm_to_ic'.  Expected 24, found 23.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(150): (vopt-2718) [TFMPC] - Missing connection for port 'ic_arb_id'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(209): (vopt-2685) [TFMPC] - Too few port connections for 'mem0'.  Expected 21, found 20.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v(209): (vopt-2718) [TFMPC] - Missing connection for port 'ecc_err_status'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_pipelined.v(910): (vopt-2697) MSB 1183 of part-select into 'core_data_in' is out of bounds.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_pipelined.v(910): (vopt-2697) LSB 1056 of part-select into 'core_data_in' is out of bounds.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_pipelined.v(910): (vopt-2697) MSB 67 of part-select into 'core_data_in' is out of bounds.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/lsu_pipelined.v(910): (vopt-2697) LSB 64 of part-select into 'core_data_in' is out of bounds.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function.sv(583): (vopt-2685) [TFMPC] - Too few port connections for 'thedesign_v1_B1_start_x'.  Expected 14, found 11.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function.sv(583): (vopt-2718) [TFMPC] - Missing connection for port 'o_profile_valid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function.sv(583): (vopt-2718) [TFMPC] - Missing connection for port 'o_shift_data'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function.sv(583): (vopt-2718) [TFMPC] - Missing connection for port 'i_shift_data'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function.sv(618): (vopt-2685) [TFMPC] - Too few port connections for 'thedesign_v1_B3_x'.  Expected 14, found 11.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function.sv(618): (vopt-2718) [TFMPC] - Missing connection for port 'o_profile_valid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function.sv(618): (vopt-2718) [TFMPC] - Missing connection for port 'o_shift_data'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function.sv(618): (vopt-2718) [TFMPC] - Missing connection for port 'i_shift_data'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function.sv(653): (vopt-2685) [TFMPC] - Too few port connections for 'thedesign_v1_B5_x'.  Expected 14, found 11.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function.sv(653): (vopt-2718) [TFMPC] - Missing connection for port 'o_profile_valid'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function.sv(653): (vopt-2718) [TFMPC] - Missing connection for port 'o_shift_data'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_function.sv(653): (vopt-2718) [TFMPC] - Missing connection for port 'i_shift_data'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2685) [TFMPC] - Too few port connections for 'fifo'.  Expected 12, found 9.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'almost_full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2685) [TFMPC] - Too few port connections for 'fifo'.  Expected 12, found 9.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'almost_full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2685) [TFMPC] - Too few port connections for 'fifo'.  Expected 12, found 9.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'almost_full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'empty'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2685) [TFMPC] - Too few port connections for 'fifo'.  Expected 12, found 9.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'almost_full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'full'.
# ** Warning: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_push.v(278): (vopt-2718) [TFMPC] - Missing connection for port 'empty'.
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=317.
# //  Questa Intel FPGA Edition-64
# //  Version 2021.3 linux_x86_64 Jul 13 2021
# //
# //  Copyright 1991-2021 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading work.tb(fast)
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# Loading design_v1_internal_10.design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0001gn_v11_full_detector(fast)
# Loading design_v1_internal_10.acl_full_detector(fast)
# Loading design_v1_internal_10.acl_reset_handler(fast__4)
# Loading design_v1_internal_10.design_v1_i_sfc_logic_s_c0_in_for_body150000_enter353_design_v10(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_i4_cleanups_push15_0(fast)
# Loading design_v1_internal_10.acl_push(fast)
# Loading design_v1_internal_10.acl_data_fifo(fast__1)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pop_i4_cleanups_pop15_0(fast)
# Loading design_v1_internal_10.acl_pop(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_i6_fpga_indvars_iv3_push12_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pop_i6_fpga_indvars_iv3_pop12_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_i1_notexitcond_0(fast)
# Loading design_v1_internal_10.acl_push(fast__1)
# Loading design_v1_internal_10.acl_data_fifo(fast__2)
# Loading design_v1_internal_10.acl_ll_fifo(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_i4_initerations_push14_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pop_i4_initerations_pop14_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_i1_lastiniteration_0(fast)
# Loading design_v1_internal_10.acl_push(fast__2)
# Loading design_v1_internal_10.acl_staging_reg(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pipeline_keep_going_0(fast)
# Loading design_v1_internal_10.acl_dspba_buffer(fast)
# Loading design_v1_internal_10.acl_pipeline(fast)
# Loading design_v1_internal_10.acl_pop(fast__1)
# Loading design_v1_internal_10.acl_push(fast__3)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_i32_i11_022_push13_0(fast)
# Loading design_v1_internal_10.acl_push(fast__4)
# Loading design_v1_internal_10.acl_data_fifo(fast__3)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pop_i32_i11_022_pop13_0(fast)
# Loading design_v1_internal_10.acl_pop(fast__2)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_mem_unnamed_9_design_v10(fast)
# Loading design_v1_internal_10.lsu_top(fast)
# Loading design_v1_internal_10.lsu_pipelined_read(fast)
# Loading design_v1_internal_10.hld_fifo(fast__1)
# Loading design_v1_internal_10.acl_low_latency_fifo(fast)
# Loading design_v1_internal_10.acl_reset_handler(fast__6)
# Loading design_v1_internal_10.acl_reset_handler(fast__5)
# Loading design_v1_internal_10.lsu_permute_address(fast)
# Loading design_v1_internal_10.dspba_delay_ver(fast)
# Loading design_v1_internal_10.design_v1_bb_B5_sr_1(fast)
# Loading design_v1_internal_10.design_v1_loop_limiter_1(fast)
# Loading design_v1_internal_10.acl_loop_limiter(fast)
# Loading design_v1_internal_10.acl_reset_handler(fast__7)
# Loading design_v1_internal_10.design_v1_bb_B2(fast)
# Loading design_v1_internal_10.design_v1_B2_branch(fast)
# Loading design_v1_internal_10.design_v1_bb_B2_stall_region(fast)
# Loading design_v1_internal_10.design_v1_B2_merge(fast)
# Loading design_v1_internal_10.design_v1_bb_B2_sr_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pipeline_keep_going12_6_sr(fast)
# Loading design_v1_internal_10.design_v1_bb_B3(fast)
# Loading design_v1_internal_10.design_v1_B3_branch(fast)
# Loading design_v1_internal_10.design_v1_B3_merge(fast)
# Loading design_v1_internal_10.design_v1_bb_B3_stall_region(fast)
# Loading design_v1_internal_10.design_v1_B3_merge_reg(fast)
# Loading design_v1_internal_10.design_v1_i_iord_bl_a_unnamed_6_design_v10(fast)
# Loading design_v1_internal_10.hld_iord(fast)
# Loading design_v1_internal_10.hld_memory_depth_quantization_pkg(fast)
# Loading design_v1_internal_10.hld_iord_stall_valid(fast)
# Loading design_v1_internal_10.design_v1_i_sfc_s_c1_in_for_body5_s_c1_enter_design_v15(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000s_c1_exit_design_v10(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000design_v11_data_fifo(fast)
# Loading design_v1_internal_10.hld_fifo(fast__2)
# Loading design_v1_internal_10.acl_mid_speed_fifo(fast__1)
# Loading altera_mf_ver.altdpram(fast__1)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_sfc_exit_s_c1_out_0000gn_v11_full_detector(fast)
# Loading design_v1_internal_10.acl_full_detector(fast__1)
# Loading design_v1_internal_10.design_v1_i_sfc_logic_s_c1_in_for_body5_s_c1_enter_design_v10(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_mem_memdep_0(fast)
# Loading design_v1_internal_10.lsu_top(fast__1)
# Loading design_v1_internal_10.lsu_pipelined_write(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_i1_memdep_phi_push9_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pop_i1_memdep_phi_pop9_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_mem_lm2_0(fast)
# Loading design_v1_internal_10.design_v1_i_sfc_s_c0_in_for_body5_s_c0_enter302_design_v11(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000c0_exit32_design_v10(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000design_v11_data_fifo(fast)
# Loading design_v1_internal_10.hld_fifo(fast__3)
# Loading design_v1_internal_10.acl_mid_speed_fifo(fast__2)
# Loading altera_mf_ver.altdpram(fast__2)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000gn_v11_full_detector(fast)
# Loading design_v1_internal_10.design_v1_i_sfc_logic_s_c0_in_for_body5_s_c0_enter302_design_v10(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_i4_cleanups15_push11_0(fast)
# Loading design_v1_internal_10.acl_push(fast__5)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pop_i4_cleanups15_pop11_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_ffwd_dest_i33_unnamed_5_design_v10(fast)
# Loading design_v1_internal_10.acl_ffwddst(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_i33_fpga_indvars_iv_push8_0(fast)
# Loading design_v1_internal_10.acl_push(fast__6)
# Loading design_v1_internal_10.acl_data_fifo(fast__4)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pop_i33_fpga_indvars_iv_pop8_0(fast)
# Loading design_v1_internal_10.acl_pop(fast__3)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_ffwd_dest_i1_cmp3236_0(fast)
# Loading design_v1_internal_10.acl_ffwddst(fast__1)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_i1_notexitcond22_0(fast)
# Loading design_v1_internal_10.acl_push(fast__7)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_i4_initerations10_push10_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pop_i4_initerations10_pop10_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_i1_lastiniteration14_0(fast)
# Loading design_v1_internal_10.acl_push(fast__8)
# Loading design_v1_internal_10.acl_data_fifo(fast__5)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pipeline_keep_going12_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_ffwd_dest_i1_cmp3237_0(fast)
# Loading design_v1_internal_10.design_v1_bb_B3_sr_1(fast)
# Loading design_v1_internal_10.design_v1_loop_limiter_0(fast)
# Loading design_v1_internal_10.acl_loop_limiter(fast__1)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pipeline_keep_going27_1_sr(fast)
# Loading design_v1_internal_10.design_v1_bb_B1_start(fast)
# Loading design_v1_internal_10.design_v1_B1_start_merge(fast)
# Loading design_v1_internal_10.design_v1_B1_start_branch(fast)
# Loading design_v1_internal_10.design_v1_bb_B1_start_stall_region(fast)
# Loading design_v1_internal_10.design_v1_B1_start_merge_reg(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_ffwd_source_i1_unnamed_3_design_v10(fast)
# Loading design_v1_internal_10.acl_ffwdsrc(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_ffwd_source_i33_unnamed_4_design_v10(fast)
# Loading design_v1_internal_10.acl_ffwdsrc(fast__1)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_mem_memdep_1_0(fast)
# Loading design_v1_internal_10.lsu_top(fast__2)
# Loading design_v1_internal_10.lsu_pipelined_write(fast__1)
# Loading design_v1_internal_10.hld_fifo(fast__4)
# Loading design_v1_internal_10.acl_low_latency_fifo(fast__1)
# Loading design_v1_internal_10.design_v1_i_iord_bl_call_unnamed_design_v12_design_v10(fast)
# Loading design_v1_internal_10.hld_iord(fast__1)
# Loading design_v1_internal_10.hld_iord_stall_valid(fast__1)
# Loading design_v1_internal_10.acl_staging_reg(fast__1)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pop_throttle_i1_throttle_pop_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pop_throttle_i1_throttle_pop_1_reg(fast)
# Loading design_v1_internal_10.design_v1_i_sfc_s_c0_in_wt_entry_s_c0_enter1_design_v10(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_sfc_exit_s_c0_out_0000s_c0_exit_design_v10(fast)
# Loading design_v1_internal_10.acl_enable_sink(fast)
# Loading design_v1_internal_10.design_v1_i_sfc_logic_s_c0_in_wt_entry_s_c0_enter1_design_v10(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_i1_notexitcond28_0(fast)
# Loading design_v1_internal_10.acl_push(fast__9)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pipeline_keep_going27_0(fast)
# Loading design_v1_internal_10.acl_pipeline(fast__1)
# Loading design_v1_internal_10.acl_staging_reg(fast__2)
# Loading design_v1_internal_10.design_v1_bb_B4(fast)
# Loading design_v1_internal_10.design_v1_B4_merge(fast)
# Loading design_v1_internal_10.design_v1_B4_branch(fast)
# Loading design_v1_internal_10.design_v1_bb_B4_stall_region(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_token_i1_throttle_push_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_token_i1_throttle_push_1_reg(fast)
# Loading design_v1_internal_10.acl_push(fast__10)
# Loading design_v1_internal_10.acl_token_fifo_counter(fast)
# Loading design_v1_internal_10.design_v1_i_iowr_bl_return_unnamed_design_v18_design_v10(fast)
# Loading design_v1_internal_10.hld_iowr(fast__1)
# Loading design_v1_internal_10.hld_iowr_stall_valid(fast__1)
# Loading design_v1_internal_10.hld_loop_profiler(fast)
# Loading design_v1_internal_10.hld_sim_latency_tracker(fast)
# Loading design_v1_internal_10.hld_loop_profiler(fast__1)
# Loading design_v1_internal_10.hld_sim_latency_tracker(fast__1)
# Loading design_v1_internal_10.hld_loop_profiler(fast__2)
# Loading design_v1_internal_10.hld_sim_latency_tracker(fast__2)
# Loading design_v1_internal_10.design_v1_bb_B0_runOnce(fast)
# Loading design_v1_internal_10.design_v1_B0_runOnce_branch(fast)
# Loading design_v1_internal_10.design_v1_bb_B0_runOnce_stall_region(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_token_i1_wt_limpush_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_push_token_i1_wt_limpush_1_reg(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pop_token_i1_wt_limpop_0(fast)
# Loading design_v1_internal_10.design_v1_i_llvm_fpga_pop_token_i1_wt_limpop_0_reg(fast)
# Loading design_v1_internal_10.design_v1_B0_runOnce_merge_reg(fast)
# Loading design_v1_internal_10.design_v1_B0_runOnce_merge(fast)
# Loading design_v1_internal_10.acl_reset_wire(fast)
# Loading design_v1_internal_10.acl_avm_to_ic(fast)
# Loading design_v1_internal_10.acl_mem1x(fast)
# Loading design_v1_internal_10.acl_reset_handler(fast__8)
# Loading design_v1_internal_10.hld_ram(fast)
# Loading design_v1_internal_10.acl_ecc_pkg(fast)
# Loading design_v1_internal_10.hld_ram_ecc(fast)
# Loading design_v1_internal_10.hld_ram_tall_depth_stitch(fast)
# Loading design_v1_internal_10.hld_ram_generic_three_way_depth_stitch(fast)
# Loading design_v1_internal_10.hld_ram_generic_two_way_depth_stitch(fast)
# Loading design_v1_internal_10.hld_ram_remaining_width(fast)
# Loading design_v1_internal_10.hld_ram_bits_per_enable(fast)
# Loading design_v1_internal_10.hld_ram_lower(fast)
# Loading design_v1_internal_10.hld_ram_lower_mlab_simple_dual_port(fast)
# Loading altera_mf_ver.altdpram(fast__3)
# Loading design_v1_internal_10.acl_ic_local_mem_router(fast)
# Loading design_v1_internal_10.design_v1_internal_ic_7924124493167283643(fast)
# Loading design_v1_internal_10.acl_ic_host_intf(fast__1)
# Loading design_v1_internal_10.acl_arb_intf(fast__1)
# Loading design_v1_internal_10.acl_ic_wrp_intf(fast__1)
# Loading design_v1_internal_10.acl_ic_rrp_intf(fast__1)
# Loading design_v1_internal_10.acl_ic_host_endpoint(fast)
# Loading design_v1_internal_10.acl_ic_host_endpoint(fast__1)
# Loading design_v1_internal_10.acl_ic_agent_endpoint(fast)
# Loading design_v1_internal_10.acl_ic_agent_wrp(fast)
# Loading design_v1_internal_10.acl_ic_agent_rrp(fast)
# Loading design_v1_internal_10.acl_arb2(fast)
# Loading design_v1_internal_10.design_v1_internal_ic_1676122696945765857(fast)
# Loading design_v1_internal_10.acl_ic_wrp_intf(fast__2)
# Loading design_v1_internal_10.acl_ic_rrp_intf(fast__2)
# Loading design_v1_internal_10.acl_ic_host_endpoint(fast__2)
# Loading design_v1_internal_10.acl_ic_host_endpoint(fast__3)
# Loading design_v1_internal_10.acl_ic_agent_endpoint(fast__1)
# Loading design_v1_internal_10.acl_ic_agent_wrp(fast__1)
# Loading design_v1_internal_10.acl_ic_agent_rrp(fast__1)
# Loading main_dpi_controller.main_dpi_controller(fast)
# Loading hls_sim_main_dpi_controller_10.hls_sim_main_dpi_controller(fast)
# Loading sp_cstart.sp_cstart(fast)
# Loading avalon_split_multibit_conduit_10.sp_cstart_avalon_split_multibit_conduit_10_dlmo3na(fast)
# Loading ssi_design_v1_B.ssi_design_v1_B(fast)
# Loading hls_sim_stream_sink_dpi_bfm_10.hls_sim_stream_sink_dpi_bfm(fast)
# Loading sso_design_v1_A.sso_design_v1_A(fast)
# Loading hls_sim_stream_source_dpi_bfm_10.hls_sim_stream_source_dpi_bfm(fast)
# Loading sso_design_v1_N.sso_design_v1_N(fast)
# Loading hls_sim_stream_source_dpi_bfm_10.hls_sim_stream_source_dpi_bfm(fast__1)
# Loading altera_irq_mapper_1920.tb_altera_irq_mapper_1920_trjgw7i(fast)
# ** Warning: (vsim-3015) [PCDPC] - Port size (66) does not match connection size (67) for port 'i_data'. The port definition is at: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iowr_stall_valid.sv(97).
#    Time: 0 ps  Iteration: 0  Instance: /tb/design_v1_inst/design_v1_internal_inst/design_v1_internal/thedesign_v1_function/thebb_design_v1_B5/thebb_design_v1_B5_stall_region/thei_iowr_bl_b_unnamed_design_v110_design_v13_aunroll_x/theiowr/GEN_STALL_VALID/hld_iowr_stall_valid_inst File: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iowr.sv Line: 410
# ** Warning: (vsim-3015) [PCDPC] - Port size (66) does not match connection size (67) for port 'o_fifodata'. The port definition is at: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iowr_stall_valid.sv(107).
#    Time: 0 ps  Iteration: 0  Instance: /tb/design_v1_inst/design_v1_internal_inst/design_v1_internal/thedesign_v1_function/thebb_design_v1_B5/thebb_design_v1_B5_stall_region/thei_iowr_bl_b_unnamed_design_v110_design_v13_aunroll_x/theiowr/GEN_STALL_VALID/hld_iowr_stall_valid_inst File: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iowr.sv Line: 410
# ** Warning: (vsim-3015) [PCDPC] - Port size (66) does not match connection size (67) for port 'o_data'. The port definition is at: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iord_stall_valid.sv(74).
#    Time: 0 ps  Iteration: 0  Instance: /tb/design_v1_inst/design_v1_internal_inst/design_v1_internal/thedesign_v1_function/thebb_design_v1_B3/thebb_design_v1_B3_stall_region/thei_iord_bl_a_unnamed_design_v16_design_v13_aunroll_x/theiord/GEN_STALL_VALID/hld_iord_stall_valid_inst File: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iord.sv Line: 427
# ** Warning: (vsim-3015) [PCDPC] - Port size (66) does not match connection size (67) for port 'i_fifodata'. The port definition is at: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iord_stall_valid.sv(79).
#    Time: 0 ps  Iteration: 0  Instance: /tb/design_v1_inst/design_v1_internal_inst/design_v1_internal/thedesign_v1_function/thebb_design_v1_B3/thebb_design_v1_B3_stall_region/thei_iord_bl_a_unnamed_design_v16_design_v13_aunroll_x/theiord/GEN_STALL_VALID/hld_iord_stall_valid_inst File: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iord.sv Line: 427
# ** Warning: (vsim-3015) [PCDPC] - Port size (34) does not match connection size (35) for port 'o_data'. The port definition is at: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iord_stall_valid.sv(74).
#    Time: 0 ps  Iteration: 0  Instance: /tb/design_v1_inst/design_v1_internal_inst/design_v1_internal/thedesign_v1_function/thebb_design_v1_B1_start/thebb_design_v1_B1_start_stall_region/thei_iord_bl_call_design_v1_unnamed_design_v12_design_v12_aunroll_x/theiord/GEN_STALL_VALID/hld_iord_stall_valid_inst File: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iord.sv Line: 427
# ** Warning: (vsim-3015) [PCDPC] - Port size (34) does not match connection size (35) for port 'i_fifodata'. The port definition is at: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iord_stall_valid.sv(79).
#    Time: 0 ps  Iteration: 0  Instance: /tb/design_v1_inst/design_v1_internal_inst/design_v1_internal/thedesign_v1_function/thebb_design_v1_B1_start/thebb_design_v1_B1_start_stall_region/thei_iord_bl_call_design_v1_unnamed_design_v12_design_v12_aunroll_x/theiord/GEN_STALL_VALID/hld_iord_stall_valid_inst File: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iord.sv Line: 427
# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (4) for port 'i_data'. The port definition is at: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iowr_stall_valid.sv(97).
#    Time: 0 ps  Iteration: 0  Instance: /tb/design_v1_inst/design_v1_internal_inst/design_v1_internal/thedesign_v1_function/thebb_design_v1_B4/thebb_design_v1_B4_stall_region/thei_iowr_bl_return_design_v1_unnamed_design_v18_design_v10/theiowr/GEN_STALL_VALID/hld_iowr_stall_valid_inst File: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iowr.sv Line: 410
# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (4) for port 'o_fifodata'. The port definition is at: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iowr_stall_valid.sv(107).
#    Time: 0 ps  Iteration: 0  Instance: /tb/design_v1_inst/design_v1_internal_inst/design_v1_internal/thedesign_v1_function/thebb_design_v1_B4/thebb_design_v1_B4_stall_region/thei_iowr_bl_return_design_v1_unnamed_design_v18_design_v10/theiowr/GEN_STALL_VALID/hld_iowr_stall_valid_inst File: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/hld_iowr.sv Line: 410
# ** Warning: (vsim-3015) [PCDPC] - Port size (25) does not match connection size (1) for port 'ic_arb_address'. The port definition is at: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_avm_to_ic.v(49).
#    Time: 0 ps  Iteration: 0  Instance: /tb/design_v1_inst/design_v1_internal_inst/local_mem_system_aspace64/local_mem_group[0]/host[0]/avm_to_ic File: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v Line: 150
# ** Warning: (vsim-3015) [PCDPC] - Port size (25) does not match connection size (1) for port 'ic_arb_address'. The port definition is at: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_avm_to_ic.v(49).
#    Time: 0 ps  Iteration: 0  Instance: /tb/design_v1_inst/design_v1_internal_inst/local_mem_system_aspace64/local_mem_group[0]/host[1]/avm_to_ic File: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v Line: 150
# ** Warning: (vsim-3015) [PCDPC] - Port size (25) does not match connection size (1) for port 'ic_arb_address'. The port definition is at: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_avm_to_ic.v(49).
#    Time: 0 ps  Iteration: 0  Instance: /tb/design_v1_inst/design_v1_internal_inst/local_mem_system_aspace64/local_mem_group[0]/host[2]/avm_to_ic File: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v Line: 150
# ** Warning: (vsim-3015) [PCDPC] - Port size (25) does not match connection size (1) for port 'ic_arb_address'. The port definition is at: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/acl_avm_to_ic.v(49).
#    Time: 0 ps  Iteration: 0  Instance: /tb/design_v1_inst/design_v1_internal_inst/local_mem_system_aspace64/local_mem_group[0]/host[3]/avm_to_ic File: ../../../components/design_v1/design_v1/design_v1_internal_10/sim/design_v1_internal.v Line: 150
# Compiling /tmp/jlrainbolt@eshop4_dpi_186110/linux_x86_64_gcc-7.4.0/exportwrapper.c
# Loading /tmp/jlrainbolt@eshop4_dpi_186110/linux_x86_64_gcc-7.4.0/vsim_auto_compile.so
# Loading /opt/intelFPGA_pro/21.4/hls/host/linux64/lib/libhls_cosim_msim.so
# End time: 11:39:07 on Oct 24,2022, Elapsed time: 0:00:30
# Errors: 0, Warnings: 329
Info: *******************************************************************
Info: Running Quartus Prime Shell
    Info: Version 21.4.0 Build 67 12/06/2021 SC Pro Edition
    Info: Copyright (C) 2021  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and any partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details, at
    Info: https://fpgasoftware.intel.com/eula.
    Info: Processing started: Mon Oct 24 11:39:08 2022
    Info: System process ID: 191823
Info: Command: quartus_sh --flow compile quartus_compile
Info: Quartus(args): compile quartus_compile
Info: Using INI file /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/quartus/quartus.ini
Info: Project Name = /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/quartus/quartus_compile
Info: Revision Name = quartus_compile
Warning (125060): Assignment "PARTITION_NETLIST_TYPE" is no longer supported. The assignment in the Intel Quartus Prime Settings file (.qsf) will be ignored
Warning (125060): Assignment "PARTITION_FITTER_PRESERVATION_LEVEL" is no longer supported. The assignment in the Intel Quartus Prime Settings file (.qsf) will be ignored
Info: Run task: IP Generation
Info: *******************************************************************
Info: Running Quartus Prime IP Generation Tool
    Info: Version 21.4.0 Build 67 12/06/2021 SC Pro Edition
    Info: Processing started: Mon Oct 24 11:39:11 2022
    Info: System process ID: 191848
Info: Command: quartus_ipgenerate quartus_compile -c quartus_compile --run_default_mode_op
Info: Using INI file /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/quartus/quartus.ini
Info: Found 1 IP file(s) in the project.
    Info: IP file /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1.ip was found in the project.
Info: Finished generating IP file(s) in the project.
    Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1).
    Info: Skipped generation of synthesis files for the Platform Designer IP file /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
    Info: Skipped generation of simulation files for the Platform Designer IP file /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/components/design_v1/design_v1.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
Info: Quartus Prime IP Generation Tool was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 1195 megabytes
    Info: Processing ended: Mon Oct 24 11:39:11 2022
    Info: Elapsed time: 00:00:00
    Info: System process ID: 191848
Info: Run task: Analysis & Synthesis
Error: Flow compile (for project /home/jlrainbolt/tutorials/best_practices/optimize_ii_using_hls_register/part_1_implemented_using_memory_module.prj/quartus/quartus_compile) was not successful
Error: run_flow flow:run1 finished: 0 Internal Error
Error (23031): Evaluation of Tcl script /opt/intelFPGA_pro/21.4/quartus/common/tcl/internal/qsh_flowengine.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 3 errors, 2 warnings
    Error: Peak virtual memory: 1195 megabytes
    Error: Processing ended: Mon Oct 24 11:39:19 2022
    Error: Elapsed time: 00:00:11
    Error: System process ID: 191823