Why there is no video output seen after programming the SDI II IP multi-rate or triple-rate design with the Agilex™ 7 FPGA device using the Quartus® Prime Pro Edition Software Programmer v22.2?

Description

Due to a problem in the Quartus® Prime Pro Edition Software Programmer version 22.2, no SDI II video output is displayed on the receiver side when using the SDI II IP multi-rate or triple-rate designs on Agilex™ 7 FPGA devices. This is due to the rx_ready signal not being asserted after performing dynamic reconfiguration of the F-Tile PHY transceiver. This issue impacts all SDI II IP design examples that support dynamic reconfiguration.   

Resolution

A patch is available to fix this problem for the Quartus® Prime Pro Edition Software Programmer version 22.2. 

Download and install Patch 0.06 below.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.

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Why there is no video output seen after programming the SDI II IP multi-rate or triple-rate design with the Agilex™ 7 FPGA F-tile device using the Quartus® Prime Pro Edition Programmer v22.1?

Why does the SDI II IP Multi-rate (up to 12G-SDI) design fail to work when merging both TX and RX simplex mode in the same channel with the Agilex™ 7 FPGA F-Tile device?