Why must Extended Display Identification Data (EDID) be provided to generate the F-Tile HDMI IP Design Example for RX-Only design in the Quartus® Prime Pro Edition Software version 24.2 on Agilex™ 7 FPGA?

Description

Due to the limitation of the F-Tile HDMI IP Design Example for RX-Only design generation, you must provide Extended Display Identification Data (EDID) file in .hex or .mif format prior to generation of the design example.

Resolution

When generating RX-Only design if you do not have the EDID content, the generation error message shown below can be avoided by creating an empty .hex file under your current working directory and insert the file name for this parameter.

Please specify a valid initial EDID content in .hex/.mif file format to the RAM file path option.

When the EDID content ready, open the F-Tile HDMI IP (Project Navigator > IP components > nios_hdmi_rx) and regenerate the F-Tile HDMI IP with the valid EDID content.
 
This problem is scheduled to be fixed in the future release of the Quartus® Prime Pro Edition Software.